IDTCSPT857DNLGI [IDT]
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQCC40, PLASTIC, VFQFN-40;
| 型号： | IDTCSPT857DNLGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQCC40, PLASTIC, VFQFN-40 驱动 逻辑集成电路 |
| 文件： | 总15页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V - 2.6V PHASE LOCKED
LOOP DIFFERENTIAL 1:10
SDRAM CLOCK DRIVER
IDTCSPT857D
ADVANCE
INFORMATION
FEATURES:
DESCRIPTION:
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications requiring improved output crosspoint
voltage
TheCSPT857DisaPLLbasedclockdriverthatactsasazerodelaybuffer
todistributeonedifferentialclockinputpair(CLK,CLK)to10differentialoutput
pairs(Y[0:9],Y[0:9])andonedifferentialpairoffeedbackclockoutput(FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the input frequency falls below
approximately20MHz,thedevicewillenterpowerdownmode. Inthismode,
thereceiversaredisabled,thePLListurnedoff,andtheoutputclockdrivers
aretristated,resultinginacurrentconsumptionoflessthan200µA.
TheCSPT857Drequiresnoexternalcomponentsandhasbeenoptimised
forverylowI/Ophaseerror,skew,andjitter,whilemaintainingfrequencyand
duty cycleovertheoperatingvoltageandtemperaturerange.TheCSPT857D,
designedforuseinbothmoduleassembliesandsystemmotherboardbased
solutions,providesanoptimumhigh-performanceclocksource.
• Operating frequency: 60MHz to 220MHz
• Very low skew:
– <100ps for PC1600 - PC2700
– <75ps for PC3200
• Very low jitter:
– <75ps for PC1600 - PC2700
– <50ps for PC3200
• 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700
• 2.6V AVDD and 2.6V VDDQ for PC3200
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-
pin VFBGA packages
The CSPT857D is available in Commercial Temperature Range (0°C to
+70°C)andIndustrialTemperatureRange(-40°Cto+85°C). SeeOrdering
Informationfordetails.
APPLICATIONS:
• Meets or exceeds JEDEC standard JESD 82-1A for registered
DDR clock driver
• Meets proposed DDR1-400 specification
• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),
PC2700 (DDR333), PC3200 (DDR400)
• Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859,
SSTVF16859, SSTVN16859, DDR1 register, provides complete
solution for DDR1 DIMMs
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OCTOBER 2003
1
c
2003 Integrated Device Technology, Inc.
DSC-6835/2
IDTCSPT857D
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
FUNCTIONALBLOCKDIAGRAM
PWRDWN
TEST
MODE
LOGIC
Y0
AVDD
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
CLK
CLK
Y5
Y6
PLL
FBIN
FBIN
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
2
IDTCSPT857D
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
PINCONFIGURATIONS
PWR
DWN
6
5
4
Y8
Y8
Y5
Y5
Y6
Y6
GND
GND
Y7
Y7
FBIN VDDQ FBOUT
FBIN FBOUT GND
Y9
Y9
VDDQ
NC
NC
NC
NC
GND VDDQ NC
GND VDDQ NC
NC
VDDQ GND
VDDQ GND
3
2
NC
Y2
Y0
Y1
GND
VDDQ CLK AVDD
Y4
GND
Y3
1
Y0
A
Y1
B
GND
Y2
D
VDDQ
E
CLK VDDQ AGND
Y3
J
Y4
K
C
G
H
F
VFBGA
TOP VIEW
56 BALL VFBGA PACKAGE LAYOUT
0.65mm
6
5
4
TOP VIEW
3
2
1
A
B
B
C
C
D
D
E
F
F
G
G
H
H
J
J
K
K
A
E
1
2
3
4
5
6
3
IDTCSPT857D
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
GND
Y0
GND
Y5
48
47
46
45
44
43
42
Y0
VDDQ
Y1
40 39 38 37 36 35 34 33 32 31
Y5
1
VDDQ
Y6
30
29
28
27
26
25
24
23
22
21
Y7
GND
Y2
2
Y7
3
Y2
VDDQ
PWRDWN
FBIN
Y1
Y6
4
VDDQ
CLK
GND
GND
GND
Y7
5
GND
GND
Y2
41
6
CLK
FBIN
40
39
38
37
36
35
VDDQ
AVDD
AGND
GND
7
VDDQ
VDDQ
FBOUT
FBOUT
Y2
Y7
8
VDDQ
VDDQ
CLK
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDQ
9
PWRDWN
10
11 12 13 14 15 16 17 18 19 20
FBIN
FBIN
CLK
VDDQ
34
VDDQ
AVDD
FBOUT
FBOUT
33
32
31
30
29
28
AGND
GND
Y3
VFQFPN
TOP VIEW
GND
Y8
Y3
Y8
ABSOLUTEMAXIMUMRATINGS(1)
VDDQ
Y4
VDDQ
Symbol
Rating
Max
Unit
V
Y9
VDDQ, AVDD
SupplyVoltageRange
InputVoltageRange
Voltagerangeappliedtoany
outputinthehighorlowstate
InputClampCurrent
–0.5to+3.6
27
26
25
(2)
VI
–0.5 to VDDQ + 0.5
–0.5 to VDDQ + 0.5
V
Y4
Y9
(2)
VO
V
GND
GND
IIK
–50
mA
mA
(VI <0)
TSSOP/ TVSOP
TOP VIEW
IOK
OutputClampCurrent
±50
(VO <0 or
VO > VDDQ)
IO
CAPACITANCE(1)
ContinuousOutputCurrent
±50
mA
(VO =0 to VDDQ)
VDDQ or GND
TSTG
Parameter
Description
Min.
Typ.
Max. Unit
ContinuousCurrent
±100
mA
°C
CIN
InputCapacitance
VI = VDDQ or GND
DeltaInputCapacitance
VI = VDDQ or GND
LoadCapacitance
2.5
—
3.5
0.25
—
pF
pF
pF
StorageTemperatureRange
– 65 to +150
NOTES:
CI(∆)
-0.25
—
—
14
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CL
NOTE:
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
1. Unused inputs must be held high or low to prevent them from floating.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
4
IDTCSPT857D
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
RECOMMENDEDOPERATINGCONDITIONS
Symbol
AVDD
Parameter
Min.
VDDQ–0.12
2.3
Typ.
VDDQ
2.5
Max.
2.7
Unit
V
SupplyVoltage
VDDQ
I/O Supply Voltage
PC1600-PC2700
PC3200
OperatingFree-AirTemperature
2.7
V
2.5
2.6
2.7
TA
-40
+85
°C
PINDESCRIPTION(TSSOP/TVSOP)
Pin Name
AGND
Pin Number
Description
17
Groundforanalogsupply
Analogsupply
AVDD
16
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
13,14
35,36
Differentialclockinput
Feedbackdifferentialclockinput
Feedbackdifferentialclockoutput
Ground
32,33
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
37
PWRDWN
VDDQ
OutputenableforYandY
I/O supply
4, 11, 12, 15, 21, 28, 34, 38, 45
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Y[0:9]
Bufferedoutputofinputclock,CLK
Bufferedoutputofinputclock,CLK
Y[0:9]
PINDESCRIPTION(VFBGA)
Pin Name
AGND
Pin Number
Description
H1
Groundfor analogsupply
Analogsupply
AVDD
G2
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
F1, F2
F5, F6
Differentialclockinput
Feedbackdifferentialclockinput
Feedbackdifferentialclockoutput
Ground
H6, G5
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
E6
PWRDWN
VDDQ
OutputenableforYandY
I/O supply
B3, B4, E1, E2, E5, G1, G6, J3, J4
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
Y[0:9]
Bufferedoutputofinputclock,CLK
Bufferedoutputofinputclock,CLK
Y[0:9]
PINDESCRIPTION(VFQFPN)
Pin Name
AGND
Pin Number
Description
9
Groundforanalogsupply
Analogsupply
AVDD
8
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
5, 6
Differentialclockinput
25,26
Feedbackdifferentialclockinput
Feedbackdifferentialclockoutput
Ground
21,22
1, 10
PWRDWN
VDDQ
27
OutputenableforYandY
I/O supply
4, 7, 13, 18, 23, 24, 28, 33, 38
3, 12, 14, 17, 19, 29, 32, 34, 37, 39
2, 11, 15, 16, 20, 30, 31, 35, 36, 40
Y[0:9]
Bufferedoutputofinputclock,CLK
Bufferedoutputofinputclock,CLK
Y[0:9]
5
IDTCSPT857D
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
FUNCTIONTABLE(1)
INPUTS
OUTPUTS
AVDD
GND
PWRDWN
CLK
CLK
Y
L
Y
H
L
FBOUT
FBOUT
PLL
Bypassed/OFF
Bypassed/OFF
OFF
H
H
L
L
H
L
H
Z
Z
L
H
L
GND
H
L
H
Z
Z
L
X
L
H
Z
Z
H
L
Z
Z
H
L
X
L
H
L
OFF
Nominal(2)
Nominal(2)
Nominal(2,3)
H
H
X
L
H
H
L
ON
H
Z
H
Z
ON
<20MHz
<20MHz
Z
Z
OFF
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance OFF-State
X = Don't Care
2. AVDD nominal is 2.5V for PC1600, PC2100, and PC2700. AVDD nominal is 2.6V for PC3200.
3. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs
= tristate.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORPC1600-
PC2700
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C; Industrial: TA = -40°C to +85°C
Symbol
VIK
Parameter
Conditions
Min.
Typ.
Max.
– 1.2
0.7
Unit
V
InputClampVoltage(AllInputs)
StaticInputLOWVoltage
Static Input HIGH Voltage
DynamicInputLOWVoltage
Dynamic Input HIGH Voltage
OutputLOWVoltage
VDDQ = 2.3V, II = -18mA
PWRDWN
– 0.3
1.7
VIL(dc)
VIH(dc)
VIL(ac)
VIH(ac)
VOL
V
PWRDWN
VDDQ + 0.3
0.7
CLK, CLK, FBIN, FBIN
CLK, CLK, FBIN, FBIN
AVDD/VDDQ = Min., IOL = 100µA
AVDD/VDDQ = Min., IOL = 12mA
AVDD/VDDQ = Min., IOH = -100µA
AVDD/VDDQ = Min., IOH = -12mA
V
V
V
1.7
VDDQ
0.1
0.6
VOH
VIX
Output HIGH Voltage
VDDQ – 0.1
1.7
InputDifferentialCrossVoltage
DCInputDifferentialVoltage
ACInputDifferentialVoltage
InputCurrent
VDDQ/2–0.2
0.36
VDDQ/2 + 0.2
VDDQ + 0.6
VDDQ + 0.6
±10
V
V
(1)
VID(DC)
(1)
VID(AC)
0.7
V
IIN
VDDQ = 2.7V, VI = 0V to 2.7V
µA
µA
mA
IDDPD
IDDQ
Power-Down Current on VDDQ andAVDD
Dynamic Power Supply Current on VDDQ
AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L
AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF
AVDD/VDDQ = Max., CLK = 170MHz, 120Ω/14pF
AVDD/VDDQ = Max., CLK = 170MHz
100
320
250
200
360
300
IADD
Dynamic Power Supply Current on AVDD
12
mA
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
6
IDTCSPT857D
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORPC3200
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C; Industrial: TA = -40°C to +85°C
Symbol
VIK
Parameter
Conditions
Min.
Typ.
Max.
– 1.2
0.7
Unit
V
InputClampVoltage(AllInputs)
StaticInputLOWVoltage
Static Input HIGH Voltage
DynamicInputLOWVoltage
Dynamic Input HIGH Voltage
OutputLOWVoltage
VDDQ = 2.5V, II = -18mA
PWRDWN
– 0.3
1.7
VIL(dc)
VIH(dc)
VIL(ac)
VIH(ac)
VOL
V
PWRDWN
VDDQ + 0.3
0.7
CLK, CLK, FBIN, FBIN
CLK, CLK, FBIN, FBIN
AVDD/VDDQ = Min., IOL = 100µA
AVDD/VDDQ = Min., IOL = 12mA
AVDD/VDDQ = Min., IOH = -100µA
AVDD/VDDQ = Min., IOH = -12mA
V
V
V
1.7
VDDQ
0.1
0.6
VOH
VIX
Output HIGH Voltage
VDDQ – 0.1
1.7
InputDifferentialCrossVoltage
DCInputDifferentialVoltage
ACInputDifferentialVoltage
InputCurrent
VDDQ/2–0.2
0.36
VDDQ/2 + 0.2
VDDQ + 0.6
VDDQ + 0.6
±10
V
V
(1)
VID(DC)
(1)
VID(AC)
0.7
V
IIN
VDDQ = 2.7V, VI = 0V to 2.7V
µA
µA
mA
IDDPD
IDDQ
Power-Down Current on VDDQ andAVDD
Dynamic Power Supply Current on VDDQ
AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L
AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF
AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF
AVDD/VDDQ = Max., CLK = 200MHz
100
320
250
200
360
300
IADD
Dynamic Power Supply Current on AVDD
12
mA
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
TIMING REQUIREMENTS FOR PC1600 - PC2700
Symbol
Parameter
Min.
Max.
200
200
60
Unit
MHz
MHz
%
fCLK
OperatingClockFrequency(1,2)
ApplicationClockFrequency(1,3)
Input Clock Duty Cycle
StabilizationTime(4)
60
60
tDC
tL
40
100
µs
NOTES:
1. The PLL will track a spread spectrum clock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3. Application clock frequency is the range over which timing specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
TIMINGREQUIREMENTSFORPC3200
Symbol
Parameter
Min.
60
Max.
220
220
60
Unit
MHz
MHz
%
fCLK
OperatingClockFrequency(1,2)
ApplicationClockFrequency(1,3)
Input Clock Duty Cycle
StabilizationTime(4)
60
tDC
tL
40
100
µs
NOTES:
1. The PLL will track a spread spectrum clock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3. Application clock frequency is the range over which timing specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
7
IDTCSPT857D
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
SWITCHINGCHARACTERISTICSFORPC1600-PC2700
Symbol
Description
Test Conditions
Min.
Typ.(1)
4.5
Max.
Unit
ns
(1)
tPLH
LOW to HIGH Level Propagation Delay Time
HIGH to LOW Level Propagation Delay Time
Jitter(period),seefigure6
Testmode, CLKtoanyoutput
Testmode, CLKtoanyoutput
66MHz
(1)
tPHL
4.5
ns
tJIT(PER)
tJIT(CC)
–90
–75
–180
–75
–160
–100
1
90
75
ps
100/ 133/ 167/ 200 MHz
66MHz
Jitter(cycle-to-cycle),seefigure3
Half-PeriodJitter,seefigure7
180
75
ps
ps
100/ 133/ 167/ 200 MHz
66MHz
tJIT(HPER)
160
100
2.5
100/ 133/ 167/ 200 MHz
100/ 133/ 167/ 200 MHz (20% to 80%)
tSLR(O)
tSLR(I)
t(∅)
OutputClockSlewRate(Single-Ended)
Input Clock Slew Rate
StaticPhaseOffset,seefigure4(2,3)
V/ns
V/ns
ps
1
4
66/ 100/ 133/ 167/ 200 MHz
–50
50
tSK(O)
tR,tF
Output Skew, see figure 5
75
ps
Output Rise and Fall Times (20% to 80%)
OutputDifferentialVoltage
Load: 120Ω / 14pF
Differentialoutputsareterminated
with 120Ω
650
900
VDDQ/2
+ 0.15
ps
(5)
VOX
VDDQ/2
V
–0.15
ThePLLontheCSPT857DwillmeetalltheabovetestparameterswhilesupportingSSCsynthesizers(4) withthefollowingparameters:
SSC
SSC
ModulationFrequency
30
0
5
50
-0.5
KHz
%
ClockInputFrequencyDeviation
PLLLoopBandwidth
f3dB
MHz
NOTES:
1. Refers to transition of non-inverting output.
2. Static phase offset does not include jitter.
3. t(φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V.
4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5. VOX is specified at the SDRAM clock input or test load.
8
IDTCSPT857D
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
SWITCHINGCHARACTERISTICSFORPC3200
Symbol
Description
Test Conditions
Testmode, CLKtoanyoutput
Testmode, CLKtoanyoutput
66MHz
Min.
Typ.(1)
4.5
Max.
Unit
ns
(1)
tPLH
LOW to HIGH Level Propagation Delay Time
HIGH to LOW Level Propagation Delay Time
Jitter(period),seefigure6
(1)
tPHL
4.5
ns
tJIT(PER)
tJIT(CC)
–90
–50
–180
–75
–160
–75
1
90
50
ps
200 MHz
Jitter(cycle-to-cycle),seefigure3
Half-PeriodJitter,seefigure7
66MHz
180
75
ps
ps
200 MHz
tJIT(HPER)
66MHz
160
75
200 MHz
tSLR(O)
tSLR(I)
t(∅)
OutputClockSlewRate(Single-Ended)
Input Clock Slew Rate
StaticPhaseOffset,seefigure4(2,3)
200 MHz (20% to 80%)
2.5
V/ns
V/ns
ps
1
4
200 MHz
–50
50
tSK(O)
tR,tF
Output Skew, see figure 5
75
ps
Output Rise and Fall Times (20% to 80%)
OutputDifferentialVoltage
Load: 120Ω / 14pF
Differentialoutputsareterminated
with 120Ω
650
900
VDDQ/2
+ 0.15
ps
(5)
VOX
VDDQ/2
V
–0.15
ThePLLontheCSPT857DwillmeetalltheabovetestparameterswhilesupportingSSCsynthesizers(4) withthefollowingparameters:
SSC
SSC
ModulationFrequency
30
0
5
50
-0.5
KHz
%
ClockInputFrequencyDeviation
PLLLoopBandwidth
f3dB
MHz
NOTES:
1. Refers to transition of non-inverting output.
2. Static phase offset does not include jitter.
3. t(φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V.
4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5. VOX is specified at the SDRAM clock input or test load.
9
IDTCSPT857D
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TESTCIRCUITANDSWITCHINGWAVEFORMS
VDD
Z = 60Ω
Z = 60Ω
C = 14pF
C = 14pF
VSS
VSS
R = 120Ω
CSPT857D
VSS
Figure 1. Output Load
VDDQ/2
R = 10Ω
Z = 60Ω
Z = 50Ω
Z = 50Ω
C = 14pF
VDDQ/2
R = 50Ω
R = 50Ω
0V
0V
R = 10Ω
Z = 60Ω
C = 14pF
VDDQ/2
CSPT857D
VDDQ/2
SCOPE
Figure 2. Output Load Test Circuit
10
IDTCSPT857D
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
TESTCIRCUITANDSWITCHINGWAVEFORMS
Yx, FBOUT
Yx, FBOUT
tcycle n
tcycle n+1
=
tjit(cc) tcycle n
tcycle n+1
Figure 3. Cycle-to-Cycle jitter
CLK
CLK
FBIN
FBIN
t(Ø)n + 1
t(Ø)n
n = N
(N is a large number of samples)
∑
1
t(Ø)n
=
t(Ø)
N
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 5. Output Skew
11
IDTCSPT857D
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TESTCIRCUITANDSWITCHINGWAVEFORMS
Yx, FBOUT
Yx, FBOUT
tcycle n
Yx, FBOUT
Yx, FBOUT
1
f
o
1
f
=
tjit(per)
tcycle n
o
Figure 6. Period jitter
Yx, FBOUT
Yx, FBOUT
thalf period n
thalf period n+1
Yx, FBOUT
Yx, FBOUT
1
f
o
1
2*f
=
tjit(hper)
thalf period n
o
Figure 7. Half-Period jitter
12
IDTCSPT857D
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
TESTCIRCUITANDSWITCHINGWAVEFORMS
80%
Clock Inputs
and Outputs
80%
VID, VOD
20%
20%
tF
tR
Figure 8. Input and Output Slew Rates
APPLICATIONINFORMATION
Clock Loading on the PLL outputs (pF)
ClockStructure
# of SDRAM Loads per Clock
Min.
Max.
#1
#2
2
4
4
8
7
14
13
IDTCSPT857D
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
APPLICATIONINFORMATION
~2.5"
~0.6" (split to terminator)
SDRAM
CSPT857D
Z = 60Ω
CLK
R = 120Ω
R = 120Ω
C = 14pF
Z = 60Ω
CLK
8 more
FBIN
FBIN
SDRAM
(1)
~0.3"
R = 120Ω
C = 14pF
Feedback path
Figure 9. Clock Structure 1
~2.5"
~0.6" (split to terminator)
SDRAM
SDRAM
Stacked
CSPT857D
Z = 60Ω
Z = 60Ω
CLK
CLK
R = 120Ω
R = 120Ω
C = 14pF
SDRAM
SDRAM
8 more
FBIN
FBIN
Stacked
(1)
~0.3"
R = 120Ω
C = 14pF
Feedback path
Figure 10. Clock Structure 2
NOTE:
1. Memory module vendors may need to adjust the feedback capacitive load in order to meet DDR SDRAM registered DIMM timing requirements.
14
IDTCSPT857D
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V-2.6V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
ORDERINGINFORMATION
X
XXXXX
XX
IDTCSPT
Package Process
Device Type
Blank
I
0°C to +70°C (Commercial)
-40°C to +85°C (Industrial)
Thin Shrink Small Outline Package
TSSOP - Green
Thin Very Small Outline Package
Very Fine Pitch Ball Grid Array
Thermally-Enhanced Plastic Very Fine Pitch
Flat No Lead Package
PA
PAG
PF
BV
NL
MLF - Green
VFQFPN
857D
2.5V - 2.6V PLL Differential 1:10 SDRAM Clock Driver
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for Tech Support:
logichelp@idt.com
(408) 654-6459
15
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