IDTCSPT857PA [IDT]
2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER; 2.5V锁相环差1时10 SDRAM时钟驱动器
| 型号： | IDTCSPT857PA |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 文件： | 总12页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
IDTCSPT857/A
FEATURES:
DESCRIPTION:
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer
todistributeonedifferentialclockinputpair(CLK,CLK)to10differentialoutput
pairs(Y[0:9],Y[0:9])andonedifferentialpairoffeedbackclockoutput(FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333) outputs to the input reference is provided. A CMOS Enable/Disable pin is
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
available for low power disable. When the output frequency falls below
approximately20MHz,thedevicewillenterpowerdownmode. Inthismode,
thereceiversaredisabled,thePLListurnedoff,andtheoutputclockdrivers
aretristated,resultinginacurrentconsumptiondeviceoflessthan200µA.
TheCSPT857requiresnoexternalcomponentsandhasbeenoptimised
forverylowI/Ophaseerror,skew,andjitter,whilemaintainingfrequencyand
duty cycleovertheoperatingvoltageandtemperaturerange.TheCSPT857,
designedforuseinbothmoduleassembliesandsystemmotherboardbased
solutions,providesanoptimumhigh-performanceclocksource.
TheCSPT857isonlyavailableinIndustrialTemperatureRange(-40°Cto
+85°C),andCSPT857AisonlyavailableinCommercialTemperatureRange
(0°Cto+70°C). SeeOrderingInformationfordetails.
FUNCTIONALBLOCKDIAGRAM
37/E6
PWRDWN
TEST
MODE
LOGIC
3/A1
Y0
16/G2
2/A2
Y0
AVDD
5/B2
Y1
6/B1
Y1
10/D1
Y2
9/D2
Y2
20/J2
Y3
19/J1
Y3
22/K1
Y4
23/K2
Y4
46/A6
13/F1
Y5
CLK
14/F2
47/A5
CLK
Y5
PLL
44/B5
36/F6
FBIN
Y6
35/F5
43/B6
FBIN
Y6
39/D6
Y7
40/D5
Y7
29/J5
Y8
30/J6
Y8
27/K6
Y9
26/K5
Y9
32/H6
FBOUT
33/H5
FBOUT
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OCTOBER 2002
1
c
2002 Integrated Device Technology, Inc.
DSC-5172/8
IDTCSPT857/A
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATIONS
PWR
DWN
6
Y8
Y8
Y5
Y5
Y6
Y6
GND
GND
NC
Y7
Y7
FBIN VDDQ FBOUT
FBIN FBOUT GND
Y9
Y9
5
4
VDDQ
NC
NC
NC
NC
GND VDDQ
GND VDDQ
NC
VDDQ GND
VDDQ GND
3
2
NC
NC
Y2
Y0
Y1
GND
VDDQ CLK AVDD
Y4
GND
Y3
1
Y0
A
Y1
B
GND
Y2
D
VDDQ
E
CLK VDDQ AGND
Y3
J
Y4
K
C
G
H
F
VFBGA
TOP VIEW
56 BALL VFBGA PACKAGE LAYOUT
0.65mm
6
5
4
TOP VIEW
3
2
1
A
B
B
C
C
D
D
E
F
F
G
G
H
H
J
J
K
K
A
E
1
2
3
4
5
6
2
IDTCSPT857/A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Rating
Max
Unit
V
VDDQ, AVDD
SupplyVoltageRange
InputVoltageRange
Voltagerangeappliedtoany
outputinthehighorlowstate
InputClampCurrent
–0.5to+3.6
(2)
1
VI
–0.5 to VDDQ + 0.5
–0.5 to VDDQ + 0.5
V
GND
Y0
GND
Y5
48
(2)
VO
V
2
3
47
46
45
44
43
42
Y0
VDDQ
Y1
Y5
IIK
–50
mA
mA
4
VDDQ
Y6
(VI <0)
IOK
OutputClampCurrent
±50
5
(VO <0 or
VO > VDDQ)
IO
6
Y1
Y6
GND
7
GND
GND
Y7
ContinuousOutputCurrent
±50
mA
8
GND
Y2
(VO =0 to VDDQ)
VDDQ or GND
TSTG
41
ContinuousCurrent
±100
mA
°C
9
40
39
38
37
36
35
StorageTemperatureRange
– 65 to +150
10
Y2
Y7
NOTES:
VDDQ
VDDQ
CLK
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
VDDQ
PWRDWN
FBIN
FBIN
CLK
VDDQ
34
VDDQ
of 150°C and a board trace length of 750 mils.
AVDD
FBOUT
FBOUT
33
32
31
30
29
28
AGND
GND
Y3
GND
Y8
CAPACITANCE(1)
Parameter
Description
Min.
Typ. Max. Unit
CIN
InputCapacitance
VI = VDDQ or GND
DeltaInputCapacitance
VI = VDDQ or GND
LoadCapacitance
2.5
—
—
14
3.5
0.25
—
pF
pF
pF
Y3
Y8
VDDQ
Y4
VDDQ
CI(∆)
-0.25
—
Y9
27
26
25
Y4
Y9
CL
NOTE:
GND
GND
1. Unused inputs must be held high or low to prevent them from floating.
TSSOP
TOP VIEW
RECOMMENDEDOPERATINGCONDITIONS
CSPT857
Typ.
VDDQ
2.5
CSPT857A
Typ.
Symbol
AVDD
VDDQ
TA
Parameter
Min.
Max.
Min.
Max.
2.7
Unit
SupplyVoltage
VDDQ–0.12
VDDQ
2.5
V
V
I/O Supply Voltage
2.3
2.7
2.3
0
2.7
OperatingFree-AirTemperature
-40
+85
+70
°C
3
IDTCSPT857/A
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PINDESCRIPTION(TSSOP)
Pin Name
AGND
Pin Number
Description
17
Groundfor2.5Vanalogsupply
AVDD
16
2.5Vanalogsupply
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
13,14
35,36
Differentialclockinput
Feedbackdifferentialclockinput
Feedbackdifferentialclockoutput
Ground
32,33
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
37
PWRDWN
VDDQ
OutputenableforYandY
2.5V supply
4, 11, 12, 15, 21, 28, 34, 38, 45
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Y[0:9]
Bufferedoutputofinputclock,CLK
Bufferedoutputofinputclock,CLK
Y[0:9]
PINDESCRIPTION(VFBGA)
Pin Name
AGND
Pin Number
Description
H1
Groundfor2.5Vanalogsupply
2.5Vanalogsupply
AVDD
G2
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
F1, F2
F5, F6
Differentialclockinput
Feedbackdifferentialclockinput
Feedbackdifferentialclockoutput
Ground
H6, G5
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
E6
PWRDWN
VDDQ
OutputenableforYandY
2.5V supply
B3, B4, E1, E2, E5, G1, G6, J3, J4
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
Y[0:9]
Bufferedoutputofinputclock,CLK
Bufferedoutputofinputclock,CLK
Y[0:9]
FUNCTIONTABLE(1)
INPUTS
OUTPUTS
AVDD
GND
PWRDWN
CLK
CLK
Y
L
Y
H
L
FBOUT
FBOUT
PLL
Bypassed/OFF
Bypassed/OFF
OFF
H
H
L
L
H
L
H
Z
Z
L
H
L
GND
H
L
H
Z
Z
L
X
L
H
Z
Z
H
L
Z
Z
H
L
X
L
H
L
OFF
2.5V(nom)
2.5V(nom)
2.5V(nom)(2)
H
H
X
L
H
H
L
ON
H
Z
H
Z
ON
<20MHz
<20MHz
Z
Z
OFF
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance OFF-State
X = Don't Care
2. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs
= tristate.
4
IDTCSPT857/A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C; Industrial: TA = –40°C to +85°C
Symbol
VIK
Parameter
Conditions
Min.
Typ.
Max.
– 1.2
0.7
Unit
V
InputClampVoltage(AllInputs)
StaticInputLOWVoltage
Static Input HIGH Voltage
DynamicInputLOWVoltage
Dynamic Input HIGH Voltage
OutputLOWVoltage
VDDQ = 2.3V, II = -18mA
PWRDWN
– 0.3
1.7
VIL(dc)
VIH(dc)
VIL(ac)
VIH(ac)
VOL
V
PWRDWN
VDDQ + 0.3
0.7
CLK, CLK, FBIN, FBIN
CLK, CLK, FBIN, FBIN
AVDD/VDDQ = Min., IOL = 100µA
AVDD/VDDQ = Min., IOL = 12mA
AVDD/VDDQ = Min., IOH = -100µA
AVDD/VDDQ = Min., IOH = -12mA
V
V
V
1.7
VDDQ
0.1
0.6
VOH
VIX
Output HIGH Voltage
VDDQ – 0.1
1.7
InputDifferentialCrossVoltage
DCInputDifferentialVoltage
ACInputDifferentialVoltage
InputCurrent
VDDQ/2–0.2
0.36
VDDQ/2 + 0.2
VDDQ + 0.6
VDDQ + 0.6
±10
V
V
(1)
VID(DC)
(1)
VID(AC)
0.7
V
IIN
VDDQ = 2.7V, VI = 0V to 2.7V
µA
µA
mA
IDDPD
IDDQ
Power-Down Current on VDDQ andAVDD
Dynamic Power Supply Current on VDDQ
AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L
AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF
AVDD/VDDQ = Max., CLK = 170MHz, 120Ω/14pF
AVDD/VDDQ = Max., CLK = 170MHz
100
320
250
200
360
300
IADD
Dynamic Power Supply Current on AVDD
12
mA
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
5
IDTCSPT857/A
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TIMINGREQUIREMENTS
Symbol
Parameter
Min.
60
Max.
200
200
60
Unit
MHz
MHz
%
fCLK
OperatingClockFrequency(1,2)
ApplicationClockFrequency(1,3)
Input Clock Duty Cycle
StabilizationTime(4)
60
tDC
tL
40
100
µs
NOTES:
1. The PLL will track a spread spectrum clock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3. Application clock frequency is the range over which timing specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
SWITCHINGCHARACTERISTICS
CSPT857
CSPT857A
Symbol
Description
Test Conditions
Min. Typ.(1) Max. Min. Typ.(1) Max.
Unit
ns
(1)
tPLH
LOW to HIGH Level Propagation Delay Time
HIGH to LOW Level Propagation Delay Time
Jitter(period),seefigure6
Testmode, CLKtoanyoutput
Testmode, CLKtoanyoutput
66MHz
4.5
4.5
4.5
4.5
(1)
tPHL
ns
tJIT(PER)
tJIT(CC)
–90
–75
–180
–75
–160
–100
1
90
75
–90
–75
90
75
ps
100/ 133/ 167/ 200 MHz
66MHz
Jitter(cycle-to-cycle),seefigure3
Half-PeriodJitter,seefigure7
180 –180
75 –75
180
75
ps
ps
100/ 133/ 167/ 200 MHz
66MHz
tJIT(HPER)
160 –160
100 –100
160
100
2
100/ 133/ 167/ 200 MHz
100/ 133/ 167/ 200 MHz (20% to 80%)
tSLR(O)
tSLR(I)
t(∅)
OutputClockSlewRate(Single-Ended)
Input Clock Slew Rate
StaticPhaseOffset,seefigure4(2,3)
2
4
1
1
V/ns
V/ns
ps
1
4
66/ 100/ 133/ 167/ 200 MHz
–100
100
75
–50
50
tSK(O)
tR,tF
Output Skew, see figure 5
75
ps
Output Rise and Fall Times (20% to 80%)
OutputDifferentialVoltage
Load: 120Ω / 14pF
Differentialoutputsareterminated
with 120Ω
650
VDDQ/2
– 0.2
900
650
900
ps
(5)
VOX
VDDQ/2 VDDQ/2
VDDQ/2
+ 0.15
V
+ 0.2 –0.15
ThePLLontheCSPT857willmeetalltheabovetestparameterswhilesupportingSSCsynthesizers(4) withthefollowingparameters:
SSC
SSC
ModulationFrequency
30
0
5
50
-0.5
30
0
5
50
-0.5
KHz
%
ClockInputFrequencyDeviation
PLLLoopBandwidth
f3dB
MHz
NOTES:
1. Refers to transition of non-inverting output.
2. Static phase offset does not include jitter.
3. t(φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V.
4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5. VOX is specified at the SDRAM clock input or test load.
6
IDTCSPT857/A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
TESTCIRCUITANDSWITCHINGWAVEFORMS
VDD
Z = 60Ω
Z = 60Ω
C = 14pF
C = 14pF
VSS
VSS
R = 120Ω
CSPT857/A
VSS
Figure 1. Output Load
VDDQ/2
R = 10Ω
Z = 60Ω
Z = 50Ω
Z = 50Ω
C = 14pF
VDDQ/2
R = 50Ω
R = 50Ω
0V
0V
R = 10Ω
Z = 60Ω
C = 14pF
VDDQ/2
CSPT857/A
VDDQ/2
SCOPE
Figure 2. Output Load Test Circuit
7
IDTCSPT857/A
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TESTCIRCUITANDSWITCHINGWAVEFORMS
Yx, FBOUT
Yx, FBOUT
tcycle n
tcycle n+1
=
tjit(cc) tcycle n
tcycle n+1
Figure 3. Cycle-to-Cycle jitter
CLK
CLK
FBIN
FBIN
t(Ø)n + 1
t(Ø)n
n = N
(N is a large number of samples)
∑
1
t(Ø)n
=
t(Ø)
N
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 5. Output Skew
8
IDTCSPT857/A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
TESTCIRCUITANDSWITCHINGWAVEFORMS
Yx, FBOUT
Yx, FBOUT
tcycle n
Yx, FBOUT
Yx, FBOUT
1
f
o
1
f
=
tjit(per)
tcycle n
o
Figure 6. Period jitter
Yx, FBOUT
Yx, FBOUT
thalf period n
thalf period n+1
Yx, FBOUT
Yx, FBOUT
1
f
o
1
2*f
=
tjit(hper)
thalf period n
o
Figure 7. Half-Period jitter
9
IDTCSPT857/A
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TESTCIRCUITANDSWITCHINGWAVEFORMS
80%
Clock Inputs
and Outputs
80%
VID, VOD
20%
20%
tF
tR
Figure 8. Input and Output Slew Rates
APPLICATIONINFORMATION
Clock Loading on the PLL outputs (pF)
ClockStructure
# of SDRAM Loads per Clock
Min.
Max.
#1
#2
2
4
4
8
7
14
10
IDTCSPT857/A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
APPLICATIONINFORMATION
~2.5"
~0.6" (split to terminator)
SDRAM
CSPT857/A
Z = 60Ω
CLK
R = 120Ω
R = 120Ω
C = 14pF
Z = 60Ω
CLK
8 more
FBIN
FBIN
SDRAM
(1)
~0.3"
R = 120Ω
C = 14pF
Feedback path
Figure 9. Clock Structure 1
~2.5"
~0.6" (split to terminator)
SDRAM
SDRAM
Stacked
CSPT857/A
Z = 60Ω
Z = 60Ω
CLK
CLK
R = 120Ω
R = 120Ω
C = 14pF
SDRAM
SDRAM
8 more
FBIN
FBIN
Stacked
(1)
~0.3"
R = 120Ω
C = 14pF
Feedback path
Figure 10. Clock Structure 2
NOTE:
1. Memory module vendors may need to adjust the feedback capacitive load in order to meet DDR SDRAM registered DIMM timing requirements.
11
IDTCSPT857/A
2.5V PLLDIFFERENTIAL1:10SDRAMCLOCKDRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ORDERINGINFORMATION
X
XXXXX
XX
IDTCSPT
Package Process
Device Type
Blank
I
0°C to +70°C (Commercial, A speed only)
-40°C to +85°C (Industrial, Std. speed only)
PA
BV
Thin Shrink Small Outline Package
Very Fine Pitch Ball Grid Array
2.5V PLL Differential 1:10 SDRAM Clock Driver
857
857A
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for Tech Support:
logichelp@idt.com
(408) 654-6459
12
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