TP2412-TR [3PEAK]
Low Cost, Low Noise CMOS RRIO Op-amps;
| 型号： | TP2412-TR |
| 厂家： | 
3PEAK |
| 描述： | Low Cost, Low Noise CMOS RRIO Op-amps |
| 文件： | 总17页 (文件大小：1258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TP2411/TP2412 /TP2414
Low Cost, Low Noise CMOS RRIO Op-amps
Description
3PEAK
Features
The TP2411, TP2412, and TP2414 are low cost, single,
dual, and quad rail-to-rail output, single-supply amplifiers
featuring low offset and input voltages, low current noise,
and wide signal bandwidth. The combination of low
offset, low noise, very low input bias currents, and high
speed make these amplifiers useful in a wide variety of
applications. Filters, integrators, photodiode amplifiers,
and high impedance sensors all benefit from this
combination of performance features. Audio and other
ac applications benefit from the wide bandwidth and low
distortion of these devices.
Gain-bandwidth Product: 10 MHz
Low Noise: 8.2 nV/√Hz(f= 1kHz)
Slew Rate: 7 V/μs
Offset Voltage: 1 mV (max)
EMIRR IN+: 88 dB( under 2.4GHz)
Low THD+N: 0.0005%
Supply Range: 2.2 V to 5.5 V
Supply Current: 1.4 mA/ch
Low Input Bias Current: 0.3pA Typical
Rail-to-Rail I/O
Applications for these amplifiers include power
amplifier (PA) controls, laser diode control loops,
portable and loop-powered instrumentation, audio
amplification for portable devices, and ASIC input and
output amplifiers.
High Output Current: 70 mA (1.0V Drop)
–40°C to 125°C Operation Range
The TP2411 is single channel version available in 8-pin
SOP and 5-pin SOT23 packages. The TP2412 is dual
channel version available in 8-pin SOP, SOT, TSSOP
and MSOP packages. The TP2414 is quad channel
version available in 14-pin SOP and TSSOP packages.
Applications
Sensor Signal Conditioning
Consumer Audio
Multi-Pole Active Filters
Control-Loop Amplifiers
Communications
Security
3PEAK and the 3PEAK logo are registered trademarks of
3PEAK INCORPORATED. All other trademarks are the property of
their respective owners.
Scanners
Pin Configuration(Top View)
TP2411
8-Pin SOP
(-S Suffix)
TP2412
8-Pin SOP/MSOP/SOT/TSSOP
(-S ,-V, -T, -TS Suffixes)
Input Voltage Noise Spectral Density
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
NC
NC
﹢Vs
Out
NC
Out A
﹢Vs
1000
﹣In
﹣In A
Out B
﹣In B
﹢In B
A
﹢In
﹢In A
﹣Vs
B
VCC= +5V
RL= 1kΩ
﹣Vs
100
TP2411
5-Pin SOT23
(-T Suffix)
TP2414
14-Pin SOP/TSSOP
(-S and -T Suffixes)
1
2
3
4
5
6
7
14
Out A
﹣In A
﹢In A
﹢Vs
Out D
1
2
3
5
4
Out
﹢Vs
10
1
13 ﹣In D
﹣Vs
A
B
D
C
12
11
﹢In D
﹣Vs
+In
-In
10 ﹢In C
﹢In B
﹣In B
Out B
9
8
﹣In C
1
10
100
1k
10k
100k
1M
Out C
Frequency(Hz)
www.3peakic.com.cn
Rev. B.01
1
Low Cost, Low Noise CMOS RRIO Op-amps
Order Information
Marking
Information
Model Name
Order Number
Package
8-Pin SOP
Transport Media, Quantity
TP2411-SR
TP2411-TR
TP2412-SR
TP2412-VR
TP2412-TSR
TP2412-TR
TP2414-SR
TP2414-TR
Tape and Reel, 4,000
Tape and Reel, 3,000
Tape and Reel, 4,000
Tape and Reel, 3,000
Tape and Reel, 3,000
Tape and Reel, 3,000
Tape and Reel, 2,500
Tape and Reel, 3,000
TP2411
411
TP2411
5-Pin SOT23
8-Pin SOP
TP2412
TP2412
TP2412
S12
8-Pin MSOP
8-Pin TSSOP
8-Pin SOT23
14-Pin SOP
14-Pin TSSOP
TP2412
TP2414
TP2414
TP2414
Note 1
Absolute Maximum Ratings
Supply Voltage: V+ – V– Note 2............................7.0V
Input Voltage............................. V– – 0.3 to V+ + 0.3
Input Current: +IN, –IN Note 3.......................... ±20mA
Output Short-Circuit Duration Note 4…......... Indefinite
Current at Supply Pins……………............... ±60mA
Operating Temperature Range........–40°C to 125°C
Maximum Junction Temperature................... 150°C
Storage Temperature Range.......... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ......... 260°C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The op amp supplies must be established simultaneously, with, or before, the application of any input signals.
Note 3: The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input
current should be limited to less than 10mA.
Note 4: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many
amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces
connected to the leads.
ESD, Electrostatic Discharge Protection
Symbol
Parameter
Condition
Minimum Level
Unit
HBM
CDM
Human Body Model ESD
ANSI/ESDA/JEDEC JS-001
ANSI/ESDA/JEDEC JS-002
2
1
kV
kV
Charged Device Model ESD
Thermal Resistance
Package Type
5-Pin SOT23
8-Pin SOP
θJA
250
158
210
191
196
120
180
θJC
81
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
43
8-Pin MSOP
8-Pin TSSOP
8-Pin SOT23
14-Pin SOP
14-Pin TSSOP
45
70
36
35
Rev. B.01
www.3peakic.com.cn
2
Low Cost, Low Noise CMOS RRIO Op-amps
Electrical Characteristics
The specifications are at TA = 27° C. VS = 5V, RL = 2kΩ, CL =100pF.Unless otherwise noted.
SYMBOL
PARAMETER
Input Offset Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
VCM = VS/2
VCM = 0V
-1
-1
± 0.25
+1
+1
mV
mV
μV/° C
pA
VOS
± 0.25
1
VOS TC
Input Offset Voltage Drift
Input Bias Current
-40°C to 125°C
TA = 27 °C
0.3
150
300
0.3
IB
TA = 85 °C
pA
TA = 125 °C
pA
IOS
Vn
Input Offset Current
Input Voltage Noise
pA
3.14
8.2
f = 0.1Hz to 10Hz
f = 1kHz
μVPP
en
in
Input Voltage Noise Density
Input Current Noise
nV/√Hz
f = 1kHz
2
8
7
fA/√Hz
Differential
Common Mode
CIN
CMRR
VCM
Input Capacitance
pF
VCM = 2.5V
90
80
55
106
106
72
dB
dB
dB
Common Mode Rejection Ratio
VCM = 0V to 3V
VCM = 0V to 5V
Common-mode Input Voltage
Range
V– -0.1
V+-0.1
50
V
PSRR
AVOL
VOL, VOH
ROUT
RO
Power Supply Rejection Ratio
Open-Loop Large Signal Gain
Output Swing from Supply Rail
Closed-Loop Output Impedance
Open-Loop Output Impedance
Output Short-Circuit Current
Supply Voltage
VS = 2.2V to 5.5V, VCM = 0V
RLOAD = 2kΩ, VOUT = -2V to 2V
RLOAD = 2kΩ
82
100
120
20
dB
dB
mV
Ω
100
G = 1, f =1MHz, IOUT = 0
f = 1kHz, IOUT = 0
0.2
125
130
Ω
ISC
Sink or source current
100
2.2
mA
V
VS
5.5
IQ
Quiescent Current per Amplifier
Phase Margin
VS = 5V
1.4
60
8
1.95
mA
°
PM
RLOAD = 1kΩ, CLOAD = 60pF
RLOAD = 1kΩ, CLOAD = 60pF
f = 1kHz
GM
Gain Margin
dB
MHz
GBWP
Gain-Bandwidth Product
10
AV = 1, VOUT = 0V to 10V, CLOAD = 100pF,
RLOAD = 2kΩ
SR
FPBW
tS
Slew Rate
3.0
7
V/μs
kHz
μs
Full Power Bandwidth Note 1
414
Settling Time, 0.1%
Settling Time, 0.01%
Total Harmonic Distortion and
Noise
0.75
0.85
AV = –1, 1V Step
THD+N
Xtalk
f = 1kHz, AV =1, RL = 2kΩ, VOUT = 1Vp-p
f = 1kHz, RL = 2kΩ
0.0005
110
%
Channel Separation
dB
Note 1: Full power bandwidth is calculated from the slew rate FPBW = SR/π • VP-P
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Rev. B.01
3
Low Cost, Low Noise CMOS RRIO Op-amps
Typical Performance Characteristics
VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified.
Offset Voltage Production Distribution
Unity Gain Bandwidth vs. Temperature
1000
15
14.9
14.8
14.7
14.6
14.5
14.4
14.3
14.2
14.1
14
Number = 38300 pcs
900
800
700
600
500
400
300
200
100
0
-40
-20
0
20
40
60
80
100 120
Temperature(℃)
Offset Voltage(uV)
Open-Loop Gain and Phase
Input Voltage Noise Spectral Density
140
330
120
1000
100
10
VCC= +5V
RL= 1kΩ
100
80
230
130
30
60
40
20
-70
0
-20
-40
-60
-170
1
-270
1000M
1
10
100
1k
10k
100k
1M
0.1
10
1k
100k
10M
Frequency(Hz)
Frequency (Hz)
Input Bias Current vs. Temperature
Input Bias Current vs. Input Common Mode Voltage
5.00E-16
1.00E-11
1.00E-13
1.00E-15
1.00E-17
1.00E-19
1.00E-21
5.00E-17
5.00E-18
0
1
2
3
4
5
6
-10
10
30
50
70
90
110 130 150
Common Mode Voltage(V)
Temperature(℃)
Rev. B.01
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4
Low Cost, Low Noise CMOS RRIO Op-amps
Typical Performance Characteristics
VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
Common Mode Rejection Ratio
CMRR vs. Frequency
180
140
120
100
160
140
120
100
80
60
40
20
0
80
60
40
20
0
1
100
10k
1M
100M
0
1
2
3
4
Frequency(Hz)
Common Mode Voltage(V)
Quiescent Current vs. Temperature
Short Circuit Current vs. Temperature
200
180
160
140
120
100
80
1.48
1.46
1.44
1.42
1.4
I
SINK
I
SOURCE
1.38
1.36
1.34
1.32
1.3
60
40
20
0
-50
0
50
100
150
-40
-15
10
35
60
85
110
Temperature(℃)
Temperature(℃)
Power-Supply Rejection Ratio
Quiescent Current vs. Supply Voltage
1.8
1.6
1.4
1.2
1
140
120
100
80
60
40
20
0
PSRR+
0.8
0.6
0.4
0.2
0
PSRR-
1
100
10k
1M
1.5
2.5
3.5
4.5
5.5
Frequency(Hz)
Supply Voltage (V)
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Rev. B.01
5
Low Cost, Low Noise CMOS RRIO Op-amps
Typical Performance Characteristics
VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
Power-Supply Rejection Ratio vs. Temperature
CMRR vs. Temperature
120
100
80
60
40
20
0
140
120
100
80
60
40
20
0
-50
0
50
100
150
-50
0
50
100
150
Temperature(℃)
Temperature(℃)
EMIRR IN+ vs. Frequency
Large-Scale Step Response
100
90
80
70
60
50
40
30
20
10
0
Gain=+1
RL=10kΩ
40
400
4000
Frequency (MHz)
Time (20μs/div)
Negative Over-Voltage Recovery
Positive Over-Voltage Recovery
Gain=+10
±V=±2.5V
Gain=+10
±V=±2.5V
Time (500ns/div)
Time (500ns/div)
Rev. B.01
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6
Low Cost, Low Noise CMOS RRIO Op-amps
Typical Performance Characteristics
VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
0.1 Hz TO 10 Hz Input Voltage Noise
Offset Voltage vs Common-Mode Voltage
500
0
-500
Vcc=±2.5V
-1000
-1500
-2000
-2500
-3000
-2.5
-1.5
-0.5
0.5
1.5
2.5
5s/div
Common-mode voltage(V)
Positive Output Swing vs. Load Current
Negative Output Swing vs. Load Current
0
-20
140
120
100
80
-40℃
25℃
-40
-60
+125℃
-80
-100
-120
-140
-160
-180
-200
60
+125℃
25℃
40
20
-40℃
0
0
1
2
3
4
5
0
1
2
3
4
5
Vout Dropout (V)
Vout Dropout (V)
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Rev. B.01
7
Low Cost, Low Noise CMOS RRIO Op-amps
Pin Functions
-IN: Inverting Input of the Amplifier.
possible should be used between power supply pins or
between supply pins and ground.
+IN: Non-Inverting Input of Amplifier.
OUT: Amplifier Output. The voltage range extends to
within mV of each supply rail.
V- or -Vs: Negative Power Supply. It is normally tied to
ground. It can also be tied to a voltage other than
ground as long as the voltage between V+ and V– is from
2.2V to 5.5V. If it is not connected to ground, bypass it
V+ or +Vs: Positive Power Supply. Typically the voltage
is from 2.2V to 5.5V. Split supplies are possible as long
as the voltage between V+ and V– is between 2.2V and
5.5V. A bypass capacitor of 0.1μF as close to the part as
with a capacitor of 0.1μF as close to the part as
possible.
Operation
The TP2411 series op amps can operate on a single-supply voltage (2.2 V to 5.5 V), or a split-supply voltage (±1.1 V to
±2.75 V), making them highly versatile and easy to use. The power-supply pins should have local bypass ceramic
capacitors (typically 0.001 μF to 0.1 μF). These amplifiers are fully specified from +2.2 V to +5.5 V and over the
extended temperature range of –40°C to +125°C. Parameters that can exhibit variance with regard to operating voltage
or temperature are presented in the Typical Characteristics.
Applications Information
Input ESD Diode Protection
The TP2411 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of input and
output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply
pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as the current is limited to
10 mA as stated in the Absolute Maximum Ratings table. Many input signals are inherently current-limited to less than
10 mA; therefore, a limiting resistor is not required. Figure 1 shows how a series input resistor (RS) may be added to
the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the
value should be kept to the minimum in noise-sensitive applications.
V+
Current-limiting resistor
required if input voltage
exceeds supply rails by
500Ω
+2.5V
IN+
>0.5V.
Ioverload
10mA max
TP2411
VIN
Vout
500Ω
IN-
5kΩ
-2.5V
V-
INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
Figure1. Input ESD Diode
Rev. B.01
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Low Cost, Low Noise CMOS RRIO Op-amps
PHASE REVERSAL
The TP2411 op amps are designed to be immune to phase reversal when the input pins exceed the supply voltages,
therefore providing further in-system stability and predictability. Figure 2 shows the input voltage exceeding the supply
voltage without any phase reversal.
Figure 2. No Phase Reversal
EMI SUSCEPTIBILITY AND INPUT FILTERING
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the device,
the dc offset observed at the amplifier output may shift from the nominal value while EMI is present. This shift is a result
of signal rectification associated with the internal semiconductor junctions. While all operational amplifier pin functions
can be affected by EMI, the input pins are likely to be the most susceptible. The TP2411 operational amplifier family
incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both common-mode and
differential mode filtering are provided by the input filter. The filter is designed for a cutoff frequency of approximately
500 MHz (–3 dB), with a roll-off of 20 dB per decade.
100
90
80
70
60
50
40
30
20
10
0
40
400
4000
Frequency (MHz)
Figure 3. TP2411 EMIRR IN+ vs Frequency
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Rev. B.01
9
Low Cost, Low Noise CMOS RRIO Op-amps
PCB Surface Leakage
In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be
considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of current to flow,
which is greater than the TP2411/2412/2414 OPA’s input bias current at +27°C (±3pA, typical). It is recommended to
use multi-layer PCB layout and route the OPA’s -IN and +IN signal under the PCB surface.
The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is
biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 1 for Inverting
Gain application.
1. For Non-Inverting Gain and Unity-Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface.
b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common Mode input voltage.
2. For Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors):
a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the
op-amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface.
Guard Ring
VIN+
VIN-
+VS
Figure 4 The Layout of Guard Ring
Power Supply Layout and Bypass
The TP2411/2412/2412 OPA’s power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e.,
0.01μF to 0.1μF) within 2mm for good high frequency performance. It can also use a bulk capacitor (i.e., 1μF or larger)
within 100mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts.
Ground layout improves performance by decreasing the amount of stray capacitance and noise at the OPA’s inputs
and outputs. To decrease stray capacitance, minimize PC board lengths and resistor leads, and place external
components as close to the op amps’ pins as possible.
Proper Board Layout
To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid
leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates a
barrier to moisture accumulation and helps reduce parasitic resistance on the board.
Keeping supply traces short and properly bypassing the power supplies minimizes power supply disturbances due to
output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be connected
as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and the inputs of the
amplifier. It is recommended that signal traces be kept at least 5mm from supply lines to minimize coupling.
A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and other
points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple
effects, orient resistors so heat sources warm both ends equally. Input signal paths should contain matching numbers
and types of components, where possible to match the number and type of thermocouple junctions. For example,
dummy components such as zero value resistors can be used to match real resistors in the opposite input path.
Matching components should be located in close proximity and should be oriented in the same manner. Ensure leads
are of equal length so that thermal conduction is in equilibrium. Keep heat sources on the PCB as far away from
amplifier input circuitry as is practical.
The use of a ground plane is highly recommended. A ground plane reduces EMI noise and also helps to maintain a
constant temperature across the circuit board.
Rev. B.01
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10
Low Cost, Low Noise CMOS RRIO Op-amps
Package Outline Dimensions
SOT23-5
D
A2
A1
θ
L1
e
Dimensions
Dimensions
In Inches
In Millimeters
Symbol
Min
Max
Min
Max
A1
A2
b
0.000
1.050
0.300
2.820
1.500
2.650
0.100
1.150
0.400
3.020
1.700
2.950
0.000
0.041
0.012
0.111
0.059
0.104
0.004
0.045
0.016
0.119
0.067
0.116
E1
E
D
E
E1
e
0.950TYP
0.037TYP
e1
L1
θ
1.800
0.300
0°
2.000
0.460
8°
0.071
0.012
0°
0.079
0.024
8°
b
e1
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Rev. B.01
11
Low Cost, Low Noise CMOS RRIO Op-amps
Package Outline Dimensions
SOT-23-8
Dimensions
Dimensions In
Inches
In Millimeters
Symbol
Min
Max
Min
Max
A
A1
A2
b
1.050
0.000
1.050
0.300
0.100
2.820
1.500
2.600
1.250
0.100
1.150
0.500
0.200
3.020
1.700
3.000
0.041
0.000
0.041
0.012
0.004
0.111
0.059
0.102
0.049
0.004
0.045
0.020
0.008
0.119
0.067
0.118
c
D
E
E1
e
0.65（BSC）
0.975（BSC）
0.300 0.600
0° 8°
0.026(BSC)
0.038(BSC)
e1
L
0.012
0°
0.024
θ
8°
Rev. B.01
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12
Low Cost, Low Noise CMOS RRIO Op-amps
Package Outline Dimensions
SOP-8
A2
C
θ
L1
A1
e
E
D
Dimensions
Dimensions In
Inches
In Millimeters
Symbol
Min
Max
Min
Max
A1
A2
b
0.100
1.350
0.330
0.190
4.780
3.800
5.800
0.250
1.550
0.510
0.250
5.000
4.000
6.300
0.004
0.053
0.013
0.007
0.188
0.150
0.228
0.010
0.061
0.020
0.010
0.197
0.157
0.248
E1
C
D
E
E1
e
b
1.270 TYP
0.050 TYP
L1
θ
0.400
0°
1.270
8°
0.016
0°
0.050
8°
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Rev. B.01
13
Low Cost, Low Noise CMOS RRIO Op-amps
Package Outline Dimensions
MSOP-8
Dimensions
Dimensions In
Inches
In Millimeters
Symbol
Min
Max
Min
Max
A
0.800
0.000
0.760
0.30 TYP
0.15 TYP
2.900
0.65 TYP
2.900
4.700
0.410
0°
1.200
0.200
0.970
0.031
0.000
0.030
0.012 TYP
0.006 TYP
0.114
0.026
0.114
0.185
0.016
0°
0.047
0.008
0.038
E
E1
A1
A2
b
C
D
3.100
0.122
e
b
e
E
3.100
5.100
0.650
6°
0.122
0.201
0.026
6°
D
E1
L1
θ
A1
R1
R
θ
L
L1
L2
Rev. B.01
www.3peakic.com.cn
14
Low Cost, Low Noise CMOS RRIO Op-amps
Package Outline Dimensions
TSSOP-8
Symbol
Dimensions In Millimeters
Min Max
3.100
Dimensions In Inches
Min Max
0.122
D
E
2.900
4.300
0.190
0.090
6.250
0.114
0.169
0.007
0.004
0.246
4.500
0.300
0.200
6.550
1.200
1.000
0.150
0.177
0.012
0.008
0.258
0.047
0.039
0.006
b
c
E1
A
A2
A1
e
0.800
0.031
0.002
0.050
0.65(BSC)
0.500
0.026（BSC）
0.020
L
0.700
7°
0.028
7°
H
θ
0.25(BSC)
1°
0.01（BSC）
1°
www.3peakic.com.cn
Rev. B.01
15
Low Cost, Low Noise CMOS RRIO Op-amps
Package Outline Dimensions
TSSOP-14
Dimensions
In Millimeters
E1
E
Symbol
MIN
-
TYP
MAX
1.20
0.15
1.05
0.28
0.19
5.06
6.60
4.50
A
A1
A2
b
-
0.05
0.90
0.20
0.10
4.86
6.20
4.30
-
1.00
-
e
c
c
-
4.96
D
D
E
6.40
E1
e
4.40
0.65 BSC
0.60
L
0.45
0.75
A1
L1
L2
R
1.00 REF
0.25 BSC
-
0.09
0°
-
R1
θ
-
8°
R
θ
L
L1
L2
Rev. B.01
www.3peakic.com.cn
16
Low Cost, Low Noise CMOS RRIO Op-amps
Package Outline Dimensions
SOP-14
D
Dimensions
E1
E
In Millimeters
TYP
Symbol
MIN
1.35
0.10
1.25
0.36
8.53
5.80
3.80
MAX
1.75
0.25
1.65
0.49
8.73
6.20
4.00
A
A1
A2
b
1.60
0.15
e
b
1.45
D
8.63
6.00
E
A2
A
E1
e
3.90
1.27 BSC
0.60
A1
L
0.45
0°
0.80
8°
L1
L2
θ
1.04 REF
0.25 BSC
L
L1
θ
L2
www.3peakic.com.cn
Rev. B.01
17
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