S-1009C30I-I4T1U
更新时间：2024-10-29 23:04:56
品牌：ABLIC
描述：0.27uA CURRENT CONSUMPTION VOLTAGE DETECTOR WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING
概述
数据手册S-1009C30I-I4T1U 概述
0.27uA CURRENT CONSUMPTION VOLTAGE DETECTOR WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING
S-1009C30I-I4T1U 数据手册
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PDF下载S-1009 Series
0.27
A CURRENT CONSUMPTION
VOLTAGE DETECTOR
www.ablic.com
© ABLIC Inc., 2009-2017
Rev.5.1_03
The S-1009 Series is a super high-accuracy voltage detector developed using CMOS technology. The detection voltage is
fixed internally with an accuracy of 0.5%. It operates with super low current consumption of 270 nA typ.
The release signal can be delayed by setting a capacitor externally. Delay time accuracy is 15%. Two output forms Nch
open-drain and CMOS output are available.
Compared with conventional CMOS voltage detectors, the S-1009 Series is the most suitable for the portable devices due
to the super-low current consumption, super high-accuracy and small packages.
Features
Detection voltage:
Detection voltage accuracy:
0.8 V to 4.6 V (0.1 V step)
0.5% (2.4 V VDET 4.6 V)
12 mV (0.8 V VDET 2.4 V)
270 nA typ. (1.2 V VDET 2.3 V)
0.6 V to 10.0 V (CMOS output product)
5% 1%
Current consumption:
Operation voltage range:
Hysteresis width:
Delay time accuracy:
Output form:
15% (CD = 4.7 nF)
Nch open-drain output (active "L")
CMOS output (active "L")
Ta = 40°C to 85°C
Operation temperature range:
Lead-free (Sn 100%), halogen-free
Applications
Power monitor and reset for CPU and microcomputer
Constant voltage power monitor for TV, DVD recorder and home appliance
Power supply monitor for portable device such as notebook PC, digital still camera and mobile phone
Packages
SOT-23-5
SC-82AB
SNT-4A
1
0.27
S-1009 Series
Rev.5.1_03
Block Diagrams
1. Nch open-drain output product
VDD
Delay
circuit
OUT
*1
*1
VREF
*1
VSS
CD
*1. Parasitic diode
Figure 1
2. CMOS output product
VDD
*1
Delay
circuit
*1
OUT
*1
VREF
*1
VSS
CD
*1. Parasitic diode
Figure 2
2
0.27
Rev.5.1_03
S-1009 Series
Product Name Structure
Users can select the output form, detection voltage value, and package type for the S-1009 Series. Refer to "1.
Product name" regarding the contents of product name, "2. Packages" regarding the package drawings and "3.
Product name list" regarding details of product name.
1. Product name
S-1009
x
xx
I
-
xxxx
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M5T1: SOT-23-5, Tape
N4T1: SC-82AB, Tape
I4T1: SNT-4A, Tape
Operation temperature
I:
Ta = 40C to 85C
Detection voltage value
08 to 46
(e.g., when the detection voltage is 1.5 V, it is expressed as 15.)
Output form
N:
C:
Nch open-drain output (active "L")
CMOS output (active "L")
*1. Refer to the tape drawings.
2. Packages
Table 1 Package Drawing Codes
Package Name
SOT-23-5
Dimension
Tape
Reel
Land
MP005-A-P-SD
NP004-A-P-SD
PF004-A-P-SD
MP005-A-C-SD
NP004-A-C-SD
NP004-A-C-S1
PF004-A-C-SD
MP005-A-R-SD
SC-82AB
SNT-4A
NP004-A-R-SD
PF004-A-R-SD
PF004-A-L-SD
3
0.27
S-1009 Series
Rev.5.1_03
3. Product name list
3. 1 Nch open-drain output product
Table 2
Detection Voltage
SOT-23-5
SC-82AB
SNT-4A
0.8 V 12 mV
0.9 V 12 mV
1.0 V 12 mV
1.1 V 12 mV
1.2 V 12 mV
1.3 V 12 mV
1.4 V 12 mV
1.5 V 12 mV
1.6 V 12 mV
1.7 V 12 mV
1.8 V 12 mV
1.9 V 12 mV
2.0 V 12 mV
2.1 V 12 mV
2.2 V 12 mV
2.3 V 12 mV
2.4 V 0.5%
2.5 V 0.5%
2.6 V 0.5%
2.7 V 0.5%
2.8 V 0.5%
2.9 V 0.5%
3.0 V 0.5%
3.1 V 0.5%
3.2 V 0.5%
3.3 V 0.5%
3.4 V 0.5%
3.5 V 0.5%
3.6 V 0.5%
3.7 V 0.5%
3.8 V 0.5%
3.9 V 0.5%
4.0 V 0.5%
4.1 V 0.5%
4.2 V 0.5%
4.3 V 0.5%
4.4 V 0.5%
4.5 V 0.5%
4.6 V 0.5%
S-1009N08I-M5T1U
S-1009N09I-M5T1U
S-1009N10I-M5T1U
S-1009N11I-M5T1U
S-1009N12I-M5T1U
S-1009N13I-M5T1U
S-1009N14I-M5T1U
S-1009N15I-M5T1U
S-1009N16I-M5T1U
S-1009N17I-M5T1U
S-1009N18I-M5T1U
S-1009N19I-M5T1U
S-1009N20I-M5T1U
S-1009N21I-M5T1U
S-1009N22I-M5T1U
S-1009N23I-M5T1U
S-1009N24I-M5T1U
S-1009N25I-M5T1U
S-1009N26I-M5T1U
S-1009N27I-M5T1U
S-1009N28I-M5T1U
S-1009N29I-M5T1U
S-1009N30I-M5T1U
S-1009N31I-M5T1U
S-1009N32I-M5T1U
S-1009N33I-M5T1U
S-1009N34I-M5T1U
S-1009N35I-M5T1U
S-1009N36I-M5T1U
S-1009N37I-M5T1U
S-1009N38I-M5T1U
S-1009N39I-M5T1U
S-1009N40I-M5T1U
S-1009N41I-M5T1U
S-1009N42I-M5T1U
S-1009N43I-M5T1U
S-1009N44I-M5T1U
S-1009N45I-M5T1U
S-1009N46I-M5T1U
S-1009N08I-N4T1U
S-1009N09I-N4T1U
S-1009N10I-N4T1U
S-1009N11I-N4T1U
S-1009N12I-N4T1U
S-1009N13I-N4T1U
S-1009N14I-N4T1U
S-1009N15I-N4T1U
S-1009N16I-N4T1U
S-1009N17I-N4T1U
S-1009N18I-N4T1U
S-1009N19I-N4T1U
S-1009N20I-N4T1U
S-1009N21I-N4T1U
S-1009N22I-N4T1U
S-1009N23I-N4T1U
S-1009N24I-N4T1U
S-1009N25I-N4T1U
S-1009N26I-N4T1U
S-1009N27I-N4T1U
S-1009N28I-N4T1U
S-1009N29I-N4T1U
S-1009N30I-N4T1U
S-1009N31I-N4T1U
S-1009N32I-N4T1U
S-1009N33I-N4T1U
S-1009N34I-N4T1U
S-1009N35I-N4T1U
S-1009N36I-N4T1U
S-1009N37I-N4T1U
S-1009N38I-N4T1U
S-1009N39I-N4T1U
S-1009N40I-N4T1U
S-1009N41I-N4T1U
S-1009N42I-N4T1U
S-1009N43I-N4T1U
S-1009N44I-N4T1U
S-1009N45I-N4T1U
S-1009N46I-N4T1U
S-1009N08I-I4T1U
S-1009N09I-I4T1U
S-1009N10I-I4T1U
S-1009N11I-I4T1U
S-1009N12I-I4T1U
S-1009N13I-I4T1U
S-1009N14I-I4T1U
S-1009N15I-I4T1U
S-1009N16I-I4T1U
S-1009N17I-I4T1U
S-1009N18I-I4T1U
S-1009N19I-I4T1U
S-1009N20I-I4T1U
S-1009N21I-I4T1U
S-1009N22I-I4T1U
S-1009N23I-I4T1U
S-1009N24I-I4T1U
S-1009N25I-I4T1U
S-1009N26I-I4T1U
S-1009N27I-I4T1U
S-1009N28I-I4T1U
S-1009N29I-I4T1U
S-1009N30I-I4T1U
S-1009N31I-I4T1U
S-1009N32I-I4T1U
S-1009N33I-I4T1U
S-1009N34I-I4T1U
S-1009N35I-I4T1U
S-1009N36I-I4T1U
S-1009N37I-I4T1U
S-1009N38I-I4T1U
S-1009N39I-I4T1U
S-1009N40I-I4T1U
S-1009N41I-I4T1U
S-1009N42I-I4T1U
S-1009N43I-I4T1U
S-1009N44I-I4T1U
S-1009N45I-I4T1U
S-1009N46I-I4T1U
4
0.27
Rev.5.1_03
S-1009 Series
3. 2 CMOS output product
Table 3
Detection Voltage
0.8 V 12 mV
0.9 V 12 mV
1.0 V 12 mV
1.1 V 12 mV
1.2 V 12 mV
1.3 V 12 mV
1.4 V 12 mV
1.5 V 12 mV
1.6 V 12 mV
1.7 V 12 mV
1.8 V 12 mV
1.9 V 12 mV
2.0 V 12 mV
2.1 V 12 mV
2.2 V 12 mV
2.3 V 12 mV
2.4 V 0.5%
2.5 V 0.5%
2.6 V 0.5%
2.7 V 0.5%
2.8 V 0.5%
2.9 V 0.5%
3.0 V 0.5%
3.1 V 0.5%
3.2 V 0.5%
3.3 V 0.5%
3.4 V 0.5%
3.5 V 0.5%
3.6 V 0.5%
3.7 V 0.5%
3.8 V 0.5%
3.9 V 0.5%
4.0 V 0.5%
4.1 V 0.5%
4.2 V 0.5%
4.3 V 0.5%
4.4 V 0.5%
4.5 V 0.5%
4.6 V 0.5%
SOT-23-5
SC-82AB
SNT-4A
S-1009C08I-M5T1U
S-1009C09I-M5T1U
S-1009C10I-M5T1U
S-1009C11I-M5T1U
S-1009C12I-M5T1U
S-1009C13I-M5T1U
S-1009C14I-M5T1U
S-1009C15I-M5T1U
S-1009C16I-M5T1U
S-1009C17I-M5T1U
S-1009C18I-M5T1U
S-1009C19I-M5T1U
S-1009C20I-M5T1U
S-1009C21I-M5T1U
S-1009C22I-M5T1U
S-1009C23I-M5T1U
S-1009C24I-M5T1U
S-1009C25I-M5T1U
S-1009C26I-M5T1U
S-1009C27I-M5T1U
S-1009C28I-M5T1U
S-1009C29I-M5T1U
S-1009C30I-M5T1U
S-1009C31I-M5T1U
S-1009C32I-M5T1U
S-1009C33I-M5T1U
S-1009C34I-M5T1U
S-1009C35I-M5T1U
S-1009C36I-M5T1U
S-1009C37I-M5T1U
S-1009C38I-M5T1U
S-1009C39I-M5T1U
S-1009C40I-M5T1U
S-1009C41I-M5T1U
S-1009C42I-M5T1U
S-1009C43I-M5T1U
S-1009C44I-M5T1U
S-1009C45I-M5T1U
S-1009C46I-M5T1U
S-1009C08I-N4T1U
S-1009C09I-N4T1U
S-1009C10I-N4T1U
S-1009C11I-N4T1U
S-1009C12I-N4T1U
S-1009C13I-N4T1U
S-1009C14I-N4T1U
S-1009C15I-N4T1U
S-1009C16I-N4T1U
S-1009C17I-N4T1U
S-1009C18I-N4T1U
S-1009C19I-N4T1U
S-1009C20I-N4T1U
S-1009C21I-N4T1U
S-1009C22I-N4T1U
S-1009C23I-N4T1U
S-1009C24I-N4T1U
S-1009C25I-N4T1U
S-1009C26I-N4T1U
S-1009C27I-N4T1U
S-1009C28I-N4T1U
S-1009C29I-N4T1U
S-1009C30I-N4T1U
S-1009C31I-N4T1U
S-1009C32I-N4T1U
S-1009C33I-N4T1U
S-1009C34I-N4T1U
S-1009C35I-N4T1U
S-1009C36I-N4T1U
S-1009C37I-N4T1U
S-1009C38I-N4T1U
S-1009C39I-N4T1U
S-1009C40I-N4T1U
S-1009C41I-N4T1U
S-1009C42I-N4T1U
S-1009C43I-N4T1U
S-1009C44I-N4T1U
S-1009C45I-N4T1U
S-1009C46I-N4T1U
S-1009C08I-I4T1U
S-1009C09I-I4T1U
S-1009C10I-I4T1U
S-1009C11I-I4T1U
S-1009C12I-I4T1U
S-1009C13I-I4T1U
S-1009C14I-I4T1U
S-1009C15I-I4T1U
S-1009C16I-I4T1U
S-1009C17I-I4T1U
S-1009C18I-I4T1U
S-1009C19I-I4T1U
S-1009C20I-I4T1U
S-1009C21I-I4T1U
S-1009C22I-I4T1U
S-1009C23I-I4T1U
S-1009C24I-I4T1U
S-1009C25I-I4T1U
S-1009C26I-I4T1U
S-1009C27I-I4T1U
S-1009C28I-I4T1U
S-1009C29I-I4T1U
S-1009C30I-I4T1U
S-1009C31I-I4T1U
S-1009C32I-I4T1U
S-1009C33I-I4T1U
S-1009C34I-I4T1U
S-1009C35I-I4T1U
S-1009C36I-I4T1U
S-1009C37I-I4T1U
S-1009C38I-I4T1U
S-1009C39I-I4T1U
S-1009C40I-I4T1U
S-1009C41I-I4T1U
S-1009C42I-I4T1U
S-1009C43I-I4T1U
S-1009C44I-I4T1U
S-1009C45I-I4T1U
S-1009C46I-I4T1U
5
0.27
S-1009 Series
Rev.5.1_03
Pin Configurations
1. SOT-23-5
Table 4
Top view
Pin No.
Symbol
OUT
Description
5
4
1
2
3
4
5
Voltage detection output pin
Input voltage pin
VDD
VSS
NC*1
CD
GND pin
No connection
1
2
3
Connection pin for delay capacitor
*1. The NC pin is electrically open.
Figure 3
The NC pin can be connected to the VDD pin or the VSS pin.
2. SC-82AB
Table 5
Top view
Pin No.
Symbol
VSS
Description
4
3
1
2
3
4
GND pin
VDD
CD
Input voltage pin
Connection pin for delay capacitor
Voltage detection output pin
OUT
1
2
Figure 4
3. SNT-4A
Table 6
Top view
Pin No.
Symbol
Description
GND pin
1
2
4
3
1
2
3
4
VSS
OUT
CD
Voltage detection output pin
Connection pin for delay capacitor
Input voltage pin
Figure 5
VDD
6
0.27
Rev.5.1_03
S-1009 Series
Absolute Maximum Ratings
Table 7
(Ta = 25°C unless otherwise specified)
Item
Power supply voltage
CD pin input voltage
Symbol
Absolute Maximum Rating
Unit
V
VDDVSS
VCD
12
VSS0.3 to VDD 0.3
VSS0.3 to 12.0
VSS0.3 to VDD 0.3
50
V
Nch open-drain output product
V
Output voltage
Output current
VOUT
IOUT
CMOS output product
V
mA
mW
mW
mW
°C
°C
SOT-23-5
SC-82AB
SNT-4A
600*1
Power dissipation
PD
350*1
300*1
Operation ambient temperature
Storage temperature
Topr
Tstg
40 to 85
40 to 125
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm 76.2 mm t1.6 mm
(2) Name: JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
700
600
500
SOT-23-5
400
SC-82AB
300
200
SNT-4A
100
0
100
150
50
0
Ambient Temperature (Ta) [C]
Figure 6 Power Dissipation of Package (When Mounted on Board)
7
0.27
S-1009 Series
Rev.5.1_03
Electrical Characteristics
1. Nch open-drain output product
Table 8
(Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
0.8 V VDET 2.4 V
2.4 V VDET 4.6 V
Min.
Typ.
Max.
Unit
V
VDET(S)
0.012
VDET(S)
0.995
VDET
VDET(S)
0.012
VDET(S)
1.005
VDET
VDET(S)
1
Detection voltage*1 VDET
VDET(S)
VDET
V
1
1
Hysteresis width
VHYS
V
0.04 0.05 0.06
0.8 V VDET 1.2 V
1.2 V VDET 2.3 V
2.3 V VDET 3.6 V
3.6 V VDET 4.6 V
VDD = 0.7 V
S-1009N08 to 14
VDD = 1.2 V
0.7
0.30
0.27
0.42
0.39
0.90
0.90
0.90
0.90
10.0
A
A
A
A
V
2
2
2
2
1
Current
consumption
ISS
VDD = VDET 0.6 V
Operation voltage
Output current
VDD
0.14
0.73
1.47
0.40
1.33
2.39
mA
mA
mA
3
3
3
Output transistor
Nch
IOUT
S-1009N15 to 46
VDD = 2.4 V
S-1009N27 to 46
VDS*2 = 0.5 V
Output transistor
Nch
Leakage current
Delay time
ILEAK
tD
0.08
29.9
A
3
V
DD = 10.0 V, VOUT = 10.0 V
CD = 4.7 nF
22.1
26.0
180
120
100
ms
4
1
1
1
0.8 V VDET 0.9 V
430 ppm/°C
370 ppm/°C
350 ppm/°C
Detection voltage
temperature
VDET
Ta VDET
Ta = 40°C to 85°C 0.9 V VDET 1.2 V
1.2 V VDET 4.6 V
coefficient*3
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 2.)
*2.
VDS: Drain-to-source voltage of the output transistor
*3. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
VDET
Ta
VDET
Ta VDET
mV/°C *1 = VDET(S) (typ.) V *2
ppm/°C *3 1000
]
[
]
[ ]
[
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
8
0.27
Rev.5.1_03
S-1009 Series
2. CMOS output product
Table 9
(Ta = 25°C unless otherwise specified)
Test
Circuit
Item
Symbol
Condition
0.8 V VDET 2.4 V
2.4 V VDET 4.6 V
Min.
Typ.
Max.
Unit
V
VDET(S)
0.012
VDET(S)
0.995
VDET
VDET(S)
0.012
VDET(S)
1.005
VDET
VDET(S)
1
Detection voltage*1 VDET
VDET(S)
VDET
V
1
1
Hysteresis width
VHYS
V
0.04 0.05 0.06
0.8 V VDET 1.2 V
1.2 V VDET 2.3 V
2.3 V VDET 3.6 V
3.6 V VDET 4.6 V
VDD = 0.7 V
S-1009C08 to 14
VDD = 1.2 V
0.6
0.30
0.27
0.42
0.39
0.90
0.90
0.90
0.90
10.0
A
A
A
A
V
2
2
2
2
1
Current
consumption
ISS
VDD = VDET 0.6 V
Operation voltage
Output current
Delay time
VDD
0.14
0.73
1.47
1.62
1.78
0.40
1.33
2.39
2.60
2.86
mA
mA
mA
mA
3
3
3
5
5
Output transistor
Nch
S-1009C15 to 46
VDD = 2.4 V
S-1009C27 to 46
VDS*2 = 0.5 V
IOUT
V
DD = 4.8 V
Output transistor
Pch
S-1009C08 to 39
VDD = 6.0 V
S-1009C40 to 46
VDS*2 = 0.5 V
mA
ms
tD
CD = 4.7 nF
22.1
26.0
180
120
100
29.9
4
1
1
1
0.8 V VDET 0.9 V
Ta = 40°C to 85°C 0.9 V VDET 1.2 V
1.2 V VDET 4.6 V
430 ppm/°C
370 ppm/°C
350 ppm/°C
Detection voltage
temperature
VDET
Ta VDET
coefficient*3
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 3.)
*2.
VDS: Drain-to-source voltage of the output transistor
*3. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
VDET
Ta
VDET
Ta VDET
mV/°C *1 = VDET(S) (typ.) V *2
ppm/°C *3 1000
]
[
]
[ ]
[
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
9
0.27
S-1009 Series
Rev.5.1_03
Test Circuits
A
R*1
100 k
VDD
VSS
VDD
VDD
VSS
VDD
OUT
CD
V
OUT
CD
V
*1. R is unnecessary for CMOS output product.
Figure 7 Test Circuit 1
Figure 8 Test Circuit 2
R*1
100 k
VDD
VDD
VDD
OUT
CD
OUT
CD
V
A
P.G.
Oscilloscope
VDS
VSS
VSS
V
*1. R is unnecessary for CMOS output product.
Figure 9 Test Circuit 3
Figure 10 Test Circuit 4
VDS
V
VDD
VDD
V
OUT
CD
A
VSS
Figure 11 Test Circuit 5
10
0.27
Rev.5.1_03
S-1009 Series
Timing Charts
1. Nch open-drain output product
VDD
Release voltage (VDET
)
Hysteresis width
Detection voltage (VDET
)
(VHYS
)
Minimum operation voltage
VSS
R
VDD
100 k
CD OUT
VSS
VDD
V
Output from OUT pin
VSS
tD
Figure 12
2. CMOS output product
VDD
Release voltage (VDET
)
Hysteresis width
Detection voltage (VDET
)
(VHYS
)
VDD
Minimum operation voltage
VSS
CD OUT
VSS
V
VDD
Output from OUT pin
VSS
tD
Remark When VDD is the minimum operation voltage or less, the output voltage from the OUT pin is indefinite
in the shaded area.
Figure 13
11
0.27
S-1009 Series
Rev.5.1_03
Operation
1. Basic operation: CMOS output (active "L") product
(1)
(2)
When the power supply voltage (VDD) is the release voltage (VDET) or more, the Nch transistor is OFF and
the Pch transistor is ON to output VDD ("H"). Since the Nch transistor N1 in Figure 14 is OFF, the comparator
(RB RC ) VDD
RA RB RC
input voltage is
.
Although VDD decreases to VDET or less, VDD is output when VDD is the detection voltage (VDET) or more.
When VDD decreases to VDET or less (point A in Figure 15), the Nch transistor is ON and the Pch transistor
is OFF so that VSS is output. At this time, the Nch transistor N1 in Figure 14 is turned on, and the input
RB VDD
voltage to the comparator is
.
RA RB
The output is indefinite by decreasing VDD to the IC’s minimum operation voltage or less. If the output is
pulled up, it will be VDD
VSS is output by increasing VDD to the minimum operation voltage or more. Although VDD exceeds VDET and
VDD is less than VDET, the output is VSS
(3)
(4)
(5)
.
.
When increasing VDD to VDET or more (point B in Figure 15), the Nch transistor is OFF and the Pch
transistor is ON so that VDD is output. At this time, VDD is output from the OUT pin after the passage of the
delay time (tD).
VDD
*1
RA
Delay
circuit
Pch
Nch
*1
OUT
RB
RC
*1
VREF
*1
N1
VSS
CD
CD
*1. Parasiteic diode
Figure 14 Operation 1
(2) (3)
A
(4)
B
(5)
VDD
(1)
Release voltage (VDET
)
Hysteresis width
Detection voltage (VDET
)
(VHYS
)
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSS
tD
Figure 15 Operation 2
12
0.27
Rev.5.1_03
S-1009 Series
2. Delay circuit
The delay circuit delays the output signal to the OUT pin from the time at which the power supply voltage (VDD
)
exceeds the release voltage (VDET) when VDD is turned on. The output signal is not delayed when VDD decreases
to the detection voltage (VDET) or less (refer to "Figure 15 Operation 2").
The delay time (tD) is determined by the time constant of the built-in constant current (approx. 100 nA) and the
attached delay capacitor (CD), or the delay time (tD0) when the CD pin is open, and calculated from the following
equation. When the CD value is sufficiently large, the tD0 value can be disregarded.
tD [ms] = Delay coefficient CD [nF] tD0 [ms]
Table 10 Delay Coefficient
Delay Coefficient
Operation
Temperature
Min.
2.82
4.70
5.64
Typ.
4.20
5.47
8.40
Max.
5.72
Ta = 85°C
Ta = 25°C
Ta = 40°C
6.24
12.01
Table 11 Delay Time
Delay Time (tD0
Typ.
0.10 ms
)
Operation Temperature
Min.
Max.
0.24 ms
Ta = 40°C to 85°C
0.01 ms
Caution 1. When the CD pin is open, a double pulse shown in Figure 16 may appear at release.
To avoid the double pulse, attach 100 pF or larger capacitor to the CD pin. Do not apply
voltage to the CD pin from the exterior.
VOUT
Time
Figure 16
2. Mounted board layout should be made in such a way that no current flows into or flows from
the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be
provided.
3. There is no limit for the capacitance of CD as long as the leakage current of the capacitor can
be ignored against the built-in constant current value. Leakage current causes deviation in
delay time. When the leakage current is larger than the built-in constant current, no release
takes place.
13
0.27
S-1009 Series
Rev.5.1_03
3. Other characteristics
3. 1 Temperature characteristics of detection voltage
The shaded area in Figure 17 shows the temperature characteristics of detection voltage in the operation
temperature range.
VDET [V]
0.945 mV/°C
*1
VDET25
0.945 mV/°C
40
25
85
Ta [°C]
*1. VDET25 is an actual detection voltage value at Ta = 25°C.
Figure 17 Temperature Characteristics of Detection Voltage (Example for VDET = 2.7 V)
3. 2 Temperature characteristics of release voltage
VDET
Ta
The temperature change
of the release voltage is calculated by using the temperature change
VDET
Ta
of the detection voltage as follows:
VDET
Ta
VDET
VDET
VDET
Ta
=
The temperature change of the release voltage and the detection voltage has the same sign consequently.
3. 3 Temperature characteristics of hysteresis voltage
VDET
Ta
VDET
Ta
The temperature change of the hysteresis voltage is expressed as
follows:
and is calculated as
VDET
Ta
VDET
Ta
VHYS
VDET
VDET
Ta
=
14
0.27
Rev.5.1_03
S-1009 Series
Standard Circuit
R*1
100 k
VDD
VSS
CD
OUT
*2
CD
*1. R is unnecessary for CMOS output product.
*2. The delay capacitor (CD) should be connected directly to the CD pin and the VSS pin.
Figure 18
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
15
0.27
S-1009 Series
Rev.5.1_03
Explanation of Terms
1. Detection voltage (VDET
)
The detection voltage is a voltage at which the output in Figure 21 turns to "L". The detection voltage varies slightly
among products of the same specification. The variation of detection voltage between the specified minimum
(VDET min.) and the maximum (VDET max.) is called the detection voltage range (refer to Figure 19).
Example: In the S-1009C15, the detection voltage is either one in the range of 1.488 V VDET 1.512 V.
This means that some S-1009C15 have VDET = 1.488 V and some have VDET = 1.512 V.
2. Release voltage (VDET
)
The release voltage is a voltage at which the output in Figure 21 turns to "H". The release voltage varies slightly
among products of the same specification. The variation of release voltages between the specified minimum (VDET
min.) and the maximum (VDET max.) is called the release voltage range (refer to Figure 20). The range is
calculated from the actual detection voltage (VDET) of a product and is in the range of VDET 1.04 VDET VDET
1.06.
Example: For the S-1009C15, the release voltage is either one in the range of 1.548 V VDET 1.602 V.
This means that some S-1009C15 have VDET = 1.548 V and some have VDET = 1.602 V.
VDD
VDD
Release voltage
Detection voltage
VDET max.
VDET min.
VDET max.
VDET min.
Release voltage
range
Detection voltage
range
OUT
OUT
Delay time
Figure 20 Release Voltage
Figure 19 Detection Voltage
R*1
VDD
100 k
VDD OUT
V
VSS
CD
V
CD
*1. R is unnecessary for CMOS output product.
Figure 21 Test Circuit of Detection Voltage and Release Voltage
16
0.27
Rev.5.1_03
S-1009 Series
3. Hysteresis width (VHYS
)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B the voltage at point A = VHYS in "Figure 15 Operation 2"). Setting the hysteresis width between the
detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.
4. Delay time (tD)
The delay time in the S-1009 Series is a period from the input voltage to the VDD pin exceeding the release voltage
(VDET) until the output from the OUT pin inverts. The delay time changes according to the delay capacitor (CD).
VDD
VDET
OUT
tD
Figure 22 Delay Time
5. Feed-through current
Feed-through current is a current that flows instantaneously at the time of detection and release of a voltage
detector. The feed-through current is large in CMOS output product, small in Nch open-drain output product.
6. Oscillation
In applications where a resistor is connected to the voltage detector input (Figure 23), taking a CMOS active "L"
product for example, the feed-through current which is generated when the output goes from "L" to "H" (release)
causes a voltage drop equal to [feed-through current] [input resistance] across the resistor. When the input
voltage drops below the detection voltage (VDET) as a result, the output voltage goes to low level. In this state, the
feed-through current stops and its resultant voltage drop disappears, and the output goes from "L" to "H". The
feed-through current is then generated again, a voltage drop appears, and repeating the process finally induces
oscillation.
VDD
RA
VIN
OUT
S-1009C
RB
VSS
Figure 23 Example for Bad Implementation Due to Detection Voltage Change
17
0.27
S-1009 Series
Rev.5.1_03
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
In CMOS output product of the S-1009 Series, the feed-through current flows at the detection and the release. If the
input impedance is high, oscillation may occur due to the voltage drop by the feed-through current during releasing.
In CMOS output product oscillation may occur when a pull-down resistor is used, and falling speed of the power
supply voltage (VDD) is slow near the detection voltage.
When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
18
0.27
Rev.5.1_03
S-1009 Series
Characteristics (Typical Data)
1. Detection voltage (VDET) vs. Temperature (Ta)
S-1009N08
0.90
S-1009N11
1.20
+VDET
−VDET
+VDET
−VDET
0.85
0.80
0.75
0.70
1.15
1.10
1.05
1.00
−
40
−
25
0
25
Ta [°C]
50
75 85
−
40
−
25
0
25
Ta [°C]
50
75 85
S-1009N12
1.40
S-1009N46
5.00
+VDET
1.30
1.20
1.10
1.00
4.80
4.60
4.40
4.20
+VDET
−VDET
−VDET
−
40
−
25
0
25
Ta [°C]
50
75 85
−
40
−
25
0
25
50
75 85
Ta [°C]
2. Hysteresis width (VHYS) vs. Temperature (Ta)
S-1009N08
8
S-1009N11
8
7
6
5
4
3
7
6
5
4
3
−
40
−
25
0
25
50
75 85
−
40
−
25
0
25
50
75 85
Ta [°C]
Ta [°C]
S-1009N12
8
S-1009N46
8
7
6
5
4
3
7
6
5
4
3
−
40
−
25
0
25
50
75 85
−
40
−
25
0
25
50
75 85
Ta [°C]
Ta [°C]
19
0.27
S-1009 Series
Rev.5.1_03
3. Current consumption (ISS) vs. Input voltage (VDD)
S-1009C08
1.50
Ta = 25°C
S-1009C11
1.00
Ta = 25°C
1.25
1.00
0.75
0.50
0.25
0.75
0.50
0.25
0
0
0
0
2
4
6
8
10
2
4
6
8
10
VDD [V]
VDD [V]
S-1009C12
1.0
Ta = 25°C
S-1009C46
1.0
Ta = 25°C
0.75
0.50
0.25
0.75
0.50
0.25
0
0
0
0
2
4
6
8
10
2
4
6
8
10
VDD [V]
VDD [V]
4. Current consumption (ISS) vs. Temperature (Ta)
S-1009N08
1.00
VDD = VDET 0.6 V
S-1009N11
1.00
VDD = VDET 0.6 V
0.75
0.50
0.25
0
0.75
0.50
0.25
0
−
40
−
25
0
25
50
75 85
−
40
−
25
0
25
Ta [°C]
50
75 85
Ta [°C]
S-1009N12
1.00
V
DD = VDET 0.6 V
S-1009N46
1.00
VDD = VDET 0.6 V
0.75
0.50
0.25
0
0.75
0.50
0.25
0
−
40
−
25
0
25
50
75 85
−
40
−
25
0
25
50
75 85
Ta [°C]
Ta [°C]
20
0.27
Rev.5.1_03
S-1009 Series
5. Nch transistor output current (IOUT
)
vs. VDS
6. Pch transistor output current (IOUT) vs. VDS
S-1009N46
15.0
Ta = 25°C
S-1009C08
40.0
Ta = 25°C
V
DD = 3.6 V
V
DD = 8.4 V
12.5
10.0
7.5
30.0
20.0
10.0
7.2 V
2.4 V
6.0 V
4.8 V
3.6 V
5.0
1.2 V
1.0 V
2.5
2.4 V
1.2 V
0
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
2.0
4.0
6.0
8.0
10.0
VDS [V]
VDS [V]
7. Nch transistor output current (IOUT
Input voltage (VDD)
)
vs.
8. Pch transistor output current (IOUT
Input voltage (VDD)
) vs.
S-1009N46
4.0
VDS = 0.5 V
S-1009C08
VDS = 0.5 V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Ta = −40°C
Ta = −40°C
3.0
2.0
1.0
+25°C
+25°C
+85°C
+85°C
0
0
1.0
2.0
3.0
4.0
5.0
6.0
0
2
4
6
8
10
V
DD [V]
VDD [V]
Remark VDS: Drain-to-source voltage of the output transistor
21
0.27
S-1009 Series
Rev.5.1_03
9. Minimum operation voltage (VOUT) vs. Input voltage (VDD)
S-1009N08
Pull-up to VDD
S-1009N11
Pull-up to VDD
Pull-up resistance: 100 k
Pull-up resistance: 100 k
1.2
1.0
0.8
0.6
0.4
0.2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Ta = −40°C
+25°C
Ta = −40°C
+25°C
+85°C
+85°C
0
0
0
0
0.2
0.4
0.6
0.8
1.0
0.2 0.4 0.6 0.8 1.0 1.2
VDD [V]
V
DD [V]
S-1009N12
Pull-up to VDD
Pull-up resistance: 100 k
S-1009N46
Pull-up to VDD
Pull-up resistance: 100 k
1.6
1.2
0.8
0.4
6.0
5.0
4.0
3.0
2.0
1.0
Ta = −40°C
Ta = −40°C
+25°C
+25°C
+85°C
+85°C
0
0
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
1.0
2.0
3.0
4.0
5.0
V
DD [V]
VDD [V]
S-1009N08
Pull-up to 10 V
S-1009N11
Pull-up to 10 V
Pull-up resistance: 100 k
Pull-up resistance: 100 k
12.0
10.0
8.0
12.0
10.0
8.0
Ta = −40°C
+25°C
Ta = −40°C
+25°C
+85°C
6.0
6.0
+85°C
4.0
4.0
2.0
2.0
0
0
0
0
0.2
0.4
0.6
0.8
1.0
0.2 0.4 0.6 0.8 1.0 1.2
VDD [V]
VDD [V]
S-1009N12
Pull-up to 10 V
Pull-up resistance: 100 k
S-1009N46
Pull-up to 10 V
Pull-up resistance: 100 k
12.0
10.0
8.0
12.0
10.0
8.0
Ta = −40°C
Ta = −40°C
+25°C
+85°C
6.0
6.0
+25°C
+85°C
4.0
4.0
2.0
2.0
0
0
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
1.0
2.0
3.0
4.0
5.0
V
DD [V]
VDD [V]
22
0.27
Rev.5.1_03
S-1009 Series
10. Dynamic response vs. Output pin capacitance (COUT) (CD pin; open)
S-1009C08
1
S-1009N08
10
tPLH
t
PLH
1
0.1
0.1
0.01
tPHL
t
PHL
0.01
0.001
0.001
0.00001 0.0001
0.001
0.01
0.1
0.1
0.1
0.1
0.00001 0.0001
0.001
0.01
0.1
0.1
0.1
0.1
Output pin capacitance [μF]
Output pin capacitance [μF]
S-1009C11
1
S-1009N11
10
tPLH
t
PLH
1
0.1
0.1
0.01
tPHL
tPHL
0.01
0.001
0.001
0.00001 0.0001
0.001
0.01
0.00001 0.0001
0.001
0.01
Output pin capacitance [μF]
Output pin capacitance [μF]
S-1009C12
1
S-1009N12
10
tPLH
t
PLH
1
0.1
0.1
0.01
tPHL
tPHL
0.01
0.001
0.001
0.00001 0.0001
0.001
0.01
0.00001 0.0001
0.001
0.01
Output pin capacitance [μF]
Output pin capacitance [μF]
S-1009C46
1
S-1009N46
10
t
PLH
tPLH
1
0.1
0.1
0.01
tPHL
tPHL
0.01
0.001
0.001
0.00001 0.0001
0.001
0.01
0.00001 0.0001
0.001
0.01
Output pin capacitance [μF]
Output pin capacitance [μF]
23
0.27
S-1009 Series
Rev.5.1_03
1 s
1 s
*1
VIH
Input voltage
R*1
*2
VDD
100 k
VIL
VDD
tPHL
tPLH
OUT
CD
*1
V
VDD*3 90%
*3
VSS
VDD1
VDD
COUT
V
Output voltage
VDD*3 10%
*1. R and VDD1 are unnecessary for CMOS output
product.
*1. VIH = 10 V
*2. VIL = 0.7 V
*3. CMOS output product: VDD
Nch open-drain product: VDD1
Figure 24 Test Condition of Response Time
Figure 25 Test Circuit of Response Time
Caution 1. The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. When the CD pin is open, a double pulse may appear at release.
To avoid the double pulse, attach 100 pF or more capacitor to the CD pin.
Response time when detecting (tPHL) is not affected by CD pin capacitance. Besides, response
time when releasing (tPLH) can be set the delay time by attaching the CD pin.
Refer to "11. Delay time (tD) vs. CD pin capacitance (CD) (without output pin capacitance)" for
details.
11. Delay time (tD) vs. CD pin capacitance (CD) (without output pin capacitance)
S-1009N08
10000
Ta = 25°C
S-1009N11
10000
Ta = 25°C
1000
100
10
1000
100
10
1
1
0.1
0.1
0.1
1
10
[nF]
100
1000
0.1
1
10
[nF]
100
1000
CD
CD
S-1009N12
10000
Ta = 25°C
S-1009N46
10000
Ta = 25°C
1000
100
10
1000
100
10
1
1
0.1
0.1
0.1
1
10
[nF]
100
1000
0.1
1
10
[nF]
100
1000
CD
CD
24
0.27
Rev.5.1_03
S-1009 Series
12. Delay time (tD) vs. Temperature (Ta)
S-1009N08
50
CD = 4.7 nF
S-1009N11
50
CD = 4.7 nF
40
30
20
10
0
40
30
20
10
0
−
40
−
25
0
25
50
75 85
−
40
−
25
0
25
50
75 85
Ta [°C]
Ta [°C]
S-1009N12
50
CD = 4.7 nF
S-1009N46
50
CD = 4.7 nF
40
30
20
10
0
40
30
20
10
0
−
40
−
25
0
25
50
75 85
−
40
−
25
0
25
50
75 85
Ta [°C]
Ta [°C]
1 s
*1
VIH
R*1
100 k
VDD
Input voltage
VDD OUT
V
*2
VSS
CD
VIL
tD
V
CD
VDD 90%
Output voltage
VSS
*1. R is unnecessary for CMOS output product.
*1. VIH = 10 V
*2. VIL = 0.7 V
Figure 26 Test Condition for Delay Time
Figure 27 Test Circuit for Delay Time
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
25
0.27
S-1009 Series
Rev.5.1_03
Application Circuit Examples
1. Microcomputer reset circuits
In microcomputers, when the power supply voltage is lower than the guaranteed operation voltage, an unspecified
operation may be performed or the contents of the memory register may be lost. When power supply voltage
returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may
malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched
off or lowered.
Using the S-1009 Series which has the low operation voltage, a high accuracy detection voltage and hysteresis,
reset circuits can be easily constructed as seen in Figure 28 and Figure 29.
VDD1
VDD2
VDD
S-1009N
Microcomputer
S-1009C
Microcomputer
VSS
VSS
Figure 28 Example of Reset Circuit
(CMOS Output Product)
Figure 29 Example of Reset Circuit
(Nch Open-drain Output Product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
26
0.27
Rev.5.1_03
S-1009 Series
2. Power-on reset circuit (Nch open-drain output product only)
A power-on reset circuit can be constructed using the S-1009N Series.
VDD
Di*2
VIN
R
100 k
*1
RA
(RA 100 k)
S-1009N
OUT
(Nch open-drain output product)
C
VSS
*1. RA should be 100 k or less to prevent oscillation.
*2. Diode (Di) instantaneously discharges the charge stored in the capacitor (C) at the power falling. Di can be
removed when the delay of the falling time is not important.
Figure 30
VDD
[V]
OUT
[V]
t [s]
t [s]
Figure 31
Remark When the power rises sharply, the output may instantaneously be set to the "H" level due to the IC’s
indefinite area (the output voltage is indefinite when it is the IC’s minimum operation voltage or less),
as seen in Figure 32.
VDD
[V]
OUT
[V]
t [s]
t [s]
Figure 32
Caution 1. The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. Note that the hysteresis width may be larger as the following equation shows when using the
above connection. Perform thorough evaluation using the actual application to set the
constant.
Maximum hysteresis width = VHYS RA 20 A
27
0.27
S-1009 Series
Rev.5.1_03
3. Change of detection voltage (Nch open-drain output product only)
If there is not a product with a specified detection voltage value in the S-1009N Series, the detection voltage can be
changed by using a resistance divider or a diode, as seen in Figure 33 and Figure 34.
In Figure 33, hysteresis width also changes.
VDD
VDD
R
Vf1
R
*1
RA
100 k
100 k
(RA 100 k)
VIN
VIN
OUT
S-1009N
OUT
S-1009N
(Nch open-drain
output product)
(Nch open-drain
ouput product)
RB
VSS
VSS
RA RB
Detection voltage = Vf1 (VDET
)
Detection voltage =
Hysteresis width =
VDET
VHYS
RB
RA RB
RB
*1. RA should be 100 k or less to prevent oscillation.
Caution If RA and RB are large, the hysteresis width
may also be larger than the value given by
the above equation due to the feed-through
current.
Figure 33
Figure 34
Caution 1. The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. Note that the hysteresis width may be larger as the following equation shows when using the
above connections. Perform thorough evaluation using the actual application to set the
constant.
RA RB
Maximum hysteresis width =
VHYSRA 20 A
RB
28
0.27
Rev.5.1_03
S-1009 Series
Marking Specifications
1. SOT-23-5
Top view
(1) to (3):
(4):
Product code (refer to Product name vs. Product code)
Lot number
5
4
(1) (2) (3) (4)
1
2
3
Product name vs. Product code
1. 1 Nch open-drain output product
1. 2 CMOS output product
Product Code
Product Code
Product Name
Product Name
(1)
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
(2)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
(3)
A
B
C
D
E
F
(1)
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
(2)
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
(3)
A
B
C
D
E
F
G
H
I
S-1009N08I-M5T1U
S-1009N09I-M5T1U
S-1009N10I-M5T1U
S-1009N11I-M5T1U
S-1009N12I-M5T1U
S-1009N13I-M5T1U
S-1009N14I-M5T1U
S-1009N15I-M5T1U
S-1009N16I-M5T1U
S-1009N17I-M5T1U
S-1009N18I-M5T1U
S-1009N19I-M5T1U
S-1009N20I-M5T1U
S-1009N21I-M5T1U
S-1009N22I-M5T1U
S-1009N23I-M5T1U
S-1009N24I-M5T1U
S-1009N25I-M5T1U
S-1009N26I-M5T1U
S-1009N27I-M5T1U
S-1009N28I-M5T1U
S-1009N29I-M5T1U
S-1009N30I-M5T1U
S-1009N31I-M5T1U
S-1009N32I-M5T1U
S-1009N33I-M5T1U
S-1009N34I-M5T1U
S-1009N35I-M5T1U
S-1009N36I-M5T1U
S-1009N37I-M5T1U
S-1009N38I-M5T1U
S-1009N39I-M5T1U
S-1009N40I-M5T1U
S-1009N41I-M5T1U
S-1009N42I-M5T1U
S-1009N43I-M5T1U
S-1009N44I-M5T1U
S-1009N45I-M5T1U
S-1009N46I-M5T1U
S-1009C08I-M5T1U
S-1009C09I-M5T1U
S-1009C10I-M5T1U
S-1009C11I-M5T1U
S-1009C12I-M5T1U
S-1009C13I-M5T1U
S-1009C14I-M5T1U
S-1009C15I-M5T1U
S-1009C16I-M5T1U
S-1009C17I-M5T1U
S-1009C18I-M5T1U
S-1009C19I-M5T1U
S-1009C20I-M5T1U
S-1009C21I-M5T1U
S-1009C22I-M5T1U
S-1009C23I-M5T1U
S-1009C24I-M5T1U
S-1009C25I-M5T1U
S-1009C26I-M5T1U
S-1009C27I-M5T1U
S-1009C28I-M5T1U
S-1009C29I-M5T1U
S-1009C30I-M5T1U
S-1009C31I-M5T1U
S-1009C32I-M5T1U
S-1009C33I-M5T1U
S-1009C34I-M5T1U
S-1009C35I-M5T1U
S-1009C36I-M5T1U
S-1009C37I-M5T1U
S-1009C38I-M5T1U
S-1009C39I-M5T1U
S-1009C40I-M5T1U
S-1009C41I-M5T1U
S-1009C42I-M5T1U
S-1009C43I-M5T1U
S-1009C44I-M5T1U
S-1009C45I-M5T1U
S-1009C46I-M5T1U
G
H
I
J
K
L
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
A
B
C
D
E
F
G
H
I
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
A
B
C
D
E
F
G
H
I
J
K
L
J
K
L
M
M
29
0.27
S-1009 Series
Rev.5.1_03
2. SC-82AB
Top view
(1) to (3):
Product code (refer to Product name vs. Product code)
4
3
(1) (2) (3)
1
2
Product name vs. Product code
2. 1 Nch open-drain output product
2. 2 CMOS output product
Product Code
Product Code
Product Name
Product Name
(1)
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
(2)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
(3)
A
B
C
D
E
F
(1)
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
(2)
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
(3)
A
B
C
D
E
F
G
H
I
S-1009N08I-N4T1U
S-1009N09I-N4T1U
S-1009N10I-N4T1U
S-1009N11I-N4T1U
S-1009N12I-N4T1U
S-1009N13I-N4T1U
S-1009N14I-N4T1U
S-1009N15I-N4T1U
S-1009N16I-N4T1U
S-1009N17I-N4T1U
S-1009N18I-N4T1U
S-1009N19I-N4T1U
S-1009N20I-N4T1U
S-1009N21I-N4T1U
S-1009N22I-N4T1U
S-1009N23I-N4T1U
S-1009N24I-N4T1U
S-1009N25I-N4T1U
S-1009N26I-N4T1U
S-1009N27I-N4T1U
S-1009N28I-N4T1U
S-1009N29I-N4T1U
S-1009N30I-N4T1U
S-1009N31I-N4T1U
S-1009N32I-N4T1U
S-1009N33I-N4T1U
S-1009N34I-N4T1U
S-1009N35I-N4T1U
S-1009N36I-N4T1U
S-1009N37I-N4T1U
S-1009N38I-N4T1U
S-1009N39I-N4T1U
S-1009N40I-N4T1U
S-1009N41I-N4T1U
S-1009N42I-N4T1U
S-1009N43I-N4T1U
S-1009N44I-N4T1U
S-1009N45I-N4T1U
S-1009N46I-N4T1U
S-1009C08I-N4T1U
S-1009C09I-N4T1U
S-1009C10I-N4T1U
S-1009C11I-N4T1U
S-1009C12I-N4T1U
S-1009C13I-N4T1U
S-1009C14I-N4T1U
S-1009C15I-N4T1U
S-1009C16I-N4T1U
S-1009C17I-N4T1U
S-1009C18I-N4T1U
S-1009C19I-N4T1U
S-1009C20I-N4T1U
S-1009C21I-N4T1U
S-1009C22I-N4T1U
S-1009C23I-N4T1U
S-1009C24I-N4T1U
S-1009C25I-N4T1U
S-1009C26I-N4T1U
S-1009C27I-N4T1U
S-1009C28I-N4T1U
S-1009C29I-N4T1U
S-1009C30I-N4T1U
S-1009C31I-N4T1U
S-1009C32I-N4T1U
S-1009C33I-N4T1U
S-1009C34I-N4T1U
S-1009C35I-N4T1U
S-1009C36I-N4T1U
S-1009C37I-N4T1U
S-1009C38I-N4T1U
S-1009C39I-N4T1U
S-1009C40I-N4T1U
S-1009C41I-N4T1U
S-1009C42I-N4T1U
S-1009C43I-N4T1U
S-1009C44I-N4T1U
S-1009C45I-N4T1U
S-1009C46I-N4T1U
G
H
I
J
K
L
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
A
B
C
D
E
F
G
H
I
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
A
B
C
D
E
F
G
H
I
J
K
L
J
K
L
M
M
30
0.27
Rev.5.1_03
S-1009 Series
3. SNT-4A
Top view
(1) to (3):
Product code (refer to Product name vs. Product code)
1
2
4
3
(1) (2) (3)
Product name vs. Product code
3. 1 Nch open-drain output product
Product Code
3. 2
CMOS output product
Product Code
(1) (3)
Product Name
Product Name
(1)
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
(2)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
(3)
A
B
C
D
E
F
(2)
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
S-1009N08I-I4T1U
S-1009N09I-I4T1U
S-1009N10I-I4T1U
S-1009N11I-I4T1U
S-1009N12I-I4T1U
S-1009N13I-I4T1U
S-1009N14I-I4T1U
S-1009N15I-I4T1U
S-1009N16I-I4T1U
S-1009N17I-I4T1U
S-1009N18I-I4T1U
S-1009N19I-I4T1U
S-1009N20I-I4T1U
S-1009N21I-I4T1U
S-1009N22I-I4T1U
S-1009N23I-I4T1U
S-1009N24I-I4T1U
S-1009N25I-I4T1U
S-1009N26I-I4T1U
S-1009N27I-I4T1U
S-1009N28I-I4T1U
S-1009N29I-I4T1U
S-1009N30I-I4T1U
S-1009N31I-I4T1U
S-1009N32I-I4T1U
S-1009N33I-I4T1U
S-1009N34I-I4T1U
S-1009N35I-I4T1U
S-1009N36I-I4T1U
S-1009N37I-I4T1U
S-1009N38I-I4T1U
S-1009N39I-I4T1U
S-1009N40I-I4T1U
S-1009N41I-I4T1U
S-1009N42I-I4T1U
S-1009N43I-I4T1U
S-1009N44I-I4T1U
S-1009N45I-I4T1U
S-1009N46I-I4T1U
S-1009C08I-I4T1U
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
A
B
C
D
E
F
G
H
I
S-1009C09I-I4T1U
S-1009C10I-I4T1U
S-1009C11I-I4T1U
S-1009C12I-I4T1U
S-1009C13I-I4T1U
S-1009C14I-I4T1U
S-1009C15I-I4T1U
S-1009C16I-I4T1U
S-1009C17I-I4T1U
S-1009C18I-I4T1U
S-1009C19I-I4T1U
S-1009C20I-I4T1U
S-1009C21I-I4T1U
S-1009C22I-I4T1U
S-1009C23I-I4T1U
S-1009C24I-I4T1U
S-1009C25I-I4T1U
S-1009C26I-I4T1U
S-1009C27I-I4T1U
S-1009C28I-I4T1U
S-1009C29I-I4T1U
S-1009C30I-I4T1U
S-1009C31I-I4T1U
S-1009C32I-I4T1U
S-1009C33I-I4T1U
S-1009C34I-I4T1U
S-1009C35I-I4T1U
S-1009C36I-I4T1U
S-1009C37I-I4T1U
S-1009C38I-I4T1U
S-1009C39I-I4T1U
S-1009C40I-I4T1U
S-1009C41I-I4T1U
S-1009C42I-I4T1U
S-1009C43I-I4T1U
S-1009C44I-I4T1U
S-1009C45I-I4T1U
S-1009C46I-I4T1U
G
H
I
J
K
L
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
A
B
C
D
E
F
G
H
I
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
A
B
C
D
E
F
G
H
I
J
K
L
J
K
L
M
M
31
2.9±0.2
1.9±0.2
4
5
+0.1
-0.06
1
2
3
0.16
0.95±0.1
0.4±0.1
No. MP005-A-P-SD-1.3
TITLE
SOT235-A-PKG Dimensions
MP005-A-P-SD-1.3
No.
ANGLE
UNIT
mm
ABLIC Inc.
4.0±0.1(10 pitches:40.0±0.2)
+0.1
-0
2.0±0.05
0.25±0.1
ø1.5
+0.2
-0
4.0±0.1
ø1.0
1.4±0.2
3.2±0.2
3
4
2 1
5
Feed direction
No. MP005-A-C-SD-2.1
TITLE
SOT235-A-Carrier Tape
MP005-A-C-SD-2.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. MP005-A-R-SD-1.1
TITLE
SOT235-A-Reel
MP005-A-R-SD-1.1
No.
ANGLE
UNIT
QTY.
3,000
mm
ABLIC Inc.
2.0±0.2
1.3±0.2
4
3
0.05
+0.1
-0.06
0.16
2
1
+0.1
-0.05
0.4
+0.1
-0.05
0.3
No. NP004-A-P-SD-2.0
TITLE
No.
SC82AB-A-PKG Dimensions
NP004-A-P-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
2.0±0.05
+0.1
-0
1.1±0.1
ø1.5
4.0±0.1
4.0±0.1
0.2±0.05
ø1.05±0.1
(0.7)
2.2±0.2
2
3
1
4
Feed direction
No. NP004-A-C-SD-3.0
SC82AB-A-Carrier Tape
NP004-A-C-SD-3.0
TITLE
No.
ANGLE
UNIT
mm
ABLIC Inc.
1.1±0.1
+0.1
-0
2.0±0.1
4.0±0.1
ø1.5
0.2±0.05
4.0±0.1
ø1.05±0.1
2.3±0.15
2
3
1
4
Feed direction
No. NP004-A-C-S1-2.0
TITLE
SC82AB-A-Carrier Tape
NP004-A-C-S1-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. NP004-A-R-SD-1.1
TITLE
No.
SC82AB-A-Reel
NP004-A-R-SD-1.1
QTY.
ANGLE
UNIT
3,000
mm
ABLIC Inc.
1.2±0.04
3
4
+0.05
-0.02
0.08
2
1
0.65
0.48±0.02
0.2±0.05
No. PF004-A-P-SD-6.0
TITLE
SNT-4A-A-PKG Dimensions
PF004-A-P-SD-6.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
-0
ø1.5
4.0±0.1
2.0±0.05
0.25±0.05
+0.1
ø0.5
-0
4.0±0.1
0.65±0.05
1.45±0.1
2
3
1
4
Feed direction
No. PF004-A-C-SD-2.0
TITLE
SNT-4A-A-Carrier Tape
PF004-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PF004-A-R-SD-1.0
SNT-4A-A-Reel
TITLE
No.
PF004-A-R-SD-1.0
QTY.
5,000
ANGLE
UNIT
mm
ABLIC Inc.
0.52
2
1.16
0.52
1
0.3
0.35
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.10 mm ~ 1.20 mm)
0.03 mm
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.10 mm to 1.20 mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
(0.25 mm min. / 0.30 mm typ.)
(1.10 mm ~ 1.20 mm)
1.
2.
SNT-4A-A
-Land Recommendation
TITLE
No.
PF004-A-L-SD-4.1
ANGLE
UNIT
No. PF004-A-L-SD-4.1
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5. When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9. Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
14. For more details on the information described herein, contact our sales office.
2.2-2018.06
www.ablic.com
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