S-8203AAB-TCT1U [ABLIC]
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK;
| 型号： | S-8203AAB-TCT1U |
| 厂家： | 
ABLIC |
| 描述： | BATTERY PROTECTION IC FOR 3-SERIES CELL PACK |
| 文件： | 总30页 (文件大小：696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S-8203A Series
BATTERY PROTECTION IC
FOR 3-SERIES CELL PACK
www.ablic.com
© ABLIC Inc., 2016-2019
Rev.1.1_00
The S-8203A Series includes high-accuracy voltage detection circuits and delay circuits, in single use, makes it possible for
users to monitor the status of 3-series cell lithium-ion rechargeable battery.
The S-8203A Series is suitable for protecting lithium-ion rechargeable battery pack from overcharge, overdischarge, and
overcurrent.
Features
• High-accuracy voltage detection function for each cell
Overcharge detection voltage n (n = 1 to 3)
Overcharge release voltage n (n = 1 to 3)
Overdischarge detection voltage n (n = 1 to 3)
Overdischarge release voltage n (n = 1 to 3)
• Discharge overcurrent detection in 2-step
Discharge overcurrent detection voltage
Short-circuiting detection voltage
3.55 V to 4.50 V*1 (50 mV step)
3.30 V to 4.50 V*2
2.0 V to 3.2 V*1 (100 mV step)
2.0 V to 3.4 V*3
Accuracy 25 mV
Accuracy 50 mV
Accuracy 80 mV
Accuracy 100 mV
0.05 V to 0.30 V*4 (50 mV step)
0.50 V to 1.0 V*4 (100 mV step)
Accuracy 15 mV
Accuracy 100 mV
• Charge overcurrent detection function
Charge overcurrent detection voltage
−0.30 V to −0.05 V (50 mV step) Accuracy 30 mV
• Settable by external capacitor; overcharge detection delay time, overdischarge detection delay time, discharge
overcurrent detection delay time, charge overcurrent detection delay time
(Load short-circuiting detection delay time is internally fixed.)
• Independent charge and discharge control by the control pins
• 0 V battery charge:
Enabled, inhibited
• Power-down function:
Available, unavailable
Absolute maximum rating 28 V
2 V to 24 V
• High-withstand voltage:
• Wide operation voltage range:
• Wide operation temperature range:
• Low current consumption
During operation:
During power-down:
• Lead-free (Sn 100%), halogen-free
Ta = −40°C to +85°C
40 μA max. (Ta = +25°C)
0.1 μA max. (Ta = +25°C)
*1. The overcharge detection voltage n (n = 1 to 3) and overdischarge detection voltage (n = 1 to 3) cannot be selected if
the voltage difference between them is 0.6 V or lower.
*2. Overcharge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV step.
(Overcharge hysteresis voltage = Overcharge detection voltage − Overcharge release voltage)
*3. Overdischarge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.2 V to 0.7 V in 100 mV
step.
(Overdischarge hysteresis voltage = Overdischarge release voltage − Overdischarge detection voltage)
*4. The discharge overcurrent detection voltage and load short-circuiting detection voltage cannot be selected if the
voltage difference between them is 0.3 V or lower.
Application
• Rechargeable lithium-ion battery pack
Package
• 16-Pin TSSOP
1
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Block Diagram
Control circuit
RVMD
VM
RVMS
VDD
VC1
Delay circuit
Delay circuit
Delay circuit
Delay circuit
Delay circuit
Overcharge 1
−
+
Overdisacharge 1
+
CO
DO
−
VC2
VC3
Overcharge 2
−
+
Overdisacharge 2
+
−
Overcharge 3
−
+
+
−
VINI
Overdisacharge 3
+
Discharge
−
overcurren
t
+
−
VC4
NPI
short-circuiting
+
−
Charge
overcurrent
RCTLC
CTLC
CTLD
VSS
CIT
RCTLD
CCT
CDT
Remark Diodes in the figure are parasitic diodes.
Figure 1
2
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Product Name Structure
1. Product name
S-8203A xx
-
TCT1
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
TCT1: 16-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Code
Package Name
16-Pin TSSOP
Dimension
Tape
Reel
FT016-A-P-SD
FT016-A-C-SD
FT016-A-R-S1
3
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
3. Product name list
Table 2
Discharge Load Short-
Charge
Overcurrent
Detection
Voltage
Overcharge Overcharge Overdischarge Overdischarge
Overcurrent
Detection
Voltage
circuiting
Detection
Voltage
0 V
Power-
Delay
Detection
Voltage
Release
Voltage
Detection
Voltage
Release
Voltage
Product Name
Battery
Charge
down
Time*1
Function
[VCU
]
[VCL
]
[VDL
]
[VDU]
[VDIOV
]
[VSHORT
0.50 V
0.50 V
0.50 V
0.50 V
0.50 V
0.50 V
0.50 V
0.50 V
0.50 V
0.50 V
0.50 V
]
[VCIOV]
S-8203AAA-TCT1U
S-8203AAB-TCT1U
S-8203AAC-TCT1U
S-8203AAD-TCT1U
S-8203AAE-TCT1U
S-8203AAF-TCT1U
S-8203AAG-TCT1U
S-8203AAH-TCT1U
S-8203AAI-TCT1U
S-8203AAJ-TCT1U
S-8203AAK-TCT1U
4.250 V
4.250 V
4.250 V
4.250 V
4.350 V
4.350 V
4.425 V
3.650 V
3.750 V
4.425 V
4.250 V
4.150 V
4.150 V
4.150 V
4.100 V
4.150 V
4.150 V
4.225 V
3.500 V
3.600 V
4.225 V
4.150 V
2.70 V
2.50 V
2.50 V
3.00 V
2.40 V
2.80 V
2.50 V
2.20 V
2.00 V
2.80 V
2.50 V
3.00 V
3.00 V
3.00 V
3.20 V
3.00 V
3.00 V
2.90 V
2.30 V
2.50 V
3.00 V
3.00 V
0.20 V
0.10 V
0.10 V
0.15 V
0.15 V
0.20 V
0.15 V
0.10 V
0.15 V
0.15 V
0.10 V
−
−
−
−
−
−
−
−
−
−
−
0.10 V
0.05 V
0.05 V
0.10 V
0.10 V
0.10 V
0.10 V
0.05 V
0.10 V
0.10 V
0.05 V
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Inhibited
Available
Available
Unavailable
Available
Available
Available
Available
Available
Available
Available
Available
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
*1. The delay time is set by the external capacitor.
But the discharge overcurrent release delay time (tDIOVR) and charge overcurrent release delay time (tCIOVR) are
calculated by discharge overcurrent detection delay time (tDIOV) and charge overcurrent detection delay time (tCIOV) as the
following equations. 1 [ms] (typ.) is the internal delay time of the S-8203A Series.
(1) tDIOVR = tDIOV × 10 + 1 [ms] (typ.), tCIOVR = tCIOV × 10 + 1 [ms] (typ.)
(2) tDIOVR = tDIOV × 0.05 + 1 [ms] (typ.), tCIOVR = tCIOV × 0.05 + 1 [ms] (typ.)
Moreover, refer to "7. Delay time setting" in " Operation" for calculational methods of delay times.
Remark Please contact our sales representatives for products other than the above.
4
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 2
Table 3
Pin No.
1
Symbol
Description
VM
CO
Voltage detection pin between VSS pin and VM pin
FET gate connection pin for charge control (Pch open-drain output)
Pin for voltage detection between VSS pin and CO pin
FET gate connection pin for discharge control (CMOS output)
Voltage detection pin between VSS pin and VINI pin
Control pin for charge FET
2
3
4
5
6
7
8
DO
VINI
CTLC
CTLD
CCT
CDT
Control pin for discharge FET
Capacitor connection pin for delay for overcharge detection voltage
Capacitor connection pin for delay for overdischarge detection voltage
Capacitor connection pin for delay for discharge overcurrent detection,
charge overcurrent detection
9
CIT
10
11
VSS
NPI
Input pin for negative power supply*1
Input pin for negative power supply*1
Connection pin for battery 3's negative voltage
Input pin for negative power supply
12
13
VC4
VC3
Connection pin for battery 2's negative voltage
Connection pin for battery 3's positive voltage
Connection pin for battery 1's negative voltage
Connection pin for battery 2's positive voltage
Connection pin for battery 1's positive voltage
Input pin for positive power supply
14
15
16
VC2
VC1
VDD
Connection pin for battery 1's positive voltage
*1. Be sure to short the VSS pin and the NPI pin when using them.
5
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Absolute Maximum Ratings
Table 4
(Ta = +25°C unless otherwise specified)
Item
Symbol
VDS
Applied Pin
Absolute Maximum Rating
Unit
Input voltage between VDD pin and
VSS pin
VDD
VSS − 0.3 to VSS + 28
V
VC1, VC2, VC3, VC4, NPI,
CTLC, CTLD, CCT, CDT, CIT
Input pin voltage 1
VIN1
VSS − 0.3 to VDD + 0.3
V
Input pin voltage 2
VIN2
VDO
VCO
PD
VM, VINI
VDD − 28 to VDD + 0.3
VSS − 0.3 to VDD + 0.3
VDD − 28 to VDD + 0.3
1100*1
V
V
DO pin output voltage
CO pin input and output voltage
Power dissipation
DO
CO
−
V
mW
°C
°C
Operation ambient temperature
Storage temperature
Topr
Tstg
−
−
−40 to +85
−40 to +125
*1. When mounted on board
[Mounted board]
(1) Board size:
(2) Board name: JEDEC STANDARD51-7
114.3 mm × 76.2 mm × t1.6 mm
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
1200
1000
800
600
400
200
0
0
50
Ambient Temperature (Ta) [°C]
Figure 3 Power Dissipation of Package (When Mounted on Board)
100
150
6
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Electrical Characteristics
Table 5 (1 / 2)
(Ta = +25°C unless otherwise specified)
Test
Circuit
Item
Detection Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
Overcharge detection voltage n
(n = 1, 2, 3)
VCU
− 0.025
VCL
− 0.05
VDL
VCU
+ 0.025
VCL
+ 0.05
VDL
VCUn
VCLn
V1 = V2 = V3 = VCU − 0.05 V
VCU
VCL
V
V
V
V
V
V
V
2
2
2
2
2
2
2
Overcharge release voltage n
(n = 1, 2, 3)
−
−
−
−
−
−
Overdischarge detection voltage n
(n = 1, 2, 3)
VDLn
VDL
− 0.08
VDU
+ 0.08
VDU
Overdischarge release voltage n
(n = 1, 2, 3)
VDUn
VDIOV
VSHORT
VCIOV
VDU
− 0.10
VDIOV
− 0.015
VSHORT
− 0.10
VCIOV
− 0.03
−1.0
+ 0.10
VDIOV
+ 0.015
VSHORT
+ 0.10
VCIOV
+ 0.03
1.0
Discharge overcurrent detection
voltage
VDIOV
VSHORT
VCIOV
Load short-circuiting detection
voltage
Charge overcurrent detection
voltage
Temperature coefficient 1*1
Temperature coefficient 2*2
Delay Time Function*4
TCOE1
TCOE2
Ta = 0°C to +50°C*3
Ta = 0°C to +50°C*3
0
0
mV/°C
mV/°C
−
−
−0.5
0.5
RCCT
RCDT
RCIT
3
3
3
MΩ
kΩ
kΩ
CCT pin internal resistance
CDT pin internal resistance
CIT pin internal resistance
V1 = 4.5 V, V2 = V3 = 3.5 V
6.15
615
123
8.31
831
10.2
V1 = 1.5 V, V2 = V3 = 3.5 V
1020
−
166
VDS
204
VDS
VDS
× 0.68
VDS
× 0.68
VDS
VCCT
VCDT
VCIT
V
V
3
3
3
2
CCT pin detection voltage
CDT pin detection voltage
CIT pin detection voltage
V1 = 4.5 V, V2 = V3 = 3.5 V
V1 = 1.5 V, V2 = V3 = 3.5 V
V6 = VDIOV + 0.015 V
−
× 0.70 × 0.72
VDS VDS
× 0.70 × 0.72
VDS VDS
× 0.70 × 0.72
V
× 0.68
Load short-circuiting detection
delay time
tSHORT
100
300
600
μs
CTLC pin response time
CTLD pin response time
0 V Battery Charge
0 V battery charge starting charger
voltage
tCTLC
tCTLD
−
−
−
−
−
−
2.5
2.5
ms
ms
2
2
0 V battery charge enabled
V1 = V2 = V3 = 0 V
V0CHA
V0INH
−
0.8
0.7
1.5
1.1
V
V
4
2
0 V battery charge inhibition battery
voltage
0 V battery charge inhibited
0.4
Internal Resistance
CTLC pin internal resistance
CTLD pin internal resistance
Resistance between
VM pin and VDD pin *5
Resistance between
VM pin and VSS pin
RCTLC
RCTLD
−
−
7
7
10
10
13
13
MΩ
MΩ
5
5
RVMD
RVMS
V1 = V2 = V3 = 1.8 V
450
250
900
500
1800
750
kΩ
kΩ
5
5
−
7
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Table 5 (2 / 2)
(Ta = +25°C unless otherwise specified)
Test
Circuit
Item
Symbol
VDSOP
Condition
Min.
Typ.
Max.
Unit
Input Voltage
Operation voltage between
VDD pin and VSS pin *6
CTLC pin change voltage*6
CTLD pin change voltage*6
Input Current
Fixed output voltage of
DO pin and CO pin
2
−
24
V
−
VCTLC
VCTLD
−
−
2.1
2.1
3.0
3.0
4.0
4.0
V
V
2
2
Current consumption during
operation
IOPE
IPDN
−
−
−
20
40
μA
μA
1
1
Current consumption during
power-down*5
V1 = V2 = V3 = 1.5 V
−
0.1
VC1 pin current
IVC1
IVC2
IVC3
IVC4
−
0
0.8
0
2.0
0.3
0.3
0
μA
μA
μA
μA
5
5
5
5
VC2 pin current
−
−
−
−0.3
−0.3
−2.0
VC3 pin current
0
VC4 pin current
−0.8
Output Current
10
CO pin source current
CO pin leakage current
DO pin source current
DO pin sink current
ICOH
ICOL
IDOH
IDOL
V13 = 0.5 V
−
−
−
−
−
0.1
−
μA
μA
μA
μA
5
5
5
5
V1 = V2 = V3 = 8 V
V14 = 0.5 V
−
10
V15 = 0.5 V
−
−10
*1. Voltage temperature coefficient 1: Overcharge detection voltage
*2. Voltage temperature coefficient 2: Discharge overcurrent detection voltage
*3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by
design, not tested in production.
*4. Refer to " Operation" for details of delay time function.
*5. For products with power-down function
*6. The S-8203A Series does not operate detection if the operation voltage between VDD pin and VSS pin (VDSOP) is CTLC pin
change voltage (VCTLC) or CTLD pin change voltage (VCTLD) or lower.
8
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Test Circuits
1. Current consumption during operation, current consumption during power-down (Test circuit 1)
Set S1 and S2 to OFF.
1. 1 Current consumption during operation (IOPE
)
Set V1 = V2 = V3 = 3.5 V, S2 to ON. ISS is the current consumption during operation (IOPE) at that time.
1. 2 Current consumption during power-down (IPDN) (With power-down function)
Set V1 = V2 = V3 = 1.5 V, S1 to ON. ISS is the current consumption during power-down (IPDN) at that time.
2. Overcharge detection voltage, overcharge release voltage, overdischarge detection voltage,
overdischarge release voltage, discharge overcurrent detection voltage, load short-circuiting
detection voltage, charge overcurrent detection voltage, CTLC pin change voltage, CTLD pin
change voltage, load short-circuiting detection delay time, CTLC pin response time, CTLD pin
response time (Test circuit 2)
Set S3 to OFF.
Confirm both VCO and VDO are in "H" (the voltage level is VDS × 0.9 V or higher) after setting V1 = V2 = V3 = 3.5 V, V6
= V7 = V8 = 0 V (this status is referred to as initial status 1).
2. 1 Overcharge detection voltage (VCU1), Overcharge release voltage (VCL1
)
The overcharge detection voltage (VCU1) is V1 when the VCO is set to "L" (the voltage level is VDS × 0.1 V or lower)
after increasing V1 gradually after setting V1 = V2 = V3 = VCU − 0.05 V from the initial status 1. After that,
decreasing V1 gradually, V1 is the overcharge release voltage (VCL1) when the VCO is set to "H" after setting V2 =
V3 = 3.5 V.
2. 2 Overdischarge detection voltage (VDL1), overdischarge release voltage (VDU1
)
The overdischarge detection voltage (VDL1) is V1 when the VDO is set to "L" after decreasing V1 gradually from the
initial status 1. After that, increasing V1 gradually, V1 is the overdischarge release voltage (VDU1) when VDO is set
to "H".
By changing Vn (n = 2 to 3), users can define the overcharge detection voltage (VCUn), the overcharge release
voltage (VCLn), the overdischarge detection voltage (VDLn), the overdischarge release voltage (VDUn) as well when
n = 1.
2. 3 Discharge overcurrent detection voltage (VDIOV
)
The discharge overcurrent detection voltage (VDIOV) is V6 when VDO is set to "L" after increasing V6 gradually from
the initial status 1.
2. 4 Load short-circuiting detection voltage (VSHORT
)
The load short-circuiting detection voltage (VSHORT) is V6 when VDO is set to "L" after increasing V6 gradually after
setting S3 to ON from the initial status 1.
2. 5 Charge overcurrent detection voltage (VCIOV
)
The charge overcurrent detection voltage (VCIOV) is V6 when VCO is set to "L" after decreasing V6 gradually from
the initial status 1.
2. 6 CTLC pin change voltage (VCTLC
)
The CTLC pin change voltage (VCTLC) is V7 when VCO is set to "L" after increasing V7 gradually from the initial
status 1.
2. 7 CTLD pin change voltage (VCTLD
)
The CTLD pin change voltage (VCTLD) is V8 when VDO is set to "L" after increasing V8 gradually from the initial
status 1.
2. 8 Load short-circuiting detection delay time (tSHORT
)
Load short-circuiting detection delay time (tSHORT) is a period in which VDO changes to "L" after changing V6 to
1.5 V instantaneously, after setting S3 to ON from the initial status 1.
9
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
2. 9 CTLC pin response time (tCTLC
)
CTLC pin response time (tCTLC) is a period in which VCO changes to "L" after changing V7 = VDS instantaneously
from the initial status 1.
2. 10 CTLD pin response time (tCTLD
)
CTLD pin response time (tCTLD) is a period in which VDO changes to "L" after changing V8 = VDS instantaneously
from the initial status 1.
3. CCT pin internal resistance, CDT pin internal resistance, CIT pin internal resistance, CCT pin
detection voltage, CDT pin detection voltage, CIT pin detection voltage (Test circuit 3)
Confirm both VCO and VDO are in "H" after setting V1 = V2 = V3 = 3.5 V, V6 = V9 = V10 = V11 = 0 V (this status is
referred to as initial status 2).
3. 1 CCT pin internal resistance (RCCT
)
The CCT pin internal resistance (RCCT) can be defined by RCCT = VDS / ICCT by using ICCT when setting V1 = 4.5 V
from the initial status 2.
3. 2 CDT pin internal resistance (RCDT
)
The CDT pin internal resistance (RCDT) can be defined by RCDT = VDS / ICDT by using ICDT when setting V1 = 1.5 V
from the initial status 2.
3. 3 CIT pin internal resistance (RCIT
)
The CIT pin internal resistance (RCIT) can be defined by RCIT = VDS / ICIT by using ICIT when setting V6 = VDIOV
0.015 V from the initial status 2.
+
3. 4 CCT pin detection voltage (VCCT
)
The CCT pin detection voltage (VCCT) is V9 when VCO is set to "L" after increasing V9 gradually, after setting V1 =
4.5 V from the initial status 2.
3. 5 CDT pin detection voltage (VCDT
)
The CDT pin detection voltage (VCDT) is V10 when VDO is set to "L" after increasing V10 gradually, after setting V1
= 1.5 V from the initial status 2.
3. 6 CIT pin detection voltage (VCIT
)
The CIT pin detection voltage (VCIT) is V11 when VDO is set to "L" after increasing V11 gradually, after setting V6 =
VDIOV + 0.015 V from the initial status 2.
10
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
4. 0 V battery charge starting charger voltage (0 V battery charge enabled) (Test circuit 4), 0 V
battery charge inhibition battery voltage (0 V battery charge inhibited) (Test circuit 2)
4. 1 0 V battery charge starting charger voltage (V0CHA) (0 V battery charge enabled)
The 0 V battery charge starting charger voltage (V0CHA) is V12 when VCO is 0.1 V or higher after increasing
V12 gradually after setting V1 = V2 = V3 = 0 V, V12 = 0 V.
4. 2 0 V Battery charge inhibition battery voltage (V0INH) (0 V battery charge inhibited)
The 0 V battery charge inhibition battery voltage (V0INH) is V1 when VCO is set to "L" after decreasing V1
gradually from the initial status 1.
5. CTLC pin internal resistance, CTLD pin internal resistance, resistance between VM pin and
VDD pin, resistance between VM pin and VSS pin, VC1 pin current, VC2 pin current, VC3 pin
current, VC4 pin current, CO pin source current, CO pin leakage current, DO pin source
current, DO pin sink current (Test circuit 5)
Set S1, S5, S6 and S7 to OFF, set S2 and S4 to ON.
Set V1 = V2 = V3 = 3.5 V, V6 = V13 = V14 = V15 = V16 = 0 V (this status is referred to as initial status 3).
5. 1 CTLC pin internal resistance (RCTLC
)
In the initial status 3, the CTLC pin internal resistance (RCTLC) can be defined by RCTLC = VDS / ICTLC by using ICTLC
.
.
5. 2 CTLD pin internal resistance (RCTLD
)
In the initial status 3, the CTLD pin internal resistance (RCTLD) can be defined by RCTLD = VDS / ICTLD by using ICTLD
5. 3 Resistance between VM pin and VDD pin (RVMD) (With power-down function)
The resistance between VM pin and VDD pin (RVMD) can be defined by RVMD = VDS / IVM by using IVM when setting
V1 = V2 = V3 = 1.8 V from the initial status 3.
5. 4 Resistance between VM pin and VSS pin (RVMS
)
The resistance between VM pin and VSS pin (RVMS) can be defined by RVMS = VDS / IVM by using IVM when setting
V6 = 1.5 V, S2 to OFF, S1 to ON from the initial status 3.
5. 5 VC1 pin current (IVC1), VC2 pin current (IVC2), VC3 pin current (IVC3), VC4 pin current (IVC4
)
In the initial status 3, I1 is the VC1 pin current (IVC1), I2 is the VC2 pin current (IVC2), I3 is the VC3 pin current (IVC3),
I4 is the VC4 pin current (IVC4).
5. 6 CO pin source current (ICOH), CO pin leakage current (ICOL
)
The CO pin source current (ICOH) is ICO when setting V13 = 0.5 V from the initial status 3. After that, the CO pin
leakage current (ICOL) is ICO when setting V1 = V2 = V3 = 8 V, S4 to OFF, S5 to ON.
5. 7 DO pin source current (IDOH), DO pin sink current (IDOL
)
The DO pin source current (IDOH) is IDO when setting V14 = 0.5 V, S6 to ON from the initial status 3. After that, the
DO pin sink current (IDOL) is IDO when setting V1 = V2 = V3 = 1.8 V, V15 = 0.5 V, S6 to OFF, S7 to ON.
11
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
S-8203A Series
S-8203A Series
S1
1
2
3
4
5
VM
VDD 16
VC1 15
1
2
3
4
5
6
7
8
VM
VDD 16
VC1 15
CO
V1
R1 = 1 MΩ
S2
CO
VC2
VC3
VC4
NPI
DO
14
13
12
11
10
V1
V2
V3
V2
V3
VC2
VC3
VC4
NPI
DO
14
13
12
11
10
VINI
CTLC
VCO
V
VINI
CTLC
CTLD
CCT
CDT
6 CTLD
7 CCT
8 CDT
VDO
V
VSS
CIT
V6
VSS
CIT
A
9
V7
9
ISS
V8
S3
C1 =
0.1 μF
C1
=
0.1 μF
Figure 4 Test Circuit 1
Figure 5 Test Circuit 2
S-8203A Series
S-8203A Series
V12
VCO
1
2
3
4
5
6
7
8
VM
VDD 16
1
2
3
4
5
6
7
8
VM
VDD 16
15
V
CO
15
14
13
12
11
10
VC1
VC2
VC3
VC4
NPI
CO
VC1
VC2 14
V1
V2
V3
R1 = 1 MΩ
V1
V2
V3
R1 = 1 MΩ
DO
VCO
DO
VINI
CTLC
CTLD
CCT
CDT
V
VC3
VC4
NPI
VINI
CTLC
CTLD
CCT
CDT
13
12
11
10
V
VSS
CIT
VSS
CIT
ICCT
VDO
A
9
9
V6
A
A
ICDT
ICIT
V11
C1
0.1 μF
=
V9
C1
=
V10
0.1 μF
Figure 6 Test Circuit 3
Figure 7 Test Circuit 4
S1 S4 S6
V13
V14
IVM
ICO
IDO
S-8203A Series
1
2
3
4
5
6
7
8
VM
VDD 16
A
A
A
I1
I2
I3
I4
CO
15
14
13
12
11
10
VC1
VC2
VC3
VC4
NPI
A
A
A
A
V1
V2
V3
DO
V15
VINI
CTLC
CTLD
CCT
CDT
ICTLC
A
A
V6
S2
S5
VSS
CIT
ICTLD
S7
9
C1 =
0.1 μF
Figure 8 Test Circuit 5
12
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Operation
Remark Refer to " Connection Example of Battery Protection IC".
1. Normal status
In the S-8203A Series, when the voltage of each of the batteries is in the range from overdischarge detection voltage
(VDLn) to overcharge detection voltage (VCUn), and the VINI pin voltage is in the range from charge overcurrent
detection voltage (VCIOV) to discharge overcurrent detection voltage (VDIOV), both of CO pin and DO pin get the VDD
level. This is the normal status. At this time, the charge and discharge FETs are on.
2. Overcharge status
In the S-8203A Series, when the voltage of one of the batteries increases to the level of higher than VCUn, the CO pin
is set in high impedance. This is the overcharge status. The CO pin is pulled down to EB− by an external resistor so
that the charge FET is turned off and it stops charging.
The overcharge status is released if either condition mentioned below is satisfied;
(1) In case that the CO pin voltage is 1 / 50 × VDS or lower, and the voltage of each of the batteries which are
VCUn or higher is in the level of overcharge release voltage (VCLn) or lower.
(2) In case that the CO pin voltage is 1 / 50 × VDS or higher, and the voltage of each of the batteries is in the level
of VCUn or lower.
3. Overdischarge status
In The S-8203A Series, when the voltage of one of the batteries decreases to the level of VDLn or lower, the DO pin
voltage gets the VSS level. This is the overdischarge status. The discharge FET is turned off and it stops discharging.
The overdischarge status is released if either condition mentioned below is satisfied;
(1) In case that the VM pin voltage is in the level of lower than VSS, and the voltage of each of the batteries is in
the level of VDLn or higher.
(2) In case that the VM pin voltage is VDS / 5 (typ.) or lower and the VM pin voltage is in the level of higher than
VSS, and the voltage of each of the batteries which are VDLn or lower is in the level of overdischarge release
voltage (VDUn) or higher.
3. 1 With power-down function
In The S-8203A Series, when it reaches the overdischarge status, the VM pin is pulled up to the VDD level by a
resistor between VM pin and VDD pin (RVMD). If the VM pin voltage and the CO pin voltage increase to the level of
VDS / 5 (typ.) or higher, respectively, the power-down function starts to operate and almost every circuit in the
S-8203A Series stops working.
The power-down function is released if either condition mentioned below is satisfied;
(1) The VM pin voltage gets VDS / 5 (typ.) or lower.
(2) The CO pin voltage gets VDS / 5 (typ.) or lower.
4. Discharge overcurrent status
The discharging current increases to a certain value or higher. As a result, if the status in which the VINI pin voltage
increases to the level of VDIOV or higher, the DO pin gets the VSS level. This is the discharge overcurrent status. The
discharge control FET is turned off and it stops discharging. In the status of discharge overcurrent, the CO pin is set
in high impedance. The VM pin is pulled down to the VSS level by a resistor between VM pin and VSS pin (RVMS).
The S-8203A Series has two levels for discharge overcurrent detection (VDIOV, VSHORT).
The S-8203A Series' actions against load short-circuiting detection voltage (VSHORT) are as well in VDIOV
.
The discharge overcurrent status is released if the following condition is satisfied.
(1) The VM pin voltage gets VDS / 10 (typ.) or lower.
13
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
5. Charge overcurrent status
In the S-8203A Series, the charge current increases to a certain value or higher. As a result, if the status in which the
VINI pin voltage decreases to the level of VCIOV or lower, the CO pin is set in high impedance. This is the charge
overcurrent status. The charge control FET is turned off and it stops charging. In this charge overcurrent status, DO
pin gets the VSS level. The VM pin is pulled up to the VDD level by resistance between VM pin and VDD pin (RVMD).
The charge overcurrent status is released if the following condition is satisfied.
(1) The CO pin voltage gets 1 / 50 × VDS (typ.) or higher.
6. 0 V Battery charge
In the S-8203A Series, regarding how to charge a discharged battery (0 V battery), users are able to select either
function mentioned below.
(1) Enable to charge a 0 V battery
A 0 V battery is charged when charger voltage is higher than 0 V battery charge starting charger voltage
(V0CHA).
(2) Inhibit charging a 0 V battery
A 0 V battery is not charged when the voltage of one of the batteries is 0 V battery charge inhibition battery
voltage (V0INH) or lower.
Caution When the VDD pin voltage is lower than the minimum value of operation voltage between VDD pin
and VSS pin (VDSOP), the S-8203A Series' action is not assured.
7. Delay time setting
In the S-8203A Series, users are able to set delay time for the period; from detecting the voltage of one of the
batteries or detecting changes in the voltage at the VINI pin, to the output to the CO pin, DO pin. Each delay time is
determined by a resistor in the IC and an external capacitor.
In the overchage detection, when the voltage of one of the batteries gets VCUn or higher, the S-8203A Series starts
charging to the CCT pin's capacitor (CCCT) via the CCT pin's internal resistor (RCCT). After a certain period, the CO pin
is set in high impedance if the voltage at the CCT pin reaches the CCT pin detection voltage (VCCT). This period is
overcharge detection delay time (tCU).
tCU is calculated using the following equation (VDS = V1 + V2 + V3).
t
CU [s] = −ln ( 1 − VCCT / VDS ) × CCCT [μF] × RCCT [MΩ]
= −ln ( 1 − 0.7 (typ.)) × CCCT [μF] × 8.31 [MΩ] (typ.)
= 10.0 [MΩ] (typ.) × CCCT [μF]
Overdischarge detection delay time (tDL), discharge overcurrent detection delay time (tDIOV), charge overcurrent
detection delay time (tCIOV) are calculated using the following equations as well.
tDL [ms] = −ln ( 1 − VCDT / VDS) × CCDT [μF] × RCDT [kΩ]
t
t
DIOV [ms] = −ln ( 1 − VCIT / VDS) × CCIT [μF] × RCIT [kΩ]
CIOV [ms] = −ln ( 1 − VCIT / VDS) × CCIT [μF] × RCIT [kΩ]
In case CCCT = CCDT = CCIT = 0.1 [μF], each delay time tCU, tDL, tDIOV, tCIOV is calculated as follows.
tCU [s] = 10.0 [MΩ] (typ.) × 0.1 [μF] = 1.0 [s] (typ.)
tDL [ms] = 1000 [kΩ] (typ.) × 0.1 [μF] = 100 [ms] (typ.)
tDIOV [ms] = 200 [kΩ] (typ.) × 0.1 [μF] = 20 [ms] (typ.)
tCIOV [ms] = 200 [kΩ] (typ.) × 0.1 [μF] = 20 [ms] (typ.)
Discharge overcurrent release delay time (tDIOVR) and charge overcurrent release delay time (tCIOVR) can be selected
from two types, and they are calculated by tDIOV and tCIOV as the following equations. 1 [ms] (typ.) is the internal delay
time of the S-8203A Series.
(1) tDIOVR = tDIOV × 10 + 1 [ms] (typ.), tCIOVR = tCIOV × 10 + 1 [ms] (typ.)
(2) tDIOVR = tDIOV × 0.05 + 1 [ms] (typ.), tCIOVR = tCIOV × 0.05 + 1 [ms] (typ.)
Load short-circuiting detection delay time (tSHORT) is fixed internally.
14
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
8. CTLC pin and CTLD pin
The S-8203A Series has two pins to control.
The CTLC pin controls the CO pin, the CTLD pin controls the DO pin. Thus it is possible for users to control the CO
pin and DO pin independently. These controls precede the battery protection circuit.
Table 6 Conditions Set by CTLC Pin
CTLC Pin
CO Pin
CTLC pin voltage ≥ VCTLC High-Z
Open*1
High-Z
CTLC pin voltage < VCTLC Normal status*2
*1. Pulled up by RCTLC when CTLC pin is open.
*2. The status is controlled by the voltage detection circuit.
Table 7 Conditions Set by CTLD Pin
CTLD Pin
DO Pin
CTLD pin voltage ≥ VCTLD VSS level
Open*1
VSS level
CTLD pin voltage < VCTLD Normal status*2
*1. Pulled up by RCTLD when CTLD pin is open.
*2. The status is controlled by the voltage detection circuit.
15
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Timing Charts
1. Overcharge detection and overdischarge detection
VCUn
VCLn
Battery voltage
VDUn
VDLn
(n = 1 to 3)
VDD
DO pin voltage
VSS
VDD
CO pin voltage
High-Z
VEB−
VDD
VM pin voltage 1 / 5 × VDD
VSS
VEB−
Charger connection
Load connection
Overcharge detection
delay time (tCU
Overdischarge detection
)
delay time (tDL
)
Status*1
(With power-down function)
(1)
(1)
(2)
(2)
(1)
(1)
(3)
(4)
(3)
(1)
(1)
Status*1
(Without power-down function)
*1. (1): Normal status
(2): Overcharge status
(3): Overdischarge status
(4): Power-down status
Remark The charger is assumed to charge with a constant current. VEB− indicates the open voltage of the charger.
Figure 9
16
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
2. Discharge overcurrent detection
VHC
VCUn
VCLn
Battery voltage
VDUn
VDLn
VHD
(n = 1 to 3)
VDD
DO pin voltage
VSS
VDD
High-Z
High-Z
CO pin voltage
VEB−
VDD
VM pin voltage
VSS
VDD
VSHORT
VINI pin voltage
VDIOV
VSS
Load connection
Discharge overcurrent detection delay
time (tDIOV
Load short circuit detection delay
)
time (tSHORT)
(1)
(1)
(1)
(2)
(2)
Status*1
*1. (1): Normal status
(2): Discharge overcurrent status
Remark The charger is assumed to charge with a constant current. VEB− indicates the open voltage of the charger.
Figure 10
17
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
3. Charge overcurrent detection
VHC
VCUn
VCLn
Battery voltage
VHD
VDUn
VDLn
(n = 1 to 3)
VDD
DO pin voltage
VSS
VDD
High-Z
High-Z
CO pin voltage
VEB−
VDD
VM pin voltage
VINI pin voltage
VSS
VEB−
VDD
VDIOV
VSS
VCIOV
Charger connection
Load connection
Charge overcurrent detection delay
time (tCIOV
Charge overcurrent detection delay
time (tCIOV
)
)
Status*1
(With power-down function)
(4)
(3)
(1)
(1)
(2)
(2)
(1)
(1)
(2)
(2)
(1)
(1)
Status*1
(3)
(Without power-down function)
*1. (1): Normal status
(2): Charge overcurrent status
(3): Overdischarge status
(4): Power-down status
Remark The charger is assumed to charge with a constant current. VEB− indicates the open voltage of the charger.
Figure 11
18
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Connection Example of Battery Protection IC
EB+
RVDD
1 VM
VDD 16
VC1 15
VC2 14
VC3 13
VC4 12
NPI 11
RVC1
RVC2
RVC3
RVC4
CVDD
CVC1
CVC2
CVC3
2 CO
3 DO
4 VINI
S-8203A
RVM
RDO
RVINI
5 CTLC
6 CTLD
7 CCT
8 CDT
RCTLC
RCTLD
VSS 10
CCCT
CCDT
CIT
9
CCIT
RCO
EB−
RSENSE
Charging
FET
Discharging
FET
Figure 12
19
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Application Circuit
EB+
RVDD
1 VM
2 CO
3 DO
4 VINI
VDD 16
RVC1
RVC2
RVC3
RVC4
CVDD
CVC1
CVC2
CVC3
VC1 15
VC2 14
VC3 13
VC4 12
NPI 11
VSS 10
CIT 9
S-8203A
RVM
RVINI
RDO
5 CTLC
6 CTLD
7 CCT
8 CDT
PTCCTLC
PTCCTLD
CCCT
CCDT
CCIT
RCO
EB−
RSENSE
Charging
FET
Discharging
FET
Figure 13 Overheat Protection via PTC
[For PTC, contact]
Murata Manufacturing Co., Ltd.
Thermistor Products Department
Nagaokakyo-shi, Kyoto 617-8555 Japan
TEL +81-75-955-6863
Contact Us: http://www.murata.com/contact/index.html
20
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Table 8 Constants for External Components
Symbol
Min.
0.47
0.47
0.47
0.47
1
Typ.
1
Max.
1
Unit
kΩ
kΩ
kΩ
kΩ
kΩ
MΩ
kΩ
kΩ
kΩ
kΩ
mΩ
Ω
μF
μF
μF
μF
μF
μF
μF
*1
*1
*1
*1
RVC1
RVC2
RVC3
RVC4
RDO
RCO
RVM
1
1
1
1
1
1
5.1
1
10
1
0.1
3
5.1
1
10
1
RCTLC
RCTLD
RVINI
0.1
0.1
1
1
0.1
1
1
RSENSE
0
−
−
100
*1
RVDD
43
100
0.1
0.1
0.1
0.1
0.1
0.1
1
*1
CVC1
0.068
0.068
0.068
0.01
0.01
0.02
0
1
*1
CVC2
1
*1
CVC3
1
CCCT
CCDT
CCIT
−
−
−
10
*1
CVDD
*1. Set up a filter constant to be RVDD × CVDD = 68 μF•Ω or more, and to be RVC1 × CVC1 = RVC2 × CVC2 = RVC3
VC3 = RVDD × CVDD
×
C
.
Caution 1. The constants may be changed without notice.
2. It is recommended that filter constants between VDD pin and VSS pin should be set approximately to
100 μF•Ω.
e.g., CVDD × RVDD = 1.0 μF × 100 Ω = 100 μF•Ω
Sufficient evaluation of transient power supply fluctuation and overcurrent protection function with the
actual application is needed to determine the proper constants. Contact our sales representatives in
case the constants should be set to other than 100 μF•Ω.
3. It has not been confirmed whether the operation is normal or not in circuits other than the connection
example. In addition, the connection example and the constants do not guarantee proper operation.
Perform thorough evaluation using the actual application to set the constants.
21
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Precautions
•
•
The application conditions for the input voltage, output voltage, and load current should not exceed the package
power dissipation.
Batteries can be connected in any order, however, there may be cases when discharging cannot be performed when
a battery is connected. In this case, short the VM pin and VSS pin or connect the battery charger to return to the
normal status.
•
•
•
If both an overcharge battery and an overdischarge battery are included among the whole batteries, the condition is
set in overcharge status and overdischarge status. Therefore either charging or discharging is impossible.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
22
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
Characteristics (Typical Data)
1. Current consumption
1. 1 IOPE vs VDS
1. 2 IOPE vs Ta
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
0
5
10
30
15
20
25
−40 −25
0
25
50
75 85
VDS [V]
Ta [°C]
1. 3 IPDN vs VDS
1. 4 IPDN vs Ta
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0
5
10
30
15
20
25
−40 −25
0
25
50
75 85
Ta [°C]
V
DS [V]
23
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
2. Overcharge detection / release voltage, overdischarge detection / release voltage, discharge overcurrent
detection voltage, load short-circuiting detection voltage, charge overcurrent detection voltage
2. 1 VCU vs Ta
2. 2 VCL vs Ta
4.275
4.270
4.265
4.260
4.255
4.250
4.245
4.240
4.235
4.230
4.225
4.200
4.190
4.180
4.170
4.160
4.150
4.140
4.130
4.120
4.110
4.100
−40 −25
0
0
0
25
Ta [°C]
50
50
50
75 85
75 85
75 85
−40 −25
0
0
0
25
Ta [°C]
50
50
50
50
75 85
75 85
75 85
75 85
2. 3 VDL vs Ta
2. 4 VDU vs Ta
2.780
2.760
2.740
2.720
2.700
2.680
2.660
2.640
2.620
3.100
3.080
3.060
3.040
3.020
3.000
2.980
2.960
2.940
2.920
2.900
−40 −25
25
Ta [°C]
−40 −25
25
Ta [°C]
2. 5 VDIOV vs Ta
2. 6 VSHORT vs Ta
0.600
0.580
0.560
0.540
0.520
0.500
0.480
0.460
0.440
0.420
0.400
0.165
0.160
0.155
0.150
0.145
0.140
0.135
−40 −25
25
Ta [°C]
−40 −25
25
Ta [°C]
2. 7 VCIOV vs Ta
−0.070
−0.080
−0.090
−0.100
−0.110
−0.120
−0.130
−40 −25
0
25
Ta [°C]
24
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
3. CCT pin internal resistance / detection voltage, CDT pin internal resistance / detection voltage, CIT
pin internal resistance / detection voltage and short-circuiting detection voltage delay time
3. 1 RCCT vs Ta
3. 2 VCCT vs Ta (VDS = 11.5 V)
8.3
12.0
11.0
10.0
9.0
8.2
8.1
8.0
7.9
7.8
8.0
7.0
6.0
−40 −25
0
0
0
0
25
Ta [°C]
50
50
50
50
75 85
75 85
75 85
75 85
−40 −25
0
25
Ta [°C]
50
50
50
75 85
75 85
75 85
3. 3 RCDT vs Ta
3. 4 VCDT vs Ta (VDS = 8.5 V)
6.2
1200
1100
1000
900
6.1
6.0
5.9
5.8
5.7
800
700
600
−40 −25
25
Ta [°C]
−40 −25
0
25
Ta [°C]
3. 5 RCIT vs Ta
3. 6 VCIT vs Ta (VDS = 10.5 V)
7.6
240
220
200
180
160
140
120
7.5
7.4
7.3
7.2
7.1
−40 −25
25
Ta [°C]
−40 −25
0
25
Ta [°C]
3. 7 tSHORT vs Ta
600.0
500.0
400.0
300.0
200.0
100.0
−40 −25
25
Ta [°C]
25
BATTERY PROTECTION IC FOR 3-SERIES CELL PACK
S-8203A Series
Rev.1.1_00
4. CO pin source / leakage current, DO pin source / sink current
4. 1 ICOH vs VCO
4. 2 ICOL vs VCO
7
6
5
4
3
2
1
0.10
0.08
0.06
0.04
0.02
0
0
0
0
5
5
10
15
20
25
30
20
10
15
VCO [V]
VCO [V]
4. 3 IDOH vs VDO
4. 4 IDOL vs VDO
7
6
5
4
3
2
1
0
−0.5
−1.0
−1.5
−2.0
−2.5
0
0
5
0
1
2
3
4
5
6
20
10
15
V
DO [V]
VDO [V]
26
5.1±0.2
16
9
8
1
0.17±0.05
0.22±0.08
0.65
No. FT016-A-P-SD-1.2
TITLE
TSSOP16-A-PKG Dimensions
FT016-A-P-SD-1.2
No.
ANGLE
mm
UNIT
ABLIC Inc.
+0.1
-0
4.0±0.1
ø1.5
0.3±0.05
2.0±0.1
8.0±0.1
1.5±0.1
ø1.6±0.1
(7.2)
4.2±0.2
+0.4
-0.2
6.5
1
16
8
9
Feed direction
No. FT016-A-C-SD-1.1
TITLE
TSSOP16-A-Carrier Tape
FT016-A-C-SD-1.1
No.
ANGLE
mm
UNIT
ABLIC Inc.
21.4±1.0
17.4±1.0
+2.0
-1.5
17.4
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FT016-A-R-S1-1.0
TITLE
No.
TSSOP16-A- Reel
FT016-A-R-S1-1.0
ANGLE
UNIT
4,000
QTY.
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com
相关型号：
©2020 ICPDF网 联系我们和版权申明