ABVFM-311.040MHZ-F-R-P [ABRACON]
Oscillator;
| 型号： | ABVFM-311.040MHZ-F-R-P |
| 厂家： | 
ABRACON |
| 描述： | Oscillator |
| 文件： | 总2页 (文件大小：1541K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CERAMIC SMD CRRYYSSTTAALL CCLLOOCCKK OOSSCILLATOR
WWIITTHH VOLTAGE CONTROL
ABVFM SERIES
FEATURES:
: PRELIMINARY
5.0 x 7.0 x 1.8mm
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APPLICATIONS:
• xDSL, Cable Modems
• Customer Premise Equipment (CPE)
• ATM, SONET, SDH, STB
• Based on a proprietary analog multiplier
• Tri-State Output
• Ultra low Phase Jitter
• 2.5V to 3.3V +/- 10% operation
• Ceramic SMD, low profile package
• LAN / WAN Data Communications Equip.
• 155.52MHz, 311.04MHz, 622.08MHz applications
STANDARD SPECIFICATIONS:
PARAMETERS
Frequency Range
60 MHz to 320 MHz
Operating Temperature
Storage Temperature
Overall Frequency Stability
Supply Voltage (Vdd)
Jitter (12KHz - 20MHz)
0°C to + 70°C (see options)
- 55°C to + 125°C
100 ppm maꢀx (see options)
2x5V - 3x3 Vdc 10ꢁ
RMS phase jitter < 0x6pS
period jitter < 20pS peak to peak
Low Phase Noise
-130 dBc/Hz @ 1kHz Offset from 212x5MHz
-140 dBc/Hz @ 10kHz Offset from 212x5MHz
-145 dBc/Hz @ 100kHz Offset from 212x5MHz
Aging (PPM/year)
Pullability
TBD Per Crystal
+/- 50ppm
PECL
Supply Current (IDD)[Fout = 212x50MHz]
Output Clock Duty Cycle @ VDD-1x3V
Output High Voltage
58mA min, 65mA typical, 75mA maꢀx
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀx
VOH = VDD-2V (VDD-1x025V min)
VOL = VDD-2V (VDD-1x620V maꢀ)
0x7ns maꢀ, 0x4ns typical
Output Low Voltage
Clock Rise time (tr) @ 20/80ꢁ
Clock Fall time (tf) @ 80/20ꢁ
CMOS
0x7ns maꢀ, 0x4ns typical
Output Clock Rise/ Fall Time [10ꢁ~90ꢁ VDD with 10pF load] 1x6ns maꢀ, 1x2ns typical
Output Clock Duty Cycle [Measured @ 50ꢁ VDD]
LVDS
Supply Current (IDD) [Fout = 212x50MHz]
Output Clock Duty Cycle @ 1x25V
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ
60mA maꢀ, 55mA typicalx
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ
247mV min, 355mV typical, 454mV maꢀ
-50mV min, 50mV maꢀ
Output Differential Voltage (VOD
)
VDD Magnitude Change (∆VOD
)
Output High Voltage
Output Low Voltage
Offset Voltage [RL = 100
Offset Magnitude Voltage[RL = 100
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V]
Differential Clock Rise Time (tr) [RL=100 , CL=10pF]
Differential Clock Fall Time (tf) [RL=100 , CL=10pF]
VOH = 1x6V maꢀ, 1x4V typical
VOL = 0x9V min, 1x1V typical
Ω]
VOS = 1x125V min, 1x1V typical, 1x375V maꢀ
∆VOS = 0mV min, 3mV typical, 25mV maꢀ
10µA maꢀ, 1µA typical
0x2ns min, 0x5ns typical, 0x7ns maꢀ
0x2ns min, 0x5ns typical, 0x7ns maꢀ
Ω]
Ω
Ω
ABBRRAACCOONN IIS
ISO 9001 / QS 9000
CERTTIIFFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
CERAMIC SMD CRRYYSSTTAALL CCLLOOCCKK OOSSCILLATOR
WWIITTHH VOLTAGE CONTROL
ABVFM SERIES
: PRELIMINARY
5.0 x 7.0 x 1.8mm
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PIN ASSIGNMENTS:
PIN #
NAME
VCON
Tri-state
GND
Q
DESCRIPTION
1
2
3
4
5
6
VCON
Tri-state
Ground
PECL, LVDS, or CMOS Outꢀut
Comꢀlimentary PECL,LVDS, or NC
VDD Connection
Q
VDD
TRI-STATE PIN OPERATION:
OUTPUT TYPE
PIN 2 LOGIC LEVEL*
OUTPUT STATE
Enabled
PECL
0 (Default)
1
0
Tri-state
LVDS & CMOS
Tri-state
Enabled
1(Default)
*Connect to VDD from logic level "1", connect to ground for logic level "0".
MARKING:
OUTLINE DRAWING:
- TUH
(Frequency: T=First “”10” digit of frequency, U=First “unit” of frequency,
H=First “tenth” of frequency, Ex: 100 for 10.0MHz)
- ABFM ZY (Z: Month, A to L; Y: Year, 5 for 2005
OPTIONS AND PART IDENTIFICATION (Left blank if standard)
:
ABFM - Frequency - Temperature - Frequency Stability - Output - Packaging
Output options:
P = PECL
Stability options:
R for 25 ꢀꢀm
C for 50 ꢀꢀm
Temperature:
D for -10°C to +60°C
E for -20°C to +70°C
F for -30°C to +70°C
N for -30°C to +85°C
L for -40°C to +85°C
L = LVDS
C = CMOS
Packaging option: T for Taꢀe and Reel (1,000ꢀcs/reel)
Dimensions: inch (mm)
Availability limited to application specific application frequencies.
Please contact factory for available frequencies.
ABBRRAACCOONN IIS
ISO 9001 / QS 9000
CERTTIIFFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
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