ALD800LHCA [ABRACON]
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR; 陶瓷贴片晶振时钟振荡器
| 型号： | ALD800LHCA |
| 厂家： | 
ABRACON |
| 描述： | CERAMIC SMD CRYSTAL CLOCK OSCILLATOR |
| 文件： | 总2页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CERAMIC SMD CRYSTAL CLOOCK OSCILLATTOORR
ALD SERIES
: PRELIMINARY
5.08 x 7.0 x 1.8mm
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APPLICATIONS:
• SONET, xDSL
• SDH, CPE
• STB
FEATURES:
• Based on a proprietary digital multiplier
• Tri-State Output
• 2.5V to 3.3V +/- 5% operation
• Ceramic SMD, low profile package
• 156.25MHz, 187.5MHz, and 212.5MHz applications
• Low Phase Jitter
STANDARD SPECIFICATIONS:
PARAMETERS
Frequency Range
750 KHz to 800 MHz
0°C to + 70°C (see options)
- 40°C to + 85°C
50 ppm maꢀx (see options)
2x5V to 3x3 Vdc 5ꢁ
5ꢁ typ, 10ꢁ maꢀx
Operating Temperature
Storage Temperature
Overall Frequency Stability
Supply Voltage (Vdd)
Linearity
Jitter (12KHz - 20MHz)
RMS phase jitter 3pS typx < 5pS maꢀx
period jitter < 35pS peak to peak
Phase Noise
-109 dBc/Hz @ 1kHz Offset from 622x08MHz
-110 dBc/Hz @ 10kHz Offset from 622x08MHz
-109 dBc/Hz @ 100kHz Offset from 622x08MHz
“1” (VIH > 0x7*VDD) or open: Oscillation/ “0” (VIH > 0x3*VDD) No Oscillation/Hi Z
Tri-State Function
PECL
Supply Current (IDD)
Symmetry (Duty Cycle)
Output Logic High
Output Logic Low
Clock Rise time (tr) @ 20/80ꢁ
Clock Fall time (tf) @ 80/20ꢁ
80mA (Fo < 155x52MHz), 100mA (Fo < 155x52MHz)
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀx
VDD -1x025V min, VDD -0x880V maꢀx
VDD -1x810V min, VDD -1x620V maꢀx
1x5ns maꢀ, 0x6nSec typical
1x5ns maꢀ, 0x6nSec typical
CMOS
Output Clock Rise/ Fall Time [10ꢁ~90ꢁ VDD with 10pF load] 1x6ns maꢀ, 1x2ns typical
Output Clock Duty Cycle [Measured @ 50ꢁ VDD]
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ
LVDS
Supply Current (IDD) [Fout = 212x50MHz]
60mA maꢀ, 55mA typicalx
Output Clock Duty Cycle @ 1x25V
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ
247mV min, 355mV typical, 454mV maꢀ
-50mV min, 50mV maꢀ
Output Differential Voltage (VOD
)
VDD Magnitude Change (∆VOD
)
Output High Voltage
Output Low Voltage
Offset Voltage [RL = 100
Offset Magnitude Voltage[RL = 100
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V]
Differential Clock Rise Time (tr) [RL=100 , CL=10pF]
Differential Clock Fall Time (tf) [RL=100 , CL=10pF]
VOH = 1x6V maꢀ, 1x4V typical
VOL = 0x9V min, 1x1V typical
Ω]
VOS = 1x125V min, 1x2V typical, 1x375V maꢀ
∆VOS = 0mV min, 3mV typical, 25mV maꢀ
10µA maꢀ, 1µA typical
0x2ns min, 0x5ns typical, 0x7ns maꢀ
0x2ns min, 0x5ns typical, 0x7ns maꢀ
Ω]
Ω
Ω
ABBRRAACCOONN IIS
ISO 9001 / QS 9000
CERTTIIFFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
CERAMICC SSMMD CRYSSTTAALL CLOCK OSCILLATTOORR
ALD SERIES
: PRELIMINARY
5.08 x 7.0 x 1.8mm
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PIN ASSIGNMENTS:
PIN #
NAME
DESCRIPTION
1
2
3
4
5
6
Tri-state or VC
Tri-state or Voltage Control
Tri-state or No Connect
Ground
Tri-state or NC
GND
Q
Q
VDD
PECL, LVDS, or CMOS Output
Complimentary PECL,LVDS, or NC
VDD Connection
TRI-STATE PIN OPERATION:
OUTPUT TYPE
PIN 1 LOGIC LEVEL*
OUTPUT STATE
Enabled
PECL
0 (Default)
(P)
1
0
Tri-state
Tri-state
LVDS & CMOS
(L, C)
1(Default)
0
Enabled
Tri-state
PECL1
(P1)
1(Default)
Enabled
*Connect to VDD from logic level "1", connect to ground for logic level "0".
MARKING:
OUTLINE DRAWING:
- TUH
(Frequency: T=First “”10” digit of frequency, U=First “unit” of frequency,
H=First “tenth” of frequency, Ex: 100 for 10.0MHz)
- ALD ZYX (Z: Month, A to L; Y: Year, 5 for 2005; X: Traceability Code)
OPTIONS AND PART IDENTIFICATION (Left blank if standard)
:
ALD - Frequency - Temperature - Frequency Stability - Output - Packaging
Output options:
P = PECL
Temperature:
Stability options:
R for 25 ppm
K for 30 ppm
H for 35 ppm
D for -10°C to +60°C
E for -20°C to +70°C
F for -30°C to +70°C
N for -30°C to +85°C
L for -40°C to +85°C
L = LVDS
C = CMOS
P1 = PECL1
Dimensions: inch (mm)
Tri-State option: A for Pin 1 = NC, Pin 2 = Tristate
Packaging option: T for Tape and Reel (1,000pcs/reel)
ABRACON IS
ISO 9001 / QS 9000
CERTTIIFFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
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