ALVD-FREQ-F-H-L [ABRACON]

LVDS Output Clock Oscillator, 0.75MHz Min, 800MHz Max, CERAMIC, SMD, 6 PIN;
ALVD-FREQ-F-H-L
型号: ALVD-FREQ-F-H-L
厂家: ABRACON    ABRACON
描述:

LVDS Output Clock Oscillator, 0.75MHz Min, 800MHz Max, CERAMIC, SMD, 6 PIN

文件: 总2页 (文件大小:281K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CERAMIC SMD CRRYYSSTTAALL CCLLOOCCKK OOSSCILLATOR  
WWIITTHH VOLTAGE CONTROL  
ALVD SERIES  
: PRELIMINARY  
5.08 x 7.0 x 1.8mm  
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
APPLICATIONS:  
• SONET, xDSL  
• SDH, CPE  
• STB  
FEATURES:  
• Based on a proprietary digital multiplier  
• Tri-State Output  
• Low Phase Jitter  
• 2.5V to 3.3V +/- 5% operation  
• Ceramic SMD, low profile package  
• 155.52MHz, 311.04MHz, and 622.08MHz applications  
STANDARD SPECIFICATIONS:  
PARAMETERS  
Frequency Range  
750 KHz to 800 MHz  
0°C to + 70°C (see options)  
- 55°C to + 125°C  
50 ppm maꢀx (see options)  
2x5V to 3x3 Vdc 5ꢁ  
0x3VDC min, 1x65VDC typ, 3x0VDC maꢀ  
100 ppm  
Operating Temperature  
Storage Temperature  
Overall Frequency Stability  
Supply Voltage (Vdd)  
Voltage Control (Vc)  
Frequency Pullability  
Linearity  
5ꢁ typ, 10ꢁ maꢀx  
Jitter (12KHz - 20MHz)  
Phase Noise  
RMS phase jitter 3pS typx < 5pS maꢀx period jitter < 35pS peak to peak  
-109 dBc/Hz @ 1kHz Offset from 622x08MHz  
-110 dBc/Hz @ 10kHz Offset from 622x08MHz  
-109 dBc/Hz @ 100kHz Offset from 622x08MHz  
“1” (VIH > 0x7*VDD) or open: Oscillation/ “0” (VIH > 0x3*VDD) No Oscillation/Hi Z  
Tri-State Function  
PECL  
Supply Current (IDD)  
65mA (Fo < 96MHz), 100mA (Fo < 700x00MHz)  
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀx  
VDD -1x025V min, VDD -0x880V maꢀx  
VDD -1x810V min, VDD -1x620V maꢀx  
0x6nSec typical, 1x5ns maꢀ  
Symmetry (Duty Cycle)  
Output Logic High  
Output Logic Low  
Clock Rise time (tr) @ 20/80ꢁ  
Clock Fall time (tf) @ 80/20ꢁ  
CMOS  
0x6nSec typical, 1x5ns maꢀ  
Output Clock Rise/ Fall Time [10ꢁ~90ꢁ VDD with 10pF load] 1x2ns typical, 1x6ns maꢀ  
Output Clock Duty Cycle [Measured @ 50ꢁ VDD] 45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ  
LVDS  
Supply Current (IDD) [Fout = 212x50MHz]  
Output Clock Duty Cycle @ 1x25V  
45mA maꢀ (Fo < 96MHz), 80mA maꢀ (Fo < 700MHz)  
45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ  
247mV min, 355mV typical, 454mV maꢀ  
-50mV min, 50mV maꢀ  
Output Differential Voltage (VOD  
)
VDD Magnitude Change (VOD  
)
Output High Voltage  
Output Low Voltage  
Offset Voltage [RL = 100  
Offset Magnitude Voltage[RL = 100  
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V]  
Differential Clock Rise Time (tr) [RL=100 , CL=10pF]  
Differential Clock Fall Time (tf) [RL=100 , CL=10pF]  
VOH = 1x4V typical, 1x6V maꢀ  
VOL = 0x9V min, 1x1V typical  
]  
VOS = 1x125V min, 1x2V typical, 1x375V maꢀ  
VOS = 0mV min, 3mV typical, 25mV maꢀ  
1µA typical, 10µA maꢀ  
0x2ns min, 0x7ns typical, 1x0ns maꢀ  
0x2ns min, 0x7ns typical, 1x0ns maꢀ  
]  
ABRACON IS  
ISO 9001 / QS 9000  
CERTTIIFFIED  
30332 Esperanza, Rancho Santa Margarita, California 92688  
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com  
CERAMIC SMD CRRYYSSTTAALL CCLLOOCCKK OOSSCILLATOR  
WWIITTHH VOLTAGE CONTROL  
ALVD SERIES  
: PRELIMINARY  
5.08 x 7.0 x 1.8mm  
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PIN ASSIGNMENTS:  
PIN #  
NAME  
DESCRIPTION  
1
2
3
4
5
6
Tri-state or VC  
Tri-state or Voltage Control  
Tri-state or No Connect  
Ground  
Tri-state or NC  
GND  
Q
Q
VDD  
PECL, LVDS, or CMOS Outꢀut  
Comꢀlimentary PECL,LVDS, or NC  
VDD Connection  
TRI-STATE PIN OPERATION:  
OUTPUT TYPE  
PIN 2 LOGIC LEVEL*  
OUTPUT STATE  
Enabled  
PECL  
0 (Default)  
(P)  
1
0
Tri-state  
Tri-state  
Enabled  
Disabled  
Enabled  
LVDS & CMOS  
(L, C)  
1(Default)  
0
PECL  
(P)  
1(Default)  
*Connect to VDD from logic level "1", connect to ground for logic level "0".  
MARKING:  
OUTLINE DRAWING:  
- TUH  
(Frequency: T=First “”10” digit of frequency, U=First “unit” of frequency,  
H=First “tenth” of frequency, Ex: 100 for 10.0MHz)  
- ALVD ZYX (Z: Month, A to L; Y: Year, 5 for 2005; X: Traceability Code)  
OPTIONS AND PART IDENTIFICATION (Left blank if standard)  
:
ALVD - Frequency - Temperature - Frequency Stability - Pulling - Output Type  
Pulling options:  
Stability options:  
R for 25 ꢀꢀm  
K for 30 ꢀꢀm  
H for 35 ꢀꢀm  
Temperature:  
N 15 150 ꢀꢀm min.  
D for -10°C to +60°C  
E for -20°C to +70°C  
F for -30°C to +70°C  
N for -30°C to +85°C  
L for -40°C to +85°C  
Output option:  
P = PECL  
P1 = PECL1  
L = LVDS  
C = CMOS  
Dimensions: inch (mm)  
ABRACON IS  
ISO 9001 / QS 9000  
CERTTIIFFIED  
30332 Esperanza, Rancho Santa Margarita, California 92688  
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com  

相关型号:

ALVD-FREQ-F-H-N15-C

CMOS Output Clock Oscillator, 0.75MHz Min, 800MHz Max, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-N15-L

LVDS Output Clock Oscillator, 0.75MHz Min, 800MHz Max, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-N15-P

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-N15-P1

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-P

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-P-N100

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-P-N100-T

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-P-T

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-P1

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-P1-N100

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-P1-N100-T

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
ABRACON

ALVD-FREQ-F-H-P1-T

PECL Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
ABRACON