ACE25AA160GUA8TH [ACE]
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase;
| 型号： | ACE25AA160GUA8TH |
| 厂家： | 
ACE TECHNOLOGY CO., LTD. |
| 描述： | Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase |
| 文件： | 总46页 (文件大小：1869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Description
The ACE25AA160G (16M-bit) Serial Peripheral Interface (SPI). and supports the Dual/Quad SPI:
Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred wit speed
of 480 Mbits/s.
Features
16M-bit Serial Flash
2048K-byte
256 bytes per programmable page
Standard, Dual, Quad SPI
Standard SPI: SCLK, CS#, SI, SO, SO, WP#, HOLD#
Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
Flexible Architecture
Sector of 4K-byte
Block of 32/64k-byte
Advanced security Features
3*256-Byte Security Registers With OTP Lock
Software/Hardware Write Protection
Write protect all/portion of memory via software
Enable/Disable protection with WP# Pin
Top or Bottom, Sector or Block selection
Package Options
See 1.1 Available Ordering OPN
All Pb-free packages are compliant RoHS, Halo- gen-Free and REACH.
Temperature Range & Moisture Sensitivity Level
Industrial Level Temperature (-40~85°C), MSL3
Industrial Plus Level Temperature (-40°C to +105°C), MSL1
Low Power Consumption
20mA maximum active current
5uA maximum standby current
Single Power Supply Voltage: Full voltage range:2.7~3.6V
Minimum 100,000 Program/Erase Cycle
VER 1.2
1
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
High Speed Clock Frequency
120MHz for fast read with 30PF load
Dual I/O Data transfer up to 240Mbits/s
Quad I/O Data transfer up to 480Mbits/s
Program/Erase Speed
Page Program time: 0.4ms typical
Sector Erase time: 100ms typical
Block Erase time: 0.15/0.25s typical
Chip Erase time: 6s typical
Absolute Maximum Ratings
Parameter
Value
-40 to 85
-65 to 150
200
Unit
℃
Ambient Operating Temperature
Storage Temperature
Output Short Circuit Current
Applied Input/Output Voltage
VCC
℃
mA
V
-0.5 to 4.0
-0.5 to 4.0
V
VER 1.2
2
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Packaging Type
SOP-8/SOP-8L
TSSOP-8
USON3*2-8
Pin Configurations
I/O
Pin Name
CS#
Functions
I
Chip Select Input
SO(IO1)
WP#(IO2)
VSS
I/O
I/O
Data Output(Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
SI(IO0)
SCLK
I/O
I
Data Input(Data Input Output 0)
Serial Clock Input
HOLD#(IO3)
VCC
I/O
Hold Input (Data Input Output 3)
Power Supply
Ordering information
ACE25AA160G XX + X H
Halogen-free
U: Tube
T: Ta p e and Reel
Pb - free
FM: SOP-8
FML: SOP-8L (208mil)
TM: TSSOP-8
UA8: USON3*2-8
VER 1.2
3
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Block Diagram
Uniform Block Sector Architecture
ACE25AA160G 64K Bytes Block SectorArchitecture
Block
Sector
511
……
496
495
……
480
……
……
……
47
……
32
31
……
16
15
Address Range
1FF000H
……
1F0000H
1EF000H
……
1E0000H
……
1FFFFFH
……
1F0FFFH
1EFFFFH
……
1E0FFFH
……
31
30
……
……
……
……
……
02F000H
……
020000H
01F000H
……
010000H
00F000H
……
02FFFFH
……
020FFFH
010FFFH
……
010FFFH
00FFFFH
……
2
1
0
……
0
000000H
000FFFH
VER 1.2
4
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Device Operation
The ACE25AA160G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of
SCLK.
Dual SPI
The ACE25AA160G supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O
Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the
device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins
become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The ACE25AA160G supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O
Fast Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be
transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI
command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins
become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status
Register to be set .
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the
operation of write status register, programming, or erasing in progress .
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high
during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip,
the HOLD# must be at high and then CS# must be at low.
VER 1.2
5
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Data Protection
The ACE25AA160G provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
Power-Up
Write Disable (WRDI)
Write Status Register (WRSR)
Page Program (PP)
Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode:
The Block Protect (BP4, BP3, BP2, BP1,BP0) bits define the section of the memory array that can be
read but not change
Hardware Protection Mode:
WP# going low to protected the BP0~BP4 bits and SRP bit
Deep Power-Down Mode:
In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down
Mode command
Table 1.ACE25AA160G Protected Area Sizes (CMP=0)
Status bit
Memory Content
BP4
X
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
BP3 BP2 BP1 BP0
Blocks
None
31
Addresses
None
1F0000H – 1FFFFFH
Density
None
64KB
128K
256K
512K
1M
64KB
128KB
256KB
512KB
1M
2M
4KB
8KB
16KB
32KB
4KB
8KB
16KB
32KB
Portion
None
X
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
X
1
0
1
X
1
0
1
X
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
30 to 31 1E0000H – 1FFFFFH
28 to 31 1C0000H – 1FFFFFH
24 to 31 180000H – 1FFFFFH
16 to 31 100000H – 1FFFFFH
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 31
31
000000H – 00FFFFH
000000H – 01FFFFH
000000H – 03FFFFH
000000H – 07FFFFH
000000H – 0FFFFFH
000000H – 1FFFFFH
1FF000H – 1FFFFFH
1FE000H – 1FFFFFH
1FC000H – 1FFFFFH
1F8000H – 1FFFFFH
000000H – 000FFFH
000000H – 001FFFH
000000H – 003FFFH
000000H – 007FFFH
31
31
31
0
0
0
0
1
1
1
VER 1.2
6
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Table 1.1ACE25AA160G Protected Area Sizes (CMP=1)
Status bit
Memory Content
BP4
X
0
BP3 BP2 BP1 BP0
Blocks
0 to 31
0 to 30
0 to 29
0 to 27
0 to 23
0 to 15
1 to 31
2 to 31
4 to 31
8 to 31
Addresses
Density
2M
Portion
ALL
X
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
X
1
0
1
X
1
0
1
X
000000H – 1FFFFFH
000000H – 1EFFFFH
000000H – 1DFFFFH
000000H –1BFFFFH
000000H –17FFFFH
000000H –0FFFFFH
010000H – 1FFFFFH
020000H – 1FFFFFH
040000H – 1FFFFFH
080000H – 1FFFFFH
1984KB
1920KB
1792KB
1536KB
1M
Lower 31/32
Lower 15/16
Lower 7/8
0
0
0
Lower 3/4
0
Lower 1/2
0
1984KB
1920KB
1792KB
1536KB
1M
Upper 31/32
Upper 15/16
Upper 7/8
0
0
0
Upper 3/4
0
16 to 31 100000H – 1FFFFFH
Upper 1/2
X
1
NONE
0 to 31
0 to 31
0 to 31
0 to 31
0 to 31
0 to 31
0 to 31
0 to 31
NONE
NONE
NONE
000000H –1FEFFFH
000000H –1FDFFFH
000000H –1FBFFFH
000000H –1F7FFFH
001000H –1FFFFFH
002000H –1FFFFFH
004000H –1FFFFFH
008000H –1FFFFFH
2044KB
2040KB
2032KB
2016KB
2044KB
2040KB
2032KB
2016KB
Lower 511/512
Lower 255/256
Lower 127/128
Lower 63/64
Upper 511/512
Upper 255/256
Upper 127/128
Upper 63/64
1
1
1
1
1
1
1
VER 1.2
7
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Status Register
S15
S14
S13
S12
S11
S10
LB
S9
S8
SUS
CMP
Reserved
Reserved
Reserved
QE
Reserved
S7
S6
S5
S4
S3
S2
S1
S0
SRP
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status
register progress. When WIP bit sets to 1, the device is busy in program/erase/write status register
progress, When WIP bit sets 0, means the device is not in program/ erase/ write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1
the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write
Status Register, Program or Erase command is accepted.
BP4, BP3,BP2, BP1,BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status
Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the
relevant memory area (as defined in Table1) becomes protected against Page Program (PP), Sector
Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is
executed, if the Block Protect (BP3, BP2, BP1, BP0) bits are all 0.
VER 1.2
8
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
SRP bit.
The Status Register Protect (SRP) bit is a non-volatile Read/Write bit in the status register. The SRP bit
controls the method of write protection: software protection, hardware protection, power supply lock-down
or one time programmable protection.
SRP
WP#
Status Register
Description
The Status Register can be written to after a Write
Enable command, WEL=1.(Default)
0
X
Software Protected
WP#=0, the Status Register locked and cannot be
written to.
1
1
0
1
Hardware Protected
WP#=1, the Status Register is unlocked and can be
written to after a Write Enable command, WEL=1.
Hardware Unprotected
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad
operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE bit
is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard
SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground).
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write
protect control and status to the Security Registers. The default state of LB is 0, the security registers are
unlocked. LB can be set to 1 using the Write Register instruction. LB is One Time Programmable, once it’s
set to 1, the Security Registers will become read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the
BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory
Protec tion table for details. The default setting is CMP=0.
SUS bit.
The SUS bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program
Suspend (75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command or
during power-down & power-up cycle.
VER 1.2
9
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Commands Description
All commands, addresses and data are shifted in and out of the device, beginning with the most
significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code
must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges
of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on
the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be
driven high after the last bit of the command sequence has been shifted in. For the command of Read,
Fast Read, Read Status Register, and Read Device ID, the shifted-in command sequence is followed by a
data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable, CS# must be driven high exactly at a byte boundary, otherwise the command is
rejected. That is CS# must driven high when the number of clock pulses after CS# being driven low is an
exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will
happen and WEL will not be reset.
Table2. Commands
Command Name
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
n-Bytes
Write Enable
06H
Write Enable for
Volatile Status
Register
50H
Write Disable
04H
05H
Read Status Register
(S7-S0)
(continuous)
(continuous)
(continuous)
Read Status
Register-1
35H
(S15-S8)
Write Status Register
Read Data
01H
03H
0BH
(S7-S0)
A23-A16
A23-A16
(S15-S8)
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
(Next byte) (continuous)
(D7-D0) (continuous)
Fast Read
Dual Output Fast
Read
3BH
BBH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(1) (continuous)
(continuous)
A7-A0
Dual I/O Fast Read
A23-A8(2)
(D7-D0)(1)
M7-M0(2)
VER 1.2 10
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Quad Output Fast
Read
6BH
EBH
E7H
FFH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(3) (continuous)
(continuous)
A23-A0
M7-M0(4)
A23-A0
Quad I/O Fast Read
Dummy(5)
Dummy(6)
(D7-D0)(3)
(D7-D0)(3)
Quad I/O Word Fast
Read
(continuous)
M7-M0(4)
Continuous Read
Reset
Page Program
02H
32H
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
(Next byte)
Quad Page Program
(D7-D0)(3)
A23-A0
D7-D0
(Next byte)
Quad I/O PP
38H
398
(Next byte)
Sector Erase
Block Erase(32KB)
Block Erase(64KB)
Chip Erase
20H
52H
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
D8H
C7/60H
Program/Erase
Suspend
75H
Program/Erase
Resume
7AH
B9H
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
ABH
ABH
dummy
dummy
dummy
(DID7-DID0)
(continuous)
Manufacturer/Device
ID
90H
A3H
dummy
dummy
dummy
dummy
00H
(MID7- MID0) (DID7-DID0) (continuous)
High Speed Mode
dummy
VER 1.2 11
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
(JDID15-J
DID8)
(JDID7-JDI
D0)
Read Identification
9FH
44H
42H
48H
(MID7- MID0)
A23-A16
(continuous)
Erase Security
Register(8)
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Program Security
Register(8)
A23-A16
(D7-D0)
dummy
(Next byte)
(D7-D0)
Read Security
Register(8)
A23-A16
Enable Reset
Reset
66H
99H
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1
2. Dual Input Address
IO0 =A22, A20, A18, A16, A14, A12, A10, A8,A6, A4, A2, A0, M6, M4, M2, M0
IO1 =A23, A21, A19, A17, A15, A13, A11, A9,A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address
IO0 =A20, A16, A12, A8, A4, A0, M4, M0
IO1 =A21, A17, A13, A9, A5, A1, M5, M1
IO2 =A22, A18, A14, A10, A6, A2, M6, M2
IO3 =A23, A19, A15, A11, A7, A3, M7, M3
5. Quad I/O Fast Read Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
VER 1.2 12
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
6. Quad I/O Word Fast Read Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Quad I/O Word Fast Read Data: the lowest address bit must be 0
8. Security Registers Address :
Security Register0: A23-A16=00H, A15-A8=00H, A7-A0= Byte Address;
Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=03H, A7-A0= Byte Address.
ID Definitions
Operation Code
M7-M0
0B
ID15-ID8
40
ID7-ID0
15
9FH
90H
ABH
0B
14
14
Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip
Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command
sequence: CS# goes low→sending the Write Enable command→CS# goes high.
Figure1. Write Enable Sequence Diagram
VER 1.2 13
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Write Enable for Volatile Status Register (50H )
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical
non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write
Enable for Volatile Status Register command must be issued prior to a Write Status Register command
and any other commands can't be inserted between them. Otherwise, Write Enable for Volatile Status
Register will be cleared. The Write Enable for Volatile Status Register command will not set the Write
Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status
Register bit values.
Figure2. Write Enable for Volatile Status Register Sequence Diagram
Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable
command sequence: CS# goes low→sending Write Disable command→CS# goes high. The WEL bit is
reset by following condition: Power-up and upon completion of the Write Status Register, Page Program,
Sector Erase, Block Erase and Chip Erase commands.
Figure3. Write Disable Sequence Diagram
VER 1.2 14
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may
be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one
of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending
a new command to the device. It is also possible to read the Status Register continuously. For command
code “05H”, the SO will output Status Register bits S7~S0. The command code “35H”, the SO will output
Status Register bits S15~S8.
Figure4. Read Status Register Sequence Diagram
Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After
the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable
Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S1 and S0 of the Status Register.
CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status
Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the
CMP and QE bit will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register
cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status
Register can still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
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The Write Status Register (WRSR) command allows the user to change the values of the Block Protect
(BP4, BP3,BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as
defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the
Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode
is entered.
Figure5. Write Status Register Sequence Diagram
Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO,
each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address
after each byte of data is shifted out. Therefore, the whole memory can be read with a single Read Data
Bytes (READ) command. During an Erase, Program or Write cycle, Read Data Byte (READ) command
will be rejected without affecting the cycle in progress.
Figure6. Read Data Bytes Sequence Diagram
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Read Data Bytes At Higher Speed (Fast Read)(0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed
by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK.
Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency f , during the falling edge of SCLK. The first byte address can be at any location. The address
C
is automatically incremented to the next higher address after each byte of data is shifted out.
Figure7. Read Data Bytes at Higher Speed Sequence Diagram
Dual Output Fast Read (3BH )
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per
clock cycle from SI and SO. The command sequence is shown in Figure 8. The first byte addressed can
be at any location. The address is automatically incremented to the next address after each byte of data is
shifted out.
Figure8. Dual Output Fast Read Sequence Diagram
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Quad Output Fast Read (6BH )
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per
clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in Figure 9. The first byte
addressed can be at any location. The address is automatically incremented to the next address after
each byte of data is shifted out.
Figure9. Quad Output Fast Read Sequence Diagram
Dual I/O Fast Read(BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the
capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI
and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted
out 2-bit per clock cycle from SI and SO. The command sequence is shown in Figure 10. The first byte
addressed can be at any location. The address is automatically incremented to the next address after
each byte of data is shifted out. To ensure optimum performance the High Speed mode (HSM) command
(A3H) must be executed once, prior to the Dual I/O Fast Read command.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the
“Continuous Read Mode” bits (M7- 0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5- 4) =(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then
lowered) does not require the BBH command code. The command sequence is shown in figure 10a. If the
“Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires the first BBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be
used to reset (M5- 4) before issuing normal command.
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Figure10. Dual I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
Figure10a. Dual I/O Fast Read Sequence Diagram (M5-4=(1, 0))
Quad I/O Fast Read(EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability
to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bits per
clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory
contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in
Figure 11. The first byte addressed can be at any location. The address is automatically incremented to
the next address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9)
must be set to enable for the Quad I/O Fast read command. To ensure optimum performance the High
Speed mode (HSM) command (A3H) must be executed once, prior to the Qual I/O Fast Read command.
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Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5- 4) =(1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then
lowered) does not re- quire the EBH command code. The command sequence is shown in Figure 11a. If
the “Continuous Read Mode” (M5- 4) do not equal (1, 0), the next command requires the first EBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be
used to reset (M5- 4) before issuing normal command.
Figure11.Quad I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
Figure11a.Quad I/O Fast Read Sequence Diagram (M5-4=(1, 0))
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Quad I/O Word Fast Read(E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the
lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in
followed Figure 12. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of
Status Register (S9) must be set to enable for the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5- 4) =(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and
then lowered) does not require the E7H command code. The command sequence is shown in followed
Figure 12a. If the “Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires
the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M7-0) before issuing normal command.
Figure12.Quad I/O Word Fast Read Sequence Diagram (M5-4≠(1, 0))
Figure12a.Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))
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Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page
Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end of the current page are programmed from the start
address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must
be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes
low→sending Page Program command→3-byte address on SI→at least 1 byte data on SI→CS# goes
high. The command sequence is shown in Figure13. If more than 256 bytes are sent to the device,
previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed
correctly within the same page. If less than 256 data bytes are sent to device, they are correctly
programmed at the requested addresses without having any effects on the other bytes of the same page.
CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page
Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated.
While the Page Program cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,
and is 0 when it is completed. As some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3,
BP2, BP1, BP0) is not executed.
Figure13. Page Program Sequence Diagram
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Quad Page Program (QPP) (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and
IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write
Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit
before sending the Page Program command. The Quad Page Program command is entered by driving
CS# Low, followed by the command code (32H), three address bytes and at least one data byte on IO
pins.
The command sequence is shown in Figure 14. If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the
requested ad- dresses without having any effects on the other bytes of the same page. CS# must be
driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page
Program command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is
initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed
Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3,
BP2, BP1, BP0) will not be executed.
Figure14. Quad Page Program Sequence Diagram
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Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase
(SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI.
Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven
low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command→3-byte address
on SI→CS# goes high. The command sequence is shown in Figure15. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not
executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset. A Sector Erase( (SE) command applied to a sector which is protected by
the Block Protect(BP4, BP3,BP2, BP1, and BP0) bit (see Table1 &1.1) will not be executed.
Figure15. Sector Erase Sequence Diagram
32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable
(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The
32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and
three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE)
command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low→sending 32KB Block Erase command→
3-byte address on SI→CS# goes high. The command sequence is shown in Figure16. CS# must be
driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block
Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle
(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
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self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a
block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1 & 1.1) will not
be executed.
Figure16. 32KB Block Erase Sequence Diagram
64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable
(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The
64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and
three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE)
command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low→sending 64KB Block Erase command→
3-byte address on SI→CS# goes high. The command sequence is shown in Figure17. CS# must be
driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block
Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle
(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Block Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset t. A
64KB Block Erase (BE) commands applied to a block which is protected by the Block Protect (BP4,
BP3,BP2, BP1, BP0) bits (see Table1 & 1.1) will not be executed.
Figure17. 64KB Block Erase Sequence Diagram
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Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE)
command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS#
must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low→send Chip Erase command→CS# goes high. The
command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the command
code has been latch in, otherwise the Chip Erase command is not executed. As soon as CS# is driven
high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in
progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write
In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase
(CE) command is executed if the Block protected by (BP2, BP1, BP0) bits. The Chip Erase(CE) command
is ignored if one or more sectors are protected.
Figure18. Chip Erase Sequence Diagram
Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest
consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program
and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if
there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The
Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once
the device has entered the Deep Power- Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The
Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the
device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the
command code on SI. CS# must be driven low for the entire duration of the sequence.
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The Deep Power-Down command sequence: CS# goes low→sending Deep Power-Down command→
CS# goes high. The command sequence is shown in Figure 19. CS# must be driven high after the eighth
bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not
executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to
ICC2 and the Deep Power- Down Mode is entered. Any Deep Power-Down (DP) command, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure19. Deep Power-Down Sequence Diagram
Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read/Device ID command is a multi-purpose command. It can be
used to release the device from the Power-Down state or obtain the devices electronic identification (ID)
number. To release the device from the Power-Down state, the command is issued by driving the CS# pin
low, shifting the instruction code “ABH” and driving CS# high as shown in Figure20. Release from
Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume
normal operation and other command are accepted. The CS# pin must remain high during the tRES1
time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by
driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in
Figure20a. The Device ID value for the ACE25AA160G is listed in Manufacturer and Device Identification
table. The Device ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is
the same as previously described, and shown in Figure 20a, except that after CS# is driven high it must
remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will
resume normal operation and other command will be accepted. If the Release from Power-Down/Device
ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the
command is ignored and will not have any effect on the current cycle.
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Figure20. Release Power-Down Sequence Diagram
Figure20a. Release Power-Down /Read Device ID Sequence Diagram
Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device
ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The
command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit
address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the
falling edge of SCLK with most significant bit (MSB) first is shown in Figure 21. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure21. Read Manufacture ID/Device Sequence Diagram
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Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed
by two bytes of device identification. The device identification indicates the memory type in the first byte,
and the memory capacity of the device in the second byte. Any Read Identification (RDID) command
while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress. The Read identification (RDID) command should not be issued while the device is in Deep
Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is
shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on
Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command
sequence is shown in Figure22. The Read Identification (RDID) command is terminated by driving CS# to
high at any time during data output. When CS# is driven high, the device is put in the Standby Mode.
Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute
commands.
Figure22. Read Identification ID Sequence Diagram
High Speed Mode(HSM)(A3H)
The High Speed Mode (HSM) command must be executed prior to Dual or Quad I/O commands when
operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows
pre-charging of internal charge pumps so the voltages required for accessing the flash memory array are
readily available. The command sequence: CS# goes low Sending A3H command Sending 3-dummy
byte CS# goes high. See Figure23. After the HSM command is executed, the device will maintain a
slightly higher standby current (ICC8) than standard SPI operation. The Release from Power-Down or
HSM command (ABH) can be used to return to standard SPI standby current (ICC1). In addition, Write
Enable command (06H) and Power-Down command (B9H) will also release the device from HSM mode
back to standard SPI standby state.
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Figure23. High Speed Mode Sequence Diagram
Continuous Read Mode Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to
further reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read
operations do not require the BBH/EBH/E7H command code.
Because the ACE25AA160G has no hardware reset pin, so if Continuous Read Mode bits are set to
“AXH”, the ACE25AA160G will not recognize any standard SPI commands. So Continuous Read Mode
Reset command will release the Continuous Read Mode from the “AXH” state and allow standard SPI
command to be recognized. The command sequence is shown in Figure 24.
Figure24. Continuous Read Mode Reset Sequence Diagram
Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sec-
tor/block erase operation and then read data from any other sector or block. The Write Status Register
command (01H) and Erase Security Registers (44H, 42H) and Erase commands (20H, 52H, D8H, C7H,
60H) and Page Program command are not allowed during Program/Erase suspend. Program/Erase
Suspend is valid only during the page program or sector/block erase operation. A maximum of time of
“tSUS” (See AC Characteristics) is required to suspend the program/erase operation
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The Program/Erase Suspend command will be accepted by the device only if the SUS bit in the Status
Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is
on-going. If the SUS bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the
device. The WIP bit will be cleared from 1 to 0 within “tSUS” and the SUS bit will be set from 0 to 1
immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device
and release the suspend state. The command sequence is shown in Figure 25.
Figure25. Program/Erase Suspend Sequence Diagram
Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase
operation after a Program/Erase Suspend command. The Program/Erase command will be accepted by
the device only if the SUS bit equal to 1 and the WIP bit equal to 0. After issued the SUS bit in the status
register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the
Sector or Block will complete the erase operation or the page will complete the program operation. The
Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The
command sequence is shown in Figure 26.
Figure26. Program/Erase Resume Sequence Diagram
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Erase Security Registers (44H)
The ACE25AA160G provides four 256-byte Security Registers which only erased all at once but able to
program individually. These registers may be used by the system manufacturers to store security and
other important information separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable
(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low→sending Erase Security Registers
Command→CS# goes high. The command sequence is shown in Figure 27. CS# must be driven high
after the eighth bit of the command code has been latched in, otherwise the Erase Security Registers
command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle
(whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security
Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security registers. Once the
LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers
command will be ignored.
Address
A23-A16
A15-A10
000000
A9-A0
Security Registers
00000000
Don’t Care
Figure27. Erase Security Registers command Sequence Diagram
VER 1.2 32
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to
256 bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security
Registers command. The Program Security Registers command is entered by driving CS# Low, followed
by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is
driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the
Program Security Registers cycle is in progress, the Status Register may be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program
Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address
A23-A16
00H
A15-A8
01H
A7-A0
Security Register1
Security Register2
Security Register3
Byte Address
Byte Address
Byte Address
00H
02H
00H
03H
Figure28. Program Security Registers command Sequence Diagram
VER 1.2 33
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a
3- byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK.
Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The
address is automatically incremented to the next address after each byte of data is shifted out. Once the
A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is
completed by driving CS# high.
Address
A23-A16
A15-A10
000000
A9-A0
Security Register
00000000
Address
Figure29. Read Security Registers command Sequence Diagram
VER 1.2 34
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will
return to its default power-on state and lose all the current volatile settings, such as Volatile Status
Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting
(P7-P0),Continuous Read Mode bit setting (M7-M0)and Wrap Bit Setting(W6-W4).
The “Reset (99H)” command sequence as follow: CS# goes low→Sending Enable Reset command→
CS# goes high→CS# goes low→Sending Reset command→CS# goes high. Once the Reset command is
accepted by the device, the device will take approximately tRST_R to reset. During this period, no
command will be accepted. Data corruption may happy if there is an on-going or suspended internal
Erase or Program operation when Reset command sequence is accepted by the device. It is
recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset
command sequence.
Figure30. Enable Reset and Reset command Sequence Diagram
VER 1.2 35
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Electrical Characteristics
Power-On Timing
Table3. Power-Up Timing and Write Inhibit Threshold
Symbol
tVSL
Parameter
VCC(min) To CS# Low
Min
10
1
Max
Unit
us
tPUW
Time Delay Before Write Instruction
Write Inhibit Voltage
10
ms
V
VWI
1
2.5
Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The
Status Register contains 00H (all Status Register bits are 0).
Data Retention and Endurance
Parameter
Typical
20
Unit
Years
Cycles
Minimum Pattern Data Retention Time
Erase/Program Endurance
100K
Latch up Characteristics
Parameter
Input Voltage Respect To VSS On I/O Pins
VCC Current
Min
-1.0V
Max
VCC+1.0V
100mA
-100mA
VER 1.2 36
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Capacitance Measurement Condition
Symbol
Parameter
Input Capacitance
Min
Typ
Max
6
Unit
pF
pF
pF
ns
V
Conditions
VIN=0V
C
IN
C
OUT
Output Capacitance
8
VOUT=0V
C
L
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
Figure31. Input Test Waveform and MeasurementLevel
VER 1.2 37
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
DC Characteristics(T=-40℃~85℃,VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ
Max.
Unit
μA
I
Input Leakage Current
Output Leakage Current
Standby Current
±2
LI
I
±2
μA
LO
CS#=VCC VIN=VCC or
VSS
I
12
0.1
15
13
5
5
5
μA
CC1
CS#=VCC VIN=VCC or
VSS
I
Deep Power-Down Current
μA
CC2
CLK=0.1VCC/0.9VCC at
120MHz ,Q=Open(*1I/O)
CLK=0.1VCC/0.9VCC at
80MHz,Open(*1,*2,4I/O)
CLK=0.1VCC/0.9VCC at
50MHz ,Q=Open(*1I/O)
20
I
Operating Current(Read)
18
mA
CC3
7
I
Operating Current(PP)
Operating Current(WRSR)
Operating Current(SE)
Operating Current(BE)
High Speed Current(BE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
10
mA
mA
mA
mA
μA
V
CC4
I
10
CC5
I
10
CC6
I
10
CC7
I
600
800
0.2VCC
VCC+0.4
0.4
CC8
V
-0.5
IL
V
Input High Voltage
0.7VCC
V
IH
V
Output Low Voltage
IOL=1.6mA
IOH=-100uA
V
OL
V
Output High Voltage
VCC-0.2
V
OH
VER 1.2 38
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
AC Characteristics(T=-40℃~85℃,VCC=2.7~3.6V，CL=30pf)
Symbol
Parameter
Min.
Typ
Max.
Unit
Serial Clock Frequency For:Fast Read(0BH),Dual
Output(3BH)
f
C
DC
120
MHz
Serial Clock Frequency For:Dual I/O(BBH), Quad
I/O(EBH),Quad Output(6BH) (Dual I/O & Quad
I/O With High Speed mode)
Serial Clock Frequency For:Dual I/O(BBH), Quad
I/O(EBH), (Dual I/O & Quad I/O Without High
Speed mode)
f
DC
DC
80
120
MHz
MHz
C1
f
40
80
C2
f
R
Serial Clock Frequency For:Read(03H)
Serial Clock High Time
DC
4
MHz
ns
t
CLH
t
CLL
Serial Clock Low Time
4
ns
t
t
CLCH
CHCL
Serial Clock Rise Time(Slew Rate)
Serial Clock Fall Time(Slew Rate)
CS# Active Setup Time
0.2
0.2
5
V/ns
V/ns
ns
t
SLCH
t
t
CHSH
SHCH
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
CS# Not Active Hold Time
5
ns
t
CHSL
5
ns
t
SHSL
SHQZ
CLQX
DVCH
CHDX
CS# High Time (read/write)
20
ns
t
t
Output Disable Time
6
ns
Output Hold Time
1
2
2
5
5
5
5
ns
t
t
Data In Setup Time
ns
Data In Hold Time
ns
t
HLCH
Hold# Low Setup Time(relative to Clock)
Hold# High Setup Time(relative to Clock)
Hold# High Hold Time(relative to Clock)
Hold# Low Hold Time(relative to Clock)
Hold# Low To High-Z Output
Hold# Low To Low-Z Output
Clock Low To Output Valid
ns
t
t
t
HHCH
ns
t
CHHL
CHHH
ns
ns
t
HLQZ
6
6
ns
HHQX
ns
t
CLQV
6.5
ns
t
WHSL
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
20
ns
t
SHWL
tDP
100
ns
0.1
us
VER 1.2 39
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
CS# High To Standby Mode Without Electronic
t
t
RES1
RES2
0.1
0.1
us
us
Signature Read
CS# High To Standby Mode With Electronic
Signature Read
tHSM
CS# High To High Speed mode
0.1
us
tSUS
CS# High To Next Command After Suspend
2
us
us
CS# High To Next Command After Reset
(from read)
tRST_R
20
CS# High To Next Command After Reset
(from program)
CS# High To Next Command After Reset
(from erase)
tRST_P
tRST_E
20
12
us
ms
t
Write Status Register Cycle Time
Page Programming Time
Sector Erase Time
60
0.4
100
500
0.7
ms
ms
ms
s
W
t
t
t
PP
SE
BE
CE
600
Block Erase Time(32K Bytes/64K Bytes)
Chip Erase Time
0.15/0.25 0.8/1.2
20
t
6
s
Max Value 4KB tSE with<50K cycles is 180ms and >50K & <100k cycles is 600ms.
Max Value 32KB tBE with<50K cycles is 0.3s and >50K & <100k cycles is 0.8s.
Max Value 64KB tBE with<50K cycles is 0.5s and >50K & <100k cycles is 1.2s.
The value guaranteed by characterization, not 100% tested in production.
Figure32. Serial Input Timing
VER 1.2 40
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Figure33. Output Timing
Figure34. Hold Timing
VER 1.2 41
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Packaging information
SOP-8
Dimensions In Millimeters
Norm
Symbol
Min
Max
A
A1
A2
b
1.350
0.100
1.300
0.330
0.190
4.700
3.800
1.750
0.250
1.500
0.510
0.250
5.000
4.000
c
D
4.900
3.900
1.270
6.000
0.350
0.635
1.040
E1
e
E
5.800
0.250
0.508
0.837
0°
6.200
0.500
0.762
1.243
8°
h
L
L1
θ
VER 1.2 42
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Packaging information
SOP-8L (208mil)
Dimensions In Millimeters
Symbol
Min
Norm
1.950
Max
A
A1
A2
b
1.750
0.050
1.700
0.350
0.190
5.130
7.700
5.180
2.160
0.250
1.910
0.480
0.250
5.330
8.100
5.380
0.150
1.800
0.420
c
0.200
D
5.230
E
7.900
E1
e
5.280
1.270 BSC
0.650
L
0.500
0°
0.800
8°
θ
VER 1.2 43
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Packaging information
TSSOP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
D
E
2.900
4.300
0.190
0.090
6.250
3.100
4.500
0.300
0.200
6.550
1.200
1.000
0.150
0.114
0.169
0.007
0.004
0.246
0.122
0.177
0.012
0.008
0.258
0.047
0.039
0.006
b
c
E1
A
A2
A1
e
0.800
0.050
0.031
0.002
0.65 (BSC)
0.25 (TYP)
0.026 (BSC)
L
0.500
1°
0.700
7°
0.020
0.028
H
0.01 (TYP)
θ
1°
7°
VER 1.2 44
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Packaging information
USON3*2-8
Dimensions In Millimeters
Symbol
Min
Norm
0.550
Max
A
A1
b
0.500
0.000
0.180
0.100
1.900
1.500
0.600
0.050
0.030
0.200
2.100
1.700
0.020
0.250
c
0.150
D
2.000
D2
e
1.600
0.500BSC
1.500BSC
3.000
Nd
E
2.900
0.100
0.300
0.050
0.050
3.100
0.300
0.400
0.150
0.250
E2
L
0.200
0.350
L1
h
0.100
0.150
VER 1.2 45
ACE25AA160G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.2 46
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