ACE25QA200GFMLTH [ACE]
2M BIT SPI NOR FLASH;型号: | ACE25QA200GFMLTH |
厂家: | ACE TECHNOLOGY CO., LTD. |
描述: | 2M BIT SPI NOR FLASH |
文件: | 总30页 (文件大小:1026K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ACE25QA200G
2M BIT SPI NOR FLASH
Description
The ACE25QA200 is 2M-bit Serial Peripheral Interface (SPI) Flash memory, and supports the Dual SPI:
Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO). The Dual Output data is transferred with speed of
108Mbits/s. The device uses a single low voltage power supply, ranging from 2.7 Volt to 3.6 Volt.
Additionally, the device supports JEDEC standard manufacturer and device ID.
In order to meet environmental requirements, offers an 8-pin SOP, an 8-pin SOP 208mil, an 8-pin TSSOP ,
an 8-pin DIP , an 8-pad USON 3x2-mm packages.
Features
Serial Peripheral Interface (SPI)
Standard SPI: SCLK, /CS, SI, SO, /WP
Dual SPI: SCLK, /CS, IO0, IO1, /WP
Read
Normal Read (Serial): 55MHz clock rate
Fast Read (Serial): 108MHz clock rate
Dual Read: 108MHz clock rate
Program
Serial-input Page Program up to 256bytes
Erase
Block erases (64/32 KB)
Sector erases (4 KB)
Chip erase
Program/Erase Speed
Page Program time: 0.7ms typical
Sector Erase time: 100ms typical
Block Erase time: 0.3/0.5s typical
Chip Erase time: 3/2s typical
Flexible Architecture
Sector of 4K-byte
Block of 32/64K-byte
Low Power Consumption
20mA maximum active current
5uA maximum power down current
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ACE25QA200G
2M BIT SPI NOR FLASH
Software/Hardware Write Protection
Enable/Disable protection with WP Pin
Write protect all/portion of memory via software
Top or Bottom, Sector or Block selection
Single Supply Voltage
Full voltage range: 2.7~3.6V
Temperature Range
Industrial (-40℃ to +85℃)
Cycling Endurance/Data Retention
Typical 100k Program-Erase cycles on any sector
Typical 20-year data retention at +55℃
Advanced Feature
64 bits Unique ID for each device
Packaging Type
SOP-8 / SOP-8L
TSSOP-8
DIP-8
USON3*2-8
Ordering information
ACE25QA200G XXX + X H
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
FM: SOP-8
FML: SOP-8L (208mil)
TM: TSSOP-8
DP: DIP-8
UA8: USON3*2-8
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2M BIT SPI NOR FLASH
Signal Description
During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max).
All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, see
Section 8.6, DC Electrical Characteristics). These signals are described next.
Table 1. Signal Names
Pin No Pin Name I/O
Description
1
2
3
4
5
6
7
8
/CS
I
Chip Select
SO (IO1) I/O
Serial Output for single bit data Instructions. IO1 for Dual Instructions.
/WP (IO2)
VSS
I
Write Protect in single bit
Ground
Serial Input for single bit data Instructions. IO0 for Dual Instructions.
Serial Clock
SI (IO0) I/O
SCLK
NC
I
No Connection
VCC
Core and I/O Power Supply
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ACE25QA200G
2M BIT SPI NOR FLASH
Block/Sector Architecture
Table 2. Block/Sector Addresses of ACE25QA200
Memory
Sector
Block(64k byte) Block(32k byte)
Density
Sector No.
Sector 0
Address range
Size(KB)
4
000000h-000FFFh
Half block 0
Block 0
Sector 7
Sector 8
4
4
4
4
4
007000h-007FFFh
008000h-008FFFh
Half block 1
Sector 15
Sector 16
00F000h-00FFFFh
010000h-010FFFh
Half block 2
Block 1
Sector 23
Sector 24
4
4
017000h-017FFFh
018000h-018FFFh
Half block 3
Sector 31
Sector 32
4
4
01F000h-01FFFFh
020000h-020FFFh
2Mbit
Half block 4
Block 2
Sector 39
Sector 40
4
4
027000h-027FFFh
028000h-028FFFh
Half block 5
Sector 47
Sector 48
4
4
02F000h-02FFFFh
030000h-030FFFh
Half block 6
Block 3
Sector 55
Sector 56
4
4
037000h-037FFFh
038000h-038FFFh
Half block 7
Sector 63
4
03F000h-03FFFFh
Notes:
1. Block = Uniform Block, and the size is 64K bytes.
2. Half block = Half Uniform Block, and the size is 32kbytes.
3. Sector = Uniform Sector, and the size is 4K bytes.
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2M BIT SPI NOR FLASH
SPI Operation
Standard SPI Instructions
The ACE25QA200 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input
data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI Instructions
The ACE25QA200 supports Dual SPI operation when using the “Dual Output Fast Read” (3BH) instructions.
These instructions allow data to be transferred to or from the device at two times the rate of the standard SPI.
When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Operation Features
Supply Voltage
(A) Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the
specified [VCC(min), VCC(max)] range must be applied (see operating ranges). In order to secure a
stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually
of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable
and valid until the end of the transmission of the instruction and, for a Write instruction, until the
completion of the internal write cycle (tW).
(B) Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the
Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore
recommended to connect the /CS line to VCC via a suitable pull-up resistor.
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive
as well as level sensitive: after power-up, the device does not become selected until a falling edge has
first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High,
prior to going Low to start the first operation.
(C) Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on
reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC
has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC
operating voltage defined in operating ranges).
When VCC has passed the POR threshold, the device is reset.
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2M BIT SPI NOR FLASH
(D) Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating
voltage to below the power on reset threshold voltage, the device stops responding to any instruction
sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to
follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal
Write cycle in progress).
Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes
ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the
device then goes in to the Standby Power mode, and the device consumption drops to ICC1.
Status Register
Table 3. Status Register
S7
S6
S5
S4
S3
S2
S1
S0
SRP
Reserved Reserved
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,
when WIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction isaccepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase instructions. These bits are written with the Write Status Register
instruction. When the Block Protect (BP2, BP1, and BP0) bits are set to 1, the relevant memory area.
Becomes protected against Page Program, Sector Erase and Block Erase instructions. The Block Protect
(BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.
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2M BIT SPI NOR FLASH
SRP bits
The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The
Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware
Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven
Low. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, and BP0) become read-only
bits and the Write Status Register (WRSR) instruction is not execution. The default value of SRP is 0.
Write Protect Features
(A) Software Protection: The Block Protect (BP2, BP1, and BP0) bits define the section of the memory
array that can be read but not change.
(B) Hardware Protection: /WP going low to protected the BP0~BP2 bits and SRP bits.
(C) Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the Release from
deep Power-Down Mode instruction.
(D) Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program, Sector Erase,
Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.
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2M BIT SPI NOR FLASH
Status Register Memory Protection
Protect Table
Table 4. ACE25QA200 Status Register Memory Protection
Status Register Content
Memory Content
Addresses
BP2
0
BP1
0
BP0
0
Blocks
Density
NONE
504KB
496KB
480KB
448KB
384KB
256KB
512KB
Portion
NONE
NONE
NONE
0
0
1
Sector 0 to 125
Sector 0 to 123
Sector 0 to 119
Sector 0 to 111
Sector 0 to 95
Sector 0 to 63
ALL
070000H-07FFFFH
060000H-07FFFFH
040000H-07FFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
Upper 126/128
Upper 124/128
Upper 120/128
Lower 112/128
Lower 96/128
Lower 64/128
ALL
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Device Identification
Three legacy Instructions are supported to access device identification that can indicate the manufacturer,
device type, and capacity (density). The returned data bytes provide the information as shown in the below
table.
Table 5. ACE25QA200 ID Definition table
Operation Code
M7-M0
68
ID15-ID8
40
ID7-ID0
13
9FH
90H
ABH
68
12
12
Instructions Description
All instructions, addresses and data are shifted in and out of the device, beginning with the most significant
bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be
shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
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ACE25QA200G
2M BIT SPI NOR FLASH
See Table 6, every instruction sequence starts with a one-byte instruction code. Depending on the instruction,
this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after
the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read
Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence
is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being
shifted out.
For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is /CS must drive high when the number of
clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the
input byte is not a full byte, nothing will happen and WEL will not be reset.
Table 6. Instruction Set Table
Instruction Name
Write Enable
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Write Disable
04H
Read Status Register
Write Status Register
Read Data
05H
(S7-S0)
(S7-S0)
01H
03H
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
(D7-D0)
(D7-D0)
Next byte
(D7-D0)
(D7-D0)(NOTES)
Fast Read
0BH
3BH
02H
Dual Output Fast Read
Page Program
Next byte
Page Program
F2H
20H
Next byte
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
52H
D8H
C7/60H
B9H
Deep Power-Down
Release From Deep
Power-Down, And Read
Device ID
ABH
dummy
dummy
dummy
(ID7-ID0)
(M7-M0)
Release From Deep
Power-Down
ABH
Manufacturer/ Device ID
JEDEC ID
90H
9FH
dummy
dummy
00H
(ID7-ID0)
(M7-M0)
(ID15-ID8)
(ID7-ID0)
Notes: Dual Output data
IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1)
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2M BIT SPI NOR FLASH
Configuration and Status Instructions
Write Enable (06H)
See Figure 1, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable
Latch bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write
Status Register instruction. The Write Enable instruction sequence: /CS goes low sending the Write
Enable instruction /CS goes high.
Figure 1. Write Enable Sequence Diagram
Write Disable (04H)
See Figure 2, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable
instruction sequence: /CS goes low sending the Write Disable instruction /CS goes high. The WEL bit is
reset by following condition: Power-up and upon completion of the Write Status Register, Page Program,
Sector Erase, Block Erase and Chip Erase instructions.
Figure 2. Write Disable Sequence Diagram
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2M BIT SPI NOR FLASH
Read Status Register (05H)
See Figure 3 the Read Status Register (RDSR) instruction is for reading the Status Register. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before
sending a new instruction to the device. It is also possible to read the Status Register continuously. For
instruction code “05H”, the SO will output Status Register bits S7~S0.
Figure 3. Read Status Register Sequence Diagram
Write Status Register (01H)
See Figure 4, the Write Status Register instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write
Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5
are always read as 0. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched
in. If not, the Write Status Register instruction is not executed. As soon as Chip Select (CS#) is driven High,
the self-timed Write Status Register cycle (the duration is tW) is initiated. While the Write Status Register
cycle is in progress, reading Status Register to check the Write In Progress (WIP) bit is achievable. The Write
In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the completion of
theWrite Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0. The Write
Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1,
and BP0) bits, which are utilized to define the size of the read-only area. The Write Status Register (WRSR)
instruction also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the
Write Protect (WP#) signal, by setting which the device can enter into Hardware Protected Mode (HPM). The
Write Status Register (WRSR) instruction is not executed once enter into the Hardware Protected Mode
(HPM).
Figure 4. Write Status Register Sequence Diagram
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2M BIT SPI NOR FLASH
Read Instructions
Read Data (03H)
See Figure 5, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit
being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on
SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is
automatically incremented to the next higher address after each byte of data is shifted out allowing for a
continuous stream of data. This means that the entire memory can be accessed with a single command as
long as the clock continues. The command is completed by driving /CS high. The whole memory can be read
with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase,
Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Normal read mode running up to 50MHz.
Figure 5. Read Data Bytes Sequence Diagram
Fast Read (0BH)
See Figure 6, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out. It
is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge
of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The address
is automatically incremented to the next higher address after each byte of data is shifted out.
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Figure 6. Fast Read Sequence Diagram
ACE25QA200G
2M BIT SPI NOR FLASH
Dual Output Fast Read (3BH)
See Figure 7, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy
byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit
per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out
Figure 7. Dual Output Fast Read Sequence Diagram
ID and Security Instructions
Read Manufacture ID/ Device ID (90H)
See Figure 8, the Read Manufacturer/Device ID instruction is an alternative to the Release from
Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific
Device ID.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a
24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
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Figure 8. Read Manufacture ID/ Device ID Sequence Diagram
ACE25QA200G
2M BIT SPI NOR FLASH
JEDEC ID (9FH)
The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of
device identification. The device identification indicates the memory type in the first byte, and the memory
capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in
progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction should
not be issued while the device is in Deep Power-Down Mode.
See Figure 9, he device is first selected by driving /CS to low. Then, the 8-bit instruction code for the
instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted
out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The JEDEC ID
instruction is terminated by driving /CS to high at any time during data output. When /CS is driven high, the
device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can
receive, decode and execute instructions.
Figure 9. JEDEC ID Sequence Diagram
Deep Power-Down (B9H)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down
(DPD) instruction especially useful for battery powered applications (see ICC1 and ICC2). The instruction is
initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 10.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power
down instruction will not be executed. After /CS is driven high, the power-down state will entered within the
time duration of tDP. While in the power-down state only the Release from Deep Power-down / Device ID
instruction, which restores the device to normal operation, will be recognized. All other Instructions are
ignored. This includes the Read Status Register instruction, which is always available during normal
operation. Ignoring all but one instruction also makes the Power Down state a useful condition for securing
maximum write protection. The device always powers-up in the normal operation with the standby current of
ICC1.
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Figure 10. Deep Power-Down Sequence Diagram
ACE25QA200G
2M BIT SPI NOR FLASH
Release from Deep Power-Down/Read Device ID (ABH)
The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the Power-Down state or obtain the devices electronic identification (ID) number.
See Figure 11, to release the device from the Power-Down state, the instruction is issued by driving the /CS
pin low, shifting the instruction code “ABH” and driving /CS high Release from Power-Down will take the time
duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
instruction are accepted. The /CS pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits
are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 12.
The Device ID value for the ACE25QA200.400 is listed in Manufacturer and Device Identification table. The
Device ID can be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the
same as previously described, and shown in Figure 12, except that after /CS is driven high it must remain
high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume
normal operation and other instruction will be accepted. If the Release from Power-Down/Device ID
instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction
is ignored and will not have any effects on the current cycle.
Figure 11. Release Power-Down Sequence Diagram
Figure 12. Release Power-Down/Read Device ID Sequence Diagram
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2M BIT SPI NOR FLASH
Program and Erase Instructions
Page Program (02H)
The Page Program instruction is for programming the memory. A Write Enable instruction must previously
have been executed to set the Write Enable Latch bit before sending the Page Program instruction.
See Figure 13, the Page Program instruction is entered by driving /CS Low, followed by the instruction code,
3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current page are programmed from the start address of
the same page (from the address whose 8 least significant bits (A7-A0) are all zero). /CS must be driven low
for the entire duration of the sequence. The Page Program instruction sequence: /CS goes low sending
Page Program instruction 3-byte address on SI at least 1 byte data on SI /CS goes high. If more than 256
bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device,
they are correctly programmed at the requested addresses without having any effects on the other bytes of
the same page. /CS must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Page Program instruction is not executed.
As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is
reset.
A Page Program instruction applied to a page which is protected by the Block Protect (BP2, BP1, and BP0)
bits is not executed.
Figure 13. Page Program Sequence Diagram
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2M BIT SPI NOR FLASH
Fast Page Program (FPP) (F2H)
The Fast Page Program (FPP) instruction is for programming the memory. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit before sending the Page Program
instruction.
See Figure 14, the Page Program instruction is entered by driving /CS Low, followed by the instruction code,
3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current page are programmed from the start address of
the same page (from the address whose 8 least significant bits (A7-A0) are all zero). /CS must be driven low
for the entire duration of the sequence. The Page Program instruction sequence: /CS goes low sending
Page Program instruction 3-byte address on SI at least 1 byte data on SI /CS goes high. If more than 256
bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device,
they are correctly programmed at the requested addresses without having any effects on the other bytes of
the same page. /CS must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Page Program instruction is not executed.
As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is
reset.
A Fast Page Program instruction applied to a page which is protected by the Block Protect (BP2, BP1, and
BP0) bits is not executed.
Figure 14. Page Program Sequence Diagram
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ACE25QA200G
2M BIT SPI NOR FLASH
Sector Erase (20H)
The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit. The Sector Erase instruction is entered by
driving /CS low, followed by the instruction code, and 3-address byte on SI. Any address inside the sector is
a valid address for the Sector Erase instruction. /CS must be driven low for the entire duration of the
sequence.
See Figure 15, The Sector Erase instruction sequence: /CS goes low sending 64KB Block Erase instruction
3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address byte has
been latched in; otherwise the Sector Erase instruction is not executed. As soon as /CS is driven high, the
self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch bit is reset. A Sector Erase instruction applied to a
sector which is protected by the Block Protect (BP2, BP1, and BP0) bits is not executed.
Figure 15. Sector Erase Sequence Diagram
32KB Block Erase (52H)
The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction
must previously have been executed to set the Write Enable Latch bit. The 32KB Block Erase instruction is
entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside
the block is a valid address for the 32KB Block Erase instruction. /CS must be driven low for the entire
duration of thesequence.
See Figure 16, the 32KB Block Erase instruction sequence: /CS goes low sending 32KB Block Erase
instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the 32KB Block Erase instruction is not executed. As soon as
/CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block
Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. TheWrite In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 32KB Block
Erase instruction applied to a block which is protected by the Block Protect (BP2, BP1, and BP0) bits is not
executed.
VER 1.2 18
Figure 16. 32KB Block Erase Sequence Diagram
ACE25QA200G
2M BIT SPI NOR FLASH
64KB Block Erase (D8H)
The 64KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction
must previously have been executed to set the Write Enable Latch bit. The 64KB Block Erase instruction is
entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside
the block is a valid address for the 64KB Block Erase instruction. /CS must be driven low for the entire
duration of thesequence.
See Figure 17, the 64KB Block Erase instruction sequence: /CS goes low sending 64KB Block Erase
instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the 64KB Block Erase instruction is not executed. As soon as
/CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block
Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 64KB Block
Erase instruction applied to a block which is protected by the Block Protect (BP2, BP1, and BP0) bits is not
executed.
Figure 17. 64KB Block Erase Sequence Diagram
Chip Erase (60/C7H)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register
bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 18.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence
for a time duration of tCE. While the Chip Erase cycle is in progress, the Read Status Register instruction
may still be accessed to check the status of the WIPbit.
The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to
accept other Instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected
by the Block Protect (BP2, BP1, and BP0) bits.
VER 1.2 19
Figure 18. Chip Erase Sequence Diagram
ACE25QA200G
2M BIT SPI NOR FLASH
Electrical Characteristics
Absolute Maximum Ratings
Parameters
Symbol
VCC
Conditions
Range
–0.5 to 4
–0.5 to 4
Unit
V
Supply Voltage
Voltage Applied to Any Pin
VIO
Relative to Ground
<20nS Transient Relative to
Ground
V
Transient Voltage on any Pin
VIOT
–2.0Vto VCC+2.0V
V
℃
Storage Temperature
Electrostatic Discharge Voltage
Notes:
TSTG
VESD
–65 to +150
(Notes)
–2000 to +2000
V
Human Body Model
JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms)
Operating Ranges
SPEC
Parameter
Symbol
Conditions
Unit
Min
2.7
0
Max
3.6
Supply Voltage
VCC
V
Commercial
Industrial
+70
+85
Temperature Operating
TA
℃
-40
Data Retention and Endurance
Parameter
Test Condition
150°C
Min
10
Units
Years
Years
Cycles
Minimum Pattern Data Retention Time
Erase/Program Endurance
125°C
20
-40 to 85°C
100K
VER 1.2 20
ACE25QA200G
2M BIT SPI NOR FLASH
Latch up Characteristics
Parameter
Min
Max
Input Voltage Respect To VSS On I/O Pins
VCC Current
-1.0V
VCC+1.0V
100mA
-100mA
Power-up Timing
Symbol
Parameter
Min Max Unit
tVSL
VCC(min) To /CS Low
300
us
Figure 19. Power-up Timing and Voltage Levels
VER 1.2 21
ACE25QA200G
2M BIT SPI NOR FLASH
DC Electrical Characteristics(T= -40℃~85℃, VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ
Max. Unit.
ILI
Input Leakage Current
Output Leakage Current
±2
±2
µA
µA
ILO
/CS=VCC, VIN=VCC
or VSS
ICC1
ICC2
Standby Current
13
2
25
5
µA
µA
/CS=VCC, VIN=VCC
or VSS
Deep Power-Down Current
SCLK=0.1VCC/0.9VCC(1)
ICC3
Operation Current:(Read)
at 108MHz,
13
18
mA
Q=Open(*1,*2,*4 I/O)
/CS=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
Operating Current(PP)
Operating Current(WRSR)
Operating Current(Sector Erase)
Operating Current(Block Erase)
Operating Current (Chip Erase)
Input Low Voltage
15
5
mA
mA
mA
mA
mA
V
/CS=VCC
/CS=VCC
20
/CS=VCC
20
/CS=VCC
20
-0.5
0.2VCC
VCC+0.4
0.4
VIH
Input High Voltage
0.8VCC
V
VOL
VOH
Output Low Voltage
IOL =100µA
IOH =-100µA
V
Output High Voltage
VCC-0.2
V
Note :( 1) ICC3 is measured with ATE loading
AC Measurement Conditions
Symbol
CL
Parameter
Min
Tpy
Max
Unit
pF
Load Capacitance
Input Rise And Fall time
30
5
TR, TF
ns
VIN
IN
Input Pause Voltage
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
0.5VCC
V
V
Input Timing Reference Voltage
Output Timing Reference Voltage
OUT
V
Figure 20.
AC Measurement I/O Waveform
VER 1.2 22
ACE25QA200G
2M BIT SPI NOR FLASH
AC Electrical Characteristics
Symbol
Parameter
Min.
DC.
DC.
4
Typ.
Max.
108
55
Unit.
MHz
MHz
ns
fc
Clock frequency for all instructions, except Read Data(03H)
Clock freq. Read Data instruction(03H)
Serial Clock High Time
fR
tCLH
tCLL
Serial Clock Low Time
4
ns
tCLCH Serial Clock Rise Time (Slew Rate)
tCHCL Serial Clock Fall Time (Slew Rate)
tSLCH /CS Active Setup Time
0.1(1)
0.1(1)
5
V/ns
V/ns
ns
tCHSH /CS Active Hold Time
5
ns
tSHCH /CS Not Active Setup
tCHSL /CS Not Active Hold Time
/CS High Time(read/write)
Time
5
ns
5
ns
tSHSL
20
ns
tSHQZ Output
tCLQX Output
Disable Time
Hold Time
6
7
ns
0
2
2
ns
tDVCH Data In Setup Time
ns
tCHDX Data In Hold Time
ns
tCLQV Clock Low To Output Valid
tWHSL Write Protect Setup Time Before /CS Low
tSHWL Write Protect Hold Time After /CS High
ns
20
ns
100
ns
tDP
/CS High To Deep Power-Down Mode
0.1
3
µs
/CS High To Standby Mode Without Electronic Signature
Read
tRES1
µs
tRES2 /CS High To Standby Mode With Electronic Signature Read
1.5
15
µs
ms
ms
ms
s
tW
Write Status Register Cycle Time
Page Programming Time
Sector Erase Time
10
0.7
100
tPP
tSE
tBE
tCE
2.4
300
Block Erase Time(32K Bytes/64K Bytes)
Chip Erase Time
0.3/0.5 2.5/3.0
3/2 7.5/5
s
Note: (1)Tested with clock frequency lower than 50 MHz.
VER 1.2 23
ACE25QA200G
2M BIT SPI NOR FLASH
Figure 21. Serial Input Timing
Figure 22. Output Timing
VER 1.2 24
ACE25QA200G
2M BIT SPI NOR FLASH
Packaging information
SOP-8
mm
Inch
Symbol
Min
Nom
Max
1.75
0.20
1.55
0.51
0.25
5.03
6.20
4.00
Min
Nom
Max
0.069
0.008
0.061
0.020
0.010
0.198
0.244
0.158
A
A1
A2
b
0.10
1.35
0.36
0.15
4.77
5.80
3.80
0.15
1.45
0.41
0.20
4.90
5.99
3.90
1.27
0.66
1.05
0.54
5
0.004
0.053
0.014
0.006
0.188
0.228
0.150
0.006
0.057
0.016
0.008
0.193
0.236
0.154
0.05
C
D
E
E1
e
L
0.46
0.85
0.41
0
0.86
1.25
0.67
8
0.018
0.033
0.016
0
0.026
0.041
0.021
5
0.034
0.049
0.026
8
L1
S
θ
VER 1.2 25
ACE25QA200G
2M BIT SPI NOR FLASH
Packaging information
SOP-8L(208mil)
mm
Inch
Symbol
Min
Nom
Max
2.16
0.25
1.91
0.51
0.25
5.33
8.10
5.38
Min
Nom
Max
0.085
0.010
0.075
0.020
0.010
0.210
0.319
0.212
A
A1
A2
b
0.05
1.70
0.36
0.19
5.13
7.70
5.18
0.15
1.80
0.41
0.20
5.23
7.90
5.28
1.27
0.65
1.31
0.74
5
0.002
0.067
0.014
0.007
0.202
0.303
0.204
0.006
0.071
0.016
0.008
0.206
0.311
0.208
0.050
0.026
0.052
0.029
5
C
D
E
E1
e
L
0.50
1.21
0.62
0
0.80
1.41
0.88
8
0.020
0.048
0.024
0
0.031
0.056
0.035
8
L1
S
θ
VER 1.2 26
ACE25QA200G
2M BIT SPI NOR FLASH
Packaging information
TSSOP-8
mm
Inch
Symbol
Min
Nom
Max
1.20
0.15
1.05
0.30
0.17
3.10
6.60
4.50
Min
Nom
Max
0.047
0.006
0.041
0.012
0.007
0.122
0.260
0.177
A
A1
A2
b
0.05
0.90
0.20
0.13
2.90
6.20
4.30
0.002
0.035
0.008
0.005
0.144
0.244
0.169
1.00
0.039
C
D
3.00
6.40
4.40
0.65
0.118
0.252
0.173
0.026
E
E1
e
L
0.45
0
0.75
8
0.018
0
0.030
8
L1
θ
1.00
0.039
VER 1.2 27
ACE25QA200G
2M BIT SPI NOR FLASH
Packaging information
DIP-8
mm
Inch
Symbol
Min
Nom
Max
Min
Nom
Max
A
A1
A2
b
5.33
0.21
0.38
3.18
0.36
1.14
0.20
9.02
7.62
6.22
0.015
0.125
0.014
0.045
0.008
0.355
0.300
0.245
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
8.89
3.30
1.14
3.43
0.56
1.78
0.36
10.16
8.13
6.48
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.10
0.135
0.022
0.070
0.014
0.400
0.320
0.255
B1
C
D
E
E1
e
eB
SL
S
7.87
2.92
0.76
9.53
3.81
1.52
0.310
0.115
0.030
0.350
0.130
0.045
0.375
0.150
0.060
VER 1.2 28
ACE25QA200G
2M BIT SPI NOR FLASH
Packaging information
USON3*2-8
mm
Nom
Symbol
Min
0.40
0
Max
A
A1
b
0.50
0.55
0.05
0.30
0.02
0.18
0.25
b1
c
0.16REF
0.15
0.10
1.90
1.40
0.20
2.10
1.60
D
2.00
D2
e
1.50
0.50BSC
1.50BSC
3.00
Nd
E
2.90
1.50
0.30
0.20
3.10
1.70
0.50
0.30
E2
L
1.60
0.40
h
0.25
VER 1.2 29
ACE25QA200G
2M BIT SPI NOR FLASH
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD. As
sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.2 30
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