ACE25QA400GUA8TH_技术文档

ACE25QA400G

4M BIT SPI NOR FLASH

Description

The ACE25QA400 is 4M-bit Serial Peripheral Interface (SPI) Flash memory, and supports the Dual SPI:

Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO). The Dual Output data is transferred with speed of

108Mbits/s. The device uses a single low voltage power supply, ranging from 2.7 Volt to 3.6 Volt.

Additionally, the device supports JEDEC standard manufacturer and device ID.

In order to meet environmental requirements, offers an 8-pin SOP, an 8-pin SOP 208mil, an 8-pin TSSOP ,

an 8-pin DIP , an 8-pad USON 3x2-mm packages.

Features



Serial Peripheral Interface (SPI)

Standard SPI: SCLK, /CS, SI, SO, /WP

Dual SPI: SCLK, /CS, IO0, IO1, /WP

Read



Normal Read (Serial): 55MHz clock rate

Fast Read (Serial): 108MHz clock rate

Dual Read: 108MHz clock rate

Program



Serial-input Page Program up to 256bytes

Erase

Block erases (64/32 KB)

Sector erases (4 KB)

Chip erase



Program/Erase Speed

Page Program time: 0.7ms typical

Sector Erase time: 100ms typical

Block Erase time: 0.3/0.5s typical

Chip Erase time: 3/2s typical

Flexible Architecture



Sector of 4K-byte

Block of 32/64K-byte

Low Power Consumption

20mA maximum active current

5uA maximum power down current

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ACE25QA400G

4M BIT SPI NOR FLASH



Software/Hardware Write Protection

Enable/Disable protection with WP Pin

Write protect all/portion of memory via software

Top or Bottom, Sector or Block selection

Single Supply Voltage



Full voltage range: 2.7~3.6V

Temperature Range

Commercial (0℃ to +70℃)

Industrial (-40℃ to +85℃)



Cycling Endurance/Data Retention

Typical 100k Program-Erase cycles on any sector

Typical 20-year data retention at +55℃

Advanced Feature

64 bits Unique ID for each device

Packaging Type

SOP-8 / SOP-8L

TSSOP-8

DIP-8

USON3*2-8

Ordering information

ACE25QAXXXG XXX + X H

Halogen-free

U: Tube

T: Tape and Reel

Pb - free

FM: SOP-8

FML: SOP-8L (208mil)

TM: TSSOP-8

DP: DIP-8

UA8: USON3*2-8

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400: 4M bit

ACE25QA400G

4M BIT SPI NOR FLASH

Signal Description

During all operations, V_CCmust be held stable and within the specified valid range: V_CC(min) to V_CC(max).

All of the input and output signals must be held High or Low (according to voltages of V_IH, V_OH, V_ILor V_OL, see

Section 8.6, DC Electrical Characteristics). These signals are described next.

Table 1. Signal Names

Pin No Pin Name I/O

Description

1

2

3

4

5

6

7

8

/CS

I

Chip Select

SO (IO1) I/O

Serial Output for single bit data Instructions. IO1 for Dual Instructions.

/WP (IO2)

VSS

I

Write Protect in single bit

Ground

Serial Input for single bit data Instructions. IO0 for Dual Instructions.

Serial Clock

SI (IO0) I/O

SCLK

NC

I

No Connection

VCC

Core and I/O Power Supply

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4M BIT SPI NOR FLASH

Block/Sector Architecture

Table 2. Block/Sector Addresses of ACE25QA400

Memory

Sector

Block(64k byte) Block(32k byte)

Density

Sector No.

Sector 0

Address range

Size(KB)

4

000000h-000FFFh

Half block 0

Block 0

Sector 7

Sector 8

4

007000h-007FFFh

008000h-008FFFh

4

Half block 1

Sector 15

Sector 16

00F000h-00FFFFh

010000h-010FFFh

Half block 2

Block 1

Sector 23

Sector 24

4

017000h-017FFFh

018000h-018FFFh

Half block 3

Sector 31

Sector 96

4

01F000h-01FFFFh

060000h-060FFFh

4Mbit

Half block 12

Block 6

Sector 103

Sector 104

4

067000h-067FFFh

068000h-068FFFh

Half block 13

Sector 111

Sector 112

4

06F000h-06FFFFh

070000h-070FFFh

Half block 14

Block 7

Sector 119

Sector 120

4

077000h-077FFFh

078000h-078FFFh

Half block 15

Sector 127

4

07F000h-07FFFFh

Notes:

1. Block = Uniform Block, and the size is 64K bytes.

2. Half block = Half Uniform Block, and the size is 32kbytes.

3. Sector = Uniform Sector, and the size is 4K bytes.

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4M BIT SPI NOR FLASH

SPI Operation

Standard SPI Instructions

The ACE25QA400 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select

(/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input

data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI Instructions

The ACE25QA400 supports Dual SPI operation when using the “Dual Output Fast Read” (3BH) instructions.

These instructions allow data to be transferred to or from the device at two times the rate of the standard SPI.

When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1.

Operation Features

Supply Voltage

(A) Operating Supply Voltage

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the

specified [VCC(min), VCC(max)] range must be applied (see operating ranges). In order to secure a

stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually

of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable

and valid until the end of the transmission of the instruction and, for a Write instruction, until the

completion of the internal write cycle (tW).

(B) Power-up Conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the

Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore

recommended to connect the /CS line to VCC via a suitable pull-up resistor.

In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive

as well as level sensitive: after power-up, the device does not become selected until a falling edge has

first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High,

prior to going Low to start the first operation.

(C) Device Reset

In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on

reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC

has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC

operating voltage defined in operating ranges).

When VCC has passed the POR threshold, the device is reset.

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4M BIT SPI NOR FLASH

(D) Power-down

At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating

voltage to below the power on reset threshold voltage, the device stops responding to any instruction

sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to

follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal

Write cycle in progress).

Active Power and Standby Power Modes

When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes

ICC.

When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the

device then goes in to the Standby Power mode, and the device consumption drops to ICC1.

Status Register

Table 3. Status Register

S7

S6

S5

S4

S3

S2

S1

S0

SRP

Reserved Reserved

BP2

BP1

BP0

WEL

WIP

The status and control bits of the Status Register are as follows:

WIP bit

The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register

progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,

when WIP bit sets 0, means the device is not in program/erase/write status register progress.

WEL bit

The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal

Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register,

Program or Erase instruction isaccepted.

BP2, BP1, BP0 bits

The Block Protect (BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software

protected against Program and Erase instructions. These bits are written with the Write Status Register

instruction. When the Block Protect (BP2, BP1, and BP0) bits are set to 1, the relevant memory area.

Becomes protected against Page Program, Sector Erase and Block Erase instructions. The Block Protect

(BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.

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4M BIT SPI NOR FLASH

SRP bits

The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The

Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware

Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven

Low. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, and BP0) become read-only

bits and the Write Status Register (WRSR) instruction is not execution. The default value of SRP is 0.

Write Protect Features

(A) Software Protection: The Block Protect (BP2, BP1, and BP0) bits define the section of the memory

array that can be read but not change.

(B) Hardware Protection: /WP going low to protected the BP0~BP2 bits and SRP bits.

(C) Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the Release from

deep Power-Down Mode instruction.

(D) Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program, Sector Erase,

Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.

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4M BIT SPI NOR FLASH

Status Register Memory Protection

Protect Table

Table 4. ACE25QA400 Status Register Memory Protection

Status Register Content

Memory Content

Addresses

BP2

0

BP1

0

BP0

0

Blocks

Density

NONE

504KB

496KB

480KB

448KB

384KB

256KB

512KB

Portion

NONE

0

1

Sector 0 to 125

Sector 0 to 123

Sector 0 to 119

Sector 0 to 111

Sector 0 to 95

Sector 0 to 63

ALL

070000H-07FFFFH

060000H-07FFFFH

040000H-07FFFFH

000000H-00FFFFH

000000H-01FFFFH

000000H-03FFFFH

000000H-07FFFFH

Upper 126/128

Upper 124/128

Upper 120/128

Lower 112/128

Lower 96/128

Lower 64/128

ALL

0

1

0

1

0

1

0

1

0

1

Device Identification

Three legacy Instructions are supported to access device identification that can indicate the manufacturer,

device type, and capacity (density). The returned data bytes provide the information as shown in the below

table.

Table 5. ACE25QA400 ID Definition table

Operation Code

M7-M0

68

ID15-ID8

40

ID7-ID0

13

9FH

90H

ABH

68

12

Instructions Description

All instructions, addresses and data are shifted in and out of the device, beginning with the most significant

bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be

shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.

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4M BIT SPI NOR FLASH

See Table 6, every instruction sequence starts with a one-byte instruction code. Depending on the instruction,

this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after

the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read

Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence

is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being

shifted out.

For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write

Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary,

otherwise the instruction is rejected, and is not executed. That is /CS must drive high when the number of

clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the

input byte is not a full byte, nothing will happen and WEL will not be reset.

Table 6. Instruction Set Table

Instruction Name

Write Enable

Byte 1

06H

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Write Disable

04H

Read Status Register

Write Status Register

Read Data

05H

(S7-S0)

01H

03H

A23-A16

A15-A8

A7-A0

(D7-D0)

dummy

(D7-D0)

Next byte

(D7-D0)

(D7-D0)^(NOTES)

Fast Read

0BH

3BH

02H

Dual Output Fast Read

Page Program

Next byte

Page Program

F2H

20H

Next byte

Sector Erase

Block Erase(32K)

Block Erase(64K)

Chip Erase

52H

D8H

C7/60H

B9H

Deep Power-Down

Release From Deep

Power-Down, And Read

Device ID

ABH

dummy

(ID7-ID0)

(M7-M0)

Release From Deep

Power-Down

ABH

Manufacturer/ Device ID

JEDEC ID

90H

9FH

dummy

00H

(ID7-ID0)

(M7-M0)

(ID15-ID8)

(ID7-ID0)

Notes: Dual Output data

IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1)

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4M BIT SPI NOR FLASH

Configuration and Status Instructions

Write Enable (06H)

See Figure 1, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable

Latch bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write

Status Register instruction. The Write Enable instruction sequence: /CS goes low sending the Write

Enable instruction /CS goes high.

Figure 1. Write Enable Sequence Diagram

Write Disable (04H)

See Figure 2, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable

instruction sequence: /CS goes low sending the Write Disable instruction /CS goes high. The WEL bit is

reset by following condition: Power-up and upon completion of the Write Status Register, Page Program,

Sector Erase, Block Erase and Chip Erase instructions.

Figure 2. Write Disable Sequence Diagram

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4M BIT SPI NOR FLASH

Read Status Register (05H)

See Figure 3 the Read Status Register (RDSR) instruction is for reading the Status Register. The Status

Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress.

When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before

sending a new instruction to the device. It is also possible to read the Status Register continuously. For

instruction code “05H”, the SO will output Status Register bits S7~S0.

Figure 3. Read Status Register Sequence Diagram

Write Status Register (01H)

See Figure 4, the Write Status Register instruction allows new values to be written to the Status Register.

Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write

Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5

are always read as 0. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched

in. If not, the Write Status Register instruction is not executed. As soon as Chip Select (CS#) is driven High,

the self-timed Write Status Register cycle (the duration is tW) is initiated. While the Write Status Register

cycle is in progress, reading Status Register to check the Write In Progress (WIP) bit is achievable. The Write

In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the completion of

theWrite Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0. The Write

Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1,

and BP0) bits, which are utilized to define the size of the read-only area. The Write Status Register (WRSR)

instruction also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the

Write Protect (WP#) signal, by setting which the device can enter into Hardware Protected Mode (HPM). The

Write Status Register (WRSR) instruction is not executed once enter into the Hardware Protected Mode

(HPM).

Figure 4. Write Status Register Sequence Diagram

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4M BIT SPI NOR FLASH

Read Instructions

Read Data (03H)

See Figure 5, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit

being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on

SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is

automatically incremented to the next higher address after each byte of data is shifted out allowing for a

continuous stream of data. This means that the entire memory can be accessed with a single command as

long as the clock continues. The command is completed by driving /CS high. The whole memory can be read

with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase,

Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Normal read mode running up to 50MHz.

Figure 5. Read Data Bytes Sequence Diagram

Fast Read (0BH)

See Figure 6, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out. It

is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge

of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max

frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The address

is automatically incremented to the next higher address after each byte of data is shifted out.

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Figure 6. Fast Read Sequence Diagram

ACE25QA400G

4M BIT SPI NOR FLASH

Dual Output Fast Read (3BH)

See Figure 7, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy

byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit

per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out

Figure 7. Dual Output Fast Read Sequence Diagram

ID and Security Instructions

Read Manufacture ID/ Device ID (90H)

See Figure 8, the Read Manufacturer/Device ID instruction is an alternative to the Release from

Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific

Device ID.

The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a

24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be

read first.

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Figure 8. Read Manufacture ID/ Device ID Sequence Diagram

ACE25QA400G

4M BIT SPI NOR FLASH

JEDEC ID (9FH)

The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of

device identification. The device identification indicates the memory type in the first byte, and the memory

capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in

progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction should

not be issued while the device is in Deep Power-Down Mode.

See Figure 9, he device is first selected by driving /CS to low. Then, the 8-bit instruction code for the

instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted

out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The JEDEC ID

instruction is terminated by driving /CS to high at any time during data output. When /CS is driven high, the

device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can

receive, decode and execute instructions.

Figure 9. JEDEC ID Sequence Diagram

Deep Power-Down (B9H)

Although the standby current during normal operation is relatively low, standby current can be further

reduced with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down

(DPD) instruction especially useful for battery powered applications (see ICC1 and ICC2). The instruction is

initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 10.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power

down instruction will not be executed. After /CS is driven high, the power-down state will entered within the

time duration of tDP. While in the power-down state only the Release from Deep Power-down / Device ID

instruction, which restores the device to normal operation, will be recognized. All other Instructions are

ignored. This includes the Read Status Register instruction, which is always available during normal

operation. Ignoring all but one instruction also makes the Power Down state a useful condition for securing

maximum write protection. The device always powers-up in the normal operation with the standby current of

ICC1.

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Figure 10. Deep Power-Down Sequence Diagram

ACE25QA400G

4M BIT SPI NOR FLASH

Release from Deep Power-Down/Read Device ID (ABH)

The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to

release the device from the Power-Down state or obtain the devices electronic identification (ID) number.

See Figure 11, to release the device from the Power-Down state, the instruction is issued by driving the /CS

pin low, shifting the instruction code “ABH” and driving /CS high Release from Power-Down will take the time

duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other

instruction are accepted. The /CS pin must remain high during the tRES1 time duration.

When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by

driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits

are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 12.

The Device ID value for the ACE25QA200.400 is listed in Manufacturer and Device Identification table. The

Device ID can be read continuously. The instruction is completed by driving /CS high.

When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the

same as previously described, and shown in Figure 12, except that after /CS is driven high it must remain

high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume

normal operation and other instruction will be accepted. If the Release from Power-Down/Device ID

instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction

is ignored and will not have any effects on the current cycle.

Figure 11. Release Power-Down Sequence Diagram

Figure 12. Release Power-Down/Read Device ID Sequence Diagram

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4M BIT SPI NOR FLASH

Program and Erase Instructions

Page Program (02H)

The Page Program instruction is for programming the memory. A Write Enable instruction must previously

have been executed to set the Write Enable Latch bit before sending the Page Program instruction.

See Figure 13, the Page Program instruction is entered by driving /CS Low, followed by the instruction code,

3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,

all transmitted data that goes beyond the end of the current page are programmed from the start address of

the same page (from the address whose 8 least significant bits (A7-A0) are all zero). /CS must be driven low

for the entire duration of the sequence. The Page Program instruction sequence: /CS goes low sending

Page Program instruction 3-byte address on SI at least 1 byte data on SI /CS goes high. If more than 256

bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are

guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device,

they are correctly programmed at the requested addresses without having any effects on the other bytes of

the same page. /CS must be driven high after the eighth bit of the last data byte has been latched in;

otherwise the Page Program instruction is not executed.

As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While

the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in

Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0

when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is

reset.

A Page Program instruction applied to a page which is protected by the Block Protect (BP2, BP1, and BP0)

bits is not executed.

Figure 13. Page Program Sequence Diagram

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4M BIT SPI NOR FLASH

Fast Page Program (FPP) (F2H)

The Fast Page Program (FPP) instruction is for programming the memory. A Write Enable instruction must

previously have been executed to set the Write Enable Latch bit before sending the Page Program

instruction.

See Figure 14, the Page Program instruction is entered by driving /CS Low, followed by the instruction code,