ACE25QC800GLFMUH [ACE]
8M BIT SPI NOR FLASH;
| 型号： | ACE25QC800GLFMUH |
| 厂家： | 
ACE TECHNOLOGY CO., LTD. |
| 描述： | 8M BIT SPI NOR FLASH |
| 文件： | 总58页 (文件大小：2413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACE25QC800G
8M BIT SPI NOR FLASH
Description
The ACE25QC800G is 8M-bit Serial Peripheral Interface(SPI) Flash memory, and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (/WP), and I/O3 (/HOLD).
The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is
transferred with speed of 480Mbits/s. The device uses a single low voltage power supply, ranging from 2.7
Volt to 3.6 Volt.
Additionally, the device supports JEDEC standard manufacturer and device ID and three 256-bytes
Security Registers.
In order to meet environmental requirements, offers 8-pin SOP, 8-pin SOP 208mil, 8-pad WSON 6x5-mm,
8-pin 3*2 USON。
Features
Serial Peripheral Interface (SPI)
Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD
Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD
Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3
Read
Normal Read (Serial): 55MHz clock rate
Fast Read (Serial): 108MHz clock rate with 30PF load
Dual I/O data transfer up to 216Mbits/S
Quad I/O data transfer up to 432Mbits/S
Continuous Read with 8/16/32/64-byte Wrap
Program
Serial-input Page Program up to 256bytes
Program Suspend and Resume
Erase
Block erase (64/32 KB)
Sector erase (4 KB)
Chip erase
Erase Suspend and Resume
Program/Erase Speed
Page Program time: 0.6ms typical
Sector Erase time: 50ms typical
Block Erase time: 0.15/0.25s typical
Chip Erase time: 4s typical
Flexible Architecture
Sector of 4K-byte
Block of 32/64K-byte
VER 1.2
1
ACE25QC800G
8M BIT SPI NOR FLASH
Low Power Consumption
20mA maximum active current
5uA maximum power down current
Software/Hardware Write Protection
3x256-Byte Security Registers with OTP Locks
Discoverable Parameters (SFDP) register
Enable/Disable protection with WP Pin
Write protect all/portion of memory via software
Top or Bottom, Sector or Block selection
Single Supply Voltage
Full voltage range: 2.7~3.6V
Temperature Range
Industrial (-40℃ to 85℃)
Cycling Endurance/Data Retention
Typical 100k Program-Erase cycles on any sector
Typical 20-year data retention at 55℃
VER 1.2
2
ACE25QC800G
8M BIT SPI NOR FLASH
Packaging Type
SOP-8
SOP-8L
DIP-8
WSON
USON3*2-8
Ordering information
ACE25QC800GX XXX + X H
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
FM: SOP-8
FML: SOP-8L (208mil)
DP: DIP-8
MM: WSON
UA8: USON3*2-8
L: Voltage 1.8V
Default: Voltage 3V
VER 1.2
3
ACE25QC800G
8M BIT SPI NOR FLASH
Signal Description
During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max).
All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL,
see Section DC Electrical Characteristics). These signals are described next.
Table1. Signal Names
Pin No
Pin Name
I/O
Function
1
/CS
I
Chip Select
Serial Output for single bit data Instructions. IO1 for Dual or Quad
Instructions.
2
SO (IO1)
I/O
Write Protect in single bit or Dual data Instructions. IO2 in Quad mode.
3
/WP (IO2)
I/O The signal has an internal pull-up resistor and may be left unconnected in
the host system if not used for Quad Instructions.
Ground
4
5
6
VSS
SI (IO0)
SCLK
Serial Input for single bit data Instructions. IO0 for Dual or Quad
I/O
Instructions.
I
Serial Clock
Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in
7
8
/HOLD (IO3) I/O Quad-I/O mode. The signal has an internal pull-up resistor and may be
left unconnected in the host system if not used for Quad Instructions.
VCC
Core and I/O Power Supply
Chip Select (/CS)
The chip select signal indicates when a instruction for the device is in process and the other signals are
relevant for the memory device. When the /CS signal is at the logic high state, the device is not selected
and all input signals are ignored and all output signals are high impedance. Unless an internal Program,
Erase or Write Status Registers embedded operation is in progress, the device will be in the Standby Power
mode. Driving the /CS input to logic low state enables the device, placing it in the Active Power mode. After
Power Up, a falling edge on /CS is required prior to the start of any instruction.
Serial Clock (SCLK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or
data input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of
SCLK.
VER 1.2
4
ACE25QC800G
8M BIT SPI NOR FLASH
Serial Input (SI)/IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and
data to be programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions,
addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well
as shifting out data (on the falling edge of SCK).
Serial Data Output (SO)/IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of
the serial SCK clock signal.
SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions,
addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well
as shifting out data (on the falling edge of SCK).
Write Protect (/WP)/IO2
When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status
Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status
Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the
memory area that are protected by the Block Protect, TB, SEC, and CMP bits in the status registers, are
also hardware protected against data modification while /WP remains Low. The /WP function is not
available when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1).
The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and
data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data
(on the falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and
may be left unconnected in the host system if not used for Quad mode.
HOLD (/HOLD)/IO3
The /HOLD function is only available when QE=0, If QE=1, The /HOLD function is disabled, the pin acts as
dedicated data I/O pin
The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
The Hold condition starts on the falling edge of the Hold (/HOLD) signal, provided that this coincides with
SCK being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic
low state, the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the /HOLD
signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in
progress.
VER 1.2
5
ACE25QC800G
8M BIT SPI NOR FLASH
VCC Power Supply
VCC is the supply voltage. It is the single voltage used for all device functions including read, program, and
erase.
VSS Ground
VSS is the reference for the VCC supply voltage.
VER 1.2
6
ACE25QC800G
8M BIT SPI NOR FLASH
Block/Sector Architecture
Table2. ACE25QC800G Block/Sector Addresses
Memory
Density
Sector
Block(64kbyte)
Block(32kbyte)
Sector No.
Address range
Size(KB)
Sector 0
:
4
:
000000h-000FFFh
Half block 0
:
Sector 7
Sector 8
:
4
4
4
4
4
:
007000h-007FFFh
008000h-008FFFh
:
Block 0
Half block 1
Half block 2
Sector 15
Sector 16
:
00F000h-00FFFFh
010000h-010FFFh
:
Sector 23
Sector 24
:
4
4
:
017000h-017FFFh
018000h-018FFFh
:
Block 1
Half block 3
Sector 31
:
4
:
01F000h-01FFFFh
:
8Mbit
:
:
Sector 224
：
4
：
4
4
：
4
4
：
4
4
：
4
0E0000h-0E0FFFh
：
Half block 28
Sector 231
Sector 232
：
0E7000h-0E7FFFh
0E8000h-0E8FFFh
：
Block 14
Half block 29
Half block 30
Half block 31
Sector 239
Sector 240
：
0EF000h-0EFFFFh
0F0000h-0F0FFFh
：
Sector 247
Sector 248
：
0F7000h-0F7FFFh
0F8000h-0F8FFFh
：
Block 15
Sector 255
0FF000h-0FFFFFh
Notes:
1. Block = Uniform Block, and the size is 64K bytes.
2. Half block = Half Uniform Block, and the size is 32k bytes.
3. Sector = Uniform Sector, and the size is 4K bytes.
VER 1.2
7
ACE25QC800G
8M BIT SPI NOR FLASH
SPI Operation
Standard SPI Instructions
The ACE25QC800G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported.
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI Instructions
The ACE25QC800G supports Dual SPI operation when using the “Dual Output Fast Read” (3BH), “Dual
I/O Fast Read” (BBH) and “Read Manufacture ID/Device ID Dual I/O” (92H) instructions. These instructions
allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the
Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI Instructions
The ACE25QC800G supports Quad SPI operation when using the “Quad Output Fast Read”(6BH), “Quad
I/O Fast Read” (EBH) ,”Quad I/O word Fast Read”(E7H),”Read Manufacture ID/Device ID Quad I/O”(94H)
and “Quad Page Program”(32H) instructions. These instructions allow data to be transferred to or from the
device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins
become bidirectional I/O pins: IO0 and IO1, and /WP and
/HOLD pins become IO2 and IO3. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in
Status Register to be set.
QPI Instructions
The ACE25QC800G supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI
protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight
serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks
are required. This can significantly reduce the SPI instruction overhead and improve system performance
in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can
be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between
these two modes. Upon power-up or after a software reset using “Enable Reset (66h)”and “Reset (99h)”
instruction, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the
non-volatile Quad Enable bit (QE) in Status Register-2 is required to be setto 1. When using QPI
instructions, the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become
IO2 and IO3 respectively.
VER 1.2
8
ACE25QC800G
8M BIT SPI NOR FLASH
Operation Features
Supply Voltage
(A) Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the
specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable DC supply voltage,
it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to
100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of
the transmission of the instruction and, for a Write instruction, until the completion of the internal write
cycle (tW).
(B) Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the
Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore
recommended to connect the /CS line to VCC via a suitable pull-up resistor.
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected until a falling
edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have
been High, prior to going Low to start the first operation.
(C) Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on
reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC
has reached the power on reset threshold voltage.
When VCC has passed the POR threshold, the device is reset.
(D) Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating
voltage to below the power on reset threshold voltage, the device stops responding to any instruction
sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to
follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal
Write cycle in progress).
Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device
consumes ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the
device then goes in to the Standby Power mode, and the device consumption drops to ICC1.
VER 1.2
9
ACE25QC800G
8M BIT SPI NOR FLASH
Hold Condition
The Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the
clocking sequence. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial
Data Input (SI) and Serial Clock (SCLK) are Don’t Care. To enter the Hold condition, the device must be
selected, with Chip Select (/CS) Low. Normally, the device is kept selected, for the whole duration of the
Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state
of the device, and this mechanism can be used if it is required to reset any processes that had been in
progress.
The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial Clock
(SCLK) already being Low (as shown in Figure 1).
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C)
already being Low. Figure 1 also shows what happens if the rising and falling edges are not timed to
coincide with Serial Clock (SCLK) being Low.
Figure1. Hold condition activation
Status Register
Status Register Table
See Table 3 for detail description of the Status Register bits.
Table3. Status Register
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
S9
S8
SUS1
CMP
SUS2
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
VER 1.2
10
ACE25QC800G
8M BIT SPI NOR FLASH
The Status and Control Bits
(A) WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status
register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status
register progress, when WIP bit sets 0, means the device is not in program/erase/write status register
progress.
(B) WEL bit
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write
Status Register, Program or Erase instruction is accepted.
(C) BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with the Write
Status Register instruction. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the
relevant memory area (as defined in Table 6 and Table 7).becomes protected against Page Program,
Sector Erase and Block Erase instructions. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set. The Chip Erase(CE) instruction
is executed, if the Block Protect(BP2,BP1,BP0)bits are 0 and CMP=0 or The Block Protect (BP2, BP1,
BP0) bits are1 and CMP=1.
(D) SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status
register. The SRP bits control the method of write protection: software protection, hardware protection,
power supply lock-down or one time programmable protection.
(E) QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad
operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE
pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during
standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground).
(F) LB bit
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S13–S11) that provide the
write protect control and status to the Security Registers. The default state of LB is 0, the security
registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One
Time Programmable, once they are set to 1, the Security Registers will become read-only
permanently.
VER 1.2
11
ACE25QC800G
8M BIT SPI NOR FLASH
(G) CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the
SEC-BP0 bits to provide more flexibility for the array protection. Please see the Status registers
Memory Protection table for details. The default setting is CMP=0.
(H) SUS1/SUS2 bit
The SUS1 and SUS2 bits are read only bits in the status register2 (S15 and S10) that are set to 1 after
executing an Erase/Program Suspend (75H) instruction (The Erase Suspend will set SUS1 to 1, and
the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by
Erase/Program Resume (7AH) instruction as well as a power-down, power-up cycle.
Status Register Protect Table
The Status Register Protect (SRP1 and SRP0) bita are non-volatile Read/Write bits in the Status Register.
The SRP bits control the morhod of write protection: software protection, hardware protection, power
supply lock-down or one time programmable protection.
Protect Table
Table4. ACE25QC800G Status Register protect table
SRP1 SRP0
/WP
Status Register
Description
The Status Register can be written to after a
Write Enable instruction, WEL=1.(Factory
Default)
0
0
0
0
1
1
X
Software Protected
/WP=0, the Status Register locked and
cannot be written.
0
1
Hardware Protected
/WP=1, the Status Register is unlocked and
can be written to after a Write Enable
instruction, WEL=1.
Hardware Unprotected
Status Register is protected and cannot be
written to again until the next Power-Down,
Power-Up cycle.
(1)
1
0
1
X
X
Power Supply Lock-Down
Status Register is permanently protected and
cannot be written to.
(2)
1
One Time Program
Notes:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. The One time Program feature is available upon special order.
VER 1.2
12
ACE25QC800G
8M BIT SPI NOR FLASH
Write Protect Features
1. Software Protection: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the
memory array that can be read but not change.
2. Hardware Protection: /WP going low to protected the writable bits of Status Register.
3. Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the Release from
deep Power-Down Mode instruction.
4. Write Enable: The Write Enable instruction is set the Write Enable Latch bit.The WEL bit will return to
reset by following situation:
Power –up
Write Disable
Write Status Register
Page Program
Sector Erase/Block Erase/Chip Erase
Sofeware Reset
VER 1.2
13
ACE25QC800G
8M BIT SPI NOR FLASH
Status Register Memory Protection
Protect Table
Table5. ACE25QC800G Status Register Memory Protection (CMP=0)
Status Register Content
Memory Content
BP4 BP3 BP2 BP1
BP0
0
Blocks
NONE
15
Addresses
Density
NONE
64KB
128KB
256KB
512KB
64KB
128KB
256KB
512KB
1MB
Portion
NONE
X
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
NONE
1
0F0000H-0FFFFFH
0E0000H-0FFFFFH
0C0000H-0FFFFFH
080000H-0FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-0FFFFFH
0FF000H-0FFFFFH
0FE000H-0FFFFFH
0FC000H-0FFFFFH
0F8000H-0FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
ALL
0
14 to 15
12 to 15
8 to 15
0
1
0
1
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 15
15
1
0
1
X
1
1MB
ALL
4KB
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
0
15
8KB
1
15
16KB
32KB
4KB
X
1
15
0
0
0
8KB
1
0
16KB
32KB
X
0
VER 1.2
14
ACE25QC800G
8M BIT SPI NOR FLASH
Table6. ACE25QC800G Status Register Memory Protection (CMP=1)
Status Register Content Memory Content
BP4
X
0
BP3
X
0
BP2
0
BP1
0
BP0
0
Blocks
0 to 15
0 to 14
0 to 13
0 to 11
0 to 7
Addresses
Density
1MB
Portion
ALL
000000H-0FFFFFH
000000H-0EFFFFH
000000H-0DFFFFH
000000H-0BFFFFH
000000H-07FFFFH
010000H-0FFFFFH
020000H-0FFFFFH
040000H-0FFFFFH
080000H-0FFFFFH
NONE
0
0
1
960KB
896KB
768KB
512KB
960KB
896KB
768KB
512KB
NONE
NONE
1020KB
1016KB
1008KB
992KB
1020KB
1016KB
1008KB
992KB
Lower 15/16
Lower 7/8
Lower 3/4
Lower 1/2
Upper 15/16
Upper 7/8
Upper 3/4
Upper 1/2
NONE
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
1 to 15
2 to 15
4 to 15
8 to 15
NONE
NONE
0 to 15
0 to 15
0 to 15
0 to 15
0 to 15
0 to 15
0 to 15
0 to 15
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
X
X
0
1
0
1
0
1
1
X
1
NONE
NONE
1
0
0
000000H-0FEFFFH
000000H-0FDFFFH
000000H-0FBFFFH
000000H-0F7FFFH
001000H-0FFFFFH
002000H-0FFFFFH
004000H-0FFFFFH
008000H-0FFFFFH
L-255/256
L-127/128
L-63/64
1
0
0
1
0
1
0
0
1
1
1
0
1
0
X
1
L-31/32
1
1
0
0
L-255/256
L-127/128
L-63/64
1
1
0
1
0
1
1
0
1
1
1
1
1
0
X
L-31/32
VER 1.2
15
ACE25QC800G
8M BIT SPI NOR FLASH
Device Identification
Three legacy Instructions are supported to access device identification that can indicate the manufacturer,
device type, and capacity (density). The returned data bytes provide the information as shown in the below
table.
Table7. ACE25QC800G ID Definition table
Operation Code
9FH
M7-M0
68
ID15-ID8
40
ID7-ID0
14
90H/92H/94H
ABH
68
13
13
Instructions Description
All instructions, addresses and data are shifted in and out of the device, beginning with the most significant
bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be
shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table 8, every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS must be
driven high after the last bit of the instruction sequence has been shifted in. For the instruction of Read,
Fast Read, Read Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in
instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the
data-out sequence is being shifted out.
For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is /CS must driven high when the number of
clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the
input byte is not a full byte, nothing will happen and WEL will not be reset.
Table8. Instruction Set Table
Instruction Name
Write Enable
Write Disable
Read Status
Register-1
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
04H
05H
35H
(S7-S0)
continuous
continuous
Read Status
Register-2
(S15-S8)
Write Enable for
Volatile Status
Register
50H
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ACE25QC800G
8M BIT SPI NOR FLASH
Instruction
Name
Byte 1
01H
Byte 2
(S7-S0)
(S15-S8)
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
Write Status
Register -1
Write Status
Register-2
Read Data
Fast Read
Dual Output Fast
Read
31H
03H
0BH
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
Next byte continuous
(D7-D0) continuous
3BH
BBH
A23-A16
A23-A8(2)
A15-A8
A7-A0
dummy
(D7-D0)(1) continuous
Dual I/O Fast
Read
A7-A0
M7-M0(2)
Next
(D7-D0)(1)
Next byte
continuous
byte
Quad Output
Fast
6BH
EBH
A23-A16
A23-A0
A15-A8
A7-A0
dummy
(D7-D0)(3) continuous
Read
Quad I/O Fast
Read
dummy(5) (D7-D0)(3)
dummy(6) (D7-D0)(3)
Next byte Next byte continuous
Next byte Next byte continuous
M7-M0(4)
Quad I/O Word
A23-A0
E7H
02H
32H
Fast Read
dM7-M0 (4)
A23-A16
(7)
Page Program
Quad Page
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
Next byte continuous
Next byte continuous
(D7-D0)(3)
A23-A16
Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
20H
52H
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
D8H
C7/60H
66H
Enable Reset
Reset
99H
Set Burst with
Wrap
dummy(6)
W7-W0
77H
75H
7AH
B9H
Program/Erase
Suspend
Program/Erase
Resume
Deep
Power-Down
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8M BIT SPI NOR FLASH
Instruction
Name
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
Release From
Deep
Power-Down,
And
ABH
dummy
dummy
dummy
(ID7-ID0)
continuous
Read Device ID
Release From
Deep
Power-Down
Manufacturer/
Device ID
ABH
90H
92H
(MID7-MI
D0)
dummy
A23-A8
dummy
00H
(ID7-ID0) continuous
continuous
Manufacturer/
Device ID by
Dual I/O
(MID7-MI
D0),(DID
7-DID0)
A7-A0,
dummy
dummy(10)
(MID7-MI
D0)(DID7
-DID0)
Manufacturer/
Device ID by
Quad I/O
A23-A0,
dummy
94H
9FH
continuous
continuous
MID7-MI
D0
JEDEC ID
ID15-ID8
ID7-ID0
A7-A0
Enter QPI Mode
Exit QPI Mode
38H
FFH
Read Serial
Flash
Discoverable
Parameter
5AH
A23-A16
A15-A8
Dummy
D7-D0
continuous
Erase Security
Registers(8)
Program Security
Registers(8)
Read Security
Registers(8)
Instruction
Name
44H
42H
48H
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
(D7-D0)
(D7-D0)
continuous
continuous
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6 - Byte 13
(U ID 63-U ID 0)
Read Unique ID
4BH
Dummy
Dummy
Dummy
Dummy
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Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0,…..)
IO1 = (D5, D1,…..)
IO2 = (D6, D2,…..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x , D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data:the lowest address bit must be 0.
8. Security Registers Address:
Security Register1: A23-A16=00H, A15-A8=00010000b, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=00100000b, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=00110000b, A7-A0= Byte Address;
9. Dummy bits and Wraps Bits
IO0 = (x, x, x, x, x, x, w4, x)
IO1 = (x, x, x, x, x, x, w5, x)
IO2 = (x, x, x, x, x, x, w6, x)
IO3 = (x, x, x, x, x, x, x,x)
10. Address, continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3)
Security Register 0 can be used to store the Flash Discoverable Parameters.
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ACE25QC800G
8M BIT SPI NOR FLASH
Configuration and Status Instructions
Write Enable (06H)
See Figure 2, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable Latch
bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register
instruction and Erase/Program Security Registers instruction. The Write Enable instruction sequence: /CS
goes low sending the Write Enable instruction /CS goeshigh.
Figure2. Write Enable Sequence Diagram
Write Disable (04H)
See Figure 3, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable
instruction sequence: /CS goes low -> sending the Write Disable instruction -> /CS goes high. The WELbit
is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program,
Sector Erase, Block Erase and Chip Erase, Erase/Program Security Registers and Reset instructions.
Figure3. Write Disable Sequence Diagram
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8M BIT SPI NOR FLASH
Read Status Register (05H or 35H)
See Figure 4 the Read Status Register (RDSR) instruction is for reading the Status Register. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP)
bit before sending a new instruction to the device. It is also possible to read the Status Register
continuously. For instruction code “05H”, the SO will output Status Register bits S7~S0. The instruction
code “35H”, the SO will output Status Register bits S15~S8, The instruction code “15H”, the SO will output
Status Register bits S23~16.
Figure4. Read Status Register Sequence Diagram
Write Status Register (01H or 31H)
See Figure 5, the Write Status Register instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write
Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register instruction has no effect on S23, S20, S19, S18, S17, S16, S15, S1 and S0 of
the Status Register. /CS must be driven high after the eighth bit of the data byte has been latched in. If not,
the self-timed Write
the Write Status Register instruction is not executed. As soon as /CS is driven high,
Status Register cycle (whose duration is t ) is initiated. While the Write Status
W
Register cycle is in progress,
the Status Register may still be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch is reset.
The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3.
The Write Status Register instruction also allows the user to set or reset the Status Register Protect (SRP1
and SRP0) bits in accordance with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and
SRP0) bits and Write Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The
Write Status Register instruction is not executed once the Hardware Protected Mode is entered.
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8M BIT SPI NOR FLASH
Figure5. Write Status Register Sequence Diagram
Write Enable for Volatile Status Register (50H)
See Figure 6, the non-volatile Status Register bits can also be written to as volatile bits.. This gives more
flexibility to change the system configuration and memory protection schemes quickly without waiting for
the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits.
Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit, it is only valid for
the Write Status Registers instruction to change the volatile Status Register bit values.
Figure6. Write Enable for Volatile Status Register
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ACE25QC800G
8M BIT SPI NOR FLASH
Read Instructions
Read Data (03H)
See Figure 7, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit
being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out
on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is
automatically incremented to the next higher address after each byte of data is shifted out allowing for a
continuous stream of data. This means that the entire memory can be accessed with a single command as
long as the clock continues. The command is completed by driving /CS high. The whole memory can be
read with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure7. Read Data Bytes Sequence Diagram
Fast Read (0BH)
See Figure 8, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out. It
is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising
edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out,
at a Max frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure8. Fast Read Sequence Diagram
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8M BIT SPI NOR FLASH
Dual Output Fast Read (3BH)
See Figure 9, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy
byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out
2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure9. Dual Output Fast Read Sequence Diagram
Quad Output Fast Read (6BH)
See Figure 10, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0) and a
dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted
out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
VER 1.2
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Figure10. Quad Output Fast Read Sequence Diagram
ACE25QC800G
8M BIT SPI NOR FLASH
Dual I/O Fast Read (BBH)
See Figure 11, the Dual I/O Fast Read instruction is similar to the Dual Output Fast Read instruction but
with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock
by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are
shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with “continuous Read Mode”
The Dual I/O Fast Read instruction can further reduce instruction overhead through setting the “continuous
Read Mode “bits (M7-4) after the inputs 3-byte address A23-A0).If the “continuous Read Mode
“bits(M5-4)=(1,0),then the next Dual I/O fast Read instruction (after CS/ is raised and then lowered) does
not require the BBH instruction code. The instruction sequence is shown in the following Figure 12.If the
“continuous Read Mode “bits (M5-4) does not eQuad (1,0),the next instruction requires the first BBH
instruction code, thus returning to normal operation. A “continuous Read Mode” Reset instruction can be
used to reset (M5-4) before issuing normal instruction.
Figure11. Dual I/O Fast Read Sequence Diagram (Initial command or previous (M5-4)≠(1,0)))
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8M BIT SPI NOR FLASH
Figure12. Dual I/O Fast Read Sequence Diagram (Previous command set (M5-4) =(1,0))
Quad I/O Fast Read (EBH)
See Figure 13, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction but with
the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock
4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the
memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first byte addressed can
be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out. The Quad Enable bit (QE) of Status Register must be set to enable for the Quad I/O Fast
read instruction.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 13, If the
“Continuous Read Mode” bits (M5-4 )= (1,0), then the next Fast Read Quad I/O instruction(after /CS is
raised and then lowered) does not require the EBH instruction code, The instruction sequence is shown in
the followed Figure 14. If the “Continuous Read Mode” bits M5-4 do not eQuad to (1,0), the next instruction
requires the first EBH instruction code, thus returning to normal operation. A “Continuous Read Mode”
Reset command can also be used to reset (M5-4) before issuing normal command.
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ACE25QC800G
8M BIT SPI NOR FLASH
Figure13. Quad I/O Fast Read Sequence Diagram (Initial command or previous (M5-4≠(1,0)))
Figure14. Quad I/O Fast Read Sequence Diagram (Previous command set (M5-4)=(1,0)))
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around”
The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by issuing a
“Set Burst with Wrap” (77H) instruction prior to EBH. The “Set Burst with Wrap” (77H) instruction can either
enable or disable the “Wrap Around” feature for the following EBH instructions. When “Wrap Around” is
enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte
page. The output data starts at the initial address specified in the instruction, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around
section within a page.
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ACE25QC800G
8M BIT SPI NOR FLASH
Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read instruction is similar to the Quad Fast Read instruction except that the
lowest address bit (A0) must eQuad 0 and 2-dummy clock. The instruction sequence is shown in the
followed Figure15, the first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of
Status Register (S9) must be set to enable for the Quad I/O Word Fast Read instruction.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input 3-byte Address bits (A23-0). If the “Continuous Read
Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read instruction (after
/CS is raised and then lowered) does not require the E7H instruction code, the instruction sequence is
shown in the followed Figure 16. If the “Continuous Read Mode” bits M5-4 do not eQuad to (1,0), the next
instruction requires the first E7H instruction code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can also be used to reset (M5-4) before issuing normal command.
Figure15. Quad I/O Word Fast Read Sequence Diagram (Initial command or previous (M5-4)≠ (1,0))
Figure16. Quad I/O word Fast Read Sequence Diagram (Previous command set (M5-4) =(1,0))
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8M BIT SPI NOR FLASH
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in standard SPI mode
The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by issuing a
“Set Burst with Wrap” (77H) instruction prior to E7H. The “Set Burst with Wrap” (77H) instruction can either
enable or disable the “Wrap Around” feature for the following E7H instructions. When “Wrap Around” is
enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte
page. The output data starts at the initial address specified in the instruction, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around
section within a page.
Set Burst with Wrap (77H)
See Figure 17, The Set Burst with Wrap instruction is used in conjunction with “Quad I/O Fast Read” and
“Quad I/O Word Fast Read” instruction to access a fixed length of 8/16/32/64-byte section within a 256-byte
page, in standard SPI mode.
The Set Burst with Wrap instruction sequence:/CS goes low ->Send Set Burst with Wrap instruction
->Send24 Dummy bits ->Send 8 bits “Wrap bits”->/CS goes high.
If W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word Read
Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To
exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap
instruction should be issued to set W4=1. The default value of W4 upon power on is 1.
W4 = 0
W4 =1 (DEFAULT)
W6
W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0
0
1
1
0
1
0
1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
VER 1.2
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Figure17. Set Burst with Wrap Sequence Diagram
ACE25QC800G
8M BIT SPI NOR FLASH
ID and Security Instructions
Read Manufacture ID/ Device ID (90H)
See Figure 18, The Read Manufacturer/Device ID instruction is an alternative to the Release from
Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the
specific Device ID.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a
24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure18. Read Manufacture ID/ Device ID Sequence Diagram
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Dual I/O Read Manufacture ID/ Device ID (92H)
See Figure 19, the Dual I/O Read Manufacturer/Device ID instruction is an alternative to the Release from
Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the
specific Device ID by Dual I/O.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92H” followed by a
24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure19. Dual I/O Read Manufacture ID/ Device ID Sequence Diagram
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Quad I/O Read Manufacture ID/ Device ID (94H)
See Figure 20, the Quad I/O Read Manufacturer/Device ID instruction is an alternative to the Release from
Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the
specific Device ID by quad I/O.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “94H” followed by a
24-bit address (A23-A0) of 000000H and4 dummy clocks. If the 24-bit address is initially set to 000001H,
the Device ID will be read first.
Figure20. Quad I/O Read Manufacture ID/ Device ID Sequence Diagram
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Read JEDEC ID (9FH)
The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of
device identification. The device identification indicates the memory type in the first byte, and the memory
capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in
progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction
should not be issued while the device is in Deep Power-Down Mode.
See Figure 21, The device is first selected by driving /CS to low. Then, the 8-bit instruction code for the
instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being
shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The
JEDEC ID instruction is terminated by driving /CS to high at any time during data output. When /CS is
driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be
selected, so that it can receive, decode and execute instructions.
Figure21. JEDEC ID Sequence Diagram
Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to
each ACE25QC800G device. The ID number can be used in conjunction with user software methods to
help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS
pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the
64-bit ID is shifted out on the falling edge of SCLK as shown in Figure 22.
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Figure22. JEDEC ID Sequence Diagram
ACE25QC800G
8M BIT SPI NOR FLASH
Deep Power-Down (B9H)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Deep Power-down instruction. The lower power consumption makes the Deep
Power-down (DPD) instruction especially useful for battery powered applications (see ICC1 and ICC2).
The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in
Figure 23.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power
down instruction will not be executed. After /CS is driven high, the power-down state will entered within the
time duration of tDP. While in the power-down state only the Release from Deep Power-down / Device ID
instruction, which restores the device to normal operation, will be recognized. All other Instructions are
ignored. This includes the Read Status Register instruction, which is always available during normal
operation. Ignoring all but one instruction also makes the Power Down state a useful condition for securing
maximum write protection. The device always powers-up in the normal operation with the standby current
of ICC1.
Figure23. Deep Power-Down Sequence Diagram
VER 1.2
34
ACE25QC800G
8M BIT SPI NOR FLASH
Release from Deep Power-Down/Read Device ID (ABH)
The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the Power-Down state or obtain the devices electronic identification (ID) number.
See Figure 24, to release the device from the Power-Down state, the instruction is issued by driving the
/CS pin low, shifting the instruction code “ABH” and driving /CS high Release from Power-Down will take
the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and
other instruction are accepted. The /CS pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure
25. The Device ID value for the ACE25QC800G is listed in Manufacturer and Device Identification table.
The Device ID can be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the Power-Down state and obtain the Device ID, the instruction is
the same as previously described, and shown in Figure 25, except that after /CS is driven high it must
remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will
resume normal operation and other instruction will be accepted. If the Release from Power-Down/Device
ID instruction is issued while an Erase, Program or Write cycle is in process (when WIP eQuad 1) the
instruction is ignored and will not have any effects on the current cycle.
Figure24. Release Power-Down Sequence Diagram
Figure25. Release Power-Down/Read Device ID Sequence Diagram
VER 1.2
35
ACE25QC800G
8M BIT SPI NOR FLASH
Read Security Registers (48H)
See Figure 26, the Read Security Registers instruction is similar to Fast Read instruction. The instruction is
followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge
of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a
Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. Once
the A7-A0 address reaches the last byte of the register (Byte FFH), it will reset to 000H, the instruction is
completed by driving /CShigh.
Address
A23-A16
00H
A15-A12
0001
A11-A8
0000
A7-A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00H
0010
0000
00H
0011
0000
Figure26. Read Security Registers instruction Sequence Diagram
VER 1.2
36
ACE25QC800G
8M BIT SPI NOR FLASH
Erase Security Registers (44H)
The ACE25QC800G provides three 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.
See Figure 27, the Erase Security Registers instruction is similar to Sector/Block Erase instruction. AWrite
Enable instruction must previously have been executed to set the Write Enable Latch bit.
The Erase Security Registers instruction sequence: /CS goes low sending Erase Security Registers
instruction /CS goes high. /CS must be driven high after the eighth bit of the instruction code has been
latched in otherwise the Erase Security Registers instruction is not executed. As soon as /CS is driven high,
the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security
Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is
reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security
registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security
Registers instruction will be ignored.
Address
A23-A16
00H
A15-A12
0001
A11-A8
0000
A7-A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00H
0010
0000
00H
0011
0000
Figure27. Erase Security Registers instruction Sequence Diagram
VER 1.2
37
ACE25QC800G
8M BIT SPI NOR FLASH
Program Security Registers (42H)
See Figure 28, the Program Security Registers instruction is similar to the Page Program instruction. It
allows from 1 to 256 bytes Security Registers data to be programmed. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit before sending the Program Security
Registers instruction. The Program Security Registers instruction is entered by driving /CS Low, followed
by the instruction code (42H), 3-byte address and at least one data byte on SI. As soon as /CS is driven
high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the
Program Security Registers cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security
Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the
Write Enable Latch bit is reset.
If the Security Registers Lock Bit (LB3/LB2/LB1) is set to 1, the Security Registers will be permanently
locked. Program Security Registers instruction will be ignored.
Address
A23-A16
00H
A15-A12
0001
A11-A8
0000
A7-A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00H
0010
0000
00H
0011
0000
Figure28. Program Security Registers instruction Sequence Diagram
VER 1.2
38
ACE25QC800G
8M BIT SPI NOR FLASH
Enable Reset (66H) and Reset Device (99H)
Because of the small package and the limitation on the number of pins, the ACE25QC800G provides a
software Reset instruction instead of a dedicated RESET pin. Once the software Reset instruction is
accepted, any on-going internal operations will be terminated and the device will return to its default
power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable
Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) and Wrap
Bit setting (W6-W4).
To avoid accidental reset, both “Enable Reset (66h)” and “Reset (99h)” instructions must be issued in
sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (66h)” command will
disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to
reset the device. Once the Reset command is accepted by the device, the device will take approximately
30us to reset. During this period, no command will be accepted.
The Enable Reset (66h) and Reset (99h) instruction sequence is shown in Figure 29.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation
when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and
the SUS bit in Status Register before issuing the Reset command sequence.
Figure29. Enable Reset (66h) and Reset (99h) Command Sequence
VER 1.2
39
ACE25QC800G
8M BIT SPI NOR FLASH
Read Serial Flash Discoverable Parameter (5AH)
See Figure 30,The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of
describing the functional and feature capabilities of serial flash devices in a standard set of internal
parameter tables. These parameter tables can be interrogated by host system software to enable
adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to
the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC
Standard No.216.
Figure30. Read Serial Flash Discoverable Parameter command Sequence Diagram
VER 1.2
40
ACE25QC800G
8M BIT SPI NOR FLASH
Program and Erase Instructions
Page Program (02H)
The Page Program instruction is for programming the memory. A Write Enable instruction must previously
have been executed to set the Write Enable Latch bit before sending the Page Program instruction.
See Figure 31, the Page Program instruction is entered by driving /CS Low, followed by the instruction
code, 3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not
all zero, all transmitted data that goes beyond the end of the current page are programmed from the start
address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). /CS must
be driven low for the entire duration of the sequence. The Page Program instruction sequence: /CS goes
low-> sending Page Program instruction ->3-byte address on SI ->at least 1 byte data on SI-> /CS goes
high.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data
bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are
sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been
latched in; otherwise the Page Program instruction is not executed.
As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in
Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is
reset.
A Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
BP0) bits (see Table 5&6) is not executed.
Figure31. Page Program Sequence Diagram
VER 1.2
41
ACE25QC800G
8M BIT SPI NOR FLASH
Quad Page Program (32H)
The Quad Page Program instruction is for programming the memory using for pins: IO0, IO1, IO2 and IO3.
To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit before sending the Page
Program instruction. The Quad Page Program instruction is entered by driving /CS Low, followed by the
command code (32H), three address bytes and at least one data byte on IO pins.
The instruction sequence is shown in Figure 32, .If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the
requested addresses without having any effects on the other bytes of the same page. /CS must be driven
high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program
instruction is not executed.
As soon as /CS is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated.
While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of
the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the
Write Enable Latch bit is reset.A Quad Page Program instruction applied to a page which is protected by
the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 5&6) is not executed
Figure32. Quad Page Program Sequence Diagram
VER 1.2
42
ACE25QC800G
8M BIT SPI NOR FLASH
Sector Erase (20H)
The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit. The Sector Erase instruction is entered by
driving /CS low, followed by the instruction code, and 3-address byte on SI. Any address inside the sector is
a valid address for the Sector Erase instruction. /CS must be driven low for the entire duration of the
sequence.
See Figure 33, The Sector Erase instruction sequence: /CS goes low-> sending Block Erase instruction->
3-byte address on SI ->/CS goes high. /CS must be driven high after the eighth bit of the last address byte
has been latched in; otherwise the Sector Erase instruction is not executed. As soon as /CS is driven high,
the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write
in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Sector Erase
instruction applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see
Table 5&6) is not executed.
Figure33. Sector Erase Sequence Diagram
VER 1.2
43
ACE25QC800G
8M BIT SPI NOR FLASH
32KB Block Erase (52H)
The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction
must previously have been executed to set the Write Enable Latch bit. The 32KB Block Erase instruction is
entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside
the block is a valid address for the 32KB Block Erase instruction. /CS must be driven low for the entire
duration of the sequence.
See Figure 34, the 32KB Block Erase instruction sequence: /CS goes low ->sending 32KB Block Erase
instruction ->3-byte address on SI ->/CS goes high. /CS must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the 32KB Block Erase instruction is not executed. As soon as
/CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block
Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A
32KB Block Erase instruction applied to a block which is protected by the Block Protect (BP4, BP3, BP2,
BP1, BP0) bits (see Table 5&6) is not executed.
Figure34. 32KB Block Erase Sequence Diagram
VER 1.2
44
ACE25QC800G
8M BIT SPI NOR FLASH
64KB Block Erase (D8H)
The 64KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction
must previously have been executed to set the Write Enable Latch bit. The 64KB Block Erase instruction is
entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside
the block is a valid address for the 64KB Block Erase instruction. /CS must be driven low for the entire
duration of the sequence.
See Figure 35, the 64KB Block Erase instruction sequence: /CS goes low sending 64KB Block Erase
instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the 64KB Block Erase instruction is not executed. As soon as
/CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block
Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A
64KB Block Erase instruction applied to a block which is protected by the Block Protect (BP4, BP3, BP2,
BP1, BP0) bits (see Table 5&6) is not executed.
Figure35. 64KB Block Erase Sequence Diagram
VER 1.2
45
ACE25QC800G
8M BIT SPI NOR FLASH
Chip Erase (60/C7H)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must eQuad 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 36.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE. While the Chip Erase cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the WIPbit.
The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to
accept other Instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Chip Erase instruction is executed only if all Block Protect (BP2,
BP1, and BP0) bits are 0.The Chip Erase instruction is ignored if one or more sectors are protected.
Figure36. Chip Erase Sequence Diagram
Erase / Program Suspend (75H)
The Erase/Program Suspend instruction allows the system to interrupt a Sector or Block Erase operation,
then read from or program data to any other sector. The Erase/Program Suspend instruction also allows
the system to interrupt a Page Program operation and then read from any other page or erase any other
sector or block. The Erase/Program Suspend instruction sequence is shown in Figure 37
The Write Status Registers instruction (01h) and Erase instructions (20h, D8h, C7h, 60h, 44h) are not
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status
Registers instruction (01h), and Program instructions (02h, 42h) are not allowed during Program Suspend.
Program Suspend is valid only during the Page Program operation.
Figure37. Erase/Program Suspend Command Sequence
VER 1.2
46
ACE25QC800G
8M BIT SPI NOR FLASH
Erase / Program Resume (7AH)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase
operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7AH”
will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the WIP bit equals
to 0.
After the Resume instruction is issued the SUS bit will be cleared from 1 to 0 immediately, the WIP bit will be
set from 0 to 1 within 200 ns and the Sector or Block will complete the erase operation or the page will
complete the program operation. If the SUS bit equals to 0 or the WIP bit equals to 1, the Resume
instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is shown
in Figure 38.
Figure38. Erase/Program Resume Command Sequence
Exit QPI Mode (FFH)
In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, an “Exit QPI (FFh)”
instruction must be issued.
When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL) and
Erase Suspend status, and the Wrap Length setting will remain unchanged.
Figure39. Exit QPI Instruction (QPI Mode only)
VER 1.2
47
ACE25QC800G
8M BIT SPI NOR FLASH
Electrical Characteristics
Absolute Maximum Ratings
Parameters
Symbol
VCC
Conditions
Range
–0.5 to 4
–0.5 to 4
Unit
Supply Voltage
V
V
Voltage Applied to Any Pin
VIO
Relative to Ground
<20nS Transient Relative to
Ground
Transient Voltage on any Pin
VIOT
–2.0Vto VCC+2.0V
V
Storage Temperature
Electrostatic Discharge Voltage
Notes:
TSTG
VESD
–65 to 150
℃
(Notes)
Human Body Model
–2000 to 2000
V
JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms)
Operating Ranges
SPEC
Max
Parameter
Symbol
Conditions
Unit
Min
2.7
0
Supply Voltage
VCC
3.6
70
85
V
Commercial
Industrial
Temperature Operating
TA
℃
-40
Data Retention and Endurance
Parameter
Test Condition
150°C
Min
10
Units
Years
Years
Cycles
Minimum Pattern Data Retention Time
Erase/Program Endurance
125°C
20
-40 to 85°C
100K
Latch up Characteristics
Parameter
Min
Max
Input Voltage Respect To VSS On I/O Pins
VCC Current
-1.0V
VCC+1.0V
100mA
-100mA
Power-up Timing
Symbol
Parameter
Min
Max
Unit
us
tVSL
VCC(min) To /CS Low
300
VER 1.2
48
Figure40. Power-up Timing and Voltage Levels
ACE25QC800G
8M BIT SPI NOR FLASH
DC Electrical Characteristics(T=-40℃~85℃, VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ
Max.
Unit.
ILI
Input Leakage Current
Output Leakage Current
±2
±2
µA
µA
ILO
/CS=VCC, VIN=VCC or
VSS
ICC1
ICC2
Standby Current
13
2
25
5
µA
µA
/CS=VCC, VIN=VCC or
VSS
Deep Power-Down Current
SCLK=0.1VCC/0.9VCC
15
13
20
18
mA
mA
at120MHz,Q=Open(*1,*2,*4 I/O)
SCLK=0.1VCC/0.9VCC
Operation Current:(Read)
ICC3
at80MHz,Q=Open(*1,*2,*4 I/O)
mA
mA
mA
mA
mA
uA
V
ICC4 Operating Current(Page Program)
/CS=VCC
/CS=VCC
/CS=VCC
/CS=VCC
/CS=VCC
15
5
ICC5
ICC6
ICC7
ICC8
ICC9
VIL
Operating Current(WRSR)
Operating Current(Sector Erase)
Operating Current(Block Erase)
Operating Current (Chip Erase)
High performance current
Input Low Voltage
20
20
20
400
800
-0.5
0.2VCC
VCC+0.4
0.4
VIH
Input High Voltage
0.8VCC
V
VOL
VOH
Output Low Voltage
IOL =100µA
V
Output High Voltage
IOH =-100µA
VCC-0.2
V
AC Measurement Conditions
Symbol
Parameter
Min
Tpy
Max
Unit
CL
TR, TF
VIN
Load Capacitance
Input Rise And Fall time
30
5
pF
ns
V
Input Pause Voltage
0.2VCC to 0.8VCC
IN
Input Timing Reference Voltage
Output Timing Reference Voltage
0.5VCC
0.5VCC
V
OUT
V
Figure41.
AC Measurement I/O Waveform
VER 1.2
49
ACE25QC800G
8M BIT SPI NOR FLASH
AC Electrical Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit.
fc
Clock frequency for all instructions, except Read Data(03H)
Clock frequency for Dual I/O(BBH),Quad I/O(EBH),Quad
output(6BH)(Dual I/O & Quad I/O without High
Performance Mode) on 2.7v-3.0v power supply
Clock freq. Read Data instruction(03H)
Serial Clock High Time
DC.
108
MHz
Fc1
DC.
80
55
MHz
fR
DC.
MHz
ns
tCLH
tCLL
4
Serial Clock Low Time
4
ns
tCLCH Serial Clock Rise Time (Slew Rate)
tCHCL Serial Clock Fall Time (Slew Rate)
tSLCH /CS Active Setup Time
0.1(1)
0.1(1)
5
V/ns
V/ns
ns
tCHSH /CS Active Hold Time
5
ns
tSHCH /CS Not Active Setup Time
tCHSL /CS Not Active Hold Time
5
ns
5
ns
/CS High Time（read/write）
tSHSL
20
ns
tSHQZ Output Disable Time
6
ns
tCLQX Output Hold Time
0
2
2
5
5
5
5
ns
tDVCH Data In Setup Time
ns
tCHDX Data In Hold Time
ns
tHLCH /Hold Low Setup Time (relative to Clock)
tHHCH /Hold High Setup Time (relative to Clock)
tCHHL /Hold High Hold Time (relative to Clock)
tCHHH /Hold Low Hold Time (relative to Clock)
tHLQZ /Hold Low To High-Z Output
tHHQX /Hold Low To Low-Z Output
tCLQV Clock Low To Output Valid
ns
ns
ns
ns
6
6
7
ns
ns
ns
tWHSL Write Protect Setup Time Before /CS Low
tSHWL Write Protect Hold Time After /CS High
20
ns
100
ns
tDP
/CS High To Deep Power-Down Mode
20
20
µs
/CS High To Standby Mode Without Electronic Signature
Read
tRES1
µs
tRES2 /CS High To Standby Mode With Electronic Signature Read
tSUS /CS High To Next Instruction After Suspend
20
20
20
20
µs
µs
tRST_R /CS High To Next Instruction After Reset(from read)
tRST_P /CS High To Next Instruction After Reset(from program)
VER 1.2
50
ACE25QC800G
8M BIT SPI NOR FLASH
Symbol
Parameter
Min.
Typ.
Max.
12
Unit.
tRST_E /CS High To Next Instruction After Reset(from erase)
tW
tBP1
tBP2
tPP
tSE
tBE
tCE
Write Status Register Cycle Time
Byte Program Time (First Byte) (3)
5
30(2)
ms
µs
µs
ms
ms
s
30
2.5
0.6
45
50
Additional Byte Program Time (After First Byte) (3)
Page Programming Time
12
2.4
300
Sector Erase Time
Block Erase Time(32K Bytes/64K Bytes)
Chip Erase Time
0.15/0.25 0.7/0.8
10
4
s
Note:
1. Tested with clock frequency lower than 50 MHz.
2. For multiple bytes after first byte within a page, tBPn = tBP1 + tBP2 * N, where N is the number of
bytes programmed.
VER 1.2
51
ACE25QC800G
8M BIT SPI NOR FLASH
Figure42. Serial Input Timing
Figure43. Output Timing
Figure44. Hold Timing
Figure45. /WP Timing
VER 1.2
52
ACE25QC800G
8M BIT SPI NOR FLASH
Packaging information
SOP-8
mm
Inch
Symbol
Min
Nom
Max
1.75
0.20
1.55
0.51
0.25
5.03
6.20
4.00
Min
Nom
Max
A
A1
A2
b
0.069
0.008
0.061
0.020
0.010
0.198
0.244
0.158
0.10
1.35
0.36
0.15
4.77
5.80
3.80
0.15
1.45
0.41
0.20
4.90
5.99
3.90
1.27
0.66
1.05
0.54
5
0.004
0.053
0.014
0.006
0.188
0.228
0.150
0.006
0.057
0.016
0.008
0.193
0.236
0.154
0.05
C
D
E
E1
e
L
0.46
0.85
0.41
0
0.86
1.25
0.67
8
0.018
0.033
0.016
0
0.026
0.041
0.021
5
0.034
0.049
0.026
8
L1
S
θ
VER 1.2
53
ACE25QC800G
8M BIT SPI NOR FLASH
Packaging information
SOP-8L (208mil)
mm
Inch
Symbol
Min
Nom
Max
2.16
0.25
1.91
0.51
0.25
5.33
8.10
5.38
Min
Nom
Max
A
A1
A2
b
0.085
0.010
0.075
0.020
0.010
0.210
0.319
0.212
0.05
1.70
0.36
0.19
5.13
7.70
5.18
0.15
1.80
0.41
0.20
5.23
7.90
5.28
1.27
0.65
1.31
0.74
5
0.002
0.067
0.014
0.007
0.202
0.303
0.204
0.006
0.071
0.016
0.008
0.206
0.311
0.208
0.050
0.026
0.052
0.029
5
C
D
E
E1
e
L
0.50
1.21
0.62
0
0.80
1.41
0.88
8
0.020
0.048
0.024
0
0.031
0.056
0.035
8
L1
S
θ
VER 1.2
54
ACE25QC800G
8M BIT SPI NOR FLASH
Packaging information
DIP-8
mm
Inch
Symbol
Min
Nom
Max
Min
Nom
Max
A
A1
A2
b
5.33
0.21
0.38
3.18
0.36
1.14
0.20
9.02
7.62
6.22
0.015
0.125
0.014
0.045
0.008
0.355
0.300
0.245
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
8.89
3.30
1.14
3.43
0.56
1.78
0.36
10.16
8.13
6.48
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.10
0.135
0.022
0.070
0.014
0.400
0.320
0.255
B1
C
D
E
E1
e
eB
SL
S
7.87
2.92
0.76
9.53
3.81
1.52
0.310
0.115
0.030
0.350
0.130
0.045
0.375
0.150
0.060
VER 1.2
55
ACE25QC800G
8M BIT SPI NOR FLASH
Packaging information
WSON
mm
Nom
0.75
Symbol
Min
0.70
0.05
0.19
0.35
5.90
3.25
4.90
3.85
Max
A
A1
A2
b
0.80
0.22
0.42
6.00
3.37
5.00
3.97
1.27
0.04
0.60
0.25
0.48
6.10
3.50
5.10
4.10
D
D1
E
E1
e
y
0.00
0.50
0.08
0.75
L
VER 1.2
56
ACE25QC800G
8M BIT SPI NOR FLASH
Packaging information
USON3*2-8
mm
Nom
0.50
Symbol
Min
0.40
0
Max
A
A1
b
0.55
0.05
0.30
0.02
0.18
0.25
b1
c
0.16REF
0.15
0.10
1.90
1.40
0.20
2.10
1.60
D
2.00
D2
e
1.50
0.50BSC
1.50BSC
3.00
Nd
E
2.90
1.50
0.30
0.20
3.10
1.70
0.50
0.30
E2
L
1.60
0.40
h
0.25
VER 1.2
57
ACE25QC800G
8M BIT SPI NOR FLASH
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD. As
sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.2
58
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