ACE34AC04FMTH [ACE]
4K I2C Serial EEPROM with Software Write Protection;
| 型号： | ACE34AC04FMTH |
| 厂家： | 
ACE TECHNOLOGY CO., LTD. |
| 描述： | 4K I2C Serial EEPROM with Software Write Protection 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总22页 (文件大小：824K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Description
The ACE34AC04 is a 1.7V rated minimum operating voltage Serial EEPROM device containing
4096-bits of Serially Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized
as 512-bytes of eight bits each. The Serial EEPROM operation is tailored specifically for DRAM memory
modules with Serial Presence Detect (SPD) to store a module‟s vital product data such as the module‟s
size, speed, voltage, data width, and timing parameters. The ACE34AC04 is protocol compatible with the
legacy JEDEC EE1002 specification (2-Kbit) devices enabling the ACE34AC04 to be utilized in legacy
applications without any software changes. The device is designed to respond to specific software
commands that allow users to identify and set which half of the memory the internal address counter is
located. This special page addressing method to select the upper or lower half of the Serial EEPROM is
what facilitates legacy compatibility. However, there is one exception to the legacy compatibility as the
ACE34AC04 does not support the Permanent Write Protection feature. Additionally, the ACE34AC04
incorporates a Reversible Software Write Protection (RSWP) feature enabling the capability to selectively
write protect any or all of the four 128-byte quadrants. Once the RSWP is set, it can only be reversed by
sending a specific software command sequence. The ACE34AC04 supports the industry standard 2-wire
I2C Fast-Mode Plus (FM+) serial interface allowing device communication to operate at up to 1MHz. A
bus timeout feature is supported to help prevent system lock-ups. The ACE34AC04 is available in space
saving SOP, TSSOP, and UDFN packages.
Features
Low voltage and low power operations:
ACE34AC04: VCC = 1.7V to 3.6V, Industrial temperature range (-40℃ to 85℃).
Maximum Standby current < 1µA .
JEDEC JC42.4 (EE1004-v) Serial Presence Detect (SPD) Compliant
Individually reversible software write protection on all four 128-byte quadrants.
16 bytes page write mode.
Partial page write operation allowed.
Industy standard 100kHz, 400 kHz,and 1MHz I2C interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed programming cycle (5ms maximum).
Bus Timeout Supported
Automatic erase before write operation.
High reliability: typically 1,000,000 cycles endurance.
100 years data retention.
Standard 8-lead JEDEC SOP, 8-lead TSSOP, and 8-pad USON3*2-8 Pb-free packages.
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Absolute Maximum Ratings
Industrial operating temperature
Storage temperature
-40℃to 85℃
-50℃to 125℃
-0.3V to VCC + 0.3V
8V
Input voltage on any pin relative to ground
Maximum voltage
ESD protection on all pins
>2000V
*Notice: Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional
operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme
conditions may affect device reliability or functionality.
Packaging Type
SOP-8
TSSOP-8
USON3*2-8
Pin Configurations
Pin Name
Pin Function
A2, A1, A0
SDA
Device Address Inputs
Serial Data Input / Open Drain Output
Serial Clock Input
SCL
NC
No-Connect
VCC
Power Supply
GND
Ground
Ordering Information
ACE34AC04 XX + X H
Halogen - free
U：Tube
T：Tape and Reel
Pb - free
FM：SOP-8
TM：TSSOP-8
UA8：USON3*2-8
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Block Diagram
Pin Description
(A) Serial Clock (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of
this clock is to clock data out of the EEPROM device.
(B) Device / Chip Select Addresses (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are
hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL.
(C) Serial Data Line (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can
be wired-OR with other open-drain output devices.
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Device Operation
The ACE34AC04 operates as a slave device and utilizes a simple 2-wire digital serial interface,
compatible with the I2C Fast-Mode Plus (I2C FM+) protocol, to communicate with a host controller,
commonly referred to as the bus Master. The Master initiates and controls all Read and Write operations
to the slave devices on the serial bus and both the Master and the slave devices can transmit and receive
data on the bus. The serial interface is comprised of just two signal lines: the Serial Clock (SCL) and the
Serial Data (SDA). The SCL pin is used to receive the clock signal from the Master, while the bidirectional
SDA pin is used to receive command and data information from the Master, as well as, to send data back
to the Master. Data is always latched into the ACE34AC04 on the rising edge of SCL and is always output
from the device on the falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike
suppression filters and Schmitt Triggers to minimize the effects of input spikes and bus noise. All
command and data information is transferred with the Most-Significant Bit (MSB) first. During the bus
communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has
been transferred, the receiving device must respond with either an acknowledge (ACK) or a no-
acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the
Master. Therefore, nine clock cycles are required for every one byte of data transferred. There are no
unused clock cycles during any Read or Write operation so there must not be any interruptions or breaks
in the data stream during each data byte transfer and ACK or NACK clock cycle. During data transfers,
data on the SDA pin must only change while SCL is low, and the data must remain stable while SCL is
high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur.
Start and Stop conditions are used to initiate and end all serial bus communication between the Master
and the slave devices. The number of data bytes transferred between a Start and a Stop condition is not
limited and is determined by the Master. In order for the serial bus to be idle, both the SCL and SDA pins
must be in the Logic 1 state at the same time.
(A) Serial Clock And Data Transitions
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP
condition as described below.
(B) Start Condition
With SCL ≥ VIH, a SDA transition from high to low is interpreted as a START condition. All valid
commands must begin with a START condition.
(C) Stop Condition
With SCL ≥ VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read
or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after
a read command.
A STOP condition after page or byte write command will trigger the chip into the STANDBY mode
after the self- timed internal programming finish.
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
(D) Acknowledge
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The
EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The
ACKNOWLEDGE signal occurs on the 9th serial clock after each word.
(E) No-ACKNOWLEDGE (NACK)
When the ACE34AC04 is transmitting data to the Master, the Master can indicate that it is done
receiving data and wants to end the operation by sending a NACK response to the ACE34AC04
instead of an ACK response. This is accomplished by the Master outputting a Logic 1 during the
ACK/NACK clock cycle, at which point theACE34AC04 will release the SDA line so that the Master
can then generate a Stop condition.
(F) Standby Mode
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP
bit in read mode, or after completing a self-time internal programming operation.
Figure 1: Timing diagram for start and stop conditions
Figure 2: Timing diagram for output acknowledge
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
(G) Timeout Function
The ACE34AC04 supports the industry standard bus Timeout feature to help prevent potential
system bus hangups. The device resets its serial interface and will stop driving the bus (will let
SDA float high) if the SCL pin is held low for more than the minimum Timeout (tOUT) specification.
The ACE34AC04 will be ready to accept a new Start condition before the maximum tOUT has
elapsed. This feature does require a minimum SCL clock speed of 10kHz to avoid any timeout
issues.
Figure 3: Timeout
(H) Software Reset
After an interruption in protocol, power loss, or system reset, any 2-wie part can be reset by following
these steps:
1.Create a Start condition.
2.Clock nine cycles.
3.Create another Start condition followed by Stop condition.
Figure 4: Software Reset
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Device Addressing
The ACE34AC04 requires a 7-bit device address and a Read/Write select bit following a Start condition
from the Master to initiate communication with the Serial EEPROM. The device address byte is comprised
of a 4-bit device type identifier followed by three device address bits (A2, A1, and A0) and a R/W bit and is
clocked by the Master on the SDA pin with the most significant bit first .The ACE34AC04 will respond to
two unique device type identifiers. The device type identifier of ‘1010’(Ah) is necessary to select the
device for reading or writing. The device type identifier of ‘0110’(6h) has multiple purposes. First, it is used
to access the page address function which determines what the internal address counter is set to. The
device type identifier of ‘0110’(6h) is also used to access the software write protection feature of the
device.
Table 1: Device Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Read/Write
Device Type Identifier
Device Address
EEPROM
Read/Write
1
0
0
1
1
1
0
0
A2
A2
A1
A0
A0
R/ W
Write Protection and
Page Address
Functions
A1
R/ W
The software device address bits (A2, A1, and A0) must match their corresponding hard-wired device
address inputs (A2, A1 and A0) allowing up to eight devices on the bus at the same time. The eighth bit of
the address byte is the R/W operation selection bit. A read operation is selected if this bit is a Logic 1, and
a Write operation is selected if this bit is a Logic 0. Upon a compare of the device address byte, the
ACE34AC04 will output an ACK during the ninth clock cycle; if a compare is not true, the device will
output a NACK during the ninth clock cycle and return the device to the low-power Standby Mode.
Table 2: Device Address Combinations
Software Device Address Bits
Hard-wired Device Address Inputs
A2, A1, A0
000
A2
A1
A0
GND
GND
GND
GND
VCC
GND
GND
VCC
GND
VCC
001
010
GND
VCC
VCC
011
100
GND
GND
VCC
GND
VCC
VCC
101
VCC
110
GND
VCC
VCC
VCC
111
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Memory Organization
To provide the greatest flexibility and backwards compatibility with the previous generations of SPD
devices, the ACE34AC04 memory organization is organized into two independent 2-Kbit memory arrays.
Each 2-Kbit (256-byte) section is internally organized into two independent quadrants of 128 bytes with
each quadrant comprised of eight pages of 16 bytes. Including both memory sections, there are four
128-byte quadrants totaling 512 bytes.
Set Page Address and Read Page Address Commands
The ACE34AC04 incorporates an innovative memory addressing technique that utilizes a Set desired half
of the memory enabled to perform Write and Read operations. Due to the requirement for A0 pin to be
driven to VHV, the SPA and the RPA commands are fully supported in a single DIMM (isolated DIMM) end
application or a single DIMM programming station only. If SPA = 0, then the first-half or lower 256 bytes of
the Serial EEPROM is selected allowing access to Quadrant 0 and Quadrant 1. Alternately, if SPA = 1,
then the second-half or upper 256 bytes of the Serial EEPROM is selected allowing access to Quadrant 2
and Quadrant 3.
Table 3: SPA Setting and Memory Organization
Block
Set Page Address (SPA)
Memory Address Locations
00h to 7Fh
Quadrant 0
Quadrant 1
Quadrant 2
Quadrant 3
0
80h to FFh
00h to 7Fh
1
80h to FFh
Setting the Set Page Address (SPA) value selects the desired half of the EEPROM for performing Write or
Read operations. This is done by sending the SPA as seen in Figure 6-1. The SPA command sequence
requires the Master to transmit a Start condition followed by sending a control byte of ‘011011*0’ where
the ‘*’ in the bit 7 position will dictate which half of the EEPROM is being addressed. A ‘0’ in this position
(or 6Ch) is required to set the page address to the first half of the memory and a ‘1’ (or 6Eh) is necessary
to set the page address to the second half of the memory. After receiving the control byte, the
ACE34AC04 should return an ACK and the Master should follow by sending two data bytes of don’t care
values. The ACE34AC04 responds with a NACK to each of these two data bytes although the JEDEC
EE1004v specification allows for either an ACK or NACK response. The protocol is completed by the
Master sending a Stop condition to end the operation.
Figure 5: Set Page Address (SPA)
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Reading the state of the SPA can be accomplished via the Read Page Address (RPA) command. The
Master can issue the RPA command to determine if the ACE34AC04’s internal address counter is located
in the first 2-Kbit section or the second 2-Kbit memory section based upon the device’s ACK or NACK
response to the RPA command. The RPA command sequence requires the Master to transmit a Start bit
followed by a control byte of‘01101101’ (6Dh). If the device’s current address counter (page address) is
located in the first half of the memory, the ACE34AC04 responds with an ACK to the RPA command.
Alternatively, a NACK response to the RPA command indicates the page address is located in the second
half of the memory .Following the control byte and the device’s ACK or NACK response, the ACE34AC04
should transmit two data bytes of don’t care values. The Master should NACK on these two data bytes
followed by the Master sending a Stop condition to end the operation. After power-up, the SPA is set to
zero indicating internal address counter is located in the first half of the memory.
Performing a software reset will also set the SPA to zero. The ACE34AC04 incorporates a Reversible
Software Write Protect (RSWP) feature that allows the ability to selectively write protect data stored in any
or all of the four 128-byte quadrants.
Figure 6: Read Page Address (RPA)
Write Operations
The ACE34AC04 supports single Byte Write and Page Write operations up to the maximum page size of
16 bytes in one operation. The only difference between a Byte Write and a Page Write operation is the
amount of data bytes sent to the device. Regardless of whether a Byte Write or Page Write operation is
performed, the internally self-timed write cycle will take the same amount of time to write the data to the
addressed memory location(s). All Byte Write and Page Write operations should be preceded by the SPA
and or RPA commands to ensure the internal address counter is located in the desired half of the memory.
If a Byte Write or Page Write operation is attempted to a protected quadrant, the ACE34AC04 will respond
(ACK or NACK) to the write operation according to Table 4.
Table 4: Acknowledge Status When Writing Data or Defining Write Protection
Write
Cycle
No
Quadrant Status
Instruction
ACK
Word Address
ACK
Data Word
ACK
Set RSWP
Clear RSWP
Byte Write or
Page Write
to Protected
Quadrant
NACK
ACK
Don’t Care
Don’t Care
NACK Don’t Care NACK
ACK
ACK
Don’t Care
Data
ACK
ACK
Yes
Write Protected
with Set RSWP
ACK
Word Address
No
Set RSWP or
Clear RSWP
Byte Write or
Page Write
ACK
ACK
Don’t Care
ACK
ACK
Don’t Care
Data
ACK
ACK
Yes
Yes
9
Not Protected
Word Address
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
(A) Byte Write
A byte write operation starts when a micro-controller sends a START bit condition, follows by a
proper EEPROM device address and then a write command. If the device address bits match the
chip select address, the EEPROM device will acknowledge at the 9th clock cycle. The
micro-controller will then send the rest of the lower 8 bits word address. At the 18th cycle, the
EEPROM will acknowledge the 8-bit address word. The micro- controller will then transmit the 8 bit
data. Following an ACKNOWLDEGE signal from the EEPROM at the 27th clock cycle, the
micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a
self-timed programming mode during which all external inputs will be disabled. After a programming
time of TWC, the byte programming will finish and the EEPROM device will return to the STANDBY
mode.
(B) Page Write
A page write is similar to a byte write with the exception that one to sixteen bytes can be
programmed along the same page or memory row. All ACE34AC04 are organized to have 16 bytes
per memory row or page.
With the same write command as the byte write, the micro-controller does not issue a STOP bit after
sending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th
clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the
36th cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller
sends a STOP bit after the n × 9th clock cycle.
After which the EEPROM device will go into a self-timed partial or full page programming mode. After
the page programming completes after a time of TWC, the devices will return to the STANDBY
mode.
The least significant 4 bits of the word address (column address) increments internally by one after
receiving each data word. The rest of the word address bits (row address) do not change internally,
but pointing to a specific memory row or page to be programmed. The first page write data word can
be of any column address. Up to 16 data words can be loaded into a page. If more then 16 data
words are loaded, the 9th data word will be loaded to the 1st data word column address. The 10th data
word will be loaded to the 2nd data word column address and so on. In other word, data word address
(column address) will “roll” over the previously loaded data.
(C) Acknowledge Polling
ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal
programming. By issuing a valid read or write address command, the EEPROM will not acknowledge
at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the
programming completes and the chip has returned to the STANDBY mode, the device will return a
valid ACKNOWLEDGE signal at the 9th clock cycle.
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Read Operations
th
The read command is similar to the write command except the 8 read/write bit in address word is set to
“1”. The three read operation modes are described as follows:
(A) Current Address Read
The EEPROM internal address word counter maintains the last read or write address plus one if the
power supply to the device has not been cut off. To initiate a current address read operation, the
micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set
to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An
8-bit data word will then be serially clocked out. The internal address word counter will then
automatically increase by one. The address roll-over during a Read is from the last byte of the last
page to the first byte of the first page of the addressed 2-Kbit (depends on the current SPA setting).
For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th
clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the
read operation. The device then returns to STANDBY mode.
(B) Sequential Read
The sequential read is very similar to current address read. The micro-controller issues a START bit
and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with
an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially
clocked out. Meanwhile the internally address word counter will then automatically increase by one.
Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock
cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the
ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the
incremented internal address counter. If the micro-controller needs another data, it sends out an
ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked
out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal
after receiving a new data word. When the internal address counter reaches its maximum valid
address, it rolls over to the beginning of the memory array address. Similar to current address read,
the micro-controller can terminate the sequential read by not acknowledging the last data word
received, but sending a STOP bit afterwards instead.
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
(C) Random Read
Random read is a two-steps process. The first step is to initialize the internal address counter with a
target read address using a “dummy write” instruction. The second step is a current address read. To
initialize the internal address counter with a target read address, the micro-controller issues a START
bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will
then acknowledge. The micro-controller will then send the address word. Again the EEPROM will
acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs
a current address read instruction to read the data. Note that once a START bit is issued, the
EEPROM will reset the internal programming process and continue to execute the new instruction
which is to read the current address.
Figure 7: Byte Write
Figure 8: Page Write
Figure 9: Current Address Read
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Figure 10: Sequential Read
Figure 11: Random Read
Write Protection
The ACE34AC04 incorporates a Reversible Software Write Protection (RSWP) feature that allows the
ability to selectively write protect data stored in each of the four independent 128-byte EEPROM
quadrants. Table 5 identifies the memory quadrant identifier with its associated quadrant, SPA and
memory address locations.
Table 5: Memory Organization
Block
Set Page Address (SPA)
0
Memory Address Locations
00h to 7Fh
Quadrant 0
Quadrant 1
Quadrant 2
Quadrant 3
80h to FFh
00h to 7Fh
1
80h to FFh
(A) Set RSWP
Setting the RSWP is enabled by sending the Set RSWP command, similar to a normal Write
command to the device which programs the write protection to the target quadrant. The Set RSWP
sequence requires sending a control byte of ‘0110MMM0’ (where ‘M’ represents the memory
quadrant identifier for the target quadrant to be write-protected) with the R/W bit set to a Logic 0. In
conjunction with sending the protocol, the A0 pin must be connected to VHV for the duration of the
RSWP sequence.
The Set RSWP command acts on a single quadrant only as specified in the Set RSWP command
and can only be reversed by issuing the Clear RSWP command and will unprotect all quadrants in
one operation.
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Table 6: Set RSWP and Clear RSWP
Control Byte
Pin
Function
Device Type Identifier
Bit 7 Bit 6 Bit 5 Bit 4
Memory Quadrant Identifier R/ W
A2
X
A1
X
A0
Bit 3
0
Bit 2
0
Bit 1
1
Bit 0
0
Set RSW P,
Quadrant 0
Set RSW P,
Quadrant 1
Set RSW P,
Quadrant 2
Set RSW P,
Quadrant 3
X
X
X
X
1
1
0
0
0
1
0
0
VHV
0
1
1
0
X
X
X
X
0
0
0
1
0
1
0
0
Clear RSWP
X = Don’t care but recommended to be hard-wired to VCC or GND.
Due to the requirement for the A0 pin to be driven to VHV, the RSWP set and RSWP clear commands are
fully supported in a single DIMM (isolated DIMM) end application or a single DIMM programming station
only.
Figure 11: Set RSWP and Clear RSWP
X = Don’t care
(B) Clear RSWP
Similar to the Set RSWP command, the reversible write protection on all quadrants can be reversed
or unprotected by transmitting the Clear RSWP command. The Clear RSWP sequence requires the
Master to send a Start condition followed by sending a control byte of „01100110‟(66h) with the R/W
bit set to a Logic 0. The ACE34AC04 should respond with an ACK. The Master transmits a word
address byte and data bytes with don’t care values. The ACE34AC04 will respond with either an
ACK or NACK to both the word address and data word. In conjunction with sending the protocol, the
A0 pin must be connected to VHV for the duration of the Clear RSWP command. To end the Clear
RSWP sequence, the Master sends a Stop condition.
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
(C) Read RSWP
The Read RSWP command allows the ability to check a quadrant’s write protection status. To find
out if the software write protection has been set to a specific quadrant, the same procedure that was
used to set the quadrant’s write protection can be utilized except that the R/W select bit is set to a
Logic 1, and the A0 pin is not required to have VHV. The Read RSWP sequence requires sending a
control byte of „0110MMM1‟ (where the „M‟ represents the memory quadrant identifier for the
quadrant to be read) with the R/W bit set to a Logic 1 .If the RSWP has not been set, then the
ACE34AC04 responds to the control byte with an ACK. If the RSWP has been set, the ACE34AC04
responds with a NACK. In either case, both Word Address and Data Word bytes will not be
acknowledged. The operation is completed by the Master creating a Stop Condition.
Table 7: Acknowledge When Reading Protection Status
Word
Address
Sent
Word
Quadrant
Status
Instruction
Sent
Instruction
Response
Data Word
Sent
Data Word
Response
Address
Response
Write
Protected
Not
Read RSWP
Read RSWP
NACK
ACK
Don’t Care
Don’t Care
NACK
NACK
Don’t Care
Don’t Care
NACK
NACK
Protected
Table 8: Read RSWP
Control Byte
Memory Quadrant Identifier R/ W
Pin
Function
Device Type Identifier
Bit 7 Bit 6 Bit 5 Bit 4
A2
A1
X
A0
Bit 3
0
Bit 2
0
Bit 1
1
Bit 0
1
Set RSW P,
Quadrant 0
Set RSW P,
Quadrant 1
Set RSW P,
Quadrant 2
Set RSW P,
Quadrant 3
X
X
X
X
X
X
X
1
1
0
0
0
0
0
1
0
1
1
1
0,1
or
0
1
1
0
VHV
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Figure 12: Read RSWP
X = Don’t care
Figure 13: SCL and SDA Bus Timing
X = Don’t care
Electrical Specifications
(A) Power-Up Requirements
During a power-up sequence, the VCC supplied to the device should monotonically rise from GND to
the minimum VCC level, with a slew rate no faster than 0.05 V/μs and no slower then 0.1 V/ms. A
decoupling cap should be connected to the VCC PAD which is no smaller than 10nF.
(B) Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a
power-up sequence, this device includes a Power-on Reset (POR) circuit. Upon power-up, the
device will not respond to any commands until the VCC level crosses the internal voltage threshold
(VPOR) that brings the device out of Reset and into Standby mode. The system designer must
ensure the instructions are not sent to the device until the VCC supply has reached a stable value
greater than or equal to the minimum VCC level.
Figure 14: Power on and Power down
If an event occurs in the system where the VCC level supplied to the device drops below the maximum
VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the
VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up sequence
in compliance with the requirements defined in this section.
VER 1.1
16
ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
AC Characteristics
VCC < 2.2V
100kHz
VCC ≥ 2.2V
Symbol
Parameter
Units
400kHz
1000kHz
Min
Max
Min
Max
10(2)
10(2)
10(2)
500
fSCL
tLOW
tHIGH
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
100
400
50
1,000
kHz
ns
4,700
1,300
600
4,000
260
ns
tI
Noise Suppression Time
50
50
ns
Time the bus must be free
before a new transmission
can start(1)
tBUF
4,700
1,300
500
ns
tHD.STA
tSU.STA
tHD.DI
tSU.DAT
tR
Start Hold Time
4,000
4,700
0.0
600
600
0.0
100
20
260
260
0.0
50
ns
ns
ns
ns
ns
ns
ns
ns
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
250
1,000
300
300
300
120
120
tF
20
tSU.STO
tHD.DAT
4,000
200
600
200
260
0
3,450
50
900
50
350
50
(1)
Vcc slew rate at power up
0.1
100
500
25
0.1
100
500
25
0.1
100
500
25
V/ms
tPWR,R
Time required after VCC is
stable before the device can
accept commands
(1)
µs
tPUP
Minimum time at Vcc=0V
between power cycles
Write Cycle Time
(1)
tPOFF
ms
tWR
5
5
5
ms
ms
tOUT
Timeout Time
35
35
35
Write
Endurance
25°C, Page Mode(1)
1,000,000
Cycles
Notes：
1. This Parameter is expected by characterization but is not fully screened by test.
2. The minimum frequency is specified at 10kHz to avoid activating the timeout feature.
VER 1.1
17
ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Units
VCC
Supply Voltage
1.7
3.6
V
Read at
ICC1
Supply Current
VCC = 3.6V
VCC = 3.6V
1.0
3.0
3.0
4.0
mA
mA
μA
100kHz
Write at
100kHz
VIN = VCC or
VSS
ICC2
Supply Current
Standby Current
VCC = 1.7V
ISB
VIN = VCC or
VSS
VCC = 3.6V
μA
ILI
ILO
Input Leakage Current
Output Leakage Current
Input Low Level(1)
VIN = VCC or VSS
VOUT = VCC or VSS
2.0
2.0
µA
µA
µA
µA
V
VIL
-0.5
VCC*0.3
VCC+0.5
0.4
VIH
Input High Level(1)
VCC*0.7
VOL1
VOL2
V
CC > 2V
IOL = 3mA
Low-Level Output Voltage
Open-Drain
VCC ≤ 2V
IOL = 2mA
Freq ≤
0.2*VCC
V
V
OL = 0.4V
VOL = 0.6V
VOL = 0.4V
3.0
6.0
mA
mA
mA
400kHz
Freq ≤
IOL
Low-Level Output Current
400kHz
Freq >
20.0
400kHz
VHV
A0 Pin High Voltage
VHV - VCC ≥ 4.8V
7
10
V
V
V
VHYST1
VHYST2
Input Hysteresis (SDA, SCL)
Input Hysteresis (SDA, SCL)
VCC < 2V
0.10*VCC
0.05*VCC
VCC ≥ 2V
Note: VIL min and VIH max are reference only and are not tested.
VER 1.1
18
ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Packaging information
TSSOP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
D
E
2.900
4.300
0.190
0.090
6.250
3.100
4.500
0.300
0.200
6.550
1.100
1.000
0.150
0.114
0.169
0.007
0.004
0.246
0.122
0.177
0.012
0.008
0.258
0.043
0.039
0.006
b
c
E1
A
A2
A1
e
0.800
0.020
0.031
0.001
0.65 (BSC)
0.25 (TYP)
0.026 (BSC)
L
0.500
1°
0.700
7°
0.020
1°
0.028
H
θ
0.01 (TYP)
7°
VER 1.1
19
ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Packaging information
SOP-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
1.350
0.100
1.350
0.330
0.170
4.700
3.800
5.800
1.750
0.250
1.550
0.510
0.250
5.100
4.000
6.200
0.053
0.004
0.053
0.013
0.006
0.185
0.150
0.228
0.069
0.010
0.061
0.020
0.010
0.200
0.157
0.244
c
D
E
E1
e
1.270 (BSC)
0.050 (BSC)
L
0.400
0°
1.270
8°
0.016
0°
0.050
8°
θ
VER 1.1
20
ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Packaging information
USON3*2-8
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
0.021
0.002
0.039
A
A1
b
0.450
0.000
0.180
0.550
0.050
0.300
0.017
0.000
0.007
b1
c
0.160REF
0.006REF
0.100
1.900
1.400
0.200
2.100
1.600
0.004
0.075
0.055
0.008
0.083
0.062
D
D2
e
0.500BSC
1.500BSC
0.020BSC
0.059BSC
Nd
E
2.900
1.500
0.300
0.200
3.100
1.700
0.500
0.300
0.114
0.059
0.012
0.066
0.122
0.067
0.020
0.12
E2
L
h
VER 1.1
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ACE34AC04
4K I2C Serial EEPROM with Software Write Protection
Notes
ACE does not assume any responsibility for use as critical components in life support devices or systems
without the express written approval of the president and general counsel of ACE Electronics Co., LTD.
As sued herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and shoes failure to perform when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety
or effectiveness.
ACE Technology Co., LTD.
http://www.ace-ele.com/
VER 1.1
22
相关型号：
ACE358
The ACE358 consists of two independent high gain, internally frequency compensated operational amplifier. It can be operated from a Single power supply and also split power supplies.
ACE
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