5962-9215605QYC [ACTEL]
Field Programmable Gate Array, 8000 Gates, 1232-Cell, CMOS, CQFP172, QFP-172;![5962-9215605QYC](http://pdffile.icpdf.com/pdf2/p00286/img/icpdf/5962-9215604_1717692_icpdf.jpg)
型号: | 5962-9215605QYC |
厂家: | ![]() |
描述: | Field Programmable Gate Array, 8000 Gates, 1232-Cell, CMOS, CQFP172, QFP-172 栅 |
文件: | 总34页 (文件大小:367K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
REVISIONS
LTR
A
DESCRIPTION
DATE (YR-MO-DA)
94-03-03
APPROVED
M. A. Frye
Added changes in accordance with NOR 5962-R116-94.
M. A. Frye
B
Added 03 device, removed CAGE number 01295, and made editorial
changes throughout.
96-07-09
C
D
E
F
Added changes in accordance with NOR 5962-R059-97.
Added changes in accordance with NOR 5962-R193-97.
Corrected radiation circuit. Updated boilerplate. ksr
96-11-12
97-03-03
98-03-31
98-09-18
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
Add 04 and 05 devices, change case outlines from CQCC2-F172 to
figure 4. Page 3, section 1.3 changed TJ from 175°C to 150°C.
Added appendix A for die. Added CQFP package option case U, and
binning circuitry delay for 04 and 05 in Table IA. ksr
G
Change the generic number for the 01 and 02 devices as well as the
bin speed. Update the binning circuit delay on table IA. Update the
bin speed for the 01 device in section 10.2.2. ksr
98-11-15
Raymond Monnin
H
J
Replaced figure 1, case outline Y with new graphic art work. ksr
Boilerplate update, part of 5 year review. ksr
00-04-28
07-05-28
Raymond Monnin
Robert M. Heber
REV
SHEET
REV
J
J
J
J
J
J
J
21
J
J
22
J
J
23
J
J
24
J
J
25
J
J
26
J
J
27
J
J
28
J
J
29
J
J
30
J
J
31
J
J
32
J
SHEET
15
16
17
18
19
20
REV STATUS
OF SHEETS
REV
J
J
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Rajesh Pithadia
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Jeff Bowling
STANDARD
MICROCIRCUIT
DRAWING
APPROVED BY
Michael A. Frye
MICROCIRCUIT, MEMORY, DIGITAL,
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
CMOS, FIELD PROGRAMMABLE GATE
ARRAY, 8000 GATES, MONOLITHIC
SILICON
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
93-04-07
REVISION LEVEL
J
SIZE
CAGE CODE
AMSC N/A
5962-92156
67268
A
SHEET
1 OF 32
DSCC FORM 2233
APR 97
5962-E317-07
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
92156
01
│
Q
│
│
│
Y
│
│
│
C
│
│
│
│
│
│
│
│
│
│
│
Federal
stock class
designator
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
\
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
Bin speed
01
02
03
04
05
1280A
8000 gate field programmable gate array
8000 gate field programmable gate array
8000 gate field programmable gate array
8000 gate field programmable gate array
8000 gate field programmable gate array
200 ns
170 ns
160 ns
120 ns
102 ns
1280A-1
RH1280
1280XL
1280XL-1
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level
as follows:
Device class
M
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN
class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
X
Y
Z
U
CMGA7 - P176
See figure 1
CMGA7 - P176
See figure 1
176
172
177
172
Pin grid array
Quad flat pack
Pin grid array with orientation pin
Quad flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
2
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/
DC supply voltage range (VCC) ..................................................................... -0.5 V dc to +7.0 V dc
Input voltage range (VI) ................................................................................ -0.5 V dc to VCC + 0.5 V dc
Output voltage range (VO) ............................................................................ -0.5 V dc to VCC + 0.5 V dc
Input clamp current (IIC)................................................................................ ±20 mA
Output clamp current (IOC)............................................................................ ±20 mA
Continuous output current (IO) ...................................................................... ±25 mA
Storage temperature range (TSTG)................................................................ -65°C to +150°C
Lead temperature (soldering, 10 seconds) ................................................... 300°C
Thermal resistance, junction-to-case (ΘJC) :
Case X and Z.............................................................................................. See MIL-STD-1835
Case Y and U ............................................................................................. 10°C/W 2/
Maximum junction temperature (TJ).............................................................. +150°C
1.4 Recommended operating conditions.
Supply voltage (VCC)..................................................................................... +4.5 V dc to +5.5 V dc
Case operating temperature range (TC)........................................................ -55°C to +125°C
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, test method 5012) ............................................. 100 percent 3/
1.6 Radiation features
Maximum total dose available (dose rate = 50 - 300 rads(Si)/s).......................... 300K rads(Si) 4/
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
-
Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil from the
Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated
herein.
3/ 100 percent test coverage of blank programmable logic devices.
4/ Device electrical characteristics are guaranteed for post irradiation levels at 25°C, in low dose rate environment (post 168
hours, 100°C, biased anneal).
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
3
DSCC FORM 2234
APR 97
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192-00
-
Standard Guide for the Measurement of Single Event Phenomena from
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr
Harbor Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)
ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD78
-
IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201; http://www.jedec.org.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless
a specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 and figure 1 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table(s).
3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered
item drawing is not part of this drawing. When required in screening (see 4.2 herein) or quality conformance inspection group A,
B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of
the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for any altered
item drawing pattern.
3.2.3.2 Programmed devices. The truth table or test vectors for programmed devices shall be as specified by an attached
altered item drawing.
3.2.4 Switching test circuit and waveforms . The switching test circuit and waveforms diagram shall be as specified on figure
3.
3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 4.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full
case operating temperature range.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
4
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/
4.5 V < VCC < 5.5 V
-55°C < TC < +125°C
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Max
Unit
Min
3.7
High Level output voltage
Low level output voltage
VOH
VOL
Test one output at a time,
CC = 4.5 V, IOH = -3.2 mA
1, 2, 3
1, 2, 3
All
All
All
V
V
V
Test one output at a time,
CC = 4.5 V, IOL = 4.0 mA
0.4
V
Low level input voltage
High level input voltage
VIL
VIH
1, 2, 3
1, 2, 3
-0.3
2.0
0.8
V
V
01,02,
04,05
VCC +0.3
03
All
2.2
VCC +0.3
25
Standby supply current
IDD
Outputs unloaded,
1, 2, 3
mA
VCC = 5.5 V,
VIN = VCC or GND
Input leakage current
Output leakage current
IIL
VCC = 5.5 V,
IN = VCC or GND
1, 2, 3
1, 2, 3
All
All
-10
-10
10
10
20
µA
µA
pF
V
IOZ
VCC = 5.5 V,
VO = VCC or GND
I/O terminal capacitance
Functional tests
CI/O
See 4.4.1c, f= 1.0 Mhz,
4
All
All
VOUT = 0 V
FT 2/
See 4.4.1e, VO = 0 V,
CC = 4.5 V
7, 8A, 8B
9, 10, 11
V
Binning circuit delay
tPBLH,
tPBHL
See figure 3, VIL = 0 V,
ns
01
02
03
04
05
200
170
160
120
102
V
V
IH = 3.0 V, VCC = 4.5 V,
OUT = 1.5 V 3/
1/ All tests shall be performed under the worst case condition unless otherwise specified. Devices supplied to this drawing will
meet levels M, D, L, R, and F, of irradiation. However, this device is only tested at the "F" level. Pre and post irradiation
values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for
any RHA level, TA = +25°C.
2/ Devices are functionally tested using a serial scan test method. Data is shifted into the SDI pin and the DCLK pin is used
as a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete functional test to
be performed. The outputs of the module can be read by shifting out the output response or by monitoring the PRA, PRB,
or SDO pins. These tests form a part of the manufacturer's test tape and shall be maintained and available at the approved
source(s) of supply upon request by DSCC or the OEM.
3/ Binning circuit delay is defined as the input-to-output delay of a special path called the "binning circuit". The binning circuit
consists of one input buffer plus 16 combinatorial logic modules plus one output buffer. The logic modules are distributed
along the left side of the device. These modules are configured as non-inverting buffers and are connected through
programmed antifuses with typical capacitive loading.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
5
DSCC FORM 2234
APR 97
TABLE IB. SEP test limits. 1/
Symbol
Characteristics
Logic Modules
Conditions
Bias
VCC
Effective LET no
upset/latchup
Maximum
=
device cross
section µm2/bit
LET = 120
(MeV-cm2/mg)
SEL
SEU
Single event
latchup
All
5.5 V
177
N/A
-55°C≤Tcase≤125°C
Single event
upset
Combinatorial
Sequential
All
4.5 V
4.5 V
5.5 V
17
4
110
320
N/A
-55°C≤Tcase≤125°C
-55°C≤Tcase≤125°C
-55°C≤Tcase≤125°C
SEDR
2/
Single event
dielectric
(antifuse) rupture
>60 2/
1/ Verification test per TRB approved test plan.
2/ Tested at worst case that ions having perpendicular incidence, cross section < 0.002um2/antifuse at LET = 60 MeV-cm2/mg.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 42 (see MIL-PRF-38535, appendix A).
3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in
a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item drawing.
3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 4.4.1
and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program
configuration.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
6
DSCC FORM 2234
APR 97
3.11.2 Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions
herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery.
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical
parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).
c. Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified. Quality conformance inspection for device
class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for
device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 5 and 6 of table IA of method 5005 of MIL-STD-883 shall be omitted.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
7
DSCC FORM 2234
APR 97
c. Subgroup 4 (C and C
IN OUT
measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the designated
terminal and GND at a frequency equal or less than 1 MHz. Sample size is five (5) devices with no failures, and all
input and output terminals tested.
d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's technical review board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the
preparing activity or acquiring activity upon request. Testing shall be on all pins, on 5 devices with zero failures.
Latch-up test shall be considered destructive. Information contained in JEDEC Standard EIA/JESD 78 may be used
for reference.
e. Programmed device (see 3.2.3.2) - For device class M, subgroups 7, 8A, and 8B tests shall consist of verifying the
functionality of the device. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of
the device. These tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.6
herein).
f. Unprogrammed devices shall be tested for programmability and dc and ac performance compliance to the
requirements of group A, subgroups 1 and 7.
(1) A sample shall be selected from each wafer lot to satisfy programmability requirements. Eight devices shall be
submitted to programming (see 3.2.3.1). If any device fails to program, the lot shall be rejected. At the
manufacturer's option, the sample may be increased to 18 total devices with no more than two total device failures
allowable.
(2) These eight devices shall also be submitted to the requirements of the specified tests of group A, subgroups 1 and
7. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 18
total devices with no more than two total device failures allowable.
(3a) Eight devices from the programmability sample shall be submitted to the requirements of group A, subgroups 9 for
binning circuit delay only. If any device fails, the lot shall be rejected. At the manufacturer's option, the sample may
be increased to 18 total devices with no more than two total device failures allowable.
(3b) If the binning circuit is tested on 100 percent of the products, then the above requirement (3A) is met.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005.
b.
T = +125°C, minimum.
A
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-
883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table IIA herein.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
8
DSCC FORM 2234
APR 97
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at
T
= +25°C ± 5°C, after exposure, to the subgroups specified in table IIA herein.
A
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A and as specified herein.
4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater than
5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-
irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after any
design or process changes which may affect the RHA response of the device.
4.4.4.2 Single event phenomena (SEP). SEP testing shall be required on class V devices (see 1.6 herein). SEP testing shall
be performed on a technology process on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by
the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup
characteristics. The recommended test conditions for SEP are as follows:
a. The package lid of the DUT is removed so as to provide an unobstructed path to the die for the ion beam.
b. The DUT is biased or exercised as appropriate to that IC being tested.
c. The temperature that SEP tests are conducted at is 25°C +/- 10°C (ambient).
d. Particle penetration range is > 20 microns (Si).
e. The flux used is between 102 and 105 ions/cm2/s.
f. The beam incidence angle(s) used are between 0° to 60° from normal.
g. Supply current and voltage(s) as well as SEU, SEL and faults are monitored and recorded in-situ.
h. For SEP test limits, see Table IB herein.
4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7,
and 9.
4.6 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be
made available upon request.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
9
DSCC FORM 2234
APR 97
Case Y
NOTES:
1. Tie bar is for reference only, the vendor supplies the tie bar with the 4 small corner holes as oblong holes, contact vendor
for other tie bar options.
2. All exposed metalized areas and leads are gold plated 100 micro inches (2.5 µm) minimum thickness over 80 to 350 micro
inches (2.0 to 8.9 µm) thickness nickel.
3. Seal ring area is connected to GNDA.
4. Die attach pad is connected to GNDA.
5. GNDQ (4 PLS) is connected to GNDA.
6. Tolerances unless otherwise specified: ±1% N.L.T ±0.005
FIGURE 1. Case outlines.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
10
DSCC FORM 2234
APR 97
Case Y - Continued
Dimension (unit: inch)
Symbol
Min.
Norm.
0.110
Max
A
A1
0.093
0.060
0.006
0.007
0.004
1.168
0.125
0.080
0.012
0.010
0.008
1.192
0.070
A2
0.009
b
0.008
c
0.006
D1/E1
D2/E2
e
1.180
1.050 BSC
0.025 BSC
0.870
F1
0.860
2.485
0.880
2.505
L1
2.495
L2
2.320 BSC
1.500
L3
1.485
1.515
H1
2.140 BSC
8.8 gm (typical)
Weight
Metric conversion is for convenience only.
Symbol Dimension (unit: mm)
Min.
2.36
1.52
0.15
0.18
0.10
29.67
Norm.
2.79
1.78
0.23
0.20
Max.
A
A1
A2
b
c
D1/E1
D2/E2
e
3.18
2.03
0.30
0.25
0.20
30.28
0.15
29.97
26.67
0.64
F1
L1
L2
L3
H1
Weight
21.84
63.12
22.10
63.37
58.93
38.10
54.36
8.8 gm (typical)
22.35
63.63
37.72
38.48
FIGURE 1. Case outlines - Continued.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
11
DSCC FORM 2234
APR 97
Case U
NOTES:
1. Tie bar is for reference only, vendor supplies tie bar with oblong holes, contact vendor for other tie bar options.
2. All exposed metalized areas and leads are gold plated 100 microinches (2.5 µ mm) minimum thickness over 80 to 350
microinches (2.0 to 8.9 µ mm) thickness nickel.
3. Seal ring area is connected to GNDA.
4. Die attach pad is connected to GNDA.
5. GNDQ (4 PLS) is connected to GNDA.
6. Tolerances unless otherwise specified: ±1% N.L.T ±0.005
FIGURE 1. Case outlines - Continued.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
12
DSCC FORM 2234
APR 97
Case U - Continued.
Symbol
Dimension (inches)
Dimension (millimeters)
Min
Min
Max
Max
3.71
0.33
0.20
29.52
A
0.116
0.007
0.004
1.138
0.146
0.013
0.008
1.162
2.95
0.17
b
c
0.10
D1
28.91
D2
1.050 BSC
0.025 BSC
26.67 BSC
0.635 BSC
e
F1
0.890
0.881
2.485
1.690
0.079
0.900
0.890
2.505
1.710
0.103
22.60
22.38
63.12
42.93
2.00
22.86
22.60
63.63
43.43
2.62
F4
L1
L2
A1
N (number of leads)
Weight
172
20 gm (Typical - with tie bar removed)
FIGURE 1. Case outlines - Continued.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
J
13
DSCC FORM 2234
APR 97
Case outlines X and Z
Device
type
All
Device
type
All
Device
type
All
Device
type
All
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
C1
C2
C3
C4
C5
C6
C7
C8
C9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CKA or I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCK or I/O
I/O
I/O
I/O
I/O
CKB or I/O
I/O
I/O
I/O
I/O
I/O
SDI or I/O
I/O
I/O
I/O
MODE
I/O
I/O
I/O
I/O
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
E1
E2
E3
E4
E5
E12
E13
E14
E15
F1
F2
F3
F4
F12
F13
F14
F15
G1
G2
G3
G4
I/O
I/O
I/O
H1
H2
H3
I/O
VSV or VCC
VCC
GND
GND
VCC
VSV or VCC
I/O
I/O
I/O
I/O
VCC
GND
VKS or GND
VPP or VCC
I/O
I/O
I/O
M13
M14
M15
N1
N2
N3
N4
N5
N6
N7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDO or I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
GND
PRB or I/O
VCC
I/O
GND
VCC
GND
I/O
H4
H12
H13
H14
H15
J1
J2
J3
J4
J12
J13
J14
J15
K1
K2
K3
K4
K12
K13
K14
K15
L1
L2
L3
L4
L12
L13
L14
L15
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
N8
N9
N10
N11
N12
N13
N14
N15
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
I/O
I/O
I/O
I/O
I/O
GND
GND 1/
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
GND
I/O
GND
VCC
I/O
I/O
I/O
G12
G13
G14
G15
GND
PRA or I/O
I/O
I/O
I/O
I/O
I/O
I/O
C10
C11
C12
C13
C14
C15
GND
I/O
GND
VCC
GND
1/ E5 is an orientation pin that is available on package Z only.
FIGURE 2. Terminal connections.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-92156
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
14
DSCC FORM 2234
APR 97
Case outline Y and U
Device
type
All
Device
type
All
Device
type
All
Device
type
All
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
2
3
4
5
6
7
8
MODE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
I/O
I/O
GND
I/O
I/O
VKS
VPP
GND
VCC
VSV
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDI or I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
VCC
GND
I/O
CKB or I/O
I/O
PRB or I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
SDO or I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
DCK or I/O
I/O
GND
VCC
VSV
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
PRA or I/O
I/O
CKA or I/O
I/O
FIGURE 2. Terminal connections - Continued.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-92156
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
15
DSCC FORM 2234
APR 97
FIGURE 3. Switching test circuit and waveforms.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
16
DSCC FORM 2234
APR 97
Note: Resistors are 1kΩ resistors.
FIGURE 4. Radiation exposure circuit.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-92156
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
17
DSCC FORM 2234
APR 97
TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Line
no.
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
Subgroups
(in accordance with
MIL-PRF-38535, table III)
TM 5005, table I)
Device
class M
Device
class Q
Device
class V
1
2
Interim electrical parameters
(see 4.2)
1, 7, 9
Static burn-in
(method 1015)
Not
required
Not
required
Required
3
4
Same as line 1
1*, 7* ∆
Dynamic burn-in
(method 1015)
Required
Required
Required
5
6
Same as line 1
1*, 7* ∆
Final electrical
parameters (see 4.2)
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
7
8
Group A test requirements (see
4.4)
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
Group C end-point electrical
2, 3, 7,
8A, 8B
2, 3, 7,
8A, 8B
1, 2, 3, 7, 8A,
8B, 9, 10, 11 ∆
parameters
(see 4.4)
9
Group D end-point electrical
parameters (see 4.4)
2, 3, 8A, 8B
1, 7, 9
2, 3, 8A, 8B
1, 7, 9
2, 3, 8A, 8B
10
Group E end-point electrical
parameters (see 4.4)
1, 7, 9
1/ Blank spaces indicate tests are not applicable.
2/ Any or all subgroups may be combined when using high-speed testers.
3/ Subgroups 7 and 8 functional tests shall verify the functionality for unprogrammed devices or that the altered item
drawing pattern exists for programmed devices.
4/ * indicates PDA applies to subgroup 1 and 7.
5/ ** see 4.4.1c.
6/ ∆ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed with
reference to the previous interim electrical parameters (see line 1).
7/ See 4.4.1d
TABLE IIB. Delta limits at +25°C.
Parameter 1/
Device types
All
IDD
IOZ
±10% of specified value of table IA
±10% of specified value of table IA
±10 ns
tPBLH, tPBHL
1/ The above parameter shall be recorded before and after
the required burn-in and life tests to determine the delta.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
18
DSCC FORM 2234
APR 97
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that much time (even though most devices do not require it). On the other hand,
responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum
since the device never provides data later than that time.
6.5.2 Waveforms.
Waveform
symbol
Input
Output
MUST BE
WILL BE
VALID
VALID
CHANGE FROM
H TO L
WILL CHANGE FROM
H TO L
CHANGE FROM
L TO H
WILL CHANGE FROM
L TO H
DON'T CARE
ANY CHANGE
PERMITTED
CHANGING
STATE UNKNOWN
HIGH
IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
19
DSCC FORM 2234
APR 97
Appendix A
Appendix A forms a part of SMD 5962-92156
A.1 Scope
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QML plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices
using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes
consisting of military high reliability (device class Q) and space application (device Class V) are reflected in the Part or
Identification Number (PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
|
|
F
|
|
92156
01
|
|
Q
|
|
9
|
|
X
|
|
Federal
stock class
designator
RHA
designator
(10.2.1)
Device
type
(see 10.2.2)
Device
class
(see 10.2.3)
Die
Code
(see 10.2.4)
Die
details
(see 10.2.5)
\___________ __________/
V
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
Generic number
Circuit function
Bin speed
01
03
04
1280A
RH1280
1280XL
8000 gate, field programmable gate array
8000 gate, field programmable gate array
8000 gate, field programmable gate array
200 ns
160 ns
120 ns
A.1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level
as follows:
Device class
Q or V
Device requirements documentation
Certification and qualification to MIL-PRF-38535
A.1.2.4 Die code. The die code designator shall be a number 9 for all devices supplied as die only with no case outline.
A.1.2.5 Die details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.5.1 Die physical dimensions.
Device type
Die size
Die thickness
Die Detail
Figure Number
01
01
03
04
421mils X 437mils
421mils X 437mils
365 mils X 385 mils
286 mils X 299 mils
15±1 mils
16±1 mils
25±1 mils
19±1 mils
A
B
C
D
A-1
A-2
A-3
A-4
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
20
DSCC FORM 2234
APR 97
A.1.2.5.2 Die bonding pad locations and electrical functions.
Device type
Die Detail
Figure Number
01
01
03
04
A
B
C
D
A-1
A-2
A-3
A-4
A.1.2.5.3 Interface materials.
Device type
Top metalization
Backside metalization
Die Detail
Figure Number
01
01
03
04
Ti-cap+Al/Cu/Si,9-12k
TiW+Al/Cu,9-12k
Ti-cap+Al/Cu/Si,9-12k
Ti-cap+Al/Cu/Si,9-12k
None (backgrind)
None (backgrind)
None (backgrind)
None (backgrind)
A
B
C
D
A-1
A-2
A-3
A-4
A.1.2.5.4 Assembly related information.
Device type
Glassivation
Die Detail
Figure Number
01
01
03
04
Ox/Nitride
Ox/Nitride
Ox/Nitride
Ox/Nitride
A
B
C
D
A-1
A-2
A-3
A-4
A.1.2.5.5 Wafer fabrication source.
Device type
Source
Die Detail
Figure Number
01
01
03
04
Matsushita Electronics Corp. Japan
Texas Instrument, Texas
Lockheed Martin Federal System, VA
Chartered Semiconductor, Singapore
A
B
C
D
A-1
A-2
A-3
A-4
A.1.3 Absolute maximum ratings.
See paragraph 1.3 within the body of this drawing for details.
A.1.4 Recommended operating conditions.
See paragraph 1.4 within the body of this drawing for details.
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
21
DSCC FORM 2234
APR 97
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing shall take precedence. Nothing in this document, however, supersedes applicable laws and regulations unless
a specific exemption has been obtained.
A.3 REQUIREMENTS.
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-
PRF-389535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
Modification in the QM plan shall not effect the form, fit or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified
in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be specified in A.1.2.5.1 and on figures A-1, A-2, A-3,
and A-4.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.5.2 and on figures A-1, A-2, A-3, and A-4.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.5.3 and on figures A-1, A-2, A-
3, and A-4.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.5.4 and figures A-1,
A-2, A-3, and A-4.
A.3.2.5 Truth table(s). Where technically applicable, (for die) the truth table(s) shall be as defined within paragraph 3.2.3 of
the body of this document.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit will be as specified on figure 4 as shown within the body of
this document.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN
listed in 10.2 herein. The certification mark shall be “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-
38535 listed manufacturer in order to supply to the requirements of this drawing (see 60.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.3.8 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result
in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item
drawing.
A.3.8.1 Unprogrammed die delivered to the user. All testing shall be verified through wafer probe test as defined in A.4.2.
A.3.8.2 Manufacturer-programmed die delivered to the user. The programming integrity test shall be performed during
programming. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program
configuration.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
22
DSCC FORM 2234
APR 97
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modification in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum it shall consist of:
a) Wafer lot acceptance for Class V product using the criteria within MIL-STD-883 test method 5007.
b) 100% wafer probe (see paragraph 30.4)
c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 test method 2010
or the alternate procedures allowed within MIL-STD-883 test method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
30.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified within paragraphs 4.4.4,
4.4.4.1, 4.4.4.1.1, and 4.4.4.2 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit application (original equipment), design applications and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43218-3990 or telephone
(614)-692-0547.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined within
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and have
agreed to this drawing.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
23
DSCC FORM 2234
APR 97
Pad#
1
2
3
4
5
6
7
8
Name
GND
MODE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
VCC
VSV, VCC
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X-Coord
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
-5075
Y-Coord
4932
4668
4495
4184
4009
3837
3662
3490
3318
3143
2974
2800
2560
2316
2141
1969
1794
1616
1428
1253
1081
906
Pad#
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Name
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X-Coord
-4706
-4073
-3793
-3613
-3444
-3269
-3100
-2859
-2619
-2450
-2275
-2106
-1945
-1782
-1613
-1438
-1269
-1095
-926
Y-Coord
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
-5284
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
-751
-582
-407
-165
154
453
628
800
377
133
-602
-848
-1022
-1276
-1528
-1702
-1875
-2053
-2373
-2626
-2800
-2973
-3148
-3402
-3658
-3833
-4005
-4180
-4389
-4928
975
1147
1322
1495
1669
1912
2160
2335
2507
2682
2852
3013
3188
3360
3533
4151
4709
I/O
VCC
I/O
I/O
I/O
I/O
SDO, I/O
I/O
I/O
I/O
I/O
See notes at end of table
Figure A-1 and A-2. A1280A Bond Pad Locations and Functions
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
24
DSCC FORM 2234
APR 97
Pad#
89
90
91
92
93
94
95
96
Name
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
VKS, GND
VPP, VCC
GND
VCC
VSV, VCC
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X-Coord
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
5075
Y-Coord
-4833
-4375
-4166
-3991
-3818
-3644
-3471
-3297
-3124
-2950
-2777
-2602
-2429
-2268
-2094
-1921
-1746
-1574
-1413
-1238
-604
Pad#
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Name
GND
I/O
SDI, I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
CLKA, I/O
VCC
GND
I/O
CLKB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
X-Coord
4620
4062
3882
3609
3436
3261
3089
2842
2629
2457
2282
2110
1876
1642
1470
1295
1122
948
775
595
350
176
3
-172
-393
-568
Y-Coord
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
5284
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
63
428
665
989
1232
1406
1579
1751
1925
2098
2272
2438
2606
2780
2953
3128
3289
3461
3636
3808
3983
4394
4952
-743
-987
-1168
-1340
-1515
-1688
-2003
-2288
-2460
-2635
-2807
-2987
-3160
-3333
-3507
-3680
-4188
-4715
I/O
I/O
I/O
DCLK, I/O
I/O
Note: 1. All dimensions in micrometer
2. The die center is the coordinate origin (0,0).
3. VSV, VKS and Vpp pins are used for programming. For normal operation, these pins should be connected to
Vcc or GND as shown.
Figure A-1 and A-2. A1280A Bond Pad Locations and Functions - Continued.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
25
DSCC FORM 2234
APR 97
Figure A-1 and A-2. A1280A Bond Pad Locations and Functions - Continued.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-92156
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
26
DSCC FORM 2234
APR 97
Pad #
1
2
3
4
5
6
7
8
Name
GND
MODE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
VCC
VSV, VCC
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X Coords
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
-4301
Y Coords
4178
4019
3867
3723
3579
3436
3223
2976
2730
2518
2305
2093
1863
1695
1545
1395
1245
1076
915
Pad #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Name
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X Coords
-3963
-3811
-3652
-3508
-3364
-3220
-3077
-2869
-2662
-2491
-2318
-2145
-1938
-1731
-1558
-1385
-1212
-1039
-867
Y Coords
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
-4516
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
771
627
483
13
-199
-726
-872
-694
-521
-348
-156
24
247
451
656
-1017
-1181
-1347
-1491
-1635
-1778
-1940
-2197
-2435
-2674
-2912
-3185
-3458
-3601
-3745
-3889
-4033
-4178
860
1064
1269
1473
1678
1917
2156
2360
2550
2739
2976
3222
3366
3509
3653
3819
3963
I/O
VCC
I/O
I/O
I/O
I/O
SDO, I/O
I/O
I/O
I/O
I/O
See notes at end of table.
Figure A-3. RH1280 Bond Pad Locations and Functions
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-92156
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
27
DSCC FORM 2234
APR 97
Pad #
89
90
91
92
93
94
95
96
Name
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
VKS, GND
VPP, VCC
GND
VCC
VSV, VCC
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X Coords
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
4301
Y Coords
-4176
-4016
-3866
-3717
-3568
-3418
-3013
-2869
-2725
-2581
-2438
-2294
-2116
-1938
-1794
-1650
-1507
-1342
-1165
-1007
-564
Pad #
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Name
GND
I/O
SDO, I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
CLKA, I/O
VCC
GND
I/O
CLKB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
X Coords
3963
3551
3407
3263
3120
2956
2794
2598
2401
2239
2077
1915
1719
1522
1360
1198
1036
874
712
550
372
210
48
-132
-356
-543
Y Coords
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
4516
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
-97
96
323
516
675
833
-729
-932
1010
1178
1328
1478
1628
1796
1977
2140
2303
2466
2663
2860
3023
3186
3330
3672
4178
-1119
-1305
-1492
-1678
-1899
-2120
-2307
-2494
-2680
-2901
-3114
-3286
-3430
-3574
-3717
-3963
I/O
I/O
I/O
DCLK, I/O
I/O
Note: 1. All dimensions in micrometer
2. The die center is the coordinate origin (0,0).
3. VSV, VKS and Vpp pins are used for programming. For normal operation, these pins should be connected to
Vcc or GND as shown.
Figure A-3. RH1280 Bond Pad Locations and Functions - Continued.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
28
DSCC FORM 2234
APR 97
Figure A-3. RH1280 Bond Pad Locations and Functions - Continued.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-92156
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
29
DSCC FORM 2234
APR 97
Pad #
1
2
3
4
5
6
7
8
Name
GND
MODE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
VCC
VSV, VCC
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X Coords
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
-3453
Y Coords
3354
3226
3104
2989
2874
2758
2587
2389
2191
2021
1851
1681
1496
1361
1240
1120
999
864
734
619
503
388
11
-160
-583
Pad #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Name
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X Coords
-3182
-3060
-2932
-2816
-2701
-2585
-2470
-2303
-2137
-2000
-1861
-1722
-1556
-1389
-1251
-1112
-973
-834
-696
-557
-418
-280
-125
19
198
Y Coords
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
-3625
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
-700
-817
-948
362
526
690
855
-1082
-1197
-1312
-1428
-1558
-1764
-1955
-2146
-2338
-2557
-2776
-2891
-3007
-3122
-3237
-3354
1019
1183
1347
1539
1731
1895
2047
2199
2389
2587
2702
2817
2933
3066
3182
I/O
VCC
I/O
I/O
I/O
I/O
SDO, I/O
I/O
I/O
I/O
I/O
See notes at end of table.
Figure A-4. A1280XL(0.6µm) Bond Pad Locations and Functions
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-92156
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
30
DSCC FORM 2234
APR 97
Pad #
89
90
91
92
93
94
95
96
Name
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
VKS, GND
VPP, VCC
GND
VCCI
VSV, VCC
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
X Coords
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
3453
Y Coords
-3352
-3224
-3104
-2984
-2864
-2744
-2419
-2303
-2188
-2072
-1957
-1842
-1699
-1556
-1440
-1325
-1210
-1077
-936
Pad #
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Name
GND
I/O
SDI, I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
CLKA, I/O
VCC
GND
I/O
CLKB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
X Coords
3182
2851
2735
2620
2505
2373
2243
2086
1928
1798
1668
1538
1380
1222
1092
962
832
702
572
442
299
169
39
-106
Y Coords
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
3625
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
-808
-453
-78
77
260
414
542
669
-286
-436
-586
-748
811
946
-898
1066
1186
1307
1442
1587
1718
1849
1980
2138
2296
2427
2558
2673
2948
3354
-1048
-1198
-1347
-1525
-1702
-1852
-2002
-2152
-2329
-2500
-2638
-2754
-2869
-2984
-3182
I/O
I/O
I/O
DCLK, I/O
I/O
Note: 1. All dimensions in micrometer
2. The die center is the coordinate origin (0,0).
3. VSV, VKS and Vpp pins are used for programming. For normal operation, these pins should be connected to
Vcc or GND as shown.
Figure A-4. A1280XL(0.6µm) Bond Pad Locations and Functions - Continued.
SIZE
STANDARD
5962-92156
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
31
DSCC FORM 2234
APR 97
Figure A-4. A1280XL(0.6µm) Bond Pad Locations and Functions - Continued.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-92156
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
J
SHEET
32
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 07-05-28
Approved sources of supply for SMD 5962-92156 are listed below for immediate acquisition only and shall be added to MIL-
HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or
deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to
and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-
38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard microcircuit 1/
drawing PIN
Vendor
CAGE
number
Vendor
similar 3/
PIN
5962-9215601MXC
5962-9215601MYC
0J4Z0
2/
A1280A-PG176B
TPC1280MGB176B
0J4Z0
2/
A1280A-CQ172B
TPC1280MHFG172B
5962-9215601MXA
5962-9215601MYA
5962-9215601MZC
0J4Z0
0J4Z0
A1280A-PG176B
A1280A-CQ172B
2/
2/
A1280A-PG177B
TPC1280MGB177B
5962-9215601MUC
5962-9215602MXC
2/
RP1280A-CQ172B
0J4Z0
2/
A1280A-1PG176B
TPC1280MGB176B-1
5962-9215602MYC
0J4Z0
2/
A1280A-1CQ172B
TPC1280MHFG172B-1
5962-9215602MXA
5962-9215602MYA
5962-9215602MZC
0J4Z0
0J4Z0
A1280A-1PG176B
A1280A-1CQ172B
2/
2/
A1280A-1PG177B
TPC1280MGB177B-1
5962-9215602MUC
5962F9215603QYC
5962-9215604QXC
5962-9215604QYC
5962-9215605QXC
5962-9215605QYC
2/
RP1280A-1CQ172B
RH1280-CQ172V
A1280XL-PG176B
A1280XL-CQ172B
A1280XL-1PG176B
A1280XL-1CQ172B
2/
0J4Z0 4/
0J4Z0 4/
0J4Z0 4/
0J4Z0 4/
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that part.
If the desired lead finish is not listed, contact the vendor to determine
its availability.
2/ No longer available from an approved source.
3/ Caution. Do not use this number for item acquisition. Items acquired to
this number may not satisfy the performance requirements of this drawing.
4/ Vendor has indicated and end-of-life (EOL) date of 3/30/2007
Vendor CAGE
number
Vendor name
and address
0J4Z0
Actel Corporation
955 East Arques Ave.
Sunnyvale, CA 94086
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN - Continued.
The following table lists the SMD part numbers for die.
Standard microcircuit
drawing PIN
Vendor
CAGE
number
Vendor
similar 1/
PIN
5962-9215601Q9A
5962-9215601Q9B
5962F9215603Q9C
5962-9215604Q9D
0J4Z0
0J4Z0
2/
A1280A-DIE
A1280A-DIE
RH1280-DIE
A1280XL-DIE
0J4Z0 3/
1/ Caution. Do not use this number for item acquisition. Items acquired to
this number may not satisfy the performance requirements of this drawing.
2/ No longer available from an approved source.
3/ Vendor has indicated and end-of-life (EOL) date of 3/30/2007
Vendor CAGE
number
Vendor name
and address
0J4Z0
Actel Corporation
955 East Arques Ave.
Sunnyvale, CA 94086
The information contained herein is disseminated for convenience
only and the Government assumes no liability whatsoever for any
inaccuracies in this information bulletin.
相关型号:
![](http://pdffile.icpdf.com/pdf2/p00278/img/page/5962-9215702_1661883_files/5962-9215702_1661883_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00278/img/page/5962-9215702_1661883_files/5962-9215702_1661883_2.jpg)
5962-9215701MSA
Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, CDFP20, CERPACK-20
IDT
![](http://pdffile.icpdf.com/pdf2/p00278/img/page/5962-9215702_1661883_files/5962-9215702_1661883_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00278/img/page/5962-9215702_1661883_files/5962-9215702_1661883_2.jpg)
5962-9215702M2A
Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, CQCC20, LCC-20
IDT
![](http://pdffile.icpdf.com/pdf2/p00278/img/page/5962-9215702_1661883_files/5962-9215702_1661883_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00278/img/page/5962-9215702_1661883_files/5962-9215702_1661883_2.jpg)
5962-9215702MRA
Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, CDIP20, 0.300 INCH, CERDIP-20
IDT
©2020 ICPDF网 联系我们和版权申明