5962-9875901QXX [ACTEL]
Field Programmable Gate Array, 1362 CLBs, 10000 Gates, CMOS, CQFP84, CERAMIC, QFP-84;型号: | 5962-9875901QXX |
厂家: | Actel Corporation |
描述: | Field Programmable Gate Array, 1362 CLBs, 10000 Gates, CMOS, CQFP84, CERAMIC, QFP-84 栅 |
文件: | 总98页 (文件大小:2005K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
v3.0
HiRel FPGAs
Features
• Low-Power 0.8µ CMOS Technology
• Highly Predictable Performance with 100% Automatic
Placement and Routing
3200DX Features
• 100 MHz System Logic Integration
• Device Sizes from 1,200 to 20,000 Gates
• Up to 6 Fast, Low-Skew Clock Networks
• Up to 202 User-Programmable I/O Pins
• More Than 500 Macro Functions
• Up to 1,276 Dedicated Flip-Flops
• I/O Drive to 10 mA
• Highest Speed FPGA SRAM, up to 2.5 kbits Configurable
Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Low-Power 0.6µ CMOS Technology
1200XL Features
• Pin for Pin Compatible with ACT 2
• System Performance to 50 MHz over Military Temperature
• Low-Power 0.6µ CMOS Technology
• Devices Available to DSCC SMD
• CQFP and CPGA Packaging
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 100% Military Temperature Tested (–55°C to +125°C)
• QML Certified Devices
ACT 2 Features
• Best-Value, High-Capacity FPGA Family
• System Performance to 40 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
• Proven Reliability Data Available
• Successful Military/Avionics Supplier for Over 10 Years
ACT 1 Features
ACT 3 Features
• Lowest-Cost FPGA Family
• Highest-Performance, Highest-Capacity FPGA Family
• System Performance to 60 MHz over Military Temperature
• System Performance to 20 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
Product Family Profile (more devices on page 2)
Family
Device
3200DX
ACT 3
1200XL
A32100DX A32200DX
A1425A
A1460A
A14100A
A1280XL
Capacity
System Gates
Logic Gates
SRAM Bits
15,000
10,000
2,048
30,000
20,000
2,560
3,750
2,500
NA
9,000
6,000
NA
15,000
10,000
NA
12,000
8,000
Logic Modules
S-Modules
C-Modules
Decode
1,362
700
662
20
2,414
1,230
1,184
24
310
160
150
NA
848
432
416
NA
1,377
697
680
NA
1,232
624
608
NA
Flip-Flops (Maximum)
User I/Os (Maximum)
738
152
1,276
202
435
100
976
168
1,493
228
998
140
Performance
System Speed (maximum)
55 MHz
84
55 MHz
60 MHz
60 MHz
60 MHz
50 MHz
Packages (by Pin Count)
CPGA
CQFP
133
132
207
196
257
256
176
172
208, 256
January 2000
1
© 2000 Actel Corporation
Product Family Profile
Family
Device
ACT 2
ACT 1
A1240A
A1280A
A1010B
A1020B
Capacity
System Gates
Logic Gates
SRAM Bits
6,000
4,000
NA
12,000
8,000
NA
1,800
1,200
NA
3,000
2,000
NA
Logic Modules
S-Modules
C-Modules
Decode
684
348
336
NA
1,232
624
608
NA
295
—
295
NA
547
—
547
NA
Flip-Flops (maximum)
User I/Os (maximum)
568
104
998
140
147
57
273
69
Packages (by pin count)
CPGA
CQFP
132
—
176
172
84
—
84
84
Performance
20 MHz
20 MHz
System Speed (maximum)
40 MHz
40 MHz
High-Reliability, Low-Risk Solution
junction temperatures. Actel’s non-PLD architecture delivers
lower dynamic operating current. Our reliability tests show a
very low failure rate of 6.6 FITs at 90°C junction temperature
with no degradation in AC performance. Special stress testing
at wafer test eliminates infant mortalities prior to packaging.
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability
ratings of less than 10 Failures-In-Time (FITs),
corresponding to a useful life of more than 40 years. Actel
FPGAs have been production proven, with more than five
million devices shipped and more than one trillion antifuses
manufactured. Actel devices are fully tested prior to
shipment, with an outgoing defect level of less than 100 ppm.
(Further reliability data is available in the Actel Device
Reliability Report, at http://www.actel.com/hirel).
Minimized Security Risk
Reverse engineering of programmed Actel devices from
optical or electrical data is extremely difficult. Programmed
antifuses cannot be identified from a photograph or by using
an SEM. The antifuse map cannot be deciphered either
electrically or by microprobing. Each device has a silicon
signature that identifies its origins, down to the wafer lot and
fabrication facility.
Benefits
Minimized Cost Risk
Minimized Testing Risk
With Actel’s line of development tools, designers can produce
as many chips as they choose for just the cost of the device
itself. There will be no NRE charges to cut into the
development budget each time a new design is tried.
Unprogrammed Actel parts are extensively tested at the
factory. Routing tracks, logic modules, and programming,
debug and test circuits are 100 percent tested before
shipment. AC performance is ensured by special speed path
tests, and programming circuitry is verified on test antifuses.
During the programming process, an algorithm is run to
ensure that all antifuses are correctly programmed. In
addition, Actel’s Silicon Explorer diagnostic tool uses
ActionProbe circuitry, allowing 100 percent observability of
all internal nodes to check and debug the design.
Minimized Time Risk
After the design is entered, placement and routing is
automatic, and programming the device takes only about 5 to
15 minutes for an average design. Designers save time in the
design entry process by using tools with which they are
familiar.
Minimized Reliability Risk
Actel FPGA Description
The PLICE antifuse is a one-time programmable, nonvolatile
connection. Since Actel devices are permanently
programmed, no downloading from EPROM or SRAM storage
is required. Inadvertent erasure is impossible, and there is no
need to reload the program after power disruptions.
Fabrication using a low-power CMOS process means cooler
The Actel families of FPGAs offer a variety of packages,
speed/performance characteristics, and processing levels for
use in all high reliability and military applications. Devices
are implemented in a silicon gate, two-level metal CMOS
process, utilizing Actel’s PLICE antifuse technology. This
2
HiRel FPGAs
ACT 3 Description
unique architecture offers gate array flexibility, high
performance, and quick turnaround through user
programming. Device utilization is typically 95 percent of
available logic modules. All Actel devices include on-chip
clock drivers and a hard-wired distribution network.
The ACT 3 family is the third-generation Actel FPGA
family. This family offers the highest-performance and
highest-capacity devices, ranging from 2,500 to 10,000 gates,
with system performance up to 60 MHz over the military
temperature range. The devices have four clock distribution
networks, including dedicated array and I/O clocks. In
addition, the ACT 3 family offers the highest I/O-to-gate ratio
available. ACT 3 devices are manufactured using 0.8µ CMOS
technology.
User-definable I/Os are capable of driving at both TTL and
CMOS drive levels. Available packages for the military are the
Ceramic Quad Flat Pack (CQFP) and the Ceramic Pin Grid
Array (CPGA). See the “Product Plan” section on page 6 for
details.
QML Certification
1200XL/3200DX Description
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits. QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
3200DX and 1200XL FPGAs were designed to integrate
system logic which is typically implemented in multiple
CPLDs, PALs, and FPGAs. These devices provide the features
and performance required for today’s complex, high-speed
digital logic systems. The 3200DX family offers the industry’s
fastest dual-port SRAM for implementing fast FIFOs, LIFOs,
and temporary data storage.
ACT 2 Description
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
The ACT 2 family is the second-generation Actel FPGA family.
This family offers the best-value, high-capacity devices,
ranging from 4,000 to 8,000 gates, with system performance
up to 40 MHz over the military temperature range. The
devices have two routed array clock distribution networks.
ACT 2 devices are manufactured using 1.0µ CMOS technology.
Development Tool Support
ACT 1 Description
The HiRel devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP Series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place and route tools.
Designer Advantage is Actel’s suite of FPGA development
point tools for PCs and Workstations that includes the
ACTgen Macro Builder, Designer with DirectTime timing
driven place and route and analysis tools, and device
programming software.
The ACT 1 family is the first Actel FPGA family and the first
antifuse-based FPGA. This family offers the lowest-cost logic
integration, with devices ranging from 1,200 to 2,000 gates,
with system performance up to 20 MHz over the military
temperature range. The devices have one routed array clock
distribution network. ACT 1 devices are manufactured using
1.0µ CMOS technology.
In addition, the HiRel devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100 percent real-time observation and analysis of a
device’s internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer, an easy to use
integrated verification and logic analysis tool that can sample
data at 100 MHz (asynchronous) or 66 MHz (synchronous).
Silicon Explorer attaches to a PC’s standard COM port,
turning the PC into a fully functional 18 channel logic
analyzer. Silicon Explorer allows designers to complete the
design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
3
Military Device Ordering Information
A14100
A
–
1
CQ
256
B
Application (Temperature Range)
C = Commercial (0 to +70°C)
M = Military (–55 to +125°C)
B = MIL-STD-883 Class B
E = Extended Flow (Space Level)
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack (CQFP)
PG = Ceramic Pin Grid Array (CPGA)
Speed Grade
Std = Standard Speed
–1 = Approximately 15% faster than Standard
Device Revision
Part Number
A1010 = 1,200 Gates—ACT 1
A1020 = 2,000 Gates—ACT 1
A1240 = 4,000 Gates—ACT 2
A1280 = 8,000 Gates—ACT 2/1200XL
A1425 = 2,500 Gates—ACT 3
A1460 = 6,000 Gates—ACT 3
A14100 = 10,000 Gates—ACT 3
A32100 = 10,000 Gates—3200DX
A32200 = 20,000 Gates—3200DX
4
HiRel FPGAs
DESC SMD/Actel Part Number Cross Reference
Actel Part Number
(Gold Leads)
DSCC SMD
DSCC SMD
(Gold Leads)
(Solder Dipped)
A1010B-PG84B
5962-9096403MXC
5962-9096404MXC
5962-9096503MUC
5962-9096504MUC
5962-9096503MTC
5962-9096504MTC
5962-9322101MXC
5962-9322102MXC
5962-9215601MXC
5962-9215602MXC
5962-9215601MYC
5962-9215602MYC
5962-9552001MXC
5962-9552002MXC
5962-9552001MYC
5962-9552002MYC
5962-9550801MXC
5962-9550802MXC
5962-9550801MYC
5962-9550802MYC
5962-9552101MXC
5962-9552102MXC
5962-9552101MYC
5962-9552102MYC
5962-9875901QXC
5962-9857902QXC
5962-9952701QXC
5962-9952702QXC
5962-9952701QYC
5962-9952702QYC
5962-9096403MXA
A1010B-1PG84B
A1020B-PG84B
5962-9096404MXA
5962-9096503MUA
A1020B-1PG84B
A1020B-CQ84B
5962-9096504MUA
5962-9096503MTA
A1020B-1CQ84B
A1240A-PG132B
A1240A-1PG132B
A1280A-PG176B
A1280A-1PG176B
A1280A-CQ172B
A1280A-1CQ172B
A1425A-PG133B
A1425A-1PG133B
A1425A-CQ132B
A1425A-1CQ132B
A1460A-PG207B
A1460A-1PG207B
A1460A-CQ196B
A1460A-1CQ196B
A14100A-PG257B
A14100A-1PG257B
A14100A-CQ256B
A14100A-1CQ256B
A32100DX-CQ84B
A32100DX-1CQ84B
A32200DX-CQ256B
A32200DX-1CQ256B
A32200DX-CQ208B
A32200DX-1CQ208B
5962-9096504MTA
5962-9322101MXA
5962-9322102MXA
5962-9215601MXA
5962-9215602MXA
5962-9215601MYA
5962-9215602MYA
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5
Product Plan
Speed Grade
Application
Std
–1*
C
M
B
E
3200DX Family
A32100DX Device
84-pin Ceramic Quad Flat Pack (CQFP)
A32200DX Device
✔
✔
✔
✔
✔
—
208-pin Ceramic Quad Flat Pack (CQFP)
256-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
ACT 3 Family
A1425A Device
132-pin Ceramic Quad Flat Pack (CQFP)
133-pin Ceramic Pin Grid Array (CPGA)
A1460A Device
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
196-pin Ceramic Quad Flat Pack (CQFP)
207-pin Ceramic Pin Grid Array (CPGA)
A14100A Device
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
256-pin Ceramic Quad Flat Pack (CQFP)
257-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
1200XL Family
A1280XL Device
172-pin Ceramic Quad Flat Pack (CQFP)
176-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
ACT 2 Family
A1240A Device
132-pin Ceramic Pin Grid Array (CPGA)
A1280A Device
✔
✔
✔
✔
✔
—
172-pin Ceramic Quad Flat Pack (CQFP)
176-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
ACT 1 Family
A1010B Device
84-pin Ceramic Pin Grid Array (CPGA)
A1020B Device
✔
✔
✔
✔
✔
—
84-pin Ceramic Quad Flat Pack (CQFP)
84-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Applications: C = Commercial
M = Military
Availability: ✔ = Available
— = Not Planned
*Speed Grade: –1 = Approx. 15% faster than Standard
B = MIL-STD-883
E = Extended Flow
6
HiRel FPGAs
3200DX Device Resources
User I/Os
CQFP
Gate Array
Equivalent
Gates
FPGA
Device Type
Logic
Modules
84-pin
208-pin
256-pin
A32100DX
1,362
10,000
60
—
—
A32200DX
2,414
20,000
—
176
202
ACT 3 Device Resources
User I/Os
Gate Array
Equivalent
Gates
CQFP
CPGA
FPGA
Device Type
Logic
Modules
132-pin
196-pin
256-pin
133-pin
207-pin
257-pin
A1425A
A1460A
A14100A
310
848
2,500
6,000
100
—
—
168
—
—
—
100
—
—
168
—
—
—
1,377
10,000
—
228
—
228
1200XL Device Resources
User I/Os
Gate Array
CQFP
172-pin
140
CPGA
176-pin
140
FPGA
Logic
Equivalent
Gates
Device Type
Modules
A1280XL
1,232
8,000
ACT 2 Device Resources
User I/Os
Gate Array
Equivalent
Gates
CQFP
CPGA
FPGA
Device Type
Logic
Modules
172-pin
132-pin
176-pin
A1240A
A1280A
684
4,000
8,000
—
104
—
—
1,232
140
140
ACT 1 Device Resources
User I/Os
Gate Array
Equivalent
Gates
CQFP
84-pin
CPGA
84-pin
FPGA
Device Type
Logic
Modules
A1010B
A1020B
295
547
1,200
2,000
—
57
69
69
7
Actel MIL-STD-883 Product Flow
883—Class B
Requirement
Step
Screen
883 Method
1.
2.
3.
Internal Visual
2010, Test Condition B
1010, Test Condition C
100%
100%
100%
Temperature Cycling
Constant Acceleration
2001, Test Condition D or E,
Y1, Orientation Only
4.
Seal
1014
a. Fine
b. Gross
100%
100%
5.
6.
Visual Inspection
2009
100%
100%
Pre-Burn-In
Electrical Parameters
In accordance with applicable Actel
device specification
7.
Burn-in Test
1015, Condition D,
160 hours @ 125°C or 80 hours @ 150°C
100%
100%
8.
Interim (Post-Burn-In)
Electrical Parameters
In accordance with applicable Actel
device specification
9.
Percent Defective Allowable
Final Electrical Test
5%
All Lots
10.
In accordance with applicable Actel
device specification, which includes a, b, and c:
a. Static Tests
100%
100%
(1) 25°C
(Subgroup 1, Table I)
(2) –55°C and +125°C
(Subgroups 2, 3, Table I)
5005
5005
b. Functional Tests
(1) 25°C
(Subgroup 7, Table I)
(2) –55°C and +125°C
(Subgroups 8A and 8B, Table I)
5005
5005
c. Switching Tests at 25°C
(Subgroup 9, Table I)
100%
100%
5005
2009
11.
External Visual
Note: When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method 2018
must be waived.
8
HiRel FPGAs
Actel Extended Flow1
Require-
ment
Step Screen
Method
1.
Wafer Lot Acceptance2
Destructive In-Line Bond Pull3
Internal Visual
5007 with Step Coverage Waiver
2011, Condition D
All Lots
Sample
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
All Lots
2.
3.
2010, Condition A
4.
Serialization
5.
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Radiographic
1010, Condition C
6.
2001, Condition D or E, Y1 Orientation Only
2020, Condition A
7.
8.
2012 (one view only)
9.
Pre-Burn-In Test
In accordance with applicable Actel device specification
1015, Condition D, 240 hours @ 125°C minimum
10.
11.
12.
13.
Burn-in Test
Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification
Reverse Bias Burn-In 1015, Condition C, 72 hours @ 150°C minimum
Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification
Percent Defective Allowable (PDA)
Calculation
5%, 3% Functional Parameters @ 25°C
14.
15.
Final Electrical Test
In accordance with Actel applicable device specification
which includes a, b, and c:
100%
100%
a. Static Tests
(1) 25°C
5005
5005
(Subgroup 1, Table1)
(2) –55°C and +125°C
(Subgroups 2, 3, Table 1)
b. Functional Tests
100%
(1) 25°C
5005
5005
(Subgroup 7, Table 15)
(2) –55°C and +125°C
(Subgroups 8A and B, Table 1)
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
100%
100%
5005
1014
16.
Seal
a. Fine
b. Gross
17.
External Visual
2009
100%
Notes:
1. Actel offers the extended flow for customers who require additional screening beyond the requirements of the MIL-STD-833, Class B. Actel is
compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow
incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004
are shown in notes 2 and 3 below.
2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived.
3. MIL-STD-883, Method 5004 requires 100 percent Radiation latch-up testing (Method 1020). Actel will not be performing any radiation testing,
and this requirement must be waived in its entirety.
9
Absolute Maximum Ratings1
Recommended Operating Conditions
Free air temperature range
Parameter
Commercial
Military
Units
Symbol
Parameter
Limits
Units
Temperature
Range1
0 to +70
–55 to +125
°C
VCC
VI
DC Supply Voltage2, 3, 4
Input Voltage
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±20
V
V
Power Supply
Tolerance2
±5
±10
%VCC
VO
IIO
Output Voltage
V
Notes:
I/O Source Sink
Current5
mA
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
2. All power supplies must be in the recommended operating range.
For more information, refer to the Power-Up Design Considerations
application note at http://www.actel.com/appnotes.
TSTG
Storage Temperature
–65 to +150
°C
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Devices should not be operated outside
the recommended operating conditions.
2. VPP = VCC , except during device programming.
3. VSV = VCC , except during device programming.
4.
5. Device inputs are normally high impedance and draw extremely
low current. However, when input voltage is greater than VCC
VKS = GND , except during device programming.
+
0.5V or less than GND – 0.5V, the internal protection diode will be
forward biased and can draw excessive current.
Electrical Specifications
Commercial
Military
Max.
Symbol Parameter
Test Condition
Min.
Max.
Min.
Units
1, 2
VOH
HIGH Level Output
IOH = –4 mA (CMOS)
3.7
V
V
I
OH = –6 mA (CMOS)
3.84
1, 2
VOL
VIH
VIL
LOW Level Output
HIGH Level Input
LOW Level Input
Input Leakage
IOL = +6 mA (CMOS)
TTL Inputs
0.33
VCC + 0.3
0.8
0.4
VCC + 0.3
0.8
V
2.0
–0.3
–10
–10
2.0
–0.3
–10
–10
V
TTL Inputs
V
IIN
VI = VCC or GND
VO = VCC or GND
+10
+10
µA
µA
pF
IOZ
3-state Output Leakage
I/O Capacitance3, 4
+10
+10
CIO
ICC(S)
10
10
Standby VCC Supply Current VI = VCC or GND, IO = 0 mA
ACT 1
3
2
20
20
mA
mA
ACT 2/3/1200XL/3200DX
ICC(D)
Dynamic VCC Supply Current
See the “Power Dissipation” section on page 11.
Notes:
1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required.
2. Tested one output at a time, VCC = min.
3. Not tested; for information only.
4. VOUT = 0V, f = 1 MHz
10
HiRel FPGAs
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc, and
the junction to ambient air characteristic is θja. The thermal
characteristics for θja are shown with two different air flow
rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a CPGA 176-pin package at military
temperature is as follows:
Max. junction temp. (°C) – Max. military temp.
150°C – 125°C
----------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1 . 1 W
θja (°C/W) 23°C/W
θja
θja
Package Type
Pin Count
θjc
Still Air
300 ft/min
Units
Ceramic Pin Grid Array
84
6.0
4.8
4.8
4.6
3.5
2.8
33
25
25
23
21
15
20
16
15
12
10
8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
132
133
176
207
257
Ceramic Quad Flat Pack
84
7.8
7.2
6.8
6.4
6.2
40
35
25
23
20
30
25
20
15
10
°C/W
°C/W
°C/W
°C/W
°C/W
132
172
196
256
Power Dissipation
General Power Equation
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst-case conditions.
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N +
OH * (VCC – VOH) * M
I
Family
ACT 3
ICC
VCC
Power
10.5 mW
10.5 mW
10.5 mW
15.8 mW
where:
CCstandby is the current flowing when no inputs or outputs
are changing.
2 mA
2 mA
2 mA
3 mA
5.25V
5.25V
5.25V
5.25V
I
1200XL/3200DX
ACT 2
I
CCactive is the current flowing due to CMOS switching.
OL, IOH are TTL sink/source currents.
OL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL
M equals the number of outputs driving TTL loads to
VOH
I
ACT 1
V
The static power dissipated by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all
outputs driving low, and 140 mW with all outputs driving high.
.
.
Active Power Component
Accurate values for N and M are difficult to determine
because they depend on the family type, on the design, and on
the system I/O. The power can be divided into two
components—static and active.
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totempole current in CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
Static Power Component
Actel FPGAs have small static power components that result
in power dissipation lower than that of PALs or PLDs. By
integrating multiple PALs or PLDs into one FPGA, an even
greater reduction in board-level power dissipation can be
achieved.
11
can be combined with frequency and voltage to represent
active power dissipation.
where:
m
n
=
=
=
=
Number of logic modules switching at fm
Number of input buffers switching at fn
Number of output buffers switching at fp
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
p
q1
Number of clock loads on the first routed
array clock (all families)
Power (uW) = CEQ * VCC2 * F
(1)
where:
CEQ
VCC
F
q2
=
Number of clock loads on the second routed
array clock (ACT 2, 1200XL, 3200DX, ACT 3
only)
= Equivalent capacitance in pF
= Power supply in volts (V)
= Switching frequency in MHz
r1
r2
s1
s2
=
=
=
=
Fixed capacitance due to first routed array
clock (all families)
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements are made over a range
of frequencies at a fixed value of VCC. Equivalent capacitance
is frequency independent so that the results can be used over
a wide range of operating conditions. Equivalent capacitance
values are shown below.
Fixed capacitance due to second routed array
clock (ACT 2, 1200XL, 3200DX, ACT 3 only)
Fixed number of clock loads on the dedicated
array clock (ACT 3 only)
Fixed number of clock loads on the dedicated
I/O clock (ACT 3 only)
CEQ Values for Actel FPGAs
CEQM
CEQI
=
=
=
Equivalent capacitance of logic modules in pF
Equivalent capacitance of input buffers in pF
1200XL
ACT 3 3200DX ACT 2 ACT 1
CEQO
Equivalent capacitance of output buffers
in pF
Modules (CEQM
)
6.7
7.2
5.2
5.8
12.9
23.8
3.7
22.1
31.2
Input Buffers (CEQI
)
11.6
23.8
CEQCR
CEQCD
CEQCI
=
=
=
Equivalent capacitance of routed array clock
in pF
Output Buffers (CEQO
)
10.4
Equivalent capacitance of dedicated array
clock in pF
Routed Array Clock
Buffer Loads (CEQCR
Dedicated Clock Buffer
Loads (CEQCD
I/O Clock Buffer Loads
(CEQCI
)
1.6
0.7
0.9
3.5
N/A
N/A
3.9
N/A
N/A
4.6
N/A
N/A
Equivalent capacitance of dedicated I/O clock
in pF
)
CL
fm
fn
=
=
=
=
=
Output lead capacitance in pF
)
Average logic module switching rate in MHz
Average input buffer switching rate in MHz
Average output buffer switching rate in MHz
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piecewise linear summation
over all components that applies to all ACT 1, 1200XL,
3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has
only one routed array clock, the terms labeled routed_Clk2,
dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2
family has two routed array clocks, and the dedicated_Clk
and IO_Clk terms do not apply. For ACT 3 devices, all terms
will apply.
Power = VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs
(p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1
+ (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2
(r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk
fp
fq1
Average first routed array clock rate in MHz
(all families)
fq2
fs1
fs2
=
=
=
Average second routed array clock rate in
MHz (ACT 2, 1200XL, 3200DX, ACT 3 only)
Average dedicated array clock rate in MHz
(ACT 3 only)
Average dedicated I/O clock rate in MHz
(ACT 3 only)
+
+
+
(s2 * CEQCI * fs2)IO_Clk
]
(2)
12
HiRel FPGAs
Fixed Capacitance Values for
Actel FPGAs (pF)
Fixed Clock Loads (s1/s2—ACT 3 Only)
s1
s2
r1
r2
Clock Loads on
Dedicated
Array Clock
Clock Loads on
Dedicated
I/O Clock
Device Type
A1010B
routed_Clk1
routed_Clk2
Device Type
A1425A
41
n/a
n/a
134
168
168
75
160
432
697
100
168
228
A1020B
69
A1460A
A1240A
134
168
168
75
A14100A
A1280A
A1280XL
A1425A
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data values input to the
circuit. The guidelines in the table below are meant to
represent worst-case scenarios so that they can be generally
used to predict the upper limits of power dissipation.
A1460A
165
195
178
230
165
195
178
230
A14100A
A32100DX
A32200DX
Type
ACT 3
3200DX/ACT 2/1200XL
ACT 1
Logic modules (m)
Input switching (n)
Outputs switching (p)
80% of modules
80% of modules
# inputs/4
90% of modules
# inputs/4
# inputs/4
#outputs/4
#outputs/4
#outputs/4
First routed array clock loads (q1)
40% of sequential
modules
40% of sequential
modules
40% of modules
Second routed array clock loads (q2)
40% of sequential
modules
40% of sequential
modules
n/a
Load capacitance (CL)
35 pF
F/10
F/5
F/10
F/2
F/2
F
35 pF
F/10
F/5
35 pF
F/10
F/5
Average logic module switching rate (fm)
Average input switching rate (fn)
Average output switching rate (fp)
Average first routed array clock rate (fq1)
Average second routed array clock rate (fq2
F/10
F
F/10
F
)
F/2
n/a
Average dedicated array clock rate (fs1
)
n/a
n/a
Average dedicated I/O clock rate (fs2)
F
n/a
n/a
13
3200DX Timing Model (Logic Functions using Array Clocks)*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
I/O Module
tINPY = 1.9 ns
t
IRD1 = 2.2 ns
Combinatorial
Module
tDLH = 6.3 ns
tRD1 = 1.3 ns
tRD2 = 1.9 ns
tRD4 = 3.3 ns
D
G
Q
tPD = 3.1 ns
Decode
Module
tINH = 0.0 ns
INSU = 0.7 ns
tRDD = 0.5 ns
t
t
INGO = 4.0 ns
tPDD = 3.3 ns
I/O Module
tDLH = 6.3 ns
Sequential
Logic Module
tRD1 = 1.3 ns
Combin-
D
D
G
Q
Q
atorial
Logic
included
in tSUD
tENHZ = 11.5 ns
tLH = 0.0 ns
tLSU = 0.4 ns
tGHL= 12.4 ns
tCO = 3.1 ns
t
SU = 0.5 ns
tHD = 0.0 ns
ARRAY
CLOCKS
tCKH = 6.5 ns
FMAX = 140 MHz
*Values shown for A32100DX–1 at worst-case military conditions.
14
HiRel FPGAs
3200DX Timing Model (Logic Functions using Quadrant Clocks)*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
I/O Module
tINPY = 1.9 ns
t
IRD1 = 2.2 ns
Combinatorial
Module
tDLH = 6.3 ns
tRD1 = 1.3 ns
tRD2 = 1.9 ns
tRD4 = 3.3 ns
D
G
Q
tPD = 3.1 ns
Decode
Module
tINH = 0.0 ns
INSU = 0.7 ns
tRDD = 0.5 ns
t
t
INGO = 4.0 ns
tPDD = 3.3 ns
I/O Module
tDLH = 6.3 ns
Sequential
Logic Module
tRD1 = 1.3 ns
Combin-
D
D
G
Q
Q
atorial
Logic
included
in tSUD
tENHZ = 11.5 ns
tLH = 0.0 ns
tLSU = 0.4 ns
tGHL= 12.4 ns
tCO = 3.1 ns
t
SU = 0.5 ns
tHD = 0.0 ns
QUADRANT
CLOCKS
t
CKH = 12 ns**
FMAX = 100 MHz
* Values shown for A32100DX–1 at worst-case military conditions.
** Load dependent.
15
3200DX Timing Model (SRAM Functions)*
Input Delays
I/O Module
tINPY = 1.9 ns
t
IRD1 = 2.2 ns
D
G
Q
Predicted
Routing
Delays
I/O Module
t
INSU = 0.7 ns
tINH = 0.0 ns
INGO = 4.0 ns
tDLH = 6.3 ns
RD [7:0]
RDAD [5:0]
REN
t
WD [7:0]
tRD1 = 1.3 ns
WRAD [5:0]
BLKEN
D
G
Q
WEN
WCLK
RCLK
tADSU = 2.1 ns
tADH = 0.0 ns
tRENSU = 0.8 ns
tRCO = 4.4 ns
tADSU = 2.1 ns
tGHL = 12.4 ns
tLSU = 0.4 ns
tLH = 0.0 ns
t
ADH = 0.0 ns
tWENSU = 3.5 ns
BENS = 3.6 ns
ARRAY
CLOCKS
t
FMAX = 140 MHz
*Values shown for A32100DX–1 at worst-case military conditions.
16
HiRel FPGAs
1200XL Timing Model*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
Combinatorial
Logic Module
I/O Module
tINYL = 1.7 ns
t
IRD2 = 5.2 ns†
tDLH = 6.6 ns
tRD1 = 1.7 ns
tRD2 = 2.5 ns
D
G
Q
tPD = 3.7 ns
t
RD4 = 3.7 ns
tRD8 = 7.0 ns
I/O Module
tDLH = 6.6 ns
Sequential
Logic Module
tINH = 0.0 ns
INSU = 0.4 ns
t
t
INGL = 3.7 ns
Combin-
D
D
G
Q
Q
atorial
Logic
included
in tSUD
tRD1 = 1.7 ns
t
ENHZ = 7.5 ns
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 5.9 ns
tCO = 3.7 ns
t
SU = 0.4 ns
ARRAY
CLOCKS
tHD = 0.0 ns
tCKH = 7.1 ns
FMAX = 110 MHz
FO = 256
tLCO = 10.7 ns (64 loads, pad-pad)
*Values shown for A1280XL–1 at worst-case military conditions.
† Input module predicted routing delay.
17
Parameter Measurement
Output Buffer Delays
E
D
PAD
PAD To AC test loads (shown below)
TRIBUFF
VCC
VCC
VCC
In
GND
1.5V
50%
VOH
E
GND
E
50%
GND
90%
50%
50%
VCC
50%
VOH
50%
1.5V
VOL
PAD
VOL
PAD
PAD
1.5V
10%
1.5V
GND
tDLH
tDHL
tENZL
tENLZ
tENZH
tENHZ
AC Test Load
Load 1
Load 2
(Used to measure propagation delay)
(Used to measure rising/falling edges)
VCC
GND
To the output under test
50 pF
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
To the output under test
50 pF
Input Buffer Delays
Combinatorial Macro Delays
S
A
B
Y
Y
PAD
PAD
INBUF
VCC
GND
50%
S, A, or B
50% 50%
VCC
3V
Y
50%
PAD
0V
1.5V
VCC
1.5V
GND
tPLH
tPHL
50%
Y
GND
50%
VCC
50%
Y
GND
50%
tPHL
tINYH
tINYL
tPLH
18
HiRel FPGAs
Sequential Timing Characteristics
Flip-Flops and Latches (ACT 3)
D
E
Y
CLK
CLR
(Positive edge triggered)
tHD
D1
tA
tWCLKA
tSUD
G, CLK
tSUENA
tHENA
E
tCO
Q
tCLR
CLR
tWASYN
Note:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
19
Sequential Timing Characteristics (continued)
Flip-Flops and Latches (1200XL/3200DX, ACT 2, and ACT 1)
D
E
CLK
Y
PRE
CLR
(Positive edge triggered)
tHD
D1
tA
tWCLKA
tSUD
G, CLK
tSUENA
tHENA
E
tCO
Q
tRS
PRE, CLR
tWASYN
Note:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
20
HiRel FPGAs
Sequential Timing Characteristics (continued)
Input Buffer Latches (ACT 2 and 1200XL/3200DX)
PAD
IBDL
G
PAD
CLK
CLKBUF
PAD
G
tINH
tINSU
tHEXT
CLK
tSUEXT
Output Buffer Latches (ACT 2 and 1200XL/3200DX)
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
21
Decode Module Timing
A
B
C
D
E
F
Y
H
G
VCC
A–G, H
50%
VCC
Y
tPHL
tPLH
SRAM Timing Characteristics
Read Port
Write Port
WRAD [5:0]
BLKEN
WEN
RDAD [5:0]
LEW
RAM Array
32x8 or 64x4
(256 bits)
REN
WCLK
RCLK
WD [7:0]
RD [7:0]
22
HiRel FPGAs
Dual-Port SRAM Timing Waveforms
3200DX SRAM Write Operation
tRCKHL
tRCKHL
WCLK
tADSU
tADH
WD[7:0]
WRAD[5:0]
Valid
tWENSU
tWENH
WEN
tBENSU
Valid
tBENH
BLKEN
Note: Identical timing for falling-edge clock.
3200DX SRAM Synchronous Read Operation
tCKHL
tRCKHL
RCLK
tRENSU
tRENH
REN
tADSU
Valid
tADH
RDAD[5:0]
tRCO
tDOH
Old Data
New Data
RD[7:0]
Note: Identical timing for falling-edge clock.
23
3200DX SRAM Asynchronous Read Operation—Type 1
(Read Address Controlled)
tRDADV
RDAD[5:0]
RD[7:0]
ADDR1
tDOH
Data 1
ADDR2
tRPD
Data 2
3200DX SRAM Asynchronous Read Operation—Type 2
(Write Address Controlled)
WEN
tWENSU
tWENH
WD[7:0]
WRAD[5:0]
BLKEN
Valid
tADH
tADSU
WCLK
tRPD
tDOH
Old Data
New Data
RD[7:0]
24
HiRel FPGAs
ACT 1 Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
tPD2
tCO
tGO
tRS
Single Module
4.7
10.8
4.7
5.5
ns
ns
ns
ns
ns
Dual Module Macros
Sequential Clk to Q
Latch G to Q
12.7
5.5
4.7
5.5
Flip-Flop (Latch) Reset to Q
4.7
5.5
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.5
2.3
1.7
2.7
ns
ns
ns
ns
ns
3.4
4.0
5.0
5.9
10.6
12.5
Logic Module Sequential Timing 2
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
8.8
0.0
8.8
0.0
10.4
0.0
ns
ns
ns
ns
tHD
tSUENA
tHENA
tWCLKA
10.4
0.0
Flip-Flop (Latch) Clock Active Pulse
Width
10.9
12.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
10.9
23.2
12.9
27.3
ns
ns
tA
Flip-Flop Clock Input Period
fMAX
Flip-Flop (Latch) Clock
Frequency
44
37
MHz
Input Module Propagation Delays
tINYH
tINYL
Pad to Y High
4.9
4.9
5.8
5.8
ns
ns
Pad to Y Low
Input Module Predicted Routing Delays1, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.5
2.3
1.7
2.7
ns
ns
ns
ns
ns
3.4
4.0
5.0
5.9
10.6
12.5
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
2. Setup times assume fanout of 3. Further derating information can be obtained from the DirectTime Analyzer utility.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
25
ACT 1 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
Input Low to High
FO = 16
FO = 128
7.8
8.9
9.2
10.5
ns
ns
Input High to Low
FO = 16
FO = 128
10.3
11.2
12.1
13.2
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO = 16
FO = 128
10.4
10.9
12.2
12.9
ns
FO = 16
FO = 128
10.4
10.9
12.2
12.9
ns
FO = 16
FO = 128
1.9
2.9
2.2
3.4
ns
Minimum Period
FO = 16
FO = 128
21.7
23.2
25.6
27.3
ns
fMAX
Maximum Frequency
FO = 16
FO = 128
46
44
40
37
MHz
TTL Output Module Timing1
tDLH
Data to Pad High
12.1
13.8
12.0
14.6
16.0
14.5
0.09
0.12
14.2
16.3
14.1
17.1
18.8
17.0
0.11
0.15
ns
ns
tDHL
Data to Pad Low
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
Delta Low to High
Delta High to Low
ns
ns
ns
ns
ns/pF
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
15.1
11.5
12.0
14.6
16.0
14.5
0.16
0.09
17.7
13.6
14.1
17.1
18.8
17.0
0.18
0.11
ns
ns
tDHL
Data to Pad Low
tENZH
tENZL
tENHZ
tENLZ
dTLH
dTHL
Notes:
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
Delta Low to High
Delta High to Low
ns
ns
ns
ns
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
26
HiRel FPGAs
A1240A Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
5.2
5.2
5.2
5.2
6.1
ns
ns
ns
ns
Sequential Clk to Q
Latch G to Q
6.1
6.1
6.1
Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.9
2.4
3.1
4.3
6.6
2.2
2.8
3.7
5.0
7.7
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
0.5
0.0
1.3
0.0
0.5
0.0
1.3
0.0
ns
ns
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
7.4
8.1
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
7.4
14.8
2.5
8.1
18.6
2.5
ns
ns
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
tINH
ns
tINSU
tOUTH
tOUTSU
fMAX
Notes:
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock Frequency
–3.5
0.0
–3.5
0.0
ns
ns
0.5
0.5
ns
63
54
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
27
A1240A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
4.0
3.6
6.9
6.6
4.7
4.3
8.1
7.7
ns
ns
ns
ns
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
5.8
6.7
6.9
7.8
ns
ns
ns
ns
ns
7.5
8.8
8.2
9.7
10.9
12.9
Global Clock Network
tCKH Input Low to High
FO = 32
FO = 256
13.3
16.3
15.7
19.2
ns
ns
tCKL
Input High to Low
FO = 32
FO = 256
13.3
16.5
15.7
19.5
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO = 32
FO = 256
5.7
6.0
6.7
7.1
ns
FO = 32
FO = 256
5.7
6.0
6.7
7.1
ns
FO = 32
FO = 256
0.6
3.1
0.6
3.1
ns
Input Latch External Setup
Input Latch External Hold
Minimum Period
FO = 32
FO = 256
0.0
0.0
0.0
0.0
ns
FO = 32
FO = 256
8.6
13.8
8.6
13.8
ns
FO = 32
FO = 256
11.5
12.2
13.5
14.3
ns
fMAX
Note:
Maximum Frequency
FO = 32
FO = 256
87
82
74
70
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
28
HiRel FPGAs
A1240A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
Min. Max.
‘Std’ Speed
Min. Max.
Parameter
Description
Units
TTL Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
11.0
13.9
12.3
16.1
9.8
13.0
ns
ns
tDHL
16.4
14.4
19.0
11.5
13.6
14.6
18.2
0.11
0.20
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
ns
ns
11.5
12.4
15.5
0.09
0.17
ns
ns
tGHL
G to Pad Low
ns
dTLH
dTHL
Delta Low to High
Delta High to Low
ns/pF
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
14.0
11.7
12.3
16.1
9.8
16.5
13.7
14.4
19.0
11.5
13.6
14.6
18.2
0.20
0.15
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
ns
ns
11.5
12.4
15.5
0.17
0.12
ns
ns
tGHL
G to Pad Low
ns
dTLH
dTHL
Notes:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
29
A1280A Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
5.2
5.2
5.2
5.2
6.1
6.1
6.1
6.1
ns
ns
ns
ns
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.4
3.4
4.2
5.1
9.2
2.8
4.0
ns
ns
ns
ns
ns
4.9
6.0
10.8
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
0.5
0.0
1.3
0.0
0.5
0.0
1.3
0.0
ns
ns
ns
ns
tHD
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
7.4
8.6
ns
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
7.4
16.4
2.5
8.6
22.1
2.5
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Notes:
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock Frequency
–3.5
0.0
–3.5
0.0
ns
ns
0.5
0.5
ns
60
41
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
30
HiRel FPGAs
A1280A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
4.0
3.6
6.9
6.6
4.7
ns
ns
ns
ns
4.3
8.1
7.7
Input Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
6.2
7.2
7.3
8.4
ns
ns
ns
ns
ns
7.7
9.1
8.9
10.5
15.2
12.9
Global Clock Network
tCKH Input Low to High
FO = 32
FO = 384
13.3
17.9
15.7
21.1
ns
ns
tCKL
Input High to Low
FO = 32
FO = 384
13.3
18.2
15.7
21.4
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
FO = 32
FO = 384
0.6
3.1
0.6
3.1
ns
Input Latch External Setup
Input Latch External Hold
Minimum Period
FO = 32
FO = 384
0.0
0.0
0.0
0.0
ns
FO = 32
FO = 384
8.6
13.8
8.6
13.8
ns
FO = 32
FO = 384
13.7
16.0
16.2
18.9
ns
fMAX
Note:
Maximum Frequency
FO = 32
FO = 384
73
63
62
53
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
31
A1280A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
Min. Max.
‘Std’ Speed
Min. Max.
Parameter
Description
Units
TTL Output Module Timing1
tDLH
Data to Pad High
11.0
13.9
12.3
16.1
9.8
13.0
16.4
14.4
19.0
11.5
13.6
14.6
18.2
0.11
0.20
ns
ns
tDHL
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
ns
ns
11.5
12.4
15.5
0.09
0.17
ns
ns
tGHL
G to Pad Low
ns
dTLH
dTHL
Delta Low to High
ns/pF
ns/pF
Delta High to Low
CMOS Output Module Timing1
tDLH
Data to Pad High
14.0
11.7
12.3
16.1
9.8
16.5
13.7
14.4
19.0
11.5
13.6
14.6
18.2
0.20
0.15
ns
ns
tDHL
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
ns
ns
11.5
12.4
15.5
0.17
0.12
ns
ns
tGHL
G to Pad Low
ns
dTLH
dTHL
Notes:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
32
HiRel FPGAs
A1280XL Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
tCO
tGO
tRS
Single Module
3.7
3.7
3.7
3.7
4.3
ns
ns
ns
ns
Sequential Clk to Q
Latch G to Q
4.3
4.3
4.3
Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.7
2.5
3.1
3.7
7.0
2.1
3.0
3.6
4.3
8.3
ns
ns
ns
ns
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
0.4
0.0
1.1
0.0
0.5
0.0
1.2
0.0
ns
ns
ns
ns
tHD
tSUENA
tHENA
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
5.3
6.1
ns
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
5.3
10.7
0.0
6.1
12.3
0.0
tA
Flip-Flop Clock Input Period
Input Buffer Latch Hold
ns
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Notes:
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock Frequency
0.4
0.4
ns
0.0
0.0
ns
0.4
0.4
ns
90
75
MHz
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
33
A1280XL Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
tINYL
tINGH
tINGL
Pad to Y High
Pad to Y Low
G to Y High
G to Y Low
1.5
1.7
2.8
3.7
1.7
2.1
3.3
4.3
ns
ns
ns
ns
Input Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
4.6
5.2
5.5
6.4
9.2
5.3
6.1
ns
ns
ns
ns
ns
6.5
7.5
10.8
Global Clock Network
tCKH Input Low to High
FO = 32
FO = 384
7.1
8.0
8.4
9.5
ns
ns
tCKL
Input High to Low
FO = 32
FO = 384
7.0
8.0
8.3
9.5
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO = 32
FO = 384
4.3
4.8
5.3
5.7
ns
FO = 32
FO = 384
4.3
4.8
5.3
5.7
ns
FO = 32
FO = 384
1.1
1.1
1.2
1.2
ns
Input Latch External Setup
Input Latch External Hold
Minimum Period
FO = 32
FO = 384
0.0
0.0
0.0
0.0
ns
FO = 32
FO = 384
3.6
4.6
4.2
5.3
ns
FO = 32
FO = 384
9.1
9.8
10.7
11.8
ns
fMAX
Note:
Maximum Frequency
FO = 32
FO = 384
110
100
90
85
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
34
HiRel FPGAs
A1280XL Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
Min. Max.
‘Std’ Speed
Min. Max.
Parameter
Description
Units
TTL Output Module Timing1
tDLH
Data to Pad High
5.3
5.7
6.2
ns
ns
tDHL
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
6.6
6.2
tENZH
tENZL
tENHZ
tENLZ
tGLH
5.3
ns
5.8
6.8
ns
7.5
8.9
ns
7.5
8.9
ns
5.9
6.9
ns
tGHL
G to Pad Low
6.6
7.8
ns
dTLH
dTHL
Delta Low to High
0.05
0.05
0.06
0.09
ns/pF
ns/pF
Delta High to Low
CMOS Output Module Timing1
tDLH
Data to Pad High
6.6
4.7
7.9
5.5
ns
ns
tDHL
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
tENZH
tENZL
tENHZ
tENLZ
tGLH
5.3
6.2
ns
5.8
6.8
ns
7.5
8.9
ns
7.5
8.9
ns
5.9
6.9
ns
tGHL
G to Pad Low
6.6
7.8
ns
dTLH
dTHL
Notes:
Delta Low to High
Delta High to Low
0.07
0.06
0.09
0.09
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
35
A1425A Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
Sequential Clock to Q
Asynchronous Clear to Q
3.0
3.0
3.0
3.5
3.5
3.5
ns
ns
ns
tCO
tCLR
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
0.9
0.0
0.9
0.0
3.8
3.8
7.9
1.0
0.0
1.0
0.0
4.4
4.4
9.3
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
tSUENA
tHENA
tWASYN
tWCLKA
tA
ns
ns
ns
ns
ns
fMAX
125
100
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
7.0
7.0
7.0
7.0
4.9
8.2
8.2
8.2
8.2
ns
ns
ns
ns
ns
tICKY
Input Reg IOCLK Pad to Y
Output Reg IOCLK Pad to Y
Input Asynchronous Clear to Y
Output Asynchronous Clear to Y
tOCKY
tICLRY
tOCLRY
Input Module Predicted Routing Delays1, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
36
HiRel FPGAs
A1425A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
I/O Module Sequential Timing
tINH
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
2.1
0.0
8.7
1.1
1.1
0.5
2.0
0.0
2.4
0.0
10.0
1.2
1.2
0.6
2.4
ns
ns
ns
ns
ns
ns
ns
ns
tINSU
Input F-F Data Setup
(w.r.t. IOCLK Pad)
tIDEH
Input Data Enable Hold
(w.r.t. IOCLK Pad)
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
Input Data Enable Setup
(w.r.t. IOCLK Pad)
Output F-F Data Hold
(w.r.t. IOCLK Pad)
Output F-F Data Setup
(w.r.t. IOCLK Pad)
Output Data Enable Hold
(w.r.t. IOCLK Pad)
Output Data Enable Setup
(w.r.t. IOCLK Pad)
TTL Output Module Timing1
tDHS
Data to Pad, High Slew
7.5
11.9
6.0
8.9
ns
ns
tDLS
Data to Pad, Low Slew
14.0
7.0
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
10.9
9.9
12.8
11.6
11.6
11.6
17.4
0.04
0.08
0.06
0.08
ns
ns
9.9
ns
10.5
15.7
0.04
0.07
0.05
0.07
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
Note:
ns/pF
ns/pF
ns/pF
ns/pF
1. Delays based on 35 pF loading.
37
A1425A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
20.3
9.1
ns
ns
tDLS
Data to Pad, Low Slew
17.3
7.7
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
13.1
9.9
15.5
11.6
11.6
13.7
20.1
0.07
0.13
0.05
0.06
ns
ns
10.5
12.5
18.1
0.06
0.11
0.04
0.05
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
ns/pF
ns/pF
ns/pF
ns/pF
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
3.0
3.5
ns
ns
tIOPWH
tIOPWL
tIOSAPW
tIOCKSW
tIOP
Minimum Pulse Width High
Minimum Pulse Width Low
Minimum Asynchronous Pulse Width
Maximum Skew
3.9
3.9
3.9
4.4
4.4
4.4
ns
ns
0.5
0.5
ns
Minimum Period
7.9
9.3
ns
fIOMAX
Maximum Frequency
125
100
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input Low to High
(Pad to S-Module Input)
4.6
4.6
5.3
5.3
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
3.9
3.9
4.4
4.4
ns
0.4
0.4
ns
Minimum Period
7.9
9.3
ns
fHMAX
Notes:
Maximum Frequency
125
100
MHz
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
38
HiRel FPGAs
A1425A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRP
Input Low to High (FO=64)
5.5
6.0
6.4
7.0
ns
ns
Input High to Low (FO=64)
Min. Pulse Width High (FO=64)
Min. Pulse Width Low (FO=64)
Maximum Skew (FO=128)
Minimum Period (FO=64)
4.9
4.9
5.7
5.7
ns
ns
1.1
1.2
85
ns
10.1
11.6
ns
fRMAX
Maximum Frequency (FO=64)
100
MHz
Clock-to-Clock Skews
tIOHCKSW
tIORCKSW
tHRCKSW
I/O Clock to H-Clock Skew
0.0
0.0
3.0
3.0
0.0
0.0
3.0
3.0
ns
ns
I/O Clock to R-Clock Skew
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
39
A1460A Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
Sequential Clock to Q
Asynchronous Clear to Q
3.0
3.0
3.0
3.5
3.5
3.5
ns
ns
ns
tCO
tCLR
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
0.9
0.0
0.9
0.0
4.8
4.8
9.9
1.0
0.0
1.0
0.0
5.6
5.6
11.6
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
tSUENA
tHENA
tWASYN
tWCLKA
tA
ns
ns
ns
ns
ns
fMAX
100
85
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
7.0
7.0
7.0
7.0
4.9
8.2
8.2
8.2
8.2
ns
ns
ns
ns
ns
tICKY
Input Reg IOCLK Pad to Y
Output Reg IOCLK Pad to Y
Input Asynchronous Clear to Y
Output Asynchronous Clear to Y
tOCKY
tICLRY
tOCLRY
Input Module Predicted Routing Delays2, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
40
HiRel FPGAs
A1460A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
I/O Module Sequential Timing
tINH
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
2.1
0.0
8.7
1.1
1.1
0.5
2.0
0.0
2.4
0.0
10.0
1.2
1.2
0.6
2.4
ns
ns
ns
ns
ns
ns
ns
ns
tINSU
Input F-F Data Setup
(w.r.t. IOCLK Pad)
tIDEH
Input Data Enable Hold
(w.r.t. IOCLK Pad)
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
Input Data Enable Setup
(w.r.t. IOCLK Pad)
Output F-F Data Hold
(w.r.t. IOCLK Pad)
Output F-F Data Setup
(w.r.t. IOCLK Pad)
Output Data Enable Hold
(w.r.t. IOCLK Pad)
Output Data Enable Setup
(w.r.t. IOCLK Pad)
TTL Output Module Timing1
tDHS
Data to Pad, High Slew
7.5
8.9
14.0
7.0
ns
ns
tDLS
Data to Pad, Low Slew
11.9
6.0
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
10.9
11.5
10.9
11.6
17.8
0.04
0.07
0.05
0.07
12.8
13.5
12.8
13.4
19.8
0.04
0.08
0.06
0.08
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
Note:
ns/pF
ns/pF
ns/pF
ns/pF
1. Delays based on 35 pF loading.
41
A1460A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
20.3
9.1
ns
ns
tDLS
Data to Pad, Low Slew
17.3
7.7
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
13.1
10.9
10.9
14.1
20.2
0.06
0.11
0.04
0.05
15.5
12.8
12.8
16.0
22.4
0.07
0.13
0.05
0.06
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
ns/pF
ns/pF
ns/pF
ns/pF
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
3.5
4.1
ns
ns
tIOPWH
tIOPWL
tIOSAPW
tIOCKSW
tIOP
Minimum Pulse Width High
Minimum Pulse Width Low
Minimum Asynchronous Pulse Width
Maximum Skew
4.8
4.8
3.9
5.7
5.7
4.4
ns
ns
0.9
1.0
85
ns
Minimum Period
9.9
11.6
ns
fIOMAX
Maximum Frequency
100
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input Low to High
(Pad to S-Module Input)
5.5
5.5
6.4
6.4
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
4.8
4.8
5.7
5.7
ns
0.9
1.0
85
ns
Minimum Period
9.9
11.6
ns
fHMAX
Notes:
Maximum Frequency
100
MHz
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
42
HiRel FPGAs
A1460A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRP
Input Low to High (FO=256)
9.0
9.0
10.5
10.5
ns
ns
Input High to Low (FO=256)
Min. Pulse Width High (FO=256)
Min. Pulse Width Low (FO=256)
Maximum Skew (FO=128)
6.3
6.3
7.1
7.1
ns
ns
1.9
75
2.1
65
ns
Minimum Period (FO=256)
12.9
14.5
ns
fRMAX
Maximum Frequency (FO=256)
MHz
Clock-to-Clock Skews
tIOHCKSW
tIORCKSW
tHRCKSW
I/O Clock to H-Clock Skew
0.0
0.0
3.0
5.0
0.0
0.0
3.0
5.0
ns
ns
I/O Clock to R-Clock Skew
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
43
A14100A Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
Sequential Clock to Q
Asynchronous Clear to Q
3.0
3.0
3.0
3.5
3.5
3.5
ns
ns
ns
tCO
tCLR
Logic Module Predicted Routing Delays2
tRD1
tRD2
tRD3
tRD4
tRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
1.0
0.6
1.0
0.6
4.8
4.8
9.9
1.0
0.6
1.0
0.6
5.6
5.6
11.6
ns
ns
tHD
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
tSUENA
tHENA
tWASYN
tWCLKA
tA
ns
ns
ns
ns
ns
fMAX
100
85
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
7.0
7.0
7.0
7.0
4.9
8.2
8.2
8.2
8.2
ns
ns
ns
ns
ns
tICKY
Input Reg IOCLK Pad to Y
Output Reg IOCLK Pad to Y
Input Asynchronous Clear to Y
Output Asynchronous Clear to Y
tOCKY
tICLRY
tOCLRY
Input Module Predicted Routing Delays2, 3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.3
1.9
2.1
2.6
4.2
1.5
2.1
2.5
2.9
4.9
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
44
HiRel FPGAs
A14100A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
I/O Module Sequential Timing
tINH
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
2.1
0.0
8.7
1.2
1.2
0.6
2.4
0.0
2.4
0.0
10.0
1.2
1.2
0.6
2.4
ns
ns
ns
ns
ns
ns
ns
ns
tINSU
Input F-F Data Setup
(w.r.t. IOCLK Pad)
tIDEH
Input Data Enable Hold
(w.r.t. IOCLK Pad)
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
Input Data Enable Setup
(w.r.t. IOCLK Pad)
Output F-F Data Hold
(w.r.t. IOCLK Pad)
Output F-F Data Setup
(w.r.t. IOCLK Pad)
Output Data Enable Hold
(w.r.t. IOCLK Pad)
Output Data Enable Setup
(w.r.t. IOCLK Pad)
TTL Output Module Timing1
tDHS
Data to Pad, High Slew
7.5
8.9
14.0
7.0
ns
ns
tDLS
Data to Pad, Low Slew
11.9
6.0
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
10.9
11.9
10.9
12.2
17.8
0.04
0.07
0.05
0.07
12.8
14.0
12.8
14.0
17.8
0.04
0.08
0.06
0.08
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
Note:
ns/pF
ns/pF
ns/pF
ns/pF
1. Delays based on 35 pF loading.
45
A14100A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
20.3
9.1
ns
ns
tDLS
Data to Pad, Low Slew
17.3
7.7
tENZHS
tENZLS
tENHSZ
tENLSZ
tCKHS
tCKLS
Enable to Pad, Z to H/L, High Slew
Enable to Pad, Z to H/L, Low Slew
Enable to Pad, H/L to Z, High Slew
Enable to Pad, H/L to Z, Low Slew
IOCLK Pad to Pad H/L, High Slew
IOCLK Pad to Pad H/L, Low Slew
Delta Low to High, High Slew
Delta Low to High, Low Slew
Delta High to Low, High Slew
Delta High to Low, Low Slew
ns
13.1
11.6
10.9
14.4
20.2
0.06
0.11
0.04
0.05
15.5
14.0
12.8
16.0
22.4
0.07
0.13
0.05
0.06
ns
ns
ns
ns
ns
dTLHHS
dTLHLS
dTHLHS
dTHLLS
ns/pF
ns/pF
ns/pF
ns/pF
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
3.5
4.1
ns
ns
tIOPWH
tIOPWL
tIOSAPW
tIOCKSW
tIOP
Minimum Pulse Width High
Minimum Pulse Width Low
Minimum Asynchronous Pulse Width
Maximum Skew
4.8
4.8
3.9
5.7
5.7
4.4
ns
ns
0.9
1.0
85
ns
Minimum Period
9.9
11.6
ns
fIOMAX
Maximum Frequency
100
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input Low to High
(Pad to S-Module Input)
5.5
5.5
6.4
6.4
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
4.8
4.8
5.7
5.7
ns
0.9
1.0
85
ns
Minimum Period
9.9
11.6
ns
fHMAX
Notes:
Maximum Frequency
100
MHz
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
46
HiRel FPGAs
A14100A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRP
Input Low to High (FO=256)
9.0
9.0
10.5
10.5
ns
ns
Input High to Low (FO=256)
Min. Pulse Width High (FO=256)
Min. Pulse Width Low (FO=256)
Maximum Skew (FO=128)
6.3
6.3
7.1
7.1
ns
ns
1.9
75
2.1
65
ns
Minimum Period (FO=256)
12.9
14.5
ns
fRMAX
Maximum Frequency (FO=256)
MHz
Clock-to-Clock Skews
tIOHCKSW
tIORCKSW
tHRCKSW
I/O Clock to H-Clock Skew
0.0
0.0
3.5
5.0
0.0
0.0
3.5
5.0
ns
ns
I/O Clock to R-Clock Skew
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
47
A32100DX Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Combinatorial Functions
tPD
Internal Array Module Delay
Internal Decode Module Delay
3.1
3.3
4.1
4.3
ns
ns
tPDD
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
1.3
1.9
2.6
3.3
0.6
0.5
1.8
2.6
3.4
4.3
0.8
0.6
ns
ns
ns
ns
ns
ns
Logic Module Sequential Timing
tCO
Flip-Flop Clock-to-Output
3.1
3.1
4.1
4.1
ns
ns
ns
ns
ns
ns
ns
tGO
Latch Gate-to-Output
tSU
Flip-Flop (Latch) Setup Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
0.5
0.0
0.6
0.0
tH
tRO
3.1
4.1
tSUENA
tHENA
tWCLKA
0.9
0.0
1.2
0.0
Flip-Flop (Latch) Clock Active Pulse
Width
4.3
5.6
5.8
7.5
ns
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
48
HiRel FPGAs
A32100DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
’–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
8.8
8.8
4.4
11.8
11.8
5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tRCKHL
tRCO
tADSU
tADH
Clock High/Low Time
Data Valid After Clock High/Low
Address/Data Setup Time
Address/Data Hold Time
Read Enable Setup
Read Enable Hold
4.4
5.9
2.1
0.0
0.8
4.4
3.5
0.0
3.6
0.0
2.8
0.0
1.1
5.9
4.7
0.0
4.8
0.0
tRENSU
tRENH
tWENSU
tWENH
tBENS
tBENH
Write Enable Setup
Write Enable Hold
Block Enable Setup
Block Enable Hold
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
Read Address Valid
10.6
14.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRDADV
tADSU
tADH
11.5
2.1
0.0
0.8
4.4
3.5
0.0
15.3
2.8
0.0
1.1
5.9
4.7
0.0
Address/Data Setup Time
Address/Data Hold Time
Read Enable Setup to Address Valid
Read Enable Hold
tRENSUA
tRENHA
tWENSU
tWENH
tDOH
Write Enable Setup
Write Enable Hold
Data Out Hold Time
1.6
2.1
49
A32100DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad to Y
Input Latch Gate-to-Output
Input Latch Hold
1.9
4.0
2.6
5.3
ns
ns
ns
ns
ns
0.0
0.7
6.1
0.0
0.9
8.1
tINSU
tILA
Input Latch Setup
Latch Active Pulse Width
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.2
2.8
3.5
3.5
5.6
2.9
3.8
4.7
4.7
7.5
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input Low to High
FO=32
FO=635
6.5
7.9
8.7
10.6
ns
ns
tCKL
Input High to Low
FO=32
FO=635
6.6
8.8
8.8
11.8
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO=32
FO=635
4.1
4.6
5.5
6.1
ns
ns
FO=32
FO=635
4.1
4.6
5.5
6.1
ns
ns
FO=32
FO=635
1.8
1.8
2.4
2.4
ns
ns
Input Latch External Setup
Input Latch External Hold
Minimum Period (1/fmax)
Maximum Datapath Frequency
FO=32
FO=635
0.0
0.0
0.0
0.0
ns
ns
FO=32
FO=635
3.0
3.8
4.0
5.1
ns
ns
FO=32
FO=635
7.1
7.9
9.5
10.5
ns
ns
fHMAX
Note:
FO=32
FO=635
140
126
105
95
MHz
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
50
HiRel FPGAs
A32100DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data to Pad High
5.1
6.3
6.8
8.3
ns
ns
Data to Pad Low
Enable Pad Z to High
6.6
8.8
ns
Enable Pad Z to Low
7.1
9.4
ns
Enable Pad High to Z
11.5
11.5
11.5
12.4
15.3
15.3
15.3
16.6
ns
Enable Pad Low to Z
ns
G to Pad High
ns
G to Pad Low
ns
I/O Latch Output Setup
I/O Latch Output Hold
0.4
0.0
0.5
0.0
ns
tLH
ns
tLCO
tACO
dTLH
dTHL
tWDO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide Decode Output
11.5
16.3
0.04
0.06
0.05
15.4
21.7
0.06
0.08
0.07
ns
ns
ns/pF
ns/pF
ns
CMOS Output Module Timing1
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data to Pad High
6.3
5.1
8.3
6.8
ns
ns
Data to Pad Low
Enable Pad Z to High
6.6
8.8
ns
Enable Pad Z to Low
7.1
9.4
ns
Enable Pad High to Z
11.5
11.5
11.5
12.4
15.3
15.3
15.3
16.6
ns
Enable Pad Low to Z
ns
G to Pad High
ns
G to Pad Low
ns
I/O Latch Setup
0.4
0.0
0.5
0.0
ns
tLH
I/O Latch Hold
ns
tLCO
tACO
dTLH
dTHL
tWDO
Notes:
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide Decode Output
13.7
19.2
0.06
0.05
0.05
18.2
25.6
0.08
0.07
0.07
ns
ns
ns/pF
ns/pF
ns
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
51
A32200DX Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Combinatorial Functions
tPD
Internal Array Module Delay
Internal Decode Module Delay
2.8
3.4
3.8
4.6
ns
ns
tPDD
Logic Module Predicted Routing Delays1
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
1.6
2.3
2.9
3.5
6.2
0.8
2.1
3.1
3.9
4.7
8.2
1.1
ns
ns
ns
ns
ns
ns
Logic Module Sequential Timing Characteristics
tCO
Flip-Flop Clock-to-Output
3.2
2.8
4.2
3.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
tGO
Latch Gate-to-Output
tSU
Flip-Flop (Latch) Setup Time
Flip-Flop (Latch) Hold Time
0.5
0.0
0.6
0.0
tH
tRO
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Asynchronous Pulse Width
3.2
4.2
tSUENA
tHENA
tWCLKA
tWASYN
Note:
0.9
0.0
4.3
5.7
1.2
0.0
5.8
7.6
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
52
HiRel FPGAs
A32200DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
8.8
8.8
4.4
11.8
11.8
5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tRCKHL
tRCO
tADSU
tADH
Clock High/Low Time
Data Valid After Clock High/Low
Address/Data Setup Time
Address/Data Hold Time
Read Enable Setup
Read Enable Hold
4.4
5.9
2.1
0.0
0.8
4.4
3.5
0.0
3.6
0.0
2.8
0.0
1.1
5.9
4.7
0.0
4.8
0.0
tRENSU
tRENH
tWENSU
tWENH
tBENS
tBENH
Write Enable Setup
Write Enable Hold
Block Enable Setup
Block Enable Hold
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
Read Address Valid
10.6
14.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRDADV
tADSU
tADH
11.5
2.1
0.0
0.8
4.4
3.5
0.0
15.3
2.8
0.0
1.1
5.9
4.7
0.0
Address/Data Setup Time
Address/Data Hold Time
Read Enable Setup to Address Valid
Read Enable Hold
tRENSUA
tRENHA
tWENSU
tWENH
tDOH
Write Enable Setup
Write Enable Hold
Data Out Hold Time
1.6
2.1
53
A32200DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINPY
tINGO
tINH
Input Data Pad to Y
Input Latch Gate-to-Output
Input Latch Hold
1.9
4.6
2.6
6.0
ns
ns
ns
ns
ns
0.0
0.7
6.1
0.0
0.9
8.1
tINSU
tILA
Input Latch Setup
Latch Active Pulse Width
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD5
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
2.6
3.4
4.6
5.4
7.0
3.5
4.6
6.1
7.2
9.3
ns
ns
ns
ns
ns
Global Clock Network
tCKH Input Low to High
FO=32
FO=635
7.3
8.5
9.8
11.3
ns
ns
tCKL
Input High to Low
FO=32
FO=635
7.2
9.3
9.6
12.5
ns
ns
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
FO=32
FO=635
3.2
3.9
4.3
5.2
ns
ns
FO=32
FO=635
3.2
3.9
4.3
5.2
ns
ns
FO=32
FO=635
1.8
1.8
2.4
2.4
ns
ns
Input Latch External Setup
Input Latch External Hold
Minimum Period (1/fmax)
Maximum Datapath Frequency
FO=32
FO=635
0.0
0.0
0.0
0.0
ns
ns
FO=32
FO=635
3.0
3.8
4.0
5.1
ns
ns
FO=32
FO=635
5.8
6.8
7.7
9.1
ns
ns
fHMAX
Note:
FO=32
FO=635
172
147
130
110
MHz
MHz
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
54
HiRel FPGAs
A32200DX Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data to Pad High
5.1
6.3
6.8
8.3
ns
ns
Data to Pad Low
Enable Pad Z to High
6.6
8.8
ns
Enable Pad Z to Low
7.1
9.5
ns
Enable Pad High to Z
11.5
11.5
11.5
12.3
15.3
15.3
15.3
16.5
ns
Enable Pad Low to Z
ns
G to Pad High
ns
G to Pad Low
ns
I/O Latch Output Setup
I/O Latch Output Hold
0.4
0.0
0.5
0.0
ns
tLH
ns
tLCO
tACO
dTLH
dTHL
tWDO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide Decode Output
11.5
16.3
0.04
0.06
0.05
15.4
21.7
0.06
0.08
0.07
ns
ns
ns/pF
ns/pF
ns
CMOS Output Module Timing1
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
tLSU
Data to Pad High
5.1
6.3
6.8
8.3
ns
ns
Data to Pad Low
Enable Pad Z to High
6.6
8.8
ns
Enable Pad Z to Low
7.1
9.5
ns
Enable Pad High to Z
11.5
11.5
11.5
12.3
15.3
15.3
15.3
16.5
ns
Enable Pad Low to Z
ns
G to Pad High
ns
G to Pad Low
ns
I/O Latch Setup
0.4
0.0
0.5
0.0
ns
tLH
I/O Latch Hold
ns
tLCO
tACO
dTLH
dTHL
tWDO
Notes:
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide Decode Output
13.7
19.2
0.06
0.05
0.05
18.2
25.6
0.08
0.07
0.07
ns
ns
ns/pF
ns/pF
ns
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
55
Pin Description
CLK
Clock (Input)
MODE
Mode (Input)
ACT 1 only. TTL Clock input for global clock distribution
network. The Clock input is buffered prior to clocking the
logic modules. This pin can also be used as an I/O.
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os. To provide debugging capability, the MODE
pin should be terminated to GND through a 10 kΩ resistor so
that the MODE pin can be pulled high when required.
CLKA
Clock A (Input)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for
global clock distribution networks. The Clock input is
buffered prior to clocking the logic modules. This pin can also
be used as an I/O.
NC
No Connection
This pin is not connected to circuitry within the device.
CLKB
Clock B (Input)
PRA, I/O
Probe A (Output)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for
global clock distribution networks. The Clock input is
buffered prior to clocking the logic modules. This pin can also
be used as an I/O.
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
LOW supply voltage.
PRB, I/O
Probe B (Output)
HCLK
Dedicated (Hard-wired) Array
Clock (Input)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
ACT 3 only. TTL Clock input for sequential modules. This
input is directly wired to each S-module and offers clock
speeds independent of the number of S-modules being driven.
This pin can also be used as an I/O.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. In the ACT 3 and
3200DX families, unused I/Os are automatically tri-stated.
With this configuration, the input buffer internal to the I/O
module is disabled. In the ACT 1, ACT 2 and 1200XL families,
unused I/Os are automatically configured as bi-directional
buffers where each buffer is configured as a LOW driver.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
VCC
5.0V Supply Voltage
IOCLK
Dedicated (Hard-wired) I/O
Clock (Input)
HIGH supply voltage.
QCLKA/B,C,D Quadrant Clock (Input/Output)
3200DX only. These four pins are the quadrant clock inputs.
When not used as a register control signal, these pins can
function as general purpose I/O.
ACT 3 only. TTL Clock input for I/O modules. This input is
directly wired to each I/O module and offers clock speeds
independent of the number of I/O modules being driven. This
pin can also be used as an I/O.
TCK
Test Clock
IOPCL
Dedicated (Hard-wired) I/O
Preset/Clear (Input)
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
JTAG pins are only available in the 3200DX device.
ACT 3 only. TTL input for I/O preset or clear. This global input
is directly wired to the preset and clear inputs of all I/O
registers. This pin functions as an I/O when no I/O preset or
clear macros are used.
56
HiRel FPGAs
TDI
Test Data In
Serial data input for JTAG instructions and data. Data is
shifted in on the rising edge of TCLK. This pin functions as an
I/O when the JTAG fuse is not programmed. JTAG pins are
only available in the 3200DX device.
TDO
Test Data Out
Serial data output for JTAG instructions and test data. This pin
functions as an I/O when the JTAG fuse is not programmed.
JTAG pins are only available in the 3200DX device.
TMS
Test Mode Select
Serial data input for JTAG test mode. Data is shifted in on the
rising edge of TCLK. This pin functions as an I/O when the
JTAG fuse is not programmed. JTAG pins are only available in
the 3200DX device.
57
Package Pin Assignments
84-Pin CPGA (Top View)
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
84-Pin
CPGA
K
L
K
L
1
2
3
4
5
6
7
8
9
10 11
Orientation Pin (C3)
58
HiRel FPGAs
84-Pin CPGA
A1010B
Function
A1020B
Function
A1010B
Function
A1020B
Function
Pin Number
Pin Number
A1
A2
I/O
I/O
I/O
I/O
F9
F10
F11
G1
G2
G3
G9
G10
G11
H1
H2
H10
H11
J1
CLK, I/O
GND
I/O
CLK, I/O
GND
I/O
A3
I/O
I/O
A4
I/O
I/O
I/O
I/O
A5
I/O
I/O
VCC
I/O
VCC
I/O
A6
I/O
I/O
A7
I/O
I/O
I/O
I/O
A8
I/O
I/O
GND
I/O
GND
I/O
A9
I/O
I/O
A10
A11
B1
I/O
I/O
I/O
I/O
PRA, I/O
NC
PRA, I/O
I/O
I/O
I/O
I/O
I/O
B2
NC
NC
I/O
I/O
B3
I/O
I/O
I/O
I/O
B4
I/O
I/O
J2
NC
I/O
I/O
B5
VCC
I/O
VCC
I/O
J5
I/O
B6
J6
I/O
I/O
B7
GND
I/O
GND
I/O
J7
I/O
I/O
B8
J10
J11
K1
NC
I/O
I/O
B9
I/O
I/O
I/O
B10
B11
C1
C2
C5
C6
C7
C10
C11
D1
D2
D10
D11
E1
PRB, I/O
SDI, I/O
NC
PRB, I/O
SDI, I/O
I/O
NC
VCC
I/O
I/O
K2
VCC
I/O
K3
NC
I/O
K4
I/O
I/O
I/O
I/O
K5
GND
I/O
GND
I/O
I/O
I/O
K6
I/O
I/O
K7
VCC
I/O
VCC
I/O
DCLK, I/O
NC
DCLK, I/O
I/O
K8
K9
I/O
I/O
I/O
I/O
K10
K11
L1
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
L2
I/O
I/O
I/O
L3
I/O
I/O
E2
GND
GND
VCC
VCC
MODE
VCC
I/O
GND
GND
VCC
VCC
MODE
VCC
I/O
L4
I/O
I/O
E3
L5
I/O
I/O
E9
L6
I/O
I/O
E10
E11
F1
L7
I/O
I/O
L8
I/O
I/O
L9
I/O
I/O
F2
L10
L11
I/O
I/O
F3
I/O
I/O
I/O
I/O
59
Package Pin Assignments (continued)
132-Pin CPGA (Top View)
1
2
3
4
5
6
7
8
9
10 11 12 13
A
B
C
D
E
F
A
B
C
D
E
F
132-Pin
CPGA
G
H
J
G
H
J
K
L
K
L
M
N
M
N
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
60
HiRel FPGAs
132-Pin CPGA
A1240A
Function
A1240A
Function
A1240A
Function
Pin Number
Pin Number
Pin Number
A1
A2
MODE
I/O
D8
D11
D12
D13
E1
I/O
I/O
K7
K8
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A3
I/O
I/O
K11
K12
K13
L1
A4
I/O
I/O
A5
I/O
I/O
A6
I/O
E2
I/O
A7
I/O
E3
GND
GND
GND
I/O
L2
A8
I/O
E11
E12
E13
F1
L3
A9
I/O
L4
A10
A11
A12
A13
B1
I/O
L5
I/O
I/O
L6
I/O
F2
I/O
L7
I/O
F3
I/O
L8
I/O
F4
GND
I/O
L9
B2
I/O
F10
F11
F12
F13
G1
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
B3
I/O
I/O
B4
I/O
I/O
B5
GND
CLKB, I/O
CLKA, I/O
PRA, I/O
GND
I/O
I/O
B6
I/O
B7
G2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
I/O
B8
G3
B9
G4
B10
B11
B12
B13
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D6
D7
G10
G11
G12
G13
H1
I/O
SDI, I/O
I/O
I/O
I/O
H2
I/O
DCLK, I/O
I/O
H3
I/O
H4
I/O
GND
PRB, I/O
VCC
I/O
H10
H11
H12
H13
J1
I/O
I/O
I/O
N2
GND
I/O
N3
GND
I/O
N4
J2
GND
GND
GND
I/O
N5
I/O
J3
N6
I/O
J11
J12
J13
K1
N7
I/O
N8
I/O
I/O
N9
I/O
I/O
N10
N11
N12
N13
I/O
K2
I/O
I/O
K3
I/O
VCC
K6
I/O
61
Package Pin Assignments (continued)
133-Pin CPGA (Top View)
1
2
3
4
5
6
7
8
9
10 11 12 13
A
B
C
D
E
F
A
B
C
D
E
F
133-Pin
CPGA
G
H
J
G
H
J
K
L
K
L
M
N
M
N
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
62
HiRel FPGAs
133-Pin CPGA
A1425A
Function
A1425A
Function
A1425A
Function
Pin Number
Pin Number
Pin Number
A1
A2
NC
GND
I/O
D8
D11
D12
D13
E1
I/O
I/O
K8
K11
K12
K13
L1
I/O
I/O
A3
I/O
I/O
A4
I/O
I/O
I/O
A5
I/O
I/O
I/O
A6
PRA, I/O
NC
E2
I/O
L2
I/O
A7
E3
MODE
VCC
I/O
L3
GND
I/O
A8
I/O
E11
E12
E13
F1
L4
A9
I/O
L5
I/O
A10
A11
A12
A13
B1
I/O
I/O
L6
PRB, I/O
GND
I/O
I/O
I/O
L7
I/O
F2
I/O
L8
NC
F3
I/O
L9
I/O
I/O
F4
I/O
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
IOPCL, I/O
GND
I/O
B2
VCC
I/O
F10
F11
F12
F13
G1
GND
I/O
B3
B4
I/O
I/O
I/O
B5
I/O
I/O
I/O
B6
CLKB, I/O
VCC
I/O
NC
VCC
GND
I/O
B7
G2
VCC
GND
I/O
B8
G3
B9
I/O
G4
I/O
B10
B11
B12
B13
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D4
D6
D7
I/O
G10
G11
G12
G13
H1
I/O
I/O
I/O
GND
VCC
NC
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
SDI, I/O
GND
I/O
H2
I/O
I/O
H3
I/O
VCC
I/O
H4
I/O
I/O
H10
H11
H12
H13
J1
I/O
NC
I/O
I/O
N2
I/O
GND
I/O
I/O
N3
I/O
I/O
N4
I/O
I/O
I/O
N5
I/O
IOCLK, I/O
GND
GND
I/O
J2
VCC
I/O
N6
I/O
J3
N7
NC
J11
J12
J13
K1
I/O
N8
I/O
VCC
I/O
N9
I/O
I/O
N10
N11
N12
N13
I/O
I/O
I/O
I/O
I/O
K2
I/O
GND
NC
DCLK, I/O
CLKA, I/O
I/O
K3
I/O
K6
I/O
K7
HCLKA, I/O
63
Package Pin Assignments (continued)
176-Pin CPGA (Top View)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
176-Pin
CPGA
K
L
K
L
M
N
P
R
M
N
P
R
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
.
64
HiRel FPGAs
176-Pin CPGA
A1280A
Function
A1280XL
Function
A1280A
Function
A1280XL
Function
Pin Number
Pin Number
A1
A2
I/O
I/O
I/O
I/O
C15
D1
I/O
I/O
I/O
I/O
A3
I/O
I/O
D2
I/O
I/O
A4
I/O
I/O
D3
I/O
I/O
A5
I/O
I/O
D4
GND
VCC
GND
PRB, I/O
VCC
I/O
GND
VCC
GND
PRB, I/O
VCC
I/O
A6
I/O
I/O
D5
A7
I/O
I/O
D6
A8
I/O
I/O
D7
A9
CLKA, I/O
I/O
CLKA, I/O
I/O
D8
A10
A11
A12
A13
A14
A15
B1
D9
I/O
I/O
D10
D11
D12
D13
D14
D15
E1
GND
VCC
GND
I/O
GND
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B2
I/O
I/O
I/O
I/O
B3
DCLK, I/O
I/O
DCLK, I/O
I/O
E2
I/O
I/O
B4
E3
I/O
I/O
B5
I/O
I/O
E4
GND
GND
I/O
GND
GND
I/O
B6
I/O
I/O
E12
E13
E14
E15
F1
B7
I/O
I/O
B8
CLKB, I/O
I/O
CLKB, I/O
I/O
I/O
I/O
B9
I/O
I/O
B10
B11
B12
B13
B14
B15
C1
I/O
I/O
I/O
I/O
I/O
I/O
F2
I/O
I/O
I/O
I/O
F3
I/O
I/O
I/O
I/O
F4
VCC
GND
I/O
VCC
GND
I/O
SDI, I/O
I/O
SDI, I/O
I/O
F12
F13
F14
F15
G1
I/O
I/O
I/O
I/O
C2
I/O
I/O
I/O
I/O
C3
MODE
I/O
MODE
I/O
I/O
I/O
C4
G2
I/O
I/O
C5
I/O
I/O
G3
I/O
I/O
C6
I/O
I/O
G4
GND
VCC
I/O
GND
VCC
I/O
C7
I/O
I/O
G12
G13
G14
G15
H1
C8
GND
PRA, I/O
I/O
GND
PRA, I/O
I/O
C9
I/O
I/O
C10
C11
C12
C13
C14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H2
VCC
VCC
GND
VCC
VCC
GND
I/O
I/O
H3
I/O
I/O
H4
65
176-Pin CPGA (Continued)
A1280A
Function
A1280XL
Function
A1280A
Function
A1280XL
Function
Pin Number
Pin Number
H12
H13
H14
H15
J1
GND
VCC
VCC
I/O
GND
VCC
VCC
I/O
N2
N3
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N4
N5
I/O
I/O
N6
J2
I/O
I/O
N7
J3
I/O
I/O
N8
J4
VCC
GND
GND
VCC
I/O
VCC
GND
GND
VCC
I/O
N9
J12
J13
J14
J15
K1
N10
N11
N12
N13
N14
N15
P1
I/O
I/O
K2
I/O
I/O
K3
I/O
I/O
K4
GND
GND
I/O
GND
GND
I/O
P2
K12
K13
K14
K15
L1
P3
P4
I/O
I/O
P5
I/O
I/O
P6
I/O
I/O
P7
L2
I/O
I/O
P8
L3
I/O
I/O
P9
L4
GND
I/O
GND
I/O
P10
P11
P12
P13
P14
P15
R1
L12
L13
L14
L15
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
N1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R2
GND
VCC
GND
I/O
GND
VCC
GND
I/O
R3
R4
R5
R6
GND
I/O
GND
I/O
R7
R8
GND
VCC
GND
I/O
GND
VCC
GND
I/O
R9
R10
R11
R12
R13
R14
R15
I/O
I/O
I/O
I/O
I/O
I/O
66
HiRel FPGAs
Package Pin Assignments (continued)
207-Pin CPGA (Top View)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
207-Pin
CPGA
K
L
K
L
M
N
P
R
S
T
M
N
P
R
S
T
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
67
207-Pin CPGA
A1460A
Function
A1460A
Function
A1460A
Function
Pin Number
Pin Number
Pin Number
A1
A2
NC
NC
I/O
C10
C11
C12
C13
C14
C15
C16
C17
D1
I/O
I/O
G3
G4
I/O
I/O
A3
I/O
G14
G15
G16
G17
H1
I/O
A4
I/O
I/O
I/O
A5
I/O
I/O
I/O
A6
I/O
GND
I/O
I/O
A7
I/O
PRA, I/O
I/O
A8
I/O
I/O
H2
A9
I/O
I/O
I/O
I/O
H3
I/O
A10
A11
A12
A13
A14
A15
A16
A17
B1
D2
I/O
H4
I/O
D3
I/O
H14
H15
H16
H17
J1
I/O
I/O
D4
GND
GND
I/O
I/O
I/O
D5
I/O
I/O
D6
I/O
I/O
NC
NC
NC
VCC
I/O
D7
MODE
I/O
I/O
D8
J2
VCC
CLKB, I/O
GND
GND
HCLK, I/O
VCC
I/O
D9
GND
I/O
J3
D10
D11
D12
D13
D14
D15
D16
D17
E1
J4
B2
VCC
I/O
J14
J15
J16
J17
K1
B3
B4
I/O
I/O
B5
I/O
GND
I/O
B6
I/O
CLKA, I/O
I/O
B7
I/O
I/O
K2
B8
I/O
I/O
K3
I/O
B9
VCC
I/O
I/O
K4
I/O
B10
B11
B12
B13
B14
B15
B16
B17
C1
E2
I/O
K14
K15
K16
K17
L1
I/O
I/O
E3
I/O
.
I/O
I/O
E4
DCLK, I/O
I/O
PRB, I/O
I/O
I/O
E14
E15
E16
E17
F1
I/O
I/O
I/O
I/O
I/O
L2
I/O
VCC
NC
NC
NC
SDI, I/O
I/O
I/O
L3
I/O
I/O
L4
I/O
F2
I/O
L14
L15
L16
L17
M1
M2
M3
M4
M14
I/O
C2
F3
I/O
I/O
C3
F4
I/O
I/O
C4
F14
F15
F16
F17
G1
I/O
I/O
C5
I/O
I/O
I/O
C6
I/O
I/O
I/O
C7
I/O
I/O
I/O
C8
I/O
I/O
I/O
C9
I/O
G2
I/O
I/O
68
HiRel FPGAs
207-Pin CPGA (Continued)
A1460A
Function
A1460A
Function
A1460A
Function
Pin Number
Pin Number
Pin Number
M15
M16
M17
N1
I/O
I/O
P17
R1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
NC
VCC
NC
I/O
I/O
I/O
I/O
I/O
VCC
S10
S11
S12
S13
S14
S15
S16
S17
T1
I/O
I/O
I/O
I/O
I/O
I/O
VCC
NC
NC
NC
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
R2
I/O
R3
N2
I/O
R4
N3
I/O
R5
N4
I/O
R6
N14
N15
N16
N17
P1
IOPCL, I/O
I/O
R7
R8
I/O
R9
T2
I/O
R10
R11
R12
R13
R14
R15
R16
R17
S1
T3
I/O
T4
P2
I/O
T5
P3
GND
GND
IOCLK, I/O
I/O
T6
P4
T7
P5
T8
P6
T9
P7
GND
I/O
T10
T11
T12
T13
T14
T15
T16
T17
P8
P9
GND
I/O
S2
P10
P11
P12
P13
P14
P15
P16
S3
I/O
S4
VCC
I/O
S5
S6
GND
I/O
S7
S8
I/O
S9
69
Package Pin Assignments (continued)
257-Pin CPGA (Top View)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
257-Pin
CPGA
K
L
K
L
M
N
P
R
T
M
N
P
R
T
V
X
Y
V
X
Y
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
70
HiRel FPGAs
257-Pin CPGA
A14100A
Function
A14100A
Function
A14100A
Function
Pin Number
Pin Number
Pin Number
A1
A2
I/O
I/O
C7
C8
I/O
I/O
E19
F1
I/O
I/O
A3
I/O
C9
I/O
F2
I/O
A4
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
D1
VCC
I/O
F3
I/O
A5
MODE
I/O
F4
I/O
A6
I/O
F16
F17
F18
F19
G1
I/O
A7
I/O
VCC
I/O
I/O
A8
I/O
I/O
A9
I/O
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
I/O
I/O
I/O
I/O
VCC
I/O
G2
I/O
I/O
G3
I/O
I/O
I/O
G4
I/O
I/O
I/O
G5
I/O
I/O
D2
I/O
G15
G16
G17
G18
G19
H1
I/O
I/O
D3
I/O
I/O
I/O
D4
GND
I/O
I/O
I/O
D5
I/O
I/O
D6
I/O
I/O
I/O
D7
I/O
I/O
B2
I/O
D8
I/O
H2
I/O
B3
I/O
D9
I/O
H3
I/O
B4
SDI, I/O
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
E1
GND
I/O
H4
I/O
B5
H16
H17
H18
H19
J1
I/O
B6
I/O
I/O
I/O
B7
I/O
I/O
I/O
B8
I/O
I/O
I/O
B9
I/O
I/O
PRA, I/O
I/O
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C1
I/O
GND
I/O
J2
I/O
J3
I/O
I/O
I/O
J4
I/O
I/O
I/O
J5
GND
I/O
I/O
I/O
J15
J16
J17
J18
J19
K1
I/O
E2
I/O
HCLK, I/O
PRB, I/O
I/O
GND
I/O
E3
I/O
E4
DCLK, I/O
NC
I/O
I/O
E5
I/O
I/O
E7
I/O
I/O
E9
I/O
K2
I/O
C2
I/O
E11
E13
E16
E17
E18
GND
I/O
K3
VCC
GND
GND
VCC
I/O
C3
VCC
GND
I/O
K4
C4
I/O
K16
K17
K18
C5
I/O
C6
I/O
I/O
71
257-Pin CPGA (Continued)
A14100A
Function
A14100A
Function
A14100A
Function
Pin Number
Pin Number
Pin Number
K19
L1
I/O
I/O
R9
R11
R13
R16
R17
R18
R19
T1
I/O
I/O
V17
V18
V19
X1
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L2
I/O
I/O
L3
I/O
IOPCL, I/O
I/O
L4
CLKA, I/O
CLKB, I/O
GND
I/O
X2
L5
I/O
X3
L15
L16
L17
L18
L19
M1
M2
M3
M4
M16
M17
M18
M19
N1
I/O
X4
I/O
X5
I/O
T2
I/O
X6
I/O
T3
I/O
X7
I/O
T4
GND
IOCLK, I/O
I/O
X8
I/O
T5
X9
I/O
T6
X10
X11
X12
X13
X14
X15
X16
X17
X18
X19
Y1
I/O
T7
I/O
I/O
T8
I/O
I/O
T9
I/O
I/O
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
V1
GND
I/O
I/O
I/O
I/O
I/O
I/O
N2
I/O
I/O
N3
I/O
I/O
N4
I/O
GND
GND
I/O
N5
I/O
Y2
N15
N16
N17
N18
N19
P1
I/O
Y3
I/O
I/O
Y4
I/O
I/O
Y5
I/O
V2
I/O
Y6
I/O
V3
VCC
I/O
Y7
I/O
V4
Y8
P2
I/O
V5
I/O
Y9
P3
I/O
V6
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
P4
I/O
V7
VCC
I/O
P16
P17
P18
P19
R1
I/O
V8
I/O
V9
I/O
I/O
V10
V11
V12
V13
V14
V15
V16
VCC
I/O
I/O
I/O
I/O
R2
I/O
I/O
R3
I/O
I/O
R4
GND
I/O
I/O
R7
I/O
72
HiRel FPGAs
Package Pin Assignments (continued)
84-Pin CQFP (Top View)
Pin #1
Index
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
84-Pin
CQFP
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
73
84-Pin CQFP
A1020B
Function
A32100DX
Function
A1020B
Function
A32100DX
Function
Pin Number
Pin Number
1
NC
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
MODE
I/O
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O
I/O
GND
I/O
2
3
I/O
I/O
4
I/O
I/O
I/O
5
I/O
I/O
I/O
6
I/O
I/O
I/O
7
VCC
GND
GND
I/O
I/O
8
I/O
GND
9
I/O
TCK, I/O
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
GND
VCC
I/O
CLKA, I/O
I/O
VCC
VCC
VCC
I/O
MODE
VCC
VCC
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
GND
I/O
I/O
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
SDI, I/O
I/O (WD)
I/O (WD)
I/O (WD)
I/O (WD)
QCLKD, I/O
I/O (WD)
I/O (WD)
PRA, I/O
CLKA, I/O
VCC
I/O
I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
I/O
QCLKA, I/O
GND
I/O (WD)
I/O
I/O
GND
I/O
I/O
GND
VCC
I/O
I/O
GND
I/O (WD)
I/O (WD)
QCLKB, I/O
I/O (WD)
GND
I/O (WD)
I/O (WD)
I/O (WD)
SDO, I/O
I/O
CLKB, I/O
PRB, I/O
I/O (WD)
I/O (WD)
QCLKC, I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O (WD)
I/O (WD)
DCLK, I/O
I/O
I/O
74
HiRel FPGAs
Package Pin Assignments (continued)
132-Pin CQFP (Top View)
132 131 130 129 128 127 126 125 124
107 106 105 104 103 102 101 100
Pin #1
Index
1
2
3
4
5
6
7
8
99
98
97
96
95
94
93
92
132-Pin
CQFP
25
26
27
28
29
30
31
32
33
75
74
73
72
71
70
69
68
67
34 35 36 37 38 39 40 41 42
59 60 61 62 63 64 65 66
75
132-Pin CQFP
A1425A
Function
A1425A
Function
A1425A
Function
Pin Number
Pin Number
Pin Number
1
NC
GND
SDI, I/O
I/O
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
I/O
I/O
89
90
VCC
GND
VCC
GND
I/O
2
3
I/O
91
4
PRB, I/O
I/O
92
5
I/O
93
6
I/O
HCLK, I/O
I/O
94
I/O
7
I/O
95
I/O
8
I/O
I/O
96
I/O
9
MODE
GND
VCC
I/O
I/O
97
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
98
IOCLK, I/O
NC
I/O
99
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
NC
I/O
I/O
GND
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
IOPCL, I/O
GND
NC
I/O
I/O
VCC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O
CLKB, I/O
PRA, I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
VCC
I/O
GND
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
DCLK, I/O
NC
I/O
76
HiRel FPGAs
Package Pin Assignments (continued)
172-Pin CQFP (Top View)
172 171 170 169 168 167 166 165 164
137 136 135 134 133 132 131 130
Pin #1
Index
1
2
3
4
5
6
7
8
129
128
127
126
125
124
123
122
172-Pin
CQFP
35
36
37
38
39
40
41
42
43
95
94
93
92
91
90
89
88
87
44 45 46 47 48 49 50 51 52
79 80 81 82 83 84 85 86
77
172-Pin CQFP
A1280A
Function
A1280XL
Function
A1280A
Function
A1280XL
Function
Pin Number
Pin Number
1
MODE
I/O
MODE
I/O
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
3
I/O
I/O
4
I/O
I/O
5
I/O
I/O
6
I/O
I/O
7
GND
I/O
GND
I/O
8
9
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
VCC
I/O
GND
VCC
VCC
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
78
HiRel FPGAs
172-Pin CQFP (Continued)
A1280A
Function
A1280XL
Function
A1280A
Function
A1280XL
Function
Pin Number
Pin Number
89
90
I/O
I/O
I/O
I/O
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
SDI, I/O
I/O
SDI, I/O
I/O
91
I/O
I/O
I/O
I/O
92
I/O
I/O
I/O
I/O
93
I/O
I/O
I/O
I/O
94
I/O
I/O
VCC
I/O
VCC
I/O
95
I/O
I/O
96
I/O
I/O
I/O
I/O
97
I/O
I/O
I/O
I/O
98
GND
I/O
GND
I/O
I/O
I/O
99
GND
I/O
GND
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
GND
VCC
VCC
I/O
GND
VCC
GND
VCC
VCC
I/O
PRA, I/O
I/O
PRA, I/O
I/O
CLKA, I/O
VCC
GND
I/O
CLKA, I/O
VCC
GND
I/O
I/O
I/O
CLKB, I/O
I/O
CLKB, I/O
I/O
VCC
I/O
VCC
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
VCC
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
I/O
DCLK, I/O
I/O
I/O
I/O
79
Package Pin Assignments (continued)
196-Pin CQFP (Top View)
196 195 194 193 192 191 190 189 188
155 154 153 152 151 150 149 148
Pin #1
Index
1
2
3
4
5
6
7
8
147
146
145
144
143
142
141
140
196-Pin
CQFP
41
42
43
44
45
46
47
48
49
107
106
105
104
103
102
101
100
99
50 51 52 53 54 55 56 57 58
91 92 93 94 95 96 97 98
80
HiRel FPGAs
196-Pin CQFP
A1460A
Function
A1460A
Function
A1460A
Function
Pin Number
Pin Number
Pin Number
1
GND
SDI, I/O
I/O
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
I/O
I/O
87
88
I/O
I/O
2
3
I/O
89
I/O
4
I/O
I/O
90
I/O
5
I/O
I/O
91
I/O
6
I/O
I/O
92
I/O
7
I/O
I/O
93
I/O
8
I/O
GND
GND
I/O
94
VCC
I/O
9
I/O
95
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O
96
I/O
MODE
VCC
GND
I/O
I/O
97
I/O
I/O
98
GND
I/O
I/O
99
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
IOPCL, I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
HCLK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
81
196-Pin CQFP (Continued)
A1460A
Function
A1460A
Function
A1460A
Function
Pin Number
Pin Number
Pin Number
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
I/O
I/O
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
I/O
I/O
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
GND
VCC
I/O
I/O
GND
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
IOCLK, I/O
GND
I/O
I/O
CLKA, I/O
CLKB, I/O
PRA, I/O
I/O
I/O
DCLK, I/O
I/O
I/O
82
HiRel FPGAs
Package Pin Assignments (continued)
208-Pin CQFP (Top View)
208 207 206 205 204 203 202 201 200
164 163 162 161 160 159 158 157
Pin #1
Index
1
2
3
4
5
6
7
8
156
155
154
153
152
151
150
149
208-Pin
CQFP
44
45
46
47
48
49
50
51
52
113
112
111
110
109
108
107
106
105
53 54 55 56 57 58 59 60 61
97 98 99 100 101 102 103 104
83
208-Pin CQFP
A32100DX
Function
A32100DX
Function
A32100DX
Function
Pin Number
Pin Number
Pin Number
1
GND
VCC
MODE
I/O
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
I/O
I/O
87
88
I/O
I/O
2
3
I/O
89
I/O
4
I/O
90
I/O
5
I/O
I/O
91
QCLKB, I/O
I/O
6
I/O
I/O
92
7
I/O
I/O
93
I/O (WD)
I/O (WD)
I/O
8
I/O
I/O
94
9
I/O
GND
GND
TMS, I/O
TDI, I/O
I/O
95
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O
96
I/O
I/O
97
I/O
I/O
98
VCC
I/O
I/O
99
I/O
I/O (WD)
I/O (WD)
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
I/O (WD)
I/O (WD)
I/O
I/O
I/O
VCC
I/O
VCC
SDO, I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
GND
I/O
QCLKA, I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
VCC
I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O (WD)
I/O (WD)
TCK, I/O
GND
I/O
84
HiRel FPGAs
208-Pin CQFP (Continued)
A32100DX
Function
A32100DX
Function
A32100DX
Function
Pin Number
Pin Number
Pin Number
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
VCC
GND
VCC
VCC
I/O
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
GND
I/O
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
I/O
SDI, I/O
I/O
CLKB, I/O
I/O
I/O (WD)
I/O (WD)
I/O
PRB, I/O
I/O
I/O
VCC
I/O
I/O (WD)
I/O (WD)
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (WD)
I/O (WD)
QCLKC, I/O
I/O
I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
I/O
QCLKD, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O (WD)
I/O (WD)
PRA, I/O
I/O
I/O (WD)
I/O (WD)
I/O
GND
I/O
I/O
I/O
I/O
CLKA, I/O
I/O
DCLK, I/O
I/O
I/O
I/O
VCC
I/O
VCC
85
Package Pin Assignments (continued)
256-Pin CQFP (Top View)
256 255 254 253 252 251 250 249 248
200 199 198 197 196 195 194 193
Pin #1
Index
1
2
3
4
5
6
7
8
192
191
190
189
188
187
186
185
256-Pin
CQFP
56
57
58
59
60
61
62
63
64
137
136
135
134
133
132
131
130
129
65 66 67 68 69 70 71 72 73
121 122 123 124 125 126 127 128
86
HiRel FPGAs
256-Pin CQFP
Pin
Number
A14100A
Function
A32200DX
Function
Pin
Number
A14100A
Function
A32200DX
Function
Pin
Number
A14100A
Function
A32200DX
Function
1
GND
SDI, I/O
I/O
NC
GND
I/O
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
89
I/O
PRB, I/O
GND
VCC
GND
VCC
I/O
I/O
I/O
2
90
3
I/O
91
I/O
4
I/O
I/O
GND
I/O
92
I/O
5
I/O
I/O
93
I/O
6
I/O
I/O
I/O
94
I/O
7
I/O
I/O
I/O
95
VCC
8
I/O
I/O
I/O
96
HCLK, I/O
I/O
VCC
9
I/O
I/O
I/O
97
GND
GND
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
GND
I/O
I/O
98
I/O
MODE
I/O
I/O
99
I/O
I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
GND
NC
I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
SDO, I/O
I/O
I/O
I/O
I/O
QCLKA, I/O
I/O
I/O
I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
VCC
GND
VCC
GND
I/O
I/O
VCC
I/O
I/O
VCC
VCC
GND
VCC
GND
TCK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O (WD)
GND
I/O (WD)
I/O
I/O
I/O
I/O
I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
QCLKB, I/O
I/O
I/O
I/O
I/O
I/O
TDI, I/O
TMS, I/O
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOPCL, I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O (WD)
I/O (WD)
I/O
GND
I/O
I/O
I/O
I/O
87
256-Pin CQFP (Continued)
Pin
Number
A14100A
Function
A32200DX
Function
Pin
Number
A14100A
Function
A32200DX
Function
Pin
Number
A14100A
Function
A32200DX
Function
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
VCC
VCC
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
GND
GND
I/O
I/O
I/O
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
I/O
I/O
I/O
PRB, I/O
I/O
I/O
CLKA, I/O
CLKB, I/O
VCC
GND
VCC
GND
PRA, I/O
I/O
I/O
I/O
CLKB, I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
GND
VCC
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
CLKA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
IOCLK, I/O
GND
I/O
MODE
VCC
I/O
I/O
I/O
GND
NC
I/O
I/O (WD)
I/O (WD)
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
QCLKD, I/O
I/O
I/O
I/O (WD)
I/O (WD)
VCC
I/O
I/O
I/O (WD)
GND
I/O (WD)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O (WD)
I/O (WD)
I/O
I/O
QCLKC, I/O
I/O
I/O
I/O
I/O
I/O
I/O (WD)
I/O (WD)
I/O
I/O
SDI, I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
I/O
I/O
DCLK, I/O
I/O
I/O (WD)
I/O (WD)
I/O
88
HiRel FPGAs
Package Mechanical Drawings
84-Pin CPGA
.050" ± .010"
Pin #1 ID
.045
.055
0.18" ± .002"
.100" BSC
.120"
.140"
1.100" ± .020" square
.080"
.110"
L
K
J
H
G
F
E
D
C
B
A
1.000 BSC
1
2
3
4
5
6
7
8
9
10 11
Orientation Pin
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
89
Package Mechanical Drawings (continued)
132-Pin CPGA
.085"
.110"
Pin #1 ID
.045
.055
0.18" ± .002"
.100" BSC
.050" ± .010"
1.360" ± .015" square
.120"
.140"
N
M
L
K
J
H
G
F
1.200 BSC
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
90
HiRel FPGAs
Package Mechanical Drawings (continued)
133-Pin CPGA
Top View
0.100"
0.130"
Pin #1
0.045"
0.055"
0.018" ± 0.002"
0.100" BSC
0.050" ± 0.010"
1.360" ± 0.015" square
0.120"
0.140"
N
M
L
Side View
K
J
H
G
F
1.200" BSC
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
Bottom View
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
91
Package Mechanical Drawings (continued)
176-Pin CPGA
INDEX MARK
0.102"
0.132"
0.100" BSC
0.018" ± .002"
0.050" ± .005"
0.120"
0.140"
1.570" ± .015" square
R
P
N
M
L
K
J
1.400 BSC
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
92
HiRel FPGAs
Package Mechanical Drawings (continued)
207-Pin CPGA
Top View
INDEX MARK
0.120" ± 0.015"
0.100" BSC
0.018" ± 0.002"
0.05" ± 0.005"
0.180" ± 0.010"
0.05" ± 0.005"
1.77" ± 0.010" square
Side View
U
T
R
P
N
M
L
K
J
1.600" BSC
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Bottom View
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
93
Package Mechanical Drawings (continued)
257-Pin CPGA
0.105" ± 0.012"
Top View
0.100" BSC
0.018" ± 0.002"
0.05" ± 0.005"
0.180" ± 0.010"
1.970" ± 0.015" square
0.05" ± 0.01"
Y
X
V
T
Side View
R
P
N
M
L
1.800" BSC
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
Bottom View
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
94
HiRel FPGAs
Package Mechanical Drawings (continued)
84-Pin CQFP
Top View
D1
D2
H
E1
E2
F
e
b
L1
Side View
A
Lid
c
A1
Notes:
1. Seal ring and lid are connected to Ground.
2. Lead material is Kovar with minimum 50 microinches gold plate over nickel.
3. Packages are shipped unformed with the ceramic tie bar in a test carrier.
95
Package Mechanical Drawings (continued)
132-Pin, 172-Pin, 196-Pin, 208-Pin, and 256-Pin CQFP (Cavity Up)
Top View
H
D1
D2
No. 1
Ceramic
Tie Bar
L1
K
E2 E1
F
e
b
Side View
Lid
A
C
Lead Kovar
A1
Notes:
1. Outside leadframe holes (from dimension H) are circular for the CQ208 and CQ256.
2. Seal ring and lid are connected to Ground.
3. Lead material is Kovar with minimum 50 microinches gold plate over nickel.
4. Packages are shipped unformed with the ceramic tie bar.
5. 32200DX – CQ208 has a heat sink on the back.
96
HiRel FPGAs
CQFP (Ceramic Quad Flat Pack)
CQFP 84
CQFP 132
Nom.
CQFP 172
Nom.
CQFP 196
Nom.
Symbol
Min.
Nom.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
A
0.070
0.060
0.008
0.004
0.640
0.090
0.075
0.100
0.080
0.012
0.008
0.660
0.094
0.080
0.007
0.004
0.940
0.105
0.090
0.116
0.100
0.010
0.008
0.960
0.094
0.080
0.007
0.004
1.168
0.105
0.090
0.116
0.100
0.010
0.008
1.192
0.094
0.080
0.007
0.004
1.336
0.105
0.090
0.116
0.100
0.010
0.008
1.364
A1
b
c
0.010
0.008
0.008
0.008
0.006
0.006
0.006
0.006
D1/E1
D2/E2
e
0.650
0.950
1.180
1.350
0.500 BSC
0.025 BSC
0.140
0.800 BSC
0.025 BSC
0.350
1.050 BSC
0.025 BSC
0.200
1.200 BSC
0.025 BSC
0.200
F
0.130
0.150
0.325
0.375
0.175
0.225
0.175
0.225
H
1.460 BSC
—
2.320 BSC
2.140 BSC
2.500
2.320 BSC
2.140 BSC
2.495
2.320 BSC
2.140 BSC
2.495
K
L1
1.595
1.600
1.615
2.485
2.505
2.485
2.505
2.485
2.505
Note:
1. All dimensions are in inches except CQ208 and CQ256, which are in millimeters.
2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
CQFP (Ceramic Quad Flat Pack)
CQFP 208
Nom.
CQFP 256
Nom.
Symbol
Min.
Max.
Min.
Max.
A
2.78
2.43
0.18
0.11
28.96
3.17
2.79
3.56
3.15
0.22
0.17
29.46
2.28
1.93
0.18
0.11
35.64
2.67
2.29
3.06
2.65
0.22
0.18
36.36
A1
b
c
0.20
0.20
0.15
0.15
D1/E1
D2/E2
e
29.21
36.00
25.5 BSC
0.50 BSC
7.75
31.5 BSC
0.50 BSC
7.75
F
7.05
8.45
7.05
8.45
H
70.00 BSC
65.90 BSC
75.00
70.00 BSC
65.90 BSC
75.00
K
L1
74.60
75.40
74.60
75.40
Note:
1. All dimensions are in inches except CQ208 and CQ256, which are in millimeters.
2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
97
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
Actel Corporation
955 East Arques Avenue
Sunnyvale, California 94086
USA
Actel Asia-Pacific
Daneshill House, Lutyens Close
Basingstoke, Hampshire RG24 8AG
United Kingdom
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Tel: +44-(0)125-630-5600
Fax: +44-(0)125-635-5420
Tel: (408) 739-1010
Fax: (408) 739-1540
Tel: +81-(0)3-3445-7671
Fax: +81-(0)3-3445-7668
5192641-2/1.00
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