A1020B-1PLG68M [ACTEL]
Field Programmable Gate Array, 547 CLBs, 2000 Gates, 547-Cell, CMOS, PQCC68, PLASTIC, LCC-68;
| 型号： | A1020B-1PLG68M |
| 厂家： | 
Actel Corporation |
| 描述： | Field Programmable Gate Array, 547 CLBs, 2000 Gates, 547-Cell, CMOS, PQCC68, PLASTIC, LCC-68 栅 |
| 文件： | 总24页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACT™ 1 Series FPGAs
F e a t u r e s
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.
• 5V and 3.3V Families fully compatible with JEDEC
specifications
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL® Packages
P r o d u c t F a m i l y P r o f i l e
A1010B
A1020B
Device
A10V10B A10V20B
• Design Library with over 250 Macro Functions
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
1,200
3,000
30
2,000
6,000
50
• Gate Array Architecture Allows Completely Automatic
Place and Route
12
20
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
Logic Modules
295
147
547
273
Flip-Flops (maximum)
• Data Rates to 75 MHz
Routing Resources
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 25 MHz
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
22
13
22
13
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
112,000
186,000
User I/Os (maximum)
Packages:
57
69
44 PLCC 44 PLCC
68 PLCC 68 PLCC
84 PLCC
• Fabricated in 1.0 micron CMOS technology
100 PQFP 100 PQFP
80 VQFP 80 VQFP
84 CPGA 84 CPGA
84 CQFP
D e s c r i p t i o n
The ACT™ 1 Series of field programmable gate arrays
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel’s
PLICE® antifuse technology. The unique architecture offers
gate array flexibility, high performance, and instant
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
Performance
5 V Data Rate (maximum)
3.3 V Data Rate (maximum)
75 MHz
55 MHz
75 MHz
55 MHz
Note: See Product Plan on page 1-286 for package availability.
T h e D e s i g n e r a n d D e s i g n e r
A d v a n t a g e ™ S y s t e m s
ACT 1 devices also provide system designers with unique
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
clock driver with a hardwired distribution network. The
network provides efficient clock distribution with minimum
skew.
The ACT 1 device family is supported by Actel’s Designer and
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
Microsoft® Windows™ and X Windows™ graphical user
interfaces and integrate with the resident CAE system to
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmap™ VHDL optimization and synthesis tool
and the ACTgen™ Macro Builder, a powerful macro function
generator for counters, adders, and other structural blocks.
The user-definable I/Os are capable of driving at both TTL
and CMOS drive levels. Available packages include plastic
and ceramic J-leaded chip carriers, ceramic and plastic quad
flatpacks, and ceramic pin grid array.
A p r i l 1 9 9 6
1 -2 8 3
© 1996 Actel Corporation
The systems are available for 386/486/Pentium™ PC and for
HP™ and Sun™ workstations and for running Viewlogic®,
Mentor Graphics®, Cadence™, OrCAD™, and Synopsys
design environments.
Figure 1 • Partial View of an ACT 1 Device
A C T 1 D e v i c e S t r u c t u r e
A partial view of an ACT 1 device (Figure 1) depicts four logic
modules and distributed horizontal and vertical interconnect
tracks. PLICE antifuses, located at intersections of the
horizontal and vertical tracks, connect logic module inputs
and outputs. During programming, these antifuses are
addressed and programmed to make the connections
required by the circuit application.
T h e A C T 1 L o g i c M o d u l e
The ACT 1 logic module is an 8-input, one-output logic circuit
chosen for the wide range of functions it implements and for
its efficient use of interconnect routing resources (Figure 2).
The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two, three,
or four inputs. Each function may have many versions, with
different combinations of active-low inputs. The logic module
can also implement a variety of D-latches, exclusivity
functions, AND-ORs, and OR-ANDs. No dedicated hardwired
latches or flip-flops are required in the array, since latches
and flip-flops may be constructed from logic modules
wherever needed in the application.
Figure 2 • ACT 1 Logic Module
I /O B u f f e r s
Each I/O pin is available as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Outputs sink or
1 -2 8 4
™
A C T
1 S e r i e s F P G A s
A C T 1 A r r a y P e r f o r m a n c e
source 10 mA at TTL levels. See Electrical Specifications for
additional I/O buffer specifications.
T e m p e r a t u r e a n d Vo lt a g e E ffe c t s
Worst-case delays for ACT 1 arrays are calculated in the same
manner as for masked array products. A typical delay
parameter is multiplied by a derating factor to account for
temperature, voltage, and processing effects. However, in an
ACT 1 array, temperature and voltage effects are less
dramatic than with masked devices. The electrical
characteristics of module interconnections on ACT 1 devices
remain constant over voltage and temperature fluctuations.
D e v i c e O r g a n i z a t i o n
ACT 1 devices consist of a matrix of logic modules arranged in
rows separated by wiring channels. This array is surrounded
by a ring of peripheral circuits including I/O buffers,
testability circuits, and diagnostic probe circuits providing
real-time diagnostic capability. Between rows of logic
modules are routing channels containing sets of segmented
metal tracks with PLICE antifuses. Each channel has 22
signal tracks. Vertical routing is permitted via 13 vertical
tracks per logic module column. The resulting network allows
arbitrary and flexible interconnections between logic
modules and I/O modules.
As a result, the total derating factor from typical to
worst-case for a standard speed ACT 1 array is only 1.19 to 1,
compared to 2 to 1 for a masked gate array.
Lo g ic Mo d u le S iz e
Logic module size also affects performance. A mask
programmed gate array cell with four transistors usually
implements only one logic level. In the more complex logic
module (similar to the complexity of a gate array macro) of
an ACT 1 array, implementation of multiple logic levels
within a single module is possible. This eliminates interlevel
wiring and associated RC delays. The effect is termed “net
compression.”
P r o b e P i n
ACT 1 devices have two independent diagnostic probe pins.
These pins allow the user to observe any two internal signals
by entering the appropriate net name in the diagnostic
software. Signals may be viewed on a logic analyzer using
Actel’s Actionprobe® diagnostic tools. The probe pins can
also be used as user-defined I/Os when debugging is finished.
O r d e r i n g I n f o r m a t i o n
A1010
B
–
2
PL
84
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I
= Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carriers
PQ = Plastic Quad Flatpacks
CQ = Ceramic Quad Flatpack
PG = Ceramic Pin Grid Array
VQ = Very Thin Quad Flatpack
Speed Grade
Blank = Standard Speed
–1
–2
–3
= Approximately 15% faster than Standard
= Approximately 25% faster than Standard
= Approximately 35% faster than Standard
Die Revision
B = 1.0 micron CMOS Process
Part Number
A1010 = 1200 Gates (5 V)
A1020 = 2000 Gates (5 V)
A10V10 = 1200 Gates (3.3 V)
A10V20 = 2000 Gates (3.3 V)
1 -2 8 5
P r o d u c t P l a n
Speed Grade*
Application
M
Std
–1
–2
–3
C
I
B
A1010B Device
44-pin Plastic Leaded Chip Carrier (PL)
68-pin Plastic Leaded Chip Carrier (PL)
100-pin Plastic Quad Flatpack (PQ)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
✔
✔
✔
✔
—
✔
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
—
—
✔
—
—
—
—
✔
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
84-pin Ceramic Pin Grid Array (PG)
A1020B Device
44-pin Plastic Leaded Chip Carrier (PL)
68-pin Plastic Leaded Chip Carrier (PL)
84-pin Plastic Leaded Chip Carrier (PL)
100-pin Plastic Quad Flatpack (PQ)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
84-pin Ceramic Pin Grid Array (PG)
84-pin Ceramic Quad Flatpack (CQ)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
✔
✔
✔
✔
✔
—
—
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
—
—
—
—
✔
—
—
—
—
—
✔
✔
✔
A10V10B Device
68-pin Plastic Leaded Chip Carrier (PL)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
✔
✔
—
—
—
—
—
—
✔
✔
—
—
—
—
—
—
A10V20B Device
68-pin Plastic Leaded Chip Carrier (PL)
84-pin Plastic Leaded Chip Carrier (PL)
80-pin Very Thin (1.0 mm) Quad Flatpack (VQ)
✔
✔
✔
—
—
—
—
—
—
—
—
—
✔
✔
✔
—
—
—
—
—
—
—
—
—
Applications: C = Commercial Availability: ✔ = Available
* Speed Grade: –1 = Approx. 15% faster than Standard
–2 = Approx. 25% faster than Standard
I
= Industrial
P = Planned
M = Military
— = Not Planned
–3 = Approx. 35% faster than Standard
B = MIL-STD-883
D e v i c e R e s o u r c e s
User I/Os
Device
Logic Modules
Gates
44-pin
68-pin
80-pin
84-pin
100-pin
A1010B, A10V10B
A1020B, A10V20B
295
547
1200
2000
34
34
57
57
57
69
57
69
57
69
1 -2 8 6
™
A C T
1 S e r i e s F P G A s
P R A
P r o b e A (O u t p u t )
P i n D e s c r i p t i o n
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect the
programmed design’s confidentiality. PRA is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
C LK
C lo c k (In p u t )
TTL Clock input for global clock distribution network. The
Clock input is buffered prior to clocking the logic modules.
This pin can also be used as an I/O.
DC LK
Dia g n o s t ic C lo c k (In p u t )
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
G N D
G r o u n d
P R B
P r o b e B (O u t p u t )
Input LOW supply voltage.
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect the
programmed design’s confidentiality. PRB is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
I/O
In p u t /O u t p u t (In p u t , O u t p u t )
I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are automatically driven LOW by the ALS software.
MO DE
Mo d e (In p u t )
The MODE pin controls the use of multifunction pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/O. To provide Actionprobe capability, the MODE
pin should be terminated to GND through a 10K resistor so
that the MODE pin can be pulled high when required.
S DI
S e r ia l Da t a In p u t (In p u t )
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
N C
N o C o n n e c t io n
This pin is not connected to circuitry within the device.
V
S u p p ly Vo lt a g e
C C
Input HIGH supply voltage.
1
R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s
A b s o l u t e M a x i m u m R a t i n g s
Free air temperature range
Parameter
Commercial Industrial
Military
Units
Symbol Parameter
Limits
Units
Temperature
Range
0 to
+70
–40 to
+85
–55 to
+125
1
°C
2
V
V
DC Supply Voltage
Input Voltage
–0.5 to +7.0
Volts
CC
I
PowerSupply
Tolerance
–0.5 to V +0.5 Volts
CC
±5
±10
±10
%V
CC
V
I
Output Voltage
I/O Sink/Source
–0.5 to V +0.5 Volts
CC
O
Note:
±20
mA
1. Ambient temperature (T ) used for commercial and industrial;
IO
A
3
case temperature (T ) used for military.
Current
C
T
Storage Temperature
–65 to +150
°C
STG
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Device should not be operated outside
the Recommended Operating Conditions.
2. V = V , except during device programming.
PP
CC
3. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than V + 0.5 V or less than GND – 0.5 V, the internal protection
CC
diode will be forward biased and can draw excessive current.
1 -2 8 7
E l e c t r i c a l S p e c i f i c a t i o n s ( 5 V )
Commercial
Industrial
Military
Symbol
Parameter
(I = –10 mA)
Min.
Max.
Min.
Max.
Min.
Max.
Units
2
2.4
V
V
OH
1
V
(I = –6 mA)
3.84
OH
OH
(I = –4 mA)
3.7
3.7
V
OH
2
(I = 10 mA)
0.5
0.33
0.8
V
OL
1
V
OL
(I = 6 mA)
0.40
0.8
0.40
0.8
V
OL
V
V
–0.3
2.0
–0.3
2.0
–0.3
2.0
V
IL
V
+ 0.3
V
+ 0.3
V + 0.3
CC
V
IH
CC
CC
2
Input Transition Time t , t
500
10
3
500
10
500
10
ns
pF
mA
µA
R
F
2, 3
C
I/O Capacitance
IO
4
Standby Current, I
(typical = 1 mA)
10
20
CC
5
Leakage Current
–10
10
–10
10
–10
10
Notes:
1. Only one output tested at a time. V = min.
CC
2. Not tested, for information only.
3. Includes worst-case 84-pin PLCC package capacitance. V = 0 V, f = 1 MHz.
OUT
4. Typical standby current = 1 mA. All outputs unloaded. All inputs = V or GND.
CC
5. V , V = V or GND.
O
IN
CC
E l e c t r i c a l S p e c i f i c a t i o n s ( 3 . 3 V )
Commercial
Parameter
Units
Min.
2.15
2.4
Max.
(I = –4 mA)
V
V
OH
1
V
OH
(I = –3.2 mA)
OH
1
V
V
V
(I = 6 mA)
0.4
0.8
V
OL
OL
–0.3
2.0
V
IL
V
+ 0.3
V
IH
CC
2
Input Transition Time t , t
500
ns
pF
mA
µA
R
F
2, 3
C
I/O Capacitance
10
0.75
10
IO
4
Standby Current, I
(typical = 0.3 mA)
CC
5
Leakage Current
–10
Notes:
1. Only one output tested at a time. V = min.
CC
2. Not tested, for information only.
3. Includes worst-case 84-pin PLCC package capacitance. V = 0 V, f = 1 MHz.
OUT
4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = V or GND.
CC
5. V , V = V or GND
O
IN
CC
1 -2 8 8
™
A C T
1 S e r i e s F P G A s
P a c k a g e T h e r m a l C h a r a c t e r i s t i c s
A sample calculation of the maximum power dissipation for
an 84-pin plastic leaded chip carrier at commercial
temperature is as follows:
The device junction to case thermal characteristics is
θjc, and the junction to ambient air characteristics is θja. The
thermal characteristics for θja are shown with two different
air flow rates. Maximum junction temperature is 150°C.
Max junction temp.(°C) – Max commercial temp.(°C)
150°C – 70°C
37°C ⁄ W
------------------------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.2 W
θja(°C ⁄ W)
θja
Still Air
θja
300 ft/min
Package Type
Pin Count
θjc
Units
44
68
84
15
13
12
45
38
37
35
29
28
°C/W
°C/W
°C/W
Plastic J-Leaded Chip Carrier
Plastic Quad Flatpack
100
80
13
12
8
48
43
33
40
40
35
20
30
°C/W
°C/W
°C/W
°C/W
Very Thin (1.0 mm) Quad Flatpack
Ceramic Pin Grid Array
84
Ceramic Quad Flatpack
84
5
G e n e r a l P o w e r E q u a t i o n
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst case conditions.
P = [ICCstandby + ICCactive] * V + IOL * V * N + IOH
*
CC
OL
(V – V ) * M
CC
OH
ICC
V
Power
CC
Where:
3 mA
5.25 V
5.25 V
3.60 V
3.30 V
15.75 mW (max)
5.25 mW (typ)
2.70 mW (max)
0.99 mW (typ)
ICCstandby is the current flowing when no inputs or
outputs are changing.
1 mA
0.75 mA
0.30 mA
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
Ac t iv e P o w e r C o m p o n e n t
V , VOH are TTL level output voltages.
OL
N equals the number of outputs driving TTL loads to
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the
V .
OL
M equals the number of outputs driving TTL loads to
V .
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
and load device inputs. An additional component of the active
power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with frequency
and voltage to represent active power dissipation.
OH
An accurate determination of N and M is problematical
because their values depend on the family type, design
details, and on the system I/O. The power can be divided into
two components: static and active.
S t a t ic P o w e r C o m p o n e n t
Actel FPGAs have small static power components that result
in lower power dissipation than PALs or PLDs. By integrating
multiple PALs/PLDs into one FPGA, an even greater
reduction in board-level power dissipation can be achieved.
1 -2 8 9
E q u iv a le n t C a p a c it a n c e
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
CEQO = Equivalent capacitance of output buffers in pF
Power (uW) = CEQ * VCC2 * F
(1)
CEQCR = Equivalent capacitance of routed array clock in
pF
Where:
CEQ is the equivalent capacitance expressed in pF.
CL
fm
fn
= Output lead capacitance in pF
V is the power supply in volts.
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
CC
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
fp
fq1
= Average first routed array clock rate in MHz (All
families)
range of frequencies at a fixed value of V . Equivalent
CC
capacitance is frequency independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
F ix e d C a p a c it a n c e Va lu e s fo r Ac t e l F P G As
(p F )
r1
C
Va lu e s fo r Ac t e l F P G As
E Q
Device Type
A1010B
routed_Clk1
41.4
68.6
40
A10V10B
A10V20B
A1010B
A1020B
A1020B
Modules (CEQM
Input Buffers (CEQI
Output Buffers (CEQO
Routed Array Clock Buffer
Loads (CEQCR
)
3.2
10.9
11.6
3.7
22.1
31.2
A10V10B
A10V20B
)
65
)
De t e r m in in g Av e r a g e S w it c h in g F r e q u e n c y
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
)
4.1
4.6
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
Logic Modules (m)
90% of modules
#inputs/4
Power = V 2 * [(m * CEQM * fm)modules
+
CC
Inputs switching (n)
(n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs
0.5 * (q1 * CEQCR * fq1)routed_Clk1
(r1 * fq1)routed_Clk1
+
Outputs switching (p)
First routed array clock loads (q1)
Load capacitance (CL)
#outputs/4
40% of modules
35 pF
+
]
(2)
Where:
Average logic module switching rate (fm) F/10
m
n
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
Average input switching rate (fn)
Average output switching rate (fp)
F/5
F/10
p
Average first routed array clock rate F
(fq1)
q1
= Number of clock loads on the first routed array
clock (All families)
r1
= Fixed capacitance due to first routed array
clock (All families)
1 -2 9 0
™
A C T
1 S e r i e s F P G A s
F u n c t i o n a l T i m i n g T e s t s
logic modules are distributed along two sides of the device, as
inverting or non-inverting buffers. The modules are
connected through programmed antifuses with typical
capacitive loading.
AC timing for logic module internal delays is determined
after place and route. The DirectTime Analyzer utility
displays actual timing parameters for circuit delays. ACT 1
devices are AC tested to a “binning” circuit specification.
Propagation delay [tPD = (tPLH + tPHL)/2] is tested to the
following AC test specifications.
The circuit consists of one input buffer + n logic modules +
one output buffer (n = 16 for A1010B; n = 28 for A1020B). The
O u t p u t B u f f e r P e r f o r m a n c e D e r a t i n g ( 5 V )
Sink
Source
12
–4
10
8
–6
–8
6
4
–10
–12
0.2
0.3
0.4
0.5
0.6
4.0
3.6
3.2
2.8
2.4
2.0
V
(Volts)
V
(Volts)
OL
OH
Military, worst-case values at 125°C, 4.5 V.
Commercial, worst-case values at 70°C, 4.75 V.
Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices.
O u t p u t B u f f e r P e r f o r m a n c e D e r a t i n g ( 3 . 3 V )
Sink
Source
12
10
–4
–6
8
–8
6
4
–10
–12
0
0.0
0.1
0.2
0.3
0.4
0.5
1.0
1.5
2.0
2.5
V
(Volts)
V
(Volts)
OL
OH
Commercial, worst-case values at 70°C, 4.75 V.
Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices.
1 -2 9 1
A C T 1 T i m i n g M o d u l e *
Input Delay
Internal Delays
Predicted
Routing
Delays
Output Delay
I/O Module
I/O Module
Logic Module
t
= 3.1 ns
INYL
t
t
= 1.4 ns
IRD2
t
= 6.7 ns
DLH
t
= 0.9 ns
= 3.1 ns
= 6.6 ns
t
t
t
= 0.9 ns
IRD1
RD1
t
t
= 2.9 ns
= 2.9 ns
PD
CO
t
= 11.6 ns
= 1.4 ns
= 3.1 ns
= 6.6 ns
ENHZ
RD2
IRD4
t
IRD8
RD4
t
RD8
ARRAY
CLOCK
t
= 5.6 ns
FO = 128
CKH
F
= 70 MHz
MAX
* Values shown for ACT 1 ‘–3 speed’ devices at worst-case commercial conditions.
P r e d i c t a b l e P e r f o r m a n c e : T i g h t D e l a y
D i s t r i b u t i o n s
T i m i n g C h a r a c t e r i s t i c s
Timing characteristics for ACT 1 devices fall into three
categories: family dependent, device dependent, and design
dependent. The input and output buffer characteristics are
common to all ACT 1 family members. Internal routing delays
are device dependent. Design dependency means actual delays
are not determined until after placement and routing of the
user design is complete. Delay values may then be determined
by using the DirectTime Analyzer utility or performing
simulation with post-layout delays.
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of
inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer routing tracks.
C r it ic a l N e t s a n d T y p ic a l N e t s
Propagation delays are expressed only for typical nets, which
are used for initial design performance evaluation. Critical
net delays can then be applied to the most time-critical paths.
Critical nets are determined by net property assignment prior
to placement and routing. Up to 6% of the nets in a design may
be designated as critical, while 90% of the nets in a design are
typical.
The ACT 1 family delivers a very tight fanout delay
distribution. This tight distribution is achieved in two ways: by
decreasing the delay of the interconnect elements and by
decreasing the number of interconnect elements per path.
Actel’s patented PLICE antifuse offers a very low
resistive/capacitive interconnect. The ACT 1 family’s
antifuses, fabricated in 1.0 micron lithography, offer nominal
levels of 200 ohms resistance and 7.5 femtofarad (fF)
capacitance per antifuse.
Lo n g T r a c k s
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes four
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 5 ns to 10 ns delay. This additional delay is
represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section.
The ACT 1 fanout distribution is also tight due to the low
number of antifuses required for each interconnect path. The
ACT 1 family’s proprietary architecture limits the number of
antifuses per path to a maximum of four, with 90% of
interconnects using two antifuses.
1 -2 9 2
™
A C T
1 S e r i e s F P G A s
T im in g De r a t in g
“standard speed” timing parameters, and must be multiplied
by the appropriate voltage and temperature derating factors
for a given application.
A best case timing derating factor of 0.45 is used to reflect
best case processing. Note that this factor is relative to the
T i m i n g D e r a t i n g F a c t o r ( T e m p e r a t u r e a n d V o l t a g e )
Industrial
Military
Min.
Max.
Min.
Max.
(Commercial Minimum/Maximum Specification) x
0.69
1.11
0.67
1.23
T i m i n g D e r a t i n g F a c t o r f o r D e s i g n s a t T y p i c a l T e m p e r a t u r e ( T = 2 5 °C ) a n d
J
V o l t a g e ( 5 . 0 V )
(Commercial Maximum Specification) x
0.85
T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s
( n o r m a l i z e d t o W o r s t -C a s e C o m m e r c i a l , T = 4 . 7 5 V , 7 0 °C )
J
–55
–40
0
25
70
85
125
4.50
4.75
5.00
5.25
5.50
0.75
0.71
0.69
0.68
0.67
0.79
0.75
0.72
0.69
0.69
0.86
0.82
0.80
0.77
0.76
0.92
0.87
0.85
0.82
0.81
1.06
1.00
0.97
0.95
0.93
1.11
1.05
1.02
0.98
0.97
1.23
1.16
1.13
1.09
1.08
Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial,TJ = 4.75 V, 70°C)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
125°C
85°C
70°C
25°C
0°C
–40°C
–55°C
4.50
4.75
5.00
5.25
5.50
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
1 -2 9 3
T e m p e r a t u r e a n d V o l t a g e D e r a t i n g
F a c t o r s ( n o r m a l i z e d t o W o r s t -C a s e
C o m m e r c i a l , T = 3 . 0 V , 7 0 °C )
J
0
25
70
2.7
3.0
3.3
3.6
1.05
0.81
0.64
0.62
1.09
0.84
0.67
0.64
1.30
1.00
0.79
0.76
Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial,TJ = 3.0 V, 70°C)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
70°C
25°C
0°C
0.6
0.5
2.7
3.0
3.3
3.6
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
1 -2 9 4
™
A C T
1
S e r i e s F P G A s
P a r a m e t e r M e a s u r e m e n t
O u t p u t B u ffe r De la y s
E
D
PAD To AC test loads (shown below)
TRIBUFF
V
V
V
CC
CC
CC
In
GND
1.5 V
50%
E
GND
E
50%
GND
50%
50%
CC
50%
50%
V
V
V
OH
OH
1.5 V
90%
PAD
PAD
PAD
1.5 V
10%
1.5 V
V
V
GND
OL
OL
t
t
t
t
t
t
ENHZ
DLH
DHL
ENZL
ENLZ
ENZH
AC T e s t Lo a d s
Load 1
Load 2
(Used to measure propagation delay)
(Used to measure rising/falling edges)
V
GND
CC
To the output under test
35 pF
R to V for t /t
CC
PLZ PZL
R to GND for t
/t
PHZ PZH
R = 1 kΩ
To the output under test
35 pF
In p u t B u ffe r De la y s
Mo d u le De la y s
S
Y
A
B
Y
PAD
INBUF
V
CC
GND
S, A or B
50% 50%
3 V
1.5 V
V
CC
PAD
0 V
1.5 V
50%
Out
50%
V
CC
GND
t
t
50%
PLH
PHL
Y
GND
50%
V
Out
CC
GND
50%
50%
t
t
INYL
INYH
t
t
PLH
PHL
1 -2 9 5
S e q u e n t i a l T i m i n g C h a r a c t e r i s t i c s
F lip -F lo p s a n d La t c h e s
D
E
CLK
Q
PRE
CLR
(Positive edge triggered)
t
HD
1
D
t
t
t
A
WCLKA
SUD
CLK
t
SUENA
E
t
CO
Q
t
RS
PRE, CLR
t
WASYN
Note: D represents all data functions involving A, B, S for multiplexed flip-flops.
1 -2 9 6
™
A C T
1 S e r i e s F P G A s
A C T 1 T i m i n g C h a r a c t e r i s t i c s
1
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V
Logic Module Propagation Delays
Parameter Description
= 4 . 7 5 V, T = 7 0 °C )
J
C C
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
Single Module
2.9
6.8
2.9
2.9
2.9
3.4
7.8
3.4
3.4
3.4
3.8
8.8
3.8
3.8
3.8
4.5
10.4
4.5
6.5
15.1
6.5
ns
ns
ns
ns
ns
PD1
PD2
CO
Dual Module Macros
Sequential Clk to Q
Latch G to Q
4.5
6.5
GO
RS
Flip-Flop (Latch) Reset to Q
4.5
6.5
2
Predicted Routing Delays
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.9
1.4
2.1
3.1
6.6
1.1
1.7
2.5
3.6
7.7
1.2
1.9
2.8
4.1
8.7
1.4
2.2
2.0
3.2
ns
ns
ns
ns
ns
RD1
RD2
RD3
RD4
RD8
3.3
4.8
4.8
7.0
10.2
14.8
3
Sequential Timing Characteristics
t
t
t
t
t
Flip-Flop (Latch) Data Input Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
5.5
0.0
5.5
0.0
6.4
0.0
6.4
0.0
7.2
0.0
7.2
0.0
8.5
0.0
8.5
0.0
10.0
0.0
ns
ns
ns
ns
SUD
4
HD
10.0
0.0
SUENA
HENA
Flip-Flop (Latch) Clock Active Pulse
Width
WCLKA
6.8
8.0
9.0
10.5
9.8
ns
t
Flip-Flop (Latch)
WASYN
Asynchronous Pulse Width
6.8
8.0
9.0
10.5
22.3
9.8
ns
ns
t
f
Flip-Flop Clock Input Period
14.2
16.7
18.9
20.0
A
Flip-Flop (Latch) Clock
Frequency (FO = 128)
MAX
70
60
53
45
50
MHz
Notes:
1.
V
= 3.0 V for 3.3V specifications.
CC
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
3. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility.
4. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro.
1 -2 9 7
A C T 1 T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )
Input Module Propagation Delays
Parameter Description
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
Pad to Y High
Pad to Y Low
3.1
3.1
3.5
3.5
4.0
4.0
4.7
4.7
6.8
6.8
ns
ns
INYH
INYL
1
Input Module Predicted Routing Delays
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.9
1.4
2.1
3.1
6.6
1.1
1.7
2.5
3.6
7.7
1.2
1.9
2.8
4.1
8.7
1.4
2.2
2.0
3.2
ns
ns
ns
ns
ns
IRD1
IRD2
IRD3
IRD4
IRD8
3.3
4.8
4.8
7.0
10.2
14.8
Global Clock Network
t
t
t
t
t
t
f
Input Low to High
FO = 16
FO = 128
4.9
5.6
5.6
6.4
6.4
7.3
7.5
8.6
6.7
7.9
CKH
CKL
PWH
PWL
CKSW
P
ns
ns
ns
ns
ns
ns
Input High to Low
FO = 16
FO = 128
6.4
7.0
7.4
8.1
8.4
9.2
9.9
10.8
8.8
10.0
Minimum Pulse Width
High
FO = 16
FO = 128 6.8
6.5
7.5
8.0
8.5
9.0
10.0
10.5
8.9
9.8
Minimum Pulse Width
Low
FO = 16 6.5
FO = 128 6.8
7.5
8.0
8.5
9.0
10.0
10.5
8.9
9.8
Maximum Skew
FO = 16
FO = 128
1.2
1.8
1.3
2.1
1.5
2.4
1.8
2.8
1.5
2.4
Minimum Period
Maximum Frequency
FO = 16
FO = 128 14.2
13.2
15.4
16.7
17.6
18.9
20.9
22.3
18.2
20
FO = 16
FO = 128
75
70
65
60
57
53
48
45
55
MAX
50 MHz
Note:
1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior
to shipment.
1 -2 9 8
™
A C T
1 S e r i e s F P G A s
A C T 1 T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )
Output Module Timing
Parameter Description
TTL Output Module Timing
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
1
t
t
t
t
t
t
Data to Pad High
6.7
7.5
7.6
8.6
8.7
9.8
10.3
11.5
10.2
12.2
15.4
13.9
0.09
0.12
15.0
16.7
14.8
17.7
22.4
20.2
ns
ns
ns
ns
ns
ns
DLH
Data to Pad Low
DHL
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
Delta Low to High
6.6
7.5
8.6
ENZH
ENZL
ENHZ
ENLZ
7.9
9.1
10.4
13.1
11.8
0.08
0.10
10.0
9.0
11.6
10.4
0.07
0.09
d
d
0.06
0.08
0.13 ns/pF
0.17 ns/pF
TLH
THL
Delta High to Low
1
CMOS Output Module Timing
t
t
t
t
t
t
Data to Pad High
7.9
6.4
9.2
7.2
10.4
8.2
12.2
9.8
17.7
14.2
13.4
18.5
22.4
20.2
ns
ns
ns
ns
ns
ns
DLH
Data to Pad Low
DHL
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
Delta Low to High
Delta High to Low
6.0
6.9
7.9
9.2
ENZH
ENZL
ENHZ
ENLZ
8.3
9.4
10.7
13.1
11.8
0.13
0.08
12.7
15.4
13.9
0.15
0.09
10.0
9.0
11.6
10.4
0.11
0.07
d
d
0.10
0.06
0.22 ns/pF
0.13 ns/pF
TLH
THL
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125.
1 -2 9 9
P a c k a g e P i n A s s i g n m e n t s
4 4 -P in P LC C
6 8 -P in P LC C
1 68
1 44
68-Pin
PLCC
44-Pin
PLCC
A1010B, A10V10B A1020B, A10V20B
A1010B
Function
A1020B
Function
Signal
Function
Functions
Signal
4
VCC
VCC
3
VCC
VCC
14
15
21
25
32
38
49
52
54
55
56
57
58
59
66
GND
GND
10
14
16
21
25
32
33
34
35
36
37
38
39
43
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
VCC
VCC
VCC
VCC
GND
GND
GND
GND
CLK, I/O
MODE
VCC
CLK, I/O
MODE
VCC
CLK, I/O
MODE
VCC
CLK, I/O
MODE
VCC
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
GND
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
GND
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
GND
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
GND
Notes:
1. NC: Denotes No Connection
2. All unlisted pin numbers are user I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.
1 -3 0 0
™
A C T
1 S e r i e s F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
8 4 -P in P LC C
1 84
A1020B
84-Pin
PLCC
A1020B, A10V20B
Function
Signal
4
VCC
12
18
19
25
26
33
40
46
60
61
64
66
67
68
72
73
74
75
82
NC
GND
GND
VCC
VCC
VCC
GND
VCC
GND
GND
CLK, I/O
MODE
VCC
VCC
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
GND
Notes:
1. NC: Denotes No Connection
2. All unlisted pin numbers are user I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.
1 -3 0 1
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
1 0 0 -P in P Q F P
100-Pin
PQFP
100
1
A1010B
Function
A1020B
Function
A1010B
Function
A1020B
Function
Pin
Pin
1
NC
NC
53
54
55
56
63
69
77
78
79
80
81
82
86
87
90
92
93
94
95
96
97
98
99
100
NC
NC
2
NC
NC
NC
NC
3
NC
NC
NC
NC
4
NC
NC
VCC
GND
VCC
NC
VCC
GND
VCC
NC
5
NC
NC
6
PRB, I/O
GND
VCC
NC
PRB, I/O
GND
VCC
NC
13
19
27
28
29
30
31
32
33
36
37
43
44
48
49
50
51
52
NC
NC
NC
NC
NC
NC
NC
I/O
NC
NC
NC
I/O
NC
NC
NC
I/O
NC
I/O
GND
GND
CLK, I/O
MODE
VCC
VCC
NC
GND
GND
CLK, I/O
MODE
VCC
VCC
I/O
NC
I/O
NC
I/O
GND
GND
VCC
VCC
NC
GND
GND
VCC
VCC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
SDI, I/O
DCLK, I/O
PRA, I/O
NC
NC
NC
NC
Notes:
1. NC: Denotes No Connection
2. All unlisted pin numbers are user I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.
1 -3 0 2
™
A C T
1 S e r i e s F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
8 0 -P in VQ F P
80
1
80-Pin
VQFP
A1010B, A10V10B
Function
A1020B, A10V20B
Function
A1010B, A10V10B
Function
A1020B, A10V20B
Function
Pin
Pin
2
NC
I/O
47
50
52
53
54
55
56
57
58
59
60
61
68
74
GND
GND
3
NC
I/O
CLK, I/O
MODE
VCC
CLK, I/O
MODE
VCC
4
NC
I/O
7
GND
VCC
NC
GND
VCC
I/O
13
17
18
19
20
27
33
41
42
43
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
SDI, I/O
DCLK, I/O
PRA, I/O
NC
SDI, I/O
DCLK, I/O
PRA, I/O
NC
VCC
GND
VCC
NC
VCC
GND
VCC
I/O
PRB, I/O
GND
PRB, I/O
GND
NC
I/O
NC
I/O
VCC
VCC
Notes:
1. NC: Denotes No Connection
2. All unlisted pin numbers are user I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.
1 -3 0 3
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
8 4 -P in C P G A
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
G
H
J
84-Pin
CPGA
K
L
Orientation Pin (C3)
Pin
A1010B Function A1020B Function
Pin
A1010B Function A1020B Function
A11
B1
PRA, I/O
NC
PRA, I/O
I/O
E10
E11
F1
VCC
MODE
VCC
CLK, I/O
GND
VCC
GND
NC
VCC
MODE
VCC
CLK, I/O
GND
VCC
GND
I/O
B2
NC
NC
B5
VCC
GND
PRB, I/O
SDI, I/O
NC
VCC
GND
PRB, I/O
SDI,I/O
I/O
F9
B7
F10
G2
G10
J2
B10
B11
C1
C2
NC
I/O
J10
K1
NC
I/O
C10
C11
D10
D11
E2
DCLK, I/O
NC
DCLK, I/O
I/O
NC
I/O
K2
VCC
GND
VCC
NC
VCC
GND
VCC
I/O
NC
I/O
K5
NC
I/O
K7
GND
GND
VCC
GND
GND
VCC
K10
K11
L1
E3
NC
I/O
E9
NC
I/O
Notes:
1. NC: Denotes No Connection
2. All unlisted pin numbers are user I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.
1 -3 0 4
™
A C T
1 S e r i e s F P G A s
P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )
8 4 -P in C Q F P
84
Pin #1
Index
1
84-Pin
CQFP
Pin
A1020B Function
Pin
A1020B Function
1
NC
53
55
56
57
61
62
63
64
71
77
CLK, I/O
MODE
VCC
7
GND
GND
VCC
VCC
VCC
GND
VCC
GND
GND
8
14
15
22
29
35
49
50
VCC
SDI, I/O
DCLK, I/O
PRA, I/O
PRB, I/O
GND
VCC
Notes:
1. NC: Denotes No Connection
2. All unlisted pin numbers are user I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.
1 -3 0 5
1 -3 0 6
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