A1440AA-1PL208B_技术文档

Accelerator Series FPGAs

– ACT^™3 Family

F e a t u r e s

• Replaces up to twenty 32 macro-cell CPLDs

• Replaces up to one hundred 20-pin PAL^®Packages

• Up to 1153 Dedicated Flip-Flops

• Up to 10,000 Gate Array Equivalent Gates

(up to 25,000 equivalent PLD Gates)

• Highly Predictable Performance with 100% Automatic

Placement and Routing

• VQFP, TQFP, BGA, and PQFP Packages

• Nonvolatile, User Programmable

• 7.5 ns Clock-to-Output Times

• Fully Tested Prior to Shipment

• Up to 250 MHz On-Chip Performance

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock Networks

• More than 500 Macro Functions

• 5.0V and 3.3V Versions

• Optimized for Logic Synthesis Methodologies

• Low-power CMOS Technology

Device

A1415

A1425

A1440

A1460

A14100

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages (40 gates)

20-Pin PAL Equivalent Packages (100 gates)

1,500

3,750

40

2,500

6,250

60

4,000

10,000

100

6,000

15,000

150

10,000

25,000

250

15

25

40

60

100

Logic Modules

S-Module

C-Module

200

104

96

310

160

150

564

288

276

848

432

416

1,377

697

680

1

Dedicated Flip-Flops

264

80

360

100

568

140

768

168

1,153

228

User I/Os (maximum)

2

Packages (by pin count)

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

100

84

100

—

100

—

133

84

100, 160

—

175

84

160

—

100

176

—

207

—

160, 208

—

257

—

208

—

100

—

132

—

176

225

196

313

256

CQFP

—

3

Performance (maximum, worst-case commercial)

4

Chip-to-Chip

108 MHz

63 MHz

110 MHz

250 MHz

7.5 ns

108 MHz

63 MHz

110 MHz

250 MHz

7.5 ns

100 MHz

63 MHz

110 MHz

250 MHz

8.5 ns

97 MHz

63 MHz

110 MHz

200 MHz

9.0 ns

93 MHz

63 MHz

105 MHz

200 MHz

9.5 ns

Accumulators (16-bit)

Loadable Counter (16-bit)

Prescaled Loadable Counters (16-bit)

Datapath, Shift Registers

Clock-to-Output (pad-to-pad)

Notes:

1. One flip-flop per S-Module, two flip-flops per I/O-Module.

2. See product plan on page 1-178 for package availability.

3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3.

4. Clock-to-Output + Setup

S e p t e m b e r 1 9 9 7

1 -1 7 5

D e s c r i p t i o n

The ACT 3 family is supported by Actel’s Designer Series

Development System which offers automatic placement and

routing (with automatic or fixed pin assignments), static

timing anlaysis, user programming, and debug and diagnostic

probe capabilities. The Designer Series is supported on the

following platforms: 486/Pentium class PC’s, Sun^®‚ and HP^®‚

workstations. The software provides CAE interfaces to

Cadence, Mentor Graphics^®, OrCAD^™and Viewlogic^®‚

design environments. Additional platforms are supported

through Actel’s Industry Alliance Program, including DATA

I/O (ABEL FPGA) and MINC.

Actel’s ACT 3 Accelerator Series of FPGAs offers the

industry’s fastest high-capacity programmable logic device.

ACT 3 FPGAs offer a high perfomance, PCI compliant

programmable solution capable of 250 MHz on-chip

performance and 7.5 nanosecond clock-to-output, with

capacities spanning from 1,500 to 10,000 gate array

equivalent gates. For further information regarding PCI

compliance of ACT 3 devices, see “Accelerator Series

FPGAs—ACT 3 PCI Compliant Family.”

The ACT 3 family builds on the proven two-module

architecture consisting of combinatorial and sequential logic

modules used in Actel’s 3200DX and 1200XL families. In

addition, the ACT 3 I/O modules contain registers which

deliver 7.5 nanosecond clock-to-out times. The devices

contain four clock distribution networks, including dedicated

array and I/O clocks, supporting very fast synchronous and

asynchronous designs. In addition, routed clocks can be used

to drive high fanout signals such as flip-flop resets and output

enables.

Predictable Performance* (Worst-Case Commercial)

Accumulators (16-bit)

63 MHz

Loadable Counters (16-bit)

110 MHz

Prescaled Loadable Counters (16-bit)

Shift Registers

250 MHz

S y s t e m P e r f o r m a n c e M o d e l

Chip #1

Chip #2

I/O Module

35 pF

I/O CLK

t

INSU

CKHS

TRACE

Chip-to-Chip Performance

(Worst-Case Commercial)

t

Total

MHz

97

CKHS

TRACE

INSU

A1425A-3

A1460A-3

7.5

1.0

1.8

10.3 ns

11.3 ns

9.0

1.0

1.3

88

1 -1 7 6

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

O r d e r i n g I n f o r m a t i o n

A14100

A

–

RQ

208

C

Application (Temperature Range)

C = Commercial (0 to +70°C)

I

= Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

PG = Ceramic Pin Grid Array

PL = Plastic Leaded Chip Carrier

PQ = Plastic Quad Flatpack

RQ = Plastic Power Quad Flatpack

VQ = Very Thin (1.0 mm) Quad Flatpack

TQ = Thin (1.4 mm) Quad Flatpack

CQ = Ceramic Quad Flatpack

BG = Plastic Ball Grid Array

Speed Grade

Std = Standard Speed

–1 = Approximately 15% faster than Standard

–2 = Approximately 25% faster than Standard

–3 = Approximately 35% faster than Standard

Die Revision

Part Number

A1415A = 1500 Gates

A14V15A = 1500 Gates (3.3V)

A1425A = 2500 Gates

A14V25A = 2500 Gates (3.3V)

A1440A = 4000 Gates

A14V40A = 4000 Gates (3.3V)

A1460A = 6000 Gates

A14V60A = 6000 Gates (3.3V)

A14100A = 10000 Gates

A14V100A = 10000 Gates (3.3V)

1 -1 7 7

P r o d u c t P l a n

Speed Grade*

Application

M

Std

–1

–2

–3

C

I

B

A1415A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

100-pin Very Thin Quad Flatpack (VQFP)

100-pin Ceramic Pin Grid Array (CPGA)

✔

—

A14V15A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Quad Flatpack (VQFP)

✔

—

✔

—

A1425A Device

—

✔

—

✔

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

100-pin Very Thin Quad Flatpack (VQFP)

132-pin Ceramic Quad Flatpack (CQFP)

133-pin Ceramic Pin Grid Array (CPGA)

160-pin Plastic Quad Flatpack (PQFP)

✔

—

✔†

✔

—

✔†

✔

—

✔

—

A14V25A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Quad Flatpack (VQFP)

160-pin Plastic Quad Flatpack (PQFP)

✔

—

✔

—

A1440A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Quad Flatpack (VQFP)

160-pin Plastic Quad Flatpack (PQFP)

175-pin Ceramic Pin Grid Array (CPGA)

176-pin Thin Quad Flatpack (TQFP)

✔

—

✔

—

A14V40A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Quad Flatpack (VQFP)

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Quad Flatpack (TQFP)

✔

—

✔

—

A1460A Device

✔

—

✔†

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Quad Flatpack (TQFP)

196-pin Ceramic Quad Flatpack (CQFP)

207-pin Ceramic Pin Grid Array (CPGA)

208-pin Plastic Quad Flatpack (PQFP)

225-pin Platic Ball Grid Array (BGA)

✔

P

—

P†

P

✔

—

✔

—

✔

—

✔

—

✔

P

—

Applications: C = Commercial

= Industrial

Availability: ✔ = Available

= Planned

— = Not Planned

* Speed Grade: –1 = Approx. 15% faster than Standard

–2 = Approx. 25% faster than Standard

I

P

M = Military

–3 = Approx. 35 % faster than Standard.

B = MIL-STD-883

† Commercial Only

1 -1 7 8

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

P r o d u c t P l a n (c o n t in u e d )

Speed Grade*

Application

M

Std

–1

–2

–3

C

I

B

A14V60A Device

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Quad Flatpack (TQFP)

208-pin Plastic Quad Flatpack (PQFP)

✔

—

✔

—

A14100A Device

208-pin Power Quad Flatpack (RQFP)

257-pin Ceramic Pin Grid Array (CPGA)

313-pin Plastic Ball Grid Array (BGA)

256-pin Ceramic Quad Flatpack (CQFP)

✔

✔†

✔

✔†

✔

—

✔

—

✔

—

✔

—

✔

—

A14V100A Device

208-pin Power Quad Flatpack (RQFP)

313-pin Plastic Ball Grid Array (BGA)

✔

—

✔

—

Applications: C = Commercial

= Industrial

Availability: ✔ = Available

= Planned

— = Not Planned

* Speed Grade: –1 = Approx. 15% faster than Standard

–2 = Approx. 25% faster than Standard

I

P

M = Military

–3 = Approx. 35 % faster than Standard.

B = MIL-STD-883

† Commercial Only

P l a s t i c D e v i c e R e s o u r c e s

User I/Os

PLCC

84-pin

PQFP, RQFP

VQFP

TQFP

BGA

Device

Series

Logic

Modules

Gates

100-pin 160-pin 208-pin 100-pin 176-pin 225-pin 313-pin

A1415

A1425

A1440

A1460

A14100

200

310

1500

2500

4000

6000

10000

70

—

80

—

100

131

—

80

83

—

564

—

140

151

—

848

167

175

168

—

1377

228

1 -1 7 9

H e r m e t i c D e v i c e R e s o u r c e s

User I/Os

CPGA

CQFP

Device

Series

Logic

Modules

Gates

100-pin 133-pin 175-pin 207-pin 257-pin 132-pin 196-pin 256-pin

A1415

A1425

A1440

A1460

A14100

200

310

1500

2500

4000

6000

10000

80

—

100

—

100

—

564

140

—

848

—

168

—

168

—

1377

—

228

—

228

P i n D e s c r i p t i o n

function as I/Os. To provide Actionprobe capability, the

MODE pin should be terminated to GND through a 10K

resistor so that the MODE pin can be pulled high when

required.

C LK A

C lo c k A (In p u t )

Clock input for clock distribution networks. The Clock input

is buffered prior to clocking the logic modules. This pin can

also be used as an I/O.

N C

N o C o n n e c t io n

This pin is not connected to circuitry within the device.

C LK B

C lo c k B (In p u t )

P R A

P r o b e A (O u t p u t )

Clock input for clock distribution networks. The Clock input

is buffered prior to clocking the logic modules. This pin can

also be used as an I/O.

The Probe A pin is used to output data from any user-defined

design node within the device. This independent diagnostic

pin can be used in conjunction with the Probe B pin to allow

real-time diagnostic output of any signal path within the

device. The Probe A pin can be used as a user-defined I/O

when debugging has been completed. The pin’s probe

capabilities can be permanently disabled to protect

programmed design confidentiality. PRA is accessible when

the MODE pin is HIGH. This pin functions as an I/O when the

MODE pin is LOW.

G N D

G r o u n d

LOW supply voltage.

H C LK

De d ic a t e d (H a r d -w ir e d )

Ar r a y C lo c k (In p u t )

Clock input for sequential modules. This input is directly

wired to each S-Module and offers clock speeds independent

of the number of S-Modules being driven. This pin can also be

used as an I/O.

P R B

P r o b e B (O u t p u t )

I/O

In p u t /O u t p u t (In p u t , O u t p u t )

The Probe B pin is used to output data from any user-defined

design node within the device. This independent diagnostic

pin can be used in conjunction with the Probe A pin to allow

real-time diagnostic output of any signal path within the

device. The Probe B pin can be used as a user-defined I/O

when debugging has been completed. The pin’s probe

capabilities can be permanently disabled to protect

programmed design confidentiality. PRB is accessible when

the MODE pin is HIGH. This pin functions as an I/O when the

MODE pin is LOW.

The I/O pin functions as an input, output, three-state, or

bidirectional buffer. Input and output levels are compatible

with standard TTL and CMOS specifications. Unused I/O pins

are tristated by the Designer Series software.

IO C LK

De d ic a t e d (H a r d -w ir e d )

I/O C lo c k (In p u t )

Clock input for I/O modules. This input is directly wired to

each I/O module and offers clock speeds independent of the

number of I/O modules being driven. This pin can also be

used as an I/O.

S DI

S e r ia l Da t a In p u t (In p u t )

IO P C L

De d ic a t e d (H a r d -w ir e d )

I/O P r e s e t /C le a r (In p u t )

Serial data input for diagnostic probe and device

programming. SDI is active when the MODE pin is HIGH. This

pin functions as an I/O when the MODE pin is LOW.

Input for I/O preset or clear. This global input is directly

wired to the preset and clear inputs of all I/O registers. This

pin functions as an I/O when no I/O preset or clear macros

are used.

DC LK

Dia g n o s t ic C lo c k (In p u t )

Clock input for diagnostic probe and device programming.

DCLK is active when the MODE pin is HIGH. This pin

functions as an I/O when the MODE pin is LOW.

MO DE

Mo d e (In p u t )

The MODE pin controls the use of diagnostic pins (DCLK,

PRA, PRB, SDI). When the MODE pin is HIGH, the special

functions are active. When the MODE pin is LOW, the pins

V

5 V S u p p ly Vo lt a g e

C C

HIGH supply voltage.

1 -1 8 0

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A r c h i t e c t u r e

Logic Modules

This section of the data sheet is meant to familiarize the user

with the architecture of the ACT 3 family of FPGA devices. A

generic description of the family will be presented first,

followed by a detailed description of the logic blocks, the

routing structure, the antifuses, and the special function

circuits. The on-chip circuitry required to program the

devices is not covered.

ACT 3 logic modules are enhanced versions of the 1200XL

family logic modules. As in the 1200XL family, there are two

types of modules: C-modules and S-modules. The C-module is

functionally equivalent to the 1200XL C-module and

implements high fanin combinatorial macros, such as 5-input

AND, 5-input OR, and so on. It is available for use as the CM8

hard macro. The S-module is designed to implement

high-speed sequential functions within a single module.

S-modules consist of a full C-module driving a flip-flop, which

allows an additional level of logic to be implemented without

additional propagation delay. It is available for use as the

DFM8A/B and DLM8A/B hard macros. C-modules and

S-modules are arranged in pairs called module-pairs.

Module-pairs are arranged in alternating patterns and make

up the bulk of the array. This arrangement allows the

placement software to support two-module macros of four

types (CC, CS, SC, and SS). The C-module implements the

following function:

T o p o lo g y

The ACT 3 family architecture is composed of six key

elements: Logic modules, I/O modules, I/O Pad Drivers,

Routing Tracks, Clock Networks, and Programming and Test

Circuits. The basic structure is similar for all devices in the

family, differing only in the number of rows, columns, and

I/Os. The array itself consists of alternating rows of modules

and channels. The logic modules and channels are in the

center of the array; the I/O modules are located along the

array periphery. A simplified floor plan is depicted in

Figure 1.

Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0

* D11

where: S0 = A0 * B0 and S1 = A1 + B1

An Array with n rows and m columns

c–1 c+1

0

1

2

3

4

5

c

m m+1 m+2 m+3

Columns

Rows

n+1

Channels

n+2

IO IO IO IO IO IO

Top I/Os

IO IO IO CLKM

n+1

n

IO IO BIN S

S

C

S

C

S

C

S

IO IO

n

IO IO

n–1

•

n–1

•

2

IO IO

IO IO BIN S

Left I/Os

1

0

1

0

Right I/Os

Bottom I/Os

BIO IO IO IO IO IO

IO IO IO IO IO IO

Figure 1 • Generalized Floor Plan of ACT 3 Device

1 -1 8 1

The S-module contains a full implementation of the C-module

plus a clearable sequential element that can either

implement a latch or flip-flop function. The S-module can

therefore implement any function implemented by the

C-module. This allows complex combinatorial-sequential

functions to be implemented with no delay penalty. The

Designer Series Development System will automatically

combine any C-module macro driving an S-module macro into

the S-module, thereby freeing up a logic module and

eliminating a module delay.

D00

D01

D10

OUT

Y

D11

S1

S0

The clear input CLR is accessible from the routing channel.

In addition, the clock input may be connected to one of three

clock networks: CLKA, CLKB, or HCLK. The C-module and

S-module functional descriptions are shown in Figures 2

and 3. The clock selection is determined by a multiplexor

select at the clock input to the S-module.

A1 B1

A0 B0

I/O s

Figure 2 • C-Module Diagram

I/O Modules

preset/clear network (IOPCL). Either preset or clear can be

selected individually on an I/O module by I/O module basis.

I/O modules provide an interface between the array and the

I/O Pad Drivers. I/O modules are located in the array and

access the routing channels in a similar fashion to logic

modules. The I/O module schematic is shown in Figure 4. The

signals DataIn and DataOut connect to the I/O pad driver.

Each I/O module contains two D-type flip-flops. Each flip-flop

is connected to the dedicated I/O clock (IOCLK). Each

flip-flop can be bypassed by nonsequential I/Os. In addition,

each flip-flop contains a data enable input that can be

accessed from the routing channels (ODE and IDE). The

asynchronous preset/clear input is driven by the dedicated

The I/O module output Y is used to bring Pad signals into the

array or to feed the output register back into the array. This

allows the output register to be used in high-speed state

machine applications. Side I/O modules have a dedicated

output segment for Y extending into the routing channels

above and below (similar to logic modules). Top/Bottom I/O

modules have no dedicated output segment. Signals coming

into the chip from the top or bottom are routed using F-fuses

and LVTs (F-fuses and LVTs are explained in detail in the

routing section).

D00

D01

Y

D

Q

OUT

D10

D11

S1

S0

CLK

CLR

A1 B1

A0 B0

Figure 3 • S-Module Diagram

1 -1 8 2

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

0

MUX

DATAOUT

D

0

1

MUX

Q

D

1

CLR/PRE

ODE

0

1

2

3

S0

S1

Y

MUX

1

MUX

D

Q

0

DATAIN

CLR/PRE

IOPCL

IOCLK

Figure 4 • Functional Diagram for I/O Module

I/O Pad Drivers

buffer (IOPCL). Their function is determined by the I/O

macros selected.

All pad drivers are capable of being tristate. Each buffer

connects to an associated I/O module with four signals: OE

(Output Enable), IE (Input Enable), DataOut, and DataIn.

Certain special signals used only during programming and

test also connect to the pad drivers: OUTEN (global output

enable), INEN (global input enable), and SLEW (individual

slew selection). See Figure 5.

C lo c k N e t w o r k s

The ACT 3 architecture contains four clock networks: two

high-performance dedicated clock networks and two general

purpose routed networks. The high-performance networks

function up to 200 MHz, while the general purpose routed

networks function up to 150 MHz.

Special I/Os

Dedicated Clocks

The special I/Os are of two types: temporary and permanent.

Temporary special I/Os are used during programming and

testing. They function as normal I/Os when the MODE pin is

inactive. Permanent special I/Os are user programmed as

either normal I/Os or special I/Os. Their function does not

change once the device has been programmed. The

permanent special I/Os consist of the array clock input

buffers (CLKA and CLKB), the hard-wired array clock input

buffer (HCLK), the hard-wired I/O clock input buffer

(IOCLK), and the hard-wired I/O register preset/clear input

Dedicated clock networks support high performance by

providing sub-nanosecond skew and guaranteed

performance. Dedicated clock networks contain no

programming elements in the path from the I/O Pad Driver to

the input of S-modules or I/O modules. There are two

dedicated clock networks: one for the array registers (HCLK),

and one for the I/O registers (IOCLK). The clock networks

are accessed by special I/Os.

1 -1 8 3

CLKB

CLKA

CLKINB

CLKINA

OE

SLEW

FROM

PADS

S0

S1

INTERNAL

SIGNAL

CLKMOD

DATAOUT

CLKO(17)

CLKO(16)

CLKO(15)

CLOCK

DRIVERS

PAD

DATAIN

IEN

CLKO(2)

CLKO(1)

CLOCK TRACKS

INEN

OUTEN

Figure 6 • Clock Networks

R o u t i n g S t r u c t u r e

The ACT 3 architecture uses vertical and horizontal routing

tracks to connect the various logic and I/O modules. These

routing tracks are metal interconnects that may either be of

continuous length or broken into segments. Segments can be

joined together at the ends using antifuses to increase their

lengths up to the full length of the track.

Figure 5 • Function Diagram for I/O Pad Driver

Routed Clocks

The routed clock networks are referred to as CLK0 and CLK1.

Each network is connected to a clock module (CLKMOD)

that selects the source of the clock signal and may be driven

as follows (see Figure 6):

H o r iz o n t a l R o u t in g

• externally from the CLKA pad

• externally from the CLKB pad

• internally from the CLKINA input

• internally from the CLKINB input

Horizontal channels are located between the rows of modules

and are composed of several routing tracks. The horizontal

routing tracks within the channel are divided into one or

more segments. The minimum horizontal segment length is

the width of a module-pair, and the maximum horizontal

segment length is the full length of the channel. Any segment

that spans more than one-third the row length is considered a

long horizontal segment. A typical channel is shown in

Figure 7. Undedicated horizontal routing tracks are used to

route signal nets. Dedicated routing tracks are used for the

global clock networks and for power and ground tie-off tracks.

The clock modules are located in the top row of I/O modules.

Clock drivers and a dedicated horizontal clock track are

located in each horizontal routing channel. The function of

the clock module is determined by the selection of clock

macros from the macro library. The macro CLKBUF is used to

connect one of the two external clock pins to a clock network,

and the macro CLKINT is used to connect an internally

generated clock signal to a clock network. Since both clock

networks are identical, the user does not care whether CLK0

or CLK1 is being used. Routed clocks can also be used to drive

high fanout nets like resets, output enables, or data enables.

This saves logic modules and results in performance

increases in some cases.

Ve r t ic a l R o u t in g

Other tracks run vertically through the modules. Vertical

tracks are of three types: input, output, and long. Vertical

tracks are also divided into one or more segments. Each

segment in an input track is dedicated to the input of a

particular module. Each segment in an output track is

dedicated to the output of a particular module. Long

segments are uncommitted and can be assigned during

1 -1 8 4

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

routing. Each output segment spans four channels (two above

and two below), except near the top and bottom of the array

where edge effects occur. LVTs contain either one or two

segments. An example of vertical routing tracks and

segments is shown in Figure 8.

MODULE ROW

HCLK

CLK0

NVCC

SIGNAL

TRACK

SIGNAL

(LHT)

SEGMENT

|

HF

SIGNAL

NVSS

CLK1

MODULE ROW

Figure 7 • Horizontal Routing Tracks and Segments

LVTS

MODULE ROW

S-MODULE

C-MODULE

VF

CHANNEL

XF

VERTICLE INPUT

SEGMENT

FF

S-MODULE

C-MODULE

Figure 8 • Vertical Routing Tracks and Segments

1 -1 8 5

An t ifu s e C o n n e c t io n s

or the channel below. The logic modules are arranged such

that half of the inputs are connected to the channel above

and half of the inputs to segments in the channel below as

shown in Figure 9.

An antifuse is a “normally open” structure as opposed to the

normally closed fuse structure used in PROMs or PALs. The

use of antifuses to implement a programmable logic device

results in highly testable structures as well as an efficient

programming architecture. The structure is highly testable

because there are no preexisting connections; temporary

connections can be made using pass transistors. These

temporary connections can isolate individual antifuses to be

programmed as well as isolate individual circuit structures to

be tested. This can be done both before and after

programming. For example, all metal tracks can be tested for

continuity and shorts between adjacent tracks, and the

functionality of all logic modules can be verified.

Module Output Connections

Module outputs have dedicated output segments. Output

segments extend vertically two channels above and two

channels below, except at the top or bottom of the array.

Output segments twist, as shown in Figure 10, so that only

four vertical tracks are required.

LVT Connections

Outputs may also connect to nondedicated segments called

Long Vertical Tracks (LVTs). Each module pair in the array

shares four LVTs that span the length of the column. Any

module in the column pair can connect to one of the LVTs in

the column using an FF connection. The FF connection uses

antifuses connected directly to the driver stage of the module

output, bypassing the isolation transistor. FF antifuses are

programmed at a higher current level than HF, VF, or XF

antifuses to produce a lower resistance value.

Four types of antifuse connections are used in the routing

structure of the ACT 3 array. (The physical structure of the

antifuse is identical in each case; only the usage differs.)

Table 1 shows four types of antifuses.

Table 1 • Antifuse Types

XF

HF

VF

FF

Horizontal-to-Vertical Connection

Horizontal-to-Horizontal Connection

Vertical-to-Vertical Connection

“Fast” Vertical Connection

Antifuse Connections

In general every intersection of a vertical segment and a

horizontal segment contains an unprogrammed antifuse

(XF-type). One exception is in the case of the clock networks.

Examples of all four types of connections are shown in

Figures 7 and 8.

Clock Connections

To minimize loading on the clock networks, a subset of inputs

has antifuses on the clock tracks. Only a few of the C-module

and S-module inputs can be connected to the clock networks.

To further reduce loading on the clock network, only a subset

of the horizontal routing tracks can connect to the clock

inputs of the S-module.

Mo d u le In t e r fa c e

Connections to Logic and I/O modules are made through

vertical segments that connect to the module inputs and

outputs. These vertical segments lie on vertical tracks that

span the entire height of the array.

P r o g r a m m in g a n d T e s t C ir c u it s

Module Input Connections

The tracks dedicated to module inputs are segmented by pass

transistors in each module row. During normal user

operation, the pass transistors are inactive, which isolates the

inputs of a module from the inputs of the module directly

above or below it. During certain test modes, the pass

transistors are active to verify the continuity of the metal

tracks. Vertical input segments span only the channel above

The array of logic and I/O modules is surrounded by test and

programming circuits controlled by the temporary special I/O

pins MODE, SDI, and DCLK. The function of these pins is

similar to all ACT family devices. The ACT 3 family also

includes support for two Actionprobe^®circuits allowing

complete observability of any logic or I/O module in the array

using the temporary special I/O pins, PRA and PRB.

1 -1 8 6

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3

F a m i l y

Y+2

Y+1

Y+2

Y+1

B1 B0

A1 D10 D11

D01 D00

B0

B1 D01

Y

A0

D10

A0 D11 A1

Y-1

Y-2

LVTs

C-MODULES

S-MODULES

Figure 9 • Logic Module Routing Interface

1 -1 8 7

5 V O p e r a t i n g C o n d i t i o n s

R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s

Parameter

Commercial Industrial Military Units

1

A b s o l u t e M a x i m u m R a t i n g s

Temperature

0 to +70

–40 to +85 –55 to

+125

°C

F r e e a ir t e m p e r a t u r e r a n g e

1

Range

Symbol

Parameter

Limits

Units

5V Power

Supply

Tolerance

±5

±10

%V

CC

V

DC Supply Voltage

Input Voltage

–0.5 to +7.0

V

CC

V

–0.5 to V +0.5

I

CC

Note:

Output Voltage

–0.5 to V +0.5

V

1. Ambient temperature (T ) is used for commercial and

O

CC

A

industrial; case temperature (T ) is used for military.

C

I

I/O Source Sink

±20

mA

IO

2

Current

T

Storage Temperature

–65 to +150

°C

STG

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to

absolute maximum rated conditions for extended periods may

affect device reliability. Device should not be operated outside

the Recommended Operating Conditions.

2. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than V + 0.5 V or less than GND – 0.5 V, the internal protection

CC

diodes will forward bias and can draw excessive current.

E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Industrial

Military

Symbol Parameter

Test Condition

Min.

Max.

Min.

3.7

Max.

Min.

3.7

Max.

Units

1,2

V

HIGH Level Output

I

= –4 mA (CMOS)

V

OH

OL

= –6 mA (CMOS) 3.84

3

= –10 mA (TTL) 2.40

V

1,2

V

LOW Level Output

= +6 mA (CMOS)

0.33

0.50

0.4

V

OL

3

= +12 mA (TTL)

V

HIGH Level Input

LOW Level Input

Input Leakage

TTL Inputs

2.0

–0.3

–10

V

+ 0.3 2.0

V

+ 0.3 2.0

V + 0.3

CC

V

IH

IL

CC

0.8

+10

–0.3

–10

0.8

+10

–0.3

–10

0.8

+10

10

V

I

V = V or GND

µA

pF

mA

IN

OZ

I

CC

3-state Output Leakage

V = V or GND

+10

10

2

+10

10

O

CC

3,4

C

I/O Capacitance

IO

I

Standby V Supply Current (typical = 0.7 mA)

10

20

CC(S)

CC(D)

CC

Dynamic V Supply Current See “Power Dissipation” Section

CC

Notes:

1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required.

2. Tested one output at a time, V = min.

CC

3. Not tested, for information only.

4.

V

= 0V, f = 1 MHz.

OUT

5. Typical standby current = 0.7 mA. All outputs unloaded. All inputs = V or GND.

CC

1 -1 8 8

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

3 . 3 V O p e r a t i n g C o n d i t i o n s

R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s

1

Parameter

Commercial

Units

A b s o l u t e M a x i m u m R a t i n g s

1

Temperature Range

0 to +70

°C

F r e e a ir t e m p e r a t u r e r a n g e

Power Supply Tolerance

3.0 to 3.6

V

Symbol

Parameter

Limits

Units

Note:

V

DC Supply Voltage

Input Voltage

–0.5 to +7.0

V

1. Ambient temperature (T ) is used for commercial.

CC

A

V

–0.5 to V +0.5

CC

I

V

Output Voltage

–0.5 to V +0.5

O

CC

I/O Source Sink

I

±20

mA

IO

2

Current

T

Storage Temperature

–65 to +150

°C

STG

Notes:

1. Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. Exposure

to absolute maximum rated conditions for extended periods

may affect device reliability. Device should not be operated

outside the Recommended Operating Conditions.

2. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than V + 0.5 V or less than GND – 0.5 V, the internal

CC

protection diodes will forward bias and can draw excessive

current.

E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Parameter

Units

Min.

Max.

(I = –4 mA)

2.15

2.4

V

OH

1

V

OH

(I = –3.2 mA)

OH

1

V

(I = 6 mA)

0.4

0.8

V

OL

–0.3

2.0

V

IL

V

+ 0.3

V

IH

CC

2

Input Transition Time t , t

500

10

ns

pF

mA

µA

R

F

2, 3

C

I/O Capacitance

IO

4

Standby Current, I

(typical = 0.3 mA)

0.75

10

CC

5

Leakage Current

–10

Notes:

1. Only one output tested at a time. V = min.

CC

2. Not tested, for information only.

3. Includes worst-case 84-pin PLCC package capacitance. V = 0 V, f = 1 MHz.

OUT

4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = V or GND.

CC

5. V , V = V or GND.

O

IN

CC

1 -1 8 9

P a c k a g e T h e r m a l C h a r a c t e r i s t i c s

The device junction to case thermal characteristic is θjc, and

the junction to ambient air characteristic is θja. The thermal

characteristics for θja are shown with two different air flow

rates.

Maximum junction temperature is 150°C.

A sample calculation of the absolute maximum power

dissipation allowed for a CPGA 175-pin package at

commercial temperature and still air is as follows:

Max. junction temp. (°C) – Max. ambient temp. (°C)

Absolute Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 3.2 W

θja (°C/W) 25°C/W

150°C – 70°C

θja

Still Air

θja

300 ft/min

1

Package Type

Pin Count

θjc

Units

Ceramic Pin Grid Array

100

133

175

207

257

20

35

30

25

22

15

17

15

14

13

8

°C/W

Ceramic Quad Flatpack

Plastic Quad Flatpack

132

196

256

13

55

36

30

24

18

°C/W

100

160

208

13

10

51

33

40

26

°C/W

Very Thin Quad Flatpack

Thin Quad Flatpack

100

176

208

84

12

11

0.4

12

43

32

17

37

35

25

13

28

°C/W

Power Quad Flatpack

Plastic Leaded Chip Carrier

Plastic Ball Grid Array

225

313

10

25

23

19

17

Note:

1. Maximum Power Dissipation in Still Air for 160-pin PQFP package is 2.4 Watts, 208-pin PQFP package is 2.4 Watts, 100-pin PQFP package

is 1.6 Watts, 100-pin VQFP package is 1.9 Watts, 176-pin TQFP package is 2.5 Watts, 84-pin PLCC package is 2.2 Watts, 208-pin RQFP

package is 4.7 Watts, 225-pin BGA package is 3.2 Watts, 313-pin BGA package is 3.5 Watts.

S t a t ic P o w e r C o m p o n e n t

P o w e r D i s s i p a t i o n

P = [I_{CC standby}+ I_active] * V + I_OL* V * N + I_OH

*

Actel FPGAs have small static power components that result

in lower power dissipation than PALs or PLDs. By integrating

multiple PALs/PLDs into one FPGA, an even greater

reduction in board-level power dissipation can be achieved.

CC

OL

(V – V ) * M

(1)

CC

OH

Where:

I_{CC standby}is the current flowing when no inputs or

outputs are changing.

The power due to standby current is typically a small

component of the overall power. Standby power is calculated

below for commercial, worst case conditions.

I_activeis the current flowing due to CMOS switching.

I_OL, I_OHare TTL sink/source currents.

I_CC

V

Power

10.5 mW

CC

V , V_OHare TTL level output voltages.

OL

2mA

5.25 V

N equals the number of outputs driving TTL loads to

The static power dissipated by TTL loads depends on the

number of outputs driving high or low and the DC load

current. Again, this value is typically small. For instance, a

32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all

outputs driving low, and 140 mW with all outputs driving high.

The actual dissipation will average somewhere between as

I/Os switch states with time.

V .

OL

M equals the number of outputs driving TTL loads to

V .

OH

An accurate determination of N and M is problematical

because their values depend on the design and on the system

I/O. The power can be divided into two components: static

and active.

1 -1 9 0

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

Ac t iv e P o w e r C o m p o n e n t

Where:

Power dissipation in CMOS devices is usually dominated by

the active (dynamic) power dissipation. This component is

frequency dependent, a function of the logic and the external

I/O. Active power dissipation results from charging internal

chip capacitances of the interconnect, unprogrammed

antifuses, module inputs, and module outputs, plus external

capacitance due to PC board traces and load device inputs.

An additional component of the active power dissipation is

the totem-pole current in CMOS transistor pairs. The net

effect can be associated with an equivalent capacitance that

can be combined with frequency and voltage to represent

active power dissipation.

m

n

= Number of logic modules switching at f_m

= Number of input buffers switching at f_n

= Number of output buffers switching at f_p

= Number of clock loads on the first routed

array clock

p

q₁

q₂

r₁

r₂

s₁

s₂

= Number of clock loads on the second routed

array clock

= Fixed capacitance due to first routed array

clock

= Fixed capacitance due to second routed array

clock

= Fixed number of clock loads on the dedicated

array clock

E q u iv a le n t C a p a c it a n c e

The power dissipated by a CMOS circuit can be expressed by

the Equation 2.

= Fixed number of clock loads on the dedicated

I/O clock

Power (uW) = C_EQ* V ²* F

(2)

CC

C_EQM= Equivalent capacitance of logic modules in pF

C_EQI= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in

pF

Where:

C_EQis the equivalent capacitance expressed in pF.

V is the power supply in volts.

CC

C_EQCR= Equivalent capacitance of routed array clock

in pF

F is the switching frequency in MHz.

Equivalent capacitance is calculated by measuring I_CCactive

at a specified frequency and voltage for each circuit

component of interest. Measurements have been made over a

C_EQCD= Equivalent capacitance of dedicated array

clock in pF

C_EQCI= Equivalent capacitance of dedicated I/O clock

in pF

range of frequencies at a fixed value of V . Equivalent

CC

capacitance is frequency independent so that the results may

be used over a wide range of operating conditions. Equivalent

capacitance values are shown below.

C_L

f_m

f_n

= Output lead capacitance in pF

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

C

Va lu e s fo r Ac t e l F P G As

E Q

fp

Modules (C_EQM

Input Buffers (_CEQI

Output Buffers (C_EQO

Routed Array Clock Buffer Loads (C_EQCR

Dedicated Clock Buffer Loads (C_EQCD

I/O Clock Buffer Loads (C_EQCI

)

6.7

7.2

f_q1

f_q2

)

= Average second routed array clock rate in

MHz

)

10.4

1.6

)

f_s1

f_s2

= Average dedicated array clock rate in MHz

= Average dedicated I/O clock rate in MHz

)

0.7

)

0.9

To calculate the active power dissipated from the complete

design, the switching frequency of each part of the logic must

be known. Equation 3 shows a piece-wise linear summation

over all components.

Power =V 2 * [(m * C_EQM* f_m)_modules+ (n * C_EQI* f_n)_inputs

CC

+ (p * (C_EQO+ C_L) * f_p)_outputs

+ 0.5 * (q₁* C_EQCR* f_q1)_{routed_Clk1}+ (r₁* f_q1)_{routed_Clk1}

+ 0.5 * (q₂* C_EQCR* f_q2)_{routed_Clk2}

+ (r₂* f_q2)_{routed_Clk2}+ 0.5 * (s₁* _CEQCD* f_s1)_{dedicated_Clk}

+ (s₂* CEQCI * f_s2)_{IO_Clk}

]

(3)

1 -1 9 1

F ix e d C a p a c it a n c e Va lu e s fo r Ac t e l F P G As

(p F )

De t e r m in in g Av e r a g e S w it c h in g F r e q u e n c y

To determine the switching frequency for a design, you must

have a detailed understanding of the data input values to the

circuit. The following guidelines are meant to represent

worst-case scenarios so that they can be generally used to

predict the upper limits of power dissipation. These

guidelines are as follows:

r₁

routed_Clk1

60

r₂

routed_Clk2

60

Device Type

A1415A

A14V15A

A1425A

57

75

Logic Modules (m)

= 80% of modules

= # inputs/4

A14V25A

A1440A

72

Inputs switching (n)

105

Outputs switching (p)

First routed array clock loads (q₁)

= # output/4

A14V40A

A1440B

100

= 40% of

sequential

modules

105

A1460A

165

A14V60A

A1460B

157

Second routed array clock loads (q₂) = 40% of

sequential

modules

= 35 pF

165

A14100A

A14V100A

A14100B

195

185

Load capacitance (C_L)

195

Average logic module switching rate = F/10

(f_m)

F ix e d C lo c k Lo a d s (s /s

)

2

1

Average input switching rate (f_n)

Average output switching rate (f_p)

Average first routed array clock rate = F/2

(f_q1)

Average second routed array clock rate = F/2

(f_q2)

Average dedicated array clock rate = F

(f_s1)

= F/5

s₁

s₂

= F/10

Clock Loads on

Device Type

dedicated array

clock

dedicated I/O

clock

A1415A

A14V15A

A1425A

A14V25A

A1440A

A14V40A

A1440B

104

160

288

432

697

80

100

140

168

228

Average dedicated I/O clock rate (f_s2) = F

A1460A

A14V60A

A1460B

A14100A

A14V100A

A14100B

1 -1 9 2

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3

F a m i l y

A C T 3 T i m i n g M o d e l *

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

Combinatorial

Logic Module

I/O Module

t

= 2.8 ns

INY

t

= 1.2 ns

IRD2

t

= 5.0 ns

DHS

t

= 0.9 ns

= 1.7 ns

= 2.8 ns

RD1

D

Q

t

= 2.0 ns

PD

t

RD4

RD8

t

I/O Module

t

= 5.0 ns

DHS

Sequential

Logic Module

t

= 0.0 ns

= 1.8 ns

= 4.7 ns

INH

t

INSU

ICKY

Combin-

atorial

D

Q

t

= 0.9 ns

t

= 4.0 ns

RD1

ENZHS

Logic

included

in t

SUD

t

= 0.7 ns

OUTH

t

OUTSU

t

= 2.0 ns

t

= 0.5 ns

= 0.0 ns

CO

SUD

ARRAY

CLOCK

t

HD

t

= 3.0 ns

HCKH

F

= 250 MHz

HMAX

t

= 7.5 ns

(pad-pad)

CKHS

I/O CLOCK

F

= 250 MHz

IOMAX

*Values shown for A1425A-3.

1 -1 9 3

O u t p u t B u f f e r D e l a y s

E

D

To AC test loads (shown below)

PAD

TRIBUFF

V

CC

In

GND

1.5 V

50%

En

Out

GND

10%

50%

En

GND

90%

50%

CC

50%

V

OH

1.5 V

Out

GND

1.5 V

V

OL

t

ENHSZ,

DHS,

ENZHS,

ENHSZ,

ENZHS,

A C T e s t L o a d s

Load 2

(Used to measure rising/falling edges)

Load 1

(Used to measure propagation delay)

V

GND

CC

To the output under test

35 pF

R to V for t /t

CC

PLZ PZL

R to GND for t

/t

PHZ PZH

R = 1 kΩ

To the output under test

35 pF

I n p u t B u f f e r D e l a y s

M o d u l e D e l a y s

S

Y

A

B

Y

PAD

INBUF

V

CC

GND

S, A or B

50% 50%

3 V

1.5 V

V

CC

In

0 V

50%

1.5 V

50%

Out

50%

V

CC

GND

t

PD

Out

GND

50%

V

Out

CC

GND

50%

t

INY

t

PD

1 -1 9 4

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

S e q u e n t i a l M o d u l e T i m i n g C h a r a c t e r i s t i c s

F lip -F lo p s

D

Q

CLK

CLR

(Positive edge triggered)

t

HD

D

t

A

WCLKA

SUD

CLK

t

WCLKA

t

CO

Q

t

CLR

t

WASYN

I /O M o d u l e : S e q u e n t i a l I n p u t T i m i n g C h a r a c t e r i s t i c s

D

E

Y

PRE

CLR

IOCLK

(Positive edge triggered)

t

INH

D

t

IOP

t

IOPWH

INSU

IOCLK

t

IDESU

IOPWL

IDEH

E

Y

t

ICKY

t

ICLRY

PRE, CLR

t

IOASPW

1 -1 9 5

I /O M o d u l e : S e q u e n t i a l O u t p u t T i m i n g C h a r a c t e r i s t i c s

Q

D

E

PRE

CLR

IOCLK

Y

(Positive edge triggered)

t

OUTH

D

t

IOP

IOPWH

OUTSU

IOCLK

t

ODESU

IOPWL

ODEH

E

Y

t

OCKY

t

CKHS,

tCKLS

Q

t

OCLRY

PRE, CLR

t

IOASPW

1 -1 9 6

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

P r e d i c t a b l e P e r f o r m a n c e :

T i g h t e s t D e l a y D i s t r i b u t i o n s

T i m i n g C h a r a c t e r i s t i c s

Timing characteristics for ACT 3 devices fall into three

categories: family dependent, device dependent, and design

dependent. The input and output buffer characteristics are

common to all ACT 3 family members. Internal routing delays

are device dependent. Design dependency means actual

delays are not determined until after placement and routing

of the user’s design is complete. Delay values may then be

determined by using the ALS Timer utility or performing

simulation with post-layout delays.

Propagation delay between logic modules depends on the

resistive and capacitive loading of the routing tracks, the

interconnect elements, and the module inputs being driven.

Propagation delay increases as the length of routing tracks,

the number of interconnect elements, or the number of

inputs increases.

From a design perspective, the propagation delay can be

statistically correlated or modeled by the fanout (number of

loads) driven by a module. Higher fanout usually requires

some paths to have longer lengths of routing track.

C r it ic a l N e t s a n d T y p ic a l N e t s

Propagation delays are expressed only for typical nets, which

are used for initial design performance evaluation. Critical

net delays can then be applied to the most time-critical

paths. Critical nets are determined by net property

assignment prior to placement and routing. Up to 6% of the

nets in a design may be designated as critical, while 90% of

the nets in a design are typical.

The ACT 3 family delivers the tightest fanout delay

distribution of any FPGA. This tight distribution is achieved

in two ways: by decreasing the delay of the interconnect

elements and by decreasing the number of interconnect

elements per path.

Actel’s patented PLICE antifuse offers a very low

resistive/capacitive interconnect. The ACT 3 family’s

antifuses, fabricated in 0.8 micron m lithography, offer

nominal levels of 200Ω resistance and 6 femtofarad (fF)

capacitance per antifuse.

Lo n g T r a c k s

Some nets in the design use long tracks. Long tracks are

special routing resources that span multiple rows, columns,

or modules. Long tracks employ three and sometimes four

antifuse connections. This increases capacitance and

resistance, resulting in longer net delays for macros

connected to long tracks. Typically up to 6% of nets in a fully

utilized device require long tracks. Long tracks contribute

approximatley 4 ns to 14 ns delay. This additional delay is

represented statistically in higher fanout (FO=8) routing

delays in the data sheet specifications section.

The ACT 3 fanout distribution is also tighter than alternative

devices due to the low number of antifuses required per

interconnect path. The ACT 3 family’s proprietary

architecture limits the number of antifuses per path to only

four, with 90% of interconnects using only two antifuses.

The ACT 3 family’s tight fanout delay distribution offers an

FPGA design environment in which fanout can be traded for

the increased performance of reduced logic level designs.

This also simplifies performance estimates when designing

with ACT 3 devices.

T im in g De r a t in g

ACT 3 devices are manufactured in a CMOS process.

Therefore, device performance varies according to

temperature, voltage, and process variations. Minimum

timing parameters reflect maximum operating voltage,

minimum operating temperature, and best-case processing.

Maximum timing parameters reflect minimum operating

voltage, maximum operating temperature, and worst-case

processing.

Table 2 • Logic Module and Routing Delay by Fanout (ns)

(Worst-Case Commercial Conditions)

Speed

FO=1

FO=2

FO=3

FO=4

FO=8

ACT 3 –3

2.9

3.2

3.4

3.7

4.8

1 -1 9 7

T i m i n g D e r a t i n g F a c t o r ( T e m p e r a t u r e a n d V o l t a g e )

Industrial

Military

Min.

Max.

Min.

Max.

(Commercial Minimum/Maximum Speciﬁcation) x

0.66

1.07

0.63

1.17

T i m i n g D e r a t i n g F a c t o r f o r D e s i g n s a t T y p i c a l T e m p e r a t u r e ( T = 2 5 °C )

J

a n d V o l t a g e ( 5 . 0 V )

(Commercial Maximum Speciﬁcation) x

0.85

T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s

( n o r m a l i z e d t o W o r s t -C a s e C o m m e r c i a l , T = 4 . 7 5 V , 7 0 °C )

J

–55

0.72

0.70

0.68

0.66

0.63

–40

0.76

0.73

0.71

0.69

0.66

0

25

70

85

125

1.17

1.12

1.09

1.06

1.01

4.50

4.75

5.00

5.25

5.50

0.85

0.82

0.79

0.77

0.74

0.90

0.87

0.84

0.82

0.79

1.04

1.00

0.97

0.94

0.90

1.07

1.03

1.00

0.97

0.93

J u n c t io n T e m p e r a t u r e a n d Vo lt a g e De r a t in g C u r v e s

(n o r m a liz e d t o Wo r s t -C a s e C o m m e r c ia l, T = 4 . 7 5 V, 7 0 °C )

J

1.20

1.10

1.00

0.90

0.80

0.70

0.60

4.50

4.75

5.00

5.25

5.50

Voltage (V)

Note: This derating factor applies to all routing and propagation dealys.

1 -1 9 8

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 1 5 A , A 1 4 V 1 5 A T i m i n g C h a r a c t e r i s t i c s

1

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V

= 4 . 7 5 V, T = 7 0 °C )

C C

J

2

1

Logic Module Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Internal Array Module

Sequential Clock to Q

2.0

2.3

2.6

3.0

3.9

ns

PD

CO

CLR

Asynchronous Clear to Q

3

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

RD1

RD2

RD3

RD4

RD8

Logic Module Sequential Timing

t

f

Flip-Flop Data Input Setup

Flip-Flop Data Input Hold

Latch Data Input Setup

0.5

0.0

0.5

0.0

1.9

4.0

0.6

0.0

0.6

0.0

2.4

5.0

0.7

0.0

0.7

0.0

3.2

6.8

0.8

0.0

0.8

0.0

3.8

8.0

0.8

0.0

0.8

0.0

4.8

10.0

ns

SUD

HD

SUD

HD

Latch Data Input Hold

Asynchronous Pulse Width

Flip-Flop Clock Pulse Width

Flip-Flop Clock Input Period

Flip-Flop Clock Frequency

WASYN

WCLKA

A

250

200

150

125

100 MHz

MAX

Notes:

1.

2. For dual-module macros, use t + t + t

V

= 3.0 V for 3.3V specifications.

CC

, t + t + t

or t + t + t

, whichever is appropriate.

SUD

PD RD1

PDn CO RD1

PDn

PD1

RD1

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -1 9 9

A 1 4 1 5 A , A 1 4 V 1 5 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

I/O Module Input Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Data Pad to Y

2.8

4.7

3.2

5.3

3.6

6.0

4.2

7.0

5.5

9.2

ns

INY

Input Reg IOCLK Pad to Y

Output Reg IOCLK Pad to Y

ICKY

OCKY

ICLRY

Input Asynchronous

Clear to Y

4.7

5.3

6.0

7.0

9.2

ns

t

Output Asynchronous

Clear to Y

OCLRY

1

Predicted Input Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

IRD1

IRD2

IRD3

IRD4

IRD8

I/O Module Sequential Timing

t

Input F-F Data Hold

(w.r.t. IOCLK Pad)

INH

0.0

2.0

0.0

5.8

0.7

0.3

1.3

0.0

2.3

0.0

6.5

0.8

0.4

1.5

0.0

2.5

0.0

7.5

0.9

0.4

1.7

0.0

3.0

0.0

8.6

1.0

0.5

2.0

0.0

3.0

0.0

8.6

1.0

0.5

2.0

ns

Input F-F Data Setup

(w.r.t. IOCLK Pad)

INSU

Input Data Enable Hold

(w.r.t. IOCLK Pad)

IDEH

Input Data Enable Setup

(w.r.t. IOCLK Pad)

IDESU

OUTH

OUTSU

ODEH

ODESU

Output F-F Data Hold

(w.r.t. IOCLK Pad)

Output F-F Data Setup

(w.r.t. IOCLK Pad)

Output Data Enable Hold

(w.r.t. IOCLK Pad)

Output Data Enable Setup

(w.r.t. IOCLK Pad)

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 0 0

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 1 5 A , A 1 4 V 1 5 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

1

I/O Module – TTL Output Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Data to Pad, High Slew

Data to Pad, Low Slew

5.0

8.0

5.6

9.0

6.4

7.5

9.8

ns

DHS

10.2

12.0

15.6

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

4.0

7.4

6.5

7.5

4.5

8.3

7.5

5.1

9.4

8.5

9.0

6.0

7.8

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

11.0

10.0

14.3

13.0

19.5

Enable to Pad, H/L to Z,

Hi Slew

Enable to Pad, H/L to Z,

Lo Slew

IOCLK Pad to Pad H/L,

Hi Slew

IOCLK Pad to Pad H/L,

Lo Slew

11.3

0.02

0.05

0.04

0.05

11.3

0.02

0.05

0.04

0.05

13.5

0.03

0.06

0.04

0.06

15.0

0.03

0.07

0.05

0.07

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

0.04 ns/pF

0.09 ns/pF

0.07 ns/pF

0.09 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Delta High to Low, Lo Slew

1

I/O Module – CMOS Output Timing

t

Data to Pad, High Slew

Data to Pad, Low Slew

6.2

7.0

7.9

9.3

12.1

22.8

ns

DHS

11.7

13.1

14.9

17.5

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

5.2

8.9

6.7

8.9

5.9

10.0

7.5

6.6

11.3

8.5

7.8

10.1

17.3

13.0

15.3

22.5

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

13.3

10.0

11.8

Enable to Pad, H/L to Z,

Hi Slew

Enable to Pad, H/L to Z,

Lo Slew

7.5

9.0

IOCLK Pad to Pad H/L,

Hi Slew

8.9

10.7

IOCLK Pad to Pad H/L,

Lo Slew

13.0

0.04

0.07

0.03

0.04

13.0

0.04

0.08

0.03

0.04

15.6

0.05

0.09

0.03

0.04

17.3

0.06

0.11

0.04

0.05

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

Delta High to Low, Lo Slew

0.08 ns/pF

0.14 ns/pF

0.05 ns/pF

0.07 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Note:

1. Delays based on 35pF loading.

1 -2 0 1

A 1 4 1 5 A , A 1 4 V 1 5 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

Dedicated (Hard-Wired) I/O Clock

Network

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Low to High

IOCKH

(Pad to I/O Module Input)

2.0

2.3

2.6

3.0

3.5

ns

t

Minimum Pulse Width High

Minimum Pulse Width Low

1.9

2.4

3.3

3.8

4.8

IOPWH

IOPWL

IOSAPW

Minimum Asynchronous

Pulse Width

1.9

4.0

2.4

5.0

3.3

6.8

3.8

8.0

4.8

ns

t

f

Maximum Skew

0.4

IOCKSW

IOP

Minimum Period

Maximum Frequency

10.0

250

200

150

125

100 MHz

IOMAX

Dedicated (Hard-Wired) Array Clock

Network

t

Input Low to High

HCKH

(Pad to S-Module Input)

3.0

3.4

3.9

4.5

5.5

ns

t

Input High to Low

HCKL

(Pad to S-Module Input)

ns

t

f

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.9

2.4

3.3

3.8

4.8

HPWH

HPWL

HCKSW

HP

0.3

Minimum Period

4.0

5.0

6.8

8.0

10.0

Maximum Frequency

250

200

150

125

100 MHz

HMAX

Routed Array Clock Networks

t

Input Low to High (FO=64)

Input High to Low (FO=64)

3.7

4.0

4.1

4.5

4.7

5.1

5.5

6.0

9.0

ns

RCKH

RCKL

RPWH

Min. Pulse Width High

(FO=64)

3.3

3.8

4.2

4.9

6.5

ns

t

Min. Pulse Width Low

(FO=64)

RPWL

ns

t

f

Maximum Skew (FO=128)

Minimum Period (FO=64)

0.7

0.8

0.9

1.0

75

RCKSW

RP

6.8

8.0

8.7

10.0

13.4

Maximum Frequency

(FO=64)

RMAX

150

125

115

100

MHz

Clock-to-Clock Skews

t

I/O Clock to H-Clock Skew

0.0

1.7

1.0

0.0

1.8

1.0

0.0

2.0

1.0

0.0

2.2

1.0

0.0

3.0

ns

IOHCKSW

IORCKSW

I/O Clock to R-Clock Skew

(FO = 64)

t

H-Clock to R-Clock Skew

(FO = 64)

(FO = 50% max.)

HRCKSW

0.0

1.0

3.0

ns

Note:

1. Delays based on 35pF loading.

1 -2 0 2

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 2 5 A , A 1 4 V 2 5 A T i m i n g C h a r a c t e r i s t i c s

1

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V

= 4 . 7 5 V, T = 7 0 °C )

C C

J

2

1

Logic Module Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Internal Array Module

Sequential Clock to Q

2.0

2.3

2.6

3.0

3.9

ns

PD

CO

CLR

Asynchronous Clear to Q

3

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

RD1

RD2

RD3

RD4

RD8

Logic Module Sequential Timing

t

f

Flip-Flop Data Input Setup

Flip-Flop Data Input Hold

Latch Data Input Setup

0.5

0.0

0.5

0.0

1.9

4.0

0.6

0.0

0.6

0.0

2.4

5.0

0.7

0.0

0.7

0.0

3.2

6.8

0.8

0.0

0.8

0.0

3.8

8.0

0.8

0.0

0.8

0.0

4.8

10.0

ns

SUD

HD

SUD

HD

Latch Data Input Hold

Asynchronous Pulse Width

Flip-Flop Clock Pulse Width

Flip-Flop Clock Input Period

Flip-Flop Clock Frequency

WASYN

WCLKA

A

250

200

150

125

100 MHz

MAX

Notes:

1.

2. For dual-module macros, use t + t + t

V

= 3.0 V for 3.3V specifications.

CC

, t + t + t

or t + t + t

, whichever is appropriate.

SUD

PD RD1

PDn CO RD1

PDn

PD1

RD1

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 0 3

A 1 4 2 5 A , A 1 4 V 2 5 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

I/O Module Input Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Data Pad to Y

2.8

4.7

3.2

5.3

3.6

6.0

4.2

7.0

5.5

9.2

ns

INY

Input Reg IOCLK Pad to Y

Output Reg IOCLK Pad to Y

ICKY

OCKY

ICLRY

Input Asynchronous

Clear to Y

4.7

5.3

6.0

7.0

9.2

ns

t

Output Asynchronous

Clear to Y

OCLRY

1

Predicted Input Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

IRD1

IRD2

IRD3

IRD4

IRD8

I/O Module Sequential Timing

t

Input F-F Data Hold

(w.r.t. IOCLK Pad)

INH

0.0

1.8

0.0

5.8

0.7

0.3

1.3

0.0

2.0

0.0

6.5

0.8

0.4

1.5

0.0

2.3

0.0

7.5

0.9

0.4

1.7

0.0

2.7

0.0

8.6

1.0

0.5

2.0

0.0

3.0

0.0

8.6

1.0

0.5

2.0

ns

Input F-F Data Setup

(w.r.t. IOCLK Pad)

INSU

Input Data Enable Hold

(w.r.t. IOCLK Pad)

IDEH

Input Data Enable Setup

(w.r.t. IOCLK Pad)

IDESU

OUTH

OUTSU

ODEH

ODESU

Output F-F Data Hold

(w.r.t. IOCLK Pad)

Output F-F Data Setup

(w.r.t. IOCLK Pad)

Output Data Enable Hold

(w.r.t. IOCLK Pad)

Output Data Enable Setup

(w.r.t. IOCLK Pad)

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 0 4

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 2 5 A , A 1 4 V 2 5 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

1

I/O Module – TTL Output Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Data to Pad, High Slew

Data to Pad, Low Slew

5.0

8.0

5.6

9.0

6.4

7.5

9.8

ns

DHS

10.2

12.0

15.6

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

4.0

7.4

6.5

7.5

4.5

8.3

7.5

5.1

9.4

8.5

9.0

6.0

7.8

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

11.0

10.0

14.3

13.0

19.5

Enable to Pad, H/L to Z,

Hi Slew

Enable to Pad, H/L to Z,

Lo Slew

IOCLK Pad to Pad H/L,

Hi Slew

IOCLK Pad to Pad H/L,

Lo Slew

11.3

0.02

0.05

0.04

0.05

11.3

0.02

0.05

0.04

0.05

13.5

0.03

0.06

0.04

0.06

15.0

0.03

0.07

0.05

0.07

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

0.04 ns/pF

0.09 ns/pF

0.07 ns/pF

0.09 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Delta High to Low, Lo Slew

1

I/O Module – CMOS Output Timing

t

Data to Pad, High Slew

Data to Pad, Low Slew

6.2

7.0

7.9

9.3

12.1

22.8

ns

DHS

11.7

13.1

14.9

17.5

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

5.2

8.9

6.7

8.9

5.9

10.0

7.5

6.6

11.3

8.5

7.8

10.1

17.3

13.0

15.3

22.5

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

13.3

10.0

11.8

Enable to Pad, H/L to Z,

Hi Slew

Enable to Pad, H/L to Z,

Lo Slew

7.5

9.0

IOCLK Pad to Pad H/L,

Hi Slew

8.9

10.7

IOCLK Pad to Pad H/L,

Lo Slew

13.0

0.04

0.07

0.03

0.04

13.0

0.04

0.08

0.03

0.04

15.6

0.05

0.09

0.03

0.04

17.3

0.06

0.11

0.04

0.05

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

Delta High to Low, Lo Slew

0.08 ns/pF

0.14 ns/pF

0.05 ns/pF

0.07 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Note:

1. Delays based on 35pF loading.

1 -2 0 5

A 1 4 2 5 A , A 1 4 V 2 5 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

Dedicated (Hard-Wired) I/O Clock

Network

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Low to High

IOCKH

(Pad to I/O Module Input)

2.0

2.3

2.6

3.0

3.5

ns

t

Minimum Pulse Width High

Minimum Pulse Width Low

1.9

2.4

3.3

3.8

4.8

IOPWH

IOPWL

IOSAPW

Minimum Asynchronous

Pulse Width

1.9

4.0

2.4

5.0

3.3

6.8

3.8

8.0

4.8

ns

t

f

Maximum Skew

0.4

IOCKSW

IOP

Minimum Period

Maximum Frequency

10.0

250

200

150

125

100 MHz

IOMAX

Dedicated (Hard-Wired) Array Clock

Network

t

Input Low to High

HCKH

(Pad to S-Module Input)

3.0

3.4

3.9

4.5

5.5

ns

t

Input High to Low

HCKL

(Pad to S-Module Input)

ns

t

f

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.9

2.4

3.3

3.8

4.8

HPWH

HPWL

HCKSW

HP

0.3

Minimum Period

4.0

5.0

6.8

8.0

10.0

Maximum Frequency

250

200

150

125

100 MHz

HMAX

Routed Array Clock Networks

t

Input Low to High (FO=64)

Input High to Low (FO=64)

3.7

4.0

4.1

4.5

4.7

5.1

5.5

6.0

9.0

ns

RCKH

RCKL

Min. Pulse Width High

(FO=64)

t

RPWH

3.3

3.8

4.2

4.9

6.5

ns

Min. Pulse Width Low

(FO=64)

RPWL

ns

t

Maximum Skew (FO=128)

Minimum Period (FO=64)

0.7

0.8

0.9

1.0

RCKSW

RP

6.8

8.0

8.7

10.0

13.4

Maximum Frequency

(FO=64)

f

RMAX

150

1.7

125

1.8

115

2.0

100

2.2

75

MHz

ns

Clock-to-Clock Skews

t

I/O Clock to H-Clock Skew

0.0

3.0

IOHCKSW

IORCKSW

I/O Clock to R-Clock Skew

(FO = 64)

(FO = 80)

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

3.0

ns

t

H-Clock to R-Clock Skew

(FO = 64)

HRCKSW

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

ns

(FO = 80)

Note:

1. Delays based on 35pF loading.

1 -2 0 6

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 4 0 A , A 1 4 V 4 0 A T i m i n g C h a r a c t e r i s t i c s

1

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V

= 4 . 7 5 V, T = 7 0 °C )

C C

J

2

1

Logic Module Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Internal Array Module

Sequential Clock to Q

2.0

2.3

2.6

3.0

3.9

ns

PD

CO

CLR

Asynchronous Clear to Q

3

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

RD1

RD2

RD3

RD4

RD8

Logic Module Sequential Timing

t

f

Flip-Flop Data Input Setup

Flip-Flop Data Input Hold

Latch Data Input Setup

0.5

0.0

0.5

0.0

1.9

4.0

0.6

0.0

0.6

0.0

2.4

5.0

0.7

0.0

0.7

0.0

3.2

6.8

0.8

0.0

0.8

0.0

3.8

8.0

0.8

0.0

0.8

0.0

4.8

10.0

ns

SUD

HD

SUD

HD

Latch Data Input Hold

Asynchronous Pulse Width

Flip-Flop Clock Pulse Width

Flip-Flop Clock Input Period

Flip-Flop Clock Frequency

WASYN

WCLKA

A

250

200

150

125

100 MHz

MAX

Notes:

1.

2. For dual-module macros, use t + t + t

V

= 3.0 V for 3.3V specifications.

CC

, t + t + t

or t + t + t

, whichever is appropriate.

SUD

PD RD1

PDn CO RD1

PDn

PD1

RD1

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 0 7

A 1 4 4 0 A , A 1 4 V 4 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

I/O Module Input Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Data Pad to Y

2.8

4.7

3.2

5.3

3.6

6.0

4.2

7.0

5.5

9.2

ns

INY

Input Reg IOCLK Pad to Y

Output Reg IOCLK Pad to Y

ICKY

OCKY

ICLRY

Input Asynchronous

Clear to Y

4.7

5.3

6.0

7.0

9.2

ns

t

Output Asynchronous

Clear to Y

OCLRY

1

Predicted Input Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

IRD1

IRD2

IRD3

IRD4

IRD8

I/O Module Sequential Timing

t

Input F-F Data Hold

(w.r.t. IOCLK Pad)

INH

0.0

1.5

0.0

5.8

0.7

0.3

1.3

0.0

1.7

0.0

6.5

0.8

0.4

1.5

0.0

2.0

0.0

7.5

0.9

0.4

1.7

0.0

2.3

0.0

8.6

1.0

0.5

2.0

0.0

2.3

0.0

8.6

1.0

0.5

2.0

ns

Input F-F Data Setup

(w.r.t. IOCLK Pad)

INSU

Input Data Enable Hold

(w.r.t. IOCLK Pad)

IDEH

Input Data Enable Setup

(w.r.t. IOCLK Pad)

IDESU

OUTH

OUTSU

ODEH

ODESU

Output F-F Data Hold

(w.r.t. IOCLK Pad)

Output F-F Data Setup

(w.r.t. IOCLK Pad)

Output Data Enable Hold

(w.r.t. IOCLK Pad)

Output Data Enable Setup

(w.r.t. IOCLK Pad)

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 0 8

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 4 0 A , A 1 4 V 4 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

1

I/O Module – TTL Output Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Data to Pad, High Slew

Data to Pad, Low Slew

5.0

8.0

5.6

9.0

6.4

7.5

9.8

ns

DHS

10.2

12.0

15.6

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

4.0

7.4

8.5

4.5

8.3

8.5

5.1

9.4

9.5

6.0

7.8

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

11.0

14.3

19.5

Enable to Pad, H/L to Z,

Hi Slew

Enable to Pad, H/L to Z,

Lo Slew

IOCLK Pad to Pad H/L,

Hi Slew

IOCLK Pad to Pad H/L,

Lo Slew

11.3

0.02

0.05

0.04

0.05

11.3

0.02

0.05

0.04

0.05

13.5

0.03

0.06

0.04

0.06

15.0

0.03

0.07

0.05

0.07

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

0.04 ns/pF

0.09 ns/pF

0.07 ns/pF

0.09 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Delta High to Low, Lo Slew

1

I/O Module – CMOS Output Timing

t

Data to Pad, High Slew

Data to Pad, Low Slew

6.2

7.0

7.9

9.3

12.1

22.8

ns

DHS

11.7

13.1

14.9

17.5

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

5.2

8.9

7.4

9.0

5.9

10.0

8.3

6.6

11.3

9.4

7.8

10.1

17.3

14.3

22.5

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

13.3

11.0

11.8

Enable to Pad, H/L to Z,

Hi Slew

Enable to Pad, H/L to Z,

Lo Slew

8.3

9.4

IOCLK Pad to Pad H/L,

Hi Slew

9.0

10.1

IOCLK Pad to Pad H/L,

Lo Slew

13.0

0.04

0.07

0.03

0.04

13.0

0.04

0.08

0.03

0.04

15.6

0.05

0.09

0.03

0.04

17.3

0.06

0.11

0.04

0.05

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

Delta High to Low, Lo Slew

0.08 ns/pF

0.14 ns/pF

0.05 ns/pF

0.07 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Note:

1. Delays based on 35pF loading.

1 -2 0 9

A 1 4 4 0 A , A 1 4 V 4 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

Dedicated (Hard-Wired) I/O Clock

Network

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Low to High

IOCKH

(Pad to I/O Module Input)

2.0

2.3

2.6

3.0

3.5

ns

t

Minimum Pulse Width High

Minimum Pulse Width Low

1.9

2.4

3.3

3.8

4.8

IOPWH

IOPWL

IOSAPW

Minimum Asynchronous

Pulse Width

1.9

4.0

2.4

5.0

3.3

6.8

3.8

8.0

4.8

ns

t

f

Maximum Skew

0.4

IOCKSW

IOP

Minimum Period

Maximum Frequency

10.0

250

200

150

125

100 MHz

IOMAX

Dedicated (Hard-Wired) Array Clock

Network

t

Input Low to High

HCKH

(Pad to S-Module Input)

3.0

3.4

3.9

4.5

5.5

ns

t

Input High to Low

HCKL

(Pad to S-Module Input)

ns

t

f

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.9

2.4

3.3

3.8

4.8

HPWH

HPWL

HCKSW

HP

0.3

Minimum Period

4.0

5.0

6.8

8.0

10.0

Maximum Frequency

250

200

150

125

100 MHz

HMAX

Routed Array Clock Networks

t

Input Low to High (FO=64)

Input High to Low (FO=64)

3.7

4.0

4.1

4.5

4.7

5.1

5.5

6.0

9.0

ns

RCKH

RCKL

RPWH

Min. Pulse Width High

(FO=64)

3.3

3.8

4.2

4.9

6.5

ns

t

Min. Pulse Width Low

(FO=64)

RPWL

ns

t

Maximum Skew (FO=128)

Minimum Period (FO=64)

0.7

0.8

0.9

1.0

RCKSW

RP

6.8

8.0

8.7

10.0

13.4

Maximum Frequency

(FO=64)

f

RMAX

150

1.7

125

1.8

115

2.0

100

2.2

75

MHz

ns

Clock-to-Clock Skews

t

I/O Clock to H-Clock Skew

0.0

3.0

IOHCKSW

IORCKSW

I/O Clock to R-Clock Skew

(FO = 64)

(FO = 144)

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

3.0

ns

t

H-Clock to R-Clock Skew

(FO = 64)

HRCKSW

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

ns

(FO = 144)

Note:

1. Delays based on 35pF loading.

1 -2 1 0

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 6 0 A , A 1 4 V 6 0 A T i m i n g C h a r a c t e r i s t i c s

1

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V

= 4 . 7 5 V, T = 7 0 °C )

C C

J

2

1

Logic Module Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Internal Array Module

Sequential Clock to Q

2.0

2.3

2.6

3.0

3.9

ns

PD

CO

CLR

Asynchronous Clear to Q

3

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

RD1

RD2

RD3

RD4

RD8

Logic Module Sequential Timing

t

f

Flip-Flop Data Input Setup

Flip-Flop Data Input Hold

Latch Data Input Setup

0.5

0.0

0.5

0.0

2.4

5.0

0.6

0.0

0.6

0.0

3.2

6.8

0.7

0.0

0.7

0.0

3.8

8.0

0.8

0.0

0.8

0.0

4.8

10.0

0.8

0.0

0.8

0.0

6.5

13.4

ns

SUD

HD

ns

SUD

HD

Latch Data Input Hold

ns

Asynchronous Pulse Width

Flip-Flop Clock Pulse Width

Flip-Flop Clock Input Period

Flip-Flop Clock Frequency

ns

WASYN

WCLKA

A

ns

200

150

125

100

75

MHz

MAX

Notes:

1.

2. For dual-module macros, use t + t + t

V

= 3.0 V for 3.3V specifications.

CC

, t + t + t

or t + t + t

, whichever is appropriate.

SUD

PD RD1

PDn CO RD1

PDn

PD1

RD1

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 1 1

A 1 4 6 0 A , A 1 4 V 6 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

I/O Module Input Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Data Pad to Y

2.8

4.7

3.2

5.3

3.6

6.0

4.2

7.0

5.5

9.2

ns

INY

Input Reg IOCLK Pad to Y

Output Reg IOCLK Pad to Y

ICKY

OCKY

ICLRY

Input Asynchronous

Clear to Y

4.7

5.3

6.0

7.0

9.2

ns

t

Output Asynchronous

Clear to Y

OCLRY

1

Predicted Input Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

IRD1

IRD2

IRD3

IRD4

IRD8

I/O Module Sequential Timing

t

Input F-F Data Hold

(w.r.t. IOCLK Pad)

INH

0.0

1.3

0.0

5.8

0.7

0.3

1.3

0.0

1.5

0.0

6.5

0.8

0.4

1.5

0.0

1.8

0.0

7.5

0.9

0.4

1.7

0.0

2.0

0.0

8.6

1.0

0.5

2.0

0.0

2.0

0.0

8.6

1.0

0.5

2.0

ns

Input F-F Data Setup

(w.r.t. IOCLK Pad)

INSU

Input Data Enable Hold

(w.r.t. IOCLK Pad)

IDEH

Input Data Enable Setup

(w.r.t. IOCLK Pad)

IDESU

OUTH

OUTSU

ODEH

ODESU

Output F-F Data Hold

(w.r.t. IOCLK Pad)

Output F-F Data Setup

(w.r.t. IOCLK Pad)

Output Data Enable Hold

(w.r.t. IOCLK Pad)

Output Data Enable Setup

(w.r.t. IOCLK Pad)

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 1 2

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 6 0 A , A 1 4 V 6 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

1

I/O Module – TTL Output Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Data to Pad, High Slew

Data to Pad, Low Slew

5.0

8.0

5.6

9.0

6.4

7.5

9.8

ns

DHS

10.2

12.0

15.6

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

4.0

7.4

7.8

7.4

9.0

4.5

8.3

8.7

8.3

9.0

5.1

9.4

6.0

7.8

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

11.0

11.6

11.0

11.5

14.3

15.1

14.3

15.0

22.1

Enable to Pad, H/L to Z,

Hi Slew

9.9

Enable to Pad, H/L to Z,

Lo Slew

9.4

IOCLK Pad to Pad H/L,

Hi Slew

10.0

IOCLK Pad to Pad H/L,

Lo Slew

12.8

0.02

0.05

0.04

0.05

12.8

0.02

0.05

0.04

0.05

15.3

0.03

0.06

0.04

0.06

17.0

0.03

0.07

0.05

0.07

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

0.04 ns/pF

0.09 ns/pF

0.07 ns/pF

0.09 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Delta High to Low, Lo Slew

1

I/O Module – CMOS Output Timing

t

Data to Pad, High Slew

Data to Pad, Low Slew

6.2

7.0

7.9

9.3

12.1

22.8

ns

DHS

11.7

13.1

14.9

17.5

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

5.2

8.9

5.9

10.0

8.3

6.6

11.3

9.4

7.8

10.1

17.3

14.3

17.9

25.1

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

13.3

11.0

13.8

Enable to Pad, H/L to Z,

Hi Slew

7.4

Enable to Pad, H/L to Z,

Lo Slew

7.4

8.3

9.4

IOCLK Pad to Pad H/L,

Hi Slew

10.4

12.1

IOCLK Pad to Pad H/L,

Lo Slew

14.5

0.04

0.07

0.03

0.04

14.5

0.04

0.08

0.03

0.04

17.4

0.05

0.09

0.03

0.04

19.3

0.06

0.11

0.04

0.05

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

Delta High to Low, Lo Slew

0.08 ns/pF

0.14 ns/pF

0.05 ns/pF

0.07 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Note:

1. Delays based on 35pF loading.

1 -2 1 3

A 1 4 6 0 A , A 1 4 V 6 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

Dedicated (Hard-Wired) I/O Clock

Network

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Low to High

IOCKH

(Pad to I/O Module Input)

2.3

2.6

3.0

3.5

4.5

ns

t

Minimum Pulse Width High

Minimum Pulse Width Low

2.4

3.2

3.8

4.8

6.5

IOPWH

IOPWL

IOSAPW

Minimum Asynchronous

Pulse Width

2.4

5.0

3.2

6.8

3.8

8.0

4.8

6.5

ns

t

f

Maximum Skew

0.6

75

IOCKSW

IOP

Minimum Period

Maximum Frequency

10.0

13.4

ns

200

150

125

100

MHz

IOMAX

Dedicated (Hard-Wired) Array Clock

Network

t

Input Low to High

HCKH

(Pad to S-Module Input)

3.7

4.1

4.7

5.5

7.0

ns

t

Input High to Low

HCKL

(Pad to S-Module Input)

ns

t

f

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

2.4

3.2

3.8

4.8

6.5

HPWH

HPWL

HCKSW

HP

ns

0.6

75

ns

Minimum Period

5.0

6.8

8.0

10.0

13.4

ns

Maximum Frequency

200

150

125

100

MHz

HMAX

Routed Array Clock Networks

t

Input Low to High (FO=256)

Input High to Low (FO=256)

6.0

6.8

7.7

9.0

11.8

ns

RCKH

RCKL

RPWH

Min. Pulse Width High

(FO=256)

4.1

4.5

5.4

6.1

8.2

ns

t

Min. Pulse Width Low

(FO=256)

RPWL

ns

t

f

Maximum Skew (FO=128)

Minimum Period (FO=256)

1.2

1.4

1.6

1.8

RCKSW

RP

8.3

9.3

11.1

12.5

16.7

Maximum Frequency

(FO=256)

RMAX

120

2.6

105

2.7

90

80

60

MHz

ns

Clock-to-Clock Skews

t

I/O Clock to H-Clock Skew

0.0

2.9

0.0

3.0

0.0

3.0

IOHCKSW

IORCKSW

I/O Clock to R-Clock Skew

(FO = 64)

(FO = 216)

0.0

1.7

5.0

0.0

1.7

5.0

0.0

1.7

5.0

0.0

1.7

5.0

0.0

5.0

ns

t

H-Clock to R-Clock Skew

(FO = 64)

HRCKSW

0.0

1.3

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

ns

(FO = 216)

Note:

1. Delays based on 35pF loading.

1 -2 1 4

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 1 0 0 A , A 1 4 V 1 0 0 A T i m i n g C h a r a c t e r i s t i c s

1

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V

= 4 . 7 5 V, T = 7 0 °C )

C C

J

2

1

Logic Module Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Internal Array Module

Sequential Clock to Q

2.0

2.3

2.6

3.0

3.9

ns

PD

CO

CLR

Asynchronous Clear to Q

3

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

RD1

RD2

RD3

RD4

RD8

Logic Module Sequential Timing

t

f

Flip-Flop Data Input Setup

Flip-Flop Data Input Hold

Latch Data Input Setup

0.5

0.0

0.5

0.0

2.4

5.0

0.6

0.0

0.6

0.0

3.2

6.8

0.8

0.5

0.8

0.5

3.8

8.0

0.8

0.5

0.8

0.5

4.8

10.0

0.8

0.5

0.8

0.5

6.5

13.4

ns

SUD

HD

ns

SUD

HD

Latch Data Input Hold

ns

Asynchronous Pulse Width

Flip-Flop Clock Pulse Width

Flip-Flop Clock Input Period

Flip-Flop Clock Frequency

ns

WASYN

WCLKA

A

ns

200

150

125

100

75

MHz

MAX

Notes:

1.

2. For dual-module macros, use t + t + t

V

= 3.0 V for 3.3V specifications.

CC

, t + t + t

or t + t + t

, whichever is appropriate.

SUD

PD RD1

PDn CO RD1

PDn

PD1

RD1

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 1 5

A 1 4 1 0 0 A , A 1 4 V 1 0 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

I/O Module Input Propagation Delays

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Data Pad to Y

2.8

4.7

3.2

5.3

3.6

6.0

4.2

7.0

5.5

9.2

ns

INY

Input Reg IOCLK Pad to Y

Output Reg IOCLK Pad to Y

ICKY

OCKY

ICLRY

Input Asynchronous

Clear to Y

4.7

5.3

6.0

7.0

9.2

ns

t

Output Asynchronous

Clear to Y

OCLRY

1

Predicted Input Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.9

1.2

1.4

1.7

2.8

1.0

1.4

1.6

1.9

3.2

1.1

1.6

1.8

2.2

3.6

1.3

1.8

2.1

2.5

4.2

1.7

2.4

2.8

3.3

5.5

ns

IRD1

IRD2

IRD3

IRD4

IRD8

I/O Module Sequential Timing

t

Input F-F Data Hold

(w.r.t. IOCLK Pad)

INH

0.0

1.2

0.0

5.8

0.7

0.3

1.3

0.0

1.4

0.0

6.5

0.8

0.4

1.5

0.0

1.5

0.0

7.5

1.0

0.5

2.0

0.0

1.8

0.0

8.6

1.0

0.5

2.0

0.0

1.8

0.0

8.6

1.0

0.5

2.0

ns

Input F-F Data Setup

(w.r.t. IOCLK Pad)

INSU

Input Data Enable Hold

(w.r.t. IOCLK Pad)

IDEH

Input Data Enable Setup

(w.r.t. IOCLK Pad)

IDESU

OUTH

OUTSU

ODEH

ODESU

Output F-F Data Hold

(w.r.t. IOCLK Pad)

Output F-F Data Setup

(w.r.t. IOCLK Pad)

Output Data Enable Hold

(w.r.t. IOCLK Pad)

Output Data Enable Setup

(w.r.t. IOCLK Pad)

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -2 1 6

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

A 1 4 1 0 0 A , A 1 4 V 1 0 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

1

I/O Module – TTL Output Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Data to Pad, High Slew

Data to Pad, Low Slew

5.0

8.0

5.6

9.0

6.4

7.5

9.8

ns

DHS

10.2

12.0

15.6

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

4.0

7.4

8.0

7.4

9.5

4.5

8.3

9.0

8.3

9.5

5.1

9.4

6.0

7.8

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

11.0

12.0

11.0

12.0

14.3

15.6

14.3

15.6

22.1

Enable to Pad, H/L to Z,

Hi Slew

10.2

9.4

Enable to Pad, H/L to Z,

Lo Slew

IOCLK Pad to Pad H/L,

Hi Slew

10.5

IOCLK Pad to Pad H/L,

Lo Slew

12.8

0.02

0.05

0.04

0.05

12.8

0.02

0.05

0.04

0.05

15.3

0.03

0.06

0.04

0.06

17.0

0.03

0.07

0.05

0.07

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

0.04 ns/pF

0.09 ns/pF

0.07 ns/pF

0.09 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Delta High to Low, Lo Slew

1

I/O Module – CMOS Output Timing

t

Data to Pad, High Slew

Data to Pad, Low Slew

6.2

7.0

7.9

9.3

12.1

22.8

ns

DHS

11.7

13.1

14.9

17.5

DLS

Enable to Pad, Z to H/L,

Hi Slew

ENZHS

5.2

8.9

5.9

10.0

9.0

6.6

11.3

10.0

9.4

7.8

10.1

17.3

15.6

14.3

17.9

25.1

ns

t

Enable to Pad, Z to H/L,

Lo Slew

ENZLS

ENHSZ

ENLSZ

CKHS

CKLS

13.3

12.0

11.0

13.8

Enable to Pad, H/L to Z,

Hi Slew

8.0

Enable to Pad, H/L to Z,

Lo Slew

7.4

8.3

IOCLK Pad to Pad H/L,

Hi Slew

10.4

12.4

IOCLK Pad to Pad H/L,

Lo Slew

14.5

0.04

0.07

0.03

0.04

14.5

0.04

0.08

0.03

0.04

17.4

0.05

0.09

0.03

0.04

19.3

0.06

0.11

0.04

0.05

d

Delta Low to High, Hi Slew

Delta Low to High, Lo Slew

Delta High to Low, Hi Slew

Delta High to Low, Lo Slew

0.08 ns/pF

0.14 ns/pF

0.05 ns/pF

0.07 ns/pF

TLHHS

TLHLS

THLHS

THLLS

Note:

1. Delays based on 35pF loading.

1 -2 1 7

A 1 4 1 0 0 A , A 1 4 V 1 0 0 A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

Dedicated (Hard-Wired) I/O Clock

Network

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed ‘Std’ Speed 3.3V Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t

Input Low to High

IOCKH

(Pad to I/O Module Input)

2.3

2.6

3.0

3.5

4.5

ns

t

Minimum Pulse Width High

Minimum Pulse Width Low

2.4

3.3

3.8

4.8

6.5

IOPWH

IOPWL

IOSAPW

Minimum Asynchronous

Pulse Width

2.4

5.0

3.3

6.8

3.8

8.0

4.8

6.5

ns

t

f

Maximum Skew

0.6

0.7

0.8

0.6

75

IOCKSW

IOP

Minimum Period

Maximum Frequency

10.0

13.4

ns

200

150

125

100

MHz

IOMAX

Dedicated (Hard-Wired) Array Clock

Network

t

Input Low to High

HCKH

(Pad to S-Module Input)

3.7

4.1

4.7

5.5

7.0

ns

t

Input High to Low

HCKL

(Pad to S-Module Input)

ns

t

f

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

2.4

3.3

3.8

4.8

6.5

HPWH

HPWL

HCKSW

HP

ns

0.6

0.7

0.8

0.6

75

ns

Minimum Period

5.0

6.8

8.0

10.0

13.4

ns

Maximum Frequency

200

150

125

100

MHz

HMAX

Routed Array Clock Networks

t

Input Low to High (FO=256)

Input High to Low (FO=256)

6.0

6.8

7.7

9.0

11.8

ns

RCKH

RCKL

RPWH

Min. Pulse Width High

(FO=256)

4.1

4.5

5.4

6.1

8.2

ns

t

Min. Pulse Width Low

(FO=256)

RPWL

ns

t

Maximum Skew (FO=128)

Minimum Period (FO=256)

1..2

1.4

1.6

1.8

RCKSW

RP

8.3

9.3

11.1

12.5

16.7

Maximum Frequency

(FO=256)

f

RMAX

120

2.6

105

2.7

90

80

60

MHz

ns

Clock-to-Clock Skews

t

I/O Clock to H-Clock Skew

0.0

2.9

0.0

3.0

0.0

3.0

IOHCKSW

IORCKSW

I/O Clock to R-Clock Skew

(FO = 64)

(FO = 350)

0.0

1.7

5.0

0.0

17

5.0

0.0

1.7

5.0

0.0

1.7

5.0

0.0

5.0

ns

t

H-Clock to R-Clock Skew

(FO = 64)

(FO = 350)

HRCKSW

0.0

1.3

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

0.0

1.0

3.0

Note:

1. Delays based on 35pF loading.

1 -2 1 8

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

P a c k a g e P i n A s s i g n m e n t s

1 0 0 -P in P Q F P (T o p Vie w )

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

100-Pin

PQFP

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Pin Number

A1415 Function A1425 Function

Pin Number

A1415 Function A1425 Function

2

IOCLK, I/O

CLKA, I/O

CLKB, I/O

VCC

IOCLK, I/O

CLKA, I/O

CLKB, I/O

VCC

48

61

62

63

64

65

67

78

79

85

86

87

96

97

VCC

14

15

16

17

18

19

20

27

28

29

34

35

36

47

PRB, I/O

GND

PRB, I/O

GND

VCC

GND

VCC

GND

HCLK, I/O

IOPCL, I/O

GND

HCLK, I/O

IOPCL, I/O

GND

PRA, I/O

DCLK, I/O

GND

PRA, I/O

DCLK, I/O

GND

VCC

SDI, I/O

MODE

VCC

SDI, I/O

MODE

VCC

GND

VCC

GND

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC : Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 1 9

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

8 4 -P in P LC C (T o p Vie w )

11 10

9

8

7

6

5

4

3

2

1

84 83 82 81 80 79 78 77 76 75

12

74

13

14

73

72

15

16

17

18

71

70

69

68

19

20

21

22

23

24

25

26

27

28

67

66

65

64

63

62

61

60

59

58

84-Pin

PLCC

29

30

31

32

57

56

55

54

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

1 -2 2 0

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

8 4 -P in P LC C

Pin Number

A1415

A14V15 Function

A1425

A14V25 Function

A1440

A14V40 Function

1

VCC

2

GND

3

VCC

4

PRA, I/O

DCLK, I/O

SDI, I/O

MODE

GND

PRA, I/O

DCLK, I/O

SDI, I/O

MODE

GND

PRA, I/O

DCLK, I/O

SDI, I/O

MODE

GND

11

12

16

27

28

40

41

42

43

45

53

59

60

61

68

69

74

83

84

VCC

PRB, I/O

VCC

PRB, I/O

VCC

PRB, I/O

VCC

GND

VCC

HCLK, I/O

IOPCL, I/O

VCC

HCLK, I/O

IOPCL, I/O

VCC

HCLK, I/O

IOPCL, I/O

VCC

GND

VCC

GND

IOCLK, I/O

CLKA, I/O

CLKB, I/O

IOCLK, I/O

CLKA, I/O

CLKB, I/O

IOCLK, I/O

CLKA, I/O

CLKB, I/O

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC : Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 2 1

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 6 0 -P in P Q F P (T o p Vie w )

1

2

3

4

5

6

7

8

9

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

160-Pin

PQFP

82

81

1 -2 2 2

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

1 6 0 -P in P Q F P

A1425

A1440

A14V40

Function

A1460

A14V60

Function

A1425

A14V25

Function

A1440

A14V40

Function

A1460

A14V60

Function

Number

A14V25

Number

Function

1

GND

SDI, I/O

NC

GND

SDI, I/O

I/O

GND

SDI, I/O

I/O

90

VCC

NC

VCC

I/O

VCC

I/O

2

91

5

92

9

MODE

VCC

NC

MODE

VCC

I/O

MODE

VCC

I/O

93

NC

I/O

10

14

15

18

19

20

24

27

28

29

40

41

43

45

46

47

49

51

53

58

59

60

62

63

74

75

76

77

78

80

81

98

GND

VCC

NC

GND

VCC

I/O

GND

VCC

I/O

99

GND

VCC

GND

NC

GND

VCC

GND

I/O

GND

VCC

GND

I/O

100

103

107

109

110

111

112

113

119

120

121

124

127

136

137

138

139

140

141

142

143

145

147

149

151

153

154

160

GND

NC

GND

I/O

GND

I/O

NC

I/O

NC

I/O

VCC

GND

VCC

NC

VCC

GND

VCC

I/O

VCC

GND

VCC

I/O

NC

I/O

VCC

GND

NC

VCC

GND

I/O

VCC

GND

I/O

NC

I/O

IOCLK, I/O

GND

NC

IOCLK, I/O

GND

I/O

IOCLK, I/O

GND

I/O

NC

I/O

NC

I/O

VCC

NC

VCC

I/O

VCC

I/O

NC

I/O

CLKA, I/O

CLKB, I/O

VCC

GND

VCC

GND

PRA, I/O

NC

CLKA, I/O

CLKB, I/O

VCC

GND

VCC

GND

PRA, I/O

I/O

CLKA, I/O

CLKB, I/O

VCC

GND

VCC

GND

PRA, I/O

I/O

NC

I/O

NC

I/O

NC

I/O

PRB, I/O

GND

VCC

HCLK, I/O

GND

NC

PRB, I/O

GND

VCC

HCLK, I/O

GND

I/O

PRB, I/O

GND

VCC

HCLK, I/O

GND

I/O

NC

I/O

NC

I/O

VCC

NC

VCC

I/O

VCC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

VCC

DCLK, I/O

VCC

DCLK, I/O

VCC

DCLK, I/O

IOPCL, I/O

GND

IOPCL, I/O

GND

IOPCL, I/O

GND

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC : Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 2 3

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 0 8 -P in P Q F P , R Q F P (T o p Vie w )

1

2

3

4

5

6

7

8

9

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

208-Pin

PQFP, RQFP

1 -2 2 4

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

2 0 8 -P in P Q F P , R Q F P

A1460

A14100

A14V100

Function

A1460

A14V60

Function

A14100

A14V100

Function

A14V60

Pin Number

Function

Pin Number

1

2

GND

SDI, I/O

MODE

VCC

GND

SDI, I/O

MODE

VCC

115

116

129

130

131

132

145

146

147

148

156

157

158

164

180

181

182

183

184

185

186

195

201

205

208

VCC

I/O

NC

11

12

25

26

27

28

40

41

52

53

60

65

76

77

78

79

80

82

98

102

104

105

114

GND

VCC

GND

VCC

GND

I/O

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

NC

VCC

GND

NC

GND

I/O

IOCLK, I/O

GND

IOCLK, I/O

GND

VCC

NC

I/O

NC

I/O

VCC

PRB, I/O

GND

VCC

PRB, I/O

GND

VCC

CLKA, I/O

CLKB, I/O

VCC

CLKA, I/O

CLKB, I/O

VCC

GND

VCC

GND

VCC

GND

VCC

HCLK, I/O

VCC

HCLK, I/O

VCC

GND

PRA, I/O

NC

PRA, I/O

I/O

NC

I/O

IOPCL, I/O

GND

VCC

IOPCL, I/O

GND

VCC

NC

I/O

DCLK, I/O

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC : Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 2 5

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 7 6 -P in T Q F P (T o p Vie w )

1

2

3

4

5

6

7

8

9

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

176-Pin

TQFP

98

97

96

95

94

93

92

91

90

89

1 -2 2 6

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

1 7 6 -P in T Q F P

A1440

A14V40

Function

A1460

A14V60

Function

A1440

A14V40

Function

A1460

Number

A14V60

Function

1

GND

SDI, I/O

MODE

VCC

GND

SDI, I/O

MODE

VCC

98

VCC

GND

VCC

GND

I/O

2

99

VCC

10

11

20

21

22

23

32

33

44

49

51

63

64

65

66

67

69

82

83

88

89

108

109

110

119

121

122

123

124

132

133

138

152

153

154

155

156

157

158

170

176

GND

VCC

NC

I/O

GND

VCC

GND

VCC

NC

I/O

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

NC

GND

I/O

IOCLK, I/O

GND

IOCLK, I/O

GND

NC

I/O

NC

I/O

NC

I/O

CLKA, I/O

CLKB, I/O

VCC

CLKA, I/O

CLKB, I/O

VCC

PRB, I/O

GND

VCC

PRB, I/O

GND

VCC

GND

VCC

HCLK, I/O

NC

HCLK, I/O

I/O

PRA, I/O

NC

PRA, I/O

I/O

NC

I/O

NC

I/O

IOPCL, I/O

GND

IOPCL, I/O

GND

DCLK, I/O

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC : Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 2 7

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 0 0 -P in VQ F P (T o p Vie w )

1

75

2

3

74

73

4

5

6

7

72

71

70

69

8

9

68

67

66

65

64

63

62

61

60

59

10

11

12

13

14

15

16

17

100-Pin

VQFP

18

19

20

21

58

57

56

55

22

23

24

25

54

53

52

51

1 -2 2 8

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

1 0 0 -P in VQ F P

Pin Number

A1415

A14V15 Function

A1425

A14V25 Function

A1440

A14V40 Function

1

2

GND

SDI, I/O

MODE

VCC

SDI, I/O

MODE

VCC

SDI, I/O

MODE

VCC

7

8

9

GND

20

21

34

35

36

37

39

50

51

57

58

67

68

69

74

75

87

88

89

90

91

92

93

100

VCC

NC

I/O

PRB, I/O

VCC

PRB, I/O

VCC

PRB, I/O

VCC

GND

VCC

HCLK, I/O

IOPCL, I/O

GND

HCLK, I/O

IOPCL, I/O

GND

HCLK, I/O

IOPCL, I/O

GND

VCC

GND

NC

I/O

IOCLK, I/O

CLKA, I/O

CLKB, I/O

VCC

IOCLK, I/O

CLKA, I/O

CLKB, I/O

VCC

IOCLK, I/O

CLKA, I/O

CLKB, I/O

VCC

GND

PRA, I/O

NC

PRA, I/O

I/O

PRA, I/O

I/O

DCLK, I/O

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC : Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 2 9

P a c k a g e P i n A s s i g m e n t s (c o n t in u e d )

1 3 2 -P in C Q F P (T o p Vie w )

132 131 130 129 128 127 126 125 124

107 106 105 104 103 102 101 100

Pin #1

Index

1

2

3

4

5

6

7

8

99

98

97

96

95

94

93

92

132-Pin

CQFP

25

26

27

28

29

30

31

32

33

75

74

73

72

71

70

69

68

67

34 35 36 37 38 39 40 41 42

59 60 61 62 63 64 65 66

1 -2 3 0

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

1 3 2 -P in C Q F P

Pin Number

A1425 Function

Pin Number

A1425 Function

1

NC

74

75

GND

2

GND

VCC

3

SDI, I/O

MODE

GND

78

VCC

9

89

VCC

10

11

22

26

27

34

36

42

43

48

50

58

59

64

65

66

67

90

GND

VCC

91

VCC

92

GND

98

IOCLK, I/O

NC

VCC

99

NC

100

101

106

107

116

117

118

122

123

131

132

NC

GND

VCC

PRB, I/O

HCLK, I/O

GND

CLKA, I/O

CLKB, I/O

PRA, I/O

GND

VCC

IOPCL, I/O

GND

VCC

DCLK, I/O

NC

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC : Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 1

P a c k a g e P i n A s s i g m e n t s (c o n t in u e d )

1 9 6 -P in C Q F P (T o p Vie w )

196 195 194 193 192 191 190 189 188

155 154 153 152 151 150 149 148

Pin #1

Index

1

2

3

4

5

6

7

8

147

146

145

144

143

142

141

140

196-Pin

CQFP

41

42

43

44

45

46

47

48

49

107

106

105

104

103

102

101

100

99

50 51 52 53 54 55 56 57 58

91 92 93 94 95 96 97 98

1 -2 3 2

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

1 9 6 -P in C Q F P

Pin Number

A1460 Function

Pin Number

A1460 Function

1

2

GND

110

111

112

137

138

139

140

148

149

155

162

172

173

174

183

189

193

196

VCC

SDI, I/O

MODE

VCC

11

12

13

37

38

39

51

52

59

64

77

79

86

94

98

100

101

GND

VCC

GND

VCC

IOCLK, I/O

GND

VCC

GND

CLKA, I/O

CLKB, I/O

PRA, I/O

GND

HCLK, I/O

PRB, I/O

GND

VCC

GND

IOPCL, I/O

GND

DCLK, I/O

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC : Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 3

P a c k a g e P i n A s s i g m e n t s (c o n t in u e d )

2 5 6 -P in C Q F P (T o p Vie w )

256 255 254 253 252 251 250 249 248

200 199 198 197 196 195 194 193

Pin #1

Index

1

2

3

4

5

6

7

8

192

191

190

189

188

187

186

185

256-Pin

CQFP

56

57

58

59

60

61

62

63

64

137

136

135

134

133

132

131

130

129

65 66 67 68 69 70 71 72 73

121 122 123 124 125 126 127 128

1 -2 3 4

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

2 5 6 -P in C Q F P

Pin Number

A14100 Function

Pin Number

A14100 Function

1

2

GND

158

159

160

161

174

175

176

188

189

219

220

221

222

223

224

225

240

256

GND

SDI, I/O

MODE

VCC

11

28

29

30

31

46

59

90

91

92

93

94

96

110

127

128

141

GND

VCC

GND

VCC

GND

VCC

IOCLK, I/O

GND

PRB, I/O

GND

CLKA, I/O

CLKB, I/O

VCC

GND

VCC

HCLK, I/O

GND

PRA, I/O

GND

IOPCL, I/O

GND

DCLK, I/O

VCC

Notes:

1. All unlisted pin numbers are user I/Os.

2. NC: Denotes No Connection

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 5

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 2 5 -P in B G A (T o p Vie w )

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A1460 Function

Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

C8

B8

B2

A1, A15, D15, F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8, P2, R15

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

P9

B14

P14

D1

NC

A11, B5, B7, D8, D12, F6, F11, H1, H12, H14, K11, L1, L13, N8, P5, R1, R8, R11, R14

PRA OR I/O

PRB or I/O

SDI or I/O

A7

L7

D4

V

A8, B12, D5, D14, E3, E8, E13, H2, H3, H11, H15, K4, L2, L12, M8, M15, P4, P8, R13

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 6

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

3 1 3 -P in B G A (T o p Vie w )

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

H

J

K

L

K

L

M

N

P

R

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AB

AC

AD

AE

AD

AE

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

A14100

A14V100 Function

Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

J13

G13

B2

A1, A25, AD2, AE25, J21, L13, M12, M14, N11, N13, N15, P12, P14, R13

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

T14

B24

AD24

G3

NC

A3, A13, A23, AA5, AA9, AA23, AB2, AB4, AB20, AC13, AC25, AD22, AE1, AE21, B14, C5, C25,

D4, D24, E3, E21, F6, F10, F16, G1, G25, H18, H24, J1, J7, J25, K12, L15, L17, M6, N1, N5, N7,

N21, N23, P20, R11, T6, T8, U9, U13, U21, V16, W7, Y20, Y24

PRA OR I/O

PRB or I/O

SDI or I/O

H12

AD12

C1

V

AB18, AD6, AE13, C13, C19, E13, G9, H22, K8, K20, M16, N3, N9, N25, U5, W13, V2, V22, V24

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 7

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 0 0 -P in C P G A (T o p Vie w )

1

2

3

4

5

6

7

8

9

10 11

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

100-Pin

CPGA

G

H

J

K

L

K

L

1

2

3

4

5

6

7

8

9

10 11

Orientation Pin

A1415 Function

Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

C7

D6

C4

C3, C6, C9, E9, F3, F9, J3, J6, J8, J9

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

H6

C10

K9

C2

A6

L3

PRA OR I/O

PRB or I/O

SDI or I/O

B3

V

B6, B10, E11, F2, F10, G2, K2, K6, K10

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 8

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 3 3 -P in C P G A (T o p Vie w )

1

2

3

4

5

6

7

8

9

10 11 12 13

A

B

C

D

E

F

A

B

C

D

E

F

133-Pin

CPGA

G

H

J

G

H

J

K

L

K

L

M

N

M

N

1

2

3

4

5

6

7

8

9

10 11 12 13

A1425 Function

Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

D7

B6

D4

A2, C3, C7, C11, C12, F10, G3, G11, L3, L7, L11, M3, N12

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

K7

C10

L10

E3

NC

A1, A7, A13, G1, G13, N1, N7, N13

PRA OR I/O

PRB or I/O

SDI or I/O

A6

L6

C2

V

B2, B7, B12, E11, G2, G12, J2, J12, M2, M7, M12

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 9

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 7 5 -P in C P G A (T o p Vie w )

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

1

2

1

2

3

4

5

6

7

175-Pin

CPGA

8

9

10

11

12

13

14

15

10

11

12

13

14

15

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

A1440 Function

Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

C9

A9

D5

D4, D8, D11, D12, E4, E14, H4, H12, L4, L12, M4, M8,

M12

GND

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

R8

E12

P13

F3

NC

A1, A2, A15, B2, B3, P2, P14, R1, R2, R14, R15

PRA OR I/O

PRB or I/O

SDI or I/O

B8

R7

D3

V

C3, C8, C13, E15, H3, H13, L1, L14, N3, N8, N13

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 4 0

™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 0 7 -P in C P G A (T o p Vie w )

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

207-Pin

CPGA

J

K

L

K

L

M

N

P

R

S

T

M

N

P

R

S

T

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

A1460 Function

Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

K1

J3

E4

C15, D4, D5, D9, D14, J4, J14, P3, P4, P7, P9, P14, R15

HCKL or I/O

IOCLK or I/O

IOPCL or I/O

MODE

J15

P5

N14

D7

NC

A1, A2, A16, A17, B1, B17, C1, C2, S1, S3, S17, T1, T2, T16, T17

PRA OR I/O

PRB or I/O

SDI or I/O

H1

K16

C3

V

B2, B9, B16, D11, J2, J16, P12, S2, S9, S16, T5

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 4 1

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 5 7 -P in C P G A (T o p Vie w )

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

257-Pin

CPGA

K

L

K

L

M

N

P

R

T

M

N

P

R

T

V

X

Y

V

X

Y

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

A14100 Function Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

L4

L5

E4

B16, C4, D4, D10, D16, E11, J5, K4, K16, L15, R4, T4, T10, T16, T17, X7

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

J16

T5

R16

A5

NC

E5

PRA OR I/O

PRB or I/O

SDI or I/O

J1

J17

B4

V

C3, C10, C13, C17, K3, K17, V3, V7, V10, V17, X14

CC

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 4 2


型号：	A1440AA-1PL208B
厂家：	Actel Corporation
描述：	Accelerator Series FPGAs - ACT 3Family 加速器系列FPGA - ACT 3Family
文件：	总68页 (文件大小：480K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A1440AA-1PL208B [ACTEL]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB