A32200DX-1PQG240C [ACTEL]
Field Programmable Gate Array, 1230 CLBs, 20000 Gates, CMOS, PQFP240, PLASTIC, QFP-240;型号: | A32200DX-1PQG240C |
厂家: | Actel Corporation |
描述: | Field Programmable Gate Array, 1230 CLBs, 20000 Gates, CMOS, PQFP240, PLASTIC, QFP-240 栅 |
文件: | 总22页 (文件大小:217K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
P r e l i m i n a r y
3200DX Field Programmable Gate Arrays
– The System Logic Integrator™ Family
F e a t u r e s
G e n e r a l D e s c r i p t i o n
The 3200DX, the first device family in Actel’s Integrator™
Series, are the first FPGAs optimized for high-speed,
high-complexity system logic integration. Based on Actel’s
proprietary PLICE antifuse technology and state-of-the-art
0.6-micron double metal CMOS process, the 3200DX offers
a fine-grained, register-rich architecture with the industry’s
fastest embedded dual-port SRAM.
H ig h C a p a c it y
• Up to 40,000 logic gates
• Up to 4 Kbits dual-port SRAM
• Fast wide decode circuitry
• Up to 292 User-programmable I/O Pins
H ig h P e r fo r m a n c e
The 3200DX was designed to integrate high performance
system logic functions typically implemented in multiple
CPLDs, PALs, and FPGAs. The 3200DX is the first
programmable logic device to embed dual-port SRAM into
the programmable array. Offering 5 ns access time, the
3200DX provides the fastest embedded SRAM of any
programmable logic device on the market today. This
combination of fast, flexible SRAM blocks with a true
dual-port architecture, allows designers to implement
extremely fast SRAM functions such as FIFOs, LIFOs and
scratchpad memory. The large number of storage elements
can efficiently address applications requiring wide datapath
manipulation and transformation functions such as
telecommunications, networking, DSP and bus interfaces.
The control and decode functions typically implemented in
CPLDs can easily be integrated into the 3200DX by taking
advantage of the wide decode modules.
• 200 MHz datapath applications
• 5 ns Dual-Port SRAM
• 100 MHz FIFOs
• 7.5 ns 35-bit Address Decode
E a s e -o f-In t e g r a t io n
• JTAG 1149.1 Boundary Scan Testing
• Synthesis-friendly architecture supports ASIC design
methodologies
• 95–100% logic utilization using automatic Place and
Route Tools
• Deterministic, user-controllable timing via
DirectTime™ software tools
• Designer Series™ development tool support including
interfaces to popular design environments such as
Cadence, Escalade, Exemplar Logic, IST, Mentor
Graphics, Synopsys and Viewlogic
The 3200DX family is supported by Actel’s Designer Series
3.0 software which provides a seamless integration into any
ASIC design flow. The Designer Series development tools
offer automatic or fixed pin assignments, automatic
placement and routing (with optional manual placement),
• Pin compatible with 1200XL Family
P r o d u c t F a m i l y P r o f i l e
Device
A3265DX
A32100DX
A32140DX
A32200DX
A32300DX
A32400DX
Capacity
Logic Gates
Dual-Port SRAM Bits
6,500
N/A
10,000
2,048
14,000
N/A
20,000
2,560
30,000
3,072
40,000
4,096
Logic Modules
Sequential
Combinatorial
Decode
510
475
20
700
662
20
954
912
24
1,230
1,184
24
1,888
1,833
28
2,526
2,466
28
SRAM Modules (64x4 or 32x8)
N/A
2
8
6
N/A
2
10
6
12
6
16
6
Clocks
JTAG
No
126
Yes
156
Yes
176
Yes
206
Yes
254
Yes
292
User I/O
A u g u s t 1 9 9 5
1
© 1995 Actel Corporation
timing analysis, user programming, and debug and diagnostic
probe capabilities. In addition, Designer 3.0 provides the
DirectTime™ tool which provides deterministic as well as
controllable timing. DirectTime allows the designer to
specify the performance requirements of individual paths and
system clock(s). Using these specifications, the software will
automatically optimize the placement and routing of the logic
to meet these constraints. Included with Designer 3.0 is
provides CAE interfaces to Cadence, Escalade, Exemplar
Logic, IST, Mentor Graphics‚ OrCAD, Synopsys, and
Viewlogic design environments. Additional development
tools are supported through Actel’s Industry Alliance
Program, including DATA I/O (ABEL FPGA) and MINC.
Actel’s FPGAs are an ideal solution for shortening the system
design and development cycle and offers a cost-effective
alternative for low volume production runs. The 3200DX
devices are an excellent choice for integrating logic that is
currently implemented in TTL, PALs, CPLDs and FPGAs.
Some example applications include high-speed controllers
and address decoding, peripheral bus interfaces, DSP, and
co-processor functions.
™
Actel’s ACTgen Macro Builder. ACTgen allows the
designer to quickly build fast, efficient logic functions such
as counters, adders, FIFOs, and RAM.
The Designer Series tools provide designers the capability to
move up to High-Level Description Languages, such as
VHDL and Verilog, or use schematic design entry with
interfaces to most EDA tools. Designer Series 3.0 is
supported on the following development platforms: 386/486
and Pentium PC, Sun‚ and HP‚ workstations. The software
D e v i c e R e s o u r c e s
User I/Os
PLCC
84-pin
PQFP
160-pin
PQFP
208-pin
PQFP
240-pin
TQFP
176-pin
BGA
225-pin
BGA
313-pin
Device Series
A3265DX
72
72
—
—
—
—
125
125
125
—
—
156
176
176
—
—
—
126
151
151
—
—
156
176
TBD
—
—
—
A32100DX
A32140DX
A32200DX
A32300DX
A32400DX
—
—
TBD
TBD
TBD
206
254
TBD
—
—
—
—
—
—
Package Definitions (Consult your local Actel Sales Representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array
O r d e r i n g I n f o r m a t i o n
A32200
DX –
1
PQ
208
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I
= Industrial (–40 to +85°C)
PP = Pre-Production
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flatpack
TQ = Thin (1.4 mm) Quad Flatpack
RQ = Power Quad Flatpack
BG = Ball Grid Array
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Sub Family
Part Number
2
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
P i n D e s c r i p t i o n
Q C LK A/B , C , D Q u a d r a n t C lo c k (In p u t /O u t p u t )
These four pins are the quadrant clock inputs. When not used
as a register control signal, these pins can function as general
purpose I/O.
C LK A, C LK B C lo c k A a n d C lo c k B (in p u t )
TTL Clock inputs for clock distribution networks. The Clock
input is buffered prior to clocking the logic modules. This pin
can also be used as an I/O.
S DI
S e r ia l Da t a In p u t (In p u t )
DC LK
Dia g n o s t ic C lo c k (In p u t )
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
T C K
T e s t C lo c k
G N D
G r o u n d (In p u t )
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
Input LOW supply voltage.
I/O
In p u t /O u t p u t (In p u t , O u t p u t )
T DI
T e s t Da t a In
I/O pin functions as an input, output, three-state or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O
pins are automatically driven LOW by the ALS software.
Serial data input for JTAG instructions and data. Data is
shifted in on the rising edge of TCLK. This pin functions as
an I/O when the JTAG fuse is not programmed.
T DO
T e s t Da t a O u t
MO DE
Mo d e (In p u t )
Serial data output for JTAG instructions and test data. This
pin functions as an I/O when the JTAG fuse is not
programmed.
The MODE pin controls the use of multi-function pins
(DCLK, PRA, PRB, SDI, TDO). When the MODE pin is
HIGH, the special functions are active.
T MS
T e s t Mo d e S e le c t
N C
N o C o n n e c t io n
Serial data input for JTAG test mode. Data is shifted in on the
rising edge of TCLK. This pin functions as an I/O when the
JTAG fuse is not programmed.
This pin is not connected to circuitry within the device.
P R A/I/O
P r o b e A (O u t p u t )
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin's probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
V
S u p p ly Vo lt a g e (In p u t )
C C
Input HIGH supply voltage.
Note: TCK, TDI, TDO, TMS are only available on
devices containing JTAG circuitry.
3 2 0 0 D X A r c h i t e c t u r a l O v e r v i e w
The 3200DX family architecture is composed of fine-grained
building blocks which produce fast, efficient logic designs.
All devices within the 3200DX family are composed of
Logic Modules, Routing Resources, Clock Networks, and I/O
modules which are the building blocks to design fast logic
designs. In addition, a subset of the device family contains
embedded dual-port SRAM modules which can implement
fast SRAM functions such as FIFOs, LIFOs, and scratchpad
memory.
P R B /I/O
P r o b e B (O u t p u t )
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
3
Lo g ic Mo d u le s
The 3200DX contains three types of logic modules:
combinatorial (C-modules), sequential (S-modules), and
decode (D-modules). Both the C-module and S-module are
identical to the 1200XL family logic modules.
A0
B0
S0
D00
D00
D10
D11
The combinatorial module (shown in Figure 1) implements
the following function:
Y
Y=!S1*!S0*D00+!S1*S0*D01*S1*!S0*D01+S1*S0*D11
where:
S0=A0*B0
S1=A1 + B1
S1
The S-module is designed to implement high-speed flip-flop
functions within a single module. The S-module implements
the same logic function as the C-module followed by a
sequential block. The sequential block can implement either a
D flip-flop or a transparent latch. The S-module can also be
configured as fully transparent so that it can be used to
implement purely combinatorial logic. The function of the
sequential module is determined by the macro selection from
the design library. The available S-module implementations
A1
B1
Figure 1 • C-module Implementation
are shown in Figure 2.
D-modules are arranged around the periphery of the device
and contain wide decode circuits providing a fast decode
function similar to CPLDs and PALs (Figure 3). This is
D00
D01
D00
D01
OUT
OUT
Y
D
Q
Y
D
Q
D10
D10
S0
D11
S1
D11
S1
S0
GATE
CLR
Up to 7-input function plus D-type flip-flop with clear
Up to 7-input function plus latch
D00
D01
D0
Y
OUT
OUT
Y
D
Q
D10
S0
D1
D11
S1
GATE
S
CLR
Up to 8-input function (same as C-module)
Up to 4-input function plus latch with clear
Figure 2 • S-module Implementations
4
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
analogous to the wide-input AND term in a CPLD or PAL
device. The output of the D-module has a programmable
inverter for active HIGH or LOW assertion. The D-module
output is hardwired to an output pin or can be fed back into
the array to be incorporated into other logic.
7 inputs
Du a l-P o r t S R AM Mo d u le s
hardwire to I/O
The 3200DX dual-port SRAM modules have been optimized
for synchronous or asynchronous applications. The SRAM
modules are arranged in 256 bit blocks which can be
configured as 32 x 8 or 64 x 4 (refer to Table 1 for the number
of SRAM modules within a particular device). The SRAM
module block structure allows them to be cascaded together
to form user-definable memory spaces. Resources within the
3200DX architecture allow the SRAM modules to be
cascaded together without incurring an additional delay
penalty. A block diagram of the 3200DX dual-port SRAM
block is shown in Figure 4.
Programmable
inverter
feedback to array
Figure 3 • D-Module Implementation
and read ports of the SRAM block have eight data inputs
(WD[7:0]) and eight outputs (RD[7:0]). The SRAM block
outputs are connected to segmented vertical routing tracks.
The 3200DX SRAM blocks are true dual-port structures
containing independent READ and WRITE logic. The
SRAM blocks contain six bits of read and write addressing
(RDAD[5:0] and WRAD[5:0] respectively) for 64x4 bit
blocks. When configured in byte mode, the highest order
address bits (RDAD5 and WRAD5) are not used. The read
and write ports of the SRAM blocks contain independent
clocks (RCLK and WCLK) with programmable polarities
offering active HIGH or LOW implementation. The write
The 3200DX dual-port SRAM blocks are ideal for
high-speed buffered applications such as DMA controllers
and FIFO and LIFO queues. Actel’s ACTgen Macro Builder
provides the capability to quickly design memory elements,
such as FIFOs, LIFOs, and RAM arrays which can be
included in any 3200DX design. Additionally, unused SRAM
blocks can be used to implement registers for other logic
within the design.
WD[7:0]
Latches
[7:0]
[5:0]
RDAD[5:0]
SRAM Module
32 x 8 or 64 x 4
Latches
Read
Port
Logic
Write
Port
Logic
(256 bits)
WRAD[5:0]
[5:0]
LEN
REN
Read
Logic
Latches
RCLK
MODE
BLKEN
WEN
RD[7:0]
Write
Logic
Routing Tracks
WCLK
Figure 4 • Dual-Port SRAM Module
5
I/O Mo d u le s
segments. The minimum horizontal segment length is the
width of a module-pair, and the maximum horizontal
segment length is the full length of the channel. Any segment
that spans more than one-third the row length is considered a
long horizontal segment. A typical channel is shown in
Figure 6. Non-dedicated horizontal routing tracks are used to
route signal nets. Dedicated routing tracks are used for the
global clock networks and for power and ground tie-off
tracks.
The I/O modules provide the interface between the device
pins and the logic array (shown in Figure 5). A variety of I/O
configurations, determined by a library macro selection, can
be implemented in the module (refer to the Macro Library
Guide for more information). I/O modules contain input and
output latches as well as a tri-state buffer. These features
allow the module to be configured for input, output, or
bi-directional pins.
Vertical Routing
EN
Other tracks run vertically through the module. Vertical
tracks are of three types: input, output, and long. Vertical
tracks are also divided into one or more segments. Each
segment in an input track is dedicated to the input of a
particular module. Each segment in an output track is
dedicated to the output of a particular module. Long segments
are uncommitted and can be assigned during routing. Each
output segment spans four channels (two above and two
below), except near the top and bottom of the array where
edge effects occur. An example of vertical routing tracks and
segments is shown in Figure 6.
Q
D
PAD
From Array
G/CLK*
Q
D
To Array
Segmented
Logic
G/CLK*
horizontal
Modules
routing
tracks
* Can be configured as a Latch or D Flip-Flop
(using C-module)
Figure 5 • I/O Module
Antifuses
I/O modules contain input and output latches for capturing
data prior to and/or from the device pins. In addition, the
Actel Designer Series software tools can build a D flip-flop
using a C-module in conjunction with the I/O latch to register
input and/or output signals. Actel’s Designer Series
development tools provide a design library of I/O macros
which can implement all I/O configurations supported by the
3200DX.
Vertical routing tracks
Figure 6 • Horizontal Routing Tracks and Segments
Antifuse Structures
R o u t in g S t r u c t u r e
An antifuse is a “normally open” structure as opposed to the
normally closed fuse structure used in PROMs or PALs. The
use of antifuses to implement a Programmable Logic Device
results in highly testable structures as well as efficient
programming algorithms. The structure is highly testable
because there are no pre-existing connections; therefore,
temporary connections can be made using pass transistors.
These temporary connections can isolate individual antifuses
to be programmed as well as isolate individual circuit
structures to be tested. This can be done both before and after
programming. For example, all metal tracks can be tested for
continuity and shorts between adjacent tracks, and the
functionality of all logic modules can be verified.
The 3200DX architecture uses Horizontal and Vertical
routing tracks to interconnect the various logic and I/O
modules. These routing tracks are metal interconnects that
may either be of continuous length or broken into pieces
called segments. Varying segment lengths allows the
interconnect of over 90% of design tracks to occur with only
two antifuse connections. Segments can be joined together at
the ends, using antifuses, to increase their lengths up to the
full length of the track. All interconnects can be
accomplished with a maximum of four antifuses.
Horizontal Routing
Horizontal channels are located between the rows of modules
and are composed of several routing tracks. The horizontal
routing tracks within the channel are divided into one or more
6
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
C lo c k N e t w o r k s
Two low-skew, high fanout clock distribution networks are
provided in each 3200DX device. These networks are
referred to as CLK0 and CLK1. Each network has a clock
module (CLKMOD) that selects the source of the clock
signal and may be driven as follows:
CLKB
CLKA
CLKINB
CLKINA
FROM
PADS
S0
S1
INTERNAL
SIGNAL
CLKMOD
1. Externally from the CLKA pad
2. Externally from the CLKB pad
3. Internally from the CLKINA input
4. Internally from the CLKINB input
CLKO(17)
CLKO(16)
CLKO(15)
CLOCK
DRIVERS
The clock modules are located in the top row of I/O modules.
Clock drivers and a dedicated horizontal clock track are
located in each horizontal routing channel.
The user controls the clock module by selecting one of two
clock macros from the macro library. The macro CLKBUF is
used to connect one of the two external clock pins to a clock
network, and the macro CLKINT is used to connect an
internally generated clock signal to a clock network. Since
both clock networks are identical, the user does not care
whether CLK0 or CLK1 is being used. The clock input pads
may also be used as normal I/Os, bypassing the clock
networks (see Figure 7).
CLKO(2)
CLKO(1)
CLOCK TRACKS
Figure 7 • Clock Networks
The 3200DX devices which contain SRAM modules (all
except A3265DX and A32140DX) have four additional
register control resources, called Quadrant Clock Networks
(Figure 8). Each quadrant clock provides a local, high-fanout
resource to the contiguous logic modules within its quadrant
of the device. Quadrant clock signals can originate from
specific I/O pins or from the internal array and can be used as
a secondary register clock, register clear, or output enable.
T e s t C ir c u it r y
The 3200DX provides two modes of device and/or
board-level testing; JTAG 1149.1 Boundary Scan Testing
and Actel’s Actionprobe® test facility. Once a 3200DX
device has been programmed, the Actionprobe test facility
QCLKA
QCLKC
Quad
Quad
Clock
Module
Clock
Module
QCLK1
QCLK3
QCLKB
QCLKD
*QCLK1IN
*QCLK3IN
S0 S1
S1 S0
Quad
Clock
Quad
Clock
QCLK2
QCLK4
Module
Module
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
*QCLK1IN, QCLK2IN, QCLK3IN, and QCKL4IN are internally generated signals.
Figure 8 • Quadrant Clock Network
7
allows the designer to probe any internal node during device The 3200DX JTAG BST circuitry consist of a Test Access
operation to aid in debugging a design.
Port (TAP) controller, JTAG instruction register, JPROBE
register, bypass register and boundary scan register. Figure 9
is a block diagram of the 3200DX JTAG circuitry.
JTAG Boundary Scan Testing (BST)
Device pin spacing is decreasing with the advent of fine-pitch
packages such as TQFP and BGA packages and
manufacturers are routinely implementing surface-mount
technology with multi-layer PC boards. Boundary scan is
becoming an attractive tool to help systems manufacturers
test their PC boards. The Joint Test Action Group (JTAG)
developed the IEEE Boundary Scan standard 1149.1 to
facilitate board-level testing during manufacturing.
When a device is operating in JTAG BST mode, four I/O pins
are used for the TDI, TDO, TMS, and TCK signals. An active
reset (nTRST) pin is not supported, however the 3200DX
contains power-on reset circuitry which resets the JTAG BST
circuitry upon power-up. The following table summarizes the
functions of the JTAG BST signals.
JTAG
Signal
Name
Function
IEEE Standard 1149.1 defines a 4-pin Test Access Port
(TAP) interface for testing integrated circuits in a system.
The 3200DX family provides four JTAG BST pins: Test
Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and
Test Mode Select (TMS). Devices are configured in a JTAG
“chain” where BST data can be transmitted serially between
devices via TDO to TDI interconnections. The TMS and
TCK signals are shared between all devices in the JTAG
chain so that all components operate in the same state.
TDI
Test Data In
Serial data input for JTAG
instructions and data. Data is
shifted in on the rising edge of
TCLK.
TDO
TMS
Test Data Out Serial data output for JTAG
instructions and test data.
Test Mode
Select
Serial data input for JTAG test
mode. Data is shifted in on the
rising edge of TCLK.
The 3200DX family implements a subset of the IEEE 1149.1
Boundary Scan Test (BST) instruction in addition to a private
instruction to allow the use of Actel’s Actionprobe facility
with JTAG BST. Refer to the IEEE 1149.1 specification for
detailed information regarding JTAG testing.
TCK
Test Clock
Clock signal to shift the JTAG
data into the device.
JTAG BST Instructions
JTAG Architecture
JTAG BST testing within the 3200DX devices is controlled
by a Test Access Port (TAP) state machine. The TAP
controller drives the three-bit instruction register, a bypass
register, and the boundary scan data registers within the
device. The TAP controller uses the TMS signal to control
The 3200DX’s JTAG BST function is enabled by
programming the JTAG anti-fuse. When JTAG BST is not
enabled, the TMS, TCLK, and TDI pins become user I/O.
Otherwise, these three pins are dedicated exclusively to
JTAG testing.
JPROBE Register
Boundary Scan Register
Output
MUX
TDO
Bypass
Register
Control Logic
TMS
Instruction
TAP Controller
Decode
TCLK
Instruction
Register
TDI
Figure 9 • JTAG BST Circuitry
8
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
the JTAG testing of the device. The JTAG test mode is
determined by the bit stream entered on the TMS pin. The
table below describes the JTAG instructions supported by the
3200DX.
Test Mode
Code
Description
EXTEST
000
Allows the external circuitry
and board-level
interconnections to be tested
by forcing a test pattern at the
output pins and capturing test
results at the input pins.
SAMPLE/
PRELOAD
001
Allows a snapshot of the
signals at the device pins to be
captured and examined during
device operation.
INTEST
010
011
Refer to IEEE 1149.1
Specification
JPROBE
A private instruction allowing
the user to connect Actel’s
Micro Probe registers to the
JTAG chain.
USER
INSTRUCTION
100
Allows the user to build
application-specific
instructions such as RAM
READ and RAM WRITE.
HIGH Z
CLAMP
BYPASS
101
110
111
Refer to IEEE 1149.1
Specification
Refer to IEEE 1149.1
Specification
Enables the by bypass register
between the TDI and TDO
pins. The test data passes
through the selected device to
adjacent devices in the JTAG
chain.
Actionprobe
If a device has been successfully programmed and the
security fuse has not been programmed, any internal logic or
I/O module output can be observed using the Actionprobe
circuitry and the PRA and/or PRB pins. The Actionprobe
diagnostic system provides the software and hardware
required to perform real-time debugging. Refer to Actel’s
1995 Data Book for further information on using the
Actionprobe facility.
9
1
R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s
A b s o l u t e M a x i m u m R a t i n g s
F r e e a ir t e m p e r a t u r e r a n g e
Parameter
Commercial Industrial Units
Symbol Parameter
Limits
Units
°C
1
Temperature Range
0 to +70
–40 to +85
V
V
DC Supply Voltage
Input Voltage
–0.5 to +7.0
V
V
CC
Power Supply
Tolerance
±5
±10
%V
CC
–0.5 to V +0.5
I
CC
V
Output Voltage
–0.5 to V +0.5
V
O
CC
Note:
T
Storage Temperature
–65 to +150
°C
STG
1. Ambient temperature (T ) is used for commercial and
A
industrial; case temperature (T ) is used for military.
C
Note:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
E l e c t r i c a l S p e c i f i c a t i o n s
Commercial
Symbol
Parameter
Units
Min.
Max.
V
HIGH Level Output
I
I
I
I
= –10 mA (CMOS)
= –6 mA (TTL)
= 10 mA (CMOS)
= 6 mA (TTL)
2.40
3.84
V
V
OH
OL
OH
OH
OL
OL
V
LOW Level Output
0.50
0.33
0.8
V
V
V
V
HIGH Level Input
LOW Level Input
Input Leakage
–0.3
2.0
V
IH
V
+ 0.3
V
IL
CC
I
I
I
V = V or GND
–10
+10
µA
IN
I
CC
Standby V Supply
V = V or GND,
I CC
CC
CC(S)
CC(D)
Current
I = 0 mA
1.5
mA
mA
O
Dynamic V Supply Current
Note 1
CC
Note:
1. See “Power Dissipation” section.
1 0
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
Maximum junction temperature is 150°C.
P a c k a g e T h e r m a l C h a r a c t e r i s t i c s
A sample calculation of the absolute maximum power
dissipation allowed for a PQFP 160-pin package at
commercial temperature is as follows:
The device junction to case thermal characteristic is θjc, and
the junction to ambient air characteristic is θja. The thermal
characteristics for θja are shown with two different air flow
rates.
Max. junction temp. (°C) – Max. commercial temp.
150°C – 70°C
---------------------------------------------------------------------------------------------------------------------------- = --------------------------------- = 2 . 6 W
θja (°C/W)
30°C/W
θja
Maximum Power Dissipation
Package Type
Pin Count
Still Air
300 ft/min
Still Air
300 ft/min
Plastic Quad Flatpack
Plastic Quad Flatpack
Plastic Leaded Chip Carrier
Thin Quad Flatpack
160
208
84
36 °C/W
25 °C/W
37 °C/W
32 °C/W
30 °C/W
16.2 °C/W
28 °C/W
25 °C/W
2.2 W
3.2 W
2.2 W
2.5 W
2.6 W
4.9 W
2.9 W
3.2 W
176
G e n e r a l P o w e r E q u a t i o n
greater reduction in board-level power dissipation can
be achieved.
P = [I standby + I active] * V + I * V * N
CC
CC
CC
OL
OL
The power due to standby current is typically a small
component of the overall power. Standby power is
calculated below for commercial, worst case conditions.
+ I * (V – V ) * M
OH
CC
OH
Where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
I
V
Power
CC
CC
2 mA
5.25 V
10.5 mW
ICCactive is the current flowing due to CMOS
switching.
The static power dissipation by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this number is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with
all outputs driving low and 140 mW with all outputs driving
high. The actual dissipation will average somewhere between
as I/Os switch states with time.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL
M equals the number of outputs driving TTL loads to
VOH
.
Ac t iv e P o w e r C o m p o n e n t
.
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totem-pole current in the CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
can be combined with frequency and voltage to represent
active power dissipation.
An accurate determination of N and M is problematic
because their values depend on the family type, design
details, and on the system I/O. The power can be divided into
two components: static and active.
S t a t ic P o w e r C o m p o n e n t
Actel FPGAs have small static power components that
result in lower power dissipation than PALs or PLDs. By
integrating multiple PALs/PLDs into one FPGA, an even
1 1
E q u iv a le n t C a p a c it a n c e
f
f
f
f
f
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
m
The power dissipated by a CMOS circuit can be expressed by
Equation 1.
n
p
Power (µW) = CEQ * VCC2 * F
(1)
q1
q2
Where:
CEQ is the equivalent capacitance expressed in picofarads
(pF).
F ix e d C a p a c it a n c e Va lu e s fo r Ac t e l F P G As
(p F )
VCC is power supply in volts (V).
r
r
2
1
F is the switching frequency in megahertz (MHz).
Device Type
routed_Clk1
routed_Clk2
Equivalent capacitance is calculated by measuring I
at
CCactive
a specified frequency and voltage for each circuit component
of interest. Measurements have been made over a range of
A3265DX
A32140DX
A32200DX
TBD
TBD
TBD
TBD
TBD
TBD
frequencies at a fixed value of V . Equivalent capacitance is
CC
frequency independent so that the results may be used over a
wide range of operating conditions. Equivalent capacitance
values are shown below.
De t e r m in in g Av e r a g e S w it c h in g F r e q u e n c y
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
C
Va lu e s fo r Ac t e l F P G As
E Q
Modules (C
)
5.2
11.6
23.8
3.5
EQM
Input Buffers (C
)
EQI
Output Buffers (C
)
EQO
Routed Array Clock Buffer Loads (C
)
EQCR
Logic Modules (m)
= 80% of
combinatorial
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
modules
Inputs switching (n)
Outputs switching (p)
= # of inputs/4
= # outputs/4
Power = VCC2 * [(m x CEQM * fm)Modules
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2)
Where:
+
+
+
First routed array clock loads (q ) = 40% of sequential
1
modules
Second routed array clock loads
(q )
= 40% of sequential
modules
m
= Number of logic modules switching at frequency
2
f
m
Load capacitance (C )
= 35 pF
= F/10
L
n
p
= Number of input buffers switching at frequency f
n
= Number of output buffers switching at frequency
Average logic module switching
f
rate (f )
p
m
q
q
= Number of clock loads on the first routed array
clock
1
2
Average input switching rate (f )
= F/5
n
Average output switching rate (f ) = F/10
= Number of clock loads on the second routed array
clock
p
Average first routed array clock rate = F
r
r
= Fixed capacitance due to first routed array clock
= Fixed capacitance due to second routed array clock
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in pF
= Equivalent capacitance of routed array clock in pF
= Output load capacitance in pF
1
(f )
q1
2
Average second routed array clock = F/2
C
C
C
C
C
EQM
rate (f )
q2
EQI
EQO
EQCR
L
1 2
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
3 2 0 0 D X T i m i n g M o d e l ( L o g i c F u n c t i o n s ) *
Input Delays
I/O Module
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
t
= 1.3 ns
INPY
t
= 3.2 ns
IRD1
Combinatorial
Module
t
= 3.7 ns
DLH
t
= 1.3 ns
RD1
D
Q
t
= 2.5 ns
PD
G
Decode
Module
t
= 0.0 ns
= 0.3 ns
= 2.6 ns
INH
t
= 0.3 ns
t
t
RDD
INSU
INGO
t
= 2.9 ns
PDD
I/O Module
t
= 3.7 ns
DLH
Sequential
Logic Module
t
= 1.3 ns
RD1
Combin-
atorial
Logic
D
D
G
Q
Q
t
= 3.7 ns
ENHZ
included
in t
SUD
t
= 0.0 ns
= 0.3 ns
= 2.0 ns
LH
t
t
LSU
LCO
t
= 2.5 ns
t
= 0.3 ns
= 0.0 ns
CO
SUD
HD
t
ARRAY
CLOCKS
F
= 200 MHz
MAX
*Values shown for A3265DX-2 at worst-case commercial conditions.
1 3
3 2 0 0 D X T i m i n g M o d e l ( S R A M F u n c t i o n s ) *
Input Delays
I/O Module
t
= 1.3 ns
INPY
t
= 3.2 ns
IRD1
D
Q
G
Predicted
Routing
Delays
I/O Module
t
= 0.3 ns
= 0.0 ns
= 2.6 ns
INSU
t
= 3.7 ns
DLH
t
INH
INGO
RD [7:0]
RDAD [5:0]
REN
t
WD [7:0]
•
•
•
t
= 2.0 ns
RD1
WRAD [5:0]
BLKEN
D
Q
WEN
G
WCLK
RCLK
t
= 1.8 ns
= 0.0 ns
= 1.0 ns
t
= 1.8 ns
ADSU
ADSU
t
= 0.0 ns
= 0.3 ns
= 0.0 ns
LCO
t
t
= 0.0 ns
= 2.9 ns
= 2.9 ns
ADH
t
ADH
LSU
t
ARRAY
t
t
RENSU
WENSU
LH
CLOCKS
t
BLKENSU
F
= 100 MHz
MAX
*Values shown for A32200DX-2 at worst-case commercial conditions.
1 4
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
P a r a m e t e r M e a s u r e m e n t
O u t p u t B u ffe r De la y s
E
D
PAD To AC test loads (shown below)
TRIBUFF
In
50%
E
50%
E
50%
50%
CC
50%
50%
V
V
V
OH
OH
1.5 V
1.5 V
90%
PAD
PAD
PAD
GND
1.5 V
10%
1.5 V
V
V
OL
OL
t
t
t
t
t
t
ENHZ
DLH
DHL
ENZL
ENLZ
ENZH
AC T e s t Lo a d s
Load 1
Load 2
(Used to measure propagation delay)
(Used to measure rising/falling edges)
V
GND
CC
To the output under test
35 pF
R to V for t /t
CC
PLZ PZL
R to GND for t
/t
PHZ PZH
R = 1 kΩ
To the output under test
35 pF
In p u t B u ffe r De la y s
Mo d u le De la y s
S
A
B
Y
Y
PAD
INBUF
S, A or B
Y
50% 50%
50%
3 V
50%
PAD
0 V
1.5 V
1.5 V
V
t
t
CC
PLH
PHL
50%
Y
Y
GND
50%
50%
50%
t
t
PLH
PHL
t
t
INYL
INYH
1 5
S e q u e n t i a l M o d u l e T i m i n g C h a r a c t e r i s t i c s
F lip -F lo p s a n d La t c h e s
D
E
CLK
Y
PRE
CLR
(Positive edge triggered)
t
HD
1
D
t
t
t
A
WCLKA
SUD
G, CLK
t
t
SUENA
WCLKI
t
HENA
E
t
CO
Q
t
RS
PRE, CLR
t
WASYN
Note:
D represents all data functions involving A, B, and S for multiplexed flip-flops.
1 6
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
S e q u e n t i a l T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
In p u t B u ffe r La t c h e s
PAD
DATA
IBDL
G
PAD
CLK
CLKBUF
DATA
G
t
INH
t
INSU
t
HEXT
CLK
t
SUEXT
Output Buffer Latches
D
G
PAD
OBDLHS
D
t
OUTSU
G
t
OUTH
1 7
D e c o d e M o d u l e T i m i n g
A
B
C
D
E
F
Y
G
V
CC
A–G, H
50%
V
CC
Y
t
PHL
t
PLH
S R A M T i m i n g C h a r a c t e r i s t i c s
Read Port
Write Port
WRAD [5:0]
BLKEN
WEN
RDAD [5:0]
LEW
RAM Array
32x8 or 64x4
(256 bits)
REN
WCLK
RCLK
WD [7:0]
RD [7:0]
1 8
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
D u a l -P o r t S R A M T i m i n g W a v e f o r m s
3 2 0 0 DX S R AM Wr it e O p e r a t io n
t
t
RCKHL
RCKHL
WCLK
t
t
t
t
t
ADSU
ADH
WD[7:0]
WRAD[5:0]
Valid
WENSU
WENH
BENH
WEN
t
BENSU
Valid
BLKEN
Note: Identical timing for falling-edge clock.
3 2 0 0 DX S R AM S y n c h r o n o u s R e a d O p e r a t io n
t
t
RCKHL
CKHL
RCLK
REN
t
t
RENSU
RENH
t
t
ADH
ADSU
Valid
RDAD[5:0]
RD[7:0]
t
RCO
t
DOH
Old Data
New Data
Note:
1. Identical timing for falling-edge clock.
1 9
3 2 0 0 DX S R AM As y n c h r o n o u s R e a d O p e r a t io n —T y p e 1
(Read Address Controlled)
t
RENHA
t
RENSUA
(Data 2 in hold state)
REN
t
RDADV
RDAD[5:0]
ADDR1
ADDR2
t
RPD
t
DOH
Data 1
Data 2
RD[7:0]
3 2 DX S R AM As y n c h r o n o u s R e a d O p e r a t io n —T y p e 2
(Write Address Controlled)
WEN
t
t
WENSU
WENH
WD[7:0]
WRAD[5:0]
BLKEN
Valid
t
t
ADH
ADSU
WCLK
t
RPD
t
DOH
Old Data
New Data
RD[7:0]
t
RENH
REN
2 0
3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
P r e d i c t a b l e P e r f o r m a n c e :
T i g h t D e l a y D i s t r i b u t i o n s
routing of the user’s design is complete. Delay values may
then be determined by using the ALS Timer utility or
performing simulation with post-layout delays.
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of inputs
increases.
C r it ic a l N e t s a n d T y p ic a l N e t s
Propagation delays are expressed only for typical nets, which
are used for initial design performance evaluation. Since the
3200DX architecture provides deterministic timing and
abundant routing resources, Actel’s Designer Series
development tools offers DirectTime; a timing-driven place
and route tool. Using DirectTime, the designer may specify
timing-critical nets and system clock frequency. Using these
timing specifications, the place and route software optimized
the layout of the design to meet the user’s specifications.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer routing tracks.
The 3200DX family delivers a very tight fanout delay
distribution. This tight distribution is achieved in two ways:
by decreasing the delay of the interconnect elements and by
decreasing the number of interconnect elements per path.
Lo n g T r a c k s
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes four
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6% of nets in a
fully utilized device require long tracks. Long tracks
contribute approximately 3 ns to 6 ns delay. This additional
delay is represented statistically in higher fanout (FO=8)
routing delays in the data sheet specifications section.
Actel’s patented PLICE antifuse offers a very low
resistive/capacitive interconnect. The 3200DX family’s
antifuses, fabricated in 0.6 micron lithography, offer nominal
levels of 100 ohms resistance and 7.0 femtofarad (fF)
capacitance per antifuse.
The 3200DX fanout distribution is also tight due to the low
number of antifuses required for each interconnect path. The
3200DX family’s proprietary architecture limits the number
of antifuses per path to a maximum of four, with 90% of
interconnects using two antifuses.
T im in g De r a t in g
A best case timing derating factor of 0.45 is used to reflect
best case processing. Note that this factor is relative to the
“standard speed” timing parameters, and must be multiplied
by the appropriate voltage and temperature derating factors
for a given application.
T i m i n g C h a r a c t e r i s t i c s
Timing characteristics for 3200DX devices fall into three
categories: family dependent, device dependent, and design
dependent. The input and output buffer characteristics are
common to all 3200DX family members. Internal routing
delays are device dependent. Design dependency means
actual delays are not determined until after placement and
T i m i n g D e r a t i n g F a c t o r ( T e m p e r a t u r e a n d V o l t a g e )
Industrial
Military
Min.
Max.
Min.
Max.
(Commercial Specification) x
0.69
1.11
0.67
1.23
T i m i n g D e r a t i n g F a c t o r f o r D e s i g n s a t T y p i c a l T e m p e r a t u r e ( T = 2 5 °C )
J
a n d V o l t a g e ( 5 . 0 V )
(Maximum Specification, Worst-Case Condition) x
0.85
Note: This derating factor applies to all routing and propagation delays.
2 1
T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s
( n o r m a l i z e d t o W o r s t -C a s e C o m m e r c i a l , T = 4 . 7 5 V , 7 0 °C )
J
–55
0.75
0.71
0.69
0.68
0.67
–40
0.79
0.75
0.72
0.69
0.69
0
25
70
85
125
1.23
1.16
1.13
1.09
1.08
4.50
4.75
5.00
5.25
5.50
0.86
0.82
0.80
0.77
0.76
0.92
0.87
0.85
0.82
0.81
1.06
1.00
0.97
0.95
0.93
1.11
1.05
1.02
0.98
0.97
Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial,T = 4.75 V, 70°C)
J
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
125°C
85°C
70°C
25°C
0°C
–40°C
–55°C
4.50
4.75
5.00
5.25
5.50
Voltage (V)
Note:
This derating factor applies to all routing and propagation delays.
2 2
相关型号:
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