A3P1000-FVQG144I [ACTEL]

ProASIC3 Flash Family FPGAs; 闪光的ProASIC3系列FPGA


型号：	A3P1000-FVQG144I
厂家：	Actel Corporation
描述：	ProASIC3 Flash Family FPGAs 闪光的ProASIC3系列FPGA
文件：	总206页 (文件大小：5922K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

v1.0

ProASIC3 Flash Family FPGAs

with Optional Soft ARM Support

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Features and Benefits

• 15 k to 1 M System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

High Capacity

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

†

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS (A3P250 and above)

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• I/O Registers on Input, Output, and Enable Paths

‡

• Hot-Swappable and Cold Sparing I/Os

†

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• Retains Programmed Design when Powered Off

High Performance

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL^†

• Six CCC Blocks, One with an Integrated PLL

• 350 MHz System Performance

†

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• Configurable

Phase-Shift,

Multiply/Divide,

Delay

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory^†

Standard (AES) Decryption (except ARM-enabled ProASIC 3

†

devices) via JTAG (IEEE 1532–compliant)

• FlashLock to Secure FPGA Contents

• 1 kbit of FlashROM User Nonvolatile Memory

Low Power

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

• Core Voltage for Low Power

†

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O

• True Dual-Port SRAM (except ×18)

ARM Processor Support in ProASIC3 FPGAs

• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft

Processor Available with or without Debug

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

ProASIC3 Product Family

ProASIC3 Devices

A3P015 A3P030 A3P060 A3P125

A3P250

A3P400

A3P600

A3P1000

ARM7 Devices

M7A3P1000

Cortex-M1 Devices

System Gates

M1A3P250

M1A3P400

M1A3P600

M1A3P1000

15 k

128

384

–

30 k

256

768

–

60 k

512

1,536

125 k

1,024

3,072

250 k

–

400 k

–

600 k

–

1 M

–

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

6,144

9,216

13,824

108

24,576

144

–

FlashROM Bits

1 k

–

1 k

–

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

Secure (AES) ISP

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

157

194

235

300

Package Pins

QFN

QN68

QN132 QN132 QN132

QN132

VQFP

VQ100

TQ144

VQ100

TQ144

PQ208

VQ100

TQFP

PQFP

PQ208

FG144 FG144/256

PQ208

FG144/256/

484

PQ208

FG144/256/

484

PQ208

FG144/256/

484

FBGA

FG144

Notes:

1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.

2. AES is not available for ARM-enabled ProASIC3 devices.

3. Six chip (main) and three quadrant global networks are available for A3P060 and above.

4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.

5. The M1A3P250 device does not support this package.

†

A3P015 and A3P030 devices do not support this feature.

‡ Supported only by A3P015 and A3P030 devices.

February 2008

I/Os Per Package

ProASIC3

Devices

A3P015

A3P030

A3P060

A3P125

A3P250 ³

A3P400 ³

A3P600

A3P1000

ARM7 Devices

M7A3P1000

Cortex-M1

Devices

M1A3P250 ^3,6

I/O Type

M1A3P400 ³

M1A3P600

M1A3P1000

Package

QN68

–

100

133

–

QN132

VQ100

TQ144

PQ208

FG144

FG256

FG484

Notes:

–

151

157

–

151

178

194

154

177

300

–

177

235

–

1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 Flash Family FPGAs

handbook to ensure complying with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer

to the ProASIC3 Flash Family FPGAs handbook for position assignments of the 15 LVPECL pairs.

4. FG256 and FG484 are footprint-compatible packages.

5. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 Ordering Information" on page III for the location of the

"G" in the part number.

6. The M1A3P250 device does not support FG256 or QN132 packages.

Table 1-1 • ProASIC3 FPGAs Package Sizes Dimensions

Package

QN68

QN132

VQ100

TQ144

PQ208

FG144

FG256

FG484

Length × Width

(mm\mm)

8 × 8

14 × 14

20 × 20

28 × 28

13 × 13

17 × 17

23 × 23

Nominal Area

(mm²)

196

400

784

169

289

529

Pitch (mm)

0.4

0.5

1.0

Height (mm)

0.90

0.75

1.00

1.40

3.40

1.45

1.60

2.23

v1.0

ProASIC3 Flash Family FPGAs

ProASIC3 Ordering Information

A3P1000

144

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (–40°C to +85°C Ambient Temperature)

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G= RoHS-Compliant (Green) Packaging

Package Type

Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)

Very Thin Quad Flat Pack (0.5 mm pitch)

Thin Quad Flat Pack (0.5 mm pitch)

Plastic Quad Flat Pack (0.5 mm pitch)

Fine Pitch Ball Grid Array (1.0 mm pitch)

Speed Grade

F = 20% Slower than Standard*

Blank = Standard

1 = 15% Faster than Standard

2 = 25% Faster than Standard

Part Number

ProASIC3 Devices

A3P015 = 15,000 System Gates

A3P030 = 30,000 System Gates

A3P060 = 60,000 System Gates

A3P125 = 125,000 System Gates

A3P250 = 250,000 System Gates

A3P400 = 400,000 System Gates

A3P600 = 600,000 System Gates

A3P1000 = 1,000,000 System Gates

ProASIC3 Devices with ARM7

M7A3P1000 = 1,000,000 System Gates

ProASIC3 Devices with Cortex-M1

M1A3P250 = 250,000 System Gates

M1A3P400 = 400,000 System Gates

M1A3P600 = 600,000 System Gates

M1A3P1000 = 1,000,000 System Gates

* The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in

the commercial temperature range.

v1.0

III

Temperature Grade Offerings

Package

ARM7 Devices

Cortex-M1 Devices

QN68

A3P015

A3P030

A3P060

A3P125

A3P250

A3P400

A3P600

A3P1000

M7A3P1000

M1A3P250

M1A3P400

M1A3P600

M1A3P1000

C, I

–

C, I

–

C, I

–

QN132

C, I

–

C, I

–

VQ100

–

TQ144

–

PQ208

–

C, I

–

C, I

FG144

–

C, I

–

FG256

–

FG484

–

Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature

2. I = Industrial temperature range: –40°C to 85°C ambient temperature

Speed Grade and Temperature Grade Matrix

Temperature Grade

–F ¹

Std.

✓

–1

✓

–2

✓

C²

✓

I³

–

✓

Notes:

1. The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only

supported in the commercial temperature range.

2. C = Commercial temperature range: 0°C to 70°C ambient temperature

3. I = Industrial temperature range: –40°C to 85°C ambient temperature

References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start

with M7 (CoreMP7) and M1 (Cortex-M1).

Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.

A3P015 and A3P030

The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.

v1.0

1 – ProASIC3 Device Family Overview

General Description

ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and

features beyond those of the ProASIC^PLUS®family. Nonvolatile flash technology gives ProASIC3

devices the advantage of being a secure, low-power, single-chip solution that is live at power-up

(LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and

A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates,

supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

ProASIC3 devices support the ARM7 soft IP core and Cortex-M1 devices. The ARM-enabled devices

have Actel ordering numbers that begin with M7A3P (CoreMP7) and M1A3P (Cortex-M1) and do

not support AES decryption.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3 devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property (IP) cannot be compromised or

copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3

family device architecture mitigates the need for ASIC migration at higher user volumes. This

makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in

the consumer, networking/ communications, computing, and avionics markets.

Security

The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock,

which provides a unique combination of reprogrammability and design security without external

overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices

can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. The AES standard was adopted by the National Institute of Standards and

Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES

decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. ProASIC3 devices with AES-based

security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP

thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure

design verification is possible.

ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the

ARM core must be protected at all times, AES encryption is always on for the core logic, so

bitstreams are always encrypted. There is no user access to encryption for the FlashROM

programming data.

v1.0

1-1

ProASIC3 Device Family Overview

Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES

security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable

IP is protected and secure, making remote ISP possible. A ProASIC3 device provides the most

impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

ProASIC3 FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based ProASIC3 devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based ProASIC3 devices greatly simplifies total system

design and reduces total system cost, often eliminating the need for CPLDs and clock generation

PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system

power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs,

the device will not have to be reloaded when system power is restored. This enables the reduction

or complete removal of the configuration PROM, expensive voltage monitor, brownout detection,

and clock generator devices from the PCB design. Flash-based ProASIC3 devices simplify total

system design and reduce cost and design risk while increasing system reliability and improving

system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-

based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs

cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft)

errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error

detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal

choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current

surge and no high-current transition period, both of which occur on many FPGAs.

ProASIC3 devices also have low dynamic power consumption to further maximize power savings.

1-2

v1.0

ProASIC3 Device Family Overview

Advanced Flash Technology

The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through

an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS

design techniques are used to implement logic and control functions. The combination of fine

granularity, enhanced flexible routing resources, and abundant flash switches allows for very high

logic utilization without compromising device routability or performance. Logic functions within

the device are interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and

Figure 1-2 on page 1-4):

•

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory^†

Extensive CCCs and PLLs^†

Advanced I/O structure

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block*

I/Os

VersaTile

ISP AES

Decryption*

User Nonvolatile

FlashROM

Charge Pumps

Bank 1

* Not supported by A3P015 and A3P030 devices

Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and

A3P125)

†

The A3P015 and A3P030 do not support PLL or SRAM.

v1.0

1-3

ProASIC3 Device Family Overview

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

(A3P600 and A3P1000)

ISP AES

Decryption

User Nonvolatile

FlashROM

Charge Pumps

Bank 2

Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input

lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the

FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation

architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of ProASIC3 devices via an IEEE 1532 JTAG interface.

VersaTiles

The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASIC^PLUS®core

tiles. The ProASIC3 VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

1-4

v1.0

ProASIC3 Device Family Overview

Refer to Figure 1-3 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

Data

CLK

CLR

LUT-3

D-FF

CLK

D-FF

Enable

CLR

Figure 1-3 • VersaTile Configurations

User Nonvolatile FlashROM

Actel ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM

can be used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks (except in the A3P015 and A3P030 devices),

as in security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel ProASIC3 development software solutions, Libero^®Integrated Design Environment (IDE)

and Designer, have extensive support for the FlashROM. One such feature is auto-generation of

sequential programming files for applications requiring a unique serial number in each part.

Another feature allows the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their

north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory

configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have

independent read and write ports that can be configured with different bit widths on each port.

For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded

SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG

macro (except in A3P015 and A3P030 devices).

v1.0

1-5

ProASIC3 Device Family Overview

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member

of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and

A3P030 devices do not have a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz to 350 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz to 350 MHz

Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

2 programmable delay types for clock skew minimization

Clock frequency synthesis (for PLL only)

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration (for PLL only).

•

Output duty cycle = 50% 1.5% or better (for PLL only)

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used (for PLL only)

•

Maximum acquisition time = 300 µs (for PLL only)

Low power consumption of 5 mW

Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL

only)

•

Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

f_{OUT_CCC}) (for PLL only)

Global Clocking

ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high fanout nets.

1-6

v1.0

ProASIC3 Device Family Overview

I/Os with Advanced I/O Standards

The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages

(1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended

and differential.

The I/Os are organized into banks, with two or four banks per device. The configuration of these

banks determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-Data-Rate applications

Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications

ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.

B-LVDS and M-LVDS can support up to 20 loads.

Part Number and Revision Date

Part Number 51700097-001-1

Revised February 2008

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version

Changes in Current Version (v1.0)

Page

51700097-001-1

This document was divided into two sections and given a version number,

starting at v1.0. The first section of the document includes features, benefits,

ordering information, and temperature and speed grade offerings. The second

section is a device family overview.

51700097-001-0

(January 2008)

This document was updated to include A3P015 device information. QN68 is a

new package that was added because it is offered in the A3P015. The following

sections were updated:

N/A

"Features and Benefits"

"ProASIC3 Ordering Information"

"Temperature Grade Offerings"

"ProASIC3 Product Family"

"A3P015 and A3P030" note

"Introduction and Overview"

The "ProASIC3 FPGAs Package Sizes Dimensions" table is new.

In the "ProASIC3 Ordering Information", the QN package measurements were

updated to include both 0.4 mm and 0.5 mm.

III

In the "General Description" section, the number of I/Os was updated from 288

to 300.

1-1

v2.2

(July 2007)

This document was previously in datasheet v2.2. As a result of moving to the

handbook format, Actel has restarted the version numbers. The new version

number is 51700097-001-0.

N/A

v1.0

1-7

ProASIC3 Device Family Overview

Previous Version

Changes in Current Version (v1.0)

Page

v2.1

The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3 i, ii, iii,

(May 2007)

Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering

Information", "Temperature Grade Offerings", and "Speed Grade and

Temperature Grade Matrix".

iii, iv

The words "ambient temperature" were added to the temperature range in iii, iii, iv

the "Automotive ProASIC3 Ordering Information", "Temperature Grade

Offerings", and "Speed Grade and Temperature Grade Matrix"sections.

v2.0

(April 2007)

In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input

Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz).

The "Clock Conditioning Circuit (CCC) and PLL" section was updated.

In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and

A3P600 device I/Os were updated.

Advance v0.7

(January 2007)

In the "Packaging Tables", Ambient was deleted.

Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".

Advance v0.6

(April 2006)

In the "I/Os Per Package" table, the I/O numbers were added for A3P060,

A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77.

Advance v0.5

(January 2006)

B-LVDS and M-LDVS are new I/O standards added to the datasheet.

The term flow-through was changed to pass-through.

Table 1 was updated to include the QN132.

N/A

The "I/Os Per Package" table was updated with the QN132. The footnotes were

also updated. The A3P400-FG144 I/O count was updated.

"Automotive ProASIC3 Ordering Information" was updated with the QN132.

"Temperature Grade Offerings" was updated with the QN132.

iii

Advance v0.4

(November 2005)

The "I/Os Per Package" table was updated for the following devices and

packages:

Device

Package

VQ100

FG144

A3P250/M7ACP250

A3P1000

FG256

Advance v0.3

Advance v0.2

M7 device information is new.

N/A

The I/O counts in the "I/Os Per Package" table were updated.

The "I/Os Per Package" table was updated.

1-8

v1.0

ProASIC3 Device Family Overview

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

v1.0

1-9

2 – ProASIC3 DC and Switching Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

V_CC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

V_JTAG

V_PUMPProgramming voltage

V_CCPLLAnalog power supply (PLL)

V_CCI

VMV

DC I/O output buffer supply voltage

DC I/O input buffer supply voltage

I/O input voltage

–0.3 V to 3.6 V

(when I/O hot insertion mode is enabled)

–0.3 V to (V_CCI+ 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

T_STG

Storage temperature

Junction temperature

–65 to +150

+125

°C

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

v1.3

2-1

ProASIC3 DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ¹

Symbol

T_A

Parameter

Ambient temperature

Commercial

0 to +70 ^4,6

1.425 to 1.575

1.4 to 3.6

Industrial

–40 to +85 ^5,6

1.425 to 1.575

1.4 to 3.6

Units

°C

V_CC

1.5 V DC core supply voltage

JTAG DC voltage

V_JTAG

V_PUMP

Programming voltage

Programming Mode

Operation ³

3.15 to 3.45

0 to 3.6

3.15 to 3.45

0 to 3.6

V_CCPLL

Analog power supply (PLL)

1.4 to 1.6

_CCIand VMV ²1.5 V DC supply voltage

1.425 to 1.575

1.7 to 1.9

1.425 to 1.575

1.7 to 1.9

1.8 V DC supply voltage

2.5 V DC supply voltage

3.3 V DC supply voltage

2.3 to 2.7

3.0 to 3.6

LVDS/B-LVDS/M-LVDS differential I/O

LVPECL differential I/O

2.375 to 2.625

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-18 on page 2-19. VMV and V_CCIshould be at the same voltage within a

given I/O bank.

3. V_PUMPcan be left floating during operation (not programming mode).

4. Maximum T_J= 85°C.

5. Maximum T_J= 100°C.

6. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature¹

Programming Program Retention

Maximum Storage

Maximum Operating

Product Grade

Commercial

Industrial

Cycles

(biased/unbiased) Temperature T_STG(°C) ²Junction Temperature T_J(°C) ²

500

20 years

110

100

500

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

2-2

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-4 • Overshoot and Undershoot Limits ¹

Average V_CCI–GND Overshoot or Undershoot

Maximum Overshoot/

Undershoot²

V_CCIand VMV

Duration as a Percentage of Clock Cycle²

2.7 V or less

10%

1.4 V

1.49 V

1.1 V

3 V

10%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC^®3 device. These

circuits ensure easy transition from the powered-off state to the powered-up state of the device.

The many different supplies can power up in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. V_CCand V_CCIare above the minimum specified trip points (Figure 2-1 on page 2-4).

2. V_CCI> V_CC– 0.75 V (typical)

3. Chip is in the operating mode.

V_CCITrip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

V_CCTrip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

V_CCand V_CCIramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

•

During programming, I/Os become tristated and weakly pulled up to V_CCI.

JTAG supply, PLL power supplies, and charge pump V_PUMPsupply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until V_CCand V_CCPLLXexceed brownout

activation levels. The V_CCactivation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4

for more details).

When PLL power supply voltage and/or V_CClevels drop below the V_CCbrownout levels (0.75 V

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

v1.3

2-3

ProASIC3 DC and Switching Characteristics

Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information

on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation

= V + VT

CCI

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

= 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, V_IH/V_IL, V_OH/V_OL, etc.

but slower because V_CCIis

below specification. For the

same reason, input buffers do not

meet V_IH/V_ILlevels, and output

buffers do not meet V_OH/V_OLlevels.

= 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V_CCis below specification.

I/Os are functional (except differential inputs)

but slower because V_CCI/V_CCare below

specification. For the same reason, input

buffers do not meet V_IH/V_ILlevels, and

output buffers do not meet V_OH/V_OLlevels.

Activation trip point:

= 0.85 V 0.25 V

Deactivation trip point:

= 0.75 V 0.25 V

Region 1: I/O buffers are OFF

Activation trip point:

= 0.9 V 0.3 V

CCI

Min V datasheet specification

CCI

voltage at a selected I/O

Deactivation trip point:

= 0.8 V 0.3 V

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

Figure 2-1 • I/O State as a Function of V_CCIand V_CCVoltage Levels

2-4

v1.3

ProASIC3 DC and Switching Characteristics

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

T_J= Junction Temperature = ∆T + T_A

EQ 2-1

where:

T_A= Ambient Temperature

∆T = Temperature gradient between junction (silicon) and ambient ∆T = θ_ja* P

_ja= Junction-to-ambient of the package. θ_janumbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θ_jcand the junction-to-ambient air thermal

resistivity is θ_ja. The thermal characteristics for θ_jaare shown for two air flow rates. The absolute

maximum junction temperature is 100°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and

in still air.

Max. junction temp. (° C) – Max. ambient temp. (° C)

100° C – 70° C

Maximum Power Allowed = ---------------------------------------------------------------------------------------------------------------------------------------- = -------------------------------------- = 1 . 46 3 W

θ_ja(° C/W)

20.5° C/W

EQ 2-2

Table 2-5 • Package Thermal Resistivities

θ_ja

Package Type

Device

Pin Count θ_jcStill Air 200 ft./min. 500 ft./min. Units

Quad Flat No Lead

A3P030

A3P060

132

100

144

208

144

256

484

144

256

484

0.4

0.3

0.2

0.1

10.0

11.0

8.0

3.8

3.2

6.3

6.6

8.0

21.4

21.2

21.1

21.0

35.3

33.5

26.1

16.2

26.9

26.6

20.5

31.6

28.1

23.3

16.8

16.6

16.5

16.4

29.4

28.0

22.5

13.3

22.9

22.8

17.0

26.2

24.4

19.0

15.3

15.0

14.9

14.8

27.1

25.7

20.8

11.9

21.5

15.9

24.2

22.7

16.7

C/W

A3P125

A3P250

Very Thin Quad Flat Pack (VQFP)

Thin Quad Flat Pack (TQFP)

Plastic Quad Flat Pack (PQFP)

All devices

PQFP with embedded heatspreader All devices

Fine Pitch Ball Grid Array (FBGA)

See note*

A3P1000

* This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal

information will be available in future revisions of the datasheet.

v1.3

2-5

ProASIC3 DC and Switching Characteristics

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 70°C, V_CC= 1.425 V)

Junction Temperature (°C)

Array Voltage V_CC(V)

–40°C

0.87

0.83

0.80

0°C

0.92

0.88

0.85

25°C

0.95

0.90

0.87

70°C

1.00

0.95

0.92

85°C

1.02

0.97

0.93

110°C

1.05

0.99

0.96

1.425

1.500

1.575

Calculating Power Dissipation

Quiescent Supply Current

Table 2-7 • Quiescent Supply Current Characteristics

A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

Typical (25°C)

Max. (Commercial)

Max. (Industrial)

Notes:

2 mA

3 mA

5 mA

8 mA

50 mA

75 mA

10 mA 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA

15 mA 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA

1. I_DDIncludes V_CC, V_PUMP, V_CCI, and VMV currents. Values do not include I/O static contribution,

which is shown in Table 2-11 and Table 2-12 on page 2-8.

2. –F speed grade devices may experience higher standby I_DDof up to five times the standard I_DD

and higher I/O leakage.

Power per I/O Pin

Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Advanced I/O Banks

Static Power

P_DC2(mW) ¹

Dynamic Power P_AC9

(µW/MHz) ²

VMV (V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

16.69

5.12

2.13

1.45

18.11

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

1.20

1.87

LVPECL

Notes:

1. P_DC2is the static power (where applicable) measured on VMV.

2. P_AC9is the total dynamic power measured on V_CCand VMV.

2-6

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

Static Power

Dynamic Power

VMV (V)

_DC2(mW) ¹

_AC9(µW/MHz) ²

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

16.72

5.14

2.13

1.48

18.13

3.3 V PCI-X

Notes:

1. P_DC2is the static power (where applicable) measured on VMV.

2. P_AC9is the total dynamic power measured on V_CCand VMV.

Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Standard I/O Banks

Static Power

P_DC2(mW) ¹

Dynamic Power

VMV (V)

P_AC9(µW/MHz) ²

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

3.3

2.5

1.8

1.5

–

16.79

5.19

2.18

1.52

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

Notes:

1. P_DC2is the static power (where applicable) measured on VMV.

1. P_AC9is the total dynamic power measured on V_CCand VMV.

v1.3

2-7

ProASIC3 DC and Switching Characteristics

Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks

Static Power

P_DC3(mW)²

Dynamic Power

C_LOAD(pF)

V_CCI(V)

_AC10(µW/MHz)³

Single-Ended

3.3 V LVTTL /

3.3

–

468.67

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

2.5

1.8

1.5

–

267.48

149.46

103.12

1.5 V LVCMOS

(JESD8-11)

3.3 V PCI

3.3 V PCI-X

Differential

LVDS

3.3

–

201.02

–

2.5

3.3

7.74

88.92

LVPECL

19.54

166.52

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. P_DC3is the static power (where applicable) measured on V_CCI

3. P_AC10is the total dynamic power measured on V_CCand V_CCI

Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings¹

Applicable to Standard Plus I/O Banks

Static Power

P_DC3(mW)²

Dynamic Power

P_AC10(µW/MHz)³

C_LOAD(pF)

V_CCI(V)

Single-Ended

3.3 V LVTTL /

3.3

–

452.67

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

2.5

1.8

1.5

–

258.32

133.59

92.84

1.5 V LVCMOS

(JESD8-11)

3.3 V PCI

3.3 V PCI-X

Notes:

3.3

–

184.92

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. P_DC3is the static power (where applicable) measured on VMV.

3. P_AC10is the total dynamic power measured on V_CCand VMV.

2-8

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings ¹

Applicable to Standard I/O Banks

Static Power

P_DC3(mW) ²

Dynamic Power

C_LOAD(pF)

V_CCI(V)

_AC10(µW/MHz) ³

Single-Ended

3.3 V LVTTL /

3.3

–

431.08

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

2.5

1.8

1.5

–

247.36

128.46

89.46

1.5 V LVCMOS

(JESD8-11)

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. P_DC3is the static power (where applicable) measured on V_CCI

3. P_AC10is the total dynamic power measured on V_CCand V_CCI

v1.3

2-9

ProASIC3 DC and Switching Characteristics

Power Consumption of Various Internal Resources

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices

Device Specific Dynamic Contributions

(µW/MHz)

Parameter

P_AC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

14.50 12.80 12.80 11.00 11.00 9.30 9.30 9.30

P_AC2

2.48 1.85 1.35 1.58 0.81 0.81 0.41 0.41

P_AC3

0.81

0.12

P_AC4

Clock contribution of a VersaTile used as a

sequential module

P_AC5

P_AC6

P_AC7

First contribution of a VersaTile used as a

sequential module

0.07

0.29

0.70

Second contribution of a VersaTile used as a

sequential module

Contribution of

a VersaTile used as a

combinatorial Module

P_AC8

P_AC9

Average contribution of a routing net

Contribution of an I/O input pin (standard

dependent)

See Table 2-8 on page 2-6 through

Table 2-10 on page 2-7.

P_AC10

P_AC11

P_AC12

P_AC13

Contribution of an I/O output pin (standard

dependent)

See Table 2-11 on page 2-8 through

Table 2-13 on page 2-9.

Average contribution of a RAM block during

a read operation

25.00

30.00

2.60

Average contribution of a RAM block during

a write operation

Dynamic contribution for PLL

Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power

spreadsheet calculator or SmartPower tool in Libero^®Integrated Design Environment (IDE) software.

2-10

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices

Definition

Device Specific Static Power (mW)

Parameter

P_DC1

Array static power in Active mode

See Table 2-7 on page 2-6.

P_DC2

I/O input pin static power (standard-dependent)

See Table 2-8 on page 2-6 through

Table 2-10 on page 2-7.

P_DC3

I/O output pin static power (standard-dependent)

See Table 2-11 on page 2-8 through

Table 2-13 on page 2-9.

P_DC4

P_DC5

Static PLL contribution

2.55 mW

Bank quiescent power (V_CCI-dependent)

See Table 2-7 on page 2-6.

Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel

v1.3

2-11

ProASIC3 DC and Switching Characteristics

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock

generated

•

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on

page 2-14.

•

Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-17 on page 2-14.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-17 on page 2-14. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

P_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

STAT

P_STAT= P_DC1+ N_INPUTS* P_DC2+ N_OUTPUTS* P_DC3

N_INPUTSis the number of I/O input buffers used in the design.

N_OUTPUTSis the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (P_AC1+ N_SPINE*P_AC2+ N_ROW*P_AC3+ N_S-CELL* P_AC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in

Table 2-16 on page 2-14.

_ROWis the number of VersaTile rows used in the design—guidelines are provided in Table 2-16

on page 2-14.

_CLKis the global clock signal frequency.

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

_AC1, P_AC2, P_AC3, and P_AC4are device-dependent.

Sequential Cells Contribution—P

S-CELL

P_S-CELL= N_S-CELL* (P_AC5+ α₁/ 2 * P_AC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.

F_CLKis the global clock signal frequency.

2-12

v1.3

ProASIC3 DC and Switching Characteristics

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* α₁/ 2 * P_AC7* F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.

F_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * α₁/ 2 * P_AC8* F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14.

_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* α₂/ 2 * P_AC9* F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-14.

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* α₂/ 2 * β₁* P_AC10* F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-14.

β₁is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-14.

F_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= P_AC11* N_BLOCKS* F_READ-CLOCK* β₂+ P_AC12* N_BLOCK* F_WRITE-CLOCK* β₃

N_BLOCKSis the number of RAM blocks used in the design.

_READ-CLOCKis the memory read clock frequency.

β₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

β₃is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on

page 2-14.

PLL Contribution—P

PLL

P_PLL= P_DC4+ P_AC13*F_CLKOUT

F_CLKOUTis the output clock frequency.¹

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated

by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include

each output clock in the formula by adding its corresponding contribution (P_AC14* F_CLKOUTproduct) to the total PLL

contribution.

v1.3

2-13

ProASIC3 DC and Switching Characteristics

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

α₁

α₂

10%

Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

β₁

β₂

β₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

2-14

v1.3

ProASIC3 DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

LVPECL (Applicable to

Advanced I/O Banks Only)L

_PD= 0.56 ns

t_PD= 0.49 ns

t_DP= 1.34 ns

I/O Module

(Non-Registered)

Combinational Cell

Output drive strength = 12 mA

High slew rate

LVTTL

t_DP= 2.64 ns (Advanced I/O Banks)

t_PD= 0.87 ns

I/O Module

(Non-Registered)

Combinational Cell

I/O Module

(Registered)

Output drive strength = 8 mA

LVTTL

_PY= 1.05 ns

High slew rate

_DP= 3.66 ns (Advanced I/O Banks)

LVPECL

(Applicable

to Advanced

I/O Banks only)

t_PD= 0.47 ns

I/O Module

(Non-Registered)

Combinational Cell

Output drive strength = 4 mA

High slew rate

LVCMOS 1.5 V

_ICLKQ= 0.24 ns

_DP= 3.97 ns (Advanced I/O Banks)

t_PD= 0.47 ns

t_ISUD= 0.26 ns

Input LVTTL

Clock

I/O Module

(Registered)

Combinational Cell

t_PY= 0.76 ns (Advanced I/O Banks)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

I/O Module

(Non-Registered)

t_PD= 0.47 ns

t_DP= 2.64 ns

(Advanced I/O Banks)

t_OCLKQ= 0.59 ns

_OSUD= 0.31 ns

_CLKQ= 0.55 ns

LVDS,

BLVDS,

M-LVDS

t_SUD= 0.43 ns

Input LVTTL

Clock

Input LVTTL

Clock

(Applicable for

Advanced I/O

Banks only)

t_PY= 1.20 ns

t_PY= 0.76 ns

(Advanced I/O Banks)

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (T_J= 70°C), Worst Case

_CC= 1.425 V

v1.3

2-15

ProASIC3 DC and Switching Characteristics

t_PY

t_DIN

PAD

DIN

CLK

To Array

I/O Interface

t_PY= MAX(t_PY(R), t_PY(F))

t_DIN= MAX(t_DIN(R), t_DIN(F))

V_IH

V_trip

V_CC

V_IL

PAD

50%

GND

t_PY

(R)

t_PY

(F)

V_CC

50%

DIN

t_DOUT

(R)

GND

t_DOUT

(F)

Figure 2-3 • Input Buffer Timing Model and Delays (example)

2-16

v1.3

ProASIC3 DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(F)

V_CC

(R)

50%

V_CC

0 V

50%

0 V

DOUT

PAD

V_OH

V_trip

V_OL

t_DP

(R)

t_DP

(F)

Figure 2-4 • Output Buffer Model and Delays (example)

v1.3

2-17

ProASIC3 DC and Switching Characteristics

EOUT

CLK

t , t , t , t , t , t

ZL ZH HZ LZ ZLS ZHS

EOUT

PAD

DOUT

CLK

= MAX(t

(r), t

(f))

I/O Interface

EOUT

50%

EOUT (F)

EOUT (R)

50%

EOUT

PAD

CCI

90% V

CCI

trip

10% V

CCI

50%

EOUT (F)

EOUT (R)

50%

EOUT

PAD

50%

ZHS

ZLS

trip

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

2-18

v1.3

ProASIC3 DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

12 12

Drive

Slew

I/O Standard

Strength Rate Min, V

Max, V

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

High

–0.3

0.8

3.6

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

High

0.7

1.7

3.6

0.7

1.7

12 12

–0.3 0.35 * V_CCI0.65 * V_CCI

–0.3 0.30 * V_CCI0.7 * V_CCI

0.45

V_CCI– 0.45 12 12

0.25 * V_CCI0.75 * V_CCI12 12

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Note: Currents are measured at 85°C junction temperature.

Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

12 12

Drive

Slew

I/O Standard Strength Rate Min, V

Max, V

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

High

–0.3

0.8

3.6

2.5 V LVCMOS 12 mA

High

0.7

1.7

3.6

0.7

1.7

12 12

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

8 mA

4 mA

–0.3 0.35 * V_CCI0.65 * V_CCI

–0.3 0.30 * V_CCI0.7 * V_CCI

0.45

V_CCI– 0.45

0.25 * V_CCI0.75 * V_CCI

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Note: Currents are measured at 85°C junction temperature.

Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard I/O Banks

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

Drive

Slew

I/O Standard Strength Rate Min, V

Max, V

3.3 V LVTTL /

3.3 V LVCMOS

8 mA

High

–0.3

0.8

3.6

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

8 mA

4 mA

2 mA

High

0.7

1.7

3.6

0.7

1.7

–0.3 0.35 * V_CCI0.65 * V_CCI

–0.3 0.30 * V_CCI0.7 * V_CCI

0.45

V_CCI– 0.45

0.25 * V_CCI0.75 * V_CCI

Note: Currents are measured at 85°C junction temperature.

v1.3

2-19

ProASIC3 DC and Switching Characteristics

Table 2-21 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

Commercial¹

Industrial²

I_IL

µA

I_IH

µA

I_IL

µA

I_IH

µA

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

3.3 V PCI-X

Notes:

1. Commercial range (0°C < T_A< 70°C)

2. Industrial range (–40°C < T_A< 85°C)

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-22 • Summary of AC Measuring Points

Standard

Measuring Trip Point (V_trip

)

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

1.4 V

1.2 V

0.90 V

0.75 V

0.285 * V_CCI(RR)

0.615 * V_CCI(FF)

0.285 * V_CCI(RR)

0.615 * V_CCI(FF)

3.3 V PCI-X

Table 2-23 • I/O AC Parameter Definitions

Parameter

Parameter Definition

Data to Pad delay through the Output Buffer

Pad to Data delay through the Input Buffer

t_DP

t_PY

t_DOUT

t_EOUT

t_DIN

t_HZ

Data to Output Buffer delay through the I/O interface

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Enable to Pad delay through the Output Buffer—HIGH to Z

Enable to Pad delay through the Output Buffer—Z to HIGH

Enable to Pad delay through the Output Buffer—LOW to Z

Enable to Pad delay through the Output Buffer—Z to LOW

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

2-20

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case V_CC= 1.425 V,

Worst Case V_CCI= 3.0 V

Advanced I/O Banks

I/O Standard

3.3 V LVTTL /

High 35

–

0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

High 35

–

0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns

0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns

0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns

Per PCI spec. High 10 25 ²0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

Per PCI-X spec. High 10 25 ²0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

3.3 V PCI-X

LVDS

High

–

0.49 1.37 0.03 1.20

0.49 1.34 0.03 1.05

–

LVPECL

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

v1.3

2-21

ProASIC3 DC and Switching Characteristics

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case V_CC= 1.425 V, Worst Case

V_CCI= 3.0 V

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL /

12 mA

High 35 pF

–

0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

8 mA

4 mA

High 35 pF

–

0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns

0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns

0.49 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns

Per PCI spec. High 10 pF 25 ²0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

Per PCI-X spec. High 10 pF 25 ²0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

3.3 V PCI-X

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst Case V_CC= 1.425 V,

Worst Case V_CCI= 3.0 V

Standard I/O Banks

I/O Standard

3.3 V LVTTL /

8 mA High 35 pF

–

0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

Notes:

8 mA High 35 pF

4 mA High 35 pF

2 mA High 35 pF

–

0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns

0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns

0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-56 for connectivity. This resistor is not required during normal operation.

2-22

v1.3

ProASIC3 DC and Switching Characteristics

Detailed I/O DC Characteristics

Table 2-27 • Input Capacitance

Symbol

C_IN

Definition

Input capacitance

Input capacitance on the clock pin

Conditions

Min. Max. Units

V_IN= 0, f = 1.0 MHz

C_INCLK

Table 2-28 • I/O Output Buffer Maximum Resistances¹

Applicable to Advanced I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

(Ω)²

100

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

300

150

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

2.5 V LVCMOS

100

200

100

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

1.8 V LVCMOS

200

100

225

112

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

1.5 V LVCMOS

200

100

224

112

4 mA

6 mA

8 mA

12 mA

Per PCI/PCI-X specification

3.3 V PCI/PCI-X

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on V_CCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

v1.3

2-23

ProASIC3 DC and Switching Characteristics

Table 2-29 • I/O Output Buffer Maximum Resistances ¹

Applicable to Standard Plus I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

3.3 V LVTTL / 3.3 V LVCMOS

Drive Strength

(Ω)²

(Ω)³

2 mA

100

300

150

4 mA

6 mA

8 mA

12 mA

16 mA

2.5 V LVCMOS

2 mA

100

200

100

4 mA

6 mA

8 mA

12 mA

1.8 V LVCMOS

1.5 V LVCMOS

2 mA

200

100

225

112

4 mA

6 mA

8 mA

2 mA

4 mA

200

100

224

112

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on V_CCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

2-24

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-30 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

(Ω)²

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

100

300

150

200

100

225

112

224

2.5 V LVCMOS

1.8 V LVCMOS

100

200

100

200

1.5 V LVCMOS

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on V_CCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

Table 2-31 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

(Ω)

V_CCI

Min.

10 k

11 k

18 k

19 k

Max.

Min.

10 k

12 k

17 k

19 k

Max.

45 k

3.3 V

2.5 V

1.8 V

1.5 V

Notes:

45 k

55 k

70 k

90 k

74 k

110 k

140 k

1. R_{(WEAK PULL-UP-MAX)}= (V_OLspec) / I_{(WEAK PULL-UP-MIN)}

2. R_{(WEAK PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_{(WEAK PULL-UP-MIN)}

v1.3

2-25

ProASIC3 DC and Switching Characteristics

Table 2-32 • I/O Short Currents I_OSH/I_OSL

Applicable to Advanced I/O Banks

Drive Strength

_OSL(mA)*

I_OSH(mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

109

127

181

103

132

268

3.3 V LVCMOS

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

109

127

181

103

132

268

2.5 V LVCMOS

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

124

169

1.8 V LVCMOS

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

1.5 V LVCMOS

4 mA

6 mA

8 mA

12 mA

Per PCI/PCI-X specification

3.3 V PCI/PCI-X

109

103

* T_J= 100°C

2-26

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-33 • I/O Short Currents I_OSH/I_OSL

Applicable to Standard Plus I/O Banks

Drive Strength

_OSL(mA)*

I_OSH(mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

103

4 mA

6 mA

8 mA

12 mA

109

16 mA

2.5 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

1.8 V LVCMOS

1.5 V LVCMOS

2 mA

4 mA

103

6 mA

8 mA

2 mA

4 mA

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

109

* T_J= 100°C

Table 2-34 • I/O Short Currents I_OSH/I_OSL

Applicable to Standard I/O Banks

Drive Strength

_OSL(mA)*

I_OSH(mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

* T_J= 100°C

v1.3

2-27

ProASIC3 DC and Switching Characteristics

The length of time an I/O can withstand I_OSH/I_OSLevents depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-35 • Duration of Short Circuit Event before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

110°C

6 months

3 months

Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.) Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS

No requirement

10 ns *

20 years (110°C)

10 years (100°C)

LVDS/B-LVDS/

M-LVDS/LVPECL

* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the

board noise. Actel recommends signal integrity evaluation/characterization of the system to

ensure that there is no excessive noise coupling into input signals.

2-28

v1.3

ProASIC3 DC and Switching Characteristics

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-37 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.8

3.6

0.4

2.4

10 10

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

109

127

181

103

132

268

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-38 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

–0.3

0.8

3.6

0.4

2.4

10 10

12 12

16 16

109

103

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

v1.3

2-29

ProASIC3 DC and Switching Characteristics

Table 2-39 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.8

3.6

0.4

2.4

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-6 • AC Loading

Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

_LOAD(pF)

3.3

1.4

* Measuring point = V_trip.See Table 2-22 on page 2-20 for a complete table of trip points.

2-30

v1.3

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

9.37 7.91 3.18 3.14 12.05 10.60

7.80 6.59 2.65 2.61 10.03

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

4 mA

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

9.20 0.05 1.22

7.66 0.04 1.02

6.51 0.04 0.86

5.72 0.03 0.76

5.89 0.05 1.22

4.91 0.04 1.02

4.17 0.04 0.86

3.66 0.03 0.76

5.89 0.05 1.22

4.91 0.04 1.02

4.17 0.04 0.86

3.66 0.03 0.76

4.24 0.05 1.22

3.53 0.04 1.02

3.00 0.04 0.86

2.64 0.03 0.76

4.00 0.05 1.22

3.33 0.04 1.02

2.83 0.04 0.86

2.49 0.03 0.76

3.69 0.05 1.22

3.08 0.04 1.02

2.62 0.04 0.86

2.30 0.03 0.76

8.82

7.51

6.59

7.57

6.31

5.36

4.71

7.57

6.31

5.36

4.71

6.08

5.06

4.30

3.78

5.77

4.80

4.08

3.58

5.23

4.35

3.70

3.25

6.63 5.60 2.25 2.22

5.82 4.92 1.98 1.95

6.00 4.89 3.59 3.85

5.00 4.07 2.99 3.20

4.25 3.46 2.54 2.73

3.73 3.04 2.23 2.39

6.00 4.89 3.59 3.85

5.00 4.07 2.99 3.20

4.25 3.46 2.54 2.73

3.73 3.04 2.23 2.39

4.32 3.39 3.86 4.30

3.60 2.82 3.21 3.58

3.06 2.40 2.73 3.05

2.69 2.11 2.40 2.68

4.08 3.08 3.92 4.42

3.39 2.56 3.26 3.68

2.89 2.18 2.77 3.13

2.53 1.91 2.44 2.75

3.76 2.54 3.99 4.88

3.13 2.12 3.32 4.06

2.66 1.80 2.83 3.45

2.34 1.58 2.48 3.03

8.54

7.49

8.69

7.23

6.15

5.40

8.69

7.23

6.15

5.40

7.01

5.83

4.96

4.36

6.76

5.63

4.79

4.20

6.45

5.37

4.57

4.01

–2

6 mA

–F

Std.

–1

–2

8 mA

–F

Std.

–1

–2

12 mA

16 mA

24 mA

Notes:

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-31

ProASIC3 DC and Switching Characteristics

Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

12.55 10.69 3.18 2.95 15.23 13.37

8.90 2.64 2.46 12.68 11.13

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

4 mA

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

12.32 0.05 1.22 0.51

10.26 0.04 1.02 0.43

8.72 0.04 0.86 0.36

7.66 0.03 0.76 0.32

8.74 0.05 1.22 0.51

7.27 0.04 1.02 0.43

6.19 0.04 0.86 0.36

5.43 0.03 0.76 0.32

8.74 0.05 1.22 0.51

7.27 0.04 1.02 0.43

6.19 0.04 0.86 0.36

5.43 0.03 0.76 0.32

6.70 0.05 1.22 0.51

5.58 0.04 1.02 0.43

4.75 0.04 0.86 0.36

4.17 0.03 0.76 0.32

6.25 0.05 1.22 0.51

5.21 0.04 1.02 0.43

4.43 0.04 0.86 0.36

3.89 0.03 0.76 0.32

5.83 0.05 1.22 0.51

4.85 0.04 1.02 0.43

4.13 0.04 0.86 0.36

3.62 0.03 0.76 0.32

10.45

8.89

7.80

8.90

7.41

6.30

5.53

8.90

7.41

6.30

5.53

6.83

5.68

4.84

4.24

6.37

5.30

4.51

3.96

5.93

4.94

4.20

3.69

7.57 2.25 2.09 10.79

6.64 1.98 1.83 9.47

9.47

8.31

–2

6 mA

–F

7.55 3.58 3.65 11.59 10.23

Std.

–1

6.28 2.98 3.04 9.65

5.35 2.54 2.59 8.20

4.69 2.23 2.27 7.20

8.52

7.25

6.36

–2

8 mA

–F

7.55 3.58 3.65 11.59 10.23

Std.

–1

6.28 2.98 3.04 9.65

5.35 2.54 2.59 8.20

4.69 2.23 2.27 7.20

5.85 3.85 4.10 9.51

4.87 3.21 3.42 7.92

4.14 2.73 2.91 6.74

3.64 2.39 2.55 5.91

5.48 3.91 4.22 9.06

4.56 3.26 3.51 7.54

3.88 2.77 2.99 6.41

3.41 2.43 2.62 5.63

5.46 3.98 4.67 8.62

4.54 3.32 3.88 7.18

3.87 2.82 3.30 6.10

3.39 2.48 2.90 5.36

8.52

7.25

6.36

8.54

7.11

6.05

5.31

8.17

6.80

5.79

5.08

8.15

6.78

5.77

5.06

–2

12 mA

16 mA

24 mA

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-32

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

4 mA

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

8.65 0.05 1.20

7.20 0.04 1.00

6.13 0.04 0.85

5.38 0.03 0.75

5.41 0.05 1.20

4.50 0.04 1.00

3.83 0.04 0.85

3.36 0.03 0.75

5.41 0.05 1.20

4.50 0.04 1.00

3.83 0.04 0.85

3.36 0.03 0.75

3.80 0.05 1.20

3.16 0.04 1.00

2.69 0.04 0.85

2.36 0.03 0.75

3.80 0.05 1.20

3.16 0.04 1.00

2.69 0.04 0.85

2.36 0.03 0.75

8.81 7.55 2.73 2.81 11.50 10.24

7.34 6.29 2.27 2.34

6.24 5.35 1.93 1.99

5.48 4.69 1.70 1.75

5.51 4.58 3.10 3.45

4.58 3.82 2.58 2.88

3.90 3.25 2.19 2.45

3.42 2.85 1.92 2.15

5.51 4.58 3.10 3.45

4.58 3.82 2.58 2.88

3.90 3.25 2.19 2.45

3.42 2.85 1.92 2.15

3.87 3.10 3.35 3.87

3.22 2.58 2.79 3.22

2.74 2.20 2.37 2.74

2.40 1.93 2.08 2.41

3.87 3.10 3.35 3.87

3.22 2.58 2.79 3.22

2.74 2.20 2.37 2.74

2.40 1.93 2.08 2.41

9.57

8.14

7.15

8.19

6.82

5.80

5.09

8.19

6.82

5.80

5.09

6.55

5.45

4.64

4.07

6.55

5.45

4.64

4.07

8.52

7.25

6.36

7.27

6.05

5.15

4.52

7.27

6.05

5.15

4.52

5.79

4.82

4.10

3.60

5.79

4.82

4.10

3.60

–2

6 mA

–F

Std.

–1

–2

8 mA

–F

Std.

–1

–2

12 mA

16 mA

Notes:

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-33

ProASIC3 DC and Switching Characteristics

Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

11.84 10.12 2.74 2.65 14.53 12.81

8.42 2.28 2.21 12.09 10.66

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

4 mA

6 mA

8 mA

12 mA

16 mA

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

11.63 0.05 1.20 0.51

9.68 0.04 1.00 0.43

8.23 0.04 0.85 0.36

7.23 0.03 0.75 0.32

8.05 0.05 1.20 0.51

6.70 0.04 1.00 0.43

5.70 0.04 0.85 0.36

5.00 0.03 0.75 0.32

8.05 0.05 1.20 0.51

6.70 0.04 1.00 0.43

5.70 0.04 0.85 0.36

5.00 0.03 0.75 0.32

6.06 0.05 1.20 0.51

5.05 0.04 1.00 0.43

4.29 0.04 0.85 0.36

3.77 0.03 0.75 0.32

6.06 0.05 1.20 0.51

5.05 0.04 1.00 0.43

4.29 0.04 0.85 0.36

3.77 0.03 0.75 0.32

9.86

8.39

7.36

8.20

6.82

5.80

5.10

8.20

6.82

5.80

5.10

6.18

5.14

4.37

3.84

6.18

5.14

4.37

3.84

7.17 1.94 1.88 10.29

6.29 1.70 1.65 9.03

7.07 3.10 3.29 10.88

5.89 2.58 2.74 9.06

5.01 2.20 2.33 7.71

4.40 1.93 2.05 6.76

7.07 3.10 3.29 10.88

5.89 2.58 2.74 9.06

5.01 2.20 2.33 7.71

4.40 1.93 2.05 6.76

5.42 3.35 3.70 8.86

4.51 2.79 3.08 7.38

3.84 2.38 2.62 6.28

3.37 2.09 2.30 5.51

5.42 3.35 3.70 8.86

4.51 2.79 3.08 7.38

3.84 2.38 2.62 6.28

3.37 2.09 2.30 5.51

9.07

7.96

9.76

8.12

6.91

6.06

9.76

8.12

6.91

6.06

8.10

6.75

5.74

5.04

8.10

6.75

5.74

5.04

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-34

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

–F

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

t_DIN

0.05

0.04

0.03

0.05

0.04

0.03

0.05

0.04

0.03

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

4 mA

6 mA

8 mA

Notes:

8.49

7.07

6.01

5.28

8.49

7.07

6.01

5.28

5.30

4.41

3.75

3.29

5.30

4.41

3.75

3.29

1.20

1.00

0.85

0.75

1.20

1.00

0.85

0.75

1.20

1.00

0.85

0.75

1.20

1.00

0.85

0.75

8.65

7.20

6.12

5.37

8.65

7.20

6.12

5.37

5.40

4.49

3.82

3.36

5.40

4.49

3.82

3.36

7.48

6.23

5.30

4.65

7.48

6.23

5.30

4.65

4.51

3.75

3.19

2.80

4.51

3.75

3.19

2.80

2.49

2.07

1.76

1.55

2.49

2.07

1.76

1.55

2.88

2.39

2.04

1.79

2.88

2.39

2.04

1.79

2.58

2.15

1.83

1.60

2.58

2.15

1.83

1.60

3.23

2.69

2.29

2.01

3.23

2.69

2.29

2.01

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-35

ProASIC3 DC and Switching Characteristics

Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

–F

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

11.37

9.46

8.05

7.07

11.37

9.46

8.05

7.07

7.89

6.57

5.59

4.91

7.89

6.57

5.59

4.91

t_DIN

0.05

0.04

0.03

0.05

0.04

0.03

0.05

0.04

0.03

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

11.58

9.64

8.20

7.20

11.58

9.64

8.20

7.20

8.04

6.69

5.69

5.00

8.04

6.69

5.69

5.00

t_ZH

10.26

8.54

7.27

6.38

10.26

8.54

7.27

6.38

7.19

5.98

5.09

4.47

7.19

5.98

5.09

4.47

t_LZ

t_HZ

Units

2 mA

4 mA

6 mA

8 mA

1.20

1.00

0.85

0.75

1.20

1.00

0.85

0.75

1.20

1.00

0.85

0.75

1.20

1.00

0.85

0.75

2.49

2.07

1.76

1.55

2.49

2.07

1.76

1.55

2.88

2.40

2.04

1.79

2.88

2.40

2.04

1.79

2.45

2.04

1.73

1.52

2.45

2.04

1.73

1.52

3.09

2.57

2.19

1.92

3.09

2.57

2.19

1.92

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-36

v1.3

ProASIC3 DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.7

1.7

3.6

0.7

1.7

10 10

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

124

169

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3

0.7

1.7

3.6

0.7

1.7

10 10

12 12

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

v1.3

2-37

ProASIC3 DC and Switching Characteristics

Table 2-49 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

2.5 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.7

1.7

3.6

0.7

1.7

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-7 • AC Loading

Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

_LOAD(pF)

2.5

1.2

* Measuring point = V_trip.See Table 2-22 on page 2-20 for a complete table of trip points.

2-38

v1.3

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-51 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

9.41 10.41 3.22 2.77 12.09 13.09

2.68 2.30 10.07 10.90

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

4 mA

–F

Std.

–1

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

10.41 0.05 1.57

8.66

7.37

6.47

6.21

5.17

4.39

3.86

6.21

5.17

4.39

3.86

4.28

3.56

3.03

2.66

4.03

3.35

2.85

2.50

3.71

3.09

2.63

2.31

0.04 1.31

0.04 1.11

0.03 0.98

0.05 1.57

0.04 1.31

0.04 1.11

0.03 0.98

0.05 1.57

0.04 1.31

0.04 1.11

0.03 0.98

0.05 1.57

0.04 1.31

0.04 1.11

0.03 0.98

0.05 1.57

0.04 1.31

0.04 1.11

0.03 0.98

0.05 1.57

0.04 1.31

0.04 1.11

0.03 0.98

7.83

6.66

5.85

6.05

5.04

4.28

3.76

6.05

5.04

4.28

3.76

4.36

3.63

3.08

2.71

4.10

3.41

2.90

2.55

3.78

3.15

2.68

2.35

8.66

7.37

6.47

6.21

5.17

4.39

3.86

6.21

5.17

4.39

3.86

4.12

3.43

2.92

2.56

3.68

3.06

2.60

2.29

2.93

2.44

2.08

1.82

2.28 1.96

2.00 1.72

3.66 3.60

3.05 3.00

2.59 2.55

2.28 2.24

3.66 3.60

3.05 3.00

2.59 2.55

2.28 2.24

3.97 4.13

3.30 3.44

2.81 2.92

2.47 2.57

4.04 4.26

3.36 3.55

2.86 3.02

2.51 2.65

4.13 4.80

3.44 4.00

2.92 3.40

2.57 2.98

8.56

7.52

8.74

7.27

6.19

5.43

8.74

7.27

6.19

5.43

7.04

5.86

4.99

4.38

6.79

5.65

4.81

4.22

6.47

5.38

4.58

4.02

9.27

8.14

8.89

7.40

6.30

5.53

8.89

7.40

6.30

5.53

6.81

5.67

4.82

4.23

6.36

5.30

4.51

3.96

5.62

4.68

3.98

3.49

–2

6 mA

–F

Std.

–1

–2

8 mA

–F

Std.

–1

–2

12 mA

16 mA

24 mA

Notes:

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-39

ProASIC3 DC and Switching Characteristics

Table 2-52 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

4 mA

–F

Std.

–1

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

0.72

0.60

0.51

0.45

13.69 0.05 1.57 0.51

11.40 0.04 1.31 0.43

9.69 0.04 1.11 0.36

8.51 0.03 0.98 0.32

9.56 0.05 1.57 0.51

7.96 0.04 1.31 0.43

6.77 0.04 1.11 0.36

5.94 0.03 0.98 0.32

9.56 0.05 1.57 0.51

7.96 0.04 1.31 0.43

6.77 0.04 1.11 0.36

5.94 0.03 0.98 0.32

7.42 0.05 1.57 0.51

6.18 0.04 1.31 0.43

5.26 0.04 1.11 0.36

4.61 0.03 0.98 0.32

6.92 0.05 1.57 0.51

5.76 0.04 1.31 0.43

4.90 0.04 1.11 0.36

4.30 0.03 0.98 0.32

6.61 0.05 1.57 0.51

5.51 0.04 1.31 0.43

4.68 0.04 1.11 0.36

4.11 0.03 0.98 0.32

13.48 13.69 3.22 2.65 16.16 16.38

11.22 11.40 2.68 2.20 13.45 13.63

9.54

8.38

9.74

8.11

6.90

6.05

9.74

8.11

6.90

6.05

7.56

6.29

5.35

4.70

7.05

5.87

4.99

4.38

6.61

5.50

4.68

4.11

9.69 2.28 1.88 11.44 11.60

8.51 2.00 1.65 10.05 10.18

9.39 3.66 3.47 12.43 12.07

7.81 3.05 2.89 10.34 10.05

–2

6 mA

–F

Std.

–1

6.65 2.59 2.46 8.80

5.84 2.28 2.16 7.72

8.55

7.50

–2

8 mA

–F

9.39 3.66 3.47 12.43 12.07

7.81 3.05 2.89 10.34 10.05

Std.

–1

6.65 2.59 2.46 8.80

5.84 2.28 2.16 7.72

7.11 3.97 3.99 10.25

5.92 3.30 3.32 8.53

5.03 2.81 2.83 7.26

4.42 2.47 2.48 6.37

6.64 4.04 4.13 9.74

5.53 3.36 3.44 8.11

4.70 2.86 2.92 6.90

4.13 2.51 2.57 6.05

6.61 4.13 4.65 9.30

5.51 3.43 3.87 7.74

4.68 2.92 3.29 6.58

4.11 2.56 2.89 5.78

8.55

7.50

9.80

8.15

6.94

6.09

9.32

7.76

6.60

5.80

9.30

7.74

6.59

5.78

–2

12 mA

16 mA

24 mA

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-40

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-53 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

4 mA

6 mA

8 mA

12 mA

Notes:

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

9.94 0.05 1.56

8.28 0.04 1.30

7.04 0.04 1.10

6.18 0.03 0.97

5.83 0.05 1.56

4.85 0.04 1.30

4.13 0.04 1.10

3.62 0.03 0.97

5.83 0.05 1.56

4.85 0.04 1.30

4.13 0.04 1.10

3.62 0.03 0.97

3.85 0.05 1.56

3.21 0.04 1.30

2.73 0.04 1.10

2.39 0.03 0.97

8.90 9.94 2.70 2.49 11.58 12.63

7.41 8.28 2.25 2.07

6.30 7.04 1.92 1.76

5.53 6.18 1.68 1.55

5.58 5.83 3.11 3.26

4.65 4.85 2.59 2.71

3.95 4.13 2.20 2.31

3.47 3.62 1.93 2.02

5.58 5.83 3.11 3.26

4.65 4.85 2.59 2.71

3.95 4.13 2.20 2.31

3.47 3.62 1.93 2.02

3.92 3.77 3.39 3.74

3.27 3.14 2.82 3.11

2.78 2.67 2.40 2.65

2.44 2.35 2.11 2.32

9.64

8.20

7.20

8.27

6.88

5.85

5.14

8.27

6.88

5.85

5.14

6.61

5.50

4.68

4.11

10.51

8.94

7.85

8.52

7.09

6.03

5.29

8.52

7.09

6.03

5.29

6.46

5.38

4.57

4.02

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-41

ProASIC3 DC and Switching Characteristics

Table 2-54 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

4 mA

6 mA

8 mA

12 mA

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

13.02 0.05 1.56 0.51

10.84 0.04 1.30 0.43

9.22 0.04 1.10 0.36

8.10 0.03 0.97 0.32

8.85 0.05 1.56 0.51

7.37 0.04 1.30 0.43

6.27 0.04 1.10 0.36

5.50 0.03 0.97 0.32

8.85 0.05 1.56 0.51

7.37 0.04 1.30 0.43

6.27 0.04 1.10 0.36

5.50 0.03 0.97 0.32

6.76 0.05 1.56 0.51

5.63 0.04 1.30 0.43

4.79 0.04 1.10 0.36

4.20 0.03 0.97 0.32

12.78 13.02 2.71 2.39 15.46 15.71

10.64 10.84 2.26 1.99 12.87 13.08

9.05

7.94

9.01

7.50

6.38

5.60

9.01

7.50

6.38

5.60

6.89

5.73

4.88

4.28

9.22 1.92 1.69 10.95 11.12

8.10 1.68 1.49 9.61 9.77

8.84 3.11 3.14 11.70 11.53

–2

–F

Std.

–1

7.36 2.59 2.61 9.74

6.26 2.20 2.22 8.29

5.50 1.93 1.95 7.27

9.60

8.16

7.17

–2

–F

8.84 3.11 3.14 11.70 11.53

Std.

–1

7.36 2.59 2.61 9.74

6.26 2.20 2.22 8.29

5.50 1.93 1.95 7.27

6.61 3.40 3.62 9.57

5.51 2.83 3.01 7.97

4.68 2.41 2.56 6.78

4.11 2.11 2.25 5.95

9.60

8.16

7.17

9.30

7.74

6.59

5.78

–2

–F

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-42

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-55 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

–F

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

t_DIN

0.05

0.04

0.03

0.05

0.04

0.03

0.05

0.04

0.03

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

4 mA

6 mA

8 mA

Notes:

9.86

8.20

6.98

6.13

9.86

8.20

6.98

6.13

5.72

4.77

4.05

3.56

5.72

4.77

4.05

3.56

1.55

1.29

1.10

0.96

1.55

1.29

1.10

0.96

1.55

1.29

1.10

0.96

1.55

1.29

1.10

0.96

8.70

7.24

6.16

5.41

8.70

7.24

6.16

5.41

5.47

4.55

3.87

3.40

5.47

4.55

3.87

3.40

9.86

8.20

6.98

6.13

9.86

8.20

6.98

6.13

5.72

4.77

4.05

3.56

5.72

4.77

4.05

3.56

2.44

2.03

1.73

1.52

2.44

2.03

1.73

1.52

2.86

2.38

2.03

1.78

2.86

2.38

2.03

1.78

2.29

1.91

1.62

1.43

2.29

1.91

1.62

1.43

3.07

2.55

2.17

1.91

3.07

2.55

2.17

1.91

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-43

ProASIC3 DC and Switching Characteristics

Table 2-56 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

–F

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

13.21

11.00

9.35

8.21

13.21

11.00

9.35

8.21

9.01

7.50

6.38

5.60

9.01

7.50

6.38

5.60

t_DIN

0.05

0.04

0.03

0.05

0.04

0.03

0.05

0.04

0.03

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

13.21

11.00

9.35

8.21

13.21

11.00

9.35

8.21

9.01

7.50

6.38

5.60

9.01

7.50

6.38

5.60

t_LZ

t_HZ

Units

2 mA

4 mA

6 mA

8 mA

1.55

1.29

1.10

0.96

1.55

1.29

1.10

0.96

1.55

1.29

1.10

0.96

1.55

1.29

1.10

0.96

12.46

10.37

8.83

7.75

12.46

10.37

8.83

7.75

8.84

7.36

6.26

5.49

8.84

7.36

6.26

5.49

2.44

2.03

1.73

1.52

2.44

2.03

1.73

1.52

2.87

2.39

2.03

1.78

2.87

2.39

2.03

1.78

2.20

1.83

1.56

1.37

2.20

1.83

1.56

1.37

2.96

2.46

2.10

1.84

2.96

2.46

2.10

1.84

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-44

v1.3

ProASIC3 DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-57 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI

3.6

0.45 V_CCI– 0.45

10 10

–0.3 0.35 * V_CCI0.65 * V_CCI

0.45 V_CCI– 0.45 12 12

0.45 V_CCI– 0.45 16 16

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-58 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSH

I_IL

I_IH

Drive

Max., Max.,

Strength Min., V Max., V

Min., V

Max., V Max., V

Min., V

mA mA mA¹mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.35 * V_CCI0.65 * V_CCI

3.6

0.45

V_CCI– 0.45

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

v1.3

2-45

ProASIC3 DC and Switching Characteristics

Table 2-59 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSH

I_IL

I_IH

Drive

Max., Max.,

Strength Min., V Max., V

Min., V

Max., V Max., V

Min., V

mA mA mA¹mA¹µA²µA²

2 mA

4 mA

Notes:

–0.3

0.35 * V_CCI0.65 * V_CCI

3.6

0.45

V_CCI– 0.45

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-8 • AC Loading

Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

_LOAD(pF)

1.8

0.9

* Measuring point = V_trip.See Table 2-22 on page 2-20 for a complete table of trip points.

2-46

v1.3

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-61 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

10.97 14.25 3.33 1.99 13.66 16.94

11.86 2.77 1.66 11.37 14.10

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

14.25 0.05 1.46 0.51

11.86 0.04 1.22 0.43

10.09 0.04 1.04 0.36

8.86 0.03 0.91 0.32

8.31 0.05 1.46 0.51

6.91 0.04 1.22 0.43

5.88 0.04 1.04 0.36

5.16 0.03 0.91 0.32

5.34 0.05 1.46 0.51

4.45 0.04 1.22 0.43

3.78 0.04 1.04 0.36

3.32 0.03 0.91 0.32

4.71 0.05 1.46 0.51

3.92 0.04 1.22 0.43

3.34 0.04 1.04 0.36

2.93 0.03 0.91 0.32

4.24 0.05 1.46 0.51

3.53 0.04 1.22 0.43

3.01 0.04 1.04 0.36

2.64 0.03 0.91 0.32

4.24 0.05 1.46 0.51

3.53 0.04 1.22 0.43

3.01 0.04 1.04 0.36

2.64 0.03 0.91 0.32

9.14

7.77

6.82

7.04

5.86

4.99

4.38

5.02

4.18

3.56

3.12

4.72

3.93

3.34

2.93

4.32

3.60

3.06

2.69

4.32

3.60

3.06

2.69

10.09 2.36 1.41 9.67

8.86 2.07 1.24 8.49

8.31 3.87 3.41 9.73

6.91 3.22 2.84 8.10

5.88 2.74 2.41 6.89

5.16 2.41 2.12 6.05

5.34 4.24 4.06 7.71

4.45 3.53 3.38 6.42

3.78 3.00 2.88 5.46

3.32 2.64 2.53 4.79

4.71 4.32 4.23 7.40

3.92 3.60 3.52 6.16

3.34 3.06 3.00 5.24

2.93 2.69 2.63 4.60

3.65 4.45 4.90 7.01

3.04 3.70 4.08 5.84

2.59 3.15 3.47 4.96

2.27 2.76 3.05 4.36

3.65 4.45 4.90 7.01

3.04 3.70 4.08 5.84

2.59 3.15 3.47 4.96

2.27 2.76 3.05 4.36

11.99

10.53

10.99

9.15

7.78

6.83

8.03

6.68

5.69

4.99

7.40

6.16

5.24

4.60

6.34

5.28

4.49

3.94

6.34

5.28

4.49

3.94

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-47

ProASIC3 DC and Switching Characteristics

Table 2-62 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34

15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77

13.21 0.04 1.04 0.36 12.01 13.21 2.36 1.36 13.91 15.11

11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27

12.58 0.05 1.46 0.51 12.51 12.58 3.88 3.28 15.19 15.27

10.48 0.04 1.22 0.43 10.41 10.48 3.23 2.73 12.65 12.71

–2

–F

Std.

–1

8.91 0.04 1.04 0.36

7.82 0.03 0.91 0.32

9.67 0.05 1.46 0.51

8.05 0.04 1.22 0.43

6.85 0.04 1.04 0.36

6.01 0.03 0.91 0.32

9.01 0.05 1.46 0.51

7.50 0.04 1.22 0.43

6.38 0.04 1.04 0.36

5.60 0.03 0.91 0.32

8.76 0.05 1.46 0.51

7.29 0.04 1.22 0.43

6.20 0.04 1.04 0.36

5.45 0.03 0.91 0.32

8.76 0.05 1.46 0.51

7.29 0.04 1.22 0.43

6.20 0.04 1.04 0.36

5.45 0.03 0.91 0.32

8.86

7.77

9.85

8.20

6.97

6.12

9.18

7.64

6.50

5.71

8.69

7.23

6.15

5.40

8.69

7.23

6.15

5.40

8.91 2.75 2.33 10.76 10.81

7.82 2.41 2.04 9.44 9.49

–2

–F

9.42 4.25 3.93 12.53 12.11

7.84 3.54 3.27 10.43 10.08

Std.

–1

6.67 3.01 2.78 8.88

5.86 2.64 2.44 7.79

8.57

7.53

–2

–F

8.77 4.33 4.10 11.87 11.45

Std.

–1

7.30 3.61 3.41 9.88

6.21 3.07 2.90 8.40

5.45 2.69 2.55 7.38

9.53

8.11

7.12

–2

–F

8.76 4.45 4.74 11.38 11.45

Std.

–1

7.29 3.71 3.95 9.47

6.20 3.15 3.36 8.06

5.45 2.77 2.95 7.07

9.53

8.11

7.12

–2

–F

8.76 4.45 4.74 11.38 11.45

Std.

–1

7.29 3.71 3.95 9.47

6.20 3.15 3.36 8.06

5.45 2.77 2.95 7.07

9.53

8.11

7.12

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-48

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-63 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

13.61 0.05 1.44 0.51 10.48 13.61 2.70 1.83 13.17 16.30

8.72 11.33 2.24 1.52 10.96 13.57

t_DINt_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

2 mA

4 mA

6 mA

8 mA

Notes:

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

11.33 0.04 1.20 0.43

9.64 0.04 1.02 0.36

8.46 0.03 0.90 0.32

7.79 0.05 1.44 0.51

6.48 0.04 1.20 0.43

5.51 0.04 1.02 0.36

4.84 0.03 0.90 0.32

4.88 0.05 1.44 0.51

4.06 0.04 1.20 0.43

3.45 0.04 1.02 0.36

3.03 0.03 0.90 0.32

4.88 0.05 1.44 0.51

4.06 0.04 1.20 0.43

3.45 0.04 1.02 0.36

3.03 0.03 0.90 0.32

7.42

6.51

6.58

5.48

4.66

4.09

4.61

3.84

3.27

2.87

4.61

3.84

3.27

2.87

9.64 1.91 1.29 9.32 11.54

8.46 1.68 1.14 8.18 10.13

7.79 3.18 3.13 9.27 10.47

–2

–F

Std.

–1

6.48 2.65 2.60 7.72

5.51 2.25 2.21 6.56

4.84 1.98 1.94 5.76

4.88 3.52 3.73 7.30

4.06 2.93 3.10 6.07

3.45 2.49 2.64 5.17

3.03 2.19 2.32 4.54

4.88 3.52 3.73 7.30

4.06 2.93 3.10 6.07

3.45 2.49 2.64 5.17

3.03 2.19 2.32 4.54

8.72

7.42

6.51

7.56

6.30

5.36

4.70

7.56

6.30

5.36

4.70

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-49

ProASIC3 DC and Switching Characteristics

Table 2-64 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

–F

Std.

–1

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

17.78 0.05 1.44

14.80 0.04 1.20

12.59 0.04 1.02

11.05 0.03 0.90

11.89 0.05 1.44

0.51 16.21 17.78 2.70 1.76 18.90 20.47

0.43 13.49 14.80 2.25 1.46 15.73 17.04

0.36 11.48 12.59 1.91 1.25 13.38 14.49

0.32 10.08 11.05 1.68 1.09 11.75 12.72

0.51 11.69 11.89 3.19 3.00 14.38 14.58

–2

–F

Std.

–1

9.90

8.42

7.39

8.93

7.44

6.33

5.55

8.93

7.44

6.33

5.55

0.04 1.20

0.04 1.02

0.03 0.90

0.05 1.44

0.04 1.20

0.04 1.02

0.03 0.90

0.05 1.44

0.04 1.20

0.04 1.02

0.03 0.90

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

9.73

8.28

7.27

9.10

7.58

6.44

5.66

9.10

7.58

6.44

5.66

9.90 2.65 2.50 11.97 12.13

8.42 2.26 2.12 10.18 10.32

–2

7.39 1.98 1.86 8.94

9.06

–F

8.79 3.53 3.59 11.79 11.48

Std.

–1

7.32 2.94 2.99 9.81

6.23 2.50 2.54 8.35

5.47 2.19 2.23 7.33

9.56

8.13

7.14

–2

–F

8.79 3.53 3.59 11.79 11.48

Std.

–1

7.32 2.94 2.99 9.81

6.23 2.50 2.54 8.35

5.47 2.19 2.23 7.33

9.56

8.13

7.14

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-65 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

13.47

11.21

9.54

8.37

7.62

6.34

5.40

4.74

t_DIN

0.05

0.04

0.03

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

10.25

8.53

7.26

6.37

6.46

5.38

4.58

4.02

t_ZH

13.47

11.21

9.54

8.37

7.62

6.34

5.40

4.74

t_LZ

t_HZ

Units

2 mA

4 mA

Notes:

–F

Std.

–1

1.44

1.20

1.02

0.90

1.44

1.20

1.02

0.90

2.39

1.99

1.69

1.49

2.89

2.41

2.05

1.80

1.45

1.21

1.03

0.90

2.98

2.48

2.11

1.85

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-50

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-66 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

–F

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

t_DIN

0.05

0.04

0.03

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

18.03

15.01

12.77

11.21

12.13

10.10

8.59

1.44

1.20

1.02

0.90

1.44

1.20

1.02

0.90

15.80

13.15

11.19

9.82

18.03

15.01

12.77

11.21

12.13

10.10

8.59

2.40

1.99

1.70

1.49

2.90

2.41

2.05

1.80

2.40

1.99

1.70

1.49

2.85

2.37

2.02

1.77

Std.

–1

–2

4 mA

–F

11.48

9.55

Std.

–1

8.13

–2

7.54

7.13

7.54

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-67 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.30 * V_CCI0.7 * V_CCI

3.6

0.25 * V_CCI0.75 * V_CCI

10 10

–0.3 0.30 * V_CCI0.7 * V_CCI

0.25 * V_CCI0.75 * V_CCI

0.25 * V_CCI0.75 * V_CCI12 12

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

v1.3

2-51

ProASIC3 DC and Switching Characteristics

Table 2-68 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

Notes:

–0.3 0.30 * V_CCI0.7 * V_CCI3.6 0.25 * V_CCI0.75 * V_CCI

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-69 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSH

I_ILI_IH

Drive

Max., Max.,

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V

mA mA mA¹mA¹µA²µA²

2 mA

–0.3 0.30 * V_CCI0.7 * V_CCI3.6

0.25 * V_CCI0.75 * V_CCI

13 16 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-9 • AC Loading

Table 2-70 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

_LOAD(pF)

1.5

0.75

* Measuring point = V_trip.See Table 2-22 on page 2-20 for a complete table of trip points.

2-52

v1.3

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-71 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–F

Std.

–1

0.79 10.05 0.05 1.73

8.20 10.05 4.07 3.32 10.88 12.73

6.82 8.36 3.39 2.77 9.06 10.60

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

8.36 0.04 1.44

7.11 0.04 1.22

6.24 0.03 1.07

6.38 0.05 1.73

5.31 0.04 1.44

4.52 0.04 1.22

3.97 0.03 1.07

5.61 0.05 1.73

4.67 0.04 1.44

3.97 0.04 1.22

3.49 0.03 1.07

4.90 0.05 1.73

4.08 0.04 1.44

3.47 0.04 1.22

3.05 0.03 1.07

4.90 0.05 1.73

4.08 0.04 1.44

3.47 0.04 1.22

3.05 0.03 1.07

5.80 7.11 2.88 2.35 7.71

5.10 6.24 2.53 2.06 6.76

5.83 6.38 4.49 4.09 8.51

4.85 5.31 3.74 3.40 7.09

4.13 4.52 3.18 2.89 6.03

3.62 3.97 2.79 2.54 5.29

5.46 5.61 4.59 4.28 8.15

4.55 4.67 3.82 3.56 6.78

3.87 3.97 3.25 3.03 5.77

3.40 3.49 2.85 2.66 5.07

4.99 4.30 4.74 5.05 7.68

4.15 3.58 3.94 4.20 6.39

3.53 3.04 3.36 3.58 5.44

3.10 2.67 2.95 3.14 4.77

4.99 4.30 4.74 5.05 7.68

4.15 3.58 3.94 4.20 6.39

3.53 3.04 3.36 3.58 5.44

3.10 2.67 2.95 3.14 4.77

9.02

7.91

9.07

7.55

6.42

5.64

8.29

6.90

5.87

5.16

6.98

5.81

4.95

4.34

6.98

5.81

4.95

4.34

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-53

ProASIC3 DC and Switching Characteristics

Table 2-72 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks

Drive

Speed

Strength

Grade

–F

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

15.36 0.05 1.73 0.51 15.39 15.36 4.08 3.18 18.07 18.04

12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.05 15.02

10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78

Std.

–1

–2

9.55 0.03 1.07 0.32

9.57 9.55 2.54 1.97 11.24 11.22

–F

12.02 0.05 1.73 0.51 12.25 11.47 4.50 3.93 14.93 14.15

10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78

Std.

–1

8.51 0.04 1.22 0.36

7.47 0.03 1.07 0.32

8.67 8.12 3.19 2.78 10.57 10.02

7.61 7.13 2.80 2.44 9.28 8.80

–2

–F

11.21 0.05 1.73 0.51 11.42 10.68 4.60 4.12 14.11 13.37

Std.

–1

9.33 0.04 1.44 0.43

7.94 0.04 1.22 0.36

6.97 0.03 1.07 0.32

9.51 8.89 3.83 3.43 11.74 11.13

8.09 7.56 3.26 2.92 9.99

7.10 6.64 2.86 2.56 8.77

9.47

8.31

–2

–F

10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37

Std.

–1

8.91 0.04 1.44 0.43

7.58 0.04 1.22 0.36

6.65 0.03 1.07 0.32

9.07 8.89 3.95 4.05 11.31 11.13

7.72 7.57 3.36 3.44 9.62

6.78 6.64 2.95 3.02 8.45

9.47

8.31

–2

–F

10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37

Std.

–1

8.91 0.04 1.44 0.43

7.58 0.04 1.22 0.36

6.65 0.03 1.07 0.32

9.07 8.89 3.95 4.05 11.31 11.13

7.72 7.57 3.36 3.44 9.62

6.78 6.64 2.95 3.02 8.45

9.47

8.31

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-54

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-73 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Speed

Strength

Grade

–F

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

t_DIN

t_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

Notes:

9.41 0.05 1.71

7.83 0.04 1.42

6.66 0.04 1.21

5.85 0.03 1.06

5.81 0.05 1.71

4.84 0.04 1.42

4.12 0.04 1.21

3.61 0.03 1.06

7.71 9.41 3.25 3.06 10.40 12.09

6.42 7.83 2.71 2.55 8.65 10.07

Std.

–1

5.46 6.66 2.31 2.17 7.36

4.79 5.85 2.02 1.90 6.46

5.39 5.81 3.64 3.76 8.08

4.49 4.84 3.03 3.13 6.72

3.82 4.12 2.58 2.66 5.72

3.35 3.61 2.26 2.34 5.02

8.56

7.52

8.50

7.08

6.02

5.28

–2

–F

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-74 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Plus I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.79

0.66

0.56

0.49

0.79

0.66

0.56

0.49

t_DP

t_DINt_PY

t_EOUT

0.51

0.43

0.36

0.32

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

–F

Std.

–1

14.51 0.05 1.71

12.08 0.04 1.42

10.27 0.04 1.21

9.02 0.03 1.06

11.15 0.05 1.71

9.28 0.04 1.42

7.89 0.04 1.21

6.93 0.03 1.06

14.42 14.51 3.26 2.91 17.11 17.20

12.01 12.08 2.72 2.43 14.24 14.31

10.21 10.27 2.31 2.06 12.12 12.18

8.97 9.02 2.03 1.81 10.64 10.69

11.35 10.71 3.65 3.60 14.04 13.40

9.45 8.91 3.04 3.00 11.69 11.15

8.04 7.58 2.58 2.55 9.94 9.49

7.06 6.66 2.27 2.24 8.73 8.33

–2

4 mA

–F

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-55

ProASIC3 DC and Switching Characteristics

Table 2-75 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

Drive

Speed

Strength

Grade

–F

t_DOUT

0.79

0.66

0.56

0.49

t_DP

t_DIN

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

9.18

7.65

6.50

5.71

1.70

1.42

1.21

1.06

7.58

6.31

5.37

4.71

9.18

7.65

6.50

5.71

2.94

2.45

2.08

1.83

2.94

2.45

2.08

1.83

Std.

–1

–2

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-76 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.79

0.66

0.56

0.49

t_DP

t_DIN

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

–F

Std.

–1

14.81

12.33

10.49

9.21

1.70

1.42

1.21

1.06

14.17

11.79

10.03

8.81

14.81

12.33

10.49

9.21

2.94

2.45

2.08

1.83

2.79

2.32

1.98

1.73

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

Table 2-77 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

Drive Strength

Per PCI specification

Notes:

V_IL

Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA¹Max, mA¹µA²µA²

Per PCI curves 10 10

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-10.

R to V_CCIfor t_DP(F)

R to GND for t_DP(R)

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 25

Test Point

R = 1 k

Test Point

Datapath

Enable Path

10 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-10 • AC Loading

2-56

v1.3

ProASIC3 DC and Switching Characteristics

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-78.

Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

0.285 * V_CCIfor t_DP(R)

0.615 * V_CCIfor t_DP(F)

_LOAD(pF)

3.3

* Measuring point = V_trip.See Table 2-22 on page 2-20 for a complete table of trip points.

Timing Characteristics

Table 2-79 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Speed Grade t_DOUT

t_DP

t_DIN

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.97

4.97

4.22

3.71

t_ZHS

5.03

4.19

3.56

3.13

Units

–F

0.79

0.66

0.56

0.49

3.22

2.68

2.28

2.00

1.04

0.86

0.73

0.65

3.28

2.73

2.32

2.04

2.34

1.95

1.66

1.46

3.86

3.21

2.73

2.40

4.30

3.58

3.05

2.68

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-80 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade t_DOUT

t_DP

t_DIN

0.05

0.04

0.03

t_PY

t_EOUT

0.51

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.51

4.59

3.90

3.42

t_ZHS

4.73

3.94

3.35

2.94

Units

–F

0.79

0.66

0.56

0.49

2.77

2.31

1.96

1.72

1.02

0.85

0.72

0.64

2.82

2.35

2.00

1.76

2.05

1.70

1.45

1.27

3.35

2.79

2.37

2.08

3.87

3.22

2.74

2.41

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-57

ProASIC3 DC and Switching Characteristics

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Actel Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

165 Ω

Z₀= 50 Ω

140 Ω

Z₀= 50 Ω

INBUF_LVDS

–

100 Ω

Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation

2-58

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-81 • LVDS Minimum and Maximum DC Input and Output Levels

DC Parameter

Description

Supply Voltage ¹

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V_CCI

V_OL

V_OH

Output Low Voltage

1.075

1.425

0.91

Output High Voltage

1.25

0.65

I_OL

Output Lower Current

1.16

2.925

I_OH

Output High Current

V_I

Input Voltage

I_IH

Input High Leakage Current

Input Low Leakage Current

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage ²

µA

I_IL

V_ODIFF

V_OCM

V_ICM

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V_IDIFF

Notes:

1. 5ꢀ

2. Differential input voltage = 350 mV.

3. Currents are measured at 85°C junction temperature.

4. I_OL/ I_OHdefined by V_ODIFF/(Resistor Network).

Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

1.075

1.325

Cross point

* Measuring point = V_trip.See Table 2-22 on page 2-20 for a complete table of trip points.

Timing Characteristics

Table 2-83 • LVDS

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Speed Grade

t_DOUT

0.79

0.66

0.56

0.49

t_DP

t_DIN

0.05

0.04

0.03

t_PY

Units

–F

2.20

1.83

1.56

1.37

1.92

1.60

1.36

1.20

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-59

ProASIC3 DC and Switching Characteristics

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations

may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers

require series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus since the driver can be located anywhere on the bus. These

configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-12. The input and output

buffer delays are available in the LVDS section in Table 2-83.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:

R_S= 60 Ω and R_T= 70 Ω, given Z₀= 50 Ω (2") and Z_stub= 50 Ω (~1.5").

Receiver

Transceiver

Driver

Receiver

Transceiver

BIBUF_LVDS

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

2-60

v1.3

ProASIC3 DC and Switching Characteristics

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-13. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVDS implementation

because the output standard specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

OUTBUF_LVPECL

100 Ω

Z = 50 Ω

INBUF_LVPECL

–

187 W

Z = 50 Ω

100 Ω

Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-84 • Minimum and Maximum DC Input and Output Levels

DC Parameter

V_CCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

Min.

Max.

Units

3.0

3.3

3.6

V_OL

Output LOW Voltage

0.96

1.8

1.27

2.11

3.3

1.06

1.92

1.43

2.28

3.6

1.30

2.13

1.57

2.41

3.9

V_OH

Output HIGH Voltage

V_IL, V_IH

V_ODIFF

V_OCM

Input LOW, Input HIGH Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

V_ICM

V_IDIFF

Table 2-85 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

1.64

1.94

Cross point

* Measuring point = V_trip.See Table 2-22 on page 2-20 for a complete table of trip points.

Timing Characteristics

Table 2-86 • LVPECL

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Speed Grade

t_DOUT

0.79

0.66

0.56

0.49

t_DP

t_DIN

0.05

0.04

0.03

t_PY

Units

–F

2.16

1.80

1.53

1.34

1.69

1.40

1.19

1.05

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-61

ProASIC3 DC and Switching Characteristics

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

DOUT

Data_out

PRE

DFN1E1P1

PRE

DFN1E1P1

Core

Array

Data

Enable

CLK

EOUT

PRE

DFN1E1P1

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

INBUF

CLKBUF

Postive-Edge Triggered

Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

2-62

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-87 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

t_OHD

F, H

t_OSUE

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

L, DOUT

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

I, EOUT

I, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

* See Figure 2-14 on page 2-62 for more information.

v1.3

2-63

ProASIC3 DC and Switching Characteristics

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

DOUT

Data_out

Core

Data

Array

DFN1E1C1

EOUT

Enable

CLK

CLR

DFN1E1C1

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

2-64

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-88 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

t_OHD

FF, HH

t_OSUE

GG, HH

LL, DOUT

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

JJ, HH

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

* See Figure 2-15 on page 2-64 for more information.

v1.3

2-65

ProASIC3 DC and Switching Characteristics

Input Register

t_ICKMPWHt_ICKMPWL

50%

CLK

t_IHD

t_ISUD

50%

Data

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-16 • Input Register Timing Diagram

Timing Characteristics

Table 2-89 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_ICLKQ

Description

–2 –1 Std. –F Units

0.24 0.27 0.32 0.38 ns

0.26 0.30 0.35 0.42 ns

0.00 0.00 0.00 0.00 ns

0.37 0.42 0.50 0.60 ns

0.00 0.00 0.00 0.00 ns

0.45 0.52 0.61 0.73 ns

0.00 0.00 0.00 0.00 ns

0.22 0.25 0.30 0.36 ns

0.00 0.00 0.00 0.00 ns

0.22 0.25 0.30 0.36 ns

0.36 0.41 0.48 0.57 ns

0.32 0.37 0.43 0.52 ns

Clock-to-Q of the Input Data Register

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

Enable Hold Time for the Input Data Register

t_IHE

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

t_IWPRE

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

t_ICKMPWHClock Minimum Pulse Width HIGH for the Input Data Register

t_ICKMPWLClock Minimum Pulse Width LOW for the Input Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-66

v1.3

ProASIC3 DC and Switching Characteristics

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-17 • Output Register Timing Diagram

Timing Characteristics

Table 2-90 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_OCLKQ

t_OSUD

Description

–2

–1 Std. –F Units

Clock-to-Q of the Output Data Register

0.59 0.67 0.79 0.95 ns

0.31 0.36 0.42 0.50 ns

0.00 0.00 0.00 0.00 ns

0.44 0.50 0.59 0.70 ns

0.00 0.00 0.00 0.00 ns

0.80 0.91 1.07 1.29 ns

0.00 0.00 0.00 0.00 ns

0.22 0.25 0.30 0.36 ns

0.00 0.00 0.00 0.00 ns

0.22 0.25 0.30 0.36 ns

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

t_OHE

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

Asynchronous Clear Minimum Pulse Width for the Output Data 0.22 0.25 0.30 0.36 ns

t_OWPRE

Asynchronous Preset Minimum Pulse Width for the Output Data 0.22 0.25 0.30 0.36 ns

t_OCKMPWHClock Minimum Pulse Width HIGH for the Output Data Register

t_OCKMPWLClock Minimum Pulse Width LOW for the Output Data Register

0.36 0.41 0.48 0.57 ns

0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-67

ProASIC3 DC and Switching Characteristics

Output Enable Register

t_OECKMPWHt_OECKMPWL

50%

CLK

t_OESUDt_OEHD

50%

D_Enable

50%

Enable

Preset

t_OEWPRE

50%

t_OEREMPRE

50%

t_OERECPRE

50%

_OESUEt_OEHE

t_OEREMCLR

50%

t_OEWCLRt_OERECCLR

50%

Clear

EOUT

t_OECLR2Q

50%

t_OEPRE2Q

50%

t_OECLKQ

Figure 2-18 • Output Enable Register Timing Diagram

2-68

v1.3

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-91 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_OECLKQ

t_OESUD

Description

–2

–1 Std. –F Units

Clock-to-Q of the Output Enable Register

0.59 0.67 0.79 0.95 ns

0.31 0.36 0.42 0.50 ns

0.00 0.00 0.00 0.00 ns

0.44 0.50 0.58 0.70 ns

0.00 0.00 0.00 0.00 ns

0.67 0.76 0.89 1.07 ns

0.00 0.00 0.00 0.00 ns

0.22 0.25 0.30 0.36 ns

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

t_OEHD

t_OESUE

t_OEHE

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLRAsynchronous Clear Removal Time for the Output Enable Register

t_OERECCLRAsynchronous Clear Recovery Time for the Output Enable Register

t_OEREMPREAsynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

t_OERECPRE

t_OEWCLR

Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

Asynchronous Clear Minimum Pulse Width for the Output Enable 0.22 0.25 0.30 0.36 ns

t_OEWPRE

Asynchronous Preset Minimum Pulse Width for the Output Enable 0.22 0.25 0.30 0.36 ns

t_OECKMPWHClock Minimum Pulse Width HIGH for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width LOW for the Output Enable Register

0.36 0.41 0.48 0.57 ns

0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-69

ProASIC3 DC and Switching Characteristics

DDR Module Specifications

Input DDR Module

Input DDR

INBUF

Data

Out_QF

(to core)

FF1

Out_QR

(to core)

CLK

CLKBUF

FF2

CLR

INBUF

DDR_IN

Figure 2-19 • Input DDR Timing Model

Table 2-92 • Parameter Definitions

Parameter Name

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Parameter Definition

Measuring Nodes (from, to)

Clock-to-Out Out_QR

Clock-to-Out Out_QF

B, D

B, E

A, B

C, D

C, E

C, B

Data Setup Time of DDR input

Data Hold Time of DDR input

Clear-to-Out Out_QR

Clear-to-Out Out_QF

Clear Removal

t_DDRIHD

t_DDRICLR2Q1

t_DDRICLR2Q2

t_DDRIREMCLR

t_DDRIRECCLR

Clear Recovery

2-70

v1.3

ProASIC3 DC and Switching Characteristics

CLK

DDRISUD

DDRIHD

Data

CLR

DDRIRECCLR

DDRIREMCLR

DDRICLKQ1

DDRICLR2Q1

Out_QF

Out_QR

DDRICLKQ2

DDRICLR2Q2

Figure 2-20 • Input DDR Timing Diagram

Timing Characteristics

Table 2-93 • Input DDR Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst Case V_CC= 1.425 V

Parameter

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Description

Clock-to-Out Out_QR for Input DDR

Clock-to-Out Out_QF for Input DDR

Data Setup for Input DDR (Fall)

Data Setup for Input DDR (Rise)

Data Hold for Input DDR (Fall)

Data Hold for Input DDR (Rise)

–2

–1

Std.

–F

Units

0.27

0.39

0.25

0.00

0.46

0.57

0.00

0.22

0.36

0.32

0.31 0.37 0.44

0.44 0.52 0.62

0.28 0.33 0.40

0.00 0.00 0.00

0.53 0.62 0.74

0.65 0.76 0.92

0.00 0.00 0.00

0.25 0.30 0.36

0.41 0.48 0.57

0.37 0.43 0.52

t_DDRIHD

t_DDRICLR2Q1Asynchronous Clear-to-Out Out_QR for Input DDR

t_DDRICLR2Q2Asynchronous Clear-to-Out Out_QF for Input DDR

t_DDRIREMCLRAsynchronous Clear Removal time for Input DDR

t_DDRIRECCLR

t_DDRIWCLR

Asynchronous Clear Recovery time for Input DDR

Asynchronous Clear Minimum Pulse Width for Input DDR

t_DDRICKMPWHClock Minimum Pulse Width High for Input DDR

t_DDRICKMPWLClock Minimum Pulse Width Low for Input DDR

F_DDRIMAX

Maximum Frequency for Input DDR

MHz

Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-71

ProASIC3 DC and Switching Characteristics

Output DDR Module

Output DDR

Data_F

(from core)

FF1

Out

CLK

CLKBUF

OUTBUF

Data_R

(from core)

FF2

CLR

INBUF

DDR_OUT

Figure 2-21 • Output DDR Timing Model

Table 2-94 • Parameter Definitions

Parameter Name

t_DDROCLKQ

Parameter Definition

Measuring Nodes (from, to)

Clock-to-Out

B, E

C, E

C, B

A, B

D, B

A, B

D, B

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROSUD1

Asynchronous Clear-to-Out

Clear Removal

Clear Recovery

Data Setup Data_F

Data Setup Data_R

Data Hold Data_F

Data Hold Data_R

t_DDROSUD2

t_DDROHD1

t_DDROHD2

2-72

v1.3

ProASIC3 DC and Switching Characteristics

CLK

t_DDROHD2

t_DDROSUD2

Data_F

t_DDROHD1

t_DDROREMCLR

Data_R 6

CLR

t_DDRORECCLR

t_DDROREMCLR

t_DDROCLR2Q

t_DDROCLKQ

Out

Figure 2-22 • Output DDR Timing Diagram

Timing Characteristics

Table 2-95 • Output DDR Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_DDROCLKQ

t_DDROSUD1

t_DDROSUD2

t_DDROHD1

Description

–2

–1 Std. –F Units

Clock-to-Out of DDR for Output DDR

0.70 0.80 0.94 1.13

0.38 0.43 0.51 0.61

0.00 0.00 0.00 0.00

0.80 0.91 1.07 1.29

0.00 0.00 0.00 0.00

0.22 0.25 0.30 0.36

0.36 0.41 0.48 0.57

0.32 0.37 0.43 0.52

Data_F Data Setup for Output DDR

Data_R Data Setup for Output DDR

Data_F Data Hold for Output DDR

t_DDROHD2

Data_R Data Hold for Output DDR

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROWCLR1

Asynchronous Clear-to-Out for Output DDR

Asynchronous Clear Removal Time for Output DDR

Asynchronous Clear Recovery Time for Output DDR

Asynchronous Clear Minimum Pulse Width for Output DDR

t_DDROCKMPWHClock Minimum Pulse Width HIGH for the Output DDR

t_DDROCKMPWLClock Minimum Pulse Width LOW for the Output DDR

F_DDOMAX

Maximum Frequency for the Output DDR

TBD TBD TBD TBD MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-73

ProASIC3 DC and Switching Characteristics

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section,

timing characteristics are presented for a sample of the library. For more details, refer to the

Fusion, IGLOO^®/e, and ProASIC3/E Macro Library Guide.

INV

NOR2

OR2

AND2

NAND2

XOR3

XOR2

MAJ3

MUX2

NAND3

Figure 2-23 • Sample of Combinatorial Cells

2-74

v1.3

ProASIC3 DC and Switching Characteristics

t_PD

NAND2 or

Any Combinatorial

Logic

t_PD= MAX(t_PD(RR), t_PD(RF)

t_PD(FF), t_PD(FR)) where edges are

applicable for the particular

combinatorial cell

V_CC

50%

V_CC

A, B, C

GND

50%

OUT

GND

V_CC

t_PD

(RR)

(FF)

t_PD

(FR)

50%

t_PD

GND

(RF)

Figure 2-24 • Timing Model and Waveforms

v1.3

2-75

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-96 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Combinatorial Cell

INV

Equation

Y = !A

Parameter

t_PD

–2

–1

Std.

0.54

0.63

0.65

0.99

0.93

1.17

0.68

0.75

–F

Units

0.40

0.47

0.49

0.74

0.70

0.87

0.51

0.56

0.46

0.54

0.55

0.84

0.79

1.00

0.58

0.64

0.65

0.76

0.78

1.19

1.12

1.41

0.81

0.90

AND2

Y = A · B

t_PD

NAND2

OR2

Y = !(A · B)

Y = A + B

t_PD

NOR2

Y = !(A + B)

Y = A ⊕ B

Y = MAJ(A, B, C)

^{Y = A}⊕ B ⊕ C

Y = A !S + B S

Y = A · B · C

t_PD

XOR2

t_PD

MAJ3

t_PD

XOR3

t_PD

MUX2

AND3

t_PD

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

VersaTile Specifications as a Sequential Module

The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each

has a data input and optional enable, clear, or preset. In this section, timing characteristics are

presented for a representative sample from the library. For more details, refer to the Fusion,

IGLOO/e, and ProASIC3/E Macro Library Guide.

Data

CLK

Out

Data

Out

DFN1

DFN1E1

CLK

PRE

Data

Out

Data

Out

DFN1C1

DFI1E1P1

CLK

CLR

Figure 2-25 • Sample of Sequential Cells

2-76

v1.3

ProASIC3 DC and Switching Characteristics

t_CKMPWHt_CKMPWL

50%

t_SUD

50%

CLK

t_HD

50%

Data

50%

t_RECPRE

50%

t_WPRE

50%

t_REMPRE

50%

t_HE

t_SUE

PRE

CLR

Out

t_REMCLR

50%

t_RECCLR

50%

t_WCLR

50%

t_PRE2Q

50%

t_CLR2Q

50%

t_CLKQ

Figure 2-26 • Timing Model and Waveforms

Timing Characteristics

Table 2-97 • Register Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_CLKQ

Description

–2

–1 Std. –F Units

Clock-to-Q of the Core Register

0.55 0.63 0.74 0.89

0.43 0.49 0.57 0.69

0.00 0.00 0.00 0.00

0.45 0.52 0.61 0.73

0.00 0.00 0.00 0.00

0.40 0.45 0.53 0.64

0.00 0.00 0.00 0.00

0.22 0.25 0.30 0.36

0.00 0.00 0.00 0.00

0.22 0.25 0.30 0.36

0.32 0.37 0.43 0.52

0.36 0.41 0.48 0.57

t_SUD

Data Setup Time for the Core Register

t_HD

Data Hold Time for the Core Register

t_SUE

Enable Setup Time for the Core Register

t_HE

Enable Hold Time for the Core Register

t_CLR2Q

t_PRE2Q

t_REMCLR

t_RECCLR

t_REMPRE

t_RECPRE

t_WCLR

Asynchronous Clear-to-Q of the Core Register

Asynchronous Preset-to-Q of the Core Register

Asynchronous Clear Removal Time for the Core Register

Asynchronous Clear Recovery Time for the Core Register

Asynchronous Preset Removal Time for the Core Register

Asynchronous Preset Recovery Time for the Core Register

Asynchronous Clear Minimum Pulse Width for the Core Register

Asynchronous Preset Minimum Pulse Width for the Core Register

Clock Minimum Pulse Width HIGH for the Core Register

Clock Minimum Pulse Width LOW for the Core Register

t_WPRE

t_CKMPWH

t_CKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-77

ProASIC3 DC and Switching Characteristics

Global Resource Characteristics

A3P250 Clock Tree Topology

Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing.

The global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250

device. It is used to drive all D-flip-flops in the device.

Central

Global Rib

CCC

VersaTile

Rows

Global Spine

Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing

2-78

v1.3

ProASIC3 DC and Switching Characteristics

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be

driven and conditioned internally by the CCC module. For more details on clock conditioning

capabilities, refer to the "Clock Conditioning Circuits" section on page 2-83. Table 2-99 to

Table 2-105 on page 2-82 present minimum and maximum global clock delays within each device.

Minimum and maximum delays are measured with minimum and maximum loading.

Timing Characteristics

Table 2-98 • A3P015 Global Resource

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

–2

–1

Std.

–F

Parameter Description

t_RCKLInput LOW Delay for Global Clock

t_RCKHInput HIGH Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

0.66 0.81 0.75 0.92 0.88 1.08 1.06 1.30

0.67 0.84 0.76 0.96 0.89 1.13 1.07 1.36

t_RCKMPWHMinimum Pulse Width HIGH for Global Clock

t_RCKMPWLMinimum Pulse Width LOW for Global Clock

t_RCKSW

F_RMAX

Notes:

Maximum Skew for Global Clock

0.18

0.21

0.25

0.30

Maximum Frequency for Global Clock

MHz

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-99 • A3P030 Global Resource

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

–2

–1

Std.

–F

Parameter

t_RCKL

Description

Min.¹Max.²Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

Input LOW Delay for Global Clock

Input HIGH Delay for Global Clock

0.67 0.81 0.76 0.92 0.89 1.09 1.07 1.31 ns

t_RCKH

0.68 0.85 0.77 0.97 0.91 1.14 1.09 1.37 ns

t_RCKMPWHMinimum Pulse Width HIGH for Global Clock

t_RCKMPWLMinimum Pulse Width LOW for Global Clock

t_RCKSW

F_RMAX

Notes:

Maximum Skew for Global Clock

0.18

0.21

0.24

0.29 ns

MHz

Maximum Frequency for Global Clock

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-79

ProASIC3 DC and Switching Characteristics

Table 2-100 • A3P060 Global Resource

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

–2

–1

Std.

–F

Parameter

t_RCKL

Description

Min.¹Max.²Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

Input LOW Delay for Global Clock

Input HIGH Delay for Global Clock

0.71 0.93 0.81 1.05 0.95 1.24 1.14 1.49 ns

t_RCKH

0.70 0.96 0.80 1.09 0.94 1.28 1.13 1.54 ns

t_RCKMPWHMinimum Pulse Width HIGH for Global Clock

t_RCKMPWLMinimum Pulse Width LOW for Global Clock

t_RCKSW

F_RMAX

Notes:

Maximum Skew for Global Clock

0.26

0.29

0.34

0.41 ns

MHz

Maximum Frequency for Global Clock

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-101 • A3P125 Global Resource

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

–2

–1

Std.

–F

Parameter

t_RCKL

Description

Min.¹Max.²Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

Input LOW Delay for Global Clock

Input HIGH Delay for Global Clock

0.77 0.99 0.87 1.12 1.03 1.32 1.24 1.58 ns

t_RCKH

0.76 1.02 0.87 1.16 1.02 1.37 1.23 1.64 ns

t_RCKMPWHMinimum Pulse Width HIGH for Global Clock

t_RCKMPWLMinimum Pulse Width LOW for Global Clock

t_RCKSW

F_RMAX

Notes:

Maximum Skew for Global Clock

0.26

0.29

0.34

0.41 ns

MHz

Maximum Frequency for Global Clock

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-80

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-102 • A3P250 Global Resource

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

–2

–1

Std.

–F

Parameter

t_RCKL

Description

Min.¹Max.²Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

Input LOW Delay for Global Clock

Input HIGH Delay for Global Clock

0.80 1.01 0.91 1.15 1.07 1.36 1.28 1.63 ns

t_RCKH

0.78 1.04 0.89 1.18 1.04 1.39 1.25 1.66 ns

t_RCKMPWHMinimum Pulse Width HIGH for Global Clock

t_RCKMPWLMinimum Pulse Width LOW for Global Clock

t_RCKSW

F_RMAX

Notes:

Maximum Skew for Global Clock

0.26

0.29

0.34

0.41 ns

MHz

Maximum Frequency for Global Clock

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-103 • A3P400 Global Resource

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

–2

–1

Std.

–F

Parameter

t_RCKL

Description

Min.¹Max.²Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

Input LOW Delay for Global Clock

Input HIGH Delay for Global Clock

0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns

t_RCKH

0.86 1.11 0.98 1.27 1.15 1.49 1.38 1.79 ns

t_RCKMPWHMinimum Pulse Width HIGH for Global Clock

t_RCKMPWLMinimum Pulse Width LOW for Global Clock

t_RCKSW

F_RMAX

Notes:

Maximum Skew for Global Clock

0.26

0.29

0.34

0.41 ns

Mhz

Maximum Frequency for Global Clock

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-81

ProASIC3 DC and Switching Characteristics

Table 2-104 • A3P600 Global Resource

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

–2

–1

Std.

–F

Parameter

t_RCKL

Description

Min.¹Max.²Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

Input LOW Delay for Global Clock

Input HIGH Delay for Global Clock

0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns

t_RCKH

0.86 1.11 0.98 1.27 1.15 1.49 1.38 1.79 ns

t_RCKMPWHMinimum Pulse Width HIGH for Global Clock

t_RCKMPWLMinimum Pulse Width LOW for Global Clock

t_RCKSW

F_RMAX

Notes:

Maximum Skew for Global Clock

0.26

0.29

0.34

0.41 ns

MHz

Maximum Frequency for Global Clock

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-105 • A3P1000 Global Resource

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

–2

–1

Std.

–F

Parameter

t_RCKL

Description

Min.¹Max.²Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

Input LOW Delay for Global Clock

Input HIGH Delay for Global Clock

0.94 1.16 1.07 1.32 1.26 1.55 1.51 1.86 ns

t_RCKH

0.93 1.19 1.06 1.35 1.24 1.59 1.49 1.91 ns

t_RCKMPWHMinimum Pulse Width HIGH for Global Clock

t_RCKMPWLMinimum Pulse Width LOW for Global Clock

t_RCKSW

F_RMAX

Notes:

Maximum Skew for Global Clock

0.26

0.29

0.35

0.41 ns

MHz

Maximum Frequency for Global Clock

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-82

v1.3

ProASIC3 DC and Switching Characteristics

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-106 • ProASIC3 CCC/PLL Specification

Parameter

Minimum

1.5

Typical

Maximum

350

Units

MHz

Clock Conditioning Circuitry Input Frequency f_{IN_CCC}

Clock Conditioning Circuitry Output Frequency f_{OUT_CCC}

Serial Clock (SCLK) for Dynamic PLL¹

0.75

350

125

Delay Increments in Programmable Delay Blocks^{2, 3}

200

Number of Programmable Values in Each Programmable

Delay Block

Input Period Jitter

1.5

CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT}

Max Peak-to-Peak Period Jitter

1 Global

Network

Used

3 Global

Networks

Used

0.75 MHz to 24 MHz

24 MHz to 100 MHz

100 MHz to 250 MHz

250 MHz to 350 MHz

Acquisition Time

0.50%

1.00%

1.75%

2.50%

0.70%

1.20%

2.00%

5.60%

(A3P250 and A3P1000 only)

LockControl = 0

LockControl = 1

LockControl = 0

LockControl = 1

300

6.0

µs

(all other dies)

µs

Tracking Jitter ⁵

(A3P250 and A3P1000 only)

LockControl = 0

LockControl = 1

LockControl = 0

LockControl = 1

1.6

(all other dies)

1.6

0.8

Output Duty Cycle

48.5

0.6

51.5

Delay Range in Block: Programmable Delay 1^{2, 3}

Delay Range in Block: Programmable Delay 2^{2, 3}

Delay Range in Block: Fixed Delay^{2, 3}

Notes:

5.56

0.025

5.56

2.2

1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific

junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.

3. T_J= 25°C, V_CC= 1.5 V

4. The A3P030 device does not contain a PLL.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL

input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by

the period jitter parameter.

v1.3

2-83

ProASIC3 DC and Switching Characteristics

Output Signal

T_{period_max}

T_{period_min}

Note: Peak-to-peak jitter measurements are defined by T_peak-to-peak= T_{period_max}– T_{period_min}

Figure 2-28 • Peak-to-Peak Jitter Definition

2-84

v1.3

ProASIC3 DC and Switching Characteristics

Embedded SRAM and FIFO Characteristics

SRAM

RAM4K9

RAM512X18

RADDR8

RADDR7

RD17

RD16

ADDRA11 DOUTA8

DOUTA7

DOUTA0

ADDRA10

ADDRA0

DINA8

RADDR0

RD0

DINA7

RW1

RW0

DINA0

WIDTHA1

WIDTHA0

PIPEA

PIPE

WMODEA

BLKA

WENA

REN

RCLK

CLKA

ADDRB11 DOUTB8

ADDRB10 DOUTB7

WADDR8

WADDR7

ADDRB0

DOUTB0

WADDR0

WD17

WD16

DINB8

DINB7

WD0

DINB0

WW1

WW0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

WEN

WCLK

RESET

Figure 2-29 • RAM Models

v1.3

2-85

ProASIC3 DC and Switching Characteristics

Timing Waveforms

t_CYC

t_CKH

t_CKL

CLK

t_ASt_AH

A₀

A₁

A₂

ADD

BLK_B

WEN_B

t_BKS

t_BKH

t_ENS

t_ENH

t_CKQ1

D_n

D₀

D₁

D₂

t_DOH1

Figure 2-30 • RAM Read for Pass-Through Output

CYC

CKL

CKH

CLK

ADD

BLK_B

WEN_B

BKS

BKH

ENH

ENS

CKQ2

DOH2

Figure 2-31 • RAM Read for Pipelined Output

2-86

v1.3

ProASIC3 DC and Switching Characteristics

t_CYC

t_CKH

t_AH

t_CKL

CLK

t_AS

A₀

A₁

A₂

ADD

BLK_B

WEN_B

t_BKS

t_BKH

t_ENS

t_ENH

t_DS

t_DH

DI₁

DI₀

D_n

D₂

Figure 2-32 • RAM Write, Output Retained (WMODE = 0)

t_CYC

t_CKH

t_CKL

CLK

ADD

t_ASt_AH

A₀

A₁

A₂

t_BKS

t_BKH

BLK_B

WEN_B

t_ENS

t_DSt_DH

DI₁

DI₀

DI₂

D_n

DI₀

DI₁

(pass-through)

DI₀

D_n

DI₁

(pipelined)

Figure 2-33 • RAM Write, Output as Write Data (WMODE = 1)

v1.3

2-87

ProASIC3 DC and Switching Characteristics

CLK1

ADD1

A₀

A₁

D₂

A₃

D₃

D₁

DI1

CCKH

CLK2

WEN_B1

WEN_B2

A₀

D₀

A₀

A₄

D₄

ADD2

DI2

CKQ1

DO2

(pass-through)

D_n

D₀

CKQ2

DO2

(pipelined)

D₀

Figure 2-34 • Write Access after Write onto Same Address

2-88

v1.3

ProASIC3 DC and Switching Characteristics

CLK1

t_ASt_AH

A₀

t_DSt_DH

A₂

D₂

A₃

D₃

ADD1

D₀

DI1

t_WRO

CLK2

WEN_B1

WEN_B2

ADD2

t_ASt_AH

A₁

A₀

t_CKQ1

A₄

DO2

(pass-through)

D_n

D₀

D₁

D₀

t_CKQ2

DO2

(pipelined)

D_n

Figure 2-35 • Read Access after Write onto Same Address

v1.3

2-89

ProASIC3 DC and Switching Characteristics

CLK1

t_AS

t_AH

A₀

A₁

A₀

ADD1

WEN_B1

t_CKQ1

DO1

(pass-through)

t_CKQ2

DO1

(pipelined)

t_CCKH

CLK2

t_AS

t_AH

A₁

ADD2

A₀

D₁

A₃

D₃

D₂

DI2

WEN_B2

Figure 2-36 • Write Access after Read onto Same Address

CYC

CKL

CKH

CLK

RESET_B

RSTBQ

Figure 2-37 • RAM Reset

2-90

v1.3

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-107 • RAM4K9

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_AS

Description

–2

–1 Std. –F Units

Address setup time

0.25 0.28 0.33 0.40 ns

0.00 0.00 0.00 0.00 ns

0.14 0.16 0.19 0.23 ns

0.10 0.11 0.13 0.16 ns

0.23 0.27 0.31 0.37 ns

0.02 0.02 0.02 0.03 ns

0.18 0.21 0.25 0.29 ns

0.00 0.00 0.00 0.00 ns

t_AH

Address hold time

t_ENS

REN_B, WEN_B setup time

REN_B, WEN_B hold time

BLK_B setup time

t_ENH

t_BKS

t_BKH

t_DS

BLK_B hold time

Input data (DI) setup time

Input data (DI) hold time

t_DH

t_CKQ1

Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.36 2.68 3.15 3.79 ns

Clock HIGH to new data valid on DO (flow-through, WMODE = 1)

Clock HIGH to new data valid on DO (pipelined)

1.79 2.03 2.39 2.87 ns

0.89 1.02 1.20 1.44 ns

t_CKQ2

t_WRO

Address collision clk-to-clk delay for reliable read access after write TBD TBD TBD TBD ns

on same address

t_CCKH

Address collision clk-to-clk delay for reliable write access after TBD TBD TBD TBD ns

write/read on same address

t_RSTBQ

RESET_B LOW to data out LOW on DO (flow-through)

RESET_B LOW to Data Out LOW on DO (pipelined)

RESET_B removal

0.92 1.05 1.23 1.48 ns

0.29 0.33 0.38 0.46 ns

1.50 1.71 2.01 2.41 ns

0.21 0.24 0.29 0.34 ns

3.23 3.68 4.32 5.19 ns

310 272 231 193 MHz

t_REMRSTB

t_RECRSTB

RESET_B recovery

t_MPWRSTBRESET_B minimum pulse width

t_CYC

Clock cycle time

F_MAX

Maximum frequency

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

v1.3

2-91

ProASIC3 DC and Switching Characteristics

Table 2-108 • RAM512X18

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_AS

Description

–2

–1 Std. –F Units

Address setup time

0.25 0.28 0.33 0.40 ns

0.00 0.00 0.00 0.00 ns

0.13 0.15 0.17 0.21 ns

0.10 0.11 0.13 0.16 ns

0.18 0.21 0.25 0.29 ns

0.00 0.00 0.00 0.00 ns

t_AH

Address hold time

t_ENS

REN_B, WEN_B setup time

REN_B, WEN_B hold time

Input data (DI) setup time

Input data (DI) hold time

t_ENH

t_DS

t_DH

t_CKQ1

t_CKQ2

t_WRO

Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 3.47 ns

Clock HIGH to new data valid on DO (pipelined) 0.90 1.02 1.20 1.44 ns

Address collision clk-to-clk delay for reliable read access after write TBD TBD TBD TBD ns

on same address

t_CCKH

Address collision clk-to-clk delay for reliable write access after TBD TBD TBD TBD ns

write/read on same address

t_RSTBQ

RESET_B LOW to data out LOW on DO (flow-through)

RESET_B LOW to data out LOW on DO (pipelined)

RESET_B removal

0.92 1.05 1.23 1.48 ns

0.29 0.33 0.38 0.46 ns

1.50 1.71 2.01 2.41 ns

0.21 0.24 0.29 0.34 ns

3.23 3.68 4.32 5.19 ns

310 272 231 193 MHz

t_REMRSTB

t_RECRSTB

RESET_B recovery

t_MPWRSTBRESET_B minimum pulse width

t_CYC

Clock cycle time

F_MAX

Maximum frequency

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-92

v1.3

ProASIC3 DC and Switching Characteristics

FIFO

FIFO4K18

RW2

RW1

RW0

RD17

RD16

WW2

WW1

WW0

RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AEVAL11

AEVAL10

AEMPTY

AEVAL0

AFVAL11

AFVAL10

AFVAL0

REN

RBLK

RCLK

WD17

WD16

WD0

WEN

WBLK

WCLK

RPIPE

RESET

Figure 2-38 • FIFO Model

v1.3

2-93

ProASIC3 DC and Switching Characteristics

Timing Waveforms

RCLK/

WCLK

t_MPWRSTB

t_RSTCK

RESET_B

t_RSTFG

EMPTY

AEMPTY

FULL

t_RSTAF

t_RSTFG

t_RSTAF

AFULL

WA/RA

(Address Counter)

MATCH (A₀)

Figure 2-39 • FIFO Reset

CYC

RCLK

RCKEF

EMPTY

CKAF

AEMPTY

WA/RA

NO MATCH

Dist = AEF_TH

MATCH (EMPTY)

(Address Counter)

Figure 2-40 • FIFO EMPTY Flag and AEMPTY Flag Assertion

2-94

v1.3

ProASIC3 DC and Switching Characteristics

t_CYC

WCLK

FULL

t_WCKFF

t_CKAF

AFULL

WA/RA

NO MATCH

Dist = AFF_TH

MATCH (FULL)

(Address Counter)

Figure 2-41 • FIFO FULL Flag and AFULL Flag Assertion

WCLK

MATCH

(EMPTY)

WA/RA

NO MATCH

Dist = AEF_TH + 1

(Address Counter)

1st Rising

2nd Rising

Edge

After 1st

Write

Edge

After 1st

Write

RCLK

EMPTY

RCKEF

CKAF

AEMPTY

Figure 2-42 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

RCLK

WA/RA

(Address Counter)

Dist = AFF_TH – 1

MATCH (FULL)

NO MATCH

1st Rising

NO MATCH

1st Rising

Edge

After 1st

Read

Edge

After 2nd

Read

WCLK

FULL

t_WCKF

t_CKAF

AFULL

Figure 2-43 • FIFO FULL Flag and AFULL Flag Deassertion

v1.3

2-95

ProASIC3 DC and Switching Characteristics

Timing Characteristics

Table 2-109 • FIFO (for all dies except A3P250)

Worst Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

Description

REN_B, WEN_B Setup Time

Parameter

t_ENS

–2

–1

Std.

–F

Units

1.34 1.52 1.79 2.15

0.00 0.00 0.00 0.00

0.19 0.22 0.26 0.31

0.00 0.00 0.00 0.00

0.18 0.21 0.25 0.29

0.00 0.00 0.00 0.00

2.17 2.47 2.90 3.48

0.94 1.07 1.26 1.52

1.72 1.96 2.30 2.76

1.63 1.86 2.18 2.62

6.19 7.05 8.29 9.96

1.69 1.93 2.27 2.72

6.13 6.98 8.20 9.85

0.92 1.05 1.23 1.48

0.29 0.33 0.38 0.46

1.50 1.71 2.01 2.41

0.21 0.24 0.29 0.34

3.23 3.68 4.32 5.19

t_ENH

REN_B, WEN_B Hold Time

t_BKS

BLK_B Setup Time

t_BKH

BLK_B Hold Time

t_DS

Input Data (DI) Setup Time

t_DH

Input Data (DI) Hold Time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock HIGH to New Data Valid on DO (flow-through)

Clock HIGH to New Data Valid on DO (pipelined)

RCLK HIGH to Empty Flag Valid

WCLK HIGH to Full Flag Valid

Clock HIGH to Almost Empty/Full Flag Valid

RESET_B LOW to Empty/Full Flag Valid

RESET_B LOW to Almost Empty/Full Flag Valid

RESET_B LOW to Data Out LOW on DO (flow-through)

RESET_B LOW to Data Out LOW on DO (pipelined)

RESET_B Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency for FIFO

310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-96

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-110 • FIFO (for A3P250 only, aspect-ratio-dependent)

Worst Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

Parameter

t_ENS

Description

REN_B, WEN_B Setup Time

–2

–1

Std.

–F

Units

3.26 3.71 4.36 5.24

0.00 0.00 0.00 0.00

0.19 0.22 0.26 0.31

0.00 0.00 0.00 0.00

0.18 0.21 0.25 0.29

0.00 0.00 0.00 0.00

2.17 2.47 2.90 3.48

0.94 1.07 1.26 1.52

1.72 1.96 2.30 2.76

1.63 1.86 2.18 2.62

6.19 7.05 8.29 9.96

1.69 1.93 2.27 2.72

6.13 6.98 8.20 9.85

0.92 1.05 1.23 1.48

0.29 0.33 0.38 0.46

1.50 1.71 2.01 2.41

0.21 0.24 0.29 0.34

3.23 3.68 4.32 5.19

t_ENH

REN_B, WEN_B Hold Time

t_BKS

BLK_B Setup Time

t_BKH

BLK_B Hold Time

t_DS

Input Data (DI) Setup Time

t_DH

Input Data (DI) Hold Time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock HIGH to New Data Valid on DO (flow-through)

Clock HIGH to New Data Valid on DO (pipelined)

RCLK HIGH to Empty Flag Valid

WCLK HIGH to Full Flag Valid

Clock HIGH to Almost Empty/Full Flag Valid

RESET_B LOW to Empty/Full Flag Valid

RESET_B LOW to Almost Empty/Full Flag Valid

RESET_B LOW to Data Out LOW on DO (flow-through)

RESET_B LOW to Data Out LOW on DO (pipelined)

RESET_B Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency for FIFO

310 272 231 193 MHz

v1.3

2-97

ProASIC3 DC and Switching Characteristics

Table 2-111 • A3P250 FIFO 512×8

Worst Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

Description

REN_B, WEN_B Setup Time

Parameter

t_ENS

–2

–1

Std.

–F

Units

3.75 4.27 5.02 6.04

0.00 0.00 0.00 0.00

0.19 0.22 0.26 0.31

0.00 0.00 0.00 0.00

0.18 0.21 0.25 0.29

0.00 0.00 0.00 0.00

2.17 2.47 2.90 3.48

0.94 1.07 1.26 1.52

1.72 1.96 2.30 2.76

1.63 1.86 2.18 2.62

6.19 7.05 8.29 9.96

1.69 1.93 2.27 2.72

6.13 6.98 8.20 9.85

0.92 1.05 1.23 1.48

0.29 0.33 0.38 0.46

1.50 1.71 2.01 2.41

0.21 0.24 0.29 0.34

3.23 3.68 4.32 5.19

t_ENH

REN_B, WEN_B Hold Time

t_BKS

BLK_B Setup Time

t_BKH

BLK_B Hold Time

t_DS

Input Data (DI) Setup Time

t_DH

Input Data (DI) Hold Time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock HIGH to New Data Valid on DO (flow-through)

Clock HIGH to New Data Valid on DO (pipelined)

RCLK HIGH to Empty Flag Valid

WCLK HIGH to Full Flag Valid

Clock HIGH to Almost Empty/Full Flag Valid

RESET_B LOW to Empty/Full Flag Valid

RESET_B LOW to Almost Empty/Full Flag Valid

RESET_B LOW to Data Out LOW on DO (flow-through)

RESET_B LOW to Data Out LOW on DO (pipelined)

RESET_B Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency for FIFO

310 272 231 193 MHz

2-98

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-112 • A3P250 FIFO 1k×4

Worst Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

Parameter

t_ENS

Description

REN_B, WEN_B Setup Time

–2

–1

Std.

5.42

0.00

0.26

0.00

0.25

0.00

3.15

1.20

2.30

2.18

8.29

2.27

8.20

1.23

0.38

2.01

0.29

4.32

231

–F

Units

4.05

0.00

0.19

0.00

0.18

0.00

2.36

0.89

1.72

1.63

6.19

1.69

6.13

0.92

0.29

1.50

0.21

3.23

310

4.61

0.00

0.22

0.00

0.21

0.00

2.68

1.02

1.96

1.86

7.05

1.93

6.98

1.05

0.33

1.71

0.24

3.68

272

6.52

0.00

0.31

0.00

0.29

0.00

3.79

1.44

2.76

2.62

9.96

2.72

9.85

1.48

0.46

2.41

0.34

5.19

193

t_ENH

REN_B, WEN_B Hold Time

t_BKS

BLK_B Setup Time

t_BKH

BLK_B Hold Time

t_DS

Input Data (DI) Setup Time

t_DH

Input Data (DI) Hold Time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock HIGH to New Data Valid on DO (flow-through)

Clock HIGH to New Data Valid on DO (pipelined)

RCLK HIGH to Empty Flag Valid

WCLK HIGH to Full Flag Valid

Clock HIGH to Almost Empty/Full Flag Valid

RESET_B LOW to Empty/Full Flag Valid

RESET_B LOW to Almost Empty/Full Flag Valid

RESET_B LOW to Data Out LOW on DO (flow-through)

RESET_B LOW to Data Out LOW on DO (pipelined)

RESET_B Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency for FIFO

MHz

v1.3

2-99

ProASIC3 DC and Switching Characteristics

Table 2-113 • A3P250 FIFO 2k×2

Worst Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

Description

REN_B, WEN_B Setup Time

Parameter

t_ENS

–2

–1

Std.

5.88

0.00

0.26

0.00

0.25

0.00

3.15

1.20

2.30

2.18

8.29

2.27

8.20

1.23

0.38

2.01

0.29

4.32

231

–F

Units

4.39

0.00

0.19

0.00

0.18

0.00

2.36

0.89

1.72

1.63

6.19

1.69

6.13

0.92

0.29

1.50

0.21

3.23

310

5.00

0.00

0.22

0.00

0.21

0.00

2.68

1.02

1.96

1.86

7.05

1.93

6.98

1.05

0.33

1.71

0.24

3.68

272

7.06

0.00

0.31

0.00

0.29

0.00

3.79

1.44

2.76

2.62

9.96

2.72

9.85

1.48

0.46

2.41

0.34

5.19

193

t_ENH

REN_B, WEN_B Hold Time

t_BKS

BLK_B Setup Time

t_BKH

BLK_B Hold Time

t_DS

Input Data (DI) Setup Time

t_DH

Input Data (DI) Hold Time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock HIGH to New Data Valid on DO (flow-through)

Clock HIGH to New Data Valid on DO (pipelined)

RCLK HIGH to Empty Flag Valid

WCLK HIGH to Full Flag Valid

Clock HIGH to Almost Empty/Full Flag Valid

RESET_B LOW to Empty/Full Flag Valid

RESET_B LOW to Almost Empty/Full Flag Valid

RESET_B LOW to Data Out LOW on DO (flow-through)

RESET_B LOW to Data Out LOW on DO (pipelined)

RESET_B Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency for FIFO

MHz

2-100

v1.3

ProASIC3 DC and Switching Characteristics

Table 2-114 • A3P250 FIFO 4k×1

Worst Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

Parameter

t_ENS

Description

REN_B, WEN_B Setup Time

–2

–1

Std.

6.50

0.00

0.26

0.00

0.25

0.00

3.15

1.20

2.30

2.18

8.29

2.27

8.20

1.23

0.38

2.01

0.29

4.32

231

–F

Units

4.86

0.00

0.19

0.00

0.18

0.00

2.36

0.89

1.72

1.63

6.19

1.69

6.13

0.92

0.29

1.50

0.21

3.23

310

5.53

0.00

0.22

0.00

0.21

0.00

2.68

1.02

1.96

1.86

7.05

1.93

6.98

1.05

0.33

1.71

0.24

3.68

272

7.81

0.00

0.31

0.00

0.29

0.00

3.79

1.44

2.76

2.62

9.96

2.72

9.85

1.48

0.46

2.41

0.34

5.19

193

t_ENH

REN_B, WEN_B Hold Time

t_BKS

BLK_B Setup Time

t_BKH

BLK_B Hold Time

t_DS

Input Data (DI) Setup Time

t_DH

Input Data (DI) Hold Time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock HIGH to New Data Valid on DO (flow-through)

Clock HIGH to New Data Valid on DO (pipelined)

RCLK HIGH to Empty Flag Valid

WCLK HIGH to Full Flag Valid

Clock HIGH to Almost Empty/Full Flag Valid

RESET_B LOW to Empty/Full Flag Valid

RESET_B LOW to Almost Empty/Full Flag Valid

RESET_B LOW to Data Out LOW on DO (pass-through)

RESET_B LOW to Data Out LOW on DO (pipelined)

RESET_B Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency

MHz

v1.3

2-101

ProASIC3 DC and Switching Characteristics

Embedded FlashROM Characteristics

t_SU

CLK

t_HOLD

Address

A₀

A₁

t_CKQ2

D₀

t_CKQ2

D₁

D₀

Data

Figure 2-44 • Timing Diagram

Timing Characteristics

Table 2-115 • Embedded FlashROM Access Time

Parameter

t_SU

Description

Address Setup Time

–2

0.53

0.00

21.42

–1

Std.

0.71

0.00

28.68

Units

0.61

0.00

24.40

t_HOLD

t_CK2Q

F_MAX

Address Hold Time

Clock to Out

Maximum Clock Frequency

MHz

2-102

v1.3

ProASIC3 DC and Switching Characteristics

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer

delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User

I/O Characteristics" section on page 2-15 for more details.

Timing Characteristics

Table 2-116 • JTAG 1532

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_DISU

Description

Test Data Input Setup Time

Test Data Input Hold Time

Test Mode Select Setup Time

Test Mode Select Hold Time

Clock to Q (data out)

–2

–1

Std.

0.67

1.33

0.67

1.33

8.00

26.67

19.00

0.00

0.27

TBD

Units

0.50

1.00

0.50

1.00

6.00

20.00

25.00

0.00

0.20

TBD

0.57

1.13

0.57

1.13

6.80

22.67

22.00

0.00

0.23

TBD

t_DIHD

t_TMSSU

t_TMDHD

t_TCK2Q

t_RSTB2Q

F_TCKMAX

t_TRSTREM

t_TRSTREC

t_TRSTMPW

Reset to Q (data out)

TCK Maximum Frequency

ResetB Removal Time

MHz

ResetB Recovery Time

ResetB Minimum Pulse

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6

for derating values.

v1.3

2-103

ProASIC3 DC and Switching Characteristics

Part Number and Revision Date

Part Number 51700097-002-3

Revised August 2008

List of Changes

The following table lists critical changes that were made in the current version of the chapter.

Previous Version

Changes in Current Version (v1.3)

Page

v1.2

(June 2008)

TJ, Maximum Junction Temperature, was changed to 100° from 110º in the

"Thermal Characteristics" section and EQ 2-2. The calculated result of Maximum

Power Allowed has thus changed to 1.463 W from 1.951 W.

2-5

Values for the A3P015 device were added to Table 2-7 · Quiescent Supply

Current Characteristics.

2-6

Values for the A3P015 device were added to Table 2-14 · Different Components

Contributing to Dynamic Power Consumption in ProASIC3 Devices. P_AC14was

removed. Table 2-15 · Different Components Contributing to the Static Power

Consumption in ProASIC3 Devices is new.

2-10,

2-11

The "PLL Contribution—PPLL" section was updated to change the P_PLLformula

2-13

2-71

from P_AC13+ P_AC14* F_CLKOUTto P_DC4+ P_AC13* F_CLKOUT

Both fall and rise values were included for t_DDRISUDand t_DDRIHDin

Table 2-93 · Input DDR Propagation Delays.

Table 2-98 · A3P015 Global Resource is new.

2-79

2-83

The typical value for Delay Increments in Programmable Delay Blocks was

changed from 160 to 200 in Table 2-106 · ProASIC3 CCC/PLL Specification.

v1.1

(January 2008)

Table note references were added to Table 2-2 · Recommended Operating

Conditions ¹, and the order of the table notes was changed.

2-2

2-3

The title for Table 2-4 · Overshoot and Undershoot Limits ¹was modified to

remove "as measured on quiet I/Os." Table note 1 was revised to remove

"estimated SSO density over cycles." Table note 2 was revised to remove "refers

only to overshoot/undershoot limits for simultaneous switching I/Os."

The "Power per I/O Pin" section was updated to include 3 additional tables

pertaining to input buffer power and output buffer power.

2-6

2-24

2-59

2-2

Table 2-29 · I/O Output Buffer Maximum Resistances ¹was revised to include

values for 3.3 V PCI/PCI-X.

Table 2-81 · LVDS Minimum and Maximum DC Input and Output Levels was

updated.

v1.0

(January 2008)

In Table 2-2 · Recommended Operating Conditions ¹, T_Jwas listed in the symbol

column and was incorrect. It was corrected and changed to T_A.

In Table 2-3 · Flash Programming Limits – Retention, Storage and Operating

Temperature1, Maximum Operating Junction Temperature was changed from

110°C to 100°C for both commercial and industrial grades.

2-2

The "PLL Behavior at Brownout Condition" section is new.

2-3

In the "PLL Contribution—PPLL" section, the following was deleted:

FCLKIN is the input clock frequency.

2-13

In Table 2-21 · Summary of Maximum and Minimum DC Input Levels, the note

was incorrect. It previously said T_Jand it was corrected and changed to T_A.

2-20

2-104

v1.3

ProASIC3 DC and Switching Characteristics

Previous Version

Changes in Current Version (v1.3)

Page

v1.0

(continued)

In Table 2-106 · ProASIC3 CCC/PLL Specification, the SCLK parameter and note 1

are new.

2-83

Table 2-116 · JTAG 1532 was populated with the parameter data, which was not

in the previous version of the document.

2-103

N/A

v2.2

This document was previously in datasheet v2.2. As a result of moving to the

handbook format, Actel restarted the version numbers so the new version

number is v1.0.

(July 2007)

v2.1

(May 2007)

The T_Jparameter in Table 3-2 • Recommended Operating Conditions was

changed to T_A, ambient temperature, and table notes 4–6 were added.

3-2

3-5

v2.0

(April 2007)

Table 3-5 • Package Thermal Resistivities was updated with A3P1000

information. The note below the table is also new.

Advance v0.7

(January 2007)

The timing characteristics tables were updated.

N/A

2-15

The "PLL Macro" section was updated to add information on the VCO and PLL

outputs during power-up.

The "PLL Macro" section was updated to include power-up information.

Table 2-11 • ProASIC3 CCC/PLL Specification was updated.

Figure 2-19 • Peak-to-Peak Jitter Definition is new.

2-15

2-29

2-18

2-21

The "SRAM and FIFO" section was updated with operation and timing

requirement information.

The "RESET" section was updated with read and write information.

2-25

2-28

The "Introduction" in the "Advanced I/Os" section was updated to include

information on input and output buffers being disabled.

PCI-X 3.3 V was added to Table 2-11 • VCCI Voltages and Compatible Standards.

2-29

2-34

In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance

descriptions were updated for levels 3 and 4.

Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3

Devices was updated.

2-64

2-40

Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–

Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum

current was updated from 4 x 52.7 to 5 x 52.7.

The "VCCPLF PLL Supply Voltage" section was updated.

2-50

2-51

The "VPUMP Programming Supply Voltage" section was updated.

The "GL Globals" section was updated to include information about direct input

into quadrant clocks.

V_JTAGwas deleted from the "TCK Test Clock" section.

2-51

In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK

was changed to TCK in note 2. Note 3 was also updated.

Ambient was deleted from Table 3-2 • Recommended Operating Conditions.

VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".

3-2

Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on

quiet I/Os)1.

v1.3

2-105

ProASIC3 DC and Switching Characteristics

Previous Version

Changes in Current Version (v1.3)

Page

Advance v0.7

(continued)

In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951.

3-5

Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was

updated.

3-6

3-5

Table 3-5 • Package Thermal Resistivities was updated.

Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels 3-17 to

Applicable to Commercial and Industrial Conditions—Software Default Settings

(Advanced) and Table 3-17 • Summary of Maximum and Minimum DC Input

Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were

updated.

3-17

Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings 3-20 to

(Advanced) and Table 3-21 • Summary of I/O Timing Characteristics—Software

Default Settings (Standard Plus) were updated.

3-20

Table 3-11 • Different Components Contributing to Dynamic Power

Consumption in ProASIC3 Devices was updated.

3-9

Table 3-24 • I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3- 3-22 to

25 • I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.

3-22

Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to

Commercial and Industrial Conditions was updated.

3-18

Table 3-28 • I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 • I/O 3-24 to

Short Currents IOSH/IOSL (Standard Plus) were updated.

3-26

The note in Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O

Reliability was updated.

3-27

Figure 3-33 • Write Access After Write onto Same Address, Figure 3-34 • Read 3-82 to

Access After Write onto Same Address, and Figure 3-35 • Write Access After

Read onto Same Address are new.

3-84

Figure 3-43 • Timing Diagram was updated.

3-96

N/A

Advance v0.5

(January 2006)

B-LVDS and M-LDVS are new I/O standards added to the datasheet.

The term flow-through was changed to pass-through.

Figure 2-7 • Efficient Long-Line Resources was updated.

N/A

2-7

The footnotes in Figure 2-15 • Clock Input Sources Including CLKBUF,

CLKBUF_LVDS/LVPECL, and CLKINT were updated.

2-16

The Delay Increments in the Programmable Delay Blocks specification in Figure

2-24 • ProASIC3E CCC Options.

2-24

The "SRAM and FIFO" section was updated.

The "RESET" section was updated.

2-21

2-25

2-27

2-28

The "WCLK and RCLK" section was updated.

The "RESET" section was updated.

The "Introduction" of the "Advanced I/Os" section was updated.

2-106

v1.3

ProASIC3 DC and Switching Characteristics

Previous Version

Changes in Current Version (v1.3)

Page

Advance v0.5

(continued)

The "I/O Banks" section is new. This section explains the following types of I/Os:

2-29

Advanced

Standard+

Standard

Table 2-12 • Automotive ProASIC3 Bank Types Definition and Differences is

new. This table describes the standards listed above.

PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-

11 • VCCI Voltages and Compatible Standards

2-29

Table 2-13 • ProASIC3 I/O Features was updated.

2-30

2-32

The "Double Data Rate (DDR) Support" section was updated to include

information concerning implementation of the feature.

The "Electrostatic Discharge (ESD) Protection" section was updated to include

testing information.

2-35

2-64

2-41

2-30

Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V

Input Tolerance Capabilities in ProASIC3 Devices.

The notes in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in

ProASIC3 Devices were updated.

The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"

section is new.

A footnote was added to Table 2-14 • Maximum I/O Frequency for Single-Ended

and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum

drive strength and high slew selected).

Table 2-18 • Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications

2-45

2-83

Table 2-50 • ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type

(A3P030 device)

Table 2-51 • ProASIC3 Output Drive for Standard+ I/O Bank Type was updated.

Table 2-54 • ProASIC3 Output Drive for Advanced I/O Bank Type was updated.

The "x" was updated in the "User I/O Naming Convention" section.

The "V_CCCore Supply Voltage" pin description was updated.

2-84

2-48

2-50

The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include

information concerning leaving the pin unconnected.

The "V_JTAGJTAG Supply Voltage" pin description was updated.

2-50

The "V_PUMPProgramming Supply Voltage" pin description was updated to

include information on what happens when the pin is tied to ground.

The "I/O User Input/Output" pin description was updated to include information

on what happens when the pin is unused.

2-50

2-51

2-53

2-54

3-1

The "JTAG Pins" section was updated to include information on what happens

when the pin is unused.

The "Programming" section was updated to include information concerning

serialization.

The "JTAG 1532" section was updated to include SAMPLE/PRELOAD

information.

"DC and Switching Characteristics" chapter was updated with new information.

v1.3

2-107

ProASIC3 DC and Switching Characteristics

Previous Version

Changes in Current Version (v1.3)

Page

N/A

Advance v0.3

M7 device information is new.

Table 2-4 • ProASIC3 Globals/Spines/Rows by Device was updated to include the

number or rows in each top or bottom spine.

2-16

EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options.

2-24

2-15

The "PLL Macro" section was updated. EXTFB information was removed from

this section.

The CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT}was updated in Table 2-

11 • ProASIC3 CCC/PLL Specification

2-29

EXTFB was removed from Figure 2-27 • CCC/PLL Macro.

Table 2-13 • ProASIC3 I/O Features was updated.

The "Hot-Swap Support" section was updated.

2-28

2-30

2-33

2-34

2-35

2-64

The "Cold-Sparing Support" section was updated.

"Electrostatic Discharge (ESD) Protection" section was updated.

The LVPECL specification in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance

Capabilities in ProASIC3 Devices was updated.

In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and V_CCIB2 was

changed to V_CCIB1.

2-97

2-50

The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"

section.

The "JTAG Pins" section was updated.

2-51

2-53

"128-Bit AES Decryption" section was updated to include M7 device

information.

Table 3-6 was updated.

3-6

Table 3-7 was updated.

In Table 3-11, PAC4 was updated.

Table 3-20 was updated.

3-93-8

3-20

3-27

The note in Table 3-32 was updated.

All Timing Characteristics tables were updated from LVTTL to Register Delays

3-31 to

3-73

The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.

3-85 to

3-90

F_TCKMAXwas updated in Table 3-110.

Figure 2-11 was updated.

3-97

2-9

Advance v0.2

The "Clock Resources (VersaNets)" section was updated.

The "VersaNet Global Networks and Spine Access" section was updated.

The "PLL Macro" section was updated.

Figure 2-27 was updated.

2-9

2-15

2-28

2-19

2-25

Figure 2-20 was updated.

Table 2-5 was updated.

Table 2-6 was updated.

2-108

v1.3

ProASIC3 DC and Switching Characteristics

Previous Version

Changes in Current Version (v1.3)

Page

Advance v0.2

(continued)

The "FIFO Flag Usage Considerations" section was updated.

2-27

Table 2-13 was updated.

2-30

2-31

2-34

2-64

2-45

2-51

2-48

3-6

Figure 2-24 was updated.

The "Cold-Sparing Support" section is new.

Table 2-43 was updated.

Table 2-18 was updated.

Pin descriptions in the "JTAG Pins" section were updated.

The "User I/O Naming Convention" section was updated.

Table 3-7 was updated.

The "Methodology" section was updated.

Table 3-40 and Table 3-39 were updated.

3-10

3-33,

3-32

v1.3

2-109

ProASIC3 DC and Switching Characteristics

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status datasheet may not have completed Actel’s