A3PE3000-2FPQ208 [ACTEL]
Field Programmable Gate Array, 3000000 Gates, CMOS, PQFP208, 0.50 MM PITCH, PLASTIC, QFP-208;型号: | A3PE3000-2FPQ208 |
厂家: | Actel Corporation |
描述: | Field Programmable Gate Array, 3000000 Gates, CMOS, PQFP208, 0.50 MM PITCH, PLASTIC, QFP-208 栅 |
文件: | 总160页 (文件大小:1251K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Advanced v0.2
™
ProASIC3E Flash Family FPGAs
Pro (Professional) I/O
Features and Benefits
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
High Capacity
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL and LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V,
GTL 2.5 V / 3.3 V, HSTL Class 1 and 2, SSTL2 Class 1 and 2,
SSTL3 Class 1 and 2
•
•
•
600 k to 3 Million System Gates
108 k to 504 kbits of True Dual-Port SRAM
Up to 616 User I/Os
Reprogrammable Flash Technology
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
•
•
•
Live-At-Power-Up Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered-Off
•
•
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay, Weak Pull-Up/Down
Schmitt-Trigger Option on Single-Ended Inputs
Weak Pull-Up/Down
On-Chip User Nonvolatile Memory
•
1 kbit of FlashROM (FROM)
Performance
IEEE1149.1 (JTAG) Boundary-Scan Test
Pin-Compatible Packages Across the ProASIC3E Family
•
150+ MHz Internal System Performance with 3.3 V,
66 MHz 64-bit PCI
•
Up to 350 MHz External System Performance
Clock Conditioning Circuit (CCC) and PLL
•
•
Six CCC Blocks, Each with an Integrated PLL
Flexible Phase Shift, Multiply/Divide, and Delay
Capabilities
In-System Programming (ISP) and Security
•
Secure ISP Using On-Chip 128-Bit AES Decryption via
JTAG (IEEE1532-compliant)
FlashLock™ to Secure FPGA Contents
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)
•
SRAMs and FIFOs
Low Power
•
Variable-Aspect Ratio 4,608-bit RAM Blocks (x1, x2, x4,
•
•
•
1.5 V Core Voltage for Low Power
x9, x18 Organizations Available)
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
•
•
True Dual-Port SRAM (except x18)
24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
High-Performance Routing Hierarchy
•
Programmable Embedded FIFO Control Logic
•
•
•
•
•
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Table 1 •
ProASIC3E Product Family
A3PE600
600 k
13,824
108
24
A3PE1500
A3PE3000
System Gates
1.5 M
38,400
270
60
1 k
Yes
6
3 M
75,264
504
112
1 k
VersaTiles (D-Flip-Flops)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM (FROM) Bits
Secure (AES) ISP
1 k
Yes
Yes
6
1
6
CCCs with Integrated PLLs
2
18
18
18
VersaNet Globals
I/O Banks
8
8
8
Maximum User I/Os
270
439
616
Package Pins
PQFP
PQ208
FG256, FG484
PQ208
FG484, FG676
PQ208
FG484, FG896
FBGA
Notes:
1. The PQ208 package has six CCCs and two PLLs.
2. Six chip (main) and three quadrant global networks are available.
3. For devices supporting lower densities, refer to the ProASIC3 Flash FPGAs datasheet.
January 2005
i
© 2005 Actel Corporation
See Actel’s website for the latest version of the datasheet.
ProASIC3E Flash Family FPGAs
I/Os Per Package
A3PE600
A3PE1500
A3PE3000
Single-Ended
I/O
Differential
I/O Pairs
Single-Ended
Differential
I/O Pairs
Single-Ended
Differential
I/O Pairs
Package
PQ208
FG256
FG484
FG676
FG896
Notes:
I/O
147
–
I/O
147
–
147
165
270
–
65
79
135
–
65
–
65
–
280
439
–
136
209
–
280
–
136
–
–
–
616
300
1. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
2. FG256 and FG484 are footprint-compatible packages.
3. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank
(group of I/Os). Refer to the "I/O Banks and I/O Standards Compatibility" on page 27 for more information about VREF and the use
of minibanks.
4. Advanced information subject to change.
Ordering Information
_
A3PE3000
1
FG
896
I
Application (Ambient Temperature Range)
Blank = Commercial (0˚C to +70˚C)
I = Industrial (–40˚C to +85˚C)
PP = Pre-Production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
=
=
PQ
FG
Plastic Quad Flat Pack (0.5 mm pitch)
Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard*
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
A3PE600
=
600,000 System Gates
A3PE1500 = 1,500,000 System Gates
A3PE3000 = 3,000,000 System Gates
Note: *DC and switching characteristics for –F speed grade targets based only on simulation.
The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might
be added and will be reflected in future revisions of this document. The –F speed grade is only supported in commercial temperature
range.
Figure 1 • Ordering Information
ii
Advanced v0.2
ProASIC3E Flash Family FPGAs
Temperature Grade Offerings
Package
PQ208
FG256
FG484
FG676
FG896
A3PE600
A3PE1500
A3PE3000
C, I
C, I
C, I
–
C, I
–
C, I
–
C, I
C, I
–
C, I
–
–
C, I
Note: C = Commercial Temperature Range: 0°C to 70°C Ambient
I = Industrial Temperature Range: –40°C to 85°C Ambient
Speed Grade and Temperature Grade Matrix
–F 3
Std.
✓
–1
✓
–2
✓
C
✓
I
–
✓
✓
✓
Notes:
1. C = Commercial Temperature Range: 0°C to 70°C Ambient
2. I = Industrial Temperature Range: –40°C to 85°C Ambient
3. DC and switching characteristics for –F speed grade targets based only on simulation.
The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in commercial
temperature range.
Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).
Advanced v0.2
iii
ProASIC3E Flash Family FPGAs
Table of Contents
Introduction and Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Device Architecture
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66
Embedded FROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
Package Pin Assignments
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Datasheet Information
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
International Traffic in Arms Regulations (ITAR) and Export Administration
Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
iv
Advanced v0.2
ProASIC3E Flash Family FPGAs
Introduction and Overview
General Description
ProASIC3E, the third-generation family of Actel Flash
FPGAs, offers performance, density, and features beyond
those of the ProASICPLUS® family. The nonvolatile Flash
technology gives ProASIC3E devices the advantage of
being a secure, low-power, single-chip solution that is
live at power-up. ProASIC3E is reprogrammable and
offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density
systems using existing ASIC or FPGA design flows and
tools.
Security
The nonvolatile, Flash-based ProASIC3E devices require
no boot PROM, so there is no vulnerable external
bitstream that can be easily copied. ProASIC3E devices
incorporate FlashLock, which provides
a
unique
combination of reprogrammability and design security
without external overhead, advantages that only an
FPGA with nonvolatile, Flash programming can offer.
ProASIC3E devices utilize a 128-bit Flash-based lock and a
separate AES key to secure programmed intellectual
property and configuration data. In addition, all FROM
data in the ProASIC3E devices can be encrypted prior to
loading, using the industry-leading AES-128 (FIPS192) bit
block cipher encryption standard. The AES standard was
adopted by the National Institute of Standards and
Technology (NIST) in 2000, and replaces the 1977 DES
ProASIC3E devices offer
1
kbit of on-chip, user
nonvolatile FlashROM (FROM) memory storage as well as
clock conditioning circuitry based on six integrated
phase-locked loops (PLLs). ProASIC3E devices have up to
3 million system gates, supported with up to 504 kbits of
true dual-port SRAM and up to 616 user I/Os.
standard. ProASIC3E devices have
a
built-in AES
decryption engine and a Flash-based AES key that make
them the most comprehensive programmable logic
device security solution available today. ProASIC3E
devices with AES-based security allow for secure, remote
field updates over public networks such as the Internet,
and ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed ProASIC3E device cannot be
read back, although secure design verification is possible.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low-unit
cost, performance, and ease of use. Unlike SRAM-based
FPGAs, the Flash-based ProASIC3E devices allow for all
functionality to be live at power-up; no external boot
PROM is required. On-board security mechanisms
prevent access to all the programming information and
enable secure remote updates of the FPGA logic.
Designers can perform secure remote in-system
reprogramming to support future design iterations and
field upgrades with confidence that valuable intellectual
property (IP) cannot be compromised or copied. Secure
ISP can be performed using the industry-standard AES
algorithm. The ProASIC3E family device architecture
mitigates the need for ASIC migration at higher user
volumes. This makes the ProASIC3E family a cost-
effective ASIC replacement solution, especially for
Security, built into the FPGA fabric, is an inherent
component of the ProASIC3E family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. ProASIC3E, with
FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible.
A
ProASIC3E device provides the most
impenetrable security for programmable logic designs.
applications
in
the
consumer,
networking/
communications, computing, and avionics markets.
Advanced v0.2
1-1
ProASIC3E Flash Family FPGAs
Single Chip
Low Power
Flash-based FPGAs store the configuration information
in on-chip Flash cells. Once programmed, the
configuration data is an inherent part of the FPGA
structure and no external configuration data needs to be
loaded at system power-up (unlike SRAM-based FPGAs).
Therefore, Flash-based ProASIC3E FPGAs do not require
system configuration components such as EEPROMs or
microcontrollers to load the device configuration data.
This reduces bill-of-materials costs and printed circuit
board (PCB) area, and increases security and system
reliability.
Flash-based
ProASIC3E
devices
exhibit
power
characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3E
devices have only a very limited power-on current surge,
and no high-current transition period, both of which
occur on many FPGAs.
ProASIC3E devices also have low dynamic power
consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3E family offers many benefits, including
nonvolatility and reprogrammability through an
advanced Flash-based, 130-nm LVCMOS process with
seven layers of metal. Standard CMOS design techniques
are used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant Flash switches allows
for very high logic utilization without compromising
device routability or performance. Logic functions within
the device are interconnected through a four-level
routing hierarchy.
Live at Power-Up
Actel’s Flash-based ProASIC3E devices support Level 0 of
the live-at-power-up classification standard, hence
helping in system components initialization, executing
critical tasks before the processor wakes up, setup and
configure memory blocks, clock generation, and bus
activity management. The live-at-power-up feature of
Flash-based ProASIC3E devices greatly simplifies total
system design and reduces total system cost, often
eliminating the need for Complex Programmable Logic
Device (CPLD) and clock generation PLL that are used for
this purpose in a system. In addition, glitches and
brownouts in system power will not corrupt the
ProASIC3E device’s Flash configuration, and unlike
SRAM-based FPGAs, the device will not have to be
reloaded when system power is restored. This enables
the reduction or complete removal of the configuration
PROM, expensive voltage monitor, brownout detection,
and clock generator devices from the PCB design. Flash-
based ProASIC3E devices simplify total system design,
and reduce cost and design risk, while increasing system
reliability and improving system initialization time.
Advanced Architecture
The proprietary ProASIC3E architecture provides
granularity comparable to standard-cell ASICs. The
ProASIC3E device consists of five distinct and
programmable architectural features (Figure 1-1 on page
1-3):
•
•
•
Dedicated FlashROM (FROM) memory
Dedicated SRAM/FIFO memory
Extensive clock conditioning circuitry (CCC) and
PLLs
Firm Errors
•
•
Pro I/O structure
FPGA VersaTiles
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. These errors are impossible to
prevent in SRAM FPGAs. The consequence of this type of
error can be a complete system failure. Firm errors do
not exist in the configuration memory of ProASIC3E
Flash-based FPGAs. Once it is programmed, the Flash cell
configuration element of ProASIC3E FPGAs cannot be
altered by high-energy neutrons and is therefore
immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily
be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
The FPGA core consists of a sea of VersaTiles. Each
VersaTile can be configured as a three-input logic
function or a D-flip-flop (with or without enable) or latch
by programming the appropriate Flash switch
interconnections. The versatility of the ProASIC3E core
tile as either
a
three-input look-up-table (LUT)
equivalent or a D-flip-flop/latch with enable allows for
efficient use of the FPGA fabric. The VersaTile capability
is unique to the Actel ProASIC families of Flash-based
FPGAs. VersaTiles are connected with any of the four
levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile,
reconfigurable interconnect programming. Maximum
core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry
allows for rapid, single-voltage (3.3 V) programming of
the ProASIC3E devices via an IEEE1532 JTAG interface.
1-2
Advanced v0.2
ProASIC3E Flash Family FPGAs
Bank 0
Bank 1
CCC
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
ISP AES
Decryption
User Nonvolatile
FlashROM (FROM)
Charge Pumps
Bank 5
Bank 4
Figure 1-1 • ProASIC3E Device Architecture Overview
The FROM can be programmed via the JTAG
programming interface, and its contents can be read
back either through the JTAG programming interface or
via direct FPGA core addressing. Note that the FROM can
ONLY be programmed from the JTAG interface, and
cannot be programmed from the internal logic array.
User Nonvolatile FlashROM (FROM)
Actel ProASIC3E devices have 1 kbit of on-chip, user-
accessible, nonvolatile FlashROM (FROM). The FROM can
be used in diverse system applications such as:
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
The FROM is programmed as 8 banks of 128 bits;
however, reading is performed on a random byte-by-
byte basis. A 7-bit address from the FPGA core defines
which of the 8 banks and which of the 16 bytes within
that bank are being read. The three MSBs of the FROM
address determine the bank and the four LSBs of the
FROM address define the byte.
Device serialization and/or inventory control
Subscription-based business models (for example,
set-top boxes)
•
Secure key storage for secure communications
algorithms
•
•
•
Asset management/tracking
Date stamping
The Actel ProASIC3E development software solutions,
Libero® Integrated Design Environment (IDE) and
Designer version 6.1 or later, have extensive support for
the FROM memory. One such feature is auto-generation
of sequential programming files for applications
requiring a unique serial number in each part. The
second part allows the inclusion of static data for system
version control. Data for the FROM can be generated
quickly and easily using Actel Libero IDE and Designer
software tools. Comprehensive programming file
support is also included to allow for easy programming
of large numbers of parts with differing FROM contents.
Version management
The FROM is written using the standard ProASIC3E
IEEE1532 JTAG programming interface. The core can be
individually programmed (erased and written) and on-
chip AES decryption can be used selectively to securely
load data over public networks, such as security keys
stored in the FROM for a user design.
Advanced v0.2
1-3
ProASIC3E Flash Family FPGAs
Additional CCC specifications:
SRAM and FIFO
•
Internal phase shift = 0°, 90°, 180°, and 270°.
Output phase shift depends on the output divider
configuration.
ProASIC3E devices have embedded SRAM blocks along
the north and south sides of the device. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available
memory configurations are 256x18, 512x9, 1kx4, 2kx2, or
4kx1 bits. The individual blocks have independent read
and write ports that can be configured with different bit
widths on each port. For example, data can be sent
through a four-bit port and read as a single bitstream.
The embedded SRAM blocks can be initialized via the
device JTAG port (ROM emulation mode), using the
UJTAG macro. Refer to the application note, UJTAG in
ProASIC3/E Devices, for more details.
•
•
Output duty cycle = 50% 1.5% or better
Low output jitter: worst case < 2.5% * clock period
peak-to-peak period jitter
–
–
–
70 ps at 350 MHz
90 ps at 100 MHz
180 ps at 24 MHz
•
•
•
Maximum acquisition time = 150 µs
Low power consumption of 5 mW
In addition, every SRAM block has an embedded FIFO
control unit. The control unit allows the SRAM block to
be configured as a synchronous FIFO without using
additional core VersaTiles. The FIFO width and depth are
programmable. The FIFO also features programmable
Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags in
addition to the normal Empty and Full flags. The
embedded FIFO control unit contains the counters
necessary for the generation of the read and write
address pointers. The embedded SRAM/FIFO blocks can
be cascaded to create larger configurations.
Exceptional tolerance to input period jitter –
allowable input jitter is up to 1.5 ns
•
Four precise phases; maximum misalignment
between adjacent phases of 40 ps * (350 MHz /
fOUT_CCC
)
Global Clocking
ProASIC3E devices have extensive support for multiple
clocking domains. In addition to the CCC and PLL support
described above, there is a comprehensive global clock
distribution network.
PLL and Clock Conditioning Circuitry (CCC)
ProASIC3E devices provide designers with very flexible
clock conditioning capabilities. Each member of the
ProASIC3E family contains an integrated PLL in each CCC.
Each VersaTile input and output port has access to nine
VersaNets: six chip (main) and three quadrant global
networks (Figure 2-9 on page 2-9). The VersaNets can be
driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to
distribute low-skew clock signals or for rapid distribution
of high-fanout nets.
The six CCC blocks are located in the four corners and the
centers of the east and west sides.
To maximize user I/Os in the PQ208 package, only the
center east and west PLLs are available. However, all six
CCC blocks are still usable; the four corner CCCs allow
simple clock delay operations as well as clock spine access
(refer to the "Clock Conditioning Circuits" section on
page 2-12 for more information).
Pro I/Os with Advanced I/O Standards
The ProASIC3E family of FPGAs features a flexible I/O
structure, supporting a range of voltages (1.5 V, 1.8 V,
2.5 V, and 3.3 V). In all, ProASIC3E FPGAs support 19
different I/O standards, including single-ended,
The inputs of the six CCC blocks are accessible from the
FPGA core or from one of several I/O inputs located near
the CCC that have dedicated connections to the CCC
block.
differential,
and
voltage-referenced.
For
more
information, see Table 2-23 on page 2-47.
The I/Os are organized into banks, with eight banks per
device (two per side). The configuration of these banks
determines the I/O standards supported (see Table 2-14
on page 2-29 for more information). Each I/O bank is
subdivided into VREF minibanks, which are used by
voltage-referenced I/Os. VREF minibanks contain from 8
to 18 I/Os. All the I/Os in a given minibank share a
common VREF line. Therefore, if any I/O in a given VREF
minibank is configured as a VREF pin, the remaining I/Os
in that minibank will be able to use that reference
voltage.
The CCC block has the following key features:
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz to
350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to
350 MHz
Clock delay adjustment via programmable and
fixed delays from –7.56 ns to +11.12 ns
Two programmable delay types; refer to Figure 2-
16 on page 2-16, Table 2-4 on page 2-17, and the
"Features Supported on Every I/O" section on
page 2-30 for more information.
•
•
Clock skew minimization
Clock frequency synthesis
1-4
Advanced v0.2
ProASIC3E Flash Family FPGAs
Each I/O module contains several input, output, and
enable registers (Figure 2-23 on page 2-32). These
registers allow the implementation of the following:
VersaTiles
The ProASIC3E core consists of VersaTiles, which have
been enhanced over the ProASICPLUS core tiles. The
ProASIC3E VersaTile supports the following:
•
Single-Data-Rate applications (e.g., PCI 66 MHz,
bidirectional SSTL 2 and 3 Class I and II)
•
•
•
•
All three-input logic functions – LUT-3 equivalent
Latch with clear or set
•
Double-Data-Rate applications (e.g., DDR LVDS I/O
for point-to-point communications and DDR
200 MHz SRAM using bidirectional HSTL Class II –
"DDR Module Specifications" section on page 3-
55)
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-2 for VersaTile configurations.
For more information about VersaTiles, refer to the
"VersaTile" section on page 2-2.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-2 • VersaTile Configurations
Advanced v0.2
1-5
ProASIC3E Flash Family FPGAs
Related Documents
Application Notes
In-System Programming (ISP) in ProASIC3/E Using FlashPro3
http://www.actel.com/documents/PA3_E_ISP_AN.pdf
Optimal Usage of Global Network Spines in ProASICPLUS Devices
http://www.actel.com/documents/PAPLUS_Spines_AN.pdf
ProASIC3/E FlashROM (FROM)
http://www.actel.com/documents/PA3_E_FROM_AN.pdf
ProASIC3/E Security
http://www.actel.com/documents/PA3_E_Security_AN.pdf
ProASIC3/E SRAM/FIFO Blocks
http://www.actel.com/documents/PA3_E_SRAMFIFO_AN.pdf
Programming a ProASIC3/E Using a Microprocessor
http://www.actel.com/documents/PA3_E_Microprocessor_AN.pdf
UJTAG Applications in ProASIC3/E Devices
http://www.actel.com/documents/PA3_E_UJTAG_AN.pdf
Using DDR for ProASIC3/E Devices
http://www.actel.com/documents/PA3_E_DDR_AN.pdf
Using Global Resources in Actel ProASIC3/E Devices
http://www.actel.com/documents/PA3_E_Global_AN.pdf
For additional ProASIC3E application notes, go to http://www.actel.com/techdocs/appnotes/products.aspx.
User’s Guides
ACTgen Core Reference Guide
http://www.actel.com/documents/gen_refguide.pdf
Designer’s User’s Guide
http://www.actel.com/documents/designerUG.pdf
ProASIC3/E Macro Library Guide
http://www.actel.com/documents/pa3_libguide.pdf
1-6
Advanced v0.2
ProASIC3E Flash Family FPGAs
Device Architecture
information (Figure 2-1). One is the sensing transistor,
which is only used for writing and verification of the
floating gate voltage. The other is the switching
transistor. The latter is used to connect or separate
routing nets, or to configure VersaTile logic. It is also
used to erase the floating gate. Dedicated high-
performance lines are connected as required using the
Flash switch for fast, low-skew, global signal distribution
throughout the device core. Maximum core utilization is
possible for virtually any design. The use of the Flash
switch technology also removes the possibility of firm
errors, which are increasingly common in SRAM-based
FPGAs.
Introduction
Flash Technology
Advanced Flash Switch
Unlike SRAM FPGAs, the ProASIC3E family uses a live-on-
power-up ISP Flash switch as its programming element.
Flash cells are distributed throughout the device to
provide nonvolatile, reconfigurable programming to
connect signal lines to the appropriate VersaTile inputs
and outputs. In the Flash switch, two transistors share
the floating gate, which stores the programming
Switch In
Floating Gate
Sensing
Switching
Word
Switch Out
Figure 2-1 • ProASIC3E Flash-Based Switch
Advanced v0.2
2-1
ProASIC3E Flash Family FPGAs
•
•
D-flip-flop with clear or set
Device Overview
Enable D-flip-flop with clear or set (on a fourth
input)
The ProASIC3E device family consists of five distinct
programmable architectural features (Figure 2-2):
VersaTiles can flexibly map the logic and sequential gates
of a design. The inputs of the VersaTile can be inverted
(allowing bubble pushing), and the output of the tile can
connect to high-speed, very-long-line routing resources.
VersaTiles and larger functions are connected with any of
the four levels of routing hierarchy.
•
•
•
•
•
FPGA fabric/core (VersaTiles)
Routing and clock resources (VersaNets)
FlashROM (FROM) memory
Dedicated SRAM/FIFO memory
Pro I/O structure
When the VersaTile is used as an enable D-flip-flop, the
SET/CLR is supported by a fourth input. The fourth input
is routed to the core cell over the VersaNet (global)
network.
Core Architecture
VersaTile
The proprietary ProASIC3E family architecture provides
granularity comparable to gate arrays. The ProASIC3E
device core consists of a sea-of-VersaTiles architecture.
The SET/CLR signal can only be routed to this fourth
input over the VersaNet (global) network. However, if in
the user design, the SET/CLR signal is not routed over the
VersaNet network, a compile warning message will be
given and the intended logic function will be
implemented by two VersaTiles instead of one.
As illustrated in Figure 2-3 on page 2-3, there are four
inputs in a logic VersaTile cell, and each VersaTile can be
configured using the appropriate Flash switch
connections:
The output of the VersaTile is F2 when the connection is
to the ultra-fast local lines, or YL when connection is to
the efficient long-lines or very-long-lines resources.
•
•
Any three-input logic function
Latch with clear or set
Bank 0
Bank 1
CCC
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
ISP AES
Decryption
User Nonvolatile
FlashROM (FROM)
Charge Pumps
Bank 5
Bank 4
Figure 2-2 • ProASIC3E Device Architecture Overview
2-2
Advanced v0.2
ProASIC3E Flash Family FPGAs
0
1
Y
pin 1
Data
X3
0
1
0
1
F2
YL
0
1
CLK
X2
CLR/
Enable
X1
CLR
XC*
Ground
Legend:
Via (hard connection) Switch (Flash connection)
Note: *This input can only be connected to the global clock distribution network.
Figure 2-3 • ProASIC3E Core VersaTile
Advanced v0.2
2-3
ProASIC3E Flash Family FPGAs
Since the I/O coordinate system changes depending on
the die/package combination, it is not listed in Table 2-1.
The Designer ChipPlanner tool provides array
coordinates for all I/O locations. I/O and cell coordinates
are used for placement constraints. However, I/O
placement is easier by package pin assignment.
Array Coordinates
During many place-and-route operations in the Actel
Designer software tool, it is possible to set constraints
that require array coordinates. Table 2-1 is provided as a
reference. The array coordinates are measured from the
lower left (0, 0). They can be used in region constraints
for specific logic groups/blocks, designated by a wildcard,
and can contain core cells, memories, and I/Os.
Figure 2-4 illustrates the array coordinates of an A3PE600
device. For more information on how to use array
coordinates for region/placement constraints, see the
Designer User's Guide or online help (available in the
software) for ProASIC3E software tools.
Table 2-1 provides array coordinates of core cells and
memory blocks.
Table 2-1 • ProASIC3E Array Coordinates
VersaTiles
Memory Rows
Top
All
Min.
Max.
Bottom
(x, y)
Min.
(x, y)
(0, 0)
(0, 0)
(0, 0)
Max.
(x, y)
Device
x
3
3
3
y
4
4
6
x
y
(x, y)
(3, 76)
A3PE600
A3PE1500
A3PE3000
194
322
450
75
(3, 2)
(197, 79)
(325, 127)
(453, 179)
123
173
(3, 2)
(3, 124)
(3, 2) or (3, 4)
(3, 174) or (3, 176)
I/O Tile
Top Row (7, 79) to (189, 79)
Bottom Row (5, 78) to (192, 78)
(0,79)
(197, 79)
(3, 77)
(3, 76)
Memory
Blocks
(194, 77)
(194, 76)
Memory
Blocks
VersaTile (Core)
(3, 75)
(194, 75)
VersaTile (Core)
(194, 4)
VersaTile(Core)
VersaTile (Core)
(3, 4)
(194, 3)
(194, 2)
Memory
Blocks
(3, 3)
(3, 2)
Memory
Blocks
(197, 1)
(197, 0)
(0, 0)
I/O Tile
UJTAG FlashROM
Top Row (5, 1) to (168, 1)
Top Row (192, 1) to (169, 1)
Bottom Row (7, 0) to (165, 0)
Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates
are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}.
Figure 2-4 • Array Coordinates for A3PE600
2-4
Advanced v0.2
ProASIC3E Flash Family FPGAs
buffers are inserted automatically by routing software to
limit the loading effects.
Routing Architecture
Routing Resources
The high-speed, very-long-line resources, which span the
entire device with minimal delay, are used to route very
long or high-fanout nets: length +/–12 VersaTiles in the
vertical direction and length +/–16 in the horizontal
direction from a given core VersaTile (Figure 2-7 on page
2-7). Very long lines in ProASIC3E devices have been
enhanced over those in previous ProASIC families. This
provides a significant performance boost for long-reach
signals.
The routing structure of ProASIC3E devices is designed to
provide high performance through a flexible four-level
hierarchy of routing resources: ultra-fast local resources,
efficient long-line resources, high-speed, very-long-line
resources, and the high-performance VersaNet networks.
The ultra-fast local resources are dedicated lines that allow
the output of each VersaTile to connect directly to every
input of the eight surrounding VersaTiles (Figure 2-5). The
exception to this is that the SET/CLR input of a VersaTile
configured as a D-type flip-flop is driven only by the
VersaTile global network.
The high-performance VersaNet global networks are
low-skew, high-fanout nets that are accessible from
external pins or from internal logic (Figure 2-8 on page
2-8). These nets are typically used to distribute clocks,
resets, and other high-fanout nets requiring minimum
skew. The VersaNet networks are implemented as clock
trees, and signals can be introduced at any junction.
These can be employed hierarchically with signals
accessing every input on all VersaTiles.
The efficient, long-line resources provide routing for
longer distances and higher fanout connections. These
resources vary in length (spanning 1, 2, or 4 VersaTiles),
run both vertically and horizontally, and cover the entire
ProASIC3E device (Figure 2-6 on page 2-6). Each VersaTile
can drive signals onto the efficient long-line resources,
which can access every input of every VersaTile. Active
Long Lines
L
L
L
L
L
L
Inputs
Ultra-Fast Local Lines
(connects a VersaTile to the
adjacent VersaTile, I/O buffer,
or memory block)
L
L
L
Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection.
Figure 2-5 • Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors
Advanced v0.2
2-5
ProASIC3E Flash Family FPGAs
Spans Four VersaTiles
Spans One VersaTile
Spans Two VersaTiles
Logic VersaTile
L
L
L
L
L
L
L
L
L
L
L
L
Spans One VersaTile
L
L
L
L
L
L
Spans Two VersaTiles
Spans Four VersaTiles
L
L
L
L
L
L
VersaTile
L
L
L
L
L
L
Figure 2-6 • Efficient Long-Line Resources
2-6
Advanced v0.2
ProASIC3E Flash Family FPGAs
High-Speed, Very-Long-Line Resources
Pad Ring
SRAM
16x12 Block of VersaTiles
Pad Ring
Figure 2-7 • Very-Long-Line Resources
Advanced v0.2
2-7
ProASIC3E Flash Family FPGAs
access to nine global network resources: three quadrant
and six chip (main) global networks, and a total of 18
globals on the device. Each of these networks contain
spines and rows that reach all the VersaTiles in the
quadrants (Figure 2-9 on page 2-9). This flexible VersaNet
global network architecture allows users to map up to 252
different internal/external clocks in a ProASIC3E device.
Details on the VersaNet networks are given in Table 2-2
on page 2-9. The flexible use of the ProASIC3E VersaNet
global network allows the designer to address several
design requirements. User applications that are clock-
resource-intensive can easily route external or gated
internal clocks using VersaNet global routing networks.
Designers can also drastically reduce delay penalties and
minimize resource usage by mapping critical, high-fanout
nets to the VersaNet global network.
Clock Resources (VersaNets)
ProASIC3E devices offer powerful and flexible control of
circuit timing through the use of analog circuitry. Each
chip has six CCCs containing a phase-locked loop (PLL)
core, delay lines, phase shifter (0°, 90°, 180°, 270°), clock
multiplier/dividers, and all the circuitry needed for the
selection and interconnection of inputs to the VersaNet
global network. The east and west CCCs each have access
to three VersaNet global lines on each side of the chip
(six total lines).
Advantages of the VersaNet Approach
One of the architectural benefits of ProASIC3E is the set of
powerful and low-delay VersaNet global networks.
ProASIC3E offers six chip (main) global networks that are
distributed from the center of the FPGA array (Figure 2-8).
In addition, ProASIC3E devices have three regional globals
in each of the four chip quadrants. Each core VersaTile has
Quadrant Global Pads
High-Performance
VersaNet Global Network
Pad Ring
Top Spine
Main (chip)
Global Network
Global
Pads
Chip (main)
Global Pads
Global Spine
Global Ribs
Bottom Spine
Spine-Selection
Tree MUX
Pad Ring
Note: Not applicable to the A3P030 device.
Figure 2-8 • Overview of ProASIC3E VersaNet Global Network
2-8
Advanced v0.2
ProASIC3E Flash Family FPGAs
North Quadrant Global Network
CCC
CCC
3
3
3
3
3
Chip (main)
Global
Network
6
6
6
6
6
6
6
CCC
3
CCC
6
3
3
3
3
CCC
CCC
South Quadrant Global Network
Note:
Figure 2-9 • Global Network Architecture
Table 2-2 • ProASIC3E Globals/Spines/Rows by Device
A3PE600
9
A3PE1500
9
A3PE3000
9
Global Clock Networks (Trees)*
Clock Spines/Trees
12
20
28
Total Spines
108
180
252
VersaTiles in Each Top or Bottom Spine
Total VersaTiles
1,120
13,824
1,888
38,400
2,656
75,264
Note: *There are six chip (main) globals and three globals per quadrant.
Advanced v0.2
2-9
ProASIC3E Flash Family FPGAs
segments, radiating from the center of a device, are the
same height.
VersaNet Global Networks and Spine Access
The ProASIC3E architecture contains nine segmented
global networks that can access all the VersaTiles, SRAM
memory, and I/O tiles on the ProASIC3E device. These
VersaNet global networks offer fast, low-skew routing
resources for high-fanout nets, including clock signals. In
addition, these highly-segmented global networks offer
users the flexibility to create low-skew local networks
using spines for up to 252 internal/external clocks (in an
A3PE3000 device) or other high-fanout nets in ProASIC3E
devices. Optimal usage of these low-skew networks can
result in significant improvement in design performance
on ProASIC3E devices.
Each spine covers a certain area of the ProASIC3E device
(the "scope" of the spine). Each spine is accessed by the
dedicated global network MUX tree architecture, which
defines how a particular spine is driven—either by the
signal on the global network from a CCC, for example, or
another net defined by the user (Figure 2-11 on page 2-
11). Quadrant spines can be driven from user I/Os on the
north and south sides of the die. The ability to drive spines
in the quadrant global networks can have a significant
effect on system performance for high-fanout inputs to a
design.
The nine spines available in a vertical column reside in
global networks with two separate regions of scope: the
quadrant global network, which has three spines, and
the chip (main) global network, which has six spines.
There are four quadrant global network regions per
device (Figure 2-9 on page 2-9).
Details of the chip (main) global network spine-selection
MUX are presented in Figure 2-11 on page 2-11. The
spine drivers for each spine are located in the middle of
the die.
Quadrant spines are driven from a north or south rib.
Access to the top and bottom ribs is from the corner CCC
or from the I/O on the north and south sides of the
device.
The spines are the vertical branches of the global
network tree, shown in Figure 2-10. Each spine in a
vertical column of a chip (main) global network is further
divided into two spine segments: one in the top and one
in the bottom half of the die. Top and bottom spine
For details on using spines in ProASIC3E devices, see the
Actel application note Optimal Usage of Global Network
Spines in ProASICPLUS Devices.
Quadrant Global Pads
High-Performance
Global Network
T1
T2
T3
PAD RING
Top Spine
Global
Pads
Chip (main)
Global Pads
Global Spine
Global Ribs
Bottom Spine
Scope of Spine
(Shaded area
plus local RAMs
and I/Os)
Spine-Selection
MUX
Embedded
RAM Blocks
PAD RING
Logic Tiles
B1
B2
B3
Figure 2-10 • Spines in a Global Clock Tree Network
2-10
Advanced v0.2
ProASIC3E Flash Family FPGAs
Clock Aggregation
Clock aggregation allows for multi-spine clock domains.
A MUX tree provides the necessary flexibility to allow
long lines or I/Os to access domains of one, two, or four
global spines. Signal access to the clock aggregation
system is achieved through long-line resources in the
central rib, and also through local resources in the north
and south ribs, allowing I/Os to directly feed into the
clock system. As Figure 2-12 indicates, this access system
is contiguous.
There is no break in the middle of the chip for the north
and south I/O VersaNet access. This is different from the
quadrant clocks, located in these ribs, which only reach
the middle of the rib. Refer to the Using Global
Resources in Actel ProASIC3/E Devices application note.
Internal/External
Signals
Internal/External
Signals
Tree Node MUX
Tree Node MUX
Internal/External
Signal
Tree Node MUX
Global Rib
Internal/External
Signal
Global Driver MUX
Spine
Figure 2-11 • Spine Selection MUX of Global Tree
Global Spine
Global Rib
Global Driver and MUX
I/O Tiles
I/O Access
Internal Signal Access
Global Signal Access
Tree Node MUX
Figure 2-12 • Clock Aggregation Tree Architecture
Advanced v0.2
2-11
ProASIC3E Flash Family FPGAs
Global Buffers with No Programmable Delays
Clock Conditioning Circuits
The CLKBUF and CLKBUF_LVPECL/LVDS macros are
composite macros that include an I/O macro driving a
global buffer, which uses a hardwired connection.
Overview of Clock Conditioning Circuitry
In ProASIC3E devices, the clock conditioning circuits
(CCCs) are used to implement frequency division,
frequency multiplication, phase shifting, and delay
operations.
The CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros
are pass-through clock sources and do not use the PLL or
provide any programmable delay functionality.
The CLKINT macro provides a global buffer function
driven by the FPGA core.
The CCCs are available in six chip locations – each of the
four chip corners and in the middle of the east and west
chip sides.
Many specific CLKBUF macros support the wide variety of
single-ended and differential I/O standards supported by
ProASIC3E devices. The available CLKBUF macros are
described in the ProASIC3/E Macro Library Guide.
Each CCC can implement up to three independent global
buffers (with or without programmable delay), or a PLL
function
(programmable
frequency
division/
multiplication, phase shift, and delays) with up to three
global outputs. Unused global outputs of a PLL can be
used to implement independent global buffers, up to a
maximum of three global outputs for a given CCC.
Global Buffer with Programmable Delay
The CLKDLY macro is a pass-through clock source that
does not use the PLL, but provides the ability to delay the
clock input using a programmable delay. The CLKDLY
macro takes the selected clock input and adds a user-
defined delay element. This has the effect of
frequency-dependent output clock phase shift from the
input clock.
A global buffer can be placed in any of the three global
locations (CLKA-GLA, CLKB-GLB, and CLKC-GLC) of a
given CCC.
a
A PLL macro uses the CLKA CCC input to drive its
reference clock. It uses the GLA and optionally the GLB
and GLC global outputs to drive the global networks. A
PLL macro can also drive the YB and YC regular core
outputs. The GLB (or GLC) global outputs cannot be
reused if the YB (or YC) outputs are used (Figure 2-13 on
page 2-13).
The CLKDLY macro can be driven by an INBUF macro to
create a composite macro, where the I/O macro drives
the global buffer (with programmable delay) using a
hardwired connection. In this case, the I/O must be
placed in one of the dedicated global I/O locations.
The CLKDLY macro can be driven directly from the FPGA
core.
Each global buffer, as well as the PLL reference clock, can
be driven from one of the following:
The CLKDLY macro can also be driven from an I/O that is
routed through the FPGA regular routing fabric. In this
case, users must instantiate a special macro, PLLINT, to
differentiate from the hardwired I/O connection
described earlier.
•
•
•
Three dedicated single-ended I/Os using
hardwired connection
a
Two dedicated differential I/Os using a hardwired
connection
The visual CLKDLY configuration in the ACTgen part of
the Libero IDE and Designer tools allows the user to
select the desired amount of delay, and configures the
delay elements appropriately. ACTgen also allows the
user to select where the input clock is coming from.
ACTgen will automatically instantiate the special macro,
PLLINT, when needed.
The FPGA core
The CCC block is fully configurable, either via Flash
configuration bits set in the programming bitstream or
through an asynchronous interface. This asynchronous
interface is dynamically accessible from inside the
ProASIC3E device to permit parameter changes (such as
divide ratios) during device operation. To increase the
versatility and flexibility of the clock conditioning
system, the CCC configuration is determined either by
the user during the design process, with configuration
data being stored in Flash memory as part of the device
programming procedure, or by writing data into a
dedicated shift register during normal device operation.
This latter mode allows the user to dynamically
reconfigure the CCC without the need for core
programming. The shift register is accessed through a
simple serial interface. Refer to the UJTAG Applications
in ProASIC3/E Devices application note and the "CCC
Electrical Specifications" section on page 2-17 for more
information.
Many specific INBUF macros support the wide variety of
single-ended and differential I/O standards supported by
the ProASIC3E family. The available INBUF macros are
described in the ProASIC3/E Macro Library Guide.
2-12
Advanced v0.2
ProASIC3E Flash Family FPGAs
Clock Source
Clock Conditioning
Output
Input LVDS/LVPECL Macro
PLL Macro
GLA
CLKA
GLA
LOCK
GLB
YB
GLC
YC
EXTFB
PADN
PADP
POWERDOWN
Y
or
GLA and (GLB or YB)
or
OADIV[4:0]
OAMUX[2:0]
DLYGLA[4:0]
OBDIV[4:0]
OBMUX[2:0]
DLYYB[4:0]
DLYGLB[4:0]
OCDIV[4:0]
OCMUX[2:0]
DLYYC[4:0]
DLYGLC[4:0]
FINDIV[6:0]
FBDIV[6:0]
FBDLY[4:0]
FBSEL[1:0]
INBUF* Macro
PAD
GLA and (GLC or YC)
or
Y
GLA and (GLB or YB) and
(GLC or YC)
XDLYSEL
VCOSEL[2:0]
CLKDLY Macro
CLK GL
GLA
or
GLB
or
DLYGL[4:0]
GLC
CLKBUF_LVDS/LVPECL Macro
PADN
CLKBUF Macro
CLKINT Macro
PAD
Y
PADP
Y
A
Y
Notes:
1. See the Actel website for future application notes concerning the dynamic PLL. Refer to "PLL Function" section on page 2-14 for
signal descriptions.
2. Refer to the ProASIC3/E Macro Library Guide for more information.
Figure 2-13 • ProASIC3E CCC Options
Advanced v0.2
2-13
ProASIC3E Flash Family FPGAs
PLL Function
The PLL functionality of the clock conditioning block is
supported by the PLL macro. Note that the PLL macro
reference clock uses the CLKA input of the CCC block,
which is only accessible from the global A[0:2] package
pins. Refer to Figure 2-14 on page 2-15 for more
information.
Note: Care must be taken if the output delay element is
used in conjunction with an output divide. As there are a
finite number of dividers and delay elements, exact
output frequency and output phase may not always be
derived from the input clock frequency.
The PLL macro reference clock can be driven by an INBUF
macro to create a composite macro, where the I/O macro
drives the global buffer (with programmable delay)
using a hardwired connection. In this case, the I/O must
be placed in one of the dedicated global I/O locations.
The PLL macro supports three inputs and up to six
outputs (Figure 2-16 on page 2-16).
Inputs:
•
•
CLKA: selected clock input
The PLL macro reference clock can be driven directly
from the FPGA core.
EXTFB: allows an external signal to be compared
to a reference clock in the PLL core's phase
detector
The PLL macro reference clock can also be driven from an
I/O that is routed through the FPGA regular routing
fabric. In this case, users must instantiate a special macro,
PLLINT, to differentiate from the hardwired I/O
connection described earlier.
•
Powerdown (active Low): disables PLLs. The
default state is Powerdown On (active Low).
Outputs:
•
•
•
Lock: indicates that PLL output has locked on the
input reference signal
The visual PLL configuration in ACTgen, associated with
the Libero IDE and Designer tools, will derive the
necessary internal divider ratios based on the input
frequency and desired output frequencies selected by
the user. ACTgen also allows the user to select the
various delays and phase shift values necessary to adjust
the phases between the reference clock (CLKA) and the
derived clocks (GLA, GLB, GLC, YB and YC). ACTgen also
allows the user to select where the input clock is coming
from. ACTgen automatically instantiates the special
macro, PLLINT, when needed.
GLA, GLB, GLC: outputs to respective global
networks
YB, YC: allows output from the CCC to be routed
back to the FPGA core
As previously described, the PLL allows up to five flexible
and independently configurable clock outputs. Figure 2-13
on page 2-13 illustrates the various clock output options
and delay elements.
As illustrated, the PLL will support three distinct output
frequencies from a given input clock. Two of these (GLB
and GLC) can be routed to the B and C global network
access, respectively, and/or routed to the device core (YB
and YC).
Also in the feedback loop, there is a delay element that
can be used to advance the clock relative to the
reference clock.
There are five delay elements to support phase control
on all five outputs (GLA, GLB, GLC, YB, and YC).
2-14
Advanced v0.2
ProASIC3E Flash Family FPGAs
Each shaded box represents an
input buffer called out by the
appropriate INBUF or
To Core
INBUF_LVDS/LVPECL.
Sample Pin Names
1
GAA0/IO0NDB0V0
1
+
GAA1/IO00PDB0V0
Source for CCC
(CLKA or CLKB or CLKC)
Routed Clock
(from FPGA Core)
1
2
+
GAA2/IO13PDB7V1
GAA[0:2]: GA represents global in the northwest corner
Notes:
1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric.
Refer to the "User I/O Naming Convention" section on page 2-48 for more information.
2. Instantiate the routed clock source input as follows:
a) Connect the output of a logic element to the clock input of PLL, CLKDLY, or CLKINT macro.
b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location. "User I/O Naming Convention"
section on page 2-48.
Figure 2-14 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT
CLKBUF
CLKINT
Y
A
PAD
Y
CLKBUF_LVDS/LVPECL
Y
PADN
PADP
Figure 2-15 • CLKBUF and CLKINT
Advanced v0.2
2-15
ProASIC3E Flash Family FPGAs
Table 2-3 • Available Selections of I/O Standards within
CLKBUF and CLKBUF_LVDS/LVPECL Macros
CLKBUF Macros
CLKBUF_LVCMOS5
CLKBUF_LVCMOS33*
CLKBUF_LVCMOS25
CLKBUF_LVCMOS18
CLKBUF_LVCMOS15
CLKBUF_PCI
CLKA
GLA
LOCK
GLB
YB
EXTFB
POWERDOWN
GLC
YC
OADIV[4:0]*
OAMUX[2:0]*
DLYGLA[4:0]*
OBDIV[4:0]*
OBMUX[2:0]*
DLYYB[4:0]*
DLYGLB[4:0]*
OCDIV[4:0]*
OCMUX[2:0]*
DLYYC[4:0]*
DLYGLC[4:0]*
FINDIV[6:0]*
FBDIV[6:0]*
FBDLY[4:0]*
FBSEL[1:0]*
CLKBUF_PCIX
CLKBUF_GTL251
CLKBUF_GTL331
CLKBUF_GTLP251
CLKBUF_GTLP331
CLKBUF_HSTL_I2
CLKBUF_HSTL_II2
CLKBUF_SSTL3_I2
CLKBUF_SSTL3_II1Y
CLKBUF_SSTL2_I2
CLKBUF_SSTL2_II2
CLKBUF_LVDS
XDLYSEL*
VCOSEL[2:0]*
Note: *See the Actel website for future application notes
concerning the dynamic PLL.
CLKBUF_LVPECL2
Figure 2-16 • CCC/PLL Macro
Note: *By default, the CLKBUF macro uses the 3.3 V LVTTL I/O
technology. For more details refer to the ProASIC3/E
Macro Library Guide.
CLKDLY
CLK
GL
DLYGL[4:0]
Note: The CLKDLY macro uses programmable delay element type 2.
Figure 2-17 • CLKDLY
2-16
Advanced v0.2
ProASIC3E Flash Family FPGAs
CCC Electrical Specifications
Timing Characteristics
Table 2-4 • ProASIC3E CCC/PLL Specification
Parameter
Min.
1.5
Typ.
Max.
350
Unit
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks1, 2
Number of Programmable Values in Each Programmable Delay Block
Input Period Jitter
0.75
350
160
32
1.5
ns
Long Term Output Pk-Pk Period Jitter
at fPLL_OUT = 24 MHz
–
–
–
180
90
ps
ps
ps
µs
%
ns
ns
ns
at fPLL_OUT = 100 MHz
at fPLL_OUT = 350 MHz
70
Acquisition Time
150
51.5
5.56
5.56
Output Duty Cycle
48.5
0.6
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
Notes:
0.025
2.2
1. This delay is a function of voltage and temperature. See Table 3-6 on page 3-4 for deratings.
2. TJ = 25°C, VCC = 1.5 V
Advanced v0.2
2-17
ProASIC3E Flash Family FPGAs
Physical Implementation of CCC
CCC Programming
The CCC circuit is composed of the following (Figure 2-18):
The clock conditioning circuit block is fully configurable,
either via static Flash configuration bits in the array, set
by the user in the programming bitstream, or through an
asynchronous dedicated shift register dynamically
accessible from inside the ProASIC3E device. The
dedicated shift register permits parameter changes such
as PLL divide ratios and delays during device operation.
This latter mode allows the user to dynamically
reconfigure the PLL without the need for core
programming. The register file is accessed through a
simple serial interface. Refer to the UJTAG Applications
in ProASIC3/E Devices application note for more
information.
•
•
•
PLL core
Three phase selectors
Six programmable delays and one fixed delay that
advance/delay phase
•
Five programmable frequency dividers that
provide frequency multiplication/division (not
shown in Figure 2-18, because they are
automatically configured based on the user's
required frequencies)
•
One dynamic shift register that provides CCC
dynamic reconfiguration capability
CLKA
GLA
Four-Phase Output
Programmable
PLL Core
Delay Type 2
Phase
Select
Programmable
Delay Type 1
Fixed Delay
GLB
Programmable
Delay Type 2
EXTFB
Phase
Select
Programmable
Delay Type 1
YB
GLC
Programmable
Delay Type 2
Clock divider and clock multiplier
blocks are not shown in this figure
or in ACTgen. They are automatically
configured based on the user's
required frequencies.
Phase
Select
YC
Programmable
Delay Type 1
Note: Refer to the "Clock Conditioning Circuits" section on page 2-12 and Table 2-4 on page 2-17 for signal descriptions.
Figure 2-18 • PLL Block
2-18
Advanced v0.2
ProASIC3E Flash Family FPGAs
Nonvolatile Memory (NVM)
Overview of User Nonvolatile FlashROM (FROM)
ProASIC3E devices have 1 kbit of on-chip nonvolatile
Flash memory that can be read from the FPGA core
fabric. The FROM is arranged in 8 banks of 128 bits
during programming. The 128 bits in each bank are
addressable as 16 bytes during the read back of the
FROM from the FPGA core (Figure 2-19).
Programming involves an automatic, on-chip bank erase
prior to reprogramming the bank. The FROM supports
asynchronous read with a nominal 10 ns access time. The
FROM can be read on byte boundaries. The top 3 bits of
the FROM address from the FPGA core define the bank
that is being accessed. The bottom 4 bits of the FROM
address from the FPGA core define which of the 16 bytes
in the bank is being accessed.
The FROM can only be programmed via the IEEE1532
JTAG port. It cannot be programmed directly from the
FPGA core. When programming, each of the 8 128-bit
banks can be selectively reprogrammed. The FROM can
only be reprogrammed on
a
bank boundary.
Byte Number in Bank
4 LSB of ADDR (READ)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
Figure 2-19 • FROM Architecture
Advanced v0.2
2-19
ProASIC3E Flash Family FPGAs
The ProASIC3E architecture enables the read side and
write side of RAMs to be organized independently,
allowing for bus conversion. For example, the write side
can be set to 256x18 and the read side to 512x9.
SRAM and FIFO
ProASIC3E devices have embedded SRAM blocks along
the north side of the device. To meet the needs of high
performance designs, the memory blocks operate strictly
in synchronous mode for both read and write
operations. The read and write clocks are completely
independent, and each may operate at any desired
frequency less than or equal to 350 MHz.
Both the write width and read width for the RAM blocks
can be specified independently with the WW (write
width) and RW (read width) pins. The different DxW
configurations are: 256x18, 512x9, 1kx4, 2kx2, and 4kx1.
Refer to the allowable RW and WW values supported for
each of the RAM macro types in Table 2-5 on page 2-23.
•
•
•
4kx1, 2kx2, 1kx4, 512x9 (dual-port RAM – two
read, two write or one read, one write)
When widths of one, two, and four are selected, the
ninth bit is unused. For example, when writing nine-bit
values and reading four-bit values, only the first four bits
and the second four bits of each nine-bit value are
addressable for read operations. The ninth bit is not
accessible.
512x9, 256x18 (two-port RAM – one read and one
write)
Sync write, sync pipelined, and nonpipelined read
The ProASIC3E memory block includes dedicated FIFO
control logic to generate internal addresses and external
flag logic (Full, Empty, AFULL, AEMPTY). Block diagrams
of the memory modules are illustrated in Figure 2-20 on
page 2-21.
Conversely, when writing four-bit values and reading
nine-bit values, the ninth bit of a read operation will be
undefined. The RAM blocks employ little-endian byte
order for read and write operations.
During RAM operation, addresses are sourced by the
user logic and the FIFO controller is ignored. In FIFO
mode, the internal addresses are generated by the FIFO
controller and routed to the RAM array by internal
MUXes. Refer to Figure 2-21 on page 2-22 for more
information about the implementation of the embedded
FIFO controller.
2-20
Advanced v0.2
ProASIC3E Flash Family FPGAs
RAM4K9
RAM512X18
FIFO4K18
RADDR8
RD17
RD16
ADDRA11 DOUTA8
RW2
RW1
RW0
WW2
WW1
WW0
ESTOP
FSTOP
RD17
RD16
RADDR7
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
DINA7
RADDR0
RD0
RD0
FULL
AFULL
EMPTY
RW1
RW0
DINA0
AEVAL11
AEVAL10
AEMPTY
WIDTHA1
WIDTHA0
PIPEA
PIPE
AEVAL0
WMODEA
BLKA
WENA
AFVAL11
AFVAL10
REN
RCLK
CLKA
AFVAL0
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
REN
RBLK
RCLK
ADDRB0
DOUTB0
WADDR0
WD17
WD16
WD17
WD16
DINB8
DINB7
WD0
DINB0
WD0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
WEN
WBLK
WCLK
RPIPE
WEN
WCLK
RESET
RESET
RESET
Figure 2-20 • Supported Basic RAM Macros
Advanced v0.2
2-21
ProASIC3E Flash Family FPGAs
RD
RD [17:0]
WD [17:0]
RCLK
WD
RCLK
WCLK
RADD [J:0]
WADD [J:0]
WCLK
RAM
REN
WEN
FREN
FWEN
CNT 16
E
WBLK
WEN
=
FULL
FSTOP
AFVAL
AFULL
V
AEMPTY
EMPTY
AEVAL
=
SUB 16
V=
CNT 16
E
RBLK
REN
ESTOP
Reset
Figure 2-21 • ProASIC3E RAM Block with Embedded FIFO Controller
2-22
Advanced v0.2
ProASIC3E Flash Family FPGAs
ADDRA and ADDRB
Signal Descriptions for RAM4K9
These are used as read or write addresses and are 12 bits
wide. When a depth of less than 4 k is specified, the
unused high-order bits must be grounded (Table 2-6).
The following signals are used to configure the RAM4K9
memory element:
WIDTHA and WIDTHB
Table 2-6 • Address Pins Used for Various Supported Bus
These signals enable the RAM to be configured in one of
four allowable aspect ratios (Table 2-5).
Widths
DxW
4kx1
2kx2
1kx4
512x9
ADDRA/ADDRB UNUSED
–
Table 2-5 • Allowable Aspect Ratio Settings for
WIDTHA[1:0]
WIDTHA1, WIDTHA0
WIDTHB1, WIDTHB0
DxW
4kx1
ADDRA[11], ADDRB[11]
ADDRA[11:10], ADDRB[11:10]
ADDRA[11:9], ADDRB[11:9]
00
01
10
11
00
01
10
11
2kx2
1kx4
DINA and DINB
512x9
These are the input data signals, and they are nine bits
wide. Not all nine bits are valid in all configurations.
When a data width less than nine is specified, unused
high-order signals must be grounded (Table 2-7).
BLKA and BLKB
These signals are active low and will enable the
respective ports when asserted. When a BLKx signal is
deasserted, that port’s outputs hold the previous value.
Table 2-7 • Data Pins Used for Various Supported Bus
Widths
WENA and WENB
DxW
4kx1
2kx2
1kx4
512x9
DINA/DINB UNUSED
DINA[8:1], DINB[8:1]
DINA[8:2], DINB[8:2]
DINA[8:4], DINB[8:4]
–
These signals switch the RAM between read and write
modes for the respective ports. A Low on these signals
indicates a write operation, and a High indicates a read.
CLKA and CLKB
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
PIPEA and PIPEB
DOUTA and DOUTB
These signals are used to specify pipelined read on the
output. A Low on PIPEA and/or PIPEB indicates a
nonpipelined read and the data appears on the
corresponding output in the same clock cycle. A High
indicates a pipelined read and data appears on the
corresponding output in the next clock cycle.
These are the output data signals, and they are nine bits
wide. Not all nine bits are valid in all configurations. As
with DINA and DINB, high-order bits become unusable.
The output data on unused pins is undefined.
Signal Descriptions for RAM512X18
RAM512X18 has slightly different behavior than the
RAM4K9, as it has dedicated read and write ports.
WMODEA and WMODEB
These signals are used to configure the behavior of the
output when RAM is in the write mode. A Low on these
signals makes the output retain data from the previous
read. A High indicates pass-through behavior where the
data being written will appear immediately on the
output. This signal gets overridden when RAM is being
read.
WW and RW
These signals enable the RAM to be configured in one of
the two allowable aspect ratios (Table 2-8).
Table 2-8 • Aspect Ratio Settings for WW[1:0]
WW1, WW0
RW1, RW0
DxW
512x9
RESET
01
01
10
This active low signal resets the output to zero when
asserted. It does not reset the content of the memory.
10
256x18
Reserved
00, 11
00, 11
Advanced v0.2
2-23
ProASIC3E Flash Family FPGAs
WD and RD
Modes of Operation
These are the input data and output signals, and they
are 18 bits wide. When a 512x9 aspect ratio is used for
write, WD[17:9] are unused and must be grounded. If
this aspect ratio is used for read, then RD[17:9] are
undefined.
There are two read modes and one write mode:
•
Read Nonpipelined (synchronous – one clock
edge): In the standard read mode, new data is
driven onto the RD bus in the clock cycle
immediately following RA and REN valid. The read
address is registered on the read port clock active
edge and data appears at RD after the RAM access
time. Setting PIPE to Off enables this mode.
WADDR and RADDR
These are read and write addresses, and they are nine
bits wide. When the 256x18 aspect ratio is used for write
or read, WADDR[8] or RADDR[8] is unused and must be
grounded.
•
Read Pipelined (synchronous – two clock edges):
The pipelined mode incurs an additional clock
delay from the address to the data but enables
operation at a much higher frequency. The read
address is registered on the read port active clock
edge, and the read data is registered and appears
at RD after the second read clock edge. Setting
the PIPE to ON enables this mode.
WCLK and RCLK
These signals are the write and read clocks, respectively.
They are both active high.
WEN and REN
These signals are the write and read enables,
respectively. They are both active low by default. These
signals can be configured as active high.
•
Write (synchronous – one clock edge): On the
write clock active edge, the write data is written
into the SRAM at the write address when WEN is
high. The setup times of the write address, write
enables, and write data are minimal with respect
to the write clock. Write and read transfers are
described with timing requirements in the "DDR
Module Specifications" section on page 3-55.
RESET
This active low signal resets the output to zero when
asserted. It does not reset the contents of the memory.
PIPE
This signal is used to specify pipelined read on the
output. A Low on PIPE indicates a nonpipelined read and
the data appears on the output in the same clock cycle. A
High indicates a pipelined read and data appears on the
output in the next clock cycle.
RAM Initialization
Each SRAM block can be individually initialized on
power-up by means of the JTAG port using the UJTAG
mechanism (refer to the "JTAG 1532" section on page 2-
51 and the ProASIC3/E SRAM/FIFO Blocks application
note). The shift register for a target block can be selected
and loaded with the proper bit configuration to enable
serial loading. The 4,608 bits of data can be loaded in a
single operation.
Clocking
The dual-port SRAM blocks are only clocked on the rising
edge. ACTgen allows falling-edge triggered clocks by
adding inverters to the netlist, hence achieving dual-port
SRAM blocks that are clocked on either edge (rising or
falling). For dual-port SRAM, each port can be clocked on
either edge and/or by separate clocks by port.
Signal Descriptions for FIFO4K18
ProASIC3E devices support inversion (bubble pushing)
throughout the FPGA architecture, including the clock
input to the SRAM modules. Inversions added to the
SRAM clock pin on the design schematic or in the HDL
code will be automatically accounted for during design
compile without incurring additional delay in the clock
path.
The following signals are used to configure the FIFO4K18
memory element:
WW and RW
These signals enable the FIFO to be configured in one of
the five allowable aspect ratios (Table 2-9).
Table 2-9 • Aspect Ratio Settings for WW[2:0]
The two-port SRAM can be clocked on the rising edge or
falling edge of the WCLK and RCLK.
WW2, WW1, WW0
RW2, RW1, RW0
DxW
4kx1
000
000
001
If negative-edge RAM and FIFO clocking is selected for
memory macros, clock edge inversion management
(bubble pushing) is automatically used within the
ProASIC3E development tools, without performance
penalty.
001
2kx2
010
010
1kx4
011
011
512x9
256x18
Reserved
100
100
101, 110, 111
101, 110, 111
2-24
Advanced v0.2
ProASIC3E Flash Family FPGAs
FSTOP is used to stop the FIFO write counter from further
counting once the FIFO is full (i.e., the Full flag goes
high). A High on this signal inhibits the counting.
WBLK and RBLK
These signals are active low and will enable the
respective ports when low. When the RBLK signal is high,
that port’s outputs hold the previous value.
For more information on these signals, refer to the
"ESTOP and FSTOP Usage" section.
WEN and REN
Read and write enables. WEN is active low and REN is
active high by default. These signals can be configured as
active high or low.
FULL, EMPTY
When the FIFO is full and no more data can be written,
the Full flag asserts high. The Full flag is synchronous to
WCLK to inhibit writing immediately upon detection of a
full condition and to prevent overflows. Since the write
address is compared to a resynchronized (and thus time-
delayed) version of the read address, the Full flag will
remain asserted until two WCLK active edges after a read
operation eliminates the full condition.
WCLK and RCLK
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
RPIPE
This signal is used to specify pipelined read on the
output. A Low on RPIPE indicates a nonpipelined read
and the data appears on the output in the same clock
cycle. A High indicates a pipelined read and data appears
on the output in the next clock cycle.
When the FIFO is empty and no more data can be read,
the Empty flag asserts high. The Empty flag is
synchronous to RCLK to inhibit reading immediately
upon detection of an empty condition and to prevent
underflows. Since the read address is compared to a
resynchronized (and thus time delayed) version of the
write address, the Empty flag will remain asserted until
two RCLK active edges after a write operation removes
the empty condition.
RESET
This active low signal resets the output to zero when
asserted. It resets the FIFO counters. It also sets all the RD
pins low, the Full and AFULL pins low, and the Empty and
AEMPTY pins high (Table 2-10).
For more information on these signals, refer to the "FIFO
Flags Usage Considerations" section on page 2-26.
WD
This is the input data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. When a data width
less than 18 is specified, unused higher-order signals
must be grounded (Table 2-10).
AFULL, AEMPTY
These are programmable flags and will be asserted on
the threshold specified by AFVAL and AEVAL,
respectively.
RD
When the number of words stored in the FIFO reaches
the amount specified by AEVAL while reading, the
AEMPTY output will go high. Likewise, when the number
of words stored in the FIFO reaches the amount specified
by AFVAL while writing, the AFULL output will go high.
This is the output data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. Like the WD bus, high-
order bits become unusable if the data width is less than
18. The output data on unused pins is undefined
(Table 2-10).
AFVAL, AEVAL
The AEVAL and AFVAL pins are used to specify the
almost-empty and almost-full threshold values,
respectively. They are 12-bit signals. For more
information on these signals, refer to the "FIFO Flags
Usage Considerations" section on page 2-26.
Table 2-10 • Input Data Signal Usage for Different Aspect
Ratios
DxW
4kx1
WD/RD Unused
WD[17:1], RD[17:1]
WD[17:2], RD[17:2]
WD[17:4], RD[17:4]
WD[17:9], RD[17:9]
–
ESTOP and FSTOP Usage
2kx2
The ESTOP pin is used to stop the read counter from
counting any further once the FIFO is empty (i.e., the
EMPTY flag goes high). Likewise, the FSTOP pin is used to
stop the write counter from counting any further once
the FIFO is full (i.e., the Full flag goes high).
1kx4
512x9
256x18
The FIFO counters in the ProASIC3E device start the count
from 0, reach the maximum depth for the configuration
(e.g., 511 for a 512x9 configuration), and then restart
from 0. An example application for the ESTOP, where the
read counter keeps counting, would be writing to the
FIFO once and reading the same content over and over,
without doing a write again.
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further
counting once the FIFO is empty (i.e., the Empty flag
goes high). A High on this signal inhibits the counting.
Advanced v0.2
2-25
ProASIC3E Flash Family FPGAs
is read, the FIFO is full and one word is read. The FULL
flag will remain asserted because a complete word
cannot be written at this point.
FIFO Flags Usage Considerations
The AEVAL and AFVAL pins are used to specify the
almost-empty and almost-full threshold values,
respectively. They are 12-bit signals. In order to handle
different read and write aspect ratios, the values
specified by the AEVAL and AFVAL pins are to be
interpreted as the address of the last word stored in the
FIFO. The FIFO actually contains separate write address
(WADDR) and read address (RADDR) counters. These
counters calculate the 12-bit memory address that is a
function of WW and RW, respectively. WADDR is
incremented every time a write operation is performed,
and RADDR is incremented every time a read operation is
performed. Whenever the difference between WADDR
and RADDR is greater than or equal to AFVAL, the AFULL
output is asserted. Likewise, whenever the difference
between WADDR and RADDR is less than or equal to
AEVAL, the AEMPTY output is asserted.
Refer to the ProASIC3/E SRAM/FIFO Blocks application
note for more information.
Pro I/Os
Introduction
ProASIC3E devices feature a flexible I/O structure,
supporting a range of mixed-voltages (1.5 V, 1.8 V, 2.5 V,
and 3.3 V) through a bank-selectable voltage. Table 2-11,
Table 2-12, Table 2-13, and Table 2-14 on page 2-29 show
the voltages and the compatible I/O standards. I/Os
provide programmable slew rates, drive strengths, weak
pull-up, and weak pull-down circuits. All I/O standards,
except 3.3 V PCI and 3.3 V PCI-X, are capable of hot
insertion. 3.3 V PCI and 3.3 V PCI-X are 5 V tolerant. See
the "5 V Input Tolerance" section on page 2-37 for
possible implementations of 5 V tolerance.
To handle different read and write aspect ratios, the
AFVAL and AEVAL are expressed in terms of total data
bits instead of total data words. When users specify the
AFVAL and AEVAL in terms of read or write words, the
ACTgen tool translates them into bit addresses and
configures these signals.
Single-ended input buffers support both the Schmitt-
trigger and programmable delay options on a per-I/O
basis.
ACTgen configures the Almost-Full flag, AFULL, to assert
when the write address exceeds the read address by a
predefined value. Assume the user has a 2kx8 FIFO, a
value of 1,500 for AFVAL means that the AFULL flag will
be asserted when a write causes the difference between
the write address and the read address to be 1,500. The
AEMPTY flag is asserted when the difference between
the write address and the read address is less than a
predefined value. In the example above, a value of 200
for AEVAL means that the AEMPTY flag will be asserted
when a read causes the difference between the write
address and the read address to drop to 200. Note that
the FIFO can be configured with different read and write
widths; in this case the AFVAL setting is based on the
number of write data entries and the AEVAL setting is
based on the number of read data entries.
All I/Os are in a known state during power-up and any
power-up sequence is allowed without current impact.
Refer to the "I/O Power-Up and Supply Voltage
Thresholds for Power-On Reset (Commercial and
Industrial)" section on page 3-3 for more information.
I/O Tile
The ProASIC3E I/O tile provides a flexible, programmable
structure for implementing a large number of I/O
standards. In addition, the registers available in the I/O
tile can be used to support high-performance register
inputs and outputs, with register enable if desired
(Figure 2-23 on page 2-32). The registers can also be used
to support the JESD-79C Double Data Rate (DDR)
standard within the I/O structure (see the "Double Data
Rate (DDR) Support" section on page 2-33 for more
information).
In the case of 512x9 and 256x18 aspect ratios, since only
4,096 bits can be addressed by 12 bits of the AFVAL/
AEVAL, the number of words must be multiplied by 8
As depicted from Figure 2-23 on page 2-32, all I/O
registers share one CLR port. The output register and
output enable register share one CLK port. Refer to the
"I/O Registers" section on page 2-32 for more
information.
and 16, instead of
9 and 18. The ACTgen tool
automatically uses the proper values.
To avoid half words being written or read, which could
happen if different read and write aspect ratios are
specified, the FIFO will assert Full or Empty as soon as at
least a minimum of one word cannot be written or read.
For example, if a two-bit word is written and a four-bit
word is being read, FIFO will remain in the empty state
when the first word is written. This occurs even if the
FIFO is not completely empty, because at this time a
single word cannot be read. The same is applicable in the
full state. If a four-bit word is written and a two-bit word
2-26
Advanced v0.2
ProASIC3E Flash Family FPGAs
Every I/O bank is divided into minibanks. Any user I/O in a
VREF minibank (a minibank is the region of scope of a
VREF pin) can be configured as a VREF pin (Figure 2-22).
Only one VREF pin is needed to control the entire VREF
minibank. The location and scope of the VREF minibanks
can be determined by the I/O name. For details, see the
"User I/O Naming Convention" section on page 2-48.
I/O Banks and I/O Standards Compatibility
I/Os are grouped into I/O voltage banks. There are eight I/O
banks (two per side). Each I/O voltage bank has dedicated
input/output supply and ground voltages (VMV/GNDQ
for input buffers and VCCI/GND for output buffers).
Because of these dedicated supplies, only I/Os with
compatible standards can be assigned to the same I/O
voltage bank. Table 2-12 on page 2-28 shows the
required voltage compatibility values for each of these
voltages.
Table 2-11 on page 2-28 shows the I/O standards
supported by the ProASIC3E devices and the
corresponding voltage levels.
I/O standards are compatible if:
For more information about I/O and global assignments
to I/O banks, refer to the specific pin table of the device
in the "Package Pin Assignments" section on page 4-1
and the "User I/O Naming Convention" section on
page 2-48.
•
•
Their VCCI and VMV values are identical
Both of the standards need a VREF, their VREF
values are identical
CCC/PLL
“B”
I/O
I/O
Common V
signal for all I/Os
in VREF minibanks
REF
Any I/O in a V
V
CCI
minibank canRbEFe used to
provide the reference
voltage to the common
VREF signal for that VREF
minibank.
GND
Power Triplet
V
CC
I/O
CCC/PLL
“C”
I/O
I/O
Up to five VREF
minibanks within
an I/O bank
I/O Pad
I/O
VCCI
JTAG
CCC/PLL
VREF signal scope is
between 8 and 18 I/Os.
GND
“D”
VCC
I/O
I/O
Figure 2-22 • Typical I/O Bank Detail Showing VREF Minibanks
Advanced v0.2
2-27
ProASIC3E Flash Family FPGAs
Table 2-11 • ProASIC3E Supported I/O Standards
A3PE600
A3PE1500
A3PE3000
Single-Ended
LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V,
LVCMOS2.5/5.0 V,
✓
✓
✓
3.3 V PCI / 3.3 V PCI-X
Differential
LVPECL and LVDS
Voltage-Referenced
✓
✓
✓
✓
✓
✓
GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class 1 and 2, SSTL2
Class 1 and 2, SSTL3 Class 1 and 2
Table 2-12 • VCCI Voltages and Compatible Standards
VCCI and VMV (typ.)
Compatible Standards
3.3 V
2.5 V
1.8 V
1.5 V
LVTTL/LVCMOS 3.3, PCI 3.3, SSTL3 (Class I and II), GTL+ 3.3, GTL 3.3, LVPECL
LVCMOS 2.5, LVCMOS 2.5/5.0, SSTL2 (Class I and II), GTL+ 2.5, GTL 2.5, LVDS
LVCMOS 1.8
LVCMOS 1.5, HSTL (Class I), HSTL (Class II)
Table 2-13 • VREF Voltages and Compatible Standards
REF (typ.)
V
Compatible Standards
SSTL3 (Class I and II)
SSTL2 (Class I and II)
GTL+ 2.5, GTL+ 3.3
1.5 V
1.25 V
1.0 V
0.8 V
0.75 V
GTL 2.5, GTL 3.3
HSTL (Class I), HSTL (Class II)
2-28
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 2-14 • Legal I/O Usage Matrix within the Same Bank
3.3 V
2.5 V
–
0.8 V
1 V
1.5 V
–
0.8 V
1 V
1.25 V
–
1.8 V
1.5 V
–
0.75 V
Note: White box: Allowable I/O standard combinations.
Gray box: Illegal I/O standard combinations.
Advanced v0.2
2-29
ProASIC3E Flash Family FPGAs
Features Supported on Every I/O
Table 2-15 lists all features supported by Transmitter/Receiver for single-ended and differential I/Os.
Table 2-15 • ProASIC3E I/O Features
Feature
Description
Single-Ended and Voltage-Referenced Transmitter Features
•
•
Hot insertion in every mode except PCI or 5-V-input-tolerant
(these modes use clamp diodes and do not allow hot insertion)
Activation of hot insertion (disabling the clamp diode) is
selectable by I/Os.
•
•
•
Weak pull-up and pull-down
Two slew rates
Skew between output buffer enable/disable time: 2 ns delay
(rising edge) and 0 ns delay (falling edge) (see "Selectable
Skew between Output Buffer Enable/Disable Time" on
page 2-41 for more information)
•
•
Five drive strengths
5 V tolerant receiver ("5 V Input Tolerance" section on
page 2-37)
•
LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs
("5 V Output Tolerance" section on page 2-40)
•
High Performance (Table 2-16 on page 2-31)
Single-Ended Receiver Features
•
•
•
ESD protection
Schmitt-trigger option
Programmable Delay: 0 ns if bypassed, 0.46 ns with 000
setting, 4.66 ns with 111 setting, 0.6 ns intermediate delay
increments (at 25°C, 1.5 V)
•
•
High performance (Table 2-16 on page 2-31)
Separate ground and power planes, GNDQ/VMV, for input
buffers only to avoid output-induced noise in the input circuitry.
Voltage-Referenced Differential Receiver Features
•
Programmable Delay: 0 ns if bypassed, 0.46 ns with 000
setting, 4.66 ns with 111 setting, 0.6 ns intermediate delay
increments (at 25°C, 1.5 V)
•
•
High performance (Table 2-16 on page 2-31)
Separate ground and power plane, GNDQ, and VMV pins for
input buffers only to avoid output-induced noise in the input
circuitry.
CMOS-Style LVDS or LVPECL Transmitter
LVDS/LVPECL Differential Receiver Features
•
•
Two I/Os and external resistors are used to provide a CMOS-
style LVDS or LVPECL transmitter solution.
Activation of hot insertion (disabling the clamp diode) is
selectable by I/Os.
•
•
Weak pull-up and pull-down
Fast slew rate
•
•
•
ESD protection
High performance (Table 2-16 on page 2-31)
Programmable Delay: 0 ns if bypassed, 0.46 ns with 000
setting, 4.66 ns with 111 setting, 0.6 ns intermediate delay
increments (at 25°C, 1.5 V)
•
Separate input buffer ground and power planes to avoid
output-induced noise in the input circuitry.
2-30
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 2-16 • Maximum I/O Frequency for Single-Ended, Voltage-Referenced, and Differential I/Os
Specification
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI
Performance up to
200 MHz
250 MHz
200 MHz
130 MHz
200 MHz
200 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
350 MHz
300 MHz
PCI-X
HSTL-I
HSTL-II
SSTL2-I
SSTL2-II
SSTL3-I
SSTL3-II
GTL+ 3.3 V
GTL+ 2.5 V
GTL 3.3 V
GTL 2.5 V
LVDS
LVPECL
Advanced v0.2
2-31
ProASIC3E Flash Family FPGAs
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to Figure 2-23 for a simplified
representation of the I/O block.
The number of input registers is selected by a set of switches (not shown in Figure 2-23) in between registers to
implement single or differential data transmission to and from the FPGA core. The Designer software sets these
switches for the user.
A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does
not have a CLR/PRE pin, as this register is used for DDR implementation.
1
2
IO/Q0
Input
Reg
Input
Reg
Y
Pull-Up/Down
Resistor Control
CLR/PRE
To FPGA Core
3
IO/Q1
Input
Reg
PAD
ICE
CLR/PRE
IO/ICLK
Signal Drive Strength
and Slew-Rate Control
E= Enable Pin
A
4
CLR/PRE
IO/D0
Output
Reg
OCE
ICE
From FPGA Core
CLR/PRE
5
IO/D1/ICE
Output
Reg
IO/OCLK
IO/OE
CLR/PRE
6
Output
Enable
Reg
OCE
IO/CLR or IO/PRE/OCE
CLR/PRE
Note: ProASIC3E I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-33).
Figure 2-23 • I/O Block Logical Representation
2-32
Advanced v0.2
ProASIC3E Flash Family FPGAs
Output Support for DDR
Double Data Rate (DDR) Support
The basic DDR output structure is shown in Figure 2-25
on page 2-34. New data is presented to the output every
half clock cycle. Note: DDR macros and I/O registers do
not require additional routing. The combiner
automatically recognizes the DDR macro and pushes its
registers to the I/O register area at the edge of the chip.
The routing delay from the I/O registers to the I/O buffers
is already taken into account in the DDR macro.
ProASIC3E devices support 350 MHz DDR inputs and
outputs. In DDR mode, new data is present on every
transition of the clock signal. Clock and data lines have
identical bandwidth and signal integrity requirements,
making it very efficient for implementing very high-
speed systems.
DDR interfaces can be implemented using HSTL, SSTL,
LVDS, and LVPECL I/O standards.
Refer to the Actel application note, Using DDR for
ProASIC3/E Devices for more information.
Input Support for DDR
The basic structure to support a DDR input is shown in
Figure 2-24. Three input registers are used to capture
incoming data, which is presented to the core on each
rising edge of the I/O register clock.
Each I/O tile on ProASIC3E devices supports DDR inputs.
Input DDR
INBUF
A
D
Out_QF
(To Core)
Data
XX
X
X
FF1
E
B
Out_QR
(To Core)
CLK
CLR
X
CLKBUF
INBUF
FF2
C
X
DDR_IN
Figure 2-24 • DDR Input Register Support in ProASIC3E Devices
Advanced v0.2
2-33
ProASIC3E Flash Family FPGAs
A
Data_F
XX
(From Core)
FF1
FF2
Out
B
C
0
1
CLK
X
X
X
E
CLKBUF
X
OUTBUF
D
Data_R
(From Core)
B
C
X
X
CLR
INBUF
DDR_OUT
Figure 2-25 • DDR Output Support for ProASIC3E Devices
2-34
Advanced v0.2
ProASIC3E Flash Family FPGAs
Hot-Swap Support
Hot swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a
powered-up system. The levels of hot-swap support and examples of related applications are described in Table 2-17.
The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required.
Table 2-17 • Levels of Hot-Swap Support
Power
Applied
Device
Circuitry
Example of
Application with
Compliance
of
Hot
Swapping
Level
to
Card Ground Connected Cards that Contain ProASIC3E
Connection to Bus Pins ProASIC3E Devices Devices
Description Device
Bus State
1
2
3
Cold swap
No
Yes
Yes
–
–
–
System and card is Compliant
powered down, and
then the card gets
plugged
system.
into
Then,
the
the
power supplies are
turned on.
Hot swap
while reset
Held in reset Must be made
–
In
PCI
hot-plug Compliant
reset
state
and maintained
for 1 ms before,
specification,
control circuitry isolates
the card busses until
the card supplies are at
their nominal operating
levels and stable.
during,
and
after insertion/
removal
Hot swap
while bus idle
Held idle (no Same as Level 2 Must remain Board bus shared with Compliant
ongoing I/O glitch-free card bus is "frozen", with cards
processes during
insertion/removal
during power and there is no toggling with two levels
up or power activity on the bus, and of staging
down
it is critical that the
logic states set on the
bus signal do not get
disturbed during card
insertion/removal.
4
Hot swap on
an active bus
Yes
Bus may have Same as Level 2 Same as Level There is activity on the Compliant
active I/O processes system bus, and it is with cards
3
ongoing,
device
inserted
but
being
or
critical that the logic with two levels
states set on the bus of staging
signal do not get
removed must be
idle.
disturbed during card
insertion/removal.
For ProASIC3E devices requiring level 3 and/or level 4
compliance, the board drivers connected to ProASIC3E
I/Os need to have 10 kΩ (or lower) output drive
resistance at hot insertion, and 1 kΩ (or lower) output
drive resistance at hot removal. If that cannot be assured,
three levels of staging can be used to meet level 3 and/or
level 4 compliance. Cards with two levels of staging
should have the following sequence:
For boards and cards with three levels of staging, it is
assumed that card power supplies have time to reach
their final value before the I/Os are connected. Pay
attention to the sizing of power supply decoupling
capacitors on the card to ensure that the power supplies
are not overloaded with capacitance.
Cards with three levels of staging should have the
following sequence:
•
•
Grounds
•
•
•
Grounds
Powers, I/Os, other pins
Powers
I/Os and other pins
Advanced v0.2
2-35
ProASIC3E Flash Family FPGAs
connected to GND, and its N side connected to pad.
During operation, these diodes are normally biased in
the off state, except when transient voltage is
significantly above VCCI or below GND levels.
Electro-Static Discharge (ESD) Protection
ProASIC3E devices are tested per JEDEC Standard
JESD22-A114-B.
ProASIC3E devices contain clamp diodes at every I/O,
global, and power pad. Clamp diodes protect all device
pads against damage from ESD as well as from excessive
voltage transients.
By selecting the appropriate I/O configuration, the diode
is turned on or off. Refer to Table 2-18 for more
information about the I/O standards and the clamp
diode.
Each I/O has two clamp diodes. One diode has its
positive (P) side connected to pad, and its negative (N)
side connected to VCCI. The second diode has its P side
The second diode is always connected to the pad,
regardless of the I/O configuration selected.
Table 2-18 • I/O Hot-Swap and 5 V Input Tolerance Capabilities
5 V Input
I/O Assignment
3.3 V LVTTL/LVCMOS
3.3 V PCI, 3.3 V PCI-X
LVCMOS 2.5 V
Clamp Diode
Hot Insertion
Tolerance
Yes1
Yes1
No
Input Buffer
Output Buffer
No
Yes
No
Yes
No
No
No
No
Yes
No
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Yes
No
LVCMOS 2.5 V / 5.0 V
LVCMOS 1.8 V
Yes2
Yes
Yes
Yes
Yes
No
LVCMOS 1. 5 V
No
Voltage-Referenced Input Buffer
Differential, LVDS/LVPECL3
Notes:
No
No
1. Can be implemented with an external IDT bus switch, resistor divider, or zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. Bidirectional LVDS or LVPECL buffers are not supported. I/Os can either be configured as input buffers or output buffers.
2-36
Advanced v0.2
ProASIC3E Flash Family FPGAs
Rtx_out_high = Rtx_out_low = 10 Ω
5 V Input Tolerance
R1 = 36 Ω (+/-5%), P(r1)min = 0.069 Ω
I/Os can support 5 V input tolerance when LVTTL 3.3 V,
LVCMOS 3.3 V, LVCMOS 2.5 V / 5 V and LVCMOS 2.5 V
configurations are used (see Table 2-19 on page 2-40 for
more details). There are four recommended solutions
(see Figure 2-26 to Figure 2-29 on page 2-40 for details of
board and macro setups) to achieve 5 V receiver
tolerance. All the solutions meet a common requirement
of limiting the voltage at the I/O input to 3.6 V or less. In
fact, the I/O absolute maximum voltage rating is 3.6 V,
and any voltage above 3.6 V may cause long term gate
oxide failures.
R2 = 82 Ω (+/-5%), P(r2)min = 0.158 Ω
Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 +10) = 45.04 mA
t
RISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up
to 25% safety margin)
RISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to
t
25% safety margin)
Example 2: (low-medium speed, medium current)
Rtx_out_high = Rtx_out_low = 10 Ω
R1 = 220 Ω (+/-5%), P(r1)min = 0.018 Ω
R2 = 390 Ω (+/-5%), P(r2)min = 0.032 Ω
Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 +10) = 9.17 mA
Solution 1
The board-level needs to ensure that the reflected
waveform at the pad does not exceed limits provided in
Table 3-2 on page 3-2. This is a long term reliability
requirement.
t
RISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to
25% safety margin)
RISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to
This scheme will also work for a 3.3 V PCI / PCI-X
configuration, but the internal diode should not be used for
clamping, and the voltage must be limited by the two
external resistors as explained below. Relying on the
diode clamping would create an excessive pad DC
voltage of 3.3 V + 0.7 V = 4 V.
t
25% safety margin)
Other values of resistors are also allowed as long as the
resistors are sized appropriately to limit the voltage at
the receiving end to 2.5 V < Vin(rx) < 3.6 V* when the
transmitter sends a logic '1'. This range of Vin_dc(rx) has
to be ensured for any combination of transmitter supply
(5 V +/- 0.5 V), transmitter output resistance, and board
resistor tolerances.
Examples of possible resistor values (based on
simplified simulation model with no line effects, and
10 Ω transmitter output resistance, where
a
Rtx_out_high = (VCCI - VOH)/ IOH, Rtx_out_low = VOL / IOL).
Temporary overshoots are allowed according to Table 3-2
on page 3-2.
Example 1: (high speed, high current)
Solution 1
ProASIC3E I/O Input
3.3 V
5.5 V
Rext1
Rext2
Requires two board resistors,
LVCMOS 3.3 V I/Os.
Figure 2-26 • Solution 1
Advanced v0.2
2-37
ProASIC3E Flash Family FPGAs
Solution 2
The board-level design needs to ensure that the reflected waveform at the pad does not exceed limits provided in
Table 3-2 on page 3-2. This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping,
and the voltage must be limited by the external resistors and zener, as shown in Figure 2-27. Relying on the diode
clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 2
ProASIC3E I/O Input
3.3 V
5.5 V
Rext1
Zener
3.3 V
Requires one board resistor, one
Zener 3.3 V diode, LVCMOS 3.3 V I/Os.
Figure 2-27 • Solution 2 ProASIC3E
2-38
Advanced v0.2
ProASIC3E Flash Family FPGAs
Solution 3
The board-level design needs to ensure that the reflected waveform at the pad does not exceed limits provided in
Table 3-2 on page 3-2. This is a long-term reliability requirement.
This scheme will also work for 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping,
and the voltage must be limited by the bus switch, as shown in Figure 2-28. Relying on the diode clamping would
create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 3
ProASIC3E I/O Input
3.3 V
Bus
Switch
IDTQS32X23
5.5 V
5.5 V
Requires a bus switch on the board,
LVTTL 3.3 V I/Os.
Figure 2-28 • Solution 3
Advanced v0.2
2-39
ProASIC3E Flash Family FPGAs
Solution 4
Solution 4
ProASIC3E I/O Input
2.5 V
2.5 V
5.5 V
On-chip
Clamp
Diode
Rext
Requires one board resistor.
Available for LVCMOS 2.5 V/5.0 V.
Figure 2-29 • Solution 4 ProASIC3E
Table 2-19 • Comparison Table for 5 V Compliant Receiver Scheme
Solution
Board Components
Two resistors
Speed
Low to High1
Medium
High
Current Limitations
1
2
3
4
Limited by transmitter's drive strength
Limited by transmitter's drive strength
N/A
Resistor and Zener 3.3 V
Bus switch
Resistor2
Low
Diode current
R = 250 Ω at TJ = 70°C
R = 500 Ω at TJ = 85°C
R = 1000 Ω at TJ = 100°C
12 mA at TJ = 70°C
6 mA at TJ = 85°C
3 mA at TJ = 100°C
Notes:
1. Speed and current consumption increase as the board resistance values decrease.
2. Resistor values ensure I/O diode long term reliability.
5 V Output Tolerance
ProASIC3E I/Os must be set to 3.3 V LVTTL or 3.3 V
LVCMOS mode to reliably drive 5 V TTL receivers. It is also
critical that there be NO external I/O pull-up resistor to
5 V, since this resistor would pull the I/O pad voltage
beyond the 3.6 V absolute maximum value, and
consequently cause damage to the I/O.
When set to 3.3 V LVTTL or 3.3 V LVCMOS mode,
ProASIC3E I/Os can directly drive signals into 5 V TTL
receivers. In fact, VOL = 0.4 V and VOH = 2.4 V voltages on
both 3.3 V LVTTL and 3.3 V LVCMOS modes exceed the
VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL
receivers. Therefore, level '1' and level '0' will be
recognized correctly by 5 V TTL receivers.
2-40
Advanced v0.2
ProASIC3E Flash Family FPGAs
Selectable Skew between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion
(disable) time.
ENABLE (IN)
Output Enable
(from FPGA core)
ENABLE (OUT)
MUX
Skew Circuit
I/O Output
Buffers
Skew Select
Figure 2-30 • Block Diagram of Output Enable Path
ENABLE (IN)
ENABLE (OUT)
Less than
0.1 ns
Less than
0.1 ns
Figure 2-31 • Timing Diagram (Option1: Bypasses Skew Circuit)
ENABLE (IN)
ENABLE (OUT)
1.2 ns
(typ)
Less than
0.1 ns
Figure 2-32 • Timing Diagram (Option 2: With Skew Circuit Selected)
Advanced v0.2
2-41
ProASIC3E Flash Family FPGAs
On a system level, the skew circuit can be used in
current shorts. Figure 2-33 presents an example of the
skew circuit implementation in bidirectional
applications
where
transmission
activities
on
a
bidirectional data lines need to be coordinated. This
circuit, when selected, provides a timing margin that can
prevent bus contention and subsequent data loss and/or
transmitter over-stress due to transmitter-to-transmitter
communication system. Figure 2-34 shows how a bus
contention is created, Figure 2-35 on page 2-43 shows
how it can be avoided with the skew circuit.
Transmitter
ENABLE/
DISABLE
Transmitter 1: ProASIC3E I/O
Transmitter 2: Generic I/O
Routing
Skew or
Routing
Delay (t)
EN(b1)
EN(b2)
EN(r1)
ENABLE(t2)
Bypass
Skew
Delay (t2)
ENABLE(t1)
Bidirectional Data Bus
Figure 2-33 • Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using ProASIC3E Devices
EN (b1)
EN (b2)
ENABLE (r1)
ENABLE (t1)
Transmitter 1: OFF
ENABLE (t2)
Transmitter 1: OFF
Transmitter 1: ON
Transmitter 2: ON
Transmitter 2: OFF
Bus
Contention
Figure 2-34 • Timing Diagram (Bypasses Skew Circuit)
2-42
Advanced v0.2
ProASIC3E Flash Family FPGAs
EN (b1)
EN (b2)
ENABLE (t1)
Transmitter 1: OFF
ENABLE (t2)
Transmitter 1: OFF
Transmitter 1: ON
Transmitter 2: ON
Transmitter 2: OFF
Result: No Bus Contention
Figure 2-35 • Timing Diagram (with Skew Circuit Selected)
Advanced v0.2
2-43
ProASIC3E Flash Family FPGAs
I/O Software Support
In the ProASIC3E development software, default settings have been defined for the various I/O standards that are
supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are
applicable for all I/O standards. Table 2-20 lists the valid I/O attributes that can be manipulated by the user for each I/O
standard.
Single-ended I/O standards in ProASIC3E support up to five different drive strengths.
Table 2-20 • I/O Attributes vs. I/O Standard Applications
I/O Standards
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
PCI-X (3.3 V)
GTL+ (3.3 V)
GTL+ (2.5 V)
GTL (3.3 V)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
GTL (2.5 V)
HSTL Class I
HSTL Class II
SSTL2 Class I & II
SSTL3 Class I & II
LVDS
LVPECL
2-44
Advanced v0.2
ProASIC3E Flash Family FPGAs
The output slew rate and multiple drive strength
controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS
2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V and
LVCMOS 1.5 V. All other I/O standards have a high output
slew rate by default.
Weak Pull-Up and Weak Pull-Down Resistors
ProASIC3E devices support optional weak pull-up and
pull-down resistors per I/O pin. When the I/O is pulled up,
it is connected to the VCCI of its corresponding I/O bank.
When it is pulled-down it is connected to GND. Refer to
Table 3-20 on page 3-20 for more information.
Refer to Table 2-21 for more information about the slew
rate and drive strength specification. Table 2-23 on
page 2-47 lists the default values for the above
selectable I/O attributes as well as those that are preset
for that I/O standard.
Slew Rate Control and Drive Strength
ProASIC3E devices support output slew rate control: high
and low. The high slew rate option is recommended to
minimize the propagation delay. This high-speed option
may introduce noise into the system if appropriate signal
integrity measures are not adopted. Selecting a low slew
rate reduces this kind of noise but adds some delays in
the system. A low slew rate is recommended when bus
transients are expected. Drive strength should also be
selected according to the design requirements and noise
immunity of the system.
Refer to Table 2-21 for SLEW and OUT_DRIVE settings.
Table 2-22 on page 2-46 lists the I/O default attributes.
Table 2-23 on page 2-47 lists the voltages for the
supported I/O standards.
Table 2-21 • I/O Standards—SLEW and OUT_DRIVE Settings
OUT_DRIVE (mA)
I/O Standards
LVTTL/LVCMOS33
LVCMOS25
2
✓
✓
✓
✓
✓
4
✓
✓
✓
✓
✓
6
✓
✓
✓
✓
✓
8
✓
✓
✓
✓
✓
12
✓
16
✓
✓
✓
✓
–
24
✓
✓
✓
–
Slew
High
High
High
High
High
Low
Low
Low
Low
Low
✓
LVCMOS25_50
LVCMOS18
✓
✓
LVCMOS15
✓
–
Advanced v0.2
2-45
ProASIC3E Flash Family FPGAs
Table 2-22 • I/O Default Attributes
I/O Standards
LVTTL/LVCMOS
3.3 V
See Table 2-21 See Table 2-21
on page 2-45 on page 2-45
Off
None
35pF
–
Off
0
Off
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
35 pF
35 pF
35 pF
35 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
20 pF
20 pF
30 pF
30 pF
0 pF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
PCI-X (3.3 V)
GTL+ (3.3 V)
GTL+ (2.5 V)
GTL (3.3 V)
GTL (2.5 V)
HSTL Class I
HSTL Class II
SSTL2 Class I & II
SSTL3 Class I & II
LVDS
LVPECL
0 pF
2-46
Advanced v0.2
ProASIC3E Flash Family FPGAs
Board Termination Voltage
Table 2-23 • Supported I/O Standards and the Corresponding VREF and VTT Voltages
Input/Output Supply
Input Reference Voltage
I/O Standard
Voltage (VMVtyp/VCCI_TYP
)
(VREF_TYP
)
(VTT_TYP)
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
3.3 V
2.5 V
2.5 V
–
–
–
–
–
–
LVCMOS 2.5 V / 5.0 V
Input
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI 3.3 V
1.8 V
1.5 V
3.3 V
3.3 V
3.3 V
2.5 V
3.3 V
2.5 V
1.5 V
1.5 V
3.3 V
3.3 V
2.5 V
2.5 V
2.5 V
3.3 V
–
–
–
–
–
–
PCI-X 3.3 V
GTL+ 3.3 V
GTL+ 2.5 V
GTL 3.3 V
–
–
1.0 V
1.0 V
0.80 V
0.80 V
0.75 V
0.75 V
1.5 V
1.5 V
1.25 V
1.25 V
–
1.5 V
1.5 V
1.2 V
1.2 V
0.75 V
0.75 V
1.5 V
1.5 V
1.25 V
1.25 V
–
GTL 2.5 V
HSTL CLASS I
HSTL CLASS II
SSTL3 CLASS I
SSTL3 CLASS II
SSTL2 CLASS I
SSTL2 CLASS II
LVDS
LVPECL
–
–
Advanced v0.2
2-47
ProASIC3E Flash Family FPGAs
User I/O Naming Convention
Due to the comprehensive and flexible nature of the ProASIC3E device user I/Os, a naming scheme is used to show the
details of the I/O (Figure 2-36). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity
for differential I/Os.
I/O Nomenclature = Gmn/IOuxwByVz
Gmn is only used for I/Os that also have CCC access – i.e., global pins.
G
Global
=
m
= Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east
middle), D (southeast corner), E (southwest corner), and F (west middle).
n
= Global input MUX and pin number of the associated Global location m, either A0, A1,A2, B0, B1, B2, C0, C1, or
C2. Figure 2-14 on page 2-15 shows the three input pins per each clock source MUX at the CCC location m.
= I/O pair number in the bank, starting at 00 from the northwest I/O bank in a clockwise direction.
= P (Positive) or N (Negative) for differential pairs, or S (Single-Ended) for the I/O that support single-ended and
voltage-referenced I/O standards only
u
x
w
= D (Differential Pair) or P (Pair) or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded
out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are
bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out.
For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal
adjacency does not meet the requirements for a true differential pair.
B
y
V
z
= Bank
= Bank number [0..7]. Bank number starting at 0 from the northwest I/O bank in a clockwise direction.
= VREF
= VREF minibank number [0...4]. A given voltage-referenced signal spans 16 pins (typically) in an I/O bank.
Voltage banks may have multiple VREF minibanks.
VCCPLB
VCOMPLB
VCOMPLA
VCCPLA
CCC/ PLL
“A”
CCC/ PLL
“B”
Bank 0
Bank 1
GNDQ
VMV2
GNDQ
VMV7
VCCI B7
GND
VCC
VCC
GND
VCCI B2
A3PE600
A3PE1500
VCC
VCOMPLF
VCCPLF
VCC
CCC/ PLL
“F”
CCC/ PLL
“C”
VCOMPLC
VCCPLC
A3PE3000
VCC
VCC
GND
VCCI B6
VCCI B3
GND
VMV3
VJTAG
VMV6
TRST
JTAG
CCC/ PLL
“D”
GNDQ
VCOMPLE
VCCPLE
TDO
GNDQ
Bank 5
Bank 4
CCC/ PLL
“E”
VPUMP
VCOMPLD
VCCPLD
Figure 2-36 • User I/O Naming Conventions of ProASIC3E Devices
2-48
Advanced v0.2
ProASIC3E Flash Family FPGAs
V
PLL Ground
COMPLA/B/C/D/E/F
Pin Descriptions
Ground to analog PLL. There are up to six VCOMPL pins
(PLL ground) on ProASIC3E. Unused VCOMPL pins should
be connected to GND.
Supply Pins
V
JTAG Supply Voltage
GND
Ground
JTAG
ProASIC3E devices have
a separate bank for the
Ground supply voltage to the core, I/O outputs, and I/O
logic.
dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG
power supply in a separate I/O bank gives greater
flexibility with supply selection and simplifies power
supply and printed circuit board design.
GNDQ
Ground (Quiet)
Quiet ground supply voltage to input buffers of I/O
banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise
originated from the output buffer ground domain. This
minimizes the noise transfer within the package, and
improves input signal integrity. GNDQ needs to always
be connected on the board to GND.
V
Programming Supply Voltage
PUMP
ProASIC3E
devices
support
single-voltage
ISP
programming of the configuration Flash and FROM. For
programming, VPUMP should be 3.3 V nominal. During
normal device operation VPUMP can be left floating or
can be tied (pulled up) to any voltage between 0 V and
3.6 V.
V
Core Supply Voltage
CC
Supply voltage to the FPGA core, nominal 1.5 V.
V
Bx
I/O Supply Voltage
CCI
User-Defined Supply Pins
Supply voltage to the bank's I/O output buffers and I/O
logic. Bx is the I/O bank number. There are eight I/O
banks on ProASIC3E devices plus a dedicated VJTAG bank.
Each bank can have a separate VCCI connection. All I/Os
in a bank will run off the same VCCIBx supply. VCCI can be
1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O
banks should have their corresponding VCCI pins tied to
GND.
V
I/O Voltage Reference
REF
Reference voltage for I/O minibanks. VREF pins are
configured by the user from regular I/Os, and any I/O in a
bank, except JTAG I/Os, which can be designated as the
voltage reference I/O. Only certain I/O standards require
a voltage reference – HSTL (I) and (II), SSTL2 (I) and (II),
SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support
the number of I/Os available in its minibank.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O
bank. X is the bank number. Within the package, the
VMV plane is decoupled from the simultaneous
switching noise originated from the output buffer VCCI
domain. This minimizes the noise transfer within the
package, and improves input signal integrity. Each bank
must have at least one VMV connection. All I/Os in a
bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of
each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V
nominal voltage. Unused I/O banks should have their
corresponding VMV pins tied to GND. VMV and VCCI
should be at the same voltage within a given I/O bank.
Used VMV pins must be connected to the corresponding
VCCI pins of the same bank (i.e. VMV0 to VCCIB0, VMV1 to
VCCIB1, etc.).
Global Pins
GL
Globals
GL I/Os have access to certain clock conditioning circuitry
(and the PLL) and/or have direct access to the global
network (spines). Additionally, the global I/Os can be
used as Pro I/Os, since they have identical capabilities.
Refer to the "User I/O Naming Convention" section on
page 2-48 for a description of naming of global pins.
JTAG Pins
TCK
Test Clock
Test clock input for the JTAG boundary-scan, ISP, and
UJTAG usage. Per the (JTAG) IEEE1532 specification, it is
recommended that TCK be tied to GND or VJTAG when
not used. This prevents a possible totem-pole current on
the input buffer stage. The TCK pin does not have an
internal weak pull-up resistor.
V
PLL Supply Voltage
CCPLA/B/C/D/E/F
Supply voltage to analog PLL. There are up to six VCCPL
pins (PLL power) on ProASIC3E devices. Unused VCCPLX
pins should be connected to VCOMPLX
.
Advanced v0.2
2-49
ProASIC3E Flash Family FPGAs
TDI
Test data Input
Physical Synthesis from Magma Design Automation™,
and Designer software from Actel.
Serial input for JTAG boundary-scan, ISP, and UJTAG
usage. There is an internal weak pull-up resistor on the
TDI pin.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of back-end support
tools for FPGA development. The Designer software
includes the following:
TDO
Test Data Output
Serial output for JTAG boundary-scan, ISP, and UJTAG
usage. The TDO pin does not have an internal weak pull-
up resistor.
•
Timer – a world-class integrated static timing
analyzer and constraints editor that supports
timing-driven place-and-route
TMS
Test Mode Select
•
•
NetlistViewer – a design netlist schematic viewer
ChipPlanner – a graphical floorplanner viewer and
editor
The TMS pin controls the use of the IEEE1532 boundary
scan pins (TCK,TDI, TDO, TRST). There is an internal weak
pull-up resistor on the TMS pin.
•
SmartPower – tool which enables the designer to
quickly estimate the power consumption of a
design
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active low input to
asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the
TRST pin. In the operating mode, a 100 Ω external pull-
down resistor should be placed between TRST and GND
to ensure that the chip does not switch into a different
mode.
•
•
PinEditor – a graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor – tool which displays all
assigned and unassigned I/O macros and their
attributes in a spreadsheet format
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel back-annotation
flow is compatible with all the major simulators. Another
tool included in the Designer software is the ACTgen
core generator, which easily creates popular and
commonly used logic functions for implementation into
your schematic or HDL design.
Special Function Pins
NC
No connect
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
Actel Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Mentor Graphics, Synplicity,
Synopsys, and Cadence®. The Designer software is
available for both the Windows® and UNIX operating
systems.
DC
Don't connect
This pin should not be connected to any signals on the
printed circuit board (PCB). These pins should be left un-
connected.
Software Tools
Programming
Programming can be performed using various
programming tools, such as Silicon Sculptor II (BP Micro
Systems) or FlashPro3 (Actel).
Overview of Tools Flow
The ProASIC3E family of FPGAs is fully supported by both
Actel Libero IDE and Designer FPGA Development
software. Actel Libero IDE is an integrated design
manager that seamlessly integrates design tools while
guiding the user through the design flow, managing all
design and log files, and passing necessary design data
among tools. Additionally, Libero IDE allows users to
integrate both schematic and HDL synthesis into a single
flow and verify the entire design in a single environment
(see the Libero IDE flow diagram located on the Actel
website). Libero IDE includes Synplify® AE from
Synplicity®, ViewDraw® AE from Mentor Graphics®,
ModelSim® HDL Simulator from Mentor Graphics,
WaveFormer Lite™ AE from SynaptiCAD®, PALACE™
The user can generate *.stp programming files from the
Designer software and can use these files to program a
device.
ProASIC3E devices can be programmed in system. For
more information on ISP of ProASIC3E devices, refer to
the In-System Programming (ISP) in ProASIC3/E Using
FlashPro3 and Programming a ProASIC3/E Using a
Microprocessor application notes.
2-50
Advanced v0.2
ProASIC3E Flash Family FPGAs
JTAG 1532
Security
ProASIC3E devices have a built-in 128-bit AES decryption
core. The decryption core facilitates secure, in-system
programming of the FPGA core array fabric and the
FROM. The FROM and the FPGA core fabric can be
programmed independently from each other, allowing
the FROM to be updated without the need for change to
the FPGA core fabric. The AES master key is stored in on-
chip nonvolatile memory (Flash). The AES master key can
be preloaded into parts in a secure programming
environment (such as the Actel in-house programming
center) and then "blank" parts can be shipped to an
untrusted programming or manufacturing center for
final personalization with an AES encrypted bitstream.
Late stage product changes or personalization can be
implemented easily and securely by simply sending a
STAPL file with AES encrypted data. Secure remote field
updates over public networks (such as the Internet) are
possible by sending and programming a STAPL file with
AES encrypted data.
Programming
ProASIC3E devices support the JTAG-based IEEE1532
standard for ISP. As part of this support, when a ProASIC3E
device is in an unprogrammed state, all user I/O pins are
disabled. This is achieved by keeping the global IO_EN
signal deactivated, which also has the effect of disabling
the input buffers. Consequently, the SAMPLE instruction
will have no effect while the ProASIC3E device is in this
unprogrammed state. This is different behavior from that
observed in the ProASICPLUS device family. This lack of
effect is necessitated by the fact that SAMPLE is defined in
the IEEE1532 specification as a noninvasive instruction. If
the input buffers were to be enabled by SAMPLE
temporarily turning on the I/Os, then it would not truly be
a noninvasive instruction, hence the lack of effect when
the ProASIC3E device is in this unprogrammed state. Refer
to the standard or the In-System Programming (ISP) in
ProASIC3/E Using FlashPro3 application note for more
details.
128-Bit AES Decryption
Boundary Scan
The 128-bit AES standard (FIPS-192) block cipher is the
NIST (National Institute of Standards and Technology)
replacement for the DES (Data Encryption Standard
FIPS46-2). AES has been designed to protect sensitive
government information well into the 21st century. It
will replace the aging DES, which NIST adopted in 1977
as a Federal Information Processing Standard used by
federal agencies to protect sensitive, unclassified
information. The 128-bit AES standard has 3.4x1038
possible 128-bit key variants, and it has been estimated
that it would take 1,000 trillion years to crack 128-bit
AES cipher text using exhaustive techniques. Keys are
stored (securely) in ProASIC3E devices in nonvolatile
Flash memory. All programming files sent to the device
can be authenticated by the part prior to programming
to ensure that bad programming data is not loaded into
the part that may possibly damage it. All programming
verification is performed on-chip, ensuring that the
contents of ProASIC3E devices remain secure.
ProASIC3E devices are compatible with IEEE Standard
1149.1, which defines a hardware architecture and the
set of mechanisms for boundary-scan testing. The basic
ProASIC3E boundary-scan logic circuit is composed of the
TAP (test access port) controller, test data registers, and
instruction register (Figure 2-37 on page 2-52). This
circuit supports all mandatory IEEE 1149.1 instructions
(EXTEST, SAMPLE/PRELOAD, and BYPASS) and the
optional IDCODE instruction (Table 2-24 on page 2-52).
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI, and TDO
(test data input and output), TMS (test mode selector),
and TRST (test reset input). TMS, TDI, and TRST are
equipped with pull-up resistors to ensure proper
operation when no input data is supplied to them. These
pins are dedicated for boundary-scan test usage. Actel
recommends that a nominal 20 kΩ pull-up resistor be
added to TDO and TCK pins. The TAP controller is a 4-bit
state machine (16 states) that operates as shown in
Figure 2-37 on page 2-52. The 1s and 0s represent the
values that must be present at TMS at a rising edge of
TCK for the given state transition to occur. IR and DR
indicate that the instruction register or the data register
is operating in that state.
AES decryption can also be used on the 1,024-bit FROM
to allow for secure remote updates of the FROM
contents. This allows for easy, secure support for
subscription model products. See the application note,
ProASIC3/E Security, for more details.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles. The TRST pin
may also be used to asynchronously place the TAP
controller in the Test-Logic-Reset state.
ISP
ProASIC3E devices support IEEE1532 ISP via JTAG and
require
a single VPUMP voltage of 3.3 V during
programming. In addition, programming via
a
Microcontroller (MCU) in a target system can be
achieved. See the application note In-System
Programming (ISP) in ProASIC3/E Using FlashPro3 for
more details.
Advanced v0.2
2-51
ProASIC3E Flash Family FPGAs
ProASIC3E devices support three types of test data
registers: bypass, device identification, and boundary
scan. The bypass register is selected when no other
register needs to be accessed in a device. This speeds up
test data transfer to other devices in a test data path.
The 32-bit device identification register is a shift register
with four fields (lowest significant byte (LSB), ID number,
part number, and version). The boundary-scan register
observes and controls the state of each I/O pin. Each I/O
cell has three boundary-scan register cells, each with a
serial-in, serial-out, parallel-in, and parallel-out pin.
The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary-
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic I/O tile and the input, output, and
control ports of an I/O buffer to capture and load data
into the register to control or observe the logic state of
each I/O.
I/O
I/O
I/O
I/O
I/O
Test Data
Registers
Bypass Register
Instruction
Register
TAP
Controller
Device
Logic
I/O
I/O
I/O
I/O
I/O
Figure 2-37 • Boundary-Scan Chain in ProASIC3E
Table 2-24 • Boundary-Scan Opcodes
Hex Opcode
EXTEST
00
07
0E
01
0F
05
FF
HIGHZ
USERCODE
SAMPLE/PRELOAD
IDCODE
CLAMP
BYPASS
2-52
Advanced v0.2
ProASIC3E Flash Family FPGAs
DC and Switching Characteristics
General Specifications
DC and switching characteristics for –F speed grade targets based only on simulation.
The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in commercial temperature range.
Operating Conditions
Stresses beyond those listed in the Table 3-1 may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not
be operated outside the recommended operating ranges specified in Table 3-2 on page 3-2.
Table 3-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits
Units
–0.3 to 1.65
V
V
V
V
V
V
V
VJTAG
VPUMP
VCCPLL
VCCI
–0.3 to 3.75
Programming voltage
–0.3 to 3.75
Analog power supply (PLL)
DC I/O output buffer supply voltage
DC I/O input buffer supply voltage
I/O input voltage
–0.3 to 1.65
–0.3 to 3.75
VMV
VI
–0.3 to 3.75
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when
I/O hot-insertion mode is disabled)
Notes:
1. Device performance is not guaranteed if storage temperature exceeds 110°C.
2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or
overshoot according to the limits shown in Table 3-3 on page 3-2.
Advanced v0.2
3-1
ProASIC3E Flash Family FPGAs
Table 3-2 • Recommended Operating Conditions
Symbol
Ta
Parameter
Commercial
0 to +70
Industrial
–40 to +85
1.425 to 1.575
1.4 to 3.6
Units
Ambient temperature
°C
V
V
V
V
V
V
V
V
V
V
V
VCC
1.5 V DC core supply voltage
JTAG DC voltage
1.425 to 1.575
1.4 to 3.6
VJTAG
VPUMP
Programming voltage
Programming Mode
Operation3
3.0 to 3.6
3.0 to 3.6
0 to 3.6
0 to 3.6
VCCPLL
Analog power supply (PLL)
1.4 to 1.6
1.4 to 1.6
VCCI and VMV 1.5 V DC supply voltage
1.8 V DC supply voltage
2.5 V DC supply voltage
3.3 V DC supply voltage
LVDS differential I/O
1.425 to 1.575
1.7 to 1.9
1.425 to 1.575
1.7 to 1.9
2.3 to 2.7
2.3 to 2.7
3.0 to 3.6
3.0 to 3.6
2.375 to 2.625
3.0 to 3.6
2.375 to 2.625
3.0 to 3.6
LVPECL differential I/O
Notes:
1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given
in Table 3-13 on page 3-15. VMV and VCCI should be at the same voltage within a given I/O bank.
2. All parameters representing voltages are measured with respect to GND unless otherwise specified.
3. VPUMP can be left floating during normal operation (not programming mode).
Table 3-3 • Overshoot and Undershoot Limits (as measured on quiet I/Os)1
Average VCCI-GND Overshoot or Undershoot Duration as a
Percentage of Clock Cycle2
Maximum Overshoot/
Undershoot)2
VCCI and VMV
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one cycle out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at
1 out of 2 cycles, then the maximum overshoot/undershoot has to be reduced by 0.15 V.
Table 3-4 • Flash Programming, Storage, and Operating Limits
Storage Temperature
Product
Grade
Program
Retention
Maximum Operating Junction
Programming Cycles
Min.
0
Max.
110
Temperature TJ (°C)
Commercial
Industrial
500
500
20 years
20 years
110
110
–40
110
Note: This is a stress rating only. Functional operation at any other condition other than those indicated is not implied.
3-2
Advanced v0.2
ProASIC3E Flash Family FPGAs
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and
Industrial)
Sophisticated power-up management circuitry is
designed into every ProASIC3E device. These circuits
ensure easy transition from the powered-off state to the
powered-up state of the device. The many different
supplies can power-up in any sequence with minimized
current spikes or surges. In addition, the I/O will be in a
known state through the power-up sequence. The basic
principle is shown in Figure 3-1.
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up <1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV
higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up
oscillations and current surges. Note the following:
•
During programming, I/Os become tristated and
weakly pulled up to VCCI
JTAG supply, PLL power supplies, and charge pump
PUMP supply have no influence on I/O behavior.
There are five regions to consider during power-up.
.
ProASIC3E I/Os are activated only if ALL of the following
three conditions are met:
•
V
1. VCC and VCCI are above the minimum specified trip
points (Figure 3-1)
Internal Power-Up Activation Sequence
1. Core
2. VCCI > VCC - 0.75 V (Typ)
3. Chip is in the operating mode
2. Input buffers
V
CCI Trip Point:
3. Output buffers: after 200 ns delay from input buffer
activation.
Ramping up: 0.6 V < trip_point_up <1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
V
=V + VT
CCI
CC
Where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
V
CC
V
= 1.575 V
CC
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
(except differential inputs)
but slower because V
is
CCI
speed, V /V , V
/V , etc.
below specifcation. For the
IH IL
OH OL
same reason, input buffers do not
meet V /V levels, and output
IH IL
buffers do not meet V /V levels.
OH OL
V
= 1.425 V
CC
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but slower because V /V are below
CCI CC
specification. For the same reason, input
but I/Os are slower because
the V
is below specification
buffers do not meet V /V levels, and
output buffers do not meet V /V levels.
OH OL
CC
IH IL
Activation trip point:
= 0.85 V 0.25 V
V
a
Deactivation trip point:
= 0.75 V 0.25 V
Region 1: I/O buffers are OFF
V
d
V
Activation trip point:
= 0.9 V 0.3 V
CCI
Min V datasheet specification
CCI
V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
a
Deactivation trip point:
= 0.8 V 0.3 V
V
d
Figure 3-1 • I/O State as a Function of VCCI and VCC Voltage Levels
Advanced v0.2
3-3
ProASIC3E Flash Family FPGAs
Where:
Thermal Characteristics
Introduction
The temperature variable in Actel Designer software
refers to the junction temperature, not the ambient
temperature. This is an important distinction because
dynamic and static power consumption cause the chip
junction to be higher than the ambient temperature.
Ta = Ambient Temperature
∆T = Temperature gradient between junction (silicon)
and ambient ∆T = θja * P
θja = Junction-to-ambient of the package. θja numbers
are located in Table 3-5.
P = Power dissipation
EQ 3-1 can be used to calculate junction temperature.
TJ = Junction Temperature = ∆T + Ta
EQ 3-1
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θjc and
the junction-to-ambient air thermal resistivity is θja. The
thermal characteristics for θja are shown for two air flow
rates. The absolute maximum junction temperature is
110°C. EQ 3-2 shows a sample calculation of the absolute
maximum power dissipation allowed for an 896-pin
FBGA package at commercial temperature and still air.
Max. junction temp. (°C) – Max. ambient temp. (°C)
150°C – 70°C
13.6°C/W
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 5.88 W
θja(°C/W)
EQ 3-2
Table 3-5 • Package Thermal Resistivities
θja
200 ft./min. 500 ft./min.
Package Type
Pin Count
208
θjc
8.0
3.8
Still Air
26.1
Units
Plastic Quad Flat Package (PQFP)
22.5
13.3
20.8
11.9
C/W
C/W
Plastic Quad Flat Package (PQFP) with
embedded heat spreader
208
16.2
Fine Pitch Ball Grid Array (FBGA)
256
484
676
896
3.8
3.2
3.2
2.4
26.6
20.5
16.4
13.6
22.8
17.0
13.0
10.4
21.5
15.9
12.0
9.4
C/W
C/W
C/W
C/W
Temperature and Voltage Derating Factors
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays
(Normalized to TJ = 70°C, VCC = 1.425 V)
Junction Temperature (°C)
Array Voltage
CC (V)
V
–40°C
0.87
0°C
0.92
0.88
0.85
25°C
0.95
0.90
0.87
70°C
1.00
0.95
0.92
85°C
1.02
0.97
0.94
100°C
1.05
1.425
1.500
1.575
0.83
1.00
0.80
0.97
3-4
Advanced v0.2
ProASIC3E Flash Family FPGAs
Calculating Power Dissipation
Quiescent Supply Current
Table 3-7 • Quiescent Supply Current Characteristics
A3PE600
A3PE1500
A3PE3000
1
30 mA
70 mA
150 mA
Static IDD
Notes:
1. IDD Includes VCC, VPUMP, VCCI, and VMV currents in industrial temperature ranges (junction temperature from –40°C to 85°C).
Values do not include I/O static contribution, which is shown in Table 3-8 and Table 3-9 on page 3-6.
2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O leakage
Power per I/O Pin
Table 3-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
VMV
(V)
Static Power
PDC2 (mW)1
Dynamic Power
PAC9 (µW/MHz)2
Single-Ended
3.3 V LVTTL/LVCMOS
3.3 V LVTTL/LVCMOS – Schmitt trigger
2.5 V LVCMOS
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
3.3
3.3
3.3
3.3
–
–
–
–
–
–
–
–
–
–
–
–
17.39
25.51
5.76
2.5 V LVCMOS – Schmitt trigger
1.8 V LVCMOS
7.16
2.72
1.8 V LVCMOS – Schmitt trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
3.3 V PCI
2.80
2.08
2.00
18.82
20.12
18.82
20.12
3.3 V PCI – Schmitt trigger
3.3 V PCI-X
3.3 V PCI-X – Schmitt trigger
Voltage-Referenced
3.3 V GTL
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
2.90
2.13
2.81
2.57
0.17
0.17
1.38
1.38
3.21
3.21
8.23
4.78
4.14
3.71
2.03
2.03
4.48
4.48
9.26
9.26
2.5 V GTL
3.3 V GTL +
2.5 V GTL +
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS
2.5
3.3
2.26
5.71
1.50
2.17
LVPECL
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
Advanced v0.2
3-5
ProASIC3E Flash Family FPGAs
Table 3-9 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings1
CLOAD
(pF)
VCCI
(V)
Static Power
PDC3 (mW)2
Dynamic Power
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL/LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
35
35
35
35
10
10
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
474.70
270.73
151.78
104.55
204.61
204.61
3.3 V PCI-X
Voltage-Referenced
3.3 V GTL
10
10
10
10
20
20
30
30
30
30
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
–
24.08
13.52
2.5 V GTL
–
3.3 V GTL+
2.5 V GTL+
HSTL (I)
–
24.10
–
13.54
7.08
13.88
16.69
25.91
26.02
42.21
26.22
HSTL (II)
27.22
SSTL2 (I)
105.56
116.60
114.87
131.76
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS
–
–
2.5
3.3
7.70
89.62
LVPECL
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI
3. PAC10 is the total dynamic power measured on VCC and VCCI
.
.
3-6
Advanced v0.2
ProASIC3E Flash Family FPGAs
Power Consumption of Various Internal Resources
Table 3-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices
Device-Specific Dynamic
Parameter
A3PE600
PAC1
Definition
Contributions (µW/MHz)
Clock contribution of a Global Rib
100
PAC2
Clock contribution of a Global Spine
10
PAC3
Clock contribution of a VersaTile row
1.00
PAC4
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
0.00
PAC5
0.07
PAC6
0.29
PAC7
0.29
PAC8
0.70
PAC9
Contribution of an I/O input pin (standard dependent)
Contribution of an I/O output pin (standard dependent)
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
First contribution of a PLL
See Table 3-8 on page 3-5.
PAC10
PAC11
PAC12
PAC13
PAC14
See Table 3-9 on page 3-6
25.00
30.00
4.00
Second contribution of a PLL
2.00
Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or SmartPower in
Actel Libero IDE software.
Advanced v0.2
3-7
ProASIC3E Flash Family FPGAs
Power Calculation Methodology
The section below describes a simplified method to estimate power consumption of an application. For more accurate
and detailed power estimations, use the SmartPower tool in the Libero IDE software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-11 on page 3-10
Enable rates of output buffers—guidelines are provided for typical applications in Table 3-12 on page 3-10
Read rate and write rate to the memory—guidelines are provided for typical applications in Table 3-12 on
page 3-10. The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
P
P
STAT is the total static power consumption.
DYN is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in Table 3-11 on page 3-10.
N
ROW is the number of VersaTile rows used in the design—guidelines are provided in Table 3-11 on page 3-10.
CLK is the global clock signal frequency.
If the number of spines and rows is not known, use the simplified formula below:
F
PCLOCK = (PAC1 + NS-CELL*PAC4 ) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
F
CLK is the global clock signal frequency.
Sequential Cells Contribution—P
S-CELL
PS-CELL = NS-CELL * (PAC5+ α1* PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell
is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-11 on page 3-10.
FCLK is the global clock signal frequency.
3-8
Advanced v0.2
ProASIC3E Flash Family FPGAs
Combinational Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* α1 * PAC7*FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-11 on page 3-10.
CLK is the global clock signal frequency.
Routing Net Contribution—P
F
NET
PNET = (NS-CELL + NC-CELL) * α1 * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design.
N
C-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-11 on page 3-10.
CLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
F
INPUTS
PINPUTS = NINPUTS * α2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-11 on page 3-10.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * α2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-11 on page 3-10.
β1 is the I/O buffer enable rate—guidelines are provided in Table 3-12 on page 3-10.
F
CLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations—guidelines are provided in Table 3-12 on page 3-10.
F
WRITE-CLOCK is the memory write clock frequency.
β3 the RAM enable rate for write operations—guidelines are provided in Table 3-12 on page 3-10.
PLL/CCC contribution—P
PLL
PPLL = PAC13 * FCLKIN + Σ PAC14 *FCLKOUT
FCLKIN is the input clock frequency.
FCLKOUT1 is the output clock frequency.
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula output clock by adding its corresponding contribution (PAC14*FCLKOUT product) to the total PLL
contribution.
Advanced v0.2
3-9
ProASIC3E Flash Family FPGAs
–
–
–
–
Bit 2
…
= 25%
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic
element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net
switches at half the clock frequency. Below are some
examples:
Bit 7 (MSB)= 0.78125%
The average toggle rate is = (100% + 50% +
25% + 12.5% +...0.78125%) / 8.
Enable Rate Definition
Output enable rate is the average percentage of time
during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate
should be 100%.
•
The average toggle rate of a shift-register is 100%
as all flip-flop outputs toggle at half of the clock
frequency.
•
The average toggle rate of an 8-bit counter is
25%:
–
–
Bit 0 (LSB) = 100%
Bit 1 = 50%
Table 3-11 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
α1
α2
10%
Table 3-12 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
β1
β2
β3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
3-10
Advanced v0.2
ProASIC3E Flash Family FPGAs
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Y
Combinational Cell
Y
LVPECL
t
= 0.54 ns
t
= 0.47 ns
PD
PD
t
= 1.60 ns
DP
I/O Module
(Non-Registered)
Combinational Cell
Y
LVTTL/LVCMOS
Output drive strength = 12 mA
High slew rate
t
= 2.74 ns
DP
t
= 0.85 ns
PD
I/O Module
(Non-Registered)
Combinational Cell
Y
I/O Module
(Registered)
LVTTL/LVCMOS
Output drive strength = 24 mA
= 2.39 ns
High slew rate
t
DP
t
= 1.31 ns
PY
t
= 0.49 ns
PD
LVPECL
D
Q
I/O Module
(Non-Registered)
Combinational Cell
Y
LVCMOS 1.5 V
Output drive strength = 12 mA
High slew
t
t
= 0.63 ns
ICLKQ
ISUD
t
= 3.30 ns
DP
t
= 0.46 ns
= 0.43 ns
PD
Input LVTTL/LVCMOS
Clock
I/O Module
(Registered)
Register Cell
Register Cell
Combinational Cell
Y
t
= 0.90 ns
PY
D
Q
D
Q
D
Q
GTL+ 3.3 V
= 1.53 ns
I/O Module
(Non-Registered)
t
= 0.46 ns
PD
t
DP
t
t
= 0.53 ns
t
t
= 0.53 ns
t
t
= 0.63 ns
CLKQ
SUD
CLKQ
OCLKQ
OSUD
= 0.40 ns
= 0.40 ns
SUD
= 0.43 ns
LVDS
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
t
= 1.50 ns
PY
t
= 0.90 ns
t
= 0.90 ns
PY
PY
Figure 3-2 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V
Advanced v0.2
3-11
ProASIC3E Flash Family FPGAs
t
t
PY
DIN
t
PYS
D
Q
PAD
DIN
Y
CLK
To array
I/O interface
t
= MAX(t (R), t (F))
PY
PY
PY
t
= MAX(t
(R), t
(F))
PYS
PYS
PYS
t
= MAX(t
(R), t
(F))
DIN
DIN
DIN
V
IH
Vtrip
Vtrip
VCC
VIL
PAD
50%
50%
Y
GND
tPY
(R)
tPY
(F)
tPYS
(R)
tPYS
(F)
VCC
50%
50%
DIN
GND
tDOUT
(R)
tDOUT
(F)
Figure 3-3 • Input Buffer Timing Model and Delays (example)
3-12
Advanced v0.2
ProASIC3E Flash Family FPGAs
tDOUT
D Q
tDP
PAD
DOUT
CLK
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O interface
tDOUT
tDOUT
(F)
VCC
(R)
50%
50%
VCC
D
0 V
50%
50%
0 V
DOUT
PAD
VOH
Vtrip
Vtrip
VOL
tDP
(R)
tDP
(F)
Figure 3-4 • Output Buffer Model and Delays (example)
Advanced v0.2
3-13
ProASIC3E Flash Family FPGAs
tEOUT
D Q
tZL,tZH,tHZ,tLZ, tZLS, tZHS
CLK
E
EOUT
D Q
CLK
PAD
DOUT
D
tEOUT= MAX(tEOUT (R), tEOUT (F))
VCC
I/O interface
D
E
Vcc
50%
tEOUT (R)
50%
tEOUT (F)
Vcc
50%
tLZ
50%
50%
50%
tHZ
EOUT
PAD
tZH
t
VCCI
ZL
90% VCCI
V
V
trip
trip
VOL
10% VCCI
VCC
D
VCC
50%
50%
E
tEOUT (F)
tEOUT (R)
50%
Vcc
50%
tZHS
EOUT
PAD
50%
VOH
tZLS
V
V
trip
trip
VOL
Figure 3-5 • Tristate Output Buffer Timing Model and Delays (example)
3-14
Advanced v0.2
ProASIC3E Flash Family FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software Settings
Table 3-13 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial
Conditions
V
V
V
V
I
I
OH
IL
IH
OL
OH
OL
Drive
Strength
Slew
Rate
I/O Standard
Min, V
Max, V
Min, V
Max, V Max, V
Min, V
mA
mA
3.3 V LVTTL/
12 mA
High
–0.3
0.8
2
3.6
0.4
2.4
12
12
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12 mA
12 mA
High
High
High
–0.3
–0.3
–0.3
0.7
1.7
3.6
3.6
3.6
0.7
1.7
12
12
12
12
12
12
0.35*VCCI
0.30VCCI
0.65*VCCI
0.7*VCCI
0.45
VCCI-0.45
0.25*VCCI 0.75*VCCI
Per PCI Specification
Per PCI-X Specification
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25 mA2
25 mA2
35 mA
33 mA
8 mA
15 mA2
17 mA
21 mA
16 mA
24 mA
High
High
High
High
High
High
High
High
High
High
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
VREF-0.05
VREF+0.05
VREF+0.05
VREF+0.1
VREF+0.1
VREF+0.1
VREF+0.1
VREF+0.2
VREF+0.2
VREF+0.2
VREF+0.2
3.6
0.4
0.4
–
25
25
51
40
8
25
25
51
40
8
VREF-0.05
VREF-0.1
VREF-0.1
VREF-0.1
VREF-0.1
VREF-0.2
VREF-0.2
VREF-0.2
VREF-0.2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
–
0.6
0.6
0.4
0.4
0.54
0.35
0.7
0.5
–
–
VCCI-0.4
VCCI-0.4
VCCI-0.62
VCCI-0.43
VCCI-1.1
VCCI-0.9
HSTL (II)
15
17
21
16
24
15
17
21
16
24
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
1. Currents are measured at 85°C junction temperature.
2. Output drive strength is below JDEC specification.
Advanced v0.2
3-15
ProASIC3E Flash Family FPGAs
Table 3-14 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL
µA
10
IIH
µA
10
IIL
µA
15
IIH
µA
15
DC I/O Standards
3.3 V LVTTL/
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
1. Commercial range (0°C < TJ < 70°C)
2. Industrial range (–40°C < TJ < 85°C)
3-16
Advanced v0.2
ProASIC3E Flash Family FPGAs
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 3-15 • Summary of AC Measuring Points
Input Reference Voltage
Board Termination
Standard
(VREF_TYP
)
Voltage (VTT_REF
)
Measuring Trip Point (Vtrip)
3.3 V LVTTL/
–
–
1.4 V
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
–
–
–
–
–
–
–
–
1.2 V
0.90 V
0.75 V
0.285*VCCI (RR)
0.615*VCCI (FF))
3.3 V PCI-X
–
–
0.285*VCCI (RR)
0.615*VCCI (FF)
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
0.8 V
0.8 V
1.0 V
1.0 V
0.75 V
0.75 V
1.25 V
1.25 V
1.5 V
1.5 V
–
1.2 V
1.2 V
1.5 V
1.5 V
0.75 V
0.75 V
1.25 V
1.25 V
1.485 V
1.485 V
–
VREF
VREF
VREF
VREF
VREF
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
VREF
VREF
VREF
VREF
VREF
Cross point
Cross point
LVPECL
–
–
Table 3-16 • I/O AC Parameter Definitions
Parameter
Definition
tDP
Data to Pad delay through the Output Buffer
tPY
Pad to Data delay through the Input Buffer with Schmitt Trigger disabled
Data to Output Buffer delay through the I/O interface
tDOUT
tEOUT
tDIN
tPYS
tHZ
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Pad to Data delay through the Input Buffer with Schmitt Trigger enabled
Enable to Pad delay through the Output Buffer—high to Z
tZH
Enable to Pad delay through the Output Buffer—Z to high
tLZ
Enable to Pad delay through the Output Buffer—low to Z
tZL
Enable to Pad delay through the Output Buffer—Z to low
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to high
Enable to Pad delay through the Output Buffer with delayed enable—Z to low
Advanced v0.2
3-17
ProASIC3E Flash Family FPGAs
Table 3-17 • Summary of I/O Timing Characteristics – Software Default Settings
Commercial-Case Conditions: TJ= 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
I/O Standard
3.3 V LVTTL/
12 mA
High
35
–
0.45 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.44 2.70 4.46 3.81
ns
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12 mA
12 mA
High
High
High
35
35
35
10
10
–
–
–
0.45 2.79 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28
0.45 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98
0.45 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
ns
ns
ns
ns
ns
Per PCI spec High
25 2 0.45 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.44 2.70 3.80 3.16
25 2 0.45 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.44 2.70 3.80 3.16
3.3 V PCI-X
Per PCI-X
spec
High
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25 mA
25 mA
35 mA
33 mA
8 mA
High
High
High
High
High
High
High
High
High
High
High
High
10
10
10
10
20
20
30
30
30
30
–
25 0.45 1.55 0.03 2.19
25 0.45 1.59 0.03 1.83
25 0.45 1.53 0.03 1.19
25 0.45 1.65 0.03 1.13
50 0.45 2.37 0.03 1.59
25 0.45 2.26 0.03 1.59
50 0.45 1.59 0.03 1.00
25 0.45 1.62 0.03 1.00
50 0.45 1.72 0.03 0.93
25 0.45 1.54 0.03 0.93
–
–
–
–
–
–
–
–
–
–
–
–
0.32 1.52 1.55
0.32 1.61 1.59
0.32 1.56 1.53
0.32 1.68 1.57
0.32 2.42 2.35
0.32 2.30 2.03
0.32 1.62 1.38
0.32 1.65 1.32
0.32 1.75 1.37
0.32 1.57 1.25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.19 3.22
3.28 3.26
3.23 3.20
3.35 3.24
4.09 4.02
3.97 3.70
3.29 3.05
3.32 2.99
3.42 3.04
3.24 2.92
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS
15 mA
17 mA
21 mA
16 mA
24 mA
24 mA
24 mA
–
–
0.45 1.57 0.03 1.50
0.45 1.60 0.03 1.31
–
–
–
–
–
–
–
–
–
–
LVPECL
–
Notes:
1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-10 on page 3-34 for connectivity.
This resistor is not required during normal operation.
Detailed I/O DC Characteristics
Table 3-18 • Input Capacitance
Symbol
CIN
Definition
Input capacitance
Input capacitance on the clock pin
Conditions
Min.
Max.
Units
pF
VIN=0, f=1.0 MHz
VIN=0, f=1.0 MHz
8
8
CINCLK
pF
3-18
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 3-19 • I/O Output Buffer Maximum Resistances1
RPULL-DOWN
(Ω)2
100
50
RPULL-UP
(Ω)3
300
150
75
Standard
Drive Strength
3.3 V LVTTL/3.3 V LVCMOS
4 mA
8 mA
12 mA
16 mA
24 mA
4 mA
25
17
50
11
33
2.5 V LVCMOS
1.8 V LVCMOS
100
50
200
100
50
8 mA
12 mA
16 mA
24 mA
2 mA
25
20
40
11
22
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
12 mA
16 mA
2 mA
20
22
20
22
1.5 V LVCMOS
200
100
67
224
112
75
4 mA
6 mA
8 mA
33
37
12 mA
Per PCI/PCI-X specification
25 mA
25 mA
35 mA
33 mA
8 mA
33
37
3.3 V PCI/PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25
75
11
–
14
–
12
–
15
–
50
50
HSTL (II)
15 mA
17 mA
21 mA
16 mA
24 mA
25
25
SSTL2 (I)
27
31
SSTL2 (II)
SSTL3 (I)
13
15
44
69
SSTL3 (II)
Notes:
18
32
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive
strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
Advanced v0.2
3-19
ProASIC3E Flash Family FPGAs
Table 3-20 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R((WEAK PULL-UP)
R(WEAK PULL-DOWN)
(Ω)
(Ω)
VCCI
Min.
10 k
11 k
18 k
19 k
Max.
45 k
55 k
70 k
90 k
Min.
10 k
12 k
17 k
19 k
Max.
3.3 V
2.5 V
1.8 V
1.5 V
Notes:
45 k
74 k
110 k
140 k
1. R(WEAK PULL-DOWN-MAX) = (VOLspec) / IWEAK PULL-DOWN-MIN
2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN
Table 3-21 • I/O Short Currents IOSH/IOSL
Drive Strength
IOSH (mA)*
IOSL (mA)*
27
3.3 V LVTTL/3.3 V LVCMOS
4 mA
8 mA
25
51
103
132
268
16
32
65
83
169
9
54
12 mA
16 mA
24 mA
4 mA
109
127
181
18
2.5 V LVCMOS
8 mA
37
12 mA
16 mA
24 mA
2 mA
74
87
124
11
1.8 V LVCMOS
4 mA
17
35
45
91
91
13
25
32
66
66
22
6 mA
44
8 mA
51
12 mA
16 mA
2 mA
74
74
1.5 V LVCMOS
16
4 mA
33
6 mA
39
8 mA
55
12 mA
55
Note: *TJ = 100°C
3-20
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 3-22 • Short Current Event Duration Before Failure
The length of time an I/O can withstand IOSH/IOSL events
depends on the junction temperature. The reliability
data below is based on a 3.3 V, 36 mA I/O setting, which
is the worst case for this type of analysis.
Temperature
–40°C
0°C
Time Before Failure
> 20 years
> 20 years
> 20 years
5 years
For example, at 110°C, the short current condition would
have to be sustained for more than three months to
cause a reliability concern. The I/O design does not
contain any short circuit protection, but such protection
would only be needed in extremely prolonged stress
conditions.
25°C
70°C
85°C
2 years
100°C
110°C
6 months
3 months
Table 3-23 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (Typ)
3.3 V LVTTL/LVCMOS / PCI / PCI-X (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
240 mV
140 mV
80 mV
60 mV
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (Min.)
No requirement
Input Rise/Fall Time (Max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger disabled)
LVTTL/LVCMOS (Schmitt trigger enabled)
10 ns (or more*)
20 years (110°C)
No requirement
No requirement, but input noise voltage 20 years (110°C)
cannot exceed schmitt hysteresis
HSTL/SSTL/GTL
LVDS/LVPECL
No requirement
No requirement
10 ns (or more*)
10 ns (or more*)
10 years (100°C)
10 years (100°C)
Note: *This limitation is related only to the noise induced into input buffer trace. If the noise is low, then the rise time and fall time of
input buffers when Schmitt trigger is disabled can be increased beyond the maximum value. The longer the rise/fall times, the more
susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to
ensure that there is no excessive noise coupling into input signals.
Advanced v0.2
3-21
ProASIC3E Flash Family FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL/3.3 V LVCMOS
Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL
input buffer and push-pull output buffer. 3.3 V LVCMOS standard is supported as part of the 3.3 V LVTTL support.
Table 3-25 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL/
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V Min, V Max, V Max, V Min, V mA
mA Max, mA1 Max, mA1 µA2
µA2
10
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
4
4
27
54
25
51
10
10
10
10
10
8 mA
8
8
10
12 mA
16 mA
24 mA
Notes:
12
16
24
12
16
24
109
127
181
103
132
268
10
10
10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Data Path
35 pF
35 pF for tZH /tZHS /t /t
ZL ZLS
5 pF for tHZ /tLZ
Figure 3-6 • AC Loading
Table 3-26 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.4
VREF (Typ) (V)
CLOAD (pF)
0
3.3
–
35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
3-22
Advanced v0.2
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 3-27 • 3.3 V LVTTL/3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Drive Strength Speed
Grade tZLS tZHS Units
(mA)
tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
4m A
–F
Std.
–1
0.72 13.22 0.05 1.44 1.88 0.51 13.47 10.87 3.23 2.93 16.16 13.56
0.60 11.01 0.04 1.20 1.56 0.43 11.21 9.05 2.69 2.44 13.45 11.29
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.51
0.45
0.72
0.60
0.51
0.45
0.72
0.60
0.51
0.45
0.72
0.60
0.51
0.45
0.72
0.60
0.51
0.45
9.36 0.04 1.02 1.33 0.36 9.54 7.70 2.29 2.08 11.44 9.60
8.22 0.03 0.90 1.17 0.32 8.37 6.76 2.01 1.82 10.04 8.43
9.45 0.05 1.44 1.88 0.51 9.62 7.74 3.65 3.68 12.31 10.42
7.86 0.04 1.20 1.56 0.43 8.01 6.44 3.04 3.06 10.24 8.68
6.69 0.04 1.02 1.33 0.36 6.81 5.48 2.58 2.61 8.71 7.38
5.87 0.03 0.90 1.17 0.32 5.98 4.81 2.27 2.29 7.65 6.48
7.24 0.05 1.44 1.88 0.51 7.37 6.03 3.93 4.17 10.06 8.72
6.03 0.04 1.20 1.56 0.43 6.14 5.02 3.27 3.47 8.37 7.26
5.12 0.04 1.02 1.33 0.36 5.22 4.27 2.79 2.95 7.12 6.17
4.50 0.03 0.90 1.17 0.32 4.58 3.75 2.44 2.59 6.25 5.42
6.75 0.05 1.44 1.88 0.51 6.87 5.67 3.99 4.30 9.56 8.36
5.62 0.04 1.20 1.56 0.43 5.72 4.72 3.32 3.58 7.96 6.96
4.78 0.04 1.02 1.33 0.36 4.87 4.02 2.83 3.04 6.77 5.92
4.20 0.03 0.90 1.17 0.32 4.27 3.53 2.48 2.67 5.94 5.20
6.30 0.05 1.44 1.88 0.51 6.42 5.64 4.07 4.76 9.10 8.32
5.24 0.04 1.20 1.56 0.43 5.34 4.69 3.38 3.96 7.58 6.93
4.46 0.04 1.02 1.33 0.36 4.54 3.99 2.88 3.37 6.44 5.89
3.92 0.03 0.90 1.17 0.32 3.99 3.50 2.53 2.96 5.66 5.17
–2
8m A
–F
Std.
–1
–2
12 mA
16 mA
24 mA
–F
Std.
–1
–2
–F
Std.
–1
–2
–F
Std.
–1
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-23
ProASIC3E Flash Family FPGAs
Table 3-28 • 3.3 V LVTTL/3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Drive Strength Speed
Grade tZLS tZHS Units
(mA)
tDOUT tDP tDIN tPY tPYS tEOUT tZL
tZH
tLZ
tHZ
4 mA
–F
Std.
–1
0.72 9.47 0.05 1.44 1.88 0.51 9.64 8.05 3.23 3.11 12.33 10.74
0.60 7.88 0.04 1.20 1.56 0.43 8.03 6.70 2.69 2.59 10.26 8.94
0.51 6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73 7.60
0.45 5.89 0.03 0.90 1.17 0.32 6.00 5.00 2.01 1.93 7.67 6.67
0.72 6.10 0.05 1.44 1.88 0.51 6.21 4.98 3.66 3.86 8.90 7.66
0.60 5.08 0.04 1.20 1.56 0.43 5.17 4.14 3.05 3.21 7.41 6.38
0.51 4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30 5.43
0.45 3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.27 2.40 5.53 4.76
0.72 4.41 0.05 1.44 1.88 0.51 4.49 3.45 3.93 4.34 7.17 6.13
0.60 3.67 0.04 1.20 1.56 0.43 3.73 2.87 3.27 3.61 5.97 5.11
0.51 3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34
0.45 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.44 2.70 4.46 3.81
0.72 4.16 0.05 1.44 1.88 0.51 4.24 3.13 4.00 4.47 6.92 5.82
0.60 3.46 0.04 1.20 1.56 0.43 3.53 2.60 3.33 3.72 5.76 4.84
0.51 2.94 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90 4.12
0.45 2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30 3.62
0.72 3.85 0.05 1.44 1.88 0.51 3.92 2.59 4.07 4.96 6.61 5.28
0.60 3.21 0.04 1.20 1.56 0.43 3.27 2.15 3.38 4.13 5.50 4.39
0.51 2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68 3.73
0.45 2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11 3.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
8 mA
–F
Std.
–1
–2
12 mA
16 mA
24 mA
Notes:
–F
Std.
–1
–2
–F
Std.
–1
–2
–F
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-24
Advanced v0.2
ProASIC3E Flash Family FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5 V
applications. It uses a 5-V-tolerant input buffer and push-pull output buffer.
Table 3-29 • Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V Min, V Max, V Max, V Min, V mA
mA Max, mA1 Max, mA1 µA2
µA2
10
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
4
4
18
37
16
32
10
10
10
10
10
8 mA
8
8
10
12 mA
16 mA
24 mA
Notes:
12
16
24
12
16
24
74
65
10
87
83
10
124
169
10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Data Path
35 pF
35 pF for tZH /tZHS /t /t
ZL ZLS
5 pF for tHZ /tLZ
Figure 3-7 • AC Loading
Table 3-30 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.2
VREF (Typ) (V)
CLOAD (pF)
0
2.5
–
35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Advanced v0.2
3-25
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 3-31 • 2.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
Drive Strength Speed
Grade tZLS tZHS Units
(mA)
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
4 mA
–F
Std.
–1
0.72 14.42 0.05 1.81 1.99 0.51 14.69 13.95 3.26 2.64 17.37 16.63
0.60 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.19 14.46 13.85
0.51 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
0.45
8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34
8 mA
–F
0.72 10.49 0.05 1.81 1.99 0.51 10.68 9.62 3.73 3.52 13.37 12.31
Std.
–1
0.60
0.51
0.45
0.72
0.60
0.51
0.45
0.72
0.60
0.51
0.45
0.72
0.60
0.51
0.45
8.73 0.04 1.51 1.66 0.43 8.89 5.35 3.10 2.93 11.13 7.59
7.43 0.04 1.29 1.41 0.36 7.57 4.55 2.64 2.49 9.47 6.45
6.52 0.03 1.13 1.24 0.32 6.64 4.00 2.32 2.19 8.31 5.67
8.14 0.05 1.81 1.99 0.51 8.29 7.34 4.04 4.08 10.97 10.02
6.77 0.04 1.51 1.66 0.43 6.90 6.11 3.37 3.39 9.13 8.34
5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10
5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23
7.58 0.05 1.81 1.99 0.51 7.72 6.88 4.11 4.23 10.40 9.57
6.31 0.04 1.51 1.66 0.43 6.42 5.73 3.42 3.52 8.66 7.96
5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77
4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95
7.12 0.05 1.81 1.99 0.51 7.26 6.85 4.20 4.80 9.94 9.54
5.93 0.04 1.51 1.66 0.43 6.04 5.70 3.49 4.00 8.28 7.94
5.04 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75
4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.98 6.18 5.93
–2
12 mA
16 mA
24 mA
–F
Std.
–1
–2
–F
Std.
–1
–2
–F
Std.
–1
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-26
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 3-32 • 2.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
Drive Strength Speed
(mA)
Grade tDOUT tDP
tDIN
0.72 10.59 0.05 1.81 1.99 0.51 9.77 10.59 3.26 2.75 12.45 13.28
0.60 8.81 0.04 1.51 1.66 0.43 8.13 8.81 2.72 2.29 10.37 11.05
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
4 mA
–F
Std.
–1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.51 7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40
0.45 6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25
0.72 6.33 0.05 1.81 1.99 0.51 6.33 6.33 3.73 3.64 9.02 9.02
–2
8 mA
–F
Std.
–1
0.60 5.27 0.04 1.51 1.66 0.43
5.27 5.27 3.10 3.03 7.50 7.50
0.51 4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 0.00
0.45 3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61
0.72 4.50 0.05 1.81 1.99 0.51 4.58 4.19 4.04 4.20 7.26 6.88
0.60 3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73
0.51 3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.14 4.87
0.45 2.79 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28
0.72 4.24 0.05 1.81 1.99 0.51 4.32 3.75 4.11 4.35 7.00 6.43
–2
12 mA
16 mA
24 mA
Notes:
–F
Std.
–1
–2
–F
Std.
–1
0.60 3.53 0.04 1.51 1.66 0.43
3.59 3.12 3.42 3.62 5.83 5.35
0.51 3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55
0.45 2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00
0.72 3.92 0.05 1.81 1.99 0.51 3.99 2.98 4.20 4.93 6.67 5.67
–2
–F
Std.
–1
0.60 3.26 0.04 1.51 1.66 0.43
3.32 2.48 3.49 4.11 5.56 4.72
0.51 2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01
0.45 2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-27
ProASIC3E Flash Family FPGAs
1.8 V LVCMOS
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.8 V
applications. It uses 1.8 V input buffer and push-pull output buffer.
Table 3-33 • Minimum and Maximum DC Input and Output Levels
1.8 V LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V
Min, V Max, V Max, V Min, V
mA mA Max, mA1 Max, mA1 µA2 µA2
2 mA
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.35*VCCI 0.65*VCCI
3.6
3.6
3.6
3.6
3.6
3.6
0.45
0.45
0.45
0.45
0.45
0.45
VCCI-0.45
VCCI-0.45
VCCI-0.45
VCCI-0.45
VCCI-0.45
VCCI-0.45
2
4
2
4
11
22
44
51
74
74
9
10
10
10
10
10
10
10
10
10
10
10
10
4 mA
0.35*VCCI 0.65*VCCI
0.35*VCCI 0.65*VCCI
0.35*VCCI 0.65*VCCI
0.35*VCCI 0.65*VCCI
0.35*VCCI 0.65*VCCI
17
35
45
91
91
6 mA
6
6
8 mA
8
8
12 mA
16 mA
Notes:
12
16
12
16
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Data Path
35 pF
35 pF for tZH /tZHS /t /t
ZL ZLS
5 pF for tHZ /tLZ
Figure 3-8 • AC Loading
Table 3-34 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
0.9
VREF (Typ) (V)
CLOAD (pF)
0
1.8
–
35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
3-28
Advanced v0.2
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 3-35 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V
Drive Strength Speed
(mA)
Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS tZHS Units
2 mA
–F
Std.
–1
0.72 19.02 0.05 1.74 2.29 0.51 18.80 19.02 3.34 1.90 21.49 21.71
0.60 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07
0.51 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.21 15.37
0.45 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50
0.72 13.68 0.05 1.74 2.29 0.51 13.94 12.92 3.91 3.33 16.62 15.61
0.60 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99
0.51 9.69 0.04 1.23 1.62 0.36 9.87 9.15 2.77 2.36 11.77 11.05
0.45 8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70
0.72 10.78 0.05 1.74 2.29 0.51 10.97 9.73 4.29 4.03 13.66 12.41
0.60 8.97 0.04 1.45 1.91 0.43 9.14 8.10 3.57 3.36 11.37 10.33
0.51 7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79
0.45 6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72
0.72 10.03 0.05 1.74 2.29 0.51 10.22 9.11 4.37 4.23 12.90 11.80
0.60 8.35 0.04 1.45 1.91 0.43 8.50 7.58 3.64 3.52 10.74 9.82
0.51 7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35
0.45 6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33
0.72 9.54 0.05 1.74 2.29 0.51 9.71 9.08 4.50 4.93 12.40 11.77
0.60 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80
0.51 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33
0.45 5.93 0.03 1.08 1.42 0.32 6.04 5.64 2.79 3.07 7.71 7.32
0.72 9.54 0.05 1.74 2.29 0.51 9.71 9.08 4.50 4.93 12.40 11.77
0.60 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80
0.51 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33
0.45 5.93 0.03 1.08 1.42 0.32 6.04 5.64 2.79 3.07 7.71 7.32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
4 mA
6 mA
8 mA
12 mA
16 mA
–F
Std.
–1
–2
–F
Std.
–1
–2
–F
Std.
–1
–2
–F
Std.
–1
–2
–F
Std.
–1
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-29
ProASIC3E Flash Family FPGAs
Table 3-36 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V
Drive Strength Speed
(mA)
Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
–F
Std.
–1
0.72 14.54 0.05 1.74 2.29 0.51 11.52 14.54 3.34 1.97 14.21 17.23
0.60 12.10 0.04 1.45 1.91 0.43 9.59 12.10 2.78 1.64 11.82 14.34
0.51 10.30 0.04 1.23 1.62 0.36 8.16 10.30 2.37 1.39 10.06 12.20
0.45 9.04 0.03 1.08 1.42 0.32 7.16 9.04 2.08 1.22 8.83 10.71
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
4 mA
–F
0.72 8.47 0.05 1.74 2.29 0.51
0.60 7.05 0.04 1.45 1.91 0.43
7.45 8.47 3.90 3.44 10.13 11.16
6.20 7.05 3.25 2.86 8.44 9.29
Std.
–1
0.51 6.00 0.04 1.23 1.62 0.36 5.28 6.00 2.76 2.44 7.18 7.90
0.45 5.26 0.03 1.08 1.42 0.32 4.63 5.26 2.42 2.14 6.30 6.93
0.72 5.43 0.05 1.74 2.29 0.51 5.36 5.43 4.29 4.17 8.05 8.12
–2
6 mA
–F
Std.
–1
0.60 4.52 0.04 1.45 1.91 0.43
4.46 4.52 3.57 3.47 6.70 6.76
0.51 3.85 0.04 1.23 1.62 0.36 3.80 3.85 3.04 2.95 5.70 5.75
0.45 3.38 0.03 1.08 1.42 0.32 3.33 3.38 2.66 2.59 5.00 5.05
0.72 4.95 0.05 1.74 2.29 0.51 5.04 4.80 4.36 4.35 7.73 7.48
–2
8 mA
–F
Std.
–1
0.60 4.12 0.04 1.45 1.91 0.43
4.20 3.99 3.63 3.62 6.43 6.23
0.51 3.51 0.04 1.23 1.62 0.36 3.57 3.40 3.09 3.08 5.47 5.30
0.45 3.08 0.03 1.08 1.42 0.32 3.13 2.98 2.71 2.71 4.80 4.65
0.72 4.56 0.05 1.74 2.29 0.51 4.64 3.71 4.48 5.09 7.33 6.39
0.60 3.79 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32
0.51 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.17 3.60 5.19 4.53
0.45 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98
0.72 4.56 0.05 1.74 2.29 0.51 4.64 3.71 4.48 5.09 7.33 6.39
–2
12 mA
16 mA
Notes:
–F
Std.
–1
–2
–F
Std.
–1
0.60 3.79 0.04 1.45 1.91 0.43
3.87 3.09 3.73 4.24 6.10 5.32
0.51 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.17 3.60 5.19 4.53
0.45 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98
–2
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-30
Advanced v0.2
ProASIC3E Flash Family FPGAs
1.5 V LVCMOS (JESD8-11)
Low-voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.5 V
applications. It uses 1.5 V input buffer and push-pull output buffer.
Table 3-37 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength Min, V Max, V
Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2
µA2
10
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3
–0.3
–0.3
–0.3
–0.3
0.30*VCCI 0.7*VCCI
0.30*VCCI 0.7*VCCI
0.30*VCCI 0.7*VCCI
0.30*VCCI 0.7*VCCI
0.30*VCCI 0.7*VCCI
3.6
3.6
3.6
3.6
3.6
0.25*VCCI 0.75*VCCI
0.25*VCCI 0.75*VCCI
0.25*VCCI 0.75*VCCI
0.25*VCCI 0.75*VCCI
2
4
6
8
2
4
16
33
39
55
55
13
25
32
66
66
10
10
10
10
10
10
6
10
8
10
0.25*VCCI 0.75*VCCI 12
12
10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Data Path
35 pF
35 pF for tZH /tZHS /t /t
ZL ZLS
5 pF for tHZ /tLZ
Figure 3-9 • AC Loading
Table 3-38 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
CLOAD (pF)
0
1.5
0.75
–
35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Advanced v0.2
3-31
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 3-39 • 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V
Drive strength Speed
(mA)
grade tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
–F
Std.
–1
0.72 16.95 0.03 2.04 2.58 0.51 17.26 15.78 4.09 3.22 19.95 18.47
0.60 14.11 0.04 1.70 2.14 0.43 14.37 13.14 3.40 2.68 16.61 15.37
0.51 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08
0.45 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48
0.72 13.49 0.05 2.04 2.58 0.51 13.74 11.85 4.53 4.03 16.43 14.54
0.60 11.23 0.04 1.70 2.14 0.43 11.44 9.87 3.77 3.36 13.68 12.10
0.51 9.55 0.04 1.44 1.82 0.36 9.73 8.39 3.21 2.86 11.63 10.29
0.45 8.39 0.03 1.27 1.60 0.32 8.54 7.37 2.81 2.51 10.21 9.04
0.72 12.56 0.05 2.04 2.58 0.51 12.79 11.10 4.62 4.26 15.47 13.79
0.60 10.45 0.04 1.70 2.14 0.43 10.64 9.24 3.84 3.55 12.88 11.48
0.51 8.89 0.04 1.44 1.82 0.36 9.06 7.86 3.27 3.02 10.96 9.76
0.45 7.80 0.03 1.27 1.60 0.32 7.95 6.90 2.87 2.65 9.62 8.57
0.72 12.04 0.05 2.04 2.58 0.51 12.26 11.09 4.77 5.07 14.94 13.77
0.60 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.46
0.51 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75
0.45 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.96 3.15 9.29 8.56
0.72 12.04 0.05 2.04 2.58 0.51 12.26 11.09 4.77 5.07 14.94 13.77
0.60 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.46
0.51 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75
0.45 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.96 3.15 9.29 8.56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
4 mA
6 mA
8 mA
12 mA
–F
Std.
–1
–2
–F
Std.
–1
–2
–F
Std.
–1
–2
–F
Std.
–1
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-32
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 3-40 • 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V
Drive strength
(mA)
Speed
grade
tDOU
tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS tZHS Units
T
2 mA
–F
Std.
–1
0.72 10.25 0.05 2.04 2.58 0.51 8.72 10.25 4.08 3.35 11.41 12.94
0.60 8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77
0.51 7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08 9.16
0.45 6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09 8.04
0.72 6.50 0.05 2.04 2.58 0.51 6.26 6.50 4.50 4.18 8.95 9.19
0.60 5.41 0.04 1.70 2.14 0.43 5.21 5.41 3.75 3.48 7.45 7.65
0.51 4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34 6.50
0.45 4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56 5.71
0.72 5.77 0.05 2.04 2.58 0.51 5.88 5.70 4.60 4.41 8.56 8.39
0.60 4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13 6.98
0.51 4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06 5.94
0.45 3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32 5.21
0.72 5.31 0.05 2.04 2.58 0.51 5.41 4.35 4.76 5.25 8.09 7.04
0.60 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86
0.51 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98
0.45 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
0.72 5.31 0.05 2.04 2.58 0.51 5.41 4.35 4.76 5.25 8.09 7.04
0.60 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86
0.51 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98
0.45 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
4 mA
–F
Std.
–1
–2
6 mA
–F
Std.
–1
–2
8 mA
–F
Std.
–1
–2
12 mA
–F
Std.
–1
–2
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-33
ProASIC3E Flash Family FPGAs
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications.
Table 3-41 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
Drive Strength
Per PCI specification
Notes:
VIL
VIH
VOL
VOH
IOL
IOH
mA Max, mA1 Max, mA1 µA2 µA2
10 10
IOSL
IOSH
IIL
IIH
Min, V Max, V Min, V Max, V Max, V Min, V mA
Per PCI curves
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the data path; Actel loadings for enable path
characterization are described in Figure 3-10.
R to VCCI for tDP (F)
R to GND for tDP (R)
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 25
Test Point
Data Path
R = 1 k
Test Point
Enable Path
10 pF for tZH /tZHS/tZL/tZLS
5 pF for tHZ /tLZ
Figure 3-10 • AC Loading
AC loading are defined per PCI/PCI-X specifications for the data path; Actel loading for tristate is described in Table 3-42.
Table 3-42 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
CLOAD (pF)
0
3.3
0.285*VCCI for tDP(R)
0.615*VCCI for tDP(F)
–
10
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-43 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
3.37
2.81
2.39
2.09
tDIN
tPY
tPYS tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
–F
0.05 1.26
0.04 1.05
0.04 0.89
0.03 0.78
2.01
1.67
1.42
1.25
0.51
0.43
0.36
0.32
3.43
2.86
2.43
2.13
2.40 3.93 4.34
2.00 3.27 3.61
1.70 2.79 3.07
1.49 2.44 2.70
6.12 5.08
5.09 4.23
4.33 3.60
3.80 3.16
ns
ns
ns
ns
Std.
–1
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-34
Advanced v0.2
ProASIC3E Flash Family FPGAs
Voltage Referenced I/O Characteristics
3.3 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and
an open drain output buffer. The VCCI pin should be connected to 3.3 V.
Table 3-44 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength Min, V Max, V
Min, V Max, V Max, V Min, V mA
mA Max, mA1 Max, mA1 µA2
25 181 268 10
µA2
25 mA3
–0.3
VREF-0.05 VREF+0.05 3.6 0.4 25
–
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 3-11 • AC Loading
Table 3-45 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF-0.05
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
1.2
CLOAD (pF)
V
VREF+0.05
0.8
0.8
10
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-46 • 3.3 V GTL
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V VREF = 0.8 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.49
2.08
1.76
1.55
tDIN
0.05
0.04
0.04
0.03
tPY
3.52
2.93
2.50
2.19
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
2.49
2.08
1.76
1.55
tLZ
tHZ
tZLS
5.13
4.27
3.63
3.19
tZHS Units
–F
2.45
2.04
1.73
1.52
5.18
4.31
3.67
3.22
ns
ns
ns
ns
Std.
–1
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-35
ProASIC3E Flash Family FPGAs
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and
an open drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 3-47 • Minimum and Maximum DC Input and Output Levels
2.5 GTL
VIL
VIH
Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
VREF-0.05 VREF+0.05 3.6 0.4 25 25 124 169 10 10
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V
25 mA3
–0.3
–
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 3-12 • AC Loading
Table 3-48 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF-0.05
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
V
VREF+0.05
0.8
0.8
1.2
10
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-49 • 2.5 V GTL
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V VREF = 0.8 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.56
2.13
1.81
1.59
tDIN
0.05
0.04
0.04
0.03
tPY
2.95
2.46
2.09
1.83
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
5.28
4.40
3.74
3.28
tZHS Units
–F
2.60
2.16
1.84
1.61
2.56
2.13
1.81
1.59
5.24
4.36
3.71
3.26
ns
ns
ns
ns
Std.
–1
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-36
Advanced v0.2
ProASIC3E Flash Family FPGAs
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer
and an open drain output buffer. The VCCI pin should be connected to 3.3 V.
Table 3-50 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL+
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL IIH
Drive Strength Min, V Max, V
Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
35 mA
–0.3
VREF-0.1 VREF+0.1
3.6
0.6
–
35
35
181
268
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 3-13 • AC Loading
Table 3-51 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF-0.1
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
V
VREF+0.1
1.0
1.0
1.5
10
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-52 • 3.3 V GTL+
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V, VREF = 1.0 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.47
2.06
1.75
1.53
tDIN
0.05
0.04
0.04
0.03
tPY
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
5.20
4.33
3.68
3.23
tZHS
5.15
4.29
3.65
3.20
Units
ns
–F
1.91
1.59
1.35
1.19
2.51
2.09
1.78
1.56
2.47
2.06
1.75
1.53
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-37
ProASIC3E Flash Family FPGAs
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer
and an open drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 3-53 • Minimum and Maximum DC Input and Output Levels
2.5 V GTL+
VIL
VIH
Min, V Max, V Max, V Min, V mA
VREF-0.1 VREF+0.1 3.6 0.6 33
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL IIH
Drive Strength Min, V Max, V
mA Max, mA1 Max, mA1 µA2 µA2
33 mA
–0.3
–
33
124
169
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 3-14 • AC Loading
Table 3-54 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF-0.1
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
V
VREF+0.1
1.0
1.0
1.5
10
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-55 • 2.5 V GTL+
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V, VREF = 1.0 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.65
2.21
1.88
1.65
tDIN
0.05
0.04
0.04
0.03
tPY
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
5.38
4.48
3.81
3.35
tZHS
5.21
4.33
3.69
3.24
Units
ns
–F
1.82
1.51
1.29
1.13
2.70
2.25
1.91
1.68
2.52
2.10
1.78
1.57
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-38
Advanced v0.2
ProASIC3E Flash Family FPGAs
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices
support Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 3-56 • Minimum and Maximum DC Input and Output Levels
HSTL Class I
VIL
VIH
Min, V Max, V Max, V Min, V mA
VREF-0.1 VREF+0.1 3.6 0.4 VCCI-0.4
VOL
VOH
IOL
IOH
mA Max, mA1 Max, mA1 µA2 µA2
39 32 10 10
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V
8 mA
–0.3
8
8
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
HSTL
Class I
50
Test Point
20 pF
Figure 3-15 • AC Loading
Table 3-57 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF-0.1
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
V
VREF+0.1
0.75
0.75
0.75
20
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-58 • HSTL Class I
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V, VREF = 0.75 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
3.82
3.18
2.70
2.37
tDIN
0.05
0.04
0.04
0.03
tPY
2.55
2.12
1.81
1.59
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
3.77
3.14
2.67
2.35
tLZ
tHZ
tZLS
6.58
5.47
4.66
4.09
tZHS
6.46
5.38
4.58
4.02
Units
ns
–F
3.89
3.24
2.75
2.42
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-39
ProASIC3E Flash Family FPGAs
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices
support Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 3-59 • Minimum and Maximum DC Input and Output Levels
HSTL Class II
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V
Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
15 mA3
–0.3
VREF-0.1 VREF+0.1
3.6
0.4 VCCI-0.4 15
15
55
66
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JDEC specification.
VTT
HSTL
Class II
25
Test Point
20 pF
Figure 3-16 • AC Loading
Table 3-60 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
0.75
VREF (Typ) (V) VTT (Typ) (V)
CLOAD (pF)
VREF-0.1
VREF+0.1
0.75
0.75
20
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-61 • HSTL Class II
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V, VREF = 0.75 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
3.63
3.02
2.57
2.26
tDIN
0.05
0.04
0.04
0.03
tPY
2.55
2.12
1.81
1.59
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
3.26
2.71
2.31
2.03
tLZ
tHZ
tZLS
6.39
5.32
4.52
3.97
tZHS
5.95
4.95
4.21
3.70
Units
ns
–F
3.70
3.08
2.62
2.30
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-40
Advanced v0.2
ProASIC3E Flash Family FPGAs
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides
a differential amplifier input buffer and a push-pull output buffer.
Table 3-62 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class I
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V Min, V Max, V Max, V Min, V
–0.3 VREF-0.2 VREF+0.2 3.6 0.54
mA
mA Max, mA1 Max, mA1 µA2 µA2
17 mA
VCCI - 0.62 17
17
87
83
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class I
50
Test Point
25
30 pF
Figure 3-17 • AC Loading
Table 3-63 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
VREF-0.2
VREF+0.2
1.25
1.25
1.25
30
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-64 • SSTL 2 Class I
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V, VREF = 1.25 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.56
2.13
1.81
1.59
tDIN
0.05
0.04
0.04
0.03
tPY
1.60
1.33
1.14
1.00
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
5.29
4.40
3.74
3.29
tZHS Units
–F
2.60
2.17
1.84
1.62
2.22
1.85
1.57
1.38
4.90
4.08
3.47
3.05
ns
ns
ns
ns
Std.
–1
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-41
ProASIC3E Flash Family FPGAs
SSTL2 Class II
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This
provides a differential amplifier input buffer and a push-pull output buffer.
Table 3-65 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class II
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V
mA mA Max, mA1 Max, mA1 µA2 µA2
21 mA
–0.3
VREF-0.2 VREF+0.2
3.6
0.35 VCCI - 0.43 21
21
124
169
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class II
25
Test Point
25
30 pF
Figure 3-18 • AC Loading
Table 3-66 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
1.25
VTT (Typ) (V)
CLOAD (pF)
VREF-0.2
VREF+0.2
1.25
1.25
30
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-67 • SSTL 2 Class II
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V, VREF = 1.25 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.60
2.17
1.84
1.62
tDIN
0.05
0.04
0.04
0.03
tPY
1.60
1.33
1.14
1.00
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
2.13
1.77
1.50
1.32
tLZ
tHZ
tZLS
5.34
4.44
3.78
3.32
tZHS
4.81
4.01
3.41
2.99
Units
ns
–F
2.65
2.21
1.88
1.65
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-42
Advanced v0.2
ProASIC3E Flash Family FPGAs
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides
a differential amplifier input buffer and a push-pull output buffer.
Table 3-68 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class I
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL IIH
Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
16 mA
–0.3
VREF-0.2 VREF+0.2
3.6
0.7
VCCI - 1.1 16
16
54
51
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class I
50
Test Point
25
30 pF
Figure 3-19 • AC Loading
Table 3-69 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF-0.2
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
1.5
VTT (Typ) (V)
CLOAD (pF)
V
VREF+0.2
1.5
1.485
30
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-70 • SSTL3 Class I
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V, VREF = 1.5 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.77
2.31
1.96
1.72
tDIN
0.05
0.04
0.04
0.03
tPY
1.50
1.25
1.06
0.93
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
2.21
1.83
1.56
1.37
tLZ
tHZ
tZLS
5.51
4.58
3.90
3.42
tZHS
4.89
4.07
3.46
3.04
Units
ns
–F
2.82
2.35
2.00
1.75
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-43
ProASIC3E Flash Family FPGAs
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This
provides a differential amplifier input buffer and a push-pull output buffer.
Table 3-71 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
24 mA
–0.3
VREF-0.2 VREF+0.2
3.6
0.5
VCCI - 0.9 24
24
109
103
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class II
25
Test Point
25
30 pF
Figure 3-20 • AC Loading
Table 3-72 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF-0.2
Input High (V)
Measuring Point* (V)
1.5
VREF (Typ) (V)
1.5
VTT (Typ) (V) CLOAD (pF)
1.485 30
V
VREF+0.2
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-73 • SSTL3- Class II
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V, VREF = 1.5 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.48
2.06
1.76
1.54
tDIN
0.05
0.04
0.04
0.03
tPY
tEOUT
0.51
0.43
0.36
0.32
tZL
tZH
tLZ
tHZ
tZLS
5.21
4.34
3.69
3.24
tZHS
4.69
3.91
3.32
2.92
Units
ns
–F
1.50
1.25
1.06
0.93
2.53
2.10
1.79
1.57
2.01
1.67
1.42
1.25
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-44
Advanced v0.2
ProASIC3E Flash Family FPGAs
LVDS
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is
handled by the Actel Designer software when the user
instantiates a differential I/O macro in the design.
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a
high-speed, differential I/O standard. It requires that one
data bit is carried through two signal lines; so two pins
are needed. It also requires external resistor termination.
The full implementation of the LVDS transmitter and
receiver is shown in an example in Figure 3-21. The
building blocks of the LVDS transmitter-receiver are one
transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVPECL implementation,
because the output standard specifications are
different.
Differential I/Os can also be used in conjunction with the
embedded Input Register (InReg), Output Register
(OutReg), Enable Register (EnReg), and Double Data
Rate (DDR). However, there is no support for
bidirectional I/Os or tristates with these standards.
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
P
165 Ω
165 Ω
ZO = 50 Ω
INBUF_LVDS
+
-
140 Ω
ZO = 50 Ω
100 Ω
N
N
Figure 3-21 • LVDS Circuit Diagram and Board-Level Implementation
Table 3-74 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
2.375
0.9
Typ.
2.5
Max.
Units
2.625
1.25
1.6
V
V
VOL
Output Low Voltage
1.075
1.425
VOH
Output High Voltage
1.25
0
V
VI
Input Voltage
2.925
450
V
VODIFF
VOCM
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
250
350
1.25
1.25
350
mV
V
1.125
0.05
100
1.375
2.35
VICM
V
VIDIFF
mV
Notes:
1. +/- 5%
2. Differential input voltage = +/-350mV
Table 3-75 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
1.075
1.325
Cross point
–
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Advanced v0.2
3-45
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 3-76 • LVDS
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.52
2.10
1.78
1.57
tDIN
0.05
0.04
0.04
0.03
tPY
2.42
2.02
1.72
1.50
Units
–F
Std.
–1
ns
ns
ns
–2
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-46
Advanced v0.2
ProASIC3E Flash Family FPGAs
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is
another differential I/O standard. It requires that one
data bit is carried through two signal lines. Like LVDS,
two pins are needed. It also requires external resistor
termination.
building blocks of the LVPECL transmitter-receiver are
one transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVDS implementation,
because the output standard specifications are different.
The full implementation of the LVDS transmitter and
receiver is shown in an example in Figure 3-22. The
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
P
165 Ω
165 Ω
ZO = 50 Ω
140 Ω
ZO = 50 Ω
INBUF_LVDS
+
-
100 Ω
N
N
Figure 3-22 • LVPECL Circuit Diagram and Board-Level Implementation
Table 3-77 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
Max.
Min.
Max.
Min.
Max.
Units
3.0
3.3
3.6
V
V
VOL
Output Low Voltage
0.96
1.8
1.27
2.11
3.3
1.06
1.92
0
1.43
2.28
3.6
1.30
2.13
0
1.57
2.41
3.9
VOH
Output High Voltage
V
VIL, VIH
VODIFF
VOCM
Input Low, Input High voltages
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
0
V
0.625
1.762
1.01
300
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
V
V
VICM
V
VIDIFF
mV
Table 3-78 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
1.64
1.94
Cross point
–
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Timing Characteristics
Table 3-79 • LVPECL
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Speed Grade
tDOUT
0.72
0.60
0.51
0.45
tDP
2.57
2.14
1.82
1.60
tDIN
0.05
0.04
0.04
0.03
tPY
2.11
1.75
1.49
1.31
Units
ns
–F
Std.
–1
ns
ns
–2
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-47
ProASIC3E Flash Family FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Preset
L
X
X
D
DOUT
X
Data_out
PRE
DFN1E1P1
F
PRE
Y
Core
Array
E
X
Data
Enable
CLK
X
C
D
Q
X
D
Q
DFN1E1P1
G
X
E
X
E
X
B
EOUT
H
I
X
X
X
A
PRE
D
J
X
X
Q
DFN1E1P1
E
K
Data Input I/O Register with:
Active High Enable
Active High Preset
Postive Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive Edge Triggered
CLKBUF
INBUF
INBUF
Figure 3-23 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
3-48
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 3-80 • Parameter Definition and Measuring Nodes
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Measuring Nodes (From, To)*
Clock-to-Q of the Output Data Register
H, DOUT
F,H
Data Setup time for the Output Data Register
tOHD
Data Hold time for the Output Data Register
F,H
tOSUE
Enable Setup time for the Output Data Register
Enable Hold time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset removal time for the Output Data Register
Asynchronous Preset Recovery time for the Output Data Register
Clock-to-Q of the Output Enable Register
G,H
tOHE
G,H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
L,DOUT
L, H
L, H
H, EOUT
J, H
Data Setup time for the Output Enable Register
Data Hold time for the Output Enable Register
Enable Setup time for the Output Enable Register
Enable Hold time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal time for the Output Enable Register
Asynchronous Preset Recovery time for the Output Enable Register
Clock-to-Q of the Input Data Register
J, H
tOESUE
K, H
K, H
I, EOUT
I, H
tOEHE
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, H
A, E
tISUD
Data Setup time for the Input Data Register
C, A
C, A
B, A
tIHD
Data Hold time for the Input Data Register
tISUE
Enable Setup time for the Input Data Register
tIHE
Enable Hold time for the Input Data Register
B, A
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal time for the Input Data Register
Asynchronous Preset Recovery time for the Input Data Register
D, E
D, A
D, A
Note: *See Figure 3-23 on page 3-48 for more information.
Advanced v0.2
3-49
ProASIC3E Flash Family FPGAs
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
X
X
D
Q
Data
X
CC
X
EE
Array
DFN1E1C1
DFN1E1C1
GG
X
EOUT
E
X
E
X
BB
Enable
CLK
CLR
CLR
LL
X
HH
X
X
AA
JJ
X
D
Q
CLR
DD
DFN1E1C1
KK
E
X
CLR
Data Input I/O Register with
Active high enable
Active high clear
X
Positive edge triggered
Data Output Register and
Enable Output Register with
Active high enable
Active high clear
INBUF
INBUF
CLKBUF
Positive edge triggered
Figure 3-24 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
3-50
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 3-81 • Parameter Definition and Measuring Nodes
Parameter name
tOCLKQ
tOSUD
Parameter Definition
Measuring Nodes (From, To)*
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
Data Setup time for the Output Data Register
tOHD
Data Hold time for the Output Data Register
FF, HH
tOSUE
Enable Setup time for the Output Data Register
Enable Hold time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal time for the Output Data Register
Asynchronous Clear Recovery time for the Output Data Register
Clock-to-Q of the Output Enable Register
GG, HH
GG, HH
LL, DOUT
LL, HH
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
LL, HH
HH, EOUT
JJ, HH
Data Setup time for the Output Enable Register
Data Hold time for the Output Enable Register
Enable Setup time for the Output Enable Register
Enable Hold time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal time for the Output Enable Register
Asynchronous Clear Recovery time for the Output Enable Register
Clock-to-Q of the Input Data Register
JJ, HH
tOESUE
KK, HH
KK, HH
II, EOUT
II, HH
tOEHE
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup time for the Input Data Register
tIHD
Data Hold time for the Input Data Register
tISUE
Enable Setup time for the Input Data Register
tIHE
Enable Hold time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal time for the Input Data Register
Asynchronous Clear Recovery time for the Input Data Register
Note: *See Figure 3-24 on page 3-50 for more information.
Advanced v0.2
3-51
ProASIC3E Flash Family FPGAs
Input Register
tICKMPWH tICKMPWL
50%
tISUD
50%
50%
50%
50%
50%
50%
CLK
t
IHD
50%
50%
1
0
Data
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
50%
50%
50%
t
ISUE
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 3-25 • Input Register Timing Diagram
Timing Characteristics
Table 3-82 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tICLKQ
Description
–2
–1
Std.
0.84
0.57
0.00
0.57
0.00
0.76
0.60
0.00
0.10
0.00
0.10
0.33
–F
Units
Clock-to-Q of the Input Data Register
0.63
0.43
0.00
0.43
0.00
0.57
0.45
0.00
0.10
0.00
0.10
0.25
0.71
0.49
0.00
0.49
0.00
0.65
0.51
0.00
0.10
0.00
0.10
0.28
1.01
0.69
0.00
0.69
0.00
1.01
0.72
0.00
0.10
0.00
0.10
0.40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup time for the Input Data Register
tIHD
Data Hold time for the Input Data Register
tISUE
Enable Setup time for the Input Data Register
tIHE
Enable Hold time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal time for the Input Data Register
Asynchronous Clear Recovery time for the Input Data Register
Asynchronous Preset Removal time for the Input Data Register
Asynchronous Preset Recovery time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data
Register
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data
Register
0.25
0.28
0.33
0.40
ns
tICKMPWH
tICKMPWL
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
0.36
0.41
0.41
0.46
0.48
0.54
0.58
0.65
ns
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-52
Advanced v0.2
ProASIC3E Flash Family FPGAs
Output Register
t
t
OCKMPWL
OCKMPWH
50%
50%
50%
50%
50%
50%
50%
1
CLK
t
t
OHD
OSUD
50%
50%
0
Data_out
Enable
Preset
50%
t
t
ORECPRE
t
OWPRE
OREMPRE
t
OHE
50%
50%
50%
t
OSUE
t
t
OREMCLR
OWCLR
t
ORECCLR
50%
50%
50%
Clear
t
OPRE2Q
50%
50%
50%
DOUT
t
OCLR2Q
t
OCLKQ
Figure 3-26 • Output Register Timing Diagram
Timing Characteristics
Table 3-83 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tOCLKQ
Description
–2
–1
Std.
–F
Units
ns
Clock-to-Q of the Output Data Register
0.63
0.43
0.00
0.43
0.00
0.57
0.45
0.00
0.10
0.00
0.10
0.25
0.25
0.36
0.41
0.71
0.49
0.00
0.49
0.00
0.65
0.51
0.00
0.10
0.00
0.10
0.28
0.28
0.41
0.46
0.84
0.57
0.00
0.57
0.00
0.76
0.60
0.00
0.10
0.00
0.10
0.33
0.33
0.48
0.54
1.01
0.69
0.00
0.69
0.00
1.01
0.72
0.00
0.10
0.00
0.10
0.40
0.40
0.58
0.65
tOSUD
Data Setup time for the Output Data Register
ns
tOHD
Data Hold time for the Output Data Register
ns
tOSUE
Enable Setup time for the Output Data Register
ns
tOHE
Enable Hold time for the Output Data Register
ns
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal time for the Output Data Register
Asynchronous Clear Recovery time for the Output Data Register
Asynchronous Preset Removal time for the Output Data Register
Asynchronous Preset Recovery time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
ns
ns
ns
ns
ns
ns
ns
ns
tOCKMPWH
tOCKMPWL
ns
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-53
ProASIC3E Flash Family FPGAs
Output Enable Register
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOESUD tOEHD
50%
50%
0
1
D_Enable
Enable
Preset
50%
tOEWPRE
50%
tOEREMPRE
tOERECPRE
50%
50%
tOESUEOEHE
t
tOEREMCLR
50%
tOEWCLR tOERECCLR
50%
50%
Clear
EOUT
tOECLR2Q
50%
tOEPRE2Q
50%
50%
tOECLKQ
Figure 3-27 • Output Enable Register Timing Diagram
Timing Characteristics
Table 3-84 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tOECLKQ
Description
–2
–1
Std.
–F
Units
Clock-to-Q of the Output Enable Register
0.63 0.71 0.84 1.01
0.43 0.49 0.57 0.69
0.00 0.00 0.00 0.00
0.43 0.49 0.57 0.69
0.45 0.51 0.60 0.72
0.57 0.65 0.76 1.01
0.45 0.51 0.60 0.72
0.00 0.00 0.00 0.00
0.10 0.10 0.10 0.10
0.00 0.00 0.00 0.00
0.10 0.10 0.10 0.10
0.25 0.28 0.33 0.40
0.25 0.28 0.33 0.40
0.36 0.41 0.48 0.58
0.41 0.46 0.54 0.65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOESUD
Data Setup time for the Output Enable Register
tOEHD
Data Hold time for the Output Enable Register
tOESUE
Enable Setup time for the Output Enable Register
tOEHE
Enable Hold time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
tOECKMPWH
tOECKMPWL
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal time for the Output Enable Register
Asynchronous Clear Recovery time for the Output Enable Register
Asynchronous Preset Removal time for the Output Enable Register
Asynchronous Preset Recovery time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width High for the Output Enable Register
Clock Minimum Pulse Width Low for the Output Enable Register
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-54
Advanced v0.2
ProASIC3E Flash Family FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
INBUF
A
X
D
Out_QF
X
Data
(To core)
FF1
B
E
Out_QR
(To Core)
X
X
CLK
CLR
CLKBUF
INBUF
FF2
C
X
DDR_IN
Figure 3-28 • Input DDR Timing Model
Table 3-85 • Parameter Definitions
Parameter Name
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Parameter Definition
Measuring Nodes (From, To)
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup time of DDR input
Data Hold time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
B, D
B, E
A, B
A, B
C,D
C,E
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
C,B
C,B
Clear Recovery
Advanced v0.2
3-55
ProASIC3E Flash Family FPGAs
CLK
t
t
DDRISUD
6
DDRIHD
8
Data
CLR
1
2
3
4
5
7
9
t
DDRIRECCLR
t
DDRIREMCLR
t
DDRICLKQ1
t
t
DDRICLR2Q1
DDRICLR2Q2
Out_QF
Out_QR
6
2
4
t
DDRICLKQ2
7
3
5
Table 3-86 • Input DDR Timing Diagram
Timing Characteristics
Table 3-87 • Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Description
–2
–1
Std.
0.84
0.84
0.57
0.00
0.76
0.76
0.00
0.10
–F
Units
ns
Clock-to-Out Out_QR for Input DDR
0.63
0.63
0.43
0.00
0.57
0.57
0.00
0.10
0.71
0.71
0.49
0.00
0.65
0.65
0.00
0.10
1.01
0.91
0.86
0.00
0.91
0.91
0.00
0.00
Clock-to-Out Out_QF for Input DDR
ns
Data Setup for Input DDR
ns
tDDRIHD
Data Hold for Input DDR
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear to out Out_QR for Input DDR
Asynchronous Clear to out Out_QF for Input DDR
Asynchronous Clear Removal time for Input DDR
Asynchronous Clear Recovery time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-56
Advanced v0.2
ProASIC3E Flash Family FPGAs
Output DDR
A
Data_F
(From Core)
X
FF1
FF2
Out
B
C
D
0
1
X
X
X
CLK
E
CLKBUF
X
OUTBUF
Data_R
(From Core)
B
C
X
X
CLR
INBUF
DDR_OUT
Figure 3-29 • Output DDR Timing Model
Table 3-88 • Parameter Definitions
Parameter Name
Parameter Definition
Measuring Nodes (From, To)
tDDROCLKQ
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
tDDROSUD2
tDDROHD1
Clock-to-Out
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROHD2
Advanced v0.2
3-57
ProASIC3E Flash Family FPGAs
CLK
tDDROHD2
tDDROSUD2
3
4
9
5
Data_F
1
2
tDDROHD1
tDDROSUD1
Data_R 6
CLR
7
8
10
tDDRORECCLR
11
tDDROREMCLR
tDDROCLKQ
tDDROCLR2Q
Out
7
2
8
3
9
4
10
Figure 3-30 • Output DDR Timing Diagram
Timing Characteristics
Table 3-89 • Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
–2
–1
Std.
0.84
0.57
0.57
0.00
0.00
0.76
0.00
0.10
–F
Units
ns
Clock-to-Out of DDR for Output DDR
0.63
0.43
0.43
0.00
0.00
0.57
0.00
0.10
0.71
0.49
0.49
0.00
0.00
0.65
0.00
0.10
1.01
0.69
0.69
0.00
0.00
0.91
0.00
0.10
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear to out for Output DDR
Asynchronous Clear Removal time for Output DDR
Asynchronous Clear Recovery time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-58
Advanced v0.2
ProASIC3E Flash Family FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section timing characteristics are
presented for a sample of the library. For more details, refer to the ProASIC3/E Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 3-31 • Sample of Combinatorial Cells
Advanced v0.2
3-59
ProASIC3E Flash Family FPGAs
tPD
A
B
NAND2 OR
Any Combinatorial
Logic
Y
tPD= MAX(tPD(RR), tPD(RF)),
tPD(FF), tPD(FR)) where edges are
applicable for the particular
combinatorial cell
VCCA
50%
50%
VCCA
A, B, C
GND
50%
50%
OUT
GND
tPD
(FF)
tPD
(RR)
V
CCA
tPD
(FR)
OUT
50%
50%
tPD
(RF)
GND
Figure 3-32 • Timing Model and Waveforms
3-60
Advanced v0.2
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 3-90 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Combinatorial Cell
Equation
Y=!A
Parameter
–2
–1
Std.
0.53
0.62
0.62
0.63
0.63
0.96
0.90
1.14
0.65
0.73
–F
Units
ns
INV
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
0.40
0.46
0.46
0.47
0.47
0.72
0.67
0.85
0.49
0.54
0.45
0.52
0.52
0.54
0.54
0.82
0.76
0.97
0.56
0.62
0.64
0.74
0.74
0.76
0.76
1.15
1.08
1.37
0.79
0.87
AND2
NAND2
OR2
Y=A . B
ns
Y=!(A . B)
ns
Y=A + B
ns
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Y=!(A + B)
Y=A ⊕ B
Y=MAJ (A , B, C)
Y=A ⊕ B ⊕ C
Y=A !S + B S
Y=A . B . C
ns
ns
ns
ns
ns
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
VersaTile Specifications as a Sequential Module
The ProASIC3E library offers a wide variety of sequential cells including flip-flops and latches. Each have a data input
and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample
from the library. For more details, refer to the ProASIC3/E Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Out
Data
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 3-33 • Sample of Sequential Cells
Advanced v0.2
3-61
ProASIC3E Flash Family FPGAs
tCKMPWH tCKMPWL
50%
tSUD
50%
50%
50%
50%
50%
50%
CLK
tHD
50%
50%
Data
0
EN
tWPRE
50%
tRECPRE
50%
50%
tREMPRE
50%
tHE
PRE
CLR
Out
tSUE
tRECCLR
50%
tWCLR
50%
tREMCLR
50%
tPRE2Q
50%
tCLR2Q
50%
50%
tCLKQ
Figure 3-34 • Timing Model and Waveforms
Timing Characteristics
Table 3-91 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tCLKQ
Description
–2
–1
Std.
–F
Units
ns
Clock-to-Q of the Core Register
0.54
0.40
0.00
0.43
0.00
0.40
0.40
0.00
0.23
0.00
0.23
0.25
0.25
0.36
0.41
0.61
0.46
0.00
0.49
0.00
0.45
0.45
0.00
0.26
0.00
0.26
0.28
0.28
0.41
0.46
0.72
0.54
0.00
0.57
0.00
0.53
0.53
0.00
0.31
0.00
0.31
0.33
0.33
0.48
0.54
0.86
0.65
0.00
0.69
0.00
0.64
0.64
0.00
0.36
0.00
0.36
0.40
0.40
0.58
0.65
tSUD
Data Setup time for the Core Register
ns
tHD
Data Hold time for the Core Register
ns
tSUE
Enable Setup time for the Core Register
ns
tHE
Enable Hold time for the Core Register
ns
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal time for the Core Register
Asynchronous Clear Recovery time for the Core Register
Asynchronous Preset Removal time for the Core Register
Asynchronous Preset Recovery time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
ns
ns
ns
ns
ns
ns
ns
tWPRE
ns
tCKMPWH
tCKMPWL
ns
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-62
Advanced v0.2
ProASIC3E Flash Family FPGAs
Global Resource Characteristics
A3PE600 Clock Tree Topology
Clock delays are device-specific. Figure 3-35 is an example of a global tree used for clock routing. The global tree
presented in Figure 3-35 is driven by a CCC located on the west side of the A3PE600 device. It is used to drive all D-flip-
flops in the device.
Central
Global RIb
CCC
VersaTile
Rows
Global Spine
Figure 3-35 • Example of Global Tree Use in an A3PE600 Device for Clock Routing
Advanced v0.2
3-63
ProASIC3E Flash Family FPGAs
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input
buffer clock delays, as these are I/O standard dependent and the clock may be driven and conditioned internally by the
CCC module. For more details on clock conditioning capabilities, please refer to "Clock Conditioning Circuits" section
on page 2-12. Table 3-92, Table 3-93, and Table 3-94 on page 3-65 present minimum and maximum global clock delays
within the device. Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Table 3-92 • A3PE600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
–F
Parameter
tRCKL
Description
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
Input Low Delay for Global Clock
Input High Delay for Global Clock
0.91
0.95
1.27
1.31
1.04
1.08
1.44
1.49
1.22
1.27
1.70
1.76
1.48
1.52
2.23
2.30
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global
Clock
tRCKMPWL
Minimum Pulse Width Low for Global
Clock
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.36
0.41
0.49
0.78
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element ,located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Table 3-93 • A3PE1500 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
–F
Parameter
tRCKL
Description
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
Input Low Delay for Global Clock
Input High Delay for Global Clock
1.04
1.07
1.40
1.44
1.19
1.22
1.59
1.63
1.39
1.44
1.87
1.92
1.54
1.56
2.44
2.50
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global
Clock
tRCKMPWL
Minimum Pulse Width Low for Global
Clock
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.37
0.41
0.48
0.94
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-64
Advanced v0.2
ProASIC3E Flash Family FPGAs
Table 3-94 • A3PE3000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
–F
Parameter
tRCKL
Description
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units
Input Low Delay for Global Clock
Input High Delay for Global Clock
1.17
1.20
1.53
1.56
1.34
1.36
1.74
1.78
1.57
1.60
2.05
2.09
1.73
1.75
2.42
2.46
ns
ns
ns
tRCKH
tRCKMPWH Minimum Pulse Width High for Global
Clock
tRCKMPWL
Minimum Pulse Width Low for Global
Clock
ns
tRCKSW
FRMAX
Notes:
Maximum Skew for Global Clock
0.36
0.42
0.49
0.71
ns
Maximum Frequency for Global Clock
MHz
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly
loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-65
ProASIC3E Flash Family FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8
RADDR7
RD17
RD16
ADDRA11 DOUTA8
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
WEN
WCLK
RESET
RESET
Figure 3-36 • RAM Models
3-66
Advanced v0.2
ProASIC3E Flash Family FPGAs
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
BLK_B
WEN_B
DO
tBKS
tBKH
tENS
tENH
tCKQ1
Dn
D0
D1
D2
tDOH1
Figure 3-37 • RAM Read for Flow-Through Output
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
BLK_B
WEN_B
DO
tBKS
tBKH
tENH
tENS
tCKQ2
Dn
D0
D1
tDOH2
Figure 3-38 • RAM Read for Pipelined Output
Advanced v0.2
3-67
ProASIC3E Flash Family FPGAs
tCYC
tCKH
tAH
tCKL
CLK
tAS
A0
tBKS
A1
A2
ADD
BLK_B
WEN_B
DI
tBKH
tENS
tENH
tDS
tDH
DI1
DI0
Dn
D2
DO
Figure 3-39 • RAM Write, Output Retained (WMODE = 0)
t
CYC
t
t
CKL
CKH
CLK
ADD
t
t
AH
AS
A
A
A
2
0
1
t
BKS
t
BKH
BLK_B
WEN_B
DI
t
ENS
t
t
DH
DS
DI
DI
DI
2
0
1
DO
D
DI
DI
n
0
1
(flow-through)
DO
DI
D
DI
1
0
n
(Pipelined)
Figure 3-40 • RAM Write, Output as Write Data (WMODE = 1)
3-68
Advanced v0.2
ProASIC3E Flash Family FPGAs
CLK1
ADD1
DI1
tAS tAH
A0
A2
D2
A3
tDS tDH
D0
D3
tWRO
CLK2
ADD2
tAS
tAH
A0
A1
A4
tCKQ1
DO2
(flow-through)
Dn
D0
D1
tCKQ2
DO2
(Pipelined)
Dn
D0
Figure 3-41 • One Port Write/Other Port Read Same
tCYC
tCKH
tCKL
CLK
RESET_B
tRSTBQ
Dm
Dn
DO
Figure 3-42 • RAM Reset
Advanced v0.2
3-69
ProASIC3E Flash Family FPGAs
Timing Characteristics
Table 3-95 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tAS
Description
–2
–1
Std.
0.40
0.00
0.26
0.00
0.34
0.00
0.32
0.00
2.32
3.05
1.14
1.31
1.31
0.00
1.84
0.29
2.80
–F
Units
ns
Address Setup time
0.30
0.00
0.20
0.00
0.26
0.00
0.24
0.00
1.73
2.28
0.85
0.98
0.98
0.00
1.38
0.22
2.10
0.34
0.00
0.22
0.00
0.29
0.00
0.27
0.00
1.97
2.60
0.97
1.12
1.12
0.00
1.56
0.25
2.38
0.48
0.00
0.32
0.00
0.41
0.00
0.38
0.00
2.79
3.67
1.37
1.57
1.57
0.00
2.21
0.35
3.36
tAH
Address Hold time
ns
tENS
REN_B,WEN_B Setup time
REN_B, WEN_B Hold time
BLK_B Setup time
ns
tENH
ns
tBKS
ns
tBKH
BLK_B Hold time
ns
tDS
Input data (DI) Setup time
Input data (DI) Hold time
ns
tDH
ns
tCKQ1
Clock High to New Data Valid on DO (output retained, WMODE =0)
Clock High to New Data Valid on DO (flow-through, WMODE =1)
Clock HIGH to New Data Valid on DO (pipelined)
RESET_B Low to Data Out Low on DO (flow through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
ns
ns
tCKQ2
tRSTBQ
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
ns
Clock Cycle time
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Table 3-96 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tAS
Description
–2
–1
Std.
0.40
0.00
0.19
0.03
0.30
0.00
2.79
1.14
1.31
1.31
0.00
1.84
0.29
2.80
–F
Units
ns
Address Setup time
0.30
0.00
0.14
0.02
0.22
0.00
2.08
0.85
0.98
0.98
0.00
1.38
0.22
2.10
0.34
0.00
0.16
0.03
0.25
0.00
2.37
0.97
1.12
1.12
0.00
1.56
0.25
2.38
0.48
0.00
0.23
0.04
0.36
0.00
3.35
1.37
1.57
1.57
0.00
2.21
0.35
3.36
tAH
Address Hold time
ns
tENS
REN_B,WEN_B Setup time
REB_B, WEN_B Hold time
Input data (DI) Setup time
Input data (DI) Hold time
ns
tENH
ns
tDS
ns
tDH
ns
tCKQ1
tCKQ2
tRSTBQ
Clock High to New Data Valid on DO (output retained, WMODE =0)
Clock High to New Data Valid on DO (pipelined)
RESET_B Low to Data Out Low on DO (flow through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
ns
Clock Cycle time
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-70
Advanced v0.2
ProASIC3E Flash Family FPGAs
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 3-43 • FIFO Model
Advanced v0.2
3-71
ProASIC3E Flash Family FPGAs
Timing Waveforms
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET_B
EF
tRSTFG
tRSTAF
AEF
FF
tRSTFG
tRSTAF
AFF
WA/RA
(Address Counter)
MATCH (A0)
Figure 3-44 • FIFO Reset
tCYC
RCLK
EF
tRCKEF
tCKAF
AEF
WA/RA
(Address Counter)
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 3-45 • FIFO Reset, EMPTY Flag, and AEMPTY Flag
3-72
Advanced v0.2
ProASIC3E Flash Family FPGAs
tCYC
WCLK
FF
tWCKFF
tCKAF
AFF
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 3-46 • FIFO FULL and AFULL Flag
WCLK
MATCH
WA/RA
NO MATCH
NO MATCH
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(EMPTY)
(Address Counter)
1st rising
2nd rising
edge
edge
after 1st
write
after 1st
write
RCLK
EF
t
RCKEF
t
CKAF
AEF
Figure 3-47 • EMPTY Flag and AEMPTY Flag Deassertion
Advanced v0.2
3-73
ProASIC3E Flash Family FPGAs
RCLK
WA/RA
(Address Counter) MATCH (FULL)
NO MATCH
NO MATCH
NO MATCH
NO MATCH
Dist = AFF_TH - 1
1st rising
1st rising
edge
after 1st
read
edge
after 2nd
read
WCLK
FF
t WCKF
tCKAF
AFF
Figure 3-48 • FULL and AFULL Flag Deassertion
Timing Characteristics
Table 3-97 • FIFO
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std.
0.19
0.08
0.34
0.00
0.30
0.00
3.05
1.14
2.26
2.15
4.85
2.28
4.80
1.31
1.31
0.00
1.80
0.29
2.75
–F
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REN_B,WEN_B Setup time
0.14
0.06
0.25
0.00
0.22
0.00
2.28
0.85
1.69
1.61
3.62
1.71
3.58
0.98
0.98
0.00
1.35
0.21
2.06
0.16
0.07
0.29
0.00
0.25
0.00
2.60
0.97
1.92
1.83
4.12
1.94
4.08
1.12
1.12
0.00
1.53
0.24
2.33
0.23
0.10
0.40
0.00
0.36
0.00
3.67
1.37
2.71
2.58
5.82
2.74
5.77
1.57
1.57
0.00
2.17
0.34
3.29
tENH
REN_B, WEN_B Hold time
tBKS
BLK_B Setup time
tBKH
BLK_B Hold time
tDS
Input data (DI) Setup time
tDH
Input data (DI) Hold time
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on DO (flow-through)
Clock High to New Data Valid on DO (pipelined)
RCLK High to Empty flag Valid
WCLK High to Full flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET_B Low to Empty/Full flag valid
RESET_B Low to Almost-Empty/Full Flag Valid
RESET_B Low to Data out Low on DO (flow through)
RESET_B Low to Data out Low on DO (pipelined)
RESET_B Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle time
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3-74
Advanced v0.2
ProASIC3E Flash Family FPGAs
Embedded FROM Characteristics
tA
tA
A0
A1
ADDR
D0
D1
DO
Figure 3-49 • Timing Diagram
Timing Characteristics
Table 3-98 • Embedded FROM Access Time
Parameter
Description
–2
10
–1
Std.
Units
ta
Data Access Time
10
10
ns
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the
corresponding standard selected, refer to the I/O Timing characteristics for more details.
Timing Characteristics
Table 3-99 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tDISU
Description
Test Data Input Setup Time
–2
–1
Std.
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (Data Out)
ns
tTMSSU
ns
tTMDHD
tTCK2Q
ns
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (Data Out)
ns
TCK maximum frequency
ResetB Removal time
20/40
20/40
20/40
MHz
ns
ResetB Recovery time
ns
ResetB minimum pulse
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Advanced v0.2
3-75
ProASIC3E Flash Family FPGAs
Package Pin Assignments
208-Pin PQFP
208
1
208-Pin PQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
Advanced v0.2
4-1
ProASIC3E Flash Family FPGAs
208-Pin PQFP*
208-Pin PQFP*
208-Pin PQFP*
Pin Number
A3PE600 Function
GND
Pin Number
A3PE600 Function
Pin Number
A3PE600 Function
IO83NPB5V0
IO82NPB5V0
IO83PPB5V0
IO82PPB5V0
GND
1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
IO108PSB6V0
77
78
2
GNDQ
VCCIB6
3
VMV7
GND
79
4
GAB2/IO133PSB7V1
GAA2/IO134PDB7V1
IO134NDB7V1
GAC2/IO132PDB7V1
IO132NDB7V1
IO130PDB7V1
IO130NDB7V1
IO127PDB7V1
IO127NDB7V1
IO126PDB7V0
IO126NDB7V0
IO124PSB7V0
VCC
IO106PDB6V0
IO106NDB6V0
GEC1/IO104PDB6V0
GEC0/IO104NDB6V0
GEB1/IO103PPB6V0
GEA1/IO102PPB6V0
GEB0/IO103NPB6V0
GEA0/IO102NPB6V0
VMV6
80
5
81
6
82
IO80NDB4V1
IO80PDB4V1
IO79NPB4V1
IO78NPB4V1
IO79PPB4V1
IO78PPB4V1
VCC
7
83
8
84
9
85
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
86
87
88
GNDQ
89
VCCIB4
GND
90
IO76NDB4V1
IO76PDB4V1
IO72NDB4V0
IO72PDB4V0
IO70NDB4V0
GDC2/IO70PDB4V0
IO68NDB4V0
GND
VMV5
91
GNDQ
92
GND
IO101NDB5V2
GEA2/IO101PDB5V2
IO100NDB5V2
GEB2/IO100PDB5V2
IO99NDB5V2
93
VCCIB7
94
IO122PPB7V0
IO121PSB7V0
IO122NPB7V0
GFC1/IO120PSB7V0
GFB1/IO119PDB7V0
GFB0/IO119NDB7V0
VCOMPLF
95
96
97
GEC2/IO99PDB5V2
IO98PSB5V2
98
GDA2/IO68PDB4V0
GDB2/IO69PSB4V0
GNDQ
99
VCCIB5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
IO96PSB5V2
IO94NDB5V1
GND
TCK
GFA0/IO118NPB6V1
VCCPLF
TDI
TMS
GFA1/IO118PPB6V1
GND
IO94PDB5V1
IO92NDB5V1
IO92PDB5V1
IO88NDB5V0
IO88PDB5V0
VCC
VMV4
GND
GFA2/IO117PDB6V1
IO117NDB6V1
GFB2/IO116PPB6V1
GFC2/IO115PPB6V1
IO116NPB6V1
IO115NPB6V1
VCC
VPUMP
GNDQ
TDO
TRST
VCCIB5
VJTAG
IO85NPB5V0
IO84NPB5V0
IO85PPB5V0
IO84PPB5V0
VMV3
GDA0/IO67NPB3V1
GDB0/IO66NPB3V1
GDA1/IO67PPB3V1
IO112PDB6V1
IO112NDB6V1
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
4-2
Advanced v0.2
ProASIC3E Flash Family FPGAs
208-Pin PQFP*
208-Pin PQFP*
208-Pin PQFP*
Pin Number
A3PE600 Function
GDB1/IO66PPB3V1
GDC0/IO65NDB3V1
GDC1/IO65PDB3V1
IO62NDB3V1
Pin Number
A3PE600 Function
GBB2/IO37PSB2V0
VMV2
Pin Number
A3PE600 Function
IO13NDB0V2
IO11PSB0V1
IO09PDB0V1
IO09NDB0V1
GND
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GNDQ
GND
IO62PDB3V1
VMV1
IO58NDB3V0
GNDQ
IO07PDB0V1
IO07NDB0V1
IO05PDB0V0
IO05NDB0V0
IO58PDB3V0
GBA1/IO35PDB1V1
GBA0/IO35NDB1V1
GBB1/IO34PDB1V1
GND
GND
VCCIB3
GCC2/IO55PSB3V0
GCB2/IO54PSB3V0
NC
VCCIB0
GBB0/IO34NDB1V1
GBC1/IO33PDB1V1
GBC0/IO33NDB1V1
IO31PDB1V1
IO31NDB1V1
IO27PDB1V0
IO27NDB1V0
GAC1/IO02PDB0V0
GAC0/IO02NDB0V0
GAB1/IO01PDB0V0
GAB0/IO01NDB0V0
GAA1/IO00PDB0V0
GAA0/IO00NDB0V0
GNDQ
IO53NDB3V0
GCA2/IO53PDB3V0
GCA1/IO52PPB3V0
GND
VCCPLC
GCA0/IO52NPB3V0
VCOMPLC
VCCIB1
VMV0
VCC
GCB0/IO51NDB2V1
GCB1/IO51PDB2V1
GCC1/IO50PSB2V1
IO49NDB2V1
IO49PDB2V1
IO23PPB1V0
IO22PSB1V0
IO23NPB1V0
IO21PDB1V0
IO21NDB1V0
IO19PPB0V2
GND
IO48PSB2V1
VCCIB2
GND
IO18PPB0V2
IO19NPB0V2
IO18NPB0V2
IO17PPB0V2
IO16PPB0V2
IO17NPB0V2
IO16NPB0V2
VCC
IO47NDB2V1
IO47PDB2V1
IO44NDB2V1
IO44PDB2V1
IO43NDB2V0
IO43PDB2V0
IO40NDB2V0
IO40PDB2V0
GBC2/IO38PSB2V0
GBA2/IO36PSB2V0
VCCIB0
VCC
IO15PDB0V2
IO15NDB0V2
IO13PDB0V2
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
Advanced v0.2
4-3
ProASIC3E Flash Family FPGAs
208-Pin PQFP*
208-Pin PQFP*
208-Pin PQFP*
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
1
GND
GNDQ
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
IO176PSB6V1
CCIB6
77
78
IO138NDB5V0
IO138PDB5V0
IO135NDB5V0
IO135PDB5V0
GND
2
V
3
VMV7
GND
79
4
GAB2/IO213PSB7V3
GAA2/IO214PDB7V3
IO214NDB7V3
GAC2/IO212PDB7V3
IO212NDB7V3
IO210PDB7V3
IO210NDB7V3
IO208PDB7V2
IO208NDB7V2
IO204PDB7V2
IO204NDB7V2
IO200PSB7V1
VCC
IO172PDB6V1
IO172NDB6V1
GEC1/IO165PDB6V0
GEC0/IO165NDB6V0
GEB1/IO164PPB6V0
GEA1/IO163PPB6V0
GEB0/IO164NPB6V0
GEA0/IO163NPB6V0
VMV6
80
5
81
6
82
IO123NDB4V3
IO123PDB4V3
IO122NDB4V2
IO122PDB4V2
IO119NDB4V2
IO119PDB4V2
VCC
7
83
8
84
9
85
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
86
87
88
GNDQ
89
VCCIB4
GND
90
IO115NDB4V2
IO115PDB4V2
IO111NDB4V1
IO111PDB4V1
IO109NDB4V1
GDC2/IO109PDB4V1
IO108NDB4V0
GND
VMV5
91
GNDQ
92
GND
IO162NDB5V3
GEA2/IO162PDB5V3
IO161NDB5V3
GEB2/IO161PDB5V3
IO160NDB5V3
GEC2/IO160PDB5V3
IO159PSB5V3
93
V
CCIB7
94
IO196PDB7V1
IO196NDB7V1
IO193PSB7V0
GFC1/IO188PSB7V0
GFB1/IO187PDB7V0
GFB0/IO187NDB7V0
VCOMPLF
95
96
97
98
GDB2/IO108PDB4V0
GDA2/IO107PSB4V0
GNDQ
99
V
CCIB5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
IO157PSB5V3
IO153NDB5V2
GND
TCK
GFA0/IO186NPB6V2
VCCPLF
TDI
TMS
GFA1/IO186PPB6V2
GND
IO153PDB5V2
IO149NDB5V2
IO149PDB5V2
IO145NDB5V1
IO145PDB5V1
VCC
VMV4
GND
GFA2/IO185PDB6V2
IO185NDB6V2
GFB2/IO184PPB6V2
GFC2/IO183PPB6V2
IO184NPB6V2
IO183NPB6V2
VCC
VPUMP
GNDQ
TDO
TRST
VCCIB5
VJTAG
IO141NDB5V1
IO141PDB5V1
IO140NDB5V1
IO140PDB5V1
VMV3
GDA0/IO106NPB3V2
GDB0/IO105NPB3V2
GDA1/IO106PPB3V2
IO180PDB6V2
IO180NDB6V2
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
4-4
Advanced v0.2
ProASIC3E Flash Family FPGAs
208-Pin PQFP*
208-Pin PQFP*
208-Pin PQFP*
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
Pin Number A3PE1500 Function
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
GDB1/IO105PPB3V2
GDC0/IO104NDB3V2
GDC1/IO104PDB3V2
IO101NDB3V2
IO101PDB3V2
IO97NDB3V1
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
GBB2/IO59PSB2V0
VMV2
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO15NDB0V1
IO12PSB0V1
IO11PDB0V1
IO11NDB0V1
GND
GNDQ
GND
VMV1
GNDQ
IO08PDB0V1
IO08NDB0V1
IO05PDB0V0
IO05NDB0V0
IO97PDB3V1
GBA1/IO57PDB1V3
GBA0/IO57NDB1V3
GBB1/IO56PDB1V3
GND
GND
V
CCIB3
GCC2/IO86PSB3V0
GCB2/IO85PSB3V0
NC
VCCIB0
GBB0/IO56NDB1V3
GBC1/IO55PDB1V3
GBC0/IO55NDB1V3
IO51PDB1V2
IO51NDB1V2
IO47PDB1V1
IO47NDB1V1
GAC1/IO02PDB0V0
GAC0/IO02NDB0V0
GAB1/IO01PDB0V0
GAB0/IO01NDB0V0
GAA1/IO00PDB0V0
GAA0/IO00NDB0V0
GNDQ
IO84NDB3V0
GCA2/IO84PDB3V0
GCA1/IO83PPB3V0
GND
VCCPLC
GCA0/IO83NPB3V0
VCOMPLC
V
CCIB1
VCC
VMV0
GCB0/IO82NDB2V3
GCB1/IO82PDB2V3
GCC1/IO81PSB2V3
IO79NDB2V3
IO79PDB2V3
IO42PSB1V1
IO41PDB1V1
IO41NDB1V1
IO38PDB1V0
IO38NDB1V0
IO31PDB0V3
GND
IO77PSB2V3
V
CCIB2
GND
IO31NDB0V3
IO28PDB0V3
IO28NDB0V3
IO26PDB0V3
IO26NDB0V3
IO23PDB0V2
IO23NDB0V2
VCC
IO70NDB2V2
IO70PDB2V2
IO67NDB2V2
IO67PDB2V2
IO66NDB2V1
IO66PDB2V1
IO63NDB2V1
IO63PDB2V1
GBC2/IO60PSB2V0
GBA2/IO58PSB2V0
V
CCIB0
VCC
IO18PDB0V2
IO18NDB0V2
IO15PDB0V1
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
Advanced v0.2
4-5
ProASIC3E Flash Family FPGAs
208-Pin PQFP*
208-Pin PQFP*
208-Pin PQFP*
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
1
GND
GNDQ
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
IO250NDB6V2
IO246PSB6V1
76
77
IO196PDB5V0
IO195NDB5V0
IO195PDB5V0
IO192NDB5V0
IO192PDB5V0
GND
2
3
VMV7
V
CCIB6
78
4
GAB2/IO303PSB7V3
GAA2/IO304PDB7V3
IO304NDB7V3
GAC2/IO302PDB7V3
IO302NDB7V3
IO298PDB7V3
IO298NDB7V3
IO294PDB7V2
IO294NDB7V2
IO290PDB7V2
IO290NDB7V2
IO286PSB7V1
VCC
GND
79
5
IO242PDB6V1
IO242NDB6V1
GEC1/IO234PPB6V0
GEB1/IO233PPB6V0
GEC0/IO234NPB6V0
GEB0/IO233NPB6V0
GEA1/IO232PDB6V0
GEA0/IO232NDB6V0
VMV6
80
6
81
7
82
IO182NDB4V3
IO182PDB4V3
IO178NDB4V3
IO178PDB4V3
IO174NDB4V2
IO174PDB4V2
VCC
8
83
9
84
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
36
37
85
86
87
88
GNDQ
89
VCCIB4
GND
90
IO168NDB4V2
IO168PDB4V2
IO164NDB4V1
IO164PDB4V1
IO154NDB4V0
GDC2/IO154PDB4V0
IO153NDB4V0
GND
VMV5
91
GND
GNDQ
92
V
CCIB7
IO231NDB5V4
GEA2/IO231PDB5V4
IO230NDB5V4
GEB2/IO230PDB5V4
IO229NDB5V4
GEC2/IO229PDB5V4
IO228PSB5V4
93
IO282PDB7V1
IO282NDB7V1
IO278PSB7V0
GFC1/IO274PSB7V0
GFB1/IO273PDB7V0
GFB0/IO273NDB7V0
VCOMPLF
94
95
96
97
98
GDB2/IO153PDB4V0
GDA2/IO152PSB4V0
GNDQ
99
V
CCIB5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
GFA0/IO272NPB6V4
VCCPLF
IO216NDB5V3
IO216PDB5V3
GND
TCK
TDI
GFA1/IO272PPB6V4
GND
TMS
IO212PSB5V2
IO210NDB5V2
IO210PDB5V2
IO206NDB5V1
IO206PDB5V1
VCC
VMV4
GFA2/IO271PDB6V4
IO271NDB6V4
GFB2/IO270PPB6V4
GFC2/IO269PPB6V4
IO270NPB6V4
IO269NPB6V4
VCC
GND
VPUMP
GNDQ
TDO
TRST
VCCIB5
VJTAG
IO200NDB5V1
IO200PDB5V1
IO196NDB5V0
VMV3
VCC
GDA0/IO151NPB3V4
GDB0/IO150NPB3V4
IO250PDB6V2
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
4-6
Advanced v0.2
ProASIC3E Flash Family FPGAs
208-Pin PQFP*
208-Pin PQFP*
208-Pin PQFP*
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
Pin Number A3PE3000 Function
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
GDA1/IO151PPB3V4
GDB1/IO150PPB3V4
GDC0/IO149NDB3V4
GDC1/IO149PDB3V4
IO146NDB3V4
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
GBA2/IO82PSB2V0
GBB2/IO83PSB2V0
VMV2
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO24PDB0V2
IO24NDB0V2
IO21PSB0V2
IO16PDB0V1
IO16NDB0V1
GND
GNDQ
GND
IO146PDB3V4
VMV1
IO142NDB3V3
GNDQ
IO11PDB0V1
IO11NDB0V1
IO08PDB0V0
IO08NDB0V0
IO142PDB3V3
GBA1/IO81PDB1V4
GBA0/IO81NDB1V4
GBB1/IO80PDB1V4
GND
GND
V
CCIB3
GCC2/IO117PSB3V0
GCB2/IO116PSB3V0
NC
VCCIB0
GBB0/IO80NDB1V4
GBC1/IO79PDB1V4
GBC0/IO79NDB1V4
IO74PDB1V4
IO74NDB1V4
IO70PDB1V3
IO70NDB1V3
GAC1/IO02PDB0V0
GAC0/IO02NDB0V0
GAB1/IO01PDB0V0
GAB0/IO01NDB0V0
GAA1/IO00PDB0V0
GAA0/IO00NDB0V0
GNDQ
IO115NDB3V0
GCA2/IO115PDB3V0
GCA1/IO114PPB3V0
GND
VCCPLC
GCA0/IO114NPB3V0
VCOMPLC
V
CCIB1
VCC
VMV0
GCB0/IO113NDB2V3
GCB1/IO113PDB2V3
GCC1/IO112PSB2V3
IO110NDB2V3
IO110PDB2V3
IO106PSB2V3
IO67PSB1V3
IO66PDB1V3
IO66NDB1V3
IO63PDB1V2
IO63NDB1V2
IO40PDB0V4
GND
V
CCIB2
GND
VCC
IO40NDB0V4
IO37PDB0V4
IO37NDB0V4
IO35PDB0V4
IO35NDB0V4
IO32PDB0V3
IO32NDB0V3
IO99NDB2V2
IO99PDB2V2
IO96NDB2V1
IO96PDB2V1
IO91NDB2V1
IO91PDB2V1
IO88NDB2V0
IO88PDB2V0
GBC2/IO84PSB2V0
V
CCIB0
VCC
IO28PDB0V3
IO28NDB0V3
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
Advanced v0.2
4-7
ProASIC3E Flash Family FPGAs
256-Pin FBGA
A1 Ball Pad Corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
4-8
Advanced v0.2
ProASIC3E Flash Family FPGAs
256-Pin FBGA*
256-Pin FBGA*
256-Pin FBGA*
Pin Number
Pin Number
A3PE600 Function
GND
A3PE600 Function
GAC1/IO02PDB0V0
IO15NDB0V2
IO15PDB0V2
IO20PDB1V0
IO25NDB1V0
IO27PDB1V0
GBC0/IO33NDB1V1
VCCPLB
Pin Number
A3PE600 Function
VCCIB1
A1
A2
C6
C7
E11
E12
E13
E14
E15
E16
F1
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
GAB0/IO01NDB0V0
IO05PDB0V0
VMV1
A3
C8
GBC2/IO38PDB2V0
IO37NDB2V0
IO41NDB2V0
IO41PDB2V0
IO124PDB7V0
IO125PDB7V0
IO126PDB7V0
IO130NDB7V1
VCCIB7
A4
C9
A5
C10
C11
C12
C13
C14
C15
C16
D1
A6
IO10PDB0V1
A7
IO12PDB0V2
A8
IO16NDB0V2
IO23NDB1V0
IO23PDB1V0
F2
A9
VMV2
F3
A10
A11
A12
A13
A14
A15
A16
B1
IO36NDB2V0
IO42PDB2V0
IO128PDB7V1
IO129PDB7V1
GAC2/IO132PDB7V1
VCOMPLA
F4
IO28NDB1V1
IO28PDB1V1
F5
F6
GND
GBB1/IO34PDB1V1
GBA0/IO35NDB1V1
GBA1/IO35PDB1V1
GND
D2
F7
VCC
D3
F8
VCC
D4
F9
VCC
D5
GNDQ
F10
F11
F12
F13
F14
F15
F16
G1
VCC
GAB2/IO133PDB7V1
GAA2/IO134PDB7V1
GNDQ
D6
IO09NDB0V1
IO09PDB0V1
IO13PDB0V2
IO21PDB1V0
IO25PDB1V0
IO27NDB1V0
GNDQ
GND
B2
D7
VCCIB2
B3
D8
IO38NDB2V0
IO40NDB2V0
IO40PDB2V0
IO45PSB2V1
IO124NDB7V0
IO125NDB7V0
IO126NDB7V0
GFC1/IO120PPB7V0
VCCIB7
B4
GAB1/IO01PDB0V0
IO05NDB0V0
IO10NDB0V1
IO12NDB0V2
IO16PDB0V2
D9
B5
D10
D11
D12
D13
D14
D15
D16
E1
B6
B7
B8
VCOMPLB
G2
B9
IO20NDB1V0
IO24NDB1V0
IO24PDB1V0
GBB2/IO37PDB2V0
IO39PDB2V0
IO39NDB2V0
IO128NDB7V1
IO129NDB7V1
IO132NDB7V1
IO130PDB7V1
VMV0
G3
B10
B11
B12
B13
B14
B15
B16
C1
G4
G5
GBC1/IO33PDB1V1
GBB0/IO34NDB1V1
GNDQ
G6
VCC
E2
G7
GND
E3
G8
GND
GBA2/IO36PDB2V0
IO42NDB2V0
IO133NDB7V1
IO134NDB7V1
VMV7
E4
G9
GND
E5
G10
G11
G12
G13
G14
G15
GND
E6
VCCIB0
VCC
C2
E7
VCCIB0
VCCIB2
C3
E8
IO13NDB0V2
IO21NDB1V0
VCCIB1
GCC1/IO50PPB2V1
IO44NDB2V1
IO44PDB2V1
C4
VCCPLA
E9
C5
GAC0/IO02NDB0V0
E10
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
Advanced v0.2
4-9
ProASIC3E Flash Family FPGAs
256-Pin FBGA*
256-Pin FBGA*
256-Pin FBGA*
Pin Number
G16
H1
A3PE600 Function
IO49NSB2V1
GFB0/IO119NPB7V0
GFA0/IO118NDB6V1
GFB1/IO119PPB7V0
VCOMPLF
Pin Number
A3PE600 Function
VCCIB6
Pin Number
A3PE600 Function
VCCIB4
K5
K6
M10
M11
M12
M13
M14
M15
M16
N1
VCC
VCCIB4
H2
K7
GND
VMV3
H3
K8
GND
VCCPLD
H4
K9
GND
GDB1/IO66PPB3V1
GDC1/IO65PDB3V1
IO61NDB3V1
IO105PDB6V0
IO105NDB6V0
GEC1/IO104PPB6V0
VCOMPLE
H5
GFC0/IO120NPB7V0
VCC
K10
K11
K12
K13
K14
K15
K16
L1
GND
H6
VCC
H7
GND
VCCIB3
H8
GND
IO54NPB3V0
IO57NPB3V0
IO55NPB3V0
IO57PPB3V0
IO113NPB6V1
IO109PPB6V0
IO108PDB6V0
IO108NDB6V0
VCCIB6
N2
H9
GND
N3
H10
H11
H12
H13
H14
H15
H16
J1
GND
N4
VCC
N5
GNDQ
GCC0/IO50NPB2V1
GCB1/IO51PPB2V1
GCA0/IO52NPB3V0
VCOMPLC
N6
GEA2/IO101PPB5V2
IO92NDB5V1
IO90NDB5V1
IO82NDB5V0
IO74NDB4V1
IO74PDB4V1
GNDQ
L2
N7
L3
N8
L4
N9
GCB0/IO51NPB2V1
GFA2/IO117PSB6V1
GFA1/IO118PDB6V1
VCCPLF
L5
N10
N11
N12
N13
N14
N15
N16
P1
L6
GND
J2
L7
VCC
J3
L8
VCC
VCOMPLD
J4
IO116NDB6V1
GFB2/IO116PDB6V1
VCC
L9
VCC
VJTAG
J5
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
VCC
GDC0/IO65NDB3V1
GDA1/IO67PDB3V1
GEB1/IO103PDB6V0
GEB0/IO103NDB6V0
VMV6
J6
GND
J7
GND
VCCIB3
J8
GND
GDB0/IO66NPB3V1
IO60NDB3V1
IO60PDB3V1
IO61PDB3V1
IO109NPB6V0
IO106NDB6V0
IO106PDB6V0
GEC0/IO104NPB6V0
VMV5
P2
J9
GND
P3
J10
J11
J12
J13
J14
J15
J16
K1
GND
P4
VCCPLE
VCC
P5
IO101NPB5V2
IO95PPB5V1
IO92PDB5V1
IO90PDB5V1
IO82PDB5V0
IO76NDB4V1
IO76PDB4V1
VMV4
GCB2/IO54PPB3V0
GCA1/IO52PPB3V0
GCC2/IO55PPB3V0
VCCPLC
P6
P7
P8
P9
GCA2/IO53PSB3V0
GFC2/IO115PSB6V1
IO113PPB6V1
IO112PDB6V1
IO112NDB6V1
P10
P11
P12
P13
P14
VCCIB5
K2
VCCIB5
K3
IO84NDB5V0
IO84PDB5V0
TCK
K4
VPUMP
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
4-10
Advanced v0.2
ProASIC3E Flash Family FPGAs
256-Pin FBGA*
Pin Number
A3PE600 Function
TRST
P15
P16
R1
GDA0/IO67NDB3V1
GEA1/IO102PDB6V0
GEA0/IO102NDB6V0
GNDQ
R2
R3
R4
GEC2/IO99PDB5V2
IO95NPB5V1
IO91NDB5V1
IO91PDB5V1
IO83NDB5V0
IO83PDB5V0
IO77NDB4V1
IO77PDB4V1
IO69NDB4V0
GDB2/IO69PDB4V0
TDI
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
T1
GNDQ
TDO
GND
T2
IO100NDB5V2
GEB2/IO100PDB5V2
IO99NDB5V2
IO88NDB5V0
IO88PDB5V0
IO89NSB5V0
IO80NSB4V1
IO81NDB4V1
IO81PDB4V1
IO70NDB4V0
GDC2/IO70PDB4V0
IO68NDB4V0
GDA2/IO68PDB4V0
TMS
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
GND
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
Advanced v0.2
4-11
ProASIC3E Flash Family FPGAs
484-Pin FBGA
A1 Ball Pad Corner
2221 201918 171615 1413 121110 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
4-12
Advanced v0.2
ProASIC3E Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
484-Pin FBGA*
Pin Number
A3PE600 Function
GND
Pin Number
A3PE600 Function
Pin Number
A3PE600 Function
GAB0/IO01NDB0V0
IO05PDB0V0
IO10PDB0V1
IO12PDB0V2
IO16NDB0V2
IO23NDB1V0
IO23PDB1V0
IO28NDB1V1
IO28PDB1V1
GBB1/IO34PDB1V1
GBA0/IO35NDB1V1
GBA1/IO35PDB1V1
GND
A1
A2
B15
B16
B17
B18
B19
B20
B21
B22
C1
NC
IO30NDB1V1
IO30PDB1V1
IO32PDB1V1
NC
D7
D8
GND
A3
VCCIB0
D9
A4
IO06NDB0V1
IO06PDB0V1
IO08NDB0V1
IO08PDB0V1
IO11PDB0V1
IO17PDB0V2
IO18NDB0V2
IO18PDB0V2
IO22PDB1V0
IO26PDB1V0
IO29NDB1V1
IO29PDB1V1
IO31NDB1V1
IO31PDB1V1
IO32NDB1V1
NC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
A5
A6
NC
A7
VCCIB2
A8
GND
A9
VCCIB7
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B1
C2
NC
C3
NC
C4
NC
C5
GND
C6
IO04NDB0V0
NC
C7
IO04PDB0V0
NC
C8
VCC
NC
C9
VCC
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D1
IO14NDB0V2
E2
NC
IO19NDB0V2
E3
GND
VCCIB1
NC
E4
GAB2/IO133PDB7V1
GAA2/IO134PDB7V1
GNDQ
GND
NC
E5
GND
VCC
E6
GND
VCC
E7
GAB1/IO01PDB0V0
IO05NDB0V0
IO10NDB0V1
IO12NDB0V2
IO16PDB0V2
IO20NDB1V0
IO24NDB1V0
IO24PDB1V0
GBC1/IO33PDB1V1
GBB0/IO34NDB1V1
GNDQ
B2
VCCIB7
NC
E8
B3
NC
NC
E9
B4
IO03NDB0V0
IO03PDB0V0
IO07NDB0V1
IO07PDB0V1
IO11NDB0V1
IO17NDB0V2
IO14PDB0V2
IO19PDB0V2
IO22NDB1V0
IO26NDB1V0
NC
GND
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
B5
NC
B6
NC
B7
NC
B8
VCCIB2
B9
NC
B10
B11
B12
B13
B14
D2
NC
NC
D3
D4
GND
GBA2/IO36PDB2V0
IO42NDB2V0
GND
D5
GAA0/IO00NDB0V0
GAA1/IO00PDB0V0
D6
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
Advanced v0.2
4-13
ProASIC3E Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
484-Pin FBGA*
Pin Number
E21
E22
F1
A3PE600 Function
NC
Pin Number
A3PE600 Function
IO25PDB1V0
IO27NDB1V0
GNDQ
Pin Number
A3PE600 Function
IO125PDB7V0
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
J5
J6
NC
IO126PDB7V0
NC
J7
IO130NDB7V1
F2
IO131NDB7V1
IO131PDB7V1
IO133NDB7V1
IO134NDB7V1
VMV7
VCOMPLB
J8
VCCIB7
F3
GBB2/IO37PDB2V0
IO39PDB2V0
IO39NDB2V0
IO43PDB2V0
IO43NDB2V0
NC
J9
GND
VCC
F4
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
F5
VCC
F6
VCC
F7
VCCPLA
VCC
F8
GAC0/IO02NDB0V0
GAC1/IO02PDB0V0
IO15NDB0V2
IO15PDB0V2
IO20PDB1V0
IO25NDB1V0
IO27PDB1V0
GBC0/IO33NDB1V1
VCCPLB
GND
F9
NC
VCCIB2
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
H2
NC
IO38NDB2V0
IO40NDB2V0
IO40PDB2V0
IO45PDB2V1
NC
H3
VCC
H4
IO128NDB7V1
IO129NDB7V1
IO132NDB7V1
IO130PDB7V1
VMV0
H5
H6
H7
IO48PDB2V1
IO46PDB2V1
IO121NDB7V0
IO121PDB7V0
NC
H8
VMV2
H9
VCCIB0
IO36NDB2V0
IO42PDB2V0
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
VCCIB0
K2
IO13NDB0V2
IO21NDB1V0
VCCIB1
K3
K4
IO124NDB7V0
IO125NDB7V0
IO126NDB7V0
GFC1/IO120PPB7V0
VCCIB7
NC
K5
NC
VCCIB1
K6
IO127NDB7V1
IO127PDB7V1
NC
VMV1
K7
G2
GBC2/IO38PDB2V0
IO37NDB2V0
IO41NDB2V0
IO41PDB2V0
VCC
K8
G3
K9
VCC
G4
IO128PDB7V1
IO129PDB7V1
GAC2/IO132PDB7V1
VCOMPLA
K10
K11
K12
K13
K14
K15
K16
K17
K18
GND
G5
GND
G6
GND
G7
NC
GND
G8
GNDQ
NC
VCC
G9
IO09NDB0V1
IO09PDB0V1
IO13PDB0V2
IO21PDB1V0
IO123NDB7V0
IO123PDB7V0
NC
VCCIB2
G10
G11
G12
J2
GCC1/IO50PPB2V1
IO44NDB2V1
IO44PDB2V1
J3
J4
IO124PDB7V0
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
4-14
Advanced v0.2
ProASIC3E Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
484-Pin FBGA*
Pin Number
A3PE600 Function
IO49NPB2V1
IO45NDB2V1
IO48NDB2V1
IO46NDB2V1
NC
Pin Number
A3PE600 Function
GND
Pin Number
A3PE600 Function
IO115NDB6V1
IO113NPB6V1
IO109PPB6V0
IO108PDB6V0
IO108NDB6V0
VCCIB6
K19
K20
K21
K22
L1
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
P3
P4
GND
GND
P5
VCC
P6
GCB2/IO54PPB3V0
GCA1/IO52PPB3V0
GCC2/IO55PPB3V0
VCCPLC
P7
L2
IO122PDB7V0
IO122NDB7V0
GFB0/IO119NPB7V0
GFA0/IO118NDB6V1
GFB1/IO119PPB7V0
VCOMPLF
P8
L3
P9
GND
L4
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
L5
GCA2/IO53PDB3V0
IO53NDB3V0
IO56PDB3V0
NC
VCC
L6
VCC
L7
VCC
L8
GFC0/IO120NPB7V0
VCC
GND
L9
IO114PDB6V1
IO111NDB6V1
NC
VCCIB3
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
GND
N2
GDB0/IO66NPB3V1
IO60NDB3V1
IO60PDB3V1
IO61PDB3V1
NC
GND
N3
GND
N4
GFC2/IO115PDB6V1
IO113PPB6V1
IO112PDB6V1
IO112NDB6V1
VCCIB6
GND
N5
VCC
N6
GCC0/IO50NPB2V1
GCB1/IO51PPB2V1
GCA0/IO52NPB3V0
VCOMPLC
N7
IO59PDB3V0
IO58NDB3V0
NC
N8
N9
VCC
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
R2
IO110PDB6V0
VCC
GCB0/IO51NPB2V1
IO49PPB2V1
IO47NDB2V1
IO47PDB2V1
NC
GND
R3
GND
R4
IO109NPB6V0
IO106NDB6V0
IO106PDB6V0
GEC0/IO104NPB6V0
VMV5
GND
R5
VCC
R6
VCCIB3
R7
IO114NDB6V1
IO117NDB6V1
GFA2/IO117PDB6V1
GFA1/IO118PDB6V1
VCCPLF
IO54NPB3V0
IO57NPB3V0
IO55NPB3V0
IO57PPB3V0
NC
R8
R9
VCCIB5
R10
R11
R12
R13
R14
R15
R16
VCCIB5
IO84NDB5V0
IO84PDB5V0
IO116NDB6V1
GFB2/IO116PDB6V1
VCC
IO56NDB3V0
IO58PDB3V0
NC
VCCIB4
VCCIB4
VMV3
VCCPLD
GND
P2
IO111PDB6V1
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
Advanced v0.2
4-15
ProASIC3E Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
Pin Number
484-Pin FBGA*
Pin Number
R17
R18
R19
R20
R21
R22
T1
A3PE600 Function
GDB1/IO66PPB3V1
GDC1/IO65PDB3V1
IO61NDB3V1
VCC
A3PE600 Function
IO95PPB5V1
IO92PDB5V1
IO90PDB5V1
IO82PDB5V0
IO76NDB4V1
IO76PDB4V1
VMV4
Pin Number
A3PE600 Function
NC
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
W1
W2
NC
W3
NC
W4
GND
IO59NDB3V0
IO62PDB3V1
NC
W5
IO100NDB5V2
GEB2/IO100PDB5V2
IO99NDB5V2
IO88NDB5V0
IO88PDB5V0
IO89NDB5V0
IO80NDB4V1
IO81NDB4V1
IO81PDB4V1
IO70NDB4V0
GDC2/IO70PDB4V0
IO68NDB4V0
GDA2/IO68PDB4V0
TMS
W6
W7
T2
IO110NDB6V0
NC
TCK
W8
T3
VPUMP
W9
T4
IO105PDB6V0
IO105NDB6V0
GEC1/IO104PPB6V0
VCOMPLE
TRST
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
T5
GDA0/IO67NDB3V1
NC
T6
T7
IO64NDB3V1
IO63PDB3V1
NC
T8
GNDQ
T9
GEA2/IO101PPB5V2
IO92NDB5V1
IO90NDB5V1
IO82NDB5V0
IO74NDB4V1
IO74PDB4V1
GNDQ
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
V2
NC
V3
GND
V4
GEA1/IO102PDB6V0
GEA0/IO102NDB6V0
GNDQ
V5
GND
V6
NC
V7
GEC2/IO99PDB5V2
IO95NPB5V1
IO91NDB5V1
IO91PDB5V1
IO83NDB5V0
IO83PDB5V0
IO77NDB4V1
IO77PDB4V1
IO69NDB4V0
GDB2/IO69PDB4V0
TDI
NC
VCOMPLD
V8
NC
VJTAG
V9
VCCIB6
GDC0/IO65NDB3V1
GDA1/IO67PDB3V1
NC
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
Y2
NC
Y3
NC
Y4
IO98NDB5V2
GND
IO64PDB3V1
IO62NDB3V1
NC
Y5
Y6
IO94NDB5V1
IO94PDB5V1
VCC
Y7
U2
IO107PDB6V0
IO107NDB6V0
GEB1/IO103PDB6V0
GEB0/IO103NDB6V0
VMV6
Y8
U3
Y9
VCC
U4
GNDQ
Y10
Y11
Y12
Y13
Y14
IO89PDB5V0
IO80PDB4V1
IO78NPB4V1
NC
U5
TDO
U6
GND
U7
VCCPLE
NC
U8
IO101NPB5V2
IO63NDB3V1
VCC
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
4-16
Advanced v0.2
ProASIC3E Flash Family FPGAs
484-Pin FBGA*
484-Pin FBGA*
Pin Number
A3PE600 Function
Pin Number
A3PE600 Function
IO93PDB5V1
IO87NDB5V0
IO87PDB5V0
NC
Y15
Y16
VCC
NC
AB7
AB8
Y17
NC
AB9
Y18
GND
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
Y19
NC
Y20
NC
IO75NDB4V1
IO75PDB4V1
IO72NDB4V0
IO72PDB4V0
IO73NDB4V0
IO73PDB4V0
NC
Y21
NC
Y22
VCCIB3
GND
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
V
CCIB6
NC
IO98PDB5V2
IO96NDB5V2
IO96PDB5V2
IO86NDB5V0
IO86PDB5V0
IO85PDB5V0
IO85NDB5V0
IO78PPB4V1
IO79NDB4V1
IO79PDB4V1
NC
NC
VCCIB4
GND
GND
NC
IO71NDB4V0
IO71PDB4V0
NC
NC
NC
VCCIB3
GND
GND
AB2
GND
AB3
VCCIB5
AB4
IO97NDB5V2
IO97PDB5V2
IO93NDB5V1
AB5
AB6
Note: *Refer to the "User I/O Naming Convention" on page 2-48.
Advanced v0.2
4-17
ProASIC3E Flash Family FPGAs
676-Pin FBGA
A1 Ball Pad Corner
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
4-18
Advanced v0.2
ProASIC3E Flash Family FPGAs
896-Pin FBGA
A1 Ball Pad Corner
30 2928 2726 2524 2322 21201918 171615141312 1110 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
Advanced v0.2
4-19
ProASIC3E Flash Family FPGAs
Datasheet Information
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” The
definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a advanced datasheet (advanced or production) containing general
product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
Unmarked (production)
This datasheet version contains information that is considered to be final.
International Traffic in Arms Regulations (ITAR) and Export
Administration Regulations (EAR)
The products described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR) or the
Export Administration Regulations (EAR). They may require an approved export license prior to their export. An export
can include a release or disclosure to a foreign national inside or outside the United States.
Advanced v0.2
5-1
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
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51700018-1/1.05
相关型号:
A3PE3000-2FPQG208
Field Programmable Gate Array, 3000000 Gates, CMOS, PQFP208, 0.50 MM PITCH, PLASTIC, QFP-208
ACTEL
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