A42MX24-3TQ176MX39_技术文档

5 . 1

40MX and 42MX FPGA Families

F e a t u r e s

H ig h C a p a c i t y

• Commercial, Military Temperature and MIL-STD-883

Ceramic Packages

• Single-Chip ASIC Alternative

• 3,000 to 54,000 System Gates

• QML Certification

• Up to 2.5 kbits Configurable Dual-Port SRAM

• Fast Wide-Decode Circuitry

• Ceramic Devices Available to DSCC SMD

E a s e o f I n t e g r a t io n

• Up to 202 User-Programmable I/O Pins

• Mixed Voltage Operation (5.0V or 3.3V I/O)

H ig h P e r f o r m a n c e

• 5.6 ns Clock-to-Out

• Synthesis-Friendly Architecture to Support ASIC Design

Methodologies

• 250 MHz Performance

• 5 ns Dual-Port SRAM Access

• 100 MHz FIFOs

• Up to 100% Resource Utilization and 100% Pin Fixing

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

• 7.5 ns 35-Bit Address Decode

H iR e l F e a t u r e s

• Low Power Consumption

• Commercial, Industrial, and Military Temperature Plastic

Packages

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

• 5.0V and 3.3V Programmable PCI-Compliant I/O

P r o d u c t P r o f i l e

Device

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

Capacity

System Gates

SRAM Bits

3,000

N/A

6,000

N/A

14,000

N/A

24,000

N/A

36,000

N/A

54,000

2,560

Logic Modules

Sequential

Combinatorial

Decode

—

295

—

547

—

348

336

N/A

624

608

N/A

954

912

24

1,230

1,184

24

Clock-to-Out

9.5 ns

5.6 ns

6.1 ns

6.3 ns

SRAM Modules

(64x4 or 32x8)

N/A

—

N/A

—

N/A

348

516

2

N/A

624

928

2

N/A

954

1,410

2

10

1,230

1,822

6

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

147

1

273

1

User I/O (Maximum)

PCI

57

No

69

No

104

No

140

No

176

Yes

202

Yes

Boundary Scan Test (BST)

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

44, 68

100

80

—

44, 68, 84

84

100, 160

100

176

—

84

160, 208

—

208, 240

—

208, 256

272

100

80

—

100, 160, 208

100

176

—

176

—

O c t o b e r 2 0 0 3

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

G e n e r a l D e s c r i p t i o n

MHz on-chip operation and 6.1 ns clock-to-output

performance with capacities spanning from 36,000 to 54,000

system gates. MX devices comply 100 percent to the

electrical and timing specifications detailed in the PCI

specification. However, as with all programmable logic

devices, the performance of the final product depends upon

the user's design and optimization techniques.

Actel’s 40MX and 42MX families provide

high-performance, single-chip solution for shortening the

system design and development cycle, offering

cost-effective alternative to ASICs. The 40MX and 42MX

devices are excellent choices for integrating logic that is

currently implemented in multiple PALs, CPLDs, and

FPGAs. Example applications include high-speed

controllers and address decoding, peripheral bus interfaces,

DSP, and co-processor functions.

a

The MX24 and MX36 devices also include system-level

features such as IEEE Standard 1149.1 (JTAG) Boudary

Scan Testing, dual-port SRAM, and fast wide-decode

modules. The A42MX36 device offers dual-port SRAM for

implementing fast FIFOs, LIFOs, and temporary data

storage. The large number of storage elements can

efficiently address applications requiring wide datapath

manipulation and can perform transformation functions

such as those required for telecommunications, networking,

and DSP.

The MX device architecture is based on Actel’s patented

antifuse technology implemented in a 0.45µ triple-metal

CMOS process. With capacities ranging from 3,000 to 54,000

system gates, the synthesis-friendly MX devices provide

performance up to 250 MHz, are live on power-up, and

require up to five times lower stand-by power consumption

than any other FPGA device. Actel’s MX FPGAs provide up

to 202 user I/Os and are available in a wide variety of

packages and speed grades.

All products in the 40MX and 42MX families are available

100 percent tested over the military temperature range. In

addition, the largest member of the family, the A42MX36, is

available in both CQ208 and CQ256 ceramic packages

screened to MIL-STD-883 levels. For easy prototyping and

conversion from plastic to ceramic, the CQ208 and PQ208

devices are pin compatible.

Actel’s 42MX devices also feature MultiPlex I/Os, which

support mixed voltage systems, enable programmable PCI,

deliver high-performance operation at both 5.0V and 3.3V,

and provide a low-power mode.

The MX PCI-Compliant devices are fully compliant with the

PCI Local Bus Specification (version 2.1). They deliver 200

O r d e r i n g I n f o r m a t i o n

A42MX16

–

PQ

100

Application (Temperature Range)

Blank = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

PL = Plastic Leaded Chip Carrier

PQ = Plastic Quad Flat Pack

TQ = Thin (1.4 mm) Quad Flat Pack

VQ = Very Thin (1.0 mm) Quad Flat Pack

BG = Ball Grid Array

CQ = Ceramic Quad Flat Pack

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% Faster than Standard

–2 = Approximately 25% Faster than Standard

–3 = Approximately 35% Faster than Standard

–F = Approximately 40% Slower than Standard

Part Number

A40MX02= 3,000 System Gates

A40MX04= 6,000 System Gates

A42MX09= 14,000 System Gates

A42MX16= 24,000 System Gates

A42MX24= 36,000 System Gates

A42MX36= 54,000 System Gates

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P r o d u c t P l a n

Speed Grade¹

Application

Std

–1

–2

–3

–F²

C

I

M

B

A40MX02 Device

44-Pin Plastic Leaded Chip Carrier (PLCC)

68-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Plastic Quad Flat Pack (PQFP)

80-Pin Very Thin Plastic Quad Flat Pack (VQFP)

A40MX04 Device

✔

—

44-Pin Plastic Leaded Chip Carrier (PLCC)

68-Pin Plastic Leaded Chip Carrier (PLCC)

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Plastic Quad Flat Pack (PQFP)

80-Pin Very Thin Plastic Quad Flat Pack (VQFP)

A42MX09 Device

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Plastic Quad Flat Pack (PQFP)

160-Pin Plastic Quad Flat Pack (PQFP)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

A42MX16 Device

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

100-Pin Plastic Quad Flat Pack (PQFP)

160-Pin Plastic Quad Flat Pack (PQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

100-Pin Very Thin Plastic Quad Flat Pack (VQFP)

A42MX24 Device

✔

—

84-Pin Plastic Leaded Chip Carrier (PLCC)

160-Pin Plastic Quad Flat Pack (PQFP)

208-Pin Plastic Quad Flat Pack (PQFP)

176-Pin Thin Plastic Quad Flat Pack (TQFP)

A42MX36 Device

✔

—

208-Pin Plastic Quad Flat Pack (PQFP)

240-Pin Plastic Quad Flat Pack (PQFP)

272-Pin Plastic Ball Grid Array (PBGA)

208-Pin Ceramic Quad Flat Pack (CQFP)

✔

—

✔

—

✔

—

✔

—

3

✔

3

256-Pin Ceramic Quad Flat Pack (CQFP)

✔

Contact your Actel sales representative for product availability.

Applications:

C

=

Commercial

Industrial

Military

Availability:

✔ = Available

*Speed Grade:

–1 = Approx. 15% faster than Standard

–2 = Approx. 25% faster than Standard

–3 = Approx. 35% faster than Standard

–F = Approx. 40% slower than Standard

I

P

= Planned

M

— = Not Planned

† Only Std, –1, –2 Speed Grade

• Only Std, –1 Speed Grade

v5 .1

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

D e v e l o p m e n t T o o l S u p p o r t

The MX devices are fully supported by Actel’s line of FPGA enabling 100 percent real-time observation and analysis of a

development tools, including the Actel DeskTOP series and

Designer Series tools. The Actel DeskTOP series is an

integrated design environment for PCs that includes design

entry, simulation, synthesis, and place-and-route tools.

Designer Series, Actel’s suite of FPGA development point

tools for PCs and Workstations, includes the ACTgen Macro

Builder, timing-driven place-and-route and analysis tools,

and device programming software.

device's internal logic nodes without design iteration. The

probe circuitry is accessed by Silicon Explorer II, an

easy-to-use integrated verification and logic analysis tool

that can sample data at 100 MHz (asynchronous) or 66 MHz

(synchronous). Silicon Explorer II attaches to a PC’s

standard COM port, turning the PC into a fully functional

18-channel logic analyzer. Silicon Explorer II allows

designers to complete the design verification process at

their desks and reduces verification time from several hours

per cycle to only a few seconds.

In addition, the MX devices contain ActionProbe circuitry

that provides built-in access to every node in a design,

P l a s t i c D e v i c e R e s o u r c e s

User I/Os

PLCC

44-Pin

PLCC

PQFP

VQFP

TQFP

PBGA

Device

68-Pin 84-Pin 100-Pin 160-Pin 208-Pin 240-Pin 80-Pin 100-Pin 176-Pin 272-Pin

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

34

—

57

—

69

72

—

57

69

83

—

57

69

—

83

—

101

125

—

104

140

150

—

140

176

—

202

Package Definitions (Contact your Actel sales representative for product availability.)

PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,

PBGA = Plastic Ball Grid Array

C e r a m i c D e v i c e R e s o u r c e s

User I/Os

CQFP

Device

208-Pin 256-Pin

A42MX36

176 202

Package Definitions (Contact your Actel sales representative for product availability.)

CQFP = Ceramic Quad Flat Pack

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P o w e r R e q u i r e m e n t s

M X A r c h i t e c t u r a l O v e r v i e w

The 40MX and 42MX devices are composed of fine-grained

building blocks that enable fast, efficient logic designs. All

devices within these families are composed of logic

modules, I/O modules, routing resources, and clock

networks, which are the building blocks for designing fast

logic designs. In addition, the A42MX36 device contains

embedded dual-port SRAM and wide decode modules. The

dual-port SRAM modules are optimized for high-speed

datapath functions such as FIFOs, LIFOs, and scratchpad

memory. The “Product Profile” on page 1 lists the specific

logic resources contained within each device.

4 0 M X

The 40MX FPGAs will operate in 5.0V-only systems or

3.3V-only systems.

V

Input

5.0V

3.3V

Output

5.0V

CC

5.0V

3.3V

4 2 M X

The 42MX FPGAs will operate in 5.0V-only systems,

3.3V-only systems, or mixed 5.0V/3.3V systems.

V

Input

Output

5.0V

CCA

CCI

L o g i c M o d u le s

5.0V

3.3V

5.0V

3.3V

5.0V

The 40MX logic module is an eight-input, one-output logic

circuit designed to implement a wide range of logic

functions with efficient use of interconnect routing

resources (Figure 1).

3.3V

3.3V, 5.0V

3.3V

The logic module can implement the four basic logic

functions (NAND, AND, OR, and NOR) in gates of two, three,

or four inputs. Each function may have many versions with

different combinations of active LOW inputs. The logic

module can also implement a variety of D-latches,

exclusivity functions, AND-ORs, and OR-ANDs. No dedicated

hard-wired latches or flip-flops are required in the array,

since latches and flip-flops can be constructed from logic

modules wherever needed in the application.

M i x e d V o l t a g e P o w e r U p a n d P o w e r

D o w n

When powering up the device in the mixed voltage mode

(V_CCA= 5.0V and V_CCI= 3.3V), V_CCAmust be greater than or

equal to V_CCIthroughout the power-up sequence. If V_CCIis

0.5V greater than V_CCAwhen both are above 1.5V, then the

I/Os’ input protection junction on the I/Os will be forward

biased, causing them to draw large amounts of current.

When V_CCAand V_CCIare in the 1.5V to 2.0V region and V

CCI

is greater than V_CCA, all I/Os would momentarily behave as

outputs that are in a logical high state, and I_CCrises to high

levels. For power down, any sequence with V_CCAand V

CCI

can be implemented.

L o w P o w e r M o d e

The 42MX devices have a power-saving feature enabled by a

special Low Power pin (LP). In this mode, the device

consumes very minimal power, with standby current as low

as 500µA (see “Electrical Specifications” on page 13 and

14). All µ I/Os are tristated, all input buffers are turned off,

and the core of the device is turned off. Since the core is

turned off, the state of the registers and the contents of the

SRAM are lost. The device enters low power mode 800ns

after the LP pin is set High. It will resume normal operation

200µs after the LP pin is driven to a logic Low.

Figure 1 • 40MX Logic Module

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

The 42MX devices contain three types of logic modules:

combinatorial (C-modules), sequential (S-modules), and

decode (D-modules).

A0

B0

S0

The C-module, shown in Figure 2, implements the following

function:

D00

Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11

D01

Y

where

D10

S0=A0*B0

S1=A1+B1

D11

The S-module, shown in Figure 3, is designed to implement

high-speed sequential functions within a single logic

module. The S-module implements the same combinatorial

logic function as the C-module while adding a sequential

element. The sequential element can be configured as

either a D flip-flop or a transparent latch. To increase

flexibility, the S-module register can be bypassed so that it

implements purely combinatorial logic.

S1

A1

B1

Figure 2 • C-Module Implementation

D00

D01

D00

D01

OUT

Y

D

Q

Y

D

Q

D10

S0

D11

S1

D11

S1

S0

GATE

CLR

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

Up to 7-Input Function Plus Latch

D00

D01

D0

Y

OUT

Y

D

Q

D10

S0

D1

D11

S1

GATE

S

CLR

Up to 8-Input Function Same as C-Module)

Up to 4-Input Function Plus Latch with Clear

Figure 3 • S-Module Implementation

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

Some of the 42MX devices contain D-modules, which are

arranged around the periphery of the devices. D-modules

contain wide-decode circuitry, which provides a fast,

wide-input AND function similar to that found in

product-term architectures (Figure 4). The D-module

allows 42MX devices to perform wide-decode functions at

speeds comparable to CPLDs and PALs. The output of the

D-module has a programmable inverter for active HIGH or

LOW assertion. The D-module output is hard-wired to an

output pin, but it can also be fed back into the array to be

incorporated into other logic.

offering active HIGH or LOW implementation. The SRAM

block contains eight data inputs (WD[7:0]), and eight

outputs (RD[7:0]) which are connected to segmented

vertical routing tracks.

The 42MX dual-port SRAM blocks provide an optimal

solution for high-speed buffered applications requiring fast

FIFO and LIFO queues. Actel’s ACTgen Macro Builder

provides the capability to quickly design memory functions,

such as FIFOs, LIFOs, and RAM arrays. In addition, unused

SRAM blocks can be used to implement registers for other

logic within the design.

D u a l-P o r t S R A M M o d u le s

The A42MX36 device contains dual-port SRAM modules that

have been optimized for synchronous or asynchronous

applications. The SRAM modules are arranged in 256-bit

blocks that can be configured as 32x8 or 64x4. SRAM

modules can be cascaded together to form memory spaces

of user-definable width and depth. A block diagram of the

42MX dual-port SRAM block is shown in Figure 5.

7 Inputs

Hard-Wire to I/O

Programmable

Inverter

The 42MX SRAM modules are true dual-port structures

containing independent read and write ports. Each SRAM

module contains six bits of read and write addressing

(RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit

blocks. When configured in byte mode, the highest order

address bits (RDAD5 and WRAD5) are not used. The read

and write ports of the SRAM block contain independent

clocks (RCLK and WCLK) with programmable polarities

Feedback to Array

Figure 4 • D-Module Implementation

WD[7:0]

Latches

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4

Latches

Read

Port

Logic

Write

Port

Logic

(256 Bits)

WRAD[5:0]

[5:0]

Read

Logic

Latches

REN

RCLK

MODE

BLKEN

WEN

RD[7:0]

Write

Logic

Routing Tracks

WCLK

Figure 5 • 42MX Dual-Port SRAM Block

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

M u l t i P le x I /O M o d u l e s

Horizontal Routing

MultiPlex I/O supports the most common voltage standards

today: pure 5.0V operation, pure 3.3V operation, and mixed

3.3V operation with 5.0V I/O tolerance for maximum

performance. Internal array performance is retained in 3.3V

systems by using complimentary pass gates that operate as

fast as they do at 5.0V at 3.3V.

Horizontal channels are located between the rows of

modules and are composed of several routing tracks. The

horizontal routing tracks within the channel are divided

into one or more segments. The minimum horizontal

segment length is the width of a module pair, and the

maximum horizontal segment length is the full length of the

channel. Any segment that spans more than one-third at the

row length is considered a long horizontal segment. A

typical channel is shown in Figure 8 on page 9.

Non-dedicated horizontal routing tracks are used to route

signal nets; dedicated routing tracks are used for global

clock networks and for power and ground tie-off tracks.

MultiPlex I/O includes selectable PCI output drives in

certain 42MX devices, enabling 100% PCI-compliance for

both 5.0V and 3.3V systems. For low-power systems,

MultiPlex I/O is used to turn off all inputs and outputs to cut

current consumption to below 100µA.

The MultiPlex I/O modules provide the interface between

the device pins and the logic array. The top of Figure 6 is a

block diagram of the 42MX I/O module. A variety of user

functions, determined by a library macro selection, can be

implemented in the module. (Refer to the Macro Library

Guide for more information.) All 42MX I/O modules contain

tristate buffers, with input and output latches that can be

configured for input, output, or bi-directional operation.

EN

Q

D

PAD

From Array

To Array

All 42MX devices contain flexible I/O structures (Figure 7 on

page 9), where each output pin has a dedicated

output-enable control. The I/O module can be used to latch

input or output data, or both, providing a fast set-up time. In

addition, the Actel Designer Series software tools can build

a D-type flip-flop using a C-module to register input and

output signals. To achieve 5.0V or 3.3V PCI-compliant output

drives on A42MX24 and A42MX36 devices, a chip-wide PCI

fuse is programmed. When the PCI fuse is not programmed,

the output drive is standard. (See the bottom portion of

Figure 6.)

G/CLK*

Q

D

G/CLK*

* Can be Configured as a Latch or D Flip-Flop

(Using C-Module)

Schematic

Actel’s Designer Series development tools provide a design

library of I/O macrofunctions that can implement all I/O

configurations supported by the MX FPGAs.

STD

Signal

R o u t i n g S t r u c t u r e

Output

The MX architecture uses vertical and horizontal routing

tracks to interconnect the various logic and I/O modules.

These routing tracks are metal interconnects that may be

either of continuous length or broken into pieces called

segments. Varying segment lengths allows the interconnect

of over 90% of design tracks to occur with only two antifuse

connections. Segments can be joined together at the ends

using antifuses to increase their lengths up to the full length

of the track. All interconnects can be accomplished with a

maximum of four antifuses.

PCI

Drive

PCI Enable

Fuse

Figure 6 • 42MX I/O Module

Vertical Routing

Another set of routing tracks run vertically through the

module. There are three types of vertical tracks: input,

output, and long, which are also divided into one or more

segments. Each segment in an input track is dedicated to

the input of a particular module; each segment in an output

track is dedicated to the output of a particular module. Long

segments are uncommitted and can be assigned during

8

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

internally-generated clock signal to a clock network. Since

both clock networks are identical, it does not matter

whether CLK0 or CLK1 is being used. The clock input pads

can also be used as normal I/Os, bypassing the clock

networks (Figure 9).

OE

From Internal Logic

The A42MX36 device has four additional register control

resources, called quadrant clock networks (Figure 10 on

page 10). Each quadrant clock provides a local, high-fanout

resource to the contiguous logic modules within its

quadrant of the device. Quadrant clock signals can originate

from specific I/O pins or from the internal array and can be

used as a secondary register clock, register clear, or output

enable.

To Internal Logic

Figure 7 • 40MX I/O Module

routing. Each output segment spans four channels (two

above and two below), except near the top and bottom of

the array, where edge effects occur. Long vertical tracks

contain either one or two segments. An example of vertical

routing tracks and segments is shown in Figure 8.

Segmented

Logic

Horizontal

Modules

Routing

Tracks

Antifuse Structures

An antifuse is a “normally open” structure as opposed to the

normally connected fuse structure used in PROMs or PALs.

The use of antifuses to implement a programmable logic

device results in highly testable structures as well as

efficient programming algorithms. The structure is

highly-testable because there are no pre-existing

connections; therefore, temporary connections can be made

using pass transistors. These temporary connections can

isolate individual antifuses to be programmed and

individual circuit structures to be tested, which can be done

before and after programming. For example, all metal

tracks can be tested for continuity and shorts between

adjacent tracks, and the functionality of all logic modules

can be verified.

Antifuses

Vertical Routing Tracks

Figure 8 • Routing Structure

CLKB

CLKA

CLKINB

CLKINA

C l o c k N e t w o r k s

From

Pads

S0

S1

Internal

Signal

The 40MX devices have one global clock distribution

network (CLK). Two low-skew, high-fanout clock

distribution networks are provided in each 42MX device.

These networks are referred to as CLK0 and CLK1. Each

network has a clock module (CLKMOD) that selects the

source of the clock signal and may be driven as follows:

CLKMOD

CLKO(17)

CLKO(16)

CLKO(15)

Clock

Drivers

• Externally from the CLKA pad

• Externally from the CLKB pad

• Internally from the CLKINTA input

• Internally from the CLKINTB input

CLKO(2)

CLKO(1)

The clock modules are located in the top row of I/O

modules. Clock drivers and a dedicated horizontal clock

track are located in each horizontal routing channel.

Clock Tracks

The user controls the clock module by selecting one of two

clock macros from the macro library. The macro CLKBUF is

used to connect one of the two external clock pins to a clock

network, and the macro CLKINT is used to connect an

Figure 9 • Clock Networks

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4 0 M X a n d 4 2 M X F P G A F a m i l i e s

T e s t C ir c u it r y

interconnections. The TMS and TCK signals are shared

among all devices in the test chain so that all components

operate in the same state.

All devices contain Actel’s ActionProbe test circuitry which

test and debug a design once it is programmed into a device.

Once a device has been programmed, the ActionProbe test

circuitry allows the designer to probe any internal node

during device operation to aid in debugging a design. In

addition, 42MX devices contain IEEE Standard 1149.1

boundary scan test circuitry.

The 42MX family implements a subset of the IEEE Standard

1149.1 BST instruction in addition to a private instruction,

which allows the use of Actel’s ActionProbe facility with

BST. Refer to the IEEE Standard 1149.1 specification for

detailed information regarding BST.

IEEE Standard 1149.1 Boundary Scan Testing (BST)

Boundary Scan Circuitry

IEEE Standard 1149.1 defines a four-pin Test Access Port

(TAP) interface for testing integrated circuits in a system.

The 42MX family provides five BST pins: Test Data In (TDI),

Test Data Out (TDO), Test Clock (TCK), and Test Mode

Select Test Reset (TRST) (42MX24A only). Devices are

configured in a test “chain” where BST data can be

transmitted serially between devices via TDO-to-TDI

The 42MX boundary scan circuitry consists of a Test Access

Port (TAP) controller, test instruction register, a JPROBE

register, a bypass register, and a boundary scan register.

Figure 11 on page 11 shows a block diagram of the 42MX

boundary scan circuitry.

QCLKA

QCLKC

Quad

Clock

Module

Clock

Module

QCLK1

QCLK3

QCLKB

QCLKD

*QCLK1IN

*QCLK3IN

S0 S1

S1 S0

Quad

Clock

Quad

Clock

QCLK2

QCLK4

Module

*QCLK2IN

*QCLK4IN

S0 S1

S1 S0

*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.

Figure 10 • Quadrant Clock Network

1 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

JPROBE Register

Boundary Scan Register

Output

MUX

TDO

Bypass

Register

Control Logic

JTAG

TMS

Instruction

Decode

TAP Controller

TCK

JTAG

TDI

Instruction

Register

Figure 11 • 42MX IEEE 1149.1 Boundary Scan Circuitry

When a device is operating in BST mode, four I/O pins are

used for the TDI, TDO, TMS, and TCK signals. An active

reset (nTRST) pin is not supported; however, the 42MX

device contain power-on circuitry that resets the boundary

scan circuitry upon power-up. Table 1 summarizes the

functions of the IEEE 1149.1 BST signals.

JTAG fuse programmed:

• TCK must be terminated—logical high or low doesn’t

matter (to avoid floating input)

• TDI, TMS may float or at logical high (internal pull-up is

present)

• TDO may float or connect to TDI of another device (it’s an

output)

Table 1 • IEEE 1149.1 BST Signals

Signal

Name

Function

JTAG fuse not programmed:

TDI

Test Data In Serial data input for BST

instructions and data. Data is

shifted in on the rising edge of

TCK.

• TCK, TDI, TDO, TMS are user I/O. If not used, they will be

configured as tristated output.

BST Instructions

TDO

TMS

Test Data

Out

Serial data output for BST

instructions and test data.

Boundary scan testing within the 42MX devices is controlled

by a Test Access Port (TAP) state machine. The TAP

controller drives the three-bit instruction register, a bypass

register, and the boundary scan data registers within the

device. The TAP controller uses the TMS signal to control

the testing of the device. The BST mode is determined by

the bitstream entered on the TMS pin. Table 2 describes the

test instructions supported by the 42MX devices.

Test Mode

Select

Serial data input for BST mode.

Data is shifted in on the rising

edge of TCK.

TCK

Test Clock

Clock signal to shift the BST

data into the device.

JTAG

Reset

All SX-A devices are IEEE 1149.1 (JTAG) compliant. SX-A

devices offer superior diagnostic and testing capabilities by

providing JTAG and probing capabilites. These functions

are controlled through the special JTAG pins in conjunction

with the program fuse.

The TMS pin is equipped with an internal pull-up resistor.

This allows the TAP controller to remain in or return to the

Test-Logic-Reset state when there is no input or when a

logical 1 is on the TMS pin. To reset the controller, TMS

must be HIGH for at least five TCK cycles.

v5 .1

1 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

Table 2 • BST Instructions

Test Mode

Code

Description

EXTEST

000

Allows the external circuitry and

board-level interconnections to

be tested by forcing a test

pattern at the output pins and

capturing test results at the

input pins.

SAMPLE/

PRELOAD

001

011

100

Allows a snapshot of the signals

at the device pins to be

captured and examined during

device operation.

JPROBE

A private instruction allowing the

user to connect Actel’s Micro

Probe registers to the test

chain.

USER

INSTRUCTION

Allows the user to build

application-specific instructions

such as RAM READ and RAM

WRITE.

HIGH Z

CLAMP

BYPASS

101

110

111

Refer to the IEEE Standard

1149.1 specification.

Refer to the IEEE Standard

1149.1 specification.

Enables the bypass register

between the TDI and TDO pins.

The test data passes through

the selected device to adjacent

devices in the test chain.

1 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

5 . 0 V O p e r a t i n g C o n d i t i o n s a n d M i x e d 5 . 0 V /3 . 3 V O p e r a t i n g C o n d i t i o n s

1

A b s o l u t e M a x i m u m R a t i n g s

F r e e A i r Te m p e r a t u r e R a n g e

R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s

Parameter

Commercial Industrial

Military

Units

Symbol Parameter

Limits

Units

Temperature

Range¹

0 to +70

±5

–40 to +85 –55 to +125 °C

V_CCA

V_CCI

/

DC Supply Voltage

–0.5 to +7.0

V

PowerSupply

Tolerance

±10

%V_CC

V_I

Input Voltage

–0.5 to V_CC+0.5

–65 to +150

V

V_CCI

4.75 to 5.25 4.5 to 5.5

3.14 to 3.47 3.0 to 3.6

4.5 to 5.5

3.0 to 3.6

V

V_O

Output Voltage

Storage Temperature

V_CCA

T_STG

°C

2

V_CCI

Notes:

1. Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended

periods may affect device reliability. Devices should not be

operated outside the Recommended Operating Conditions.

1. Ambient temperature (T_A) is used for commercial and

industrial; case temperature (T_C) is used for military.

2. Operating condition for I/Os in mixed voltage mode.

2. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than V

+ 0.5V or less than GND – 0.5V, the internal

protecti^Co^Cn^Adiode will be forward-biased and can draw

excessive current.

E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Commercial ‘–F’

Industrial

Military

Max.

Symbol

Parameter

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

1

V_OH

(I_OH= –10 mA) ²TTL

(I_OH= –6 mA) TTL

(I_OH= –4 mA) TTL

(I_OL= 10 mA) ²TTL

(I_OL= 6 mA) TTL

2.4

V

3.7

V

1

V_OL

0.5

0.8

0.5

0.8

V

0.40

0.8

0.40

0.8

V

V_IL

V_IH

I_IL

–0.3

V

2.0 V_CCI+ 0.3 2.0 V_CCI+ 0.3 2.0 V_CCI+ 0.3 2.0 V_CCI+ 0.3

V

(V_IN= 0.5)

–10

500

10

–10

500

10

µA

ns

pF

mA

I_IH

(V_IN= 2.7)

2

Input Transition Time t_R, t_F

C_IOI/O Capacitance^{2, 3}

500

10

4

Standby Current, I_CC

Notes 5 & 6

25.0

Notes 6 & 7

25

I_CC(D)Dynamic V_CCISupply Current

Low Power Mode Standby Current

See the “Power Dissipation” section on page 18.

I_CC– 0.5 I_CC– 0.5

Note 8

I_CC– 0.5

mA

Notes:

1. Only one output tested at a time. V_CCI= min.

2. Not tested, for information only.

3. Includes worst-case 84-pin PLCC package capacitance. V_OUT= 0 V, f = 1 MHz.

4. All outputs unloaded. All inputs = V_CCIor GND. I_CClimit includes I_PPand I_SVduring normal operation.

5. A40MX02 and A40MX04 I_CC= 3 mA, A42MX09 I_CC= 5 mA, A42MX16 I_CC= 6 mA, A42MX24, A42MX24A, and A42MX36 I_CC= 25 mA.

6. I_CCMax = 2 mA is available by special request. Contact your local Actel Sales representative for additional information.

7. A40MX02 and A40MX04 I_CC= 10 mA, A42MX09, A42MX16, A42MX24, A42MX24A, and A42MX36 I_CC= 25 mA.

8. In Low Power Mode, A40MX09, A42MX16, A42MX24, and A42MX36 ICC = 500 µA; A40MX02 and A40MX04 = N/A.

v5 .1

1 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

3 . 3 V O p e r a t i n g C o n d i t i o n s

A b s o l u t e M a x i m u m R a t i n g s

1

R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s

V _{C C}= V _{C C A}a n d V _{C C I}

Parameter

Commercial Industrial

Military

Units

F r e e A ir T e m p e r a t u r e R a n g e

Temperature

Range¹

0 to

+70

–40 to

+85

–55 to

+125

°C

Symbol

Parameter

Limits

Units

PowerSupply

Tolerance

V_CC

V_I

DC Supply Voltage

Input Voltage

–0.5 to +7.0

V

±5

±10

%V

V

–0.5 to V_CC+0.5

V_CCI

V_CCA

Note:

3.0 to 3.6

3.0 to 3.6 3.0 to 3.6

V_O

Output Voltage

V

I/O Source Sink

Current²

I_IO

±20

mA

°C

1. Ambient temperature (T_A) is used for commercial, and

industrial; case temperature (T_C) is used for military.

T_STG

Storage Temperature

–65 to +150

Notes:

1. Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended

periods may affect device reliability. Devices should not be

operated outside the Recommended Operating Conditions.

2. Device inputs are normally high impedance and draw

extremely low current. However, when input voltage is greater

than V + 0.5V or less than GND – 0.5V, the internal protection

diodes^Cw^Cill forward-bias and can draw excessive current.

E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Parameter

Commercial ‘–F’

Industrial

Military

Max.

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

(I_OH= –4 mA)

(I_OH= –3.2 mA)

(I_OL= 6 mA)

2.15

2.4

2.15

2.4

V

1

V_OH

1

V_OL

V_IL

V_IH

I_IL

0.4

0.8

0.4

0.8

0.48

0.8

0.48

0.8

V

–0.3

V

2.0 V_CC+ 0.3 2.0 V_CC+ 0.3 2.0 V_CC+ 0.3 2.0 V_CC+ 0.3

V

–10

500

10

–10

500

10

µA

ns

pF

mA

I_IH

2

Input Transition Time t_R, t_F

C_IOI/O Capacitance^{2, 3}

500

10

4

Standby Current, I_CC

Notes 5 & 6

25

Notes 6 & 7

25

I_CC(D)Dynamic V_CCSupply Current

Low Power Mode Standby Current

Notes:

See the “Power Dissipation” section on page 18.

I_CC– 5.0 I_CC– 5.0

Note 8

I_CC– 5.0

mA

1. Only one output IV curve tested at a time. V_CC= min.

2. Not tested, for information only.

3. Includes worst-case 84-pin PLCC package capacitance. V_OUT= 0 V, f = 1 MHz.

4. All outputs unloaded. All inputs = V_CCor GND.

5. A40MX02 and A40MX04 I_CC= 3 mA, A42MX09 I_CC= 5 mA, A42MX16 I_CC= 6 mA, A42MX24 and A42MX36 I_CC= 25 mA.

6. I_CCMax = 1.5mA is available by special request. Contact your Actel Sales representative for additional information.

7. A40MX02 and A40MX04 I_CC= 10 mA, A42MX09, A42MX16, A42MX24, and A42MX36 I_CC= 25 mA.

8. In Low Power Mode, A42MX09, A42MX16, A42MX24, A42MX36 I_CC= 50 µA. A40MX02 and A40MX04 = N/A.

1 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

O u t p u t D r i v e C h a r a c t e r i s t i c s f o r

5 . 0 V P C I S i g n a l i n g

MX PCI device I/O drivers were designed specifically for

high-performance PCI systems. Figure 12 on page 17 shows

the typical output drive characteristics of the MX devices.

MX output drivers are compliant with the PCI Local Bus

Specification.

D C S p e c if i c a t io n ( 5 . 0 V P C I S ig n a li n g ) ¹

PCI

Maximum

MX

Symbol Parameter

Condition

Minimum

Maximum

Units

V_CC

V_IH

V_IL

I_IH

Supply Voltage

4.75

2.0

5.25

V_CC+ 0.5

0.8

4.75

2.0

–0.3

—

5.25²

V_CC+ 0.3

0.8

V

Input High Voltage

Input Low Voltage

–0.5

V

Input High Leakage Current

Input Low Leakage Current

V_IN= 2.7

V_IN=0.5

70

10

µA

I_IL

–70

—

–10

I_OUT= –2 mA

I_OUT= –6 mA

2.4

V_OH

Output High Voltage

Output Low Voltage

V

3.84

—

I_OUT= 3 mA,

6 mA

V_OL

0.55

0.33

C_IN

Input Pin Capacitance

CLK Pin Capacitance

Pin Inductance

10

12

20

—

10

pF

nH

C_CLK

L_PIN

Notes:

5

< 8 nH³

1. PCI Local Bus Specification Section 4.2.1.1.

2. Maximum rating for V –0.5V to 7.0V.

CC

3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.

A C S p e c if i c a t io n s ( 5 . 0 V P C I S i g n a l in g ) ¹

PCI

Minimum

MX

Maximum Minimum Maximum Units

Symbol Parameter

Condition

I_CL

Low Clamp Current

–5 < V_IN≤ –1

–25 + (V_IN+1)

/0.015

–60

–10

mA

Slew (r) Output Rise Slew Rate

Slew (f) Output Fall Slew Rate

Note:

0.4V to 2.4V load

2.4V to 0.4V load

1

5

1.8

2.8

4.3

V/ns

1. PCI Local Bus Specification Section 4.2.1.2.

v5 .1

1 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

O u t p u t D r i v e C h a r a c t e r i s t i c s f o r 3 . 3 V P C I S i g n a l i n g

D C S p e c if i c a t io n ( 3 . 3 V P C I S ig n a li n g ) ¹

PCI

MX

Symbol Parameter

Condition

Minimum

Maximum

Minimum

Maximum

Units

V_CC

V_IH

V_IL

I_IH

Supply Voltage

3.0

0.5

3.6

V_CC+ 0.5

0.8

3.0

0.5

3.6

V_CC+ 0.3

0.8

V

Input High Voltage

Input Low Voltage

–0.5

–0.3

V

Input High Leakage Current

Input Leakage Current

Output High Voltage

Output Low Voltage

V_IN= 2.7

70

10

µA

V

I_IL

–70

–10

V_OH

V_OL

I_OUT= –2 mA

0.9

5

3.3

I_OUT= 3 mA,

6 mA

0.1

0.1 V_CC

V

C_IN

Input Pin Capacitance

CLK Pin Capacitance

Pin Inductance

10

12

20

10

pF

nH

C_CLK

L_PIN

Notes:

< 8 nH³

1. PCI Local Bus Specification Section 4.2.2.1.

2. Maximum rating for V –0.5V to 7.0V.

CC

3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.

A C S p e c if i c a t io n s f o r ( 3 . 3 V P C I S ig n a li n g ) ¹

PCI

Minimum

MX

Maximum Minimum Maximum Units

Symbol Parameter

Condition

I_CL

Low Clamp Current

–5 < V_IN≤ –1

–25 + (V_IN+1)

/0.015

–60

–10

mA

Slew (r) Output Rise Slew Rate

Slew (f) Output Fall Slew Rate

Note:

0.2V to 0.6V load

0.6V to 0.2V load

1

4

1.8

2.8

4.0

V/ns

1. PCI Local Bus Specification Section 4.2.2.2.

1 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

0.50

0.45

0.40

PCI I_OLMaximum

0.35

0.30

0.25

0.20

MX PCI I_OL

0.15

0.10

PCI I_OLMinimum

0.05

0.00

0

1

2

3

4

5

6

–0.05

–0.10

–0.15

–0.20

PCI I_OHMaximum

MX PCI I_OH

PCI I_OHMinimum

Voltage Out (V)

Figure 12 • Typical Output Drive Characteristics (Based upon measured data)

v5 .1

1 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e T h e r m a l C h a r a c t e r i s t i c s

The device junction-to-case thermal characteristic is θ_jc,

and the junction-to-ambient air characteristic is θ_ja. The

thermal characteristics for θ_jaare shown with two different

air flow rates. Ambient temperature (T_A) is used for

commercial and industrial; case temperature (T_C) is used

for military.

Maximum junction temperature is 150°C.

A sample calculation of the absolute maximum power

dissipation allowed for a PQFP 160-pin package at

commercial temperature is as follows:

Max. junction temp. (°C) – Max. commercial temp.

----------------------------------------------------------------------------------------------------------------------------

150°C – 70°C

---------------------------------

=

= 2.5W

θ_ja(°C/W)

32°C/W

θ_ja

Plastic Packages

Pin Count

θ_jc

Still Air

300 ft/min

Plastic Quad Flat Pack

100

160

208

240

12

10

8

34°C/W

32°C/W

30°C/W

19°C/W

43°C/W

36°C/W

32°C/W

28°C/W

39°C/W

38°C/W

20°C/W

31°C/W

24°C/W

23°C/W

16°C/W

31°C/W

25°C/W

22°C/W

21°C/W

33°C/W

32°C/W

14.5°C/W

3.5

16

13

12

11

12

10

3

Plastic Leaded Chip Carrier

Thin Plastic Quad Flat Pack

Very Thin Plastic Quad Flat Pack

Plastic Ball Grid Array

44

68

84

176

80

100

272

θ_ja

Ceramic Packages

Pin Count

θ_jc

Still Air

Ceramic Quad Flat Pack

208

256

6.3

6.2

22°C/W

20°C/W

S t a t ic P o w e r C o m p o n e n t

P o w e r D i s s i p a t i o n

Actel FPGAs have small static power components that

result in power dissipation lower than PALs or CPLDs. By

integrating multiple PALs/CPLDs into one FPGA, an even

greater reduction in board-level power dissipation can

be achieved.

G e n e r a l P o w e r E q u a t i o n

P = [I_CCstandby + I_CCactive] * V_CCI+ I_OL* V * N

OL

+ I_OH* (V_CCI– V ) * M

OH

where:

I_CCstandby is the current flowing when no inputs or

outputs are changing.

The power due to standby current is typically a small

component of the overall power. Standby power is

calculated for commercial, worst-case conditions:

I_CCactive is the current flowing due to CMOS switching.

I_OL, I_OHare TTL sink/source currents.

I_CC

V

Power

CCA

2 mA

5.25 V

10.5 mW

V , V_OHare TTL level output voltages.

OL

The static power dissipation by TTL loads depends on the

number of outputs driving HIGH or LOW, and on the DC load

current. Again, this number is typically small. For instance,

a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with

all outputs driving LOW, and 140 mW with all outputs driving

HIGH. The actual dissipation will average somewhere in

between, as I/Os switch states with time.

N equals the number of outputs driving TTL loads to V .

OL

M equals the number of outputs driving TTL loads to V .

OH

Accurate values for N and M are difficult to determine

because they depend on the family type, on design details,

and on the system I/O. The power can be divided into two

components: static and active.

1 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A c t i v e P o w e r C o m p o n e n t

where:

Power dissipation in CMOS devices is usually dominated by

the active (dynamic) power dissipation. This component is

frequency-dependent and a function of the logic and the

external I/O. Active power dissipation results from charging

internal chip capacitances of the interconnect,

unprogrammed antifuses, module inputs, and module

outputs, plus external capacitance due to PC board traces

and load device inputs. An additional component of the

active power dissipation is the totem pole current in the

CMOS transistor pairs. The net effect can be associated

with an equivalent capacitance that can be combined with

frequency and voltage to represent active power dissipation.

m

n

= Number of logic modules switching at frequency f_m

= Number of input buffers switching at frequency f_n

= Number of output buffers switching at frequency f_p

= Number of clock loads on the first routed array

clock

p

q₁

q₂

= Number of clock loads on the second routed array

clock

r₁

r₂

= Fixed capacitance due to first routed array clock

= Fixed capacitance due to second routed array

clock

C_EQM= Equivalent capacitance of logic modules in pF

C_EQI= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in pF

E q u iv a l e n t C a p a c it a n c e

The power dissipated by a CMOS circuit can be expressed by

the equation:

C_EQCR= Equivalent capacitance of routed array clock in pF

Power (µW) = C_EQ* V ²* F

(1)

C_L

f_m

f_n

= Output load capacitance in p

CCA

where:

= Average logic module switching rate in MHz

= Average input buffer switching rate in MHz

= Average output buffer switching rate in MHz

= Average first routed array clock rate in MHz

= Average second routed array clock rate in MHz

C_EQ= Equivalent capacitance expressed in picofarads

(pF)

f_p

f_q1

f_q2

V

= Power supply in volts (V)

CCA

F

= Switching frequency in megahertz (MHz)

Equivalent capacitance is calculated by measuring

I_CCactive at a specified frequency and voltage for each

circuit component of interest. Measurements have been

F ix e d C a p a c it a n c e V a lu e s

f o r M X F P G A s ( p F )

r₁

r₂

made over a range of frequencies at a fixed value of V

.

CC

Device Type

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

routed_Clk1 routed_Clk2

Equivalent capacitance is frequency-independent, so the

results can be used over a wide range of operating

conditions. Equivalent capacitance values are shown below.

41.4

68.6

118

165

185

220

N/A

118

165

185

220

C _{E Q}Va lu e s f o r A c t e l M X F P G A s

Modules (C_EQM

Input Buffers (C_EQI

Output Buffers (C_EQO

Routed Array Clock Buffer Loads (C_EQCR

)

3.5

6.9

)

18.2

1.4

)

To calculate the active power dissipated from the complete

design, the switching frequency of each part of the logic

must be known. The equation below shows a piece-wise

linear summation over all components.

Power = V ²* [(m x C_EQM* f_m)_Modules

+

CCA

(n * C_EQI* f_n)_Inputs+ (p * (C_EQO+ C_L) * f_p)_outputs

+

0.5 * (q₁* C_EQCR* f_q1)_{routed_Clk1}+ (r₁* f_q1)_{routed_Clk1}

0.5 * (q₂* C_EQCR* f_q2)_{routed_Clk2}+ (r₂* f_q2)_{routed_Clk2}

+

(2)

v5 .1

1 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

D e t e r m in i n g Av e r a g e S w i t c h in g F r e q u e n c y

To determine the switching frequency for a design, the data

input values to the circuit must be clearly understood. The

following guidelines represent worst-case scenarios; these

can be used to generally predict the upper limits of power

dissipation.

Logic Modules (m)

=

80% of

Combinatorial

Modules

Average Logic Module Switching

Rate (f_m)

=

F/10

F/5

F/10

F

Average Input Switching Rate

(f_n)

Logic Modules (m)

=

80% of

Combinatorial

Modules

Average Output Switching Rate

(f_p)

Inputs Switching (n)

Outputs Switching (p)

=

# of Inputs/4

Average First Routed Array

Clock Rate (f_q1)

# of Outputs/4

First Routed Array Clock Loads

(q₁)

40% of Sequential

Modules

Average Second Routed Array

Clock Rate (f_q2)

F/2

Second Routed Array Clock

Loads (q₂)

=

40% of Sequential

Modules

Load Capacitance (C_L)

35 pF

4 0 M X T i m i n g M o d e l *

Input Delay

Internal Delays

Predicted

Routing

Delays

Output Delay

I/O Module

t_INYL= 0.62 ns

t_IRD2= 2.59 ns

t_IRD1= 2.09 ns

Logic Module

t_DLH= 3.32 ns

t_ENHZ= 7.92 ns

t_RD1= 1.28 ns

t_RD2= 1.80 ns

t_RD4= 2.33 ns

t_RD8= 4.93 ns

t_PD= 1.24 ns

t

_IRD4= 3.64 ns

t_CO= 1.24 ns

t_IRD8= 5.73 ns

Array

Clock

t_CKH= 4.55 ns

FO = 128

F_MAX= 180 MHz

* Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.

2 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T i m i n g M o d e l *

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

t_IRD1

2.24 ns†

=

t_INYL= 1.16 ns

Combinatorial

Logic Module

t_DLH= 2.70 ns

t_RD1= 0.80 ns

t_RD2= 1.00 ns

t_RD4= 1.50 ns

t_RD8= 2.50 ns

D

G

Q

t

_PD= 1.55 ns

I/O Module

t_DLH= 2.70 ns

Sequential

Logic Module

t_INH= 0.00 ns

_INSU= 0.54 ns

t

_INGL= 1.40 ns

Combin-

atorial

Logic

included

in t_SUD

D

G

Q

t_RD1= 0.80 ns

t

_ENHZ= 5.40 ns

t_OUTH= 0.00 ns

t_OUTSU= 0.30 ns

t_GLH= 2.90 ns

t_CO= 1.37 ns

t

_SUD= 0.36 ns

t_HD= 0.00 ns

Array

Clocks

t_CKH= 2.70 ns

F_MAX= 245 MHz

FO = 32

t

_LCO= 5.60 ns (light loads, pad-to-pad)

*Values are shown for A42MX09 ‘–2’ at 5.0V worst-case commercial conditions

† Input module predicted routing delay

v5 .1

2 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T i m i n g M o d e l ( L o g i c F u n c t i o n s u s i n g Q u a d r a n t C l o c k s ) *

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

t_INPY= 1.14 ns

t

_IRD1= 2.18 ns

Combinatorial

Module

t_DLH= 2.84 ns

t_RD1= 1.04 ns

t_RD2= 1.42 ns

t_RD4= 2.18 ns

D

G

Q

t

_PD= 1.46 ns

Decode

Module

t_INH= 0.00 ns

_INSU= 0.53 ns

t_RDD= 0.38 ns

t

_INGO= 1.55 ns

t_PDD= 1.78 ns

I/O Module

t_DLH= 2.84 ns

Sequential

Logic Module

t_RD1= 1.04 ns

Combin-

D

G

Q

atorial

Logic

included

in t_SUD

t_ENHZ= 5.80 ns

t_LH= 0.00 ns

_LSU= 0.53 ns

t

_CO= 1.43 ns

t_SUD= 0.30 ns

_HD= 0.00 ns

t_GHL= 3.27 ns

t

Quadrant

Clocks

t

_CKH= 3.03 ns**

F_MAX= 163 MHz

* Preliminary values are shown for A42MX36 ‘–2’ at 5.0V worst-case commercial conditions

** Load-dependent

2 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T i m i n g M o d e l ( S R A M F u n c t i o n s ) *

Input Delays

I/O Module

t_INPY= 1.14 ns

t

_IRD1= 2.18 ns

D

G

Q

Predicted

Routing

Delays

I/O Module

t_INSU= 0.53 ns

t_INH= 0.00 ns

t_INGO= 1.55 ns

t_DLH= 2.84 ns

RD [7:0]

RDAD [5:0]

REN

WD [7:0]

t_RD1= 1.04 ns

WRAD [5:0]

BLKEN

D

G

Q

WEN

WCLK

RCLK

t_ADSU= 1.80 ns

t_GHL= 5.50 ns

t_LSU= 0.30 ns

t_LH= 0.00 ns

t

_ADH= 0.00 ns

t

_ADH= 0.00 ns

t_WENSU= 2.90 ns

_BENS= 2.90 ns

t_RENSU= 0.80 ns

t_RCO= 3.80 ns

Array

Clocks

t

F

_MAX= 151 MHz

*Values are shown for A42MX36 ‘–2’ at 5.0V worst-case commercial conditions.

v5 .1

2 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a r a m e t e r M e a s u r e m e n t

O u t p u t B u f f e r D e l a y s

E

D

PAD To AC test loads (shown below)

TRIBUFF

In

50%

V_OH

E

50%

E

50%

V_CCI

50%

V_OH

50%

1.5V

V_OL

90%

PAD

V_OL

PAD

GND

1.5V

10%

1.5V

t_DLH

t_DHL

t_ENZL

t_ENLZ

t_ENZH

t_ENHZ

A C Te s t L o a d s

Load 1

Load 2

(Used to measure propagation delay)

(Used to measure rising/falling edges)

V_CCI

GND

To the output under test

35 pF

R to V_CCIfor t_PLZ/t_PZL

R to GND for t_{PHZ PZH}

/t

R = 1 kΩ

To the output under test

35 pF

I n p u t B u ff e r D e la y s

M o d u le D e l a y s

S

A

B

Y

PAD

INBUF

S, A or B

Y

50% 50%

3V

50%

PAD

0V

50%

1.5V

V_CCI

1.5V

t_PLH

t_PHL

Y

GND

50%

t_PHL

50%

t_PLH

t_INYH

t_INYL

2 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

S e q u e n t i a l M o d u l e T i m i n g C h a r a c t e r i s t i c s

F l ip -F l o p s a n d L a t c h e s

D

E

CLK

Y

PRE

CLR

(Positive Edge-Triggered)

t_HD

D¹

t_A

t_WCLKA

t_SUD

G, CLK

t_SUENA

t_WCLKI

t_HENA

E

t_CO

Q

t_RS

PRE, CLR

t_WASYN

Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.

v5 .1

2 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

S e q u e n t i a l T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

I n p u t B u f f e r L a t c h e s

PAD

DATA

IBDL

G

PAD

CLK

CLKBUF

DATA

G

t_INH

t_INSU

t_HEXT

CLK

t_SUEXT

O u t p u t B u f f e r L a t c h e s

D

G

PAD

OBDLHS

D

G

t_OUTSU

t_OUTH

2 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

D e c o d e M o d u l e T i m i n g

A

B

C

D

E

F

Y

H

G

A–G, H

50%

Y

t_PHL

t_PLH

S R A M T i m i n g C h a r a c t e r i s t i c s

Read Port

Write Port

WRAD [5:0]

BLKEN

WEN

RDAD [5:0]

LEW

RAM Array

32x8 or 64x4

(256 Bits)

REN

WCLK

RCLK

WD [7:0]

RD [7:0]

v5 .1

2 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

D u a l -P o r t S R A M T i m i n g W a v e f o r m s

4 2 M X S R A M Wr it e O p e r a t io n

t_RCKHL

WCLK

t_ADSU

t_ADH

WD[7:0]

WRAD[5:0]

Valid

t_WENSU

t_WENH

WEN

t_BENSU

Valid

t_BENH

BLKEN

Note: Identical timing for falling edge clock.

4 2 M X S R A M S y n c h r o n o u s R e a d O p e r a t i o n

t_CKHL

t_RCKHL

RCLK

t_RENSU

t_RENH

REN

t_ADSU

Valid

t_ADH

RDAD[5:0]

t_RCO

t_DOH

Old Data

New Data

RD[7:0]

Note: Identical timing for falling edge clock.

2 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X S R A M A s y n c h r o n o u s R e a d O p e r a t i o n —Ty p e

1

(Read Address Controlled)

t_RDADV

RDAD[5:0]

RD[7:0]

ADDR1

t_DOH

ADDR2

t_RPD

Data 1

Data 2

4 2 M X S R A M A s y n c h r o n o u s R e a d O p e r a t i o n —Ty p e

2

(Write Address Controlled)

WEN

t_WENSU

t_WENH

WD[7:0]

WRAD[5:0]

BLKEN

Valid

t_ADH

t_ADSU

WCLK

t_RPD

t_DOH

Old Data

New Data

RD[7:0]

v5 .1

2 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

L o n g T r a c k s

P r e d i c t a b l e P e r f o r m a n c e :

T i g h t D e l a y D i s t r i b u t i o n s

Some nets in the design use long tracks, which are special

routing resources that span multiple rows, columns, or

modules. Long tracks employ three and sometimes four

antifuse connections, which increase capacitance and

resistance, resulting in longer net delays for macros

connected to long tracks. Typically, up to 6 percent of

nets in a fully utilized device require long tracks. Long

tracks add approximately a 3 ns to a 6 ns delay, which is

represented statistically in higher fanout (FO=8) routing

delays in the data sheet specifications section, beginning on

page 34.

Propagation delay between logic modules depends on the

resistive and capacitive loading of the routing tracks, the

interconnect elements, and the module inputs being driven.

Propagation delay increases as the length of routing tracks,

the number of interconnect elements, or the number of

inputs increases.

From a design perspective, the propagation delay can be

statistically correlated or modeled by the fanout (number of

loads) driven by a module. Higher fanout usually requires

some paths to have longer routing tracks.

T im i n g D e r a t in g

The MX FPGAs deliver a tight fanout delay distribution,

which is achieved in two ways: by decreasing the delay of the

interconnect elements and by decreasing the number of

interconnect elements per path.

A timing derating factor of 0.45 is used to reflect best-case

processing. Note that this factor is relative to the standard

speed timing parameters and must be multiplied by the

appropriate voltage and temperature derating factors for a

given application.

Actel’s patented antifuse offers

a

very low

resistive/capacitive interconnect. The antifuses, fabricated

in 0.45 µ lithography, offer nominal levels of 100 ¾

resistance and 7.0 femtofarad (fF) capacitance per antifuse.

T i m i n g D e r a t i n g F a c t o r s

C o m m e r c ia l t o I n d u s t r i a l

MX fanout distribution is also tight due to the low number of

antifuses required for each interconnect path. The

proprietary architecture limits the number of antifuses per

path to a maximum of four, with 90 percent of interconnects

using only two antifuses.

Industrial

Min.

Max.

(Commercial Specification) x

0.69

1.11

T i m i n g C h a r a c t e r i s t i c s

C o m m e r c ia l W o r s t -C a s e t o T y p ic a l

Device timing characteristics fall into three categories:

family-dependent, device-dependent, and design-dependent.

The input and output buffer characteristics are common to

all MX devices. For mixed voltage of the A42MX devices, the

timing numbers are defined in the 3.3V section for I/Os while

for the internal logic resources, the timing numbers are

defined in the 5.0V section. Internal routing delays are

device-dependent. Design dependency means actual delays

are not determined until after place-and-route of the user’s

design is complete. Delay values may then be determined by

using the Designer Series utility or by performing simulation

with post-layout delays.

Commerical Typical

(T_J= 25°C, V_CC= 5.0V)

(Commercial, Worst-Case

Condition) x

0.85

Note: This derating factor applies to all routing and propagation

delays.

C r it ic a l N e t s a n d Ty p i c a l N e t s

Propagation delays in this data sheet apply to typical nets.

The abundant routing resources in the MX architecture

allows for deterministic timing using Actel’s Designer Series

development tools, which include TDPR, a timing-driven

place-and-route tool. Using Timer, the designer can specify

timing-critical nets and system clock frequency. Using these

timing specifications, the place-and-route software

optimizes the layout of the design to meet the user’s

specifications.

3 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 2 M X T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s

(N o r m a liz e d t o T _J= 2 5 °C , V_{C C A}/V_{C C I}= 5 . 0 V)

Temperature

42MX

Voltage

–55°C

0.93

0.88

0.85

0.84

0.83

–40°C

0.95

0.90

0.87

0.86

0.85

0°C

1.05

1.00

0.96

0.95

0.94

25°C

1.09

1.03

1.00

0.97

0.96

70°C

1.25

1.18

1.15

1.12

1.10

85°C

1.29

1.22

1.18

1.14

1.13

125°C

1.41

1.34

1.29

1.28

1.26

4.50

4.75

5.00

5.25

5.50

(Normalized to T_J= 25°C, V_CCA/V_CCI= 5.0V)

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

–55 C

–40 C

0 C

25 C

70 C

85 C

125 C

4.50

4.75

5.00

5.25

5.50

Voltage (V)

Note: This derating factor applies to all routing and propagation delays.

v5 .1

3 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

4 0 M X T e m p e r a t u r e a n d V o l t a g e D e r a t i n g F a c t o r s

(N o r m a liz e d t o T _J= 2 5 °C , V_{C C A}/V _{C C I}= 5 . 0 V)

Temperature

40MX

Voltage

–55°C

0.89

0.84

0.82

0.80

0.79

–40°C

0.93

0.88

0.85

0.82

0°C

1.02

0.97

0.94

0.91

0.90

25°C

1.09

1.03

1.00

0.97

0.96

70°C

1.25

1.18

1.15

1.12

1.10

85°C

1.31

1.24

1.20

1.16

1.15

125°C

1.45

1.37

1.33

1.29

1.28

4.50

4.75

5.00

5.25

5.50

40MX Junction Temperature and Voltage Derating Curves

(Normalized to T_J= 25°C, V_CCA/V_CCI= 5.0V)

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

–55 C

–40 C

0 C

25 C

70 C

85 C

125 C

4.50

4.75

5.00

5.25

5.50

Voltage (V)

Note: This derating factor applies to all routing and propagation delays.

3 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P C I S y s t e m T i m i n g S p e c i f i c a t i o n

P C I M o d e l s

Table 3 and Table 4 list the critical PCI timing parameters

and the corresponding timing parameter for the MX

PCI-compliant devices.

Actel provides synthesizable VHDL and Verilog-HDL models

for a PCI Target interface, a PCI Target and Target+DMA

Master interface. Contact your Actel sales representative

for more details.

Table 3 • Clock Specification for 33 MHz PCI

PCI

A42MX24

A42MX36

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

T_CYC

T_HIGH

T_LOW

CLK Cycle Time

CLK High Time

CLK Low Time

30

11

—

4.0

1.9

—

4.0

1.9

—

ns

Table 4 • Timing Parameters for 33 MHz PCI

PCI

A42MX24

A42MX36

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

T_VAL

CLK to Signal Valid—Bused Signals

2

11

12

—

28

—

2.0

—

9.0

4.0

8.3¹

—

2.0

—

9.0

4.0

8.3¹

—

ns

T_VAL(PTP)CLK to Signal Valid—Point-to-Point

2

T_ON

Float to Active

2

—

T_OFF

T_SU

Active to Float

Input Set-Up Time to CLK—Bused Signals

Input Set-Up Time to CLK—Point-to-Point

Input Hold to CLK

7

1.5

0

1.5

0

T_SU(PTP)

T_H

10, 12

0

—

Note:

1. T_OFFis system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.

v5 .1

3 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.2

2.7

1.2

1.4

3.1

1.4

1.6

3.5

1.6

1.9

4.1

1.9

2.7

5.7

2.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.3

1.8

2.3

2.9

4.9

1.5

2.1

2.7

3.3

5.7

1.7

2.4

3.0

3.7

6.5

2.0

2.8

3.6

4.4

7.6

2.8

3.9

ns

5.0

6.1

10.6

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

3.1

0.0

3.1

0.0

3.5

0.0

3.5

0.0

4.0

0.0

4.0

0.0

4.7

0.0

4.7

0.0

6.6

0.0

6.6

0.0

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

3.3

3.8

4.3

5.0

7.0

ns

t_WASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

3.3

4.8

3.8

5.6

4.3

6.3

5.0

7.5

7.0

ns

t_A

Flip-Flop Clock Input Period

10.4

f_MAX

Flip-Flop (Latch) Clock

Frequency (FO = 128)

181

168

154

134

80

MHz

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.

3 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

0.7

0.6

0.8

0.7

0.9

0.8

1.1

1.0

1.5

1.3

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.1

2.6

3.1

3.6

5.7

2.4

3.0

3.6

4.2

6.6

2.2

3.4

4.1

4.8

7.5

3.2

4.0

4.8

5.6

8.8

4.5

5.6

ns

6.7

7.8

12.4

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input Low to HIGH

FO = 16

FO = 128

4.6

5.3

6.0

7.0

9.8

ns

Input High to LOW

FO = 16

FO = 128

4.8

5.6

6.3

7.4

10.4

Minimum Pulse Width HIGH FO = 16

FO = 128

2.2

2.4

2.6

2.7

2.9

3.1

3.4

3.6

4.8

5.1

ns

Minimum Pulse Width LOW FO = 16

FO = 128

2.2

2.4

2.6

2.7

2.9

3.01

3.4

3.6

4.8

5.1

ns

Maximum Skew

FO = 16

FO = 128

0.4

0.5

0.6

0.5

0.7

0.6

0.8

1.2

ns

Minimum Period

Maximum Frequency

FO = 16

FO = 128

4.7

4.8

5.4

5.6

6.1

6.3

7.2

7.5

10.0

10.4

ns

f_MAX

Note:

FO = 16

FO = 128

188

181

175

168

160

154

139

134

83

80

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5 .1

3 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.3

4.0

3.8

4.6

4.3

5.2

5.1

6.1

7.2

8.6

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

3.7

4.3

4.9

5.8

8.0

4.7

5.4

6.1

7.2

10.1

17.1

12.6

7.9

9.1

10.4

7.7

12.2

9.0

5.9

6.8

0.02

0.03

0.02

0.03

0.04

0.04 ns/pF

0.06 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.9

3.4

4.5

3.9

5.1

4.4

6.05

5.2

8.5

7.3

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Note:

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

3.4

3.9

4.4

5.2

7.3

4.9

5.6

6.4

7.5

10.5

17.0

12.6

7.9

9.1

10.4

7.7

12.2

9.0

5.9

6.8

0.03

0.02

0.04

0.02

0.04

0.03

0.05

0.03

0.07 ns/pF

0.04 ns/pF

1. Delays based on 35 pF loading.

3 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.7

3.7

1.7

2.0

4.3

2.0

2.3

4.9

2.3

2.7

5.7

2.7

3.7

8.0

3.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.0

2.7

3.4

4.2

7.1

2.2

3.1

3.9

4.8

8.2

2.5

3.5

4.4

5.4

9.2

3.0

4.1

4.2

5.7

ns

5.2

7.3

6.3

8.9

10.9

15.2

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

4.3

0.0

4.3

0.0

4.9

0.0

4.9

0.0

5.6

0.0

5.6

0.0

6.6

0.0

6.6

0.0

9.2

0.0

9.2

0.0

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.6

5.3

6.0

7.0

9.8

ns

t_WASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

4.6

6.8

5.3

7.8

6.0

8.9

7.0

9.8

ns

t_A

Flip-Flop Clock Input Period

10.4

14.6

f_MAX

Flip-Flop (Latch) Clock

Frequency (FO = 128)

109

101

92

80

48

MHz

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.

v5 .1

3 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

1.0

0.9

1.1

1.0

1.3

1.1

1.5

1.3

2.1

1.9

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.9

3.6

4.4

5.1

8.0

3.4

4.2

3.8

4.8

4.5

5.6

6.3

7.8

ns

5.0

5.7

6.7

9.4

5.9

6.7

7.8

11.0

17.3

9.26

10.5

12.6

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input LOW to HIGH

FO = 16

FO = 128

6.4

7.4

8.3

9.8

13.7

ns

Input HIGH to LOW

FO = 16

FO = 128

6.7

7.8

8.8

10.4

14.5

Minimum Pulse Width

HIGH

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Minimum Pulse Width

LOW

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Maximum Skew

FO = 16

FO = 128

0.6

0.8

0.6

0.9

0.7

1.0

0.8

1.2

1.6

ns

Minimum Period

Maximum Frequency

FO = 16

FO = 128

6.5

6.8

7.5

7.8

8.5

8.9

10.1

10.4

14.1

14.6

ns

f_MAX

Note:

FO = 16

FO = 128

113

109

105

101

96

92

83

80

50

48

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 2 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

4.7

5.6

5.4

6.4

6.1

7.3

7.2

8.6

10.0

12.0

11.3

14.1

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

5.2

6.0

6.8

8.1

6.6

7.6

8.6

10.1

17.1

12.6

0.04

0.06

11.1

8.2

12.8

9.5

14.5

10.7

0.04

0.05

0.03

0.04

0.03

0.04

0.06 ns/pF

0.08 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

5.5

4.8

6.4

5.5

7.2

6.2

8.5

7.3

11.9

10.2

14.7

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Note:

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

4.7

5.5

6.2

7.3

6.8

7.9

8.9

10.5

17.1

12.6

0.07

0.04

11.1

8.2

12.8

9.5

14.5

10.7

0.06

0.04

0.05

0.03

0.05

0.03

0.10 ns/pF

0.06 ns/pF

1. Delays based on 35 pF loading.

v5 .1

3 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.2

2.3

1.2

1.4

3.1

1.4

1.6

3.5

1.6

1.9

4.1

1.9

2.7

5.7

2.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.2

1.9

2.4

2.9

5.0

1.6

2.2

2.8

3.4

5.8

1.8

2.5

3.2

3.9

6.6

2.1

2.9

3.7

4.5

7.8

3.0

4.1

ns

5.2

6.3

10.9

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

3.1

0.0

3.1

0.0

3.5

0.0

3.5

0.0

4.0

0.0

4.0

0.0

4.7

0.0

4.7

0.0

6.6

0.0

6.6

0.0

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

3.3

3.8

4.3

5.0

7.0

ns

t_WASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

3.3

4.8

3.8

5.6

4.3

6.3

5.0

7.5

7.0

ns

t_A

Flip-Flop Clock Input Period

10.4

f_MAX

Flip-Flop (Latch) Clock Frequency

(FO = 128)

181

167

154

134

80

MHz

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.

4 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

0.7

0.6

0.8

0.7

0.9

0.8

1.1

1.0

1.5

1.3

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.1

2.6

3.1

3.6

5.7

2.4

3.0

3.6

4.2

6.6

2.2

3.4

4.1

4.8

7.5

3.2

4.0

4.8

5.6

8.8

4.5

5.6

ns

6.7

7.8

12.4

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input LOW to HIGH

FO = 16

FO = 128

4.6

5.3

6.0

7.1

9.9

ns

Input HIGH to LOW

FO = 16

FO = 128

4.8

5.6

6.3

7.5

10.4

Minimum Pulse Width HIGH FO = 16

FO = 128

2.2

2.4

2.6

2.7

2.9

3.1

3.4

3.6

4.8

5.1

ns

Minimum Pulse Width LOW FO = 16

FO = 128

2.2

2.4

2.6

2.7

2.9

3.1

3.4

3.6

4.8

5.1

ns

Maximum Skew

FO = 16

FO = 128

0.4

0.5

0.6

0.5

0.7

0.6

0.8

1.2

ns

Minimum Period

Maximum Frequency

FO = 16

FO = 128

4.7

4.8

5.4

5.6

6.1

6.3

7.2

7.5

10.1

10.4

ns

f_MAX

Note:

FO = 16

FO = 128

188

181

175

168

160

154

139

134

83

80

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5 .1

4 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.3

4.0

3.8

4.6

4.3

5.2

5.1

6.1

7.2

8.6

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

3.7

4.3

4.9

5.8

8.1

4.7

5.4

6.1

7.2

10.1

17.1

12.6

7.9

9.1

10.4

7.7

12.2

9.0

5.9

6.8

0.02

0.03

0.04

0.04 ns/pF

0.06 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.9

3.4

4.5

3.9

5.1

4.4

6.1

5.2

8.5

7.3

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Note:

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

3.4

3.9

4.4

5.2

7.3

4.9

5.6

6.4

7.5

10.5

17.1

12.6

7.9

9.1

10.4

7.7

12.2

9.0

5.0

6.8

0.03

0.02

0.04

0.02

0.04

0.03

0.05

0.03

0.07 ns/pF

0.04 ns/pF

1. Delays based on 35 pF loading.

4 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.7

3.7

1.7

2.0

4.3

2.0

2.3

4.9

2.3

2.7

5.7

2.7

3.7

8.0

3.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.9

2.7

3.4

4.1

7.1

2.2

3.1

3.9

4.8

8.1

2.5

3.5

4.4

5.4

9.2

3.0

4.1

4.2

5.7

ns

5.2

7.3

6.3

8.9

10.9

15.2

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch) Data Input Set-Up

4.3

0.0

4.3

0.0

5.0

0.0

5.0

0.0

5.6

0.0

5.6

0.0

6.6

0.0

6.6

0.0

9.2

0.0

9.2

0.0

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.6

5.3

5.6

7.0

9.8

ns

t_WASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

4.6

6.8

5.3

7.8

5.6

8.9

7.0

9.8

ns

t_A

Flip-Flop Clock Input Period

10.4

14.6

f_MAX

Flip-Flop (Latch) Clock Frequency

(FO = 128)

109

101

92

80

48

MHz

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.

v5 .1

4 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

1.0

0.9

1.1

1.0

1.3

1.1

1.5

1.3

2.1

1.9

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.9

3.6

4.4

5.1

8.0

3.34

4.2

5.0

5.9

9.3

3.8

4.8

4.5

5.6

6.3

7.8

ns

5.7

6.7

9.4

6.7

7.8

11.0

17.2

10.5

12.4

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input LOW to HIGH

FO = 16

FO = 128

6.4

7.4

8.4

9.9

13.8

ns

Input HIGH to LOW

FO = 16

FO = 128

6.8

7.8

8.9

10.4

14.6

Minimum Pulse Width

HIGH

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Minimum Pulse Width

LOW

FO = 16

FO = 128

3.1

3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Maximum Skew

FO = 16

FO = 128

0.6

0.8

0.6

0.9

0.7

1.0

0.8

1.2

1.6

ns

Minimum Period

Maximum Frequency

FO = 16

FO = 128

6.5

6.8

7.5

7.8

8.5

8.9

10.1

10.4

14.1

14.6

ns

f_MAX

Note:

FO = 16

FO = 128

113

109

105

101

96

92

83

80

50

48

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

4 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 0 M X 0 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V _{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

4.7

5.6

5.4

6.4

6.1

7.3

7.2

8.6

10.0

12.0

11.3

14.1

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

5.2

6.0

6.9

8.1

6.6

7.6

8.6

10.1

17.1

12.6

0.04

0.06

11.1

8.2

12.8

9.5

14.5

10.7

0.04

0.05

0.03

0.04

0.03

0.04

0.06 ns/pF

0.08 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

5.5

4.8

6.4

5.5

7.2

6.2

8.5

7.3

11.9

10.2

14.7

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Note:

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

4.7

5.5

6.2

7.3

6.8

7.9

8.9

10.5

17.1

12.6

0.07

0.04

11.1

8.2

12.8

9.5

14.5

10.7

0.06

0.04

0.05

0.03

0.05

0.03

0.10 ns/pF

0.06 ns/pF

1. Delays based on 35 pF loading.

v5 .1

4 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.2

1.3

1.2

1.3

1.4

1.6

1.5

1.6

1.8

1.9

1.8

2.1

2.5

2.7

2.6

2.9

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.7

0.9

1.2

1.4

2.3

0.8

1.0

1.3

1.5

2.6

0.9

1.2

1.5

1.7

2.9

1.0

1.4

1.7

2.0

3.4

1.4

1.9

2.4

2.9

4.8

ns

Logic Module Sequential Timing^{3, 4}

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.3

0.0

0.4

0.0

0.4

0.0

0.5

0.0

0.4

0.0

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.8

0.0

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

3.4

3.8

4.3

5.0

7.0

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

4.5

3.5

0.0

0.3

0.0

0.3

4.9

3.8

0.0

0.3

0.0

0.3

5.6

4.3

0.0

0.4

0.0

0.4

6.6

5.1

0.0

0.4

0.0

0.4

9.2

7.1

0.0

0.6

0.0

0.6

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

t_INH

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock

Frequency

268

244

224

195

117

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

4 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.0

0.8

1.3

1.2

0.9

1.4

1.3

1.0

1.6

1.2

1.9

2.2

1.7

2.7

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.0

2.3

2.5

2.8

3.7

2.2

2.5

2.8

3.1

4.1

2.5

2.9

3.2

3.5

4.7

3.0

3.4

3.7

4.1

5.5

4.2

4.7

5.2

5.7

7.7

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 256

2.4

2.7

3.0

3.4

3.6

4.0

5.0

5.5

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 256

3.5

3.9

4.3

4.4

4.9

5.2

5.7

7.3

8.0

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width

HIGH

FO = 32

FO = 256

1.2

1.3

1.4

1.5

1.7

1.8

2.0

2.5

2.7

ns

Minimum Pulse Width

LOW

FO = 32

FO = 256

1.2

1.3

1.4

1.5

1.7

1.8

2.0

2.5

2.7

ns

Maximum Skew

FO = 32

FO = 256

0.3

0.4

0.5

0.6

ns

Input Latch External

Set-Up

FO = 32

FO = 256

0.0

ns

Input Latch External Hold FO = 32

FO = 256

2.3

2.2

2.6

2.4

3.0

3.3

3.5

3.9

4.9

5.5

ns

Minimum Period

FO = 32

FO = 256

3.4

3.7

4.1

4.0

4.5

4.7

5.2

7.8

8.6

ns

f_MAX

Note:

Maximum Frequency

FO = 32

FO = 256

296

268

269

244

247

224

215

195

129

117

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5 .1

4 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.5

2.9

2.6

2.9

4.9

5.3

2.6

2.7

3.2

2.9

3.2

5.4

5.9

2.9

3.1

3.6

3.3

3.7

6.2

6.7

3.3

3.6

4.3

3.9

4.3

7.3

7.9

3.8

5.1

6.0

ns

5.5

6.1

10.2

11.1

5.3

G-to-Pad LOW

5.3

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

5.2

5.8

6.6

7.7

10.8

15.3

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

7.4

8.2

9.3

10.9

0.04

0.05

d_TLH

d_THL

Capacity Loading, LOW to HIGH

0.03

0.04

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

Capacity Loading, HIGH to LOW

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.4

2.9

2.7

2.9

4.9

5.3

4.2

2.7

3.2

2.9

3.2

5.4

5.9

4.6

3.1

3.6

3.3

3.7

6.2

6.7

5.2

3.6

4.3

3.9

4.3

7.3

7.9

6.1

5.1

6.0

ns

5.5

6.1

10.2

11.1

8.6

G-to-Pad LOW

8.6

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

5.2

5.8

6.6

7.7

10.8

15.3

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

7.4

8.2

9.3

10.9

0.04

0.05

d_TLH

d_THL

Note:

Capacity Loading, LOW to HIGH

Capacity Loading, HIGH to LOW

0.03

0.04

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

1. Delays based on 35 pF loading.

4 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.6

1.8

1.7

2.0

1.8

2.0

1.9

2.2

2.1

2.3

2.1

2.5

2.7

2.5

2.9

3.5

3.8

3.5

4.1

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.0

1.3

1.6

1.9

3.2

1.1

1.4

1.8

2.1

3.6

1.2

1.6

2.0

2.4

4.1

1.4

1.9

2.4

2.9

4.8

2.0

2.7

3.3

4.0

6.7

ns

Logic Module Sequential Timing ^{3, 4}

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.5

0.0

0.6

0.0

0.5

0.0

0.6

0.0

0.6

0.0

0.7

0.0

0.7

0.0

0.8

0.0

0.9

0.0

1.2

0.0

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.7

5.3

6.0

7.0

9.8

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

6.2

5.0

0.0

0.3

0.0

0.3

6.9

5.6

0.0

0.3

0.0

0.3

7.8

6.2

0.0

0.3

0.0

0.3

9.2

7.1

0.0

0.4

0.0

0.4

12.9

9.9

0.0

0.6

0.0

0.6

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

t_INH

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock

Frequency

161

146

135

117

70

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

v5 .1

4 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.5

1.2

1.8

1.6

1.3

2.0

1.8

1.4

2.3

2.17

1.7

3.0

2.4

3.7

ns

2.7

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.8

3.2

3.5

3.9

5.2

3.2

3.5

3.9

4.3

5.8

3.6

4.0

4.4

4.9

6.6

4.2

4.7

5.2

5.7

7.7

5.9

6.6

ns

7.3

8.0

10.8

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 256

4.1

4.5

5.0

5.1

5.6

6.0

6.7

8.4

9.3

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 256

5.0

5.4

5.5

6.0

6.2

6.8

7.3

8.0

10.2

11.2

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width

HIGH

FO = 32

FO = 256

1.7

1.9

2.1

2.3

2.5

2.7

3.5

3.8

ns

Minimum Pulse Width

LOW

FO = 32

FO = 256

1.7

1.9

2.1

2.3

2.5

2.7

3.5

3.8

ns

Maximum Skew

FO = 32

FO = 256

0.4

0.5

0.6

0.9

ns

Input Latch External

Set-Up

FO = 32

FO = 256

0.0

ns

Input Latch External Hold FO = 32

FO = 256

3.3

3.7

4.1

4.2

4.6

4.9

5.5

6.9

7.6

ns

Minimum Period

FO = 32

FO = 256

5.6

6.1

6.2

6.8

6.7

7.4

7.8

8.5

12.9

14.2

ns

f_MAX

Note:

Maximum Frequency

FO = 32

FO = 256

177

161

146

148

135

129

117

77

70

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

5 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 0 9 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.4

4.0

3.7

4.1

6.9

7.5

5.8

3.8

4.5

4.1

4.5

7.6

8.3

6.5

4.3

5.1

4.6

5.1

8.6

9.4

7.3

5.1

6.1

7.1

8.3

ns

5.5

7.6

6.1

8.5

10.2

11.1

8.6

14.2

15.5

12.0

G-to-Pad LOW

8.6

I/O Latch Set-Up

0.7

0.0

0.8

0.0

0.9

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.7

9.7

10.9

12.9

18.0

25.3

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

12.2

0.00

0.09

13.5

0.00

0.10

15.4

0.00

0.10

18.1

0.10

d_TLH

d_THL

Capacity Loading, LOW to HIGH

0.01 ns/pF

0.10 ns/pF

Capacity Loading, HIGH to LOW

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.4

4.1

3.7

4.1

6.9

7.5

5.8

3.8

4.5

4.1

4.5

7.6

8.3

6.5

5.5

4.2

4.6

5.1

8.6

9.4

7.3

6.4

5.0

9.0

7.0

ns

5.5

7.6

6.1

8.5

10.2

11.1

8.6

14.2

15.5

12.0

G-to-Pad LOW

8.6

I/O Latch Set-Up

0.7

0.0

0.8

0.0

0.9

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.7

9.7

10.9

12.9

18.0

25.3

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

12.2

0.04

0.05

13.5

0.04

0.05

15.4

0.05

0.06

18.1

0.06

0.07

d_TLH

d_THL

Note:

Capacity Loading, LOW to HIGH

Capacity Loading, HIGH to LOW

0.08 ns/pF

0.10 ns/pF

1. Delays based on 35 pF loading.

v5 .1

5 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.4

1.6

1.5

1.6

1.5

1.7

1.8

1.7

2.0

2.1

2.0

2.3

2.8

3.0

2.8

3.3

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.8

1.0

1.3

1.6

2.6

0.9

1.2

1.4

1.7

2.9

1.0

1.3

1.6

2.0

3.2

1.2

1.5

1.9

2.3

3.8

1.6

2.1

2.7

3.2

5.3

ns

Logic Module Sequential Timing^3,4

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.3

0.0

0.7

0.0

0.4

0.0

0.8

0.0

0.4

0.0

0.9

0.0

0.5

0.0

1.0

0.0

0.7

0.0

1.4

0.0

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

3.4

3.8

4.3

5.0

7.1

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

4.5

6.8

0.0

0.5

0.0

0.5

5.0

7.6

0.0

0.5

0.0

0.5

5.6

8.6

0.0

0.6

0.0

0.6

6.6

10.1

0.0

9.2

14.1

0.0

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

t_INH

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

0.7

1.0

0.0

0.7

1.0

Flip-Flop (Latch) Clock

Frequency

215

1955

1795

1565

94

MHz

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, point and position whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

5 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.1

0.8

1.4

1.2

0.9

1.6

1.3

1.0

1.8

1.6

1.2

2.1

2.2

1.7

2.9

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.8

2.1

2.3

2.6

3.6

2.0

2.3

2.6

3.0

4.0

2.3

2.6

3.0

3.3

4.6

2.7

3.1

3.5

3.9

5.4

4.0

4.3

4.9

5.4

7.5

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 384

2.6

2.9

3.2

3.3

3.6

3.9

4.3

5.4

6.0

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 384

3.8

4.5

4.2

5.0

4.8

5.6

6.6

7.8

9.2

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width

HIGH

FO = 32

FO = 384 3.7

3.2

3.5

4.1

4.0

4.59

4.7

5.4

6.6

7.6

ns

Minimum Pulse Width LOW FO = 32

3.2

3.5

4.1

4.0

4.6

4.7

5.4

6.6

7.6

ns

FO = 384 3.7

Maximum Skew

FO = 32

FO = 384

0.3

0.4

0.5

0.7

ns

Input Latch External Set-Up FO = 32

0.0

ns

FO = 384 0.0

Input Latch External Hold FO = 32

2.8

3.1

3.5

5.5

4.0

4.1

4.7

5.7

6.6

ns

FO = 384 3.2

Minimum Period

FO = 32

FO = 384 4.6

4.2

4.67

5.1

5.6

5.8

6.4

9.7

10.7

ns

f_MAX

Note:

Maximum Frequency

FO = 32

FO = 384

237

215

195

198

179

172

156

103

94

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5 .1

5 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.5

3.0

2.7

3.0

5.4

5.0

2.9

2.8

3.3

3.0

3.3

6.0

5.6

3.2

3.7

3.4

3.8

6.8

6.3

3.6

3.7

4.4

4.0

4.4

8.0

7.4

4.3

5.2

6.1

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

5.6

6.2

11.2

10.4

6.0

G-to-Pad LOW

6.0

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

5.7

6.3

7.1

8.4

11.9

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.0

8.9

10.1

0.03

0.04

11.9

0.04

0.05

16.7

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.2

2.5

2.7

3.0

5.4

5.0

5.1

3.6

2.7

3.0

3.3

6.0

5.6

4.0

3.1

3.4

3.8

6.8

6.3

6.4

4.7

3.6

4.0

4.4

8.0

7.4

7.5

6.6

5.1

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

5.6

6.2

11.2

10.4

10.5

G-to-Pad LOW

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

5.7

6.3

7.1

8.4

11.9

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.0

8.9

10.1

0.03

0.04

11.9

0.04

0.05

16.7

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

1. Delays based on 35 pF loading.

5 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.9

2.0

1.9

2.2

2.1

2.2

2.1

2.4

2.5

2.4

2.8

3.0

2.8

3.3

4.0

4.2

4.0

4.6

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.1

1.5

1.8

2.2

3.6

1.2

1.6

2.0

2.4

4.0

1.4

1.8

2.3

2.7

4.5

1.6

2.1

2.7

3.2

5.3

2.3

3.0

3.8

4.5

7.5

ns

Logic Module Sequential Timing^{3, 4}

t_SUD

Flip-Flop (Latch) Data Input Set-Up

0.5

0.0

1.0

0.0

0.5

0.0

1.1

0.0

0.6

0.0

1.2

0.0

0.7

0.0

1.4

0.0

0.9

0.0

2.0

0.0

ns

t_HD

Flip-Flop (Latch) Data Input Hold

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.8

5.3

6.0

7.1

9.9

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

6.2

9.5

0.0

0.7

0.0

0.7

6.9

10.6

0.0

0.8

0.0

0.8

7.9

12.0

0.0

9.2

14.1

0.0

12.9

19.8

0.0

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

t_INH

ns

t_INSU

t_OUTH

t_OUTSU

f_MAX

Notes:

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock Frequency

0.9

1.01

0.0

1.4

ns

0.0

ns

0.89

1.01

1.4

ns

129

117

108

94

56

MHz

1. For dual-module macros use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

v5 .1

5 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.5

1.1

2.0

1.6

1.3

2.2

1.9

1.4

2.5

2.2

1.7

2.9

3.1

2.4

4.1

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.6

2.9

3.3

3.6

5.1

2.9

3.2

3.6

4.0

5.6

3.2

3.7

4.1

4.6

6.4

3.8

4.3

4.9

5.4

7.5

5.3

6.1

ns

6.8

7.6

10.5

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 384

4.4

4.8

5.3

5.5

6.0

6.5

7.1

9.0

9.9

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 384

5.3

6.2

5.9

6.9

6.7

7.9

7.8

9.2

11.0

12.9

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width

HIGH

FO = 32

FO = 384

5.7

6.6

6.3

7.4

7.1

8.3

8.4

9.8

11.8

13.7

ns

Minimum Pulse Width

LOW

FO = 32

FO = 384

5.3

6.2

5.9

6.9

6.7

7.9

7.8

9.2

11.0

12.9

ns

Maximum Skew

FO = 32

FO = 384

0.5

2.2

0.5

2.4

0.6

2.7

0.7

3.2

1.0

4.5

ns

Input Latch External

Set-Up

FO = 32

FO = 384

0.0

ns

Input Latch External Hold FO = 32

FO = 384

3.9

4.5

4.3

4.9

5.6

5.7

6.6

8.0

9.2

ns

Minimum Period

FO = 32

FO = 384

7.0

7.7

7.8

8.6

8.4

9.3

9.7

10.7

16.2

17.8

ns

f_MAX

Note:

Maximum Frequency

FO = 32

FO = 384

142

129

117

119

108

103

94

62

56

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

5 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 1 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

TTL Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.5

4.1

3.8

4.2

7.6

7.0

4.8

3.9

4.6

4.2

4.6

8.4

7.8

5.3

4.4

5.2

4.8

5.3

9.5

8.8

6.0

5.2

6.1

7.3

8.6

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

5.6

7.8

6.2

8.7

11.2

10.4

7.2

15.7

14.5

10.0

G-to-Pad LOW

7.2

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.0

8.9

10.1

11.9

16.7

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

11.3

0.04

0.05

12.5

0.04

0.05

14.2

0.05

0.06

16.7

0.06

0.07

23.3

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.08 ns/pF

0.10 ns/pF

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.5

3.4

3.8

4.2

7.6

7.0

7.1

5.0

3.8

4.2

4.6

8.4

7.8

7.9

5.6

4.3

4.8

5.3

9.5

8.8

8.9

6.6

5.1

9.3

7.1

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LCO

5.6

7.8

6.2

8.7

11.2

10.4

10.5

15.7

14.5

14.7

G-to-Pad LOW

I/O Latch Clock-to-Out (Pad-to-Pad),

64 Clock Loading

8.0

8.9

10.1

11.9

16.7

ns

t_ACO

Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

11.3

0.04

0.05

12.5

0.04

0.05

14.2

0.05

0.06

16.7

0.06

0.07

23.3

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.08 ns/pF

0.10 ns/pF

1. Delays based on 35 pF loading.

v5 .1

5 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 2 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.2

1.4

1.3

1.6

1.5

1.8

2.1

2.5

3.0

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.8

1.0

1.3

1.5

2.4

0.9

1.2

1.4

1.7

2.7

1.0

1.3

1.6

1.9

3.0

1.2

1.5

1.9

2.2

3.6

1.7

2.1

2.6

3.1

5.0

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

1.3

1.2

1.4

1.3

1.6

1.5

1.9

1.8

2.7

2.5

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.3

0.0

0.4

0.0

0.4

0.0

0.5

0.0

0.7

0.0

t_H

t_RO

1.4

1.6

1.8

2.1

2.9

t_SUENA

t_HENA

t_WCLKA

0.4

0.0

0.5

0.0

0.5

0.0

0.6

0.0

0.8

0.0

Flip-Flop (Latch) Clock Active Pulse

Width

3.3

4.4

3.7

4.8

4.2

5.3

4.9

6.5

6.9

9.0

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

5 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A4 2 MX2 4 T im in g C h a r a c t e r is t ic s (N o m in a l 5 . 0 V O p e r a t io n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.0

1.3

1.1

1.4

1.3

1.6

1.5

1.9

2.1

2.6

ns

0.0

0.5

4.7

0.0

0.5

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.7

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.8

2.1

2.3

2.5

3.4

2.0

2.3

2.5

2.8

3.8

2.3

2.6

2.9

3.2

4.3

2.7

3.1

3.4

3.7

5.1

3.8

4.3

4.8

5.2

7.1

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=486

2.6

2.9

3.2

3.3

3.6

3.9

4.3

5.4

5.9

ns

t_CKL

Input HIGH to LOW

FO=32

FO=486

3.7

4.3

4.1

4.7

4.6

5.4

6.3

7.6

8.8

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH FO=32

FO=486

2.2

2.4

2.6

2.7

3.0

3.2

3.5

4.5

4.9

ns

Minimum Pulse Width LOW FO=32

FO=486

2.2

2.4

2.6

2.7

3.0

3.2

3.5

4.5

4.9

ns

Maximum Skew

FO=32

0.5

0.6

0.7

0.8

1.1

ns

FO=486

Input Latch External Set-Up FO=32

FO=486

0.0

ns

Input Latch External Hold

FO=32

2.8

3.3

3.1

3.7

3.5

4.2

4.1

4.9

5.7

6.9

ns

FO=486

Minimum Period (1/f_MAX

)

FO=32

4.7

5.1

5.2

5.7

6.2

6.5

7.1

10.9

11.9

ns

FO=486

f_MAX

Note:

Maximum Datapath

Frequency

FO=32

FO=486

210

193

191

175

176

161

153

140

92

84

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5 .1

5 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A4 2 MX2 4 T im in g C h a r a c t e r is t ic s (N o m in a l 5 . 0 V O p e r a t io n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

2.4

2.8

2.5

2.8

5.2

4.8

2.9

2.7

3.2

2.8

3.1

5.7

5.3

3.2

3.1

3.6

3.2

3.5

6.5

6.0

3.6

4.2

3.8

4.2

7.6

7.1

4.3

5.1

5.9

5.3

5.9

10.7

9.9

6.0

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

G-to-Pad LOW

I/O Latch Output Set-Up

I/O Latch Output Hold

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LH

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

t_LCO

5.6

6.1

6.9

8.1

11.4

22.0

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

32 I/O

t_ACO

10.6

0.04

0.03

11.8

0.04

0.03

13.4

0.04

0.03

15.7

0.05

0.04

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.07 ns/pF

0.06 ns/pF

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.1

2.4

2.5

2.8

5.2

4.8

4.9

3.5

2.6

2.8

3.1

5.7

5.3

5.4

3.9

3.0

3.2

3.5

6.5

6.0

6.2

4.6

3.5

3.8

4.2

7.6

7.1

7.2

6.4

4.9

ns

5.3

5.8

10.7

9.9

10.1

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LH

I/O Latch Hold

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

t_LCO

5.5

6.1

6.9

8.1

11.3

22.0

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

32 I/O

t_ACO

10.6

0.04

0.03

11.8

0.04

0.03

13.4

0.04

0.03

15.7

0.05

0.04

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.07 ns/pF

0.06 ns/pF

1. Delays based on 35 pF loading.

6 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 2 4 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

2.0

1.1

1.8

2.2

2.1

2.5

3.0

3.4

4.2

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

1.7

2.0

1.1

1.5

1.8

1.3

1.6

2.0

2.3

3.7

1.4

1.8

2.2

2.6

4.2

1.7

2.1

2.6

3.1

5.0

2.3

3.0

3.7

4.3

7.0

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

2.1

3.4

2.0

1.9

2.3

2.1

2.7

2.5

3.7

3.4

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.9

0.0

t_H

t_RO

2.0

2.2

2.5

2.9

4.1

t_SUENA

t_HENA

t_WCLKA

0.6

0.0

0.6

0.0

0.7

0.0

0.8

0.0

1.2

0.0

Flip-Flop (Latch) Clock Active Pulse

Width

4.6

6.1

5.2

6.8

5.8

7.7

6.9

9.0

9.6

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

12.6

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

v5 .1

6 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A4 2 MX 2 4 T im in g C h a r a c t e r is t ic s (N o m in a l 3 . 3 V O p e r a t io n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.4

1.8

1.6

1.9

1.8

2.2

2.6

3.0

3.6

ns

0.0

0.7

6.5

0.0

0.7

7.3

0.0

0.8

8.2

0.0

1.0

9.7

0.0

1.4

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

13.5

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.6

2.9

3.2

3.5

4.8

2.9

3.2

3.6

3.9

5.3

3.2

3.6

4.0

4.4

6.1

3.8

4.3

4.8

5.2

7.1

5.3

6.0

ns

6.6

7.3

10.0

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=486

4.4

4.8

5.3

5.5

6.0

6.5

7.1

9.1

10.0

ns

t_CKL

Input HIGH to LOW

FO=32

FO=486

5.1

6.0

5.7

6.6

6.4

7.5

7.6

8.8

10.6

12.4

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH FO=32

FO=486

3.0

3.3

3.7

3.8

4.2

4.5

4.9

6.3

6.9

ns

Minimum Pulse Width LOW FO=32

FO=486

3.0

3.3

3.4

3.7

3.8

4.2

4.5

4.9

6.3

6.9

ns

Maximum Skew

FO=32

0.8

1.0

1.1

1.6

ns

FO=486

Input Latch External Set-Up FO=32

FO=486

0.0

ns

Input Latch External Hold

FO=32

3.9

4.6

4.3

5.2

4.9

5.8

5.7

6.9

8.1

9.6

ns

FO=486

Minimum Period (1/f_MAX

)

FO=32

7.8

8.6

8.7

9.5

9.47

10.4

10.8

11.9

18.2

19.9

ns

FO=486

f_MAX

Note:

Maximum Datapath

Frequency

FO=32

FO=486

126

116

115

105

106

97

92

84

55

50

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

6 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A4 2 MX 2 4 T im in g C h a r a c t e r is t ic s (N o m in a l 3 . 3 V O p e r a t io n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3 Speed

Min. Max.

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

3.4

4.0

3.6

3.9

7.2

6.7

4.8

3.8

4.4

4.0

4.4

8.0

7.5

5.3

4.3

5.0

4.5

5.0

9.07

8.5

6.0

5.0

5.9

5.3

5.8

10.7

9.9

7.2

7.1

8.3

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

7.4

8.2

14.9

13.9

10.0

G-to-Pad LOW

I/O Latch Output Set-Up

I/O Latch Output Hold

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

7.67

8.5

9.6

11.3

15.9

30.8

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

14.8

0.05

0.04

16.5

0.05

0.04

18.7

0.06

0.05

22.0

0.07

0.06

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.10 ns/pF

0.08 ns/pF

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.8

3.5

3.6

3.4

7.2

6.7

6.8

5.3

3.9

4.0

8.0

7.5

7.6

5.5

4.1

4.5

5.0

9.01

8.5

8.6

6.4

4.9

9.0

6.8

ns

5.3

7.4

5.8

8.2

10.7

9.9

14.9

13.9

14.2

10.1

G-to-Pad LOW

I/O Latch Set-Up

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

7.7

8.5

9.6

11.3

15.9

30.8

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

14.8

0.05

0.04

16.5

0.05

0.04

18.7

0.06

0.05

22.0

0.07

0.06

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.10 ns/pF

0.08 ns/pF

1. Delays based on 35 pF loading.

v5 .1

6 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.3

1.6

1.5

1.8

1.7

2.0

2.4

2.7

3.3

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

0.9

1.3

1.6

2.0

3.3

0.3

1.0

1.4

1.8

2.2

3.7

0.4

1.2

1.6

2.0

2.5

4.2

0.4

1.4

1.9

2.4

2.9

4.9

0.5

2.0

2.7

3.4

4.1

6.9

0.7

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

1.3

1.4

1.6

1.9

2.7

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.3

0.0

0.34

0.0

0.4

0.0

0.5

0.0

0.7

0.0

t_H

t_RO

1.6

1.7

2.0

2.3

3.2

t_SUENA

t_HENA

t_WCLKA

0.7

0.0

0.8

0.0

0.9

0.0

1.0

0.0

1.4

0.0

Flip-Flop (Latch) Clock Active Pulse

Width

3.3

4.4

3.7

4.8

4.2

5.5

4.9

6.4

6.9

9.0

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

6 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

Logic Module Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Synchronous SRAM Operations

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

t_RC

Read Cycle Time

6.8

3.4

7.5

3.8

8.5

4.3

10.0

5.0

14.0

7.0

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock HIGH/LOW Time

Data Valid After Clock HIGH/LOW

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

3.4

3.78

4.3

5.0

7.0

1.6

0.0

0.6

3.4

2.7

0.0

2.8

0.0

1.8

0.0

0.7

3.8

3.0

0.0

3.1

0.0

2.0

0.0

0.8

4.3

3.4

0.0

3.5

0.0

2.4

0.0

0.9

5.0

4.0

0.0

4.1

0.0

3.4

0.0

1.3

7.0

5.6

0.0

5.7

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

8.1

9.0

10.2

12.0

16.8

ns

t_RDADV

t_ADSU

t_ADH

8.8

1.6

0.0

0.6

3.4

2.7

0.0

9.8

1.8

0.0

0.7

3.8

3.0

0.0

11.1

2.0

0.0

0.8

4.3

3.4

0.0

13.0

2.4

0.0

0.9

5.0

4.0

0.0

18.2

3.4

0.0

1.3

7.0

5.6

0.0

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

1.2

1.34

1.5

1.8

2.5

v5 .1

6 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.0

1.4

1.1

1.6

1.3

1.8

1.5

2.1

2.9

ns

0.0

0.5

4.7

0.0

0.5

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.7

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.0

2.3

2.6

3.0

4.3

2.2

2.6

2.9

3.3

4.8

2.5

2.9

3.3

3.8

5.5

2.9

3.4

3.9

4.4

6.4

4.1

4.8

5.5

6.2

9.0

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=635

2.7

3.0

3.3

3.4

3.8

4.0

4.4

5.6

6.2

ns

t_CKL

Input HIGH to LOW

FO=32

FO=635

3.8

4.9

4.2

5.4

4.8

6.1

5.6

7.2

7.8

10.1

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH FO=32

1.8

2.0

2.2

2.5

2.6

2.9

3.6

4.1

ns

FO=635 2.0

Minimum Pulse Width LOW FO=32

1.8

2.0

2.2

2.5

2.6

2.9

3.6

4.1

ns

FO=635 2.0

Maximum Skew

FO=32

0.8

0.9

1.0

1.4

ns

FO=635

Input Latch External Set-Up FO=32

0.0

ns

FO=635 0.0

Input Latch External Hold

FO=32 2.8

3.2

3.7

3.6

4.2

4.9

5.9

6.9

ns

FO=635 3.3

Minimum Period (1/f_MAX

)

FO=32 5.5

6.1

6.6

7.2

7.6

8.3

12.7

13.8

ns

FO=635 6.0

f_HMAX

Note:

Maximum Datapath

Frequency

FO=32

FO=635

180

166

164

151

139

131

121

79

73

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

6 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 4 . 7 5 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

2.6

3.0

2.7

3.0

5.3

4.9

2.9

2.8

3.3

3.0

3.3

5.8

5.5

3.3

3.2

3.7

3.3

3.7

6.6

6.2

3.7

3.8

4.4

3.9

4.3

7.8

7.3

4.4

5.3

6.2

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

5.5

6.1

10.9

10.2

6.1

G-to-Pad LOW

6.1

I/O Latch Output Set-Up

I/O Latch Output Hold

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

5.7

6.3

7.1

8.4

11.8

16.1

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

7.8

8.6

9.8

11.5

0.10

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.07

0.08

0.09

0.14 ns/pF

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.5

2.5

2.7

2.9

5.3

4.9

5.0

3.9

2.7

3.0

3.3

5.8

5.5

5.6

4.5

3.1

3.3

3.7

6.6

6.2

6.3

5.2

3.6

3.9

4.3

7.8

7.3

7.5

7.3

5.1

ns

5.5

6.1

10.9

10.2

10.4

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

5.7

6.3

7.1

8.4

11.8

16.1

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

7.78

0.07

8.6

9.8

11.5

0.10

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.08

0.09

0.14 ns/pF

1. Delays based on 35 pF loading.

v5 .1

6 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e C o m m e r c i a l C o n d it i o n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.9

2.2

2.1

2.5

2.3

2.8

2.7

3.3

3.8

4.7

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

1.3

1.8

2.3

2.8

4.6

0.5

1.5

2.0

2.5

3.1

5.2

0.5

1.7

2.3

2.8

3.5

5.8

0.6

2.0

2.7

3.4

4.1

6.9

0.7

2.7

3.7

4.7

5.7

9.6

1.0

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

1.8

2.0

2.3

2.7

3.7

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.9

0.0

t_H

t_RO

2.2

2.4

2.7

3.2

4.5

t_SUENA

t_HENA

t_WCLKA

1.0

0.0

1.1

0.0

1.2

0.0

1.4

0.0

2.0

0.0

Flip-Flop (Latch) Clock Active Pulse

Width

4.6

6.1

5.2

6.8

5.8

7.7

6.9

9.0

9.6

ns

t_WASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

12.6

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

6 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

Logic Module Timing

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Synchronous SRAM Operations

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

t_RC

Read Cycle Time

9.5

4.8

10.5

5.3

11.9

6.0

14.0

7.0

19.6

9.8

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock HIGH/LOW Time

Data Valid After Clock HIGH/LOW

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

4.8

5.3

6.0

7.0

9.8

2.3

0.0

0.9

4.8

3.8

0.0

3.9

0.0

2.5

0.0

1.0

5.3

4.2

0.0

4.3

0.0

2.8

0.0

1.1

6.0

4.8

0.0

4.9

0.0

3.4

0.0

1.3

7.0

5.6

0.0

5.7

0.0

4.8

0.0

1.8

9.8

7.8

0.0

8.0

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

11.3

12.6

14.3

16.8

23.5

ns

t_RDADV

t_ADSU

t_ADH

12.3

2.3

0.0

0.9

4.8

3.8

0.0

13.7

2.5

0.0

1.0

5.3

4.2

0.0

15.5

2.8

0.0

1.1

6.0

4.8

0.0

18.2

3.4

0.0

1.3

7.0

5.6

0.0

25.5

4.8

0.0

1.8

9.8

7.8

0.0

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

1.8

2.0

2.1

2.5

3.5

v5 .1

6 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed ‘–2’ Speed ‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.4

2.0

1.6

2.2

1.8

2.5

2.1

2.9

3.0

4.1

ns

0.0

0.7

6.5

0.0

0.7

7.3

0.0

0.8

8.2

0.0

1.0

9.7

0.0

1.4

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

13.5

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.8

3.2

3.7

4.2

6.1

3.1

3.5

4.1

4.6

6.8

3.5

4.1

4.7

5.3

7.7

4.07

4.8

5.5

6.2

9.0

5.7

6.7

ns

7.7

8.7

12.6

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=635

4.6

5.0

5.1

5.6

5.7

6.3

6.7

7.4

9.3

10.3

ns

t_CKL

Input HIGH to LOW

FO=32

FO=635

5.3

6.8

5.9

7.6

6.7

8.6

7.8

10.1

11.0

14.1

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH FO=32

FO=635

2.5

2.8

2.7

3.1

3.5

3.6

4.1

5.1

5.7

ns

Minimum Pulse Width LOW FO=32

FO=635

2.5

2.8

2.7

3.1

3.5

3.6

4.1

5.1

5.7

ns

Maximum Skew

FO=32

1.0

1.2

1.3

1.5

2.2

ns

FO=635

Input Latch External Set-Up FO=32

FO=635

0.0

ns

Input Latch External Hold

FO=32

4.0

4.6

4.4

5.2

5.0

5.9

6.9

8.2

9.6

ns

FO=635

Minimum Period (1/f_MAX

)

FO=32

9.2

9.9

10.2

11.0

11.1

12.0

12.7

13.8

21.2

23.0

ns

FO=635

f_HMAX

Note:

Maximum Datapath

Frequency

FO=32

FO=635

108

100

98

91

90

83

79

73

47

44

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

7 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 7 0 °C )

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

3.6

4.2

3.7

4.1

7.34

6.9

4.9

4.0

4.6

4.2

4.6

8.2

7.6

5.5

4.5

5.2

4.7

5.2

9.3

8.7

6.2

5.3

6.2

7.4

8.6

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

5.5

7.7

6.1

8.5

10.9

10.2

7.3

15.3

14.3

10.2

G-to-Pad LOW

7.3

I/O Latch Output Set-Up

I/O Latch Output Hold

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

7.9

8.8

10.0

11.8

16.5

22.5

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

10.9

0.10

12.1

0.11

13.7

0.12

16.1

0.14

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.20 ns/pF

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.9

3.4

3.7

4.1

7.4

6.9

7.0

5.5

3.8

4.1

4.6

8.2

7.6

7.8

6.2

4.3

4.7

5.2

9.3

8.7

8.9

7.3

5.1

10.3

7.1

ns

5.5

7.7

6.1

8.5

10.9

10.2

10.4

15.3

14.3

14.6

G-to-Pad LOW

I/O Latch Set-Up

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

7.9

8.8

10.0

11.8

16.5

22.5

ns

Array Latch Clock-to-Out

(Pad-to-Pad)

t_ACO

32 I/O

10.9

0.10

12.1

0.11

13.7

0.12

16.1

0.14

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.20 ns/pF

1. Delays based on 35 pF loading.

v5 .1

7 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n )

( Wo r s t -C a s e M il it a r y C o n d it io n s , V_{C C}= 4 . 5 V, T _J= 1 2 5 °C )

‘–2’ Speed ‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.5

1.8

1.7

2.0

2.4

2.7

3.3

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

1.0

1.4

1.8

2.2

3.7

0.4

1.2

1.6

2.0

2.5

4.2

0.4

1.4

1.9

2.4

2.9

4.9

0.5

2.0

2.7

3.4

4.1

6.9

0.7

ns

Logic Module Sequential Timing ^{3, 4}

t_CO

Flip-Flop Clock-to-Output

1.4

1.6

1.9

2.7

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

0.4

0.0

0.4

0.0

0.5

0.0

0.7

0.0

t_H

t_RO

1.7

2.0

2.3

3.2

t_SUENA

t_HENA

t_WCLKA

t_WASYN

0.8

0.0

3.7

0.9

0.0

4.2

1.0

0.0

4.9

1.4

0.0

6.9

Flip-Flop (Latch) Asynchronous Pulse

Width

4.8

5.5

6.4

9.0

ns

Notes:

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate..

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

7 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s , V_{C C}= 4 . 5 V, T _J= 1 2 5 °C )

Logic Module Timing

‘–2’ Speed

Min. Max.

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Parameter Description

Synchronous SRAM Operations

Min.

Max.

Min.

Max. Units

t_RC

Read Cycle Time

7.5

3.8

8.5

4.3

10.0

5.0

14.0

7.0

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock HIGH/LOW Time

Data Valid After Clock HIGH/LOW

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

3.8

4.3

5.0

7.0

ns

1.8

0.0

0.7

3.8

3.0

0.0

3.1

0.0

2.0

0.0

0.8

4.3

3.4

0.0

3.5

0.0

2.4

0.0

0.9

5.0

4.0

0.0

4.1

0.0

3.4

0.0

1.3

7.0

5.6

0.0

5.7

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

9.0

10.2

12.0

16.8

ns

t_RDADV

t_ADSU

t_ADH

9.8

1.8

0.0

0.7

3.8

3.0

0.0

11.1

2.1

0.0

0.8

4.3

3.4

0.0

13.0

2.4

0.0

0.9

5.0

4.0

0.0

18.2

3.4

0.0

1.3

7.0

5.6

0.0

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

1.4

1.5

1.8

2.5

v5 .1

7 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s , V_{C C}= 4 . 5 V, T _J= 1 2 5 °C )

‘–2’ Speed ‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

Min.

Max.

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.1

1.6

1.3

1.8

1.5

2.1

2.9

ns

0.0

0.5

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.7

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

2.2

2.6

2.9

3.3

4.8

2.5

2.9

3.3

3.8

5.5

2.9

3.4

3.9

4.4

6.4

4.1

4.8

5.5

6.2

9.0

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=635

3.0

3.3

3.4

3.8

4.0

4.4

5.6

6.2

ns

t_CKL

Input HIGH to LOW

FO=32

FO=635

4.2

5.4

4.8

6.1

5.6

7.2

7.8

10.1

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

FO=32

FO=635

2.0

2.2

2.5

2.6

2.9

3.7

4.1

ns

FO=32

FO=635

2.0

2.2

2.5

2.6

2.9

3.7

4.1

ns

FO=32

FO=635

0.8

0.9

1.0

1.4

ns

Input Latch External Set-Up

Input Latch External Hold

FO=32

FO=635

0.0

ns

FO=32

FO=635

3.2

3.7

3.6

4.2

4.9

5.9

6.9

ns

Minimum Period (1/f_MAX

)

FO=32

FO=635

6.1

6.6

7.2

7.6

8.3

12.7

13.8

ns

f_HMAX

Note:

FO=32

FO=635

164

151

139

131

121

79

73

MHz

Maximum Datapath Frequency

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

7 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 5 . 0 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s , V_{C C}= 4 . 5 V, T _J= 1 2 5 °C )

‘–2’ Speed

Min. Max.

‘–1’ Speed

Min. Max.

‘Std’ Speed

‘–F’ Speed

Min. Max. Units

Parameter Description

Min.

Max.

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

2.8

3.3

3.0

3.3

5.8

5.5

3.3

3.2

3.7

3.3

3.7

6.6

6.2

3.7

3.8

4.4

3.9

4.3

7.8

7.3

4.4

5.3

6.2

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

5.5

6.1

11.0

10.2

6.1

G-to-Pad LOW

6.1

I/O Latch Output Set-Up

I/O Latch Output Hold

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

6.3

7.1

8.4

11.8

ns

t_ACO

Array Latch Clock-to-Out (Pad-to-Pad)

32 I/O

8.6

9.8

11.5

0.10

16.1

0.14

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

0.08

0.09

ns/pF

Capacitive Loading, HIGH to LOW

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.9

2.7

3.0

3.3

5.8

5.5

5.6

4.5

3.1

3.3

3.7

6.6

6.2

6.3

5.2

3.7

3.9

4.3

7.8

7.3

7.5

7.3

5.1

ns

5.5

6.1

10.9

10.2

10.4

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

6.3

7.1

8.4

11.8

ns

t_ACO

Array Latch Clock-to-Out (Pad-to-Pad)

32 I/O

8.6

9.78

0.09

11.5

0.10

16.1

0.14

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.08

ns/pF

1. Delays based on 35 pF loading.

v5 .1

7 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n )

( Wo r s t -C a s e M il it a r y C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 1 2 5 °C )

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

2.4

2.9

2.7

3.3

3.2

3.9

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

Decode-to-Output Routing Delay

1.7

2.3

2.9

3.6

6.0

6.7

2.0

2.6

3.3

4.0

6.8

0.8

2.3

3.1

3.9

4.7

8.0

0.9

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

2.4

2.7

3.1

ns

t_GO

Latch Gate-to-Output

t_SU

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

0.6

0.0

0.7

0.0

0.8

0.0

t_H

t_RO

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

Flip-Flop (Latch) Clock Active Pulse Width

Flip-Flop (Latch) Asynchronous Pulse Width

2.9

3.2

3.8

t_SUENA

t_HENA

t_WCLKA

t_WASYN

Notes:

1.3

0.0

6.0

7.9

1.4

0.0

6.8

8.9

1.7

0.0

8.0

10.5

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the Timer utility.

3. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold

timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input

subtracts (adds) to the internal setup (hold) time.

7 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 1 2 5 °C )

Logic Module Timing

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

Synchronous SRAM Operations

Min.

Max.

Min.

Max.

Min.

Max.

Units

t_RC

Read Cycle Time

12.1

6.1

13.8

6.9

16.2

8.1

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

t_ADH

Clock HIGH/LOW Time

Data Valid After Clock HIGH/LOW

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

6.2

7.0

8.2

2.9

0.0

3.2

0.0

1.2

6.9

5.5

0.0

5.6

0.0

3.9

0.0

1.5

8.1

6.4

0.0

6.6

0.0

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

6.1

4.8

0.0

4.9

0.0

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

14.7

16.6

19.5

ns

t_RDADV

t_ADSU

t_ADH

15.9

2.9

0.0

1.1

6.1

4.8

0.0

18.0

3.2

0.0

1.2

6.9

5.5

0.0

21.1

3.9

0.0

1.5

8.1

6.4

0.0

Address/Data Set-Up Time

Address/Data Hold Time

Read Enable Set-Up to Address Valid

Read Enable Hold

t_RENSUA

t_RENHA

t_WENSU

t_WENH

t_DOH

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

2.4

2.5

2.9

v5 .1

7 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 1 2 5 °C )

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.9

2.6

2.1

2.9

2.5

3.4

ns

0.0

0.8

8.4

0.0

0.9

9.5

0.0

1.1

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

11.2

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

3.6

4.2

4.8

5.4

7.9

4.0

4.7

5.4

6.1

8.9

4.8

5.6

ns

6.4

7.2

10.5

Global Clock Network

t_CKHInput LOW to HIGH

FO=32

FO=635

5.9

6.5

6.7

7.3

7.8

8.6

ns

t_CKL

Input HIGH to LOW

FO=32

FO=635

6.9

8.8

7.8

10.0

9.1

11.7

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width HIGH

Minimum Pulse Width LOW

Maximum Skew

FO=32

FO=635

3.1

3.5

4.0

4.2

4.7

ns

FO=32

FO=635

3.1

3.5

4.0

4.2

4.7

ns

FO=32

FO=635

1.4

1.6

1.8

ns

Input Latch External Set-Up

Input Latch External Hold

FO=32

FO=635

0.0

ns

FO=32

FO=635

5.1

5.9

5.8

6.7

6.8

7.9

ns

Minimum Period (1/f_MAX

)

FO=32

FO=635

11.8

12.7

12.8

13.8

14.7

15.9

ns

f_HMAX

Note:

Maximum Datapath Frequency FO=32

FO=635

85

78

71

67

62

MHz

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

7 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

A 4 2 M X 3 6 T i m i n g C h a r a c t e r i s t i c s ( N o m i n a l 3 . 3 V O p e r a t i o n ) (c o n t in u e d )

(Wo r s t -C a s e Milit a r y C o n d it io n s , V_{C C}= 3 . 0 V, T _J= 1 2 5 °C )

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

Parameter Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

TTL Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

4.6

5.3

4.8

5.3

9.5

8.9

6.3

5.2

6.1

6.2

7.2

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

5.4

6.4

6.0

7.1

10.8

10.0

7.2

12.7

11.8

8.4

G-to-Pad LOW

7.2

8.4

I/O Latch Output Set-Up

I/O Latch Output Hold

0.8

0.0

0.9

0.0

1.1

0.0

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

10.2

11.6

13.7

ns

t_ACO

Array Latch Clock-to-Out (Pad-to-Pad)

32 I/O

14.0

0.13

15.9

0.14

18.7

0.16

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

ns/pF

Capacitive Loading, HIGH to LOW

CMOS Output Module Timing¹

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

6.4

4.5

4.8

5.3

9.5

8.9

9.1

7.3

5.1

8.5

5.9

ns

5.5

6.4

6.0

7.1

10.8

10.0

10.3

12.7

11.8

12.1

G-to-Pad LOW

I/O Latch Set-Up

0.8

0.0

0.9

0.0

1.1

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out (Pad-to-Pad)

32 I/O

10.2

13.7

ns

t_ACO

Array Latch Clock-to-Out (Pad-to-Pad)

32 I/O

14.0

0.13

18.7

0.16

18.7

0.16

ns

d_TLH

d_THL

Note:

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

ns/pF

1. Delays based on 35 pF loading.

v5 .1

7 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P i n D e s c r i p t i o n s

C LK , C LK A,

accessible when the MODE pin is HIGH. This pin functions

as an I/O when the MODE pin is LOW.

C LK B

G lo b a l C lo c k (In p u t )

Q C LK A, B , C , D Q u a d r a n t C lo c k (In p u t /O u t p u t )

Quadrant clock inputs. When not used as a register control

signal, these pins can function as general-purpose I/Os.

TTL clock inputs for clock distribution networks. The clock

input is buffered prior to clocking the logic modules. This

pin can also be used as an I/O.

S DI

S e r ia l Da t a In p u t (In p u t )

DC LK

Dia g n o s t ic C lo c k (In p u t )

Serial data input for diagnostic probe and device

programming. SDI is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

TTL clock input for diagnostic probe and device

programming. DCLK is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

S DO , T DO ,

G N D

G r o u n d (In p u t )

I/O

S e r ia l Da t a (O u t p u t )

Input LOW supply voltage.

Serial data output for diagnostic probe and device

programming. SDO is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

SDO is not available for 40MX devices.

I/O

In p u t /O u t p u t (In p u t , O u t p u t )

Input, output, tri-state, or bi-directional buffer. Input and

output levels are compatible with standard TTL and CMOS

specifications. Unused I/O pins are automatically driven

LOW by the Designer Series software.

T C K

Te s t C lo c k

Clock signal to shift the Boundary Scan Test (BST) data into

the device. This pin functions as an I/O when the test fuse is

not programmed. BST pins are only available in the

A42MX24, A42MX24A, and A42MX36 devices.

LP

Lo w P o w e r Mo d e

Controls the low power mode of all 42MX devices. This pin

must be set HIGH to switch the device to low power mode.

To exit the LOW power mode, the LP pin must be set LOW.

T DI

Te s t Da t a In

Serial data input for BST instructions and data. Data is

shifted in on the rising edge of TCK. This pin functions as an

I/O when the test fuse is not programmed. BST pins are only

available in the A42MX24 and A42MX36 devices.

MO DE

Mo d e (In p u t )

Controls the use of multifunction pins (DCLK, PRA, PRB,

SDI, TDO). To provide verification capability, the MODE pin

should be held HIGH. To facilitate this, the MODE pin

should be terminated to GND through a 10K¾ resistor so

that the MODE pin can be pulled HIGH when required.

T DO

Te s t Da t a O u t

Serial data output for BST instructions and test data. This

pin functions as an I/O when the test fuse is not

programmed. BST pins are only available in the A42MX24

and A42MX36 devices.

N C

N o C o n n e c t io n

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

T MS

Te s t Mo d e S e le c t

Serial data input for boundary scan test mode. Data is shifted

in on the rising edge of TCK. This pin functions as an I/O

when the test fuse is not programmed. BST pins are only

available in the A42MX24 and A42MX36 devices.

P R A, I/O

P r o b e A (O u t p u t )

The Probe A pin is used to output data from any

user-defined design node within the device. This

independent diagnostic pin can be used in conjunction with

the Probe B pin to allow real-time diagnostic output of any

signal path within the device. The Probe A pin can be used

as a user-defined I/O when verification has been completed.

The pin's probe capabilities can be permanently disabled to

protect programmed design confidentiality. PRA is

accessible when the MODE pin is HIGH. This pin functions

as an I/O when the MODE pin is LOW.

V _{C C}

S u p p ly Vo lt a g e (In p u t )

Input HIGH supply voltage.

V _{C C A}

S u p p ly Vo lt a g e (In p u t )

Input HIGH supply voltage, supplies array core only.

V _{C C I}

S u p p ly Vo lt a g e (In p u t )

Input HIGH supply voltage, supplies I/O cells only.

WD

Wid e De c o d e O u t p u t

P R B , I/O

P r o b e B (O u t p u t )

When a wide decode module is used in a 42MX device, this

pin can be used as a dedicated output from the wide decode

module. This direct connection eliminates additional

interconnect delays associated with regular logic modules.

To implement the direct I/O connection, connect an output

buffer of any type to the output of the wide decode macro

and place this output on one of the reserved WD pins.

The Probe B pin is used to output data from any

user-defined design node within the device. This

independent diagnostic pin can be used in conjunction with

the Probe A pin to allow real-time diagnostic output of any

signal path within the device. The Probe B pin can be used

as a user-defined I/O when verification has been completed.

The pin’s probe capabilities can be permanently disabled to

protect programmed design confidentiality. PRB is

8 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s

4 4 -P in P LC C

1 44

44-Pin

PLCC

4 4 -p in P L C C

A40MX02

Function

A40MX04

Function

A40MX02

Function

A40MX04

Function

Pin Number

1

2

I/O

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

I/O

3

V_CC

I/O

V_CC

I/O

V_CC

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

GND

I/O

GND

I/O

GND

CLK, I/O

MODE

V_CC

GND

CLK, I/O

MODE

V_CC

I/O

V_CC

I/O

V_CC

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

v5 .1

8 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s

6 8 -P in P LC C

1 68

68-Pin

PLCC

6 8 -P i n P L C C

Number

A40MX02 A40MX04

Number

A40MX02 A40MX04

Number

A40MX02 A40MX04

Function

1

2

I/O

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

I/O

3

I/O

GND

I/O

GND

I/O

4

V_CC

I/O

V_CC

I/O

5

I/O

6

I/O

CLK, I/O

I/O

CLK, I/O

I/O

7

I/O

8

I/O

MODE

V_CC

MODE

V_CC

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

I/O

SDI, I/O

I/O

DCLK, I/O DCLK, I/O

I/O

PRA, I/O

PRB, I/O

I/O

PRA, I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

8 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

8 4 -P in P LC C

1

84

84-Pin

PLCC

v5 .1

8 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

8 4 -P i n P L C C

A40MX04 A42MX09 A42MX16 A42MX24

A40MX04 A42MX09 A42MX16

A42MX24

Function

Number Function Function Function Function

Number Function Function Function

1

I/O

V_CC

I/O

NC

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

CLKB, I/O CLKB, I/O CLKB, I/O

I/O I/O I/O

PRB, I/O PRB, I/O PRB, I/O

I/O

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O (WD)

I/O

2

3

I/O

4

V_CC

I/O

5

I/O

GND

I/O

GND

I/O

I/O (WD)

GND

I/O

6

I/O

7

I/O

GND

I/O

GND

I/O

GND

8

I/O

I/O (WD)

I/O

I/O (WD)

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

DCLK, I/O DCLK, I/O DCLK, I/O

I/O

SDO, I/O SDO, I/O SDO, TDO (WD)

I/O

MODE

I/O

MODE

I/O

MODE

I/O

GND

I/O

TCK, I/O

GND (LP)

V_CCA

V_CCI

I/O

GND (LP) GND (LP)

V_CCA

V_CCI

I/O

V_CCI

V_CCA

I/O

V_CCI

V_CCA

I/O

CLK, I/O

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

MODE

V_CC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

TMS, I/O

TDI, I/O

I/O (WD)

I/O

SDI, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

I/O (WD)

PRA, I/O

I/O

I/O (WD)

I/O

PRA, I/O PRA, I/O

I/O I/O

CLKA, I/O CLKA, I/O

V_CCAV_CCA

I/O

GND

I/O

CLKA, I/O

V_CCA

I/O

8 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 0 0 -P in P Q F P P a c k a g e (T o p Vie w )

100-Pin

PQFP

100

1

v5 .1

8 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

1 0 0 -P in P Q F P

A40MX02 A40MX04 A42MX09 A42MX16

Number Function Function Function Function

1

NC

I/O

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

I/O

V_CC

I/O

NC

V_CC

I/O

GND

I/O

V_CC

I/O

NC

I/O

V_CC

I/O

NC

V_CC

I/O

GND

I/O

V_CC

I/O

NC

V_CCA

I/O

V_CCA

I/O

2

DCLK, I/O DCLK, I/O

3

I/O

MODE

I/O

MODE

I/O

4

I/O

5

I/O

6

PRB, I/O PRB, I/O

I/O

7

I/O

GND

I/O

V_CC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

8

I/O

9

GND

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

I/O

GND

I/O

V_CC

I/O

NC

I/O

GND

I/O

SDO, I/O SDO, I/O

I/O

GND

I/O

GND

I/O

V_CCA

V_CCI

I/O

V_CCA

I/O

GND

I/O

GND

I/O

GND (LP) GND (LP)

I/O

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

V_CCA

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

8 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

1 0 0 -P in P Q F P ( C o n t in u e d )

A40MX02 A40MX04 A42MX09 A42MX16

Number Function Function Function Function

79

80

81

82

83

84

85

86

87

88

89

NC

I/O

NC

I/O

SDI, I/O

I/O

SDI, I/O

I/O

90

91

92

93

94

95

96

97

98

99

100

CLK, I/O CLK, I/O

V_CCA

I/O

V_CCA

I/O

MODE

V_CC

I/O

MODE

V_CC

I/O

CLKB, I/O CLKB, I/O

I/O I/O

PRB, I/O PRB, I/O

I/O

V_CC

I/O

GND

I/O

GND

I/O

NC

I/O

GND

I/O

GND

I/O

NC

I/O

GND

I/O

GND

I/O

NC

I/O

PRA, I/O PRA, I/O

I/O I/O

CLKA, I/O CLKA, I/O

SDI, I/O

I/O

DCLK, I/O DCLK, I/O

PRA, I/O PRA, I/O

I/O

v5 .1

8 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 6 0 -P in P Q F P P a c k a g e (T o p Vie w )

160

1

160-Pin

PQFP

8 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

1 6 0 -P in P Q F P

Number

A42MX09

Function

A42MX16

Function

A42MX24

Fucntion

Number

A42MX09

Function

A42MX16

Function

A42MX24

Fucntion

1

I/O

DCLK, I/O

NC

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

I/O

2

3

I/O

4

I/O

I/O (WD)

V_CCI

GND

I/O

GND

I/O

GND

I/O

5

I/O

6

NC

V_CCI

I/O

7

I/O

8

I/O

9

I/O

GND

I/O

GND

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

NC

I/O

GND

NC

GND

I/O

GND

I/O

NC

I/O

I/O (WD)

I/O

NC

V_CCA

I/O

V_CCA

I/O

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

V_CCA

V_CCI

GND

V_CCA

GND (LP)

I/O

V_CCA

V_CCI

GND

V_CCA

GND (LP)

I/O

V_CCA

V_CCI

GND

V_CCA

GND (LP)

TCK, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

V_CCA

CLKA, I/O

I/O

V_CCA

CLKA, I/O

I/O

V_CCA

CLKA, I/O

I/O

PRA, I/O

NC

PRA, I/O

I/O

PRA, I/O

I/O (WD)

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

I/O (WD)

GND

NC

GND

I/O

GND

I/O

GND

NC

GND

I/O

I/O (WD)

I/O

NC

V_CCI

I/O

V_CCI

NC

I/O

I/O (WD)

SDI, I/O

I/O

NC

I/O

SDI, I/O

I/O

SDI, I/O

I/O

NC

I/O

GND

v5 .1

8 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

1 6 0 -P in P Q F P ( C o n t in u e d )

Number

A42MX09

Function

A42MX16

Function

A42MX24

Fucntion

Number

A42MX09

Function

A42MX16

Function

A42MX24

Fucntion

81

82

I/O

SDO, I/O

I/O

SDO, I/O

I/O

SDO, TDO, I/O

I/O (WD)

I/O

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

I/O

83

I/O

84

I/O

NC

GND

I/O

85

I/O

GND

I/O

GND

I/O

86

NC

I/O

V_CCI

I/O

V_CCI

87

I/O

88

I/O

I/O (WD)

GND

I/O

89

GND

NC

I/O

GND

I/O

NC

GND

I/O

90

I/O

GND

I/O

GND

I/O

91

I/O

92

I/O

93

I/O

94

I/O

95

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

96

I/O

I/O (WD)

I/O

97

I/O

98

V_CCA

GND

NC

I/O

V_CCA

GND

I/O

V_CCA

GND

NC

V_CCI

GND

NC

I/O

V_CCA

V_CCI

GND

I/O

V_CCA

V_CCI

GND

I/O

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

I/O

NC

I/O

GND

NC

I/O

GND

I/O

GND

I/O

I/O (WD)

I/O

GND

NC

I/O

GND

I/O

GND

I/O

NC

GND

I/O

V_CCA

I/O

V_CCA

I/O

I/O (WD)

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

I/O (WD)

I/O

GND

I/O

GND

I/O

NC

I/O

TDI, I/O

TMS, I/O

GND

I/O

MODE

GND

MODE

GND

MODE

GND

9 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 0 8 -P in P Q F P P a c k a g e (T o p Vie w )

208

1

208-Pin PQFP

v5 .1

9 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 0 8 -P in P Q F P

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

1

GND

NC

MODE

I/O

GND

V_CCA

MODE

I/O

GND

V_CCA

MODE

I/O

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

NC

I/O

2

3

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

NC

GND

I/O

9

NC

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

I/O

GND

TMS, I/O

TDI, I/O

I/O

GND

TMS, I/O

TDI, I/O

I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

V_CCI

NC

I/O

V_CCI

I/O

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

QCLKA, I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

I/O (WD)

I/O

I/O (WD)

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

GND

V_CCA

NC

I/O

GND

V_CCA

V_CCI

I/O

GND

V_CCA

V_CCI

I/O

NC

I/O

9 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 0 8 -P in P Q F P ( C o n t in u e d )

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

85

86

I/O

I/O (WD)

I/O

I/O (WD)

I/O

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

I/O

TCK, I/O

GND (LP)

V_CCA

GND

V_CCI

V_CCA

I/O

TCK, I/O

GND (LP)

V_CCA

GND

V_CCI

V_CCA

I/O

87

I/O

GND (LP)

V_CCA

GND

V_CCI

V_CCA

I/O

88

I/O

89

NC

I/O

90

I/O

91

I/O

QCLKB, I/O

I/O

92

I/O

93

I/O

I/O (WD)

I/O

I/O (WD)

I/O

94

I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

95

NC

V_CCI

I/O

96

I/O

97

I/O

98

V_CCI

I/O

V_CCI

I/O

99

I/O

NC

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

I/O

I/O (WD)

I/O

I/O (WD)

I/O

SDO, I/O

I/O

SDO, TDO, I/O SDO, TDO, I/O

I/O

GND

V_CCA

I/O

GND

V_CCA

I/O

NC

I/O

GND

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

I/O (WD)

I/O

I/O (WD)

I/O

V_CCI

NC

V_CCI

I/O

V_CCI

I/O

NC

I/O

GND

I/O

I/O (WD)

v5 .1

9 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 0 8 -P in P Q F P ( C o n t in u e d )

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

Number

A42MX16

Function

A42MX24

Function

A42MX36

Function

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

I/O

I/O (WD)

I/O

I/O (WD)

I/O

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

I/O

I/O (WD)

I/O

I/O (WD)

I/O

NC

I/O

QCLKD, I/O

I/O

NC

I/O

NC

I/O (WD)

I/O

I/O (WD)

QCLKC, I/O

I/O

NC

I/O

I/O (WD)

PRA, I/O

I/O

I/O (WD)

PRA, I/O

I/O

NC

I/O

PRA, I/O

I/O

NC

I/O

CLKA, I/O

NC

CLKA, I/O

I/O

CLKA, I/O

I/O

NC

I/O

NC

V_CCI

I/O

V_CCI

V_CCA

GND

I/O

V_CCA

GND

V_CCA

I/O (WD)

I/O

I/O (WD)

I/O

GND

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

PRB, I/O

9 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 4 0 -P in P Q F P P a c k a g e (T o p Vie w )

240

1

•

240-Pin

PQFP

v5 .1

9 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 4 0 -P in P Q F P

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

1

I/O

DCLK, I/O

I/O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

I/O

81

82

I/O

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

GND

I/O

2

3

I/O

83

I/O

SDO, TDO, I/O

I/O

4

I/O

84

I/O

5

I/O

QCLKD, I/O

I/O

85

V_CCA

I/O

I/O (WD)

I/O

6

I/O (WD)

V_CCI

86

7

I/O (WD)

I/O

87

I/O

8

88

V_CCA

V_CCI

V_CCA

GND (LP)

TCK, I/O

I/O

V_CCI

I/O

9

I/O

89

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

I/O

90

I/O

91

I/O

V_CCI

I/O

92

I/O (WD)

I/O

93

I/O

I/O (WD)

I/O

94

GND

I/O

QCLKC, I/O

I/O

95

QCLKB, I/O

I/O

96

I/O

I/O (WD)

I/O

SDI, I/O

I/O

97

I/O

98

I/O

V_CCA

GND

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

I/O

I/O (WD)

I/O

I/O (WD)

I/O

PRB, I/O

I/O

CLKB, I/O

I/O

GND

I/O

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCI

V_CCA

GND

I/O

V_CCI

I/O

CLKA, I/O

I/O

PRA, I/O

I/O

I/O (WD)

I/O

V_CCA

GND

I/O

I/O (WD)

I/O

9 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 4 0 -P in P Q F P ( C o n t in u e d )

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

I/O

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

V_CCA

GND

I/O

V_CCI

I/O

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

I/O

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

I/O

I/O (WD)

I/O

QCLKA, I/O

I/O

V_CCA

I/O

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCI

I/O

I/O (WD)

I/O

GND

MODE

V_CCA

GND

TDI, I/O

TMS, I/O

GND

I/O

V_CCA

I/O

v5 .1

9 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P in As s ig n m e n t s (c o n t in u e d )

8 0 -P in VQ F P

80

1

80-Pin

VQFP

9 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

8 0 -P i n V Q F P

A40MX02

Function

A40MX04

Function

A40MX02

Function

A40MX04

Function

Pin Number

1

I/O

NC

I/O

GND

I/O

V_CC

I/O

NC

V_CC

I/O

GND

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

GND

I/O

V_CC

I/O

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

NC

I/O

2

3

NC

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

GND

I/O

8

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

CLK, I/O

I/O

CLK, I/O

I/O

MODE

V_CC

NC

MODE

V_CC

I/O

NC

I/O

NC

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

NC

SDI, I/O

DCLK, I/O

PRA, I/O

NC

PRB, I/O

I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

V_CC

I/O

V_CC

I/O

v5 .1

9 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 0 0 -P in V Q F P P a c k a g e ( T o p V ie w )

100

1

100-Pin

VQFP

1 0 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

1 0 0 -P in VQ F P P a c k a g e

A42MX09

Function

A42MX16

Function

A42MX09

Function

A42MX16

Function

Pin Number

1

I/O

MODE

I/O

MODE

I/O

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

I/O

2

3

4

I/O

5

I/O

GND

I/O

GND

I/O

6

I/O

7

GND

I/O

GND

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

I/O

GND (LP)

V_CCA

V_CCI

V_CCA

I/O

GND (LP)

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

I/O

NC

V_CCI

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

I/O

SDI, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

V_CCA

I/O

CLKA, I/O

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

SDO, I/O

DCLK, I/O

v5 .1

1 0 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 7 6 -P in T Q F P P a c k a g e (T o p Vie w )

176

1

176-Pin

TQFP

1 0 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

1 7 6 -P in T Q F P

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

1

GND

MODE

I/O

GND

MODE

I/O

GND

MODE

I/O

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

GND

I/O

GND

I/O

GND

TMS, I/O

TDI, I/O

I/O

2

3

I/O

4

I/O

5

I/O

I/O (WD)

I/O

6

I/O

7

I/O

8

NC

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

NC

I/O

NC

I/O

I/O (WD)

I/O

NC

I/O

V_CCA

I/O

V_CCA

I/O

NC

I/O

NC

I/O

I/O (WD)

I/O

NC

I/O

GND

NC

I/O

GND

I/O

GND

I/O

NC

I/O

NC

GND

NC

V_CCA

NC

V_CCI

NC

I/O

NC

GND

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCA

I/O

GND

V_CCA

I/O (WD)

I/O

V_CCA

I/O

V_CCA

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

I/O (WD)

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

I/O (WD)

I/O

NC

SDO, I/O

I/O

SDO, I/O

I/O

SDO, TDO, I/O

I/O

v5 .1

1 0 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

1 7 6 -P in T Q F P ( C o n t in u e d )

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

Number

A42MX09

Function

A42MX16

Function

A42MX24

Function

89

90

GND

I/O

GND

I/O

GND

I/O

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

GND

I/O

GND

I/O

GND

I/O

91

I/O

SDI, I/O

NC

SDI, I/O

I/O

SDI, I/O

I/O

92

I/O

93

I/O

I/O (WD)

I/O

94

I/O

95

I/O

96

NC

I/O

NC

V_CCI

I/O

V_CCI

97

I/O

98

I/O

99

I/O

NC

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

I/O

NC

I/O

I/O (WD)

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

NC

GND (LP)

V_CCA

GND

V_CCI

V_CCA

NC

I/O

GND

I/O

GND

I/O

I/O (WD)

PRA, I/O

I/O

NC

I/O

TCK, I/O

GND (LP)

V_CCA

GND

V_CCI

V_CCA

I/O

PRA, I/O

I/O

PRA, I/O

I/O

GND (LP)

V_CCA

GND

V_CCI

V_CCA

I/O

CLKA, I/O

V_CCA

GND

I/O

CLKA, I/O

V_CCA

GND

I/O

CLKA, I/O

V_CCA

GND

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

V_CCA

I/O

V_CCA

I/O

PRB, I/O

NC

PRB, I/O

I/O

PRB, I/O

I/O (WD)

I/O

NC

I/O

NC

I/O

NC

I/O (WD)

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

V_CCI

I/O

V_CCI

I/O

I/O (WD)

I/O

NC

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

1 0 4

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s

2 0 8 -P in C Q F P (T o p Vie w )

208 207 206 205 204 203 202 201 200

164 163 162 161 160 159 158 157

Pin #1

Index

1

2

3

4

5

6

7

8

156

155

154

153

152

151

150

149

A42MX36

208-Pin

CQFP

44

45

46

47

48

49

50

51

52

113

112

111

110

109

108

107

106

105

53 54 55 56 57 58 59 60 61

97 98 99 100 101 102 103 104

v5 .1

1 0 5

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 0 8 -P in C Q F P

A42MX36

Pin Number Function

A42MX36

Pin Number Function

A42MX36

Pin Number Function

1

GND

V_CCA

MODE

I/O

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

I/O

79

80

V_CCA

V_CCI

I/O

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

I/O

2

3

I/O

81

I/O

4

I/O

82

I/O

5

I/O

83

I/O

6

I/O

84

I/O

7

I/O

85

I/O (WD)

I/O

8

I/O

86

I/O

9

I/O

87

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

I/O

88

I/O

89

I/O

TCK, I/O

GND (LP)

V_CCA

GND

V_CCI

V_CCA

I/O

90

I/O

GND

TMS, I/O

TDI, I/O

I/O

91

QCLKB, I/O

I/O

92

I/O

93

I/O (WD)

I/O

94

V_CCA

I/O

95

I/O (WD)

I/O

96

I/O

97

I/O

V_CCA

I/O

98

V_CCI

I/O

V_CCI

I/O

99

I/O

GND

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

I/O (WD)

I/O

TDO, I/O

I/O

QCLKA, I/O

I/O (WD)

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCA

I/O

I/O (WD)

I/O

V_CCA

I/O

GND

I/O

GND

I/O

1 0 6

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 0 8 -P in C Q F P (C o n t in u e d )

A42MX36

Pin Number Function

A42MX36

Pin Number Function

A42MX36

Pin Number Function

A42MX36

Pin Number Function

157

158

159

160

161

162

163

164

165

166

167

168

169

GND

I/O

170

171

172

173

174

175

176

177

178

179

180

181

182

I/O

QCLKD, I/O

I/O

183

184

185

186

187

188

189

190

191

192

193

194

195

V_CCA

GND

196

197

198

199

200

201

202

203

204

205

206

207

208

QCLKC, I/O

I/O

SDI, I/O

I/O

CLKB, I/O

I/O

I/O (WD)

I/O

PRB, I/O

I/O

I/O (WD)

PRA, I/O

I/O

V_CCI

I/O (WD)

I/O

I/O (WD)

I/O

CLKA, I/O

I/O

I/O (WD)

DCLK, I/O

I/O

V_CCI

v5 .1

1 0 7

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 5 6 -P in C Q F P (T o p Vie w )

256 255 254 253 252 251 250 249 248

200 199 198 197 196 195 194 193

Pin #1

Index

1

2

3

4

5

6

7

8

192

191

190

189

188

187

186

185

A42MX36

256-Pin

CQFP

56

57

58

59

60

61

62

63

64

137

136

135

134

133

132

131

130

129

65 66 67 68 69 70 71 72 73

121 122 123 124 125 126 127 128

1 0 8

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 5 6 -P in C Q F P

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

1

NC

GND

I/O

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

I/O

87

88

I/O, (WD)

I/O

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

NC

GND

I/O

2

3

I/O

89

4

I/O

90

I/O

5

I/O

GND

I/O

91

I/O

6

I/O

92

I/O

7

I/O

93

I/O

8

I/O

94

I/O

9

I/O

95

V_CCI

V_CCA

GND

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

GND

I/O

96

GND

I/O

97

I/O

98

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

I/O

V_CCA

GND

NC

I/O

I/O, (WD)

I/O

NC

I/O

NC

I/O

I/O, (WD)

I/O

SDO, TDO, I/O

I/O

V_CCA

I/O

I/O (WD)

I/O

QCLKA, I/O

I/O

V_CCA

I/O

GND

I/O

V_CCA

V_CCI

GND

V_CCA

GND

TCK, I/O

I/O

V_CCI

I/O

V_CCA

V_CCI

GND

I/O

I/O (WD)

GND

I/O, (WD)

I/O

V_CCI

I/O

I/O, (WD)

I/O

GND

I/O

GND

I/O

QCLKB, I/O

I/O

GND

NC

V_CCA

I/O

NC

I/O

v5 .1

1 0 9

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 5 6 -P in C Q F P (C o n t in u e d )

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

Number

A42MX36

Function

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

I/O

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

I/O

DCLK, I/O

I/O

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

I/O (WD)

I/O

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

I/O

PRB, I/O

I/O

QCLKD, I/O

I/O

I/O (WD)

V_CCI

CLKB, I/O

I/O

I/O (WD)

GND

I/O (WD)

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCA

V_CCI

I/O

GND

I/O

CLKA, I/O

I/O

V_CCI

I/O

PRA, I/O

I/O

I/O (WD)

I/O

MODE

V_CCA

GND

NC

QCLKC, I/O

I/O

I/O (WD)

I/O

I/O (WD)

I/O

SDI, I/O

I/O

NC

GND

NC

I/O

1 1 0

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

2 7 2 -P in B G A P a c k a g e ( T o p V ie w )

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20

A

B

C

D

E

F

G

H

J

272-Pin PBGA

K

L

M

N

P

R

T

U

V

W

Y

v5 .1

1 1 1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 7 2 -P in P B G A

A42MX36

Function

A42MX36

Function

A42MX36

Function

A42MX36

Function

Ball

A1

A2

GND

I/O

C4

C5

I/O

I/O (WD)

I/O

E19

E20

F1

I/O

K10

K11

K12

K17

K18

K19

K20

L1

GND

I/O

A3

C6

I/O

A4

I/O (WD)

I/O

C7

QCLKC, I/O

I/O

F2

I/O

A5

C8

F3

I/O

V_CCA

GND (LP)

I/O

A6

I/O

C9

I/O

F4

V_CCI

I/O

A7

I/O (WD)

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D1

CLKB

PRA, I/O

I/O (WD)

I/O

F17

F18

F19

F20

G1

A8

I/O

A9

I/O

L2

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

I/O

L3

V_CCA

GND

V_CCI

I/O

CLKA

I/O

QCLKD, I/O

I/O

L4

G2

I/O

L9

I/O

I/O (WD)

SDI, I/O

I/O

G3

I/O

L10

L11

L12

L17

L18

L19

L20

M1

I/O

G4

V_CCI

I/O

G17

G18

G19

G20

H1

I/O (WD)

I/O

GND

DCLK, I/O

I/O

D2

I/O

TCK, I/O

I/O

D3

I/O

H2

I/O

D4

I/O

H3

I/O

M2

I/O

B2

D5

V_CCI

I/O

H4

V_CCA

I/O

M3

I/O

B3

D6

H17

H18

H19

H20

J1

M4

V_CCI

GND

I/O

B4

D7

I/O

M9

B5

I/O

D8

V_CCA

I/O (WD)

V_CCI

I/O

M10

M11

M12

M17

M18

M19

M20

N1

B6

I/O

D9

I/O

B7

I/O (WD)

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

E1

I/O

B8

J2

I/O

B9

PRB, I/O

I/O

V_CCI

I/O

J3

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C1

J4

V_CCI

GND

V_CCA

I/O

V_CCI

I/O

J9

I/O

I/O (WD)

I/O

J10

J11

J12

J17

J18

J19

J20

K1

I/O

V_CCA

GND

I/O

N2

I/O

N3

I/O

I/O (WD)

I/O

N4

V_CCI

I/O

N17

N18

N19

N20

P1

I/O (WD)

I/O

GND

I/O

E2

I/O

E3

I/O

K2

I/O

E4

V_CCA

V_CCI

I/O

K3

I/O

P2

I/O

C2

MODE

GND

E17

E18

K4

V_CCI

GND

P3

I/O

C3

K9

P4

V_CCA

1 1 2

v5 .1

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

2 7 2 -P in P B G A (C o n t in u e d )

A42MX36

Function

A42MX36

Function

A42MX36

Function

A42MX36

Function

Ball

P17

P18

P19

P20

R1

I/O

U6

U7

I/O (WD)

I/O

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

W1

I/O

W16

W17

W18

W19

W20

Y1

I/O (WD)

I/O

U8

I/O

I/O (WD)

I/O

I/O (WD)

GND

I/O

U9

I/O (WD)

V_CCA

V_CCI

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V1

I/O (WD)

I/O

R2

I/O

R3

I/O

Y2

R4

V_CCI

I/O

SDO, TDO, I/O

I/O

Y3

R17

R18

R19

R20

T1

QCLKB, I/O

I/O

Y4

TDI, I/O

I/O (WD)

I/O

Y5

I/O

V_CCI

I/O

GND

I/O

Y6

I/O

W2

Y7

QCLKA, I/O

I/O

GND

I/O

W3

Y8

T2

I/O

W4

TMS, I/O

I/O

Y9

I/O

T3

I/O

W5

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

I/O

T4

I/O

W6

I/O

T17

T18

T19

T20

U1

V_CCA

I/O

V2

I/O

W7

I/O

V3

GND

I/O

W8

I/O (WD)

I/O

V4

W9

I/O

V5

W10

W11

W12

W13

W14

W15

I/O

V6

I/O

U2

I/O

V7

I/O

U3

I/O

V8

I/O (WD)

I/O

I/O (WD)

I/O

I/O (WD)

GND

U4

I/O

V9

U5

V_CCI

V10

I/O

v5 .1

1 1 3

4 0 M X a n d 4 2 M X F P G A F a m i l i e s

L i s t o f C h a n g e s

The following table lists critical changes that were made in the current version of the document.

Previous version Changes in current version (v5.1)

Page

The “Low Power Mode” on page 5 was updated.

page 5

v5.0

Footnote 8 in the “Electrical Specifications” table on page 13 was updated.

Footnote 8 in the “Electrical Specifications” table on page 14 was updated.

page 13

page 14

Because the changes in this data sheet are extensive and technical in nature, this should ALL

be viewed as a new document. Please read it as you would a data sheet that is published

for the first time.

v4.0.1

Note that the “Package Characteristics and Mechanical Drawings” section has been

eliminated from the data sheet. The mechanical drawings are now contained in a separate

document, “Package Characteristics and Mechanical Drawings,” available on the Actel

web site.

D a t a S h e e t C a t e g o r i e s

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” The definition of

these categories are as follows:

P r o d u c t B r i e f

The product brief is a summerized version of a advanced datasheet (advanced or production) containing general product

information. This brief gives an overview of specific device and family information.

D a t a s h e e t S u p p l e m e n t

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for

specifications that do not differ between the two families.

A d v a n c e d

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades.

This information can be used as estimates, but not for production.

U n m a r k e d ( p r o d u c t io n )

This datasheet version contains information that is considered to be final.

1 1 4

v5 .1

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Corporation

2061 Stierlin Court

Mountain View, CA 94043-4655

USA

Actel Europe Ltd.

Actel Japan

Actel Hong Kong

39th Floor

One Pacific Place

88 Queensway

Dunlop House, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Tel: (650) 318-4200

Fax: (650) 318-4600

Tel: +44 (0)1276 401450

Fax: +44 (0)1276 401490

Tel: +81 03-3445-7671

Fax: +81 03-3445-7668

Admiralty, Hong Kong

Tel: 852-22735712

5172136-7/10.03


型号：	A42MX24-3TQ176MX39
厂家：	Actel Corporation
描述：	Field Programmable Gate Array, 1890-Cell, CMOS, PQFP176, 栅可编程逻辑
文件：	总115页 (文件大小：2797K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A42MX24-3TQ176MX39 [ACTEL]

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