A54SX32ACQ208B [ACTEL]
Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 238MHz, 2880-Cell, CMOS, CQFP208, CERAMIC, QFP-208;型号: | A54SX32ACQ208B |
厂家: | Actel Corporation |
描述: | Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 238MHz, 2880-Cell, CMOS, CQFP208, CERAMIC, QFP-208 时钟 栅 可编程逻辑 |
文件: | 总108页 (文件大小:779K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
v5.3
™
SX-A Family FPGAs
u
e
•
•
Configurable I/O Support for 3.3 V / 5 V PCI, 5 V
TTL, 3.3 V LVTTL, 2.5 V LVCMOS2
2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with
5 V Input Tolerance and 5 V Drive Strength
Devices Support Multiple Temperature Grades
Configurable Weak-Resistor Pull-Up or Pull-Down
for I/O at Power-Up
Individual Output Slew Rate Control
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Leading-Edge Performance
•
•
250 MHz System Performance
350 MHz Internal Performance
•
•
Specifications
•
•
•
•
•
•
12,000 to 108,000 Available System Gates
Up to 360 User-Programmable I/O Pins
Up to 2,012 Dedicated Flip-Flops
•
•
0.22 μ / 0.25 μ CMOS Process Technology
Features
•
•
Boundary-Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Actel Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and
Design Theft
•
•
Hot-Swap Compliant I/Os
Power-Up/Down Friendly (No Sequencing Required
for Supply Voltages)
•
•
66 MHz PCI Compliant
Nonvolatile, Single-Chip Solution
Table 1 • SX-A Product Profile
Device
A54SX08A
A54SX16A
A54SX32A
A54SX72A
Capacity
Typical Gates
System Gates
8,000
12,000
16,000
24,000
32,000
48,000
72,000
108,000
Logic Modules
768
512
1,452
924
528
2,880
1,800
1,080
1,980
6,036
4,024
2,012
4,024
Combinatorial Cells
Dedicated Flip-Flops
Maximum Flip-Flops
256
512 1
990
Maximum User I/Os
Global Clocks
130
180
249
360
3
3
3
3
Quadrant Clocks
Boundary Scan Testing
3.3 V / 5 V PCI
0
Yes
0
Yes
0
Yes
4
Yes
Yes
Yes
Yes
Yes
Input Set-Up (External)
Speed Grades2
0 ns
0 ns
0 ns
0 ns
–F, Std, –1, –2
C, I, A, M
–F, Std, –1, –2, –3
C, I, A, M
–F, Std, –1, –2, –3
C, I, A, M
–F, Std, –1, –2, –3
C, I, A, M
Temperature Grades
Package (by pin count)
PQFP
TQFP
PBGA
FBGA
CQFP
208
208
208
100, 144, 176
329
144, 256, 484
208, 256
208
100, 144
100, 144
–
–
144
–
–
144, 256
–
–
256, 484
208, 256
Notes:
1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers.
2. All –3 speed grades have been discontinued.
February 2007
i
© 2007 Actel Corporation
See the Actel website for the latest version of the datasheet.
SX-A Family FPGAs
Ordering Information
A54SX16A
2
PQ
208
G
Application (Temperature Range)
Blank = Commercial (0 to +70°)
I
= Industrial (-40 to +85°C)
A
= Automotive (-40 to +125°C)
M = Military (-55 to +125°C)
= MIL-STD-883 Class B
B
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
BG = 1.27 mm Plastic Ball Grid Array
FG = 1.0 mm Fine Pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
CQ = Ceramic Quad Flat Pack1
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard2
–F = Approximately 40% Slower than Standard
Part Number
A54SX08A = 12,000 System Gates
A54SX16A = 24,000 System Gates
A54SX32A = 48,000 System Gates
A54SX72A = 108,000 System Gates
Notes:
1. For more information about the CQFP package options, refer to the HiRel SX-A datasheet.
2. All –3 speed grades have been discontinued.
Device Resources
User I/Os (Including Clock Buffers)
208-Pin
PQFP
100-Pin
TQFP
144-Pin
TQFP
176-Pin
TQFP
329-Pin
PBGA
144-Pin
FBGA
256-Pin
FBGA
484-Pin
FBGA
Device
A54SX08A
A54SX16A
A54SX32A
A54SX72A
130
175
174
171
81
81
81
–
113
113
113
–
–
–
–
–
111
111
111
–
–
–
180
203
203
–
147
–
249
–
249
360
Notes: Package Definitions: PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array,
FBGA = Fine Pitch Ball Grid Array
ii
v5.3
SX-A Family FPGAs
Temperature Grade Offering
Package
PQ208
TQ100
TQ144
TQ176
BG329
FG144
FG256
FG484
CQ208
CQ256
A54SX08A
C,I,A,M
A54SX16A
C,I,A,M
A54SX32A
C,I,A,M
C,I,A,M
C,I,A,M
C,I,M
A54SX72A
C,I,A,M
C,I,A,M
C,I,A,M
C,I,A,M
C,I,A,M
C,I,M
C,I,A,M
C,I,A,M
C,I,A,M
C,I,A,M
C,I,A,M
C,I,M
C,I,A,M
C,I,A,M
C,M,B
C,M,B
C,M,B
C,M,B
Notes:
1. C = Commercial
2. I = Industrial
3. A = Automotive
4. M = Military
5. B = MIL-STD-883 Class B
6. For more information regarding automotive products, refer to the SX-A Automotive Family FPGAs datasheet.
7. For more information regarding Mil-Temp and ceramic packages, refer to the HiRel SX-A Family FPGAs datasheet.
Speed Grade and Temperature Grade Matrix
F
Std
✓
–1
✓
–2
✓
–3
Commercial
Industrial
✓
Discontinued
Discontinued
✓
✓
✓
Automotive
Military
✓
✓
✓
✓
MIL-STD-883B
Notes:
✓
1. For more information regarding automotive products, refer to the SX-A Automotive Family FPGAs datasheet.
2. For more information regarding Mil-Temp and ceramic packages, refer to the HiRel SX-A Family FPGAs datasheet.
Contact your Actel Sales representative for more information on availability.
v5.3
iii
SX-A Family FPGAs
Table of Contents
General Description
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Detailed Specifications
Operating Conditions
Typical SX-A Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PCI Compliance for the SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Package Pin Assignments
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
329-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
International Traffic in Arms Regulations (ITAR) and Export Administration
Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
iv
v5.3
SX-A Family FPGAs
General Description
Introduction
SX-A Family Architecture
The SX-A family’s device architecture provides a unique
approach to module organization and chip routing that
satisfies performance requirements and delivers the most
The Actel SX-A family of FPGAs offers a cost-effective,
single-chip solution for low-power, high-performance
designs. Fabricated on 0.22 μm / 0.25 μm CMOS
antifuse technology and with the support of 2.5 V,
3.3 V and 5 V I/Os, the SX-A is a versatile platform to
integrate designs while significantly reducing time-
to-market.
optimal register/logic mix for
applications.
a wide variety of
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements (Figure 1-1). The
antifuses are normally open circuit and, when
programmed, form
connection.
a
permanent low-impedance
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Metal 4
Metal 3
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug Contact
Silicon Substrate
Note: The A54SX72A device has four layers of metal with the antifuse between Metal 3 and Metal 4. The A54SX08A, A54SX16A, and
A54SX32A devices have three layers of metal with the antifuse between Metal 2 and Metal 3.
Figure 1-1 • SX-A Family Interconnect Elements
v5.3
1-1
SX-A Family FPGAs
different combinatorial functions to be implemented in a
single module. An example of the flexibility enabled by
the inversion capability is the ability to integrate a 3-input
exclusive-OR function into a single C-cell. This facilitates
construction of 9-bit parity-tree functions with 1.9 ns
propagation delays.
Logic Module Design
The SX-A family architecture is described as a “sea-of-
modules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. The Actel SX-A family provides two types of
logic modules: the register cell (R-cell) and the
combinatorial cell (C-cell).
Module Organization
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable, using the S0 and S1
lines control signals (Figure 1-2). The R-cell registers feature
programmable clock polarity selectable on a register-by-
register basis. This provides additional flexibility while
allowing mapping of synthesized functions into the SX-A
FPGA. The clock source for the R-cell can be chosen from
either the hardwired clock, the routed clocks, or internal
logic.
All C-cell and R-cell logic modules are arranged into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
Clusters are grouped together into SuperClusters
(Figure 1-4 on page 1-3). SuperCluster 1 is a two-wide
grouping of Type 1 Clusters. SuperCluster 2 is a two-wide
group containing one Type 1 Cluster and one Type 2
Cluster. SX-A devices feature more SuperCluster 1
modules than SuperCluster 2 modules because designers
typically require significantly more combinatorial logic
than flip-flops.
The C-cell implements a range of combinatorial functions
of up to five inputs (Figure 1-3). Inclusion of the DB input
and its associated inverter function allows up to 4,000
Routed
Data Input
S1
S0
PRE
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLR
CLKB,
Internal Logic
CKS
CKP
Figure 1-2 • R-Cell
D0
D1
Y
D2
D3
Sa
Sb
DB
B1
A1
A0 B0
Figure 1-3 • C-Cell
1-2
v5.3
SX-A Family FPGAs
Routing Resources
The routing and interconnect resources of SX-A devices
are in the top two metal layers above the logic modules
(Figure 1-1 on page 1-1), providing optimal use of silicon,
thus enabling the entire floor of the device to be
spanned with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using the Actel patented metal-to-metal programmable
antifuse interconnect elements. The antifuses are
normally open circuits and, when programmed, form a
permanent low-impedance connection.
interconnection to achieve its fast signal propagation
time of less than 0.1 ns.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster, and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering a maximum pin-to-pin
propagation time of 0.3 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. The Actel segmented routing structure provides
a variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
100% automatic place-and-route software to minimize
signal propagation delays.
The general system of routing tracks allows any logic
module in the array to be connected to any other logic
or I/O module. Within this system, most connections
typically require three or fewer antifuses, resulting in
fast and predictable performance.
The unique local and general routing structure featured
in SX-A devices allows 100% pin-locking with full logic
utilization, enables concurrent printed circuit board
(PCB) development, reduces design time, and allows
designers to achieve performance goals with minimum
effort.
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 1-5 on page 1-4 and
Figure 1-6 on page 1-4). This routing architecture also
dramatically reduces the number of antifuses required to
complete
a circuit, ensuring the highest possible
performance, which is often required in applications such
as fast counters, state machines, and data path logic. The
interconnect elements (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring
R-Cell in a given SuperCluster. DirectConnect uses a
hardwired signal path requiring no programmable
R-Cell
C-Cell
D0
D1
Routed
S1
Data Input
S0
PRE
Y
D2
D3
DirectConnect
D
Q
Y
Input
Sb
Sa
HCLK
CLKA,
CLKB,
Internal Logic
CLR
DB
CKS
CKP
A0 B0
A1 B1
Cluster 1
Cluster 1
Cluster 2
Cluster 1
Type 1 SuperCluster
Type 2 SuperCluster
Figure 1-4 • Cluster Organization
v5.3
1-3
SX-A Family FPGAs
DirectConnect
• No Antifuses
• 0.1 ns Maximum Routing Delay
FastConnect
• One Antifuse
• 0.3 ns Maximum Routing Delay
Routing Segments
• Typically Two Antifuses
• Max. Five Antifuses
Figure 1-5 • DirectConnect and FastConnect for Type 1 SuperClusters
DirectConnect
• No Antifuses
• 0.1 ns Maximum Routing Delay
FastConnect
• One Antifuse
• 0.3 ns Maximum Routing Delay
Routing Segments
• Typically Two Antifuses
• Max. Five Antifuses
Figure 1-6 • DirectConnect and FastConnect for Type 2 SuperClusters
1-4
v5.3
SX-A Family FPGAs
Clock Resources
Actel’s high-drive routing structure provides three clock
networks (Table 1-1). The first clock, called HCLK, is
hardwired from the HCLK buffer to the clock select
multiplexor (MUX) in each R-cell. HCLK cannot be
connected to combinatorial logic. This provides a fast
propagation path for the clock signal. If not used, this
pin must be set as Low or High on the board. It must not
be left floating. Figure 1-7 describes the clock circuit
used for the constant load HCLK and the macros
supported.
and CLKB circuit used and the macros supported in SX-A
devices with the exception of A54SX72A.
In addition, the A54SX72A device provides four
quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD—
corresponding to bottom-left, bottom-right, top-left,
and top-right locations on the die, respectively), which
can be sourced from external pins or from internal logic
signals within the device. Each of these clocks can
individually drive up to an entire quadrant of the chip,
or they can be grouped together to drive multiple
quadrants (Figure 1-9 on page 1-6). QCLK pins can
function as user I/O pins. If not used, the QCLK pins
must be tied Low or High on the board and must not be
left floating.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Design
software and the pin must be tied to GND on the board.
For more information on how to use quadrant clocks in
the A54SX72A device, refer to the Global Clock Networks
in Actel’s Antifuse Devices and Using A54SX72A and
RT54SX72S Quadrant Clocks application notes.
Two additional clocks (CLKA, CLKB) are global clocks that
can be sourced from external pins or from internal logic
signals within the SX-A device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB pins are not used or sourced from signals,
these pins must be set as Low or High on the board. They
must not be left floating. Figure 1-8 describes the CLKA
The CLKA, CLKB, and QCLK circuits for A54SX72A as well
as the macros supported are shown in Figure 1-10 on
page 1-6. Note that bidirectional clock buffers are only
available in A54SX72A. For more information, refer to
the "Pin Description" section on page 1-15.
Table 1-1 • SX-A Clock Resources
A54SX08A
A54SX16A
A54SX32A
A54SX72A
Routed Clocks (CLKA, CLKB)
2
1
0
2
1
0
2
1
0
2
1
4
Hardwired Clocks (HCLK)
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD)
Constant Load
Clock Network
HCLKBUF
Figure 1-7 • SX-A HCLK Clock Buffer
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 1-8 • SX-A Routed Clock Buffer
v5.3
1-5
SX-A Family FPGAs
4 QCLKBUFS
4
Quadrant 2
Quadrant 3
5:1
5:1
QCLKINT (to array)
Quadrant 0
QCLKINT (to array)
4
Quadrant 1
5:1
5:1
QCLKINT (to array)
QCLKINT (to array)
Figure 1-9 • SX-A QCLK Architecture
OE
From Internal Logic
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
CLKBIBUF
CLKBIBUFI
QCLKBUF
QCLKBUFI
QCLKINT
QCLKINTI
QCLKBIBUF
QCLKBIBUFI
Figure 1-10 • A54SX72A Routed Clock and QCLK Buffer
1-6
v5.3
SX-A Family FPGAs
I/O Modules
For a simplified I/O schematic, refer to Figure 1 in the
Other Architectural Features
application note, Actel eX, SX-A, and RTSX-S I/Os.
Technology
Each user I/O on an SX-A device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Mixed I/O standards can be set for individual pins,
though this is only allowed with the same voltage as the
input. These I/Os, combined with array registers, can
achieve clock-to-output-pad timing as fast as 3.8 ns, even
without the dedicated I/O registers. In most FPGAs, I/O
cells that have embedded latches and flip-flops,
requiring instantiation in HDL code; this is a design
complication not encountered in SX-A FPGAs. Fast pin-
to-pin timing ensures that the device is able to interface
with any other device in the system, which in turn
enables parallel design of system components and
reduces overall design time. All unused I/Os are
configured as tristate outputs by the Actel Designer
software, for maximum flexibility when designing new
boards or migrating existing designs.
SX-A I/Os should be driven by high-speed push-pull
devices with a low-resistance pull-up device when being
configured as tristate output buffers. If the I/O is driven
by a voltage level greater than VCCI and a fast push-pull
device is NOT used, the high-resistance pull-up of the
driver and the internal circuitry of the SX-A I/O may
create a voltage divider. This voltage divider could pull
the input voltage below specification for some devices
connected to the driver. A logic '1' may not be correctly
presented in this case. For example, if an open drain
driver is used with a pull-up resistor to 5 V to provide the
logic '1' input, and VCCI is set to 3.3 V on the SX-A device,
the input signal may be pulled down by the SX-A input.
The Actel SX-A family is implemented on a high-voltage,
twin-well CMOS process using 0.22 μ / 0.25 μ design
rules. The metal-to-metal antifuse is comprised of a
combination of amorphous silicon and dielectric material
with barrier metals and has a programmed ('on' state)
resistance of 25 Ω with capacitance of 1.0 fF for low
signal impedance.
Performance
The unique architectural features of the SX-A family
enable the devices to operate with internal clock
frequencies of 350 MHz, causing very fast execution of
even complex logic functions. The SX-A family is an
optimal platform upon which to integrate the
functionality previously contained in multiple complex
programmable logic devices (CPLDs). In addition, designs
that previously would have required a gate array to meet
performance goals can be integrated into an SX-A device
with dramatic improvements in cost and time-to-market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
User Security
Reverse engineering is virtually impossible in SX-A
devices because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses. In
addition, since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept at device
power-up.
Each I/O module has an available power-up resistor of
approximately 50 kΩ that can configure the I/O in a
known state during power-up. For nominal pull-up and
pull-down resistor values, refer to Table 1-4 on page 1-8
of the application note Actel eX, SX-A, and RTSX-S I/Os.
Just slightly before VCCA reaches 2.5 V, the resistors are
disabled, so the I/Os will be controlled by user logic. See
Table 1-2 on page 1-8 and Table 1-3 on page 1-8 for
more information concerning available I/O features.
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
where they cannot be accessed or bypassed without
destroying access to the rest of the device, making both
invasive and more-subtle noninvasive attacks ineffective
against Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure
(Figure 1-11).
™
u
e
Figure 1-11 • FuseLock
For more information, refer to Actel’s Implementation of
Security in Actel Antifuse FPGAs application note.
v5.3
1-7
SX-A Family FPGAs
Power-Up/Down and Hot Swapping
SX-A I/Os are configured to be hot-swappable, with the
exception of 3.3 V PCI. During power-up/down (or partial
up/down), all I/Os are tristated. VCCA and VCCI do not
have to be stable during power-up/down, and can be
powered up/down in any order. When the SX-A device is
plugged into an electrically active system, the device will
not degrade the reliability of or cause damage to the
host system. The device’s output pins are driven to a high
impedance state until normal chip operating conditions
are reached. Table 1-4 summarizes the VCCA voltage at
which the I/Os behave according to the user’s design for
an SX-A device at room temperature for various ramp-up
rates. The data reported assumes a linear ramp-up
profile to 2.5 V. For more information on power-up and
hot-swapping, refer to the application note, Actel SX-A
and RT54SX-S Devices in Hot-Swap and Cold-Sparing
Applications.
Table 1-2 • I/O Features
Function
Description
Input Buffer Threshold Selections
•
•
•
5 V: PCI, TTL
3.3 V: PCI, LVTTL
2.5 V: LVCMOS2 (commercial only)
Flexible Output Driver
Output Buffer
•
•
•
5 V: PCI, TTL
3.3 V: PCI, LVTTL
2.5 V: LVCMOS2 (commercial only)
“Hot-Swap” Capability (3.3 V PCI is not hot swappable)
•
•
I/O on an unpowered device does not sink current
Can be used for “cold-sparing”
Selectable on an individual I/O basis
Individually selectable slew rate; high slew or low slew (The default is high slew rate).
The slew is only affected on the falling edge of an output. Rising edges of outputs are
not affected.
Power-Up
Individually selectable pull-ups and pull-downs during power-up (default is to power-up
in tristate)
Enables deterministic power-up of device
VCCA and VCCI can be powered in any order
Table 1-3 • I/O Characteristics for All I/O Configurations
Hot Swappable
Slew Rate Control
Power-Up Resistor
Pull-up or pull-down
Pull-up or pull-down
Pull-up or pull-down
TTL, LVTTL, LVCMOS2
3.3 V PCI
Yes
No
Yes
Yes. Only affects falling edges of outputs
No. High slew rate only
5 V PCI
No. High slew rate only
Table 1-4 • Power-Up Time at which I/Os Become Active
Supply Ramp Rate 0.25 V/μs 0.025 V/μs 5 V/ms
2.5 V/ms
ms
0.5 V/ms 0.25 V/ms 0.1 V/ms 0.025 V/ms
Units
μs
10
10
10
10
μs
96
ms
ms
2.7
2.5
2.8
2.6
ms
5.4
4.7
5.2
5.0
ms
12.9
11.0
12.1
12.1
ms
50.8
41.6
47.2
47.2
A54SX08A
A54SX16A
A54SX32A
A54SX72A
0.34
0.36
0.46
0.41
0.65
100
100
100
0.62
0.74
0.67
1-8
v5.3
SX-A Family FPGAs
Flexible Mode
Boundary-Scan Testing (BST)
In Flexible mode, TDI, TCK, and TDO may be employed as
either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are not present in
flexible JTAG mode.
All SX-A devices are IEEE 1149.1 compliant and offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
The BST function is controlled through the special JTAG
pins (TMS, TDI, TCK, TDO, and TRST). The functionality of
the JTAG pins is defined by two available modes:
Dedicated and Flexible. TMS cannot be employed as a
user I/O in either mode.
To select the Flexible mode, uncheck the Reserve JTAG
box in the Device Selection Wizard dialog in the Actel
Designer software. In Flexible mode, TDI, TCK, and TDO
pins may function as user I/Os or BST pins. The
functionality is controlled by the BST Test Access Port
(TAP) controller. The TAP controller receives two control
inputs, TMS and TCK. Upon power-up, the TAP controller
enters the Test-Logic-Reset state. In this state, TDI, TCK,
and TDO function as user I/Os. The TDI, TCK, and TDO are
transformed from user I/Os into BST pins when a rising
edge on TCK is detected while TMS is at logic low. To
return to Test-Logic Reset state, TMS must be high for at
least five TCK cycles. An external 10 k pull-up resistor
to VCCI should be placed on the TMS pin to pull it
High by default.
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, the user must reserve the
JTAG pins in Actel’s Designer software. Reserve the JTAG
pins by checking the Reserve JTAG box in the Device
Selection Wizard (Figure 1-12).
Table 1-6
describes
the
different
configuration
The default for the software is Flexible mode; all boxes
are unchecked. Table 1-5 lists the definitions of the
options in the Device Selection Wizard.
requirements of BST pins and their functionality in
different modes.
Table 1-6 • Boundary-Scan Pin Configurations and
Functions
Designer
"Reserve JTAG"
Selection
TAP Controller
State
Mode
Dedicated (JTAG)
Flexible (User I/O)
Flexible (JTAG)
Checked
Unchecked
Unchecked
Any
Test-Logic-Reset
Any EXCEPT Test-
Logic-Reset
TRST Pin
Figure 1-12 • Device Selection Wizard
Table 1-5 • Reserve Pin Definitions
The TRST pin functions as a dedicated Boundary-Scan
Reset pin when the Reserve JTAG Test Reset option is
selected as shown in Figure 1-12. An internal pull-up
resistor is permanently enabled on the TRST pin in this
mode. Actel recommends connecting this pin to ground
in normal operation to keep the JTAG state controller in
the Test-Logic-Reset state. When JTAG is being used, it
can be left floating or can be driven high.
Pin
Function
Reserve JTAG
Keeps pins from being used and
changes the behavior of JTAG pins (no
pull-up on TMS)
Reserve JTAG Test Regular I/O or JTAG reset with an
When the Reserve JTAG Test Reset option is not
selected, this pin will function as a regular I/O. If unused
as an I/O in the design, it will be configured as a tristated
output.
Reset
internal pull-up
Reserve Probe
Keeps pins from being used or regular
I/O
v5.3
1-9
SX-A Family FPGAs
JTAG Instructions
Table 1-7 lists the supported instructions with the corresponding IR codes for SX-A devices.
Table 1-8 lists the codes returned after executing the IDCODE instruction for SX-A devices. Note that bit 0 is always '1'.
Bits 11-1 are always '02F', which is the Actel manufacturer code.
Table 1-7 • JTAG Instruction Code
Instructions (IR4:IR0)
EXTEST
Binary Code
00000
SAMPLE/PRELOAD
INTEST
00001
00010
USERCODE
IDCODE
00011
00100
HighZ
01110
CLAMP
01111
Diagnostic
BYPASS
10000
11111
Reserved
All others
Table 1-8 • JTAG Instruction Code
Device
Process
Revision
Bits 31-28
Bits 27-12
40B4, 42B4
40B4, 42B4
40B8, 42B8
40B8, 42B8
22B8
A54SX08A
0.22 µ
0
1
0
1
1
0
1
1
0
1
1
8, 9
A, B
9
A54SX16A
A54SX32A
A54SX72A
0.22 µ
B
0.25 µ
0.2 2µ
B
9
40BD, 42BD
40BD, 42BD
22BD
B
0.25 µ
0.22 µ
B
9
40B2, 42B2
40B2, 42B2
22B2
B
0.25 µ
B
1-10
v5.3
SX-A Family FPGAs
Probing Capabilities
SX-A devices also provide an internal probing capability
that is accessed with the JTAG pins. The Silicon Explorer II
diagnostic hardware is used to control the TDI, TCK, TMS,
and TDO pins to select the desired nets for debugging.
The user assigns the selected internal nets in Actel Silicon
Explorer II software to the PRA/PRB output pins for
observation. Silicon Explorer II automatically places the
device into JTAG mode. However, probing functionality is
only activated when the TRST pin is driven high or left
floating, allowing the internal pull-up resistor to pull
TRST High. If the TRST pin is held Low, the TAP controller
remains in the Test-Logic-Reset state so no probing can
be performed. However, the user must drive the TRST pin
High or allow the internal pull-up resistor to pull TRST
High.
When selecting the Reserve Probe Pin box as shown in
Figure 1-12 on page 1-9, direct the layout tool to reserve
the PRA and PRB pins as dedicated outputs for probing.
This Reserve option is merely a guideline. If the designer
assigns user I/Os to the PRA and PRB pins and selects the
Reserve Probe Pin option, Designer Layout will
override the Reserve Probe Pin option and place the
user I/Os on those pins.
To allow probing capabilities, the security fuse must not
be programmed. Programming the security fuse disables
the JTAG and probe circuitry. Table 1-9 summarizes the
possible device configurations for probing once the
device leaves the Test-Logic-Reset JTAG state.
Table 1-9 • Device Configuration Options for Probe Capability (TRST Pin Reserved)
JTAG Mode
TRST1
Security Fuse Programmed
PRA, PRB2
User I/O3
TDI, TCK, TDO2
JTAG Disabled
JTAG I/O
Dedicated
Low
No
No
No
No
Yes
High
Low
Probe Circuit Outputs
User I/O3
Flexible
User I/O3
High
Probe Circuit Outputs
Probe Circuit Secured
JTAG I/O
Probe Circuit Secured
Notes:
1. If the TRST pin is not reserved, the device behaves according to TRST = High as described in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
the Designer software.
v5.3
1-11
SX-A Family FPGAs
PRA/PRB pins for observation. Figure 1-13 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification.
SX-A Probe Circuit Control Pins
SX-A devices contain internal probing circuitry that
provides built-in access to every node in a design,
enabling 100% real-time observation and analysis of a
device's internal logic nodes without design iteration.
The probe circuitry is accessed by Silicon Explorer II, an
easy to use, integrated verification and logic analysis tool
that can sample data at 100 MHz (asynchronous) or
66 MHz (synchronous). Silicon Explorer II attaches to a
PC’s standard COM port, turning the PC into a fully
functional 18-channel logic analyzer. Silicon Explorer II
allows designers to complete the design verification
process at their desks and reduces verification time from
several hours per cycle to a few seconds.
Design Considerations
In order to preserve device probing capabilities, users
should avoid using the TDI, TCK, TDO, PRA, and PRB pins
as input or bidirectional ports. Since these pins are active
during probing, critical input signals through these pins
are not available. In addition, the security fuse must not
be programmed to preserve probing capabilities. Actel
recommends that you use a 70 Ω series termination
resistor on every probe connector (TDI, TCK, TMS, TDO,
PRA, PRB). The 70 Ω series termination is used to prevent
data transmission corruption during probing and
reading back the checksum.
The Silicon Explorer II tool uses the boundary-scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
SX-A FPGA
70 Ω
70 Ω
70 Ω
TDI
TCK
TMS
Silicon Explorer II
Serial Connection
70 Ω
TDO
70 Ω
70 Ω
PRA
PRB
Figure 1-13 • Probe Setup
1-12
v5.3
SX-A Family FPGAs
Design Environment
The SX-A family of FPGAs is fully supported by both Actel
Libero® Integrated Design Environment (IDE) and
Designer FPGA development software. Actel Libero IDE is
Programming
Device programming is supported through Silicon
Sculptor series of programmers. In particular, Silicon
Sculptor is compact, robust, single-site and multi-site
device programmer for the PC.
a
design management environment, seamlessly
integrating design tools while guiding the user through
the design flow, managing all design and log files, and
passing necessary design data among tools. Additionally,
Libero IDE allows users to integrate both schematic and
HDL synthesis into a single flow and verify the entire
design in a single environment. Libero IDE includes
Synplify® for Actel from Synplicity®, ViewDraw® for
Actel from Mentor Graphics®, ModelSim® HDL Simulator
from Mentor Graphics, WaveFormer Lite™ from
SynaptiCAD™, and Designer software from Actel. Refer
to the Libero IDE flow diagram for more information
(located on the Actel website).
With standalone software, Silicon Sculptor
allows
concurrent programming of multiple units from the
same PC, ensuring the fastest programming times
possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition,
integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor also provides extensive
hardware self-testing capability.
The procedure for programming an SX-A device using
Silicon Sculptor is as follows:
1. Load the .AFM file
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via in-house
programming from the factory.
timing-driven place-and-route, and
a
world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results
of place-and-route. Additionally, the back-annotation
flow is compatible with all the major simulators and the
simulation results can be cross-probed with Silicon
Explorer II, Actel’s integrated verification and logic
analysis tool. Another tool included in the Designer
software is the SmarGen core generator, which easily
creates popular and commonly used logic functions for
implementation in your schematic or HDL design. Actel's
Designer software is compatible with the most popular
FPGA design entry and verification tools from companies
such as Mentor Graphics, Synplicity, Synopsys, and
Cadence Design Systems. The Designer software is
available for both the Windows and UNIX operating
systems.
For detailed information on programming, read the
following documents Programming Antifuse Devices and
Silicon Sculptor User’s Guide.
v5.3
1-13
SX-A Family FPGAs
Related Documents
Application Notes
Global Clock Networks in Actel’s Antifuse Devices
http://www.actel.com/documents/GlobalClk_AN.pdf
Using A54SX72A and RT54SX72S Quadrant Clocks
http://www.actel.com/documents/QCLK_AN.pdf
Implementation of Security in Actel Antifuse FPGAs
http://www.actel.com/documents/Antifuse_Security_AN.pdf
Actel eX, SX-A, and RTSX-S I/Os
http://www.actel.com/documents/AntifuseIO_AN.pdf
Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications
http://www.actel.com/documents/HotSwapColdSparing_AN.pdf
Programming Antifuse Devices
http://www.actel.com/documents/AntifuseProgram_AN.pdf
Datasheets
HiRel SX-A Family FPGAs
http://www.actel.com/documents/HRSXA_DS.pdf
SX-A Automotive Family FPGAs
http://www.actel.com/documents/SXA_Auto_DS.pdf
User’s Guides
Silicon Sculptor User’s Guide
http://www.actel.com/documents/SiliSculptII_Sculpt3_ug.pdf
1-14
v5.3
SX-A Family FPGAs
PRA/B, I/O
Probe A/B
Pin Description
The Probe pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the other
probe pin to allow real-time diagnostic output of any
signal path within the device. The Probe pin can be used
as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be
permanently disabled to protect programmed design
confidentiality.
CLKA/B, I/O
Clock A and B
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL,
LVTTL, LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. The
clock input is buffered prior to clocking the R-cells. When
not used, this pin must be tied Low or High (NOT left
floating) on the board to avoid unwanted power
consumption.
TCK, I/O
Test Clock
For A54SX72A, these pins can also be configured as user
I/Os. When employed as user I/Os, these pins offer built-
in programmable pull-up or pull-down resistors active
during power-up only. When not used, these pins must
be tied Low or High (NOT left floating).
Test clock input for diagnostic probe and device
programming. In Flexible mode, TCK becomes active
when the TMS pin is set Low (refer to Table 1-6 on
page 1-9). This pin functions as an I/O when the
boundary scan state machine reaches the "logic reset"
state.
QCLKA/B/C/D, I/O Quadrant Clock A, B, C, and D
These four pins are the quadrant clock inputs and are
only used for A54SX72A with A, B, C, and
D
TDI, I/O
Test Data Input
corresponding to bottom-left, bottom-right, top-left,
and top-right quadrants, respectively. They are clock
inputs for clock distribution networks. Input levels are
compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V
PCI, or 5 V PCI specifications. Each of these clock inputs
can drive up to a quarter of the chip, or they can be
grouped together to drive multiple quadrants. The clock
input is buffered prior to clocking the R-cells. When not
used, these pins must be tied Low or High on the board
(NOT left floating).
These pins can also be configured as user I/Os. When
employed as user I/Os, these pins offer built-in
programmable pull-up or pull-down resistors active
during power-up only.
Serial input for boundary scan testing and diagnostic
probe. In Flexible mode, TDI is active when the TMS pin is
set Low (refer to Table 1-6 on page 1-9). This pin
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set Low (refer to
Table 1-6 on page 1-9). This pin functions as an I/O when
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer II is being used, TDO
will act as an output when the checksum command is
run. It will return to user /IO when checksum is complete.
GND
Ground
TMS
Test Mode Select
Low supply voltage.
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set Low, the TCK, TDI, and
TDO pins are boundary scan pins (refer to Table 1-6 on
page 1-9). Once the boundary scan pins are in test mode,
they will remain in that mode until the internal
boundary scan state machine reaches the logic reset
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The logic
reset state is reached five TCK cycles after the TMS pin is
set High. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
HCLK
Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL, LVTTL,
LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. This input is
directly wired to each R-cell and offers clock speeds
independent of the number of R-cells being driven.
When not used, HCLK must be tied Low or High on the
board (NOT left floating). When used, this pin should be
held Low or High during power-up to avoid unwanted
static power consumption.
TRST, I/O
Boundary Scan Reset Pin
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL, LVTTL, LVCMOS2, 3.3 V PCI or 5 V PCI specifications.
Unused I/O pins are automatically tristated by the
Designer software.
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the Reserve JTAG Reset Pin is
not selected in Designer.
NC
No Connection
V
Supply Voltage
CCI
This pin is not connected to circuitry within the device
and can be driven to any voltage or be left floating with
no effect on the operation of the device.
Supply voltage for I/Os. See Table 2-2 on page 2-1. All
V
CCI power pins in the device should be connected.
V
Supply Voltage
CCA
Supply voltage for array. See Table 2-2 on page 2-1. All
CCA power pins in the device should be connected.
V
v5.3
1-15
SX-A Family FPGAs
Detailed Specifications
Operating Conditions
Table 2-1 • Absolute Maximum Ratings
Symbol
Parameter
DC Supply Voltage for I/Os
Limits
–0.3 to +6.0
Units
VCCI
VCCA
VI
V
V
DC Supply Voltage for Arrays
Input Voltage
–0.3 to +3.0
–0.5 to +5.75
–0.5 to + VCCI + 0.5
–65 to +150
V
VO
Output Voltage
V
TSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
"Recommended Operating Conditions".
Table 2-2 • Recommended Operating Conditions
Parameter
Commercial
0 to +70
Industrial
–40 to +85
2.25 to 2.75
3.0 to 3.6
Units
Temperature Range
2.5 V Power Supply Range (VCCA and VCCI
3.3 V Power Supply Range (VCCI
5 V Power Supply Range (VCCI
°C
V
)
2.25 to 2.75
3.0 to 3.6
)
V
)
4.75 to 5.25
4.75 to 5.25
V
Typical SX-A Standby Current
Table 2-3 • Typical Standby Current for SX-A at 25°C with VCCA = 2.5 V
Product
V
CCI = 2.5 V
0.8 mA
VCCI = 3.3 V
1.0 mA
VCCI = 5 V
A54SX08A
A54SX16A
A54SX32A
A54SX72A
2.9 mA
2.9 mA
3.0 mA
4.5 mA
0.8 mA
1.0 mA
0.9 mA
1.0 mA
3.6 mA
3.8 mA
Table 2-4 • Supply Voltages
VCCA
2. 5 V
2.5 V
2.5 V
VCCI
*
Maximum Input Tolerance
Maximum Output Drive
2.5 V
3.3 V
5 V
5.75 V
5.75 V
5.75 V
2.7 V
3.6 V
5.25 V
Note: *3.3 V PCI is not 5 V tolerant due to the clamp diode, but instead is 3.3 V tolerant.
v5.3
2-1
SX-A Family FPGAs
Electrical Specifications
Table 2-5 • 3.3 V LVTTL and 5 V TTL Electrical Specifications
Commercial
Industrial
Symbol
Parameter
Min.
(IOH = –1 mA) 0.9 VCCI
Max.
Min.
Max.
Units
VOH
VCCI = Minimum
VI = VIH or VIL
0.9 VCCI
V
VCCI = Minimum
VI = VIH or VIL
(IOH = –8 mA)
(IOL= 1 mA)
(IOL= 12 mA)
2.4
2.4
V
V
V
VOL
VCCI = Minimum
VI = VIH or VIL
0.4
0.4
0.4
0.4
VCCI = Minimum
VI = VIH or VIL
VIL
Input Low Voltage
Input High Voltage
0.8
5.75
10
0.8
5.75
10
V
V
VIH
2.0
–10
–10
2.0
–10
–10
IIL/IIH
IOZ
Input Leakage Current, VIN = VCCI or GND
Tristate Output Leakage Current
Input Transition Time tR, tF
I/O Capacitance
µA
µA
ns
10
10
tR, tF
CIO
ICC
10
10
10
10
pF
mA
Standby Current
10
20
IV Curve* Can be derived from the IBIS model on the web.
Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx.
Table 2-6 • 2.5 V LVCMOS2 Electrical Specifications
Commercial
Industrial
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
VOH
VDD = MIN,
VI = VIH or VIL
(IOH = –100 μA)
(IOH = –1 mA)
(IOH =–-2 mA)
(IOL= 100 μA)
(IOL= 1 mA)
2.1
2.1
V
VDD = MIN,
VI = VIH or VIL
2.0
1.7
2.0
1.7
V
V
V
V
V
VDD = MIN,
VI = VIH or VIL
VOL
VDD = MIN,
VI = VIH or VIL
0.2
0.4
0.7
0.2
0.4
0.7
VDD = MIN,
VI = VIH or VIL
VDD = MIN,
(IOL= 2 mA)
VI = VIH or VIL
VIL
Input Low Voltage, VOUT ≤ VVOL(max)
Input High Voltage, VOUT ≥ VVOH(min)
Input Leakage Current, VIN = VCCI or GND
Tristate Output Leakage Current, VOUT = VCCI or GND
Input Transition Time tR, tF
-0.3
1.7
0.7
5.75
10
-0.3
1.7
0.7
5.75
10
V
V
VIH
IIL/IIH
IOZ
–10
–10
–10
–10
µA
µA
ns
10
10
tR, tF
CIO
ICC
10
10
I/O Capacitance
10
10
pF
mA
Standby Current
10
20
IV Curve* Can be derived from the IBIS model on the web.
Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx.
2-2
v5.3
SX-A Family FPGAs
PCI Compliance for the SX-A Family
The SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
Table 2-7 • DC Specifications (5 V PCI Operation)
Symbol
VCCA
VCCI
VIH
Parameter
Supply Voltage for Array
Condition
Min.
2.25
4.75
2.0
–0.5
–
Max.
2.75
5.25
5.75
0.8
Units
V
Supply Voltage for I/Os
Input High Voltage
V
V
VIL
Input Low Voltage
V
IIH
Input High Leakage Current1
Input Low Leakage Current1
Output High Voltage
Output Low Voltage2
Input Pin Capacitance3
CLK Pin Capacitance
VIN = 2.7
70
µA
µA
V
IIL
VIN = 0.5
–
–70
–
VOH
VOL
IOUT = –2 mA
IOUT = 3 mA, 6 mA
2.4
–
0.55
10
V
CIN
–
pF
pF
CCLK
Notes:
5
12
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter includes
FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and
ACK64#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
v5.3
2-3
SX-A Family FPGAs
Table 2-8 • AC Specifications (5 V PCI Operation)
Symbol
Parameter
Condition
0 < VOUT ≤ 1.4 1
1.4 ≤ VOUT < 2.4 1, 2
Min.
Max.
Units
mA
mA
–
IOH(AC)
Switching Current High
–44
–
–
(–44 + (VOUT – 1.4)/0.024)
–
1, 3
3.1 < VOUT < VCCI
EQ 2-1 on
page 2-5
(Test Point)
V
OUT = 3.1 3
–
–142
mA
mA
mA
–
IOL(AC)
Switching Current Low
VOUT ≥ 2.2 1
95
–
–
2.2 > VOUT > 0.55 1
0.71 > VOUT > 0 1, 3
(VOUT/0.023)
–
EQ 2-2 on
page 2-5
(Test Point)
VOUT = 0.71 3
–
206
–
mA
mA
ICL
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
–5 < VIN ≤ –1
–25 + (VIN + 1)/0.015
slewR
slewF
Notes:
0.4 V to 2.4 V load 4
2.4 V to 0.4 V load 4
1
1
5
V/ns
V/ns
5
1. Refer to the V/I curves in Figure 2-1 on page 2-5. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A
and B) are provided with the respective diagrams in Figure 2-1 on page 2-5. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge
rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and
should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.
Pin
1/2 in. max.
Output
Buffer
50 pF
2-4
v5.3
SX-A Family FPGAs
Figure 2-1 shows the 5 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.
200.0
I
MAX Spec
OL
I
OL
150.0
100.0
50.0
I
MIN Spec
3.5
OL
0.0
0
0.5
1
1.5
2
2.5
3
4
4.5
I
5
5.5
6
–50.0
–100.0
–150.0
–200.0
I
MIN Spec
OH
MAX Spec
OH
I
OH
Voltage Out (V)
Figure 2-1 • 5 V PCI V/I Curve for SX-A Family
OH = 11.9 * (VOUT – 5.25) * (VOUT + 2.45)
I
IOL = 78.5 * VOUT * (4.4 – VOUT
for 0V < VOUT < 0.71V
)
for VCCI > VOUT > 3.1V
EQ 2-1
EQ 2-2
Table 2-9 • DC Specifications (3.3 V PCI Operation)
Symbol
VCCA
VCCI
VIH
Parameter
Condition
Min.
Max.
Units
V
Supply Voltage for Array
Supply Voltage for I/Os
Input High Voltage
Input Low Voltage
Input Pull-up Voltage1
Input Leakage Current2
Output High Voltage
Output Low Voltage
Input Pin Capacitance3
CLK Pin Capacitance
2.25
3.0
2.75
3.6
V
0.5VCCI
–0.5
VCCI + 0.5
0.3VCCI
–
V
VIL
V
IIPU
0.7VCCI
–10
V
IIL
0 < VIN < VCCI
IOUT = –500 µA
IOUT = 1,500 µA
+10
μA
V
VOH
VOL
0.9VCCI
–
0.1VCCI
10
V
CIN
–
pF
pF
CCLK
Notes:
5
12
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a
floated network. Designers should ensure that the input buffer is conducting minimum current at this input voltage in applications
sensitive to static power utilization.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
v5.3
2-5
SX-A Family FPGAs
Table 2-10 • AC Specifications (3.3 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
mA
mA
–
1
IOH(AC)
Switching Current High
0 < VOUT ≤ 0.3VCCI
–12VCCI
–
–
1
0.3VCCI ≤ VOUT < 0.9VCCI
(–17.1(VCCI – VOUT))
–
1, 2
0.7VCCI < VOUT < VCCI
EQ 2-3 on
page 2-7
2
(Test Point)
V
OUT = 0.7VCC
–
–32VCCI
mA
mA
mA
–
1
IOL(AC)
Switching Current Low
VCCI > VOUT ≥ 0.6VCCI
16VCCI
–
–
1
0.6VCCI > VOUT > 0.1VCCI
0.18VCCI > VOUT > 0 1, 2
(26.7VOUT
)
–
EQ 2-4 on
page 2-7
2
(Test Point)
VOUT = 0.18VCC
–
38VCCI
mA
mA
ICL
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
–
–
4
4
ICH
VCCI + 4 > VIN ≥ VCCI + 1
0.2VCCI - 0.6VCCI load 3
0.6VCCI - 0.2VCCI load 3
25 + (VIN – VCCI – 1)/0.015
mA
slewR
slewF
Notes:
1
1
V/ns
V/ns
1. Refer to the V/I curves in Figure 2-2 on page 2-7. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C
and D) are provided with the respective diagrams in Figure 2-2 on page 2-7. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain
outputs.
Pin
1/2 in. max.
Output
Buffer
10 pF
1 k/25 Ω
Pin
1 k/25 Ω
Output
Buffer
10 pF
2-6
v5.3
SX-A Family FPGAs
Figure 2-2 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.
150.0
I
MAX Spec
OL
I
OL
100.0
50.0
I
MIN Spec
2.5
OL
0.0
0
0.5
MIN Spec
1
1.5
2
3
3.5
4
–50.0
–100.0
–150.0
I
OH
I
MAX Spec
I
OH
OH
Voltage Out (V)
Figure 2-2 • 3.3 V PCI V/I Curve for SX-A Family
IOH = (98.0/VCCI) * (VOUT – VCCI) * (VOUT + 0.4VCCI
)
IOL = (256/VCCI) * VOUT * (VCCI – VOUT
)
for 0.7 VCCI < VOUT < VCCI
for 0V < VOUT < 0.18 VCCI
EQ 2-3
EQ 2-4
v5.3
2-7
SX-A Family FPGAs
Power Dissipation
A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during
operation. The thermal characteristics of a circuit depend on the device and package used, the operating temperature,
the operating current, and the system's ability to dissipate heat.
A complete power evaluation should be performed early in the design process to help identify potential heat-related
problems in the system and to prevent the system from exceeding the device’s maximum allowed junction
temperature.
The actual power dissipated by most applications is significantly lower than the power the package can dissipate.
However, a thermal analysis should be performed for all projects. To perform a power evaluation, follow these steps:
1. Estimate the power consumption of the application.
2. Calculate the maximum power allowed for the device and package.
3. Compare the estimated power and maximum power values.
Estimating Power Dissipation
The total power dissipation for the SX-A family is the sum of the DC power dissipation and the AC power dissipation:
P
Total = PDC + PAC
EQ 2-5
DC Power Dissipation
The power due to standby current is typically a small component of the overall power. An estimation of DC power
dissipation under typical conditions is given by:
PDC = IStandby * VCCA
EQ 2-6
Note: For other combinations of temperature and voltage settings, refer to the eX, SX-A and RT54SX-S Power
Calculator.
AC Power Dissipation
The power dissipation of the SX-A family is usually dominated by the dynamic power dissipation. Dynamic power
dissipation is a function of frequency, equivalent capacitance, and power supply voltage. The AC power dissipation is
defined as follows:
PAC = PC-cells + PR-cells + PCLKA + PCLKB + PHCLK + POutput Buffer + PInput Buffer
EQ 2-7
or:
VCCA2 * [(m * CEQCM * fm)C-cells + (m * CEQSM * fm)R-cells + (n * CEQI * fn)Input Buffer + (p * (CEQO + CL) * fp)Output Buffer
PAC
=
+ (0.5 * (q1 * CEQCR * fq1) + (r1 * fq1 CLKA
))
+ (0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))CLKB + (0.5 * (s1 * CEQHV * fs1) +
(CEQHF * fs1))HCLK
]
EQ 2-8
2-8
v5.3
SX-A Family FPGAs
Where:
CEQCM = Equivalent capacitance of combinatorial modules
(C-cells) in pF
CEQSM = Equivalent capacitance of sequential modules (R-Cells) in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of CLKA/B in pF
CEQHV = Variable capacitance of HCLK in pF
CEQHF = Fixed capacitance of HCLK in pF
CL = Output lead capacitance in pF
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average CLKA rate in MHz
f
q2 = Average CLKB rate in MHz
fs1 = Average HCLK rate in MHz
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1 = Number of clock loads on CLKA
q2 = Number of clock loads on CLKB
r1 = Fixed capacitance due to CLKA
r2 = Fixed capacitance due to CLKB
s1 = Number of clock loads on HCLK
x = Number of I/Os at logic low
y = Number of I/Os at logic high
Table 2-11 • CEQ Values for SX-A Devices
A54SX08A
1.70 pF
1.50 pF
1.30 pF
7.40 pF
1.05 pF
0.85 pF
A54SX16A
2.00 pF
1.50 pF
1.30 pF
7.40 pF
1.05 pF
0.85 pF
A54SX32A
2.00 pF
1.30 pF
1.30 pF
7.40 pF
1.05 pF
0.85 pF
A54SX72A
1.80 pF
1.50 pF
1.30 pF
7.40 pF
1.05 pF
0.85 pF
Combinatorial modules (CEQCM
Sequential modules (CEQCM
Input buffers (CEQI
Output buffers (CEQO
)
)
)
)
Routed array clocks (CEQCR
)
Dedicated array clocks
–
variable
(CEQHV
Dedicated array clocks – fixed (CEQHF
Routed array clock A (r1)
)
)
30.00 pF
35.00 pF
55.00 pF
50.00 pF
110.00 pF
90.00 pF
240.00 pF
310.00 pF
v5.3
2-9
SX-A Family FPGAs
Guidelines for Estimating Power
The following guidelines are meant to represent worst-case scenarios; they can be generally used to predict the upper
limits of power dissipation:
Logic Modules (m) = 20% of modules
Inputs Switching (n) = Number inputs/4
Outputs Switching (p) = Number of outputs/4
CLKA Loads (q1) = 20% of R-cells
CLKB Loads (q2) = 20% of R-cells
Load Capacitance (CL) = 35 pF
Average Logic Module Switching Rate (fm) = f/10
Average Input Switching Rate (fn) =f/5
Average Output Switching Rate (fp) = f/10
Average CLKA Rate (fq1) = f/2
Average CLKB Rate (fq2) = f/2
Average HCLK Rate (fs1) = f
HCLK loads (s1) = 20% of R-cells
To assist customers in estimating the power dissipations of their designs, Actel has published the eX, SX-A and RT54SX-S
Power Calculator worksheet.
2-10
v5.3
SX-A Family FPGAs
Thermal Characteristics
Introduction
The temperature variable in Actel Designer software refers to the junction temperature, not the ambient, case, or
board temperatures. This is an important distinction because dynamic and static power consumption will cause the
chip's junction to be higher than the ambient, case, or board temperatures. EQ 2-9 and EQ 2-10 give the relationship
between thermal resistance, temperature gradient and power.
TJ – TA
θJA = ----------------
P
EQ 2-9
TC – TA
θJA = -----------------
P
EQ 2-10
Where:
θ
θ
=
=
Junction-to-air thermal resistance
Junction-to-case thermal resistance
JA
JC
TJ = Junction temperature
TA = Ambient temperature
TC = Ambient temperature
P
= total power dissipated by the device
Table 2-12 • Package Thermal Characteristics
θJA
Pin
1.0 m/s
2.5 m/s
Package Type
Count
θJC
14
11
11
8
Still Air 200 ft./min. 500 ft./min.
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Thin Quad Flat Pack (TQFP)
100
144
176
208
208
329
144
256
484
33.5
33.5
24.7
26.1
16.2
17.1
26.9
26.6
18
27.4
28
25
Thin Quad Flat Pack (TQFP)
25.7
18
Thin Quad Flat Pack (TQFP)
19.9
22.5
13.3
13.8
22.9
22.8
14.7
Plastic Quad Flat Pack (PQFP)1
Plastic Quad Flat Pack (PQFP) with Heat Spreader2
Plastic Ball Grid Array (PBGA)
Fine Pitch Ball Grid Array (FBGA)
Fine Pitch Ball Grid Array (FBGA)
Fine Pitch Ball Grid Array (FBGA)
20.8
11.9
12.8
21.5
21.5
13.6
3.8
3
3.8
3.8
3.2
Notes:
1. The A54SX08A PQ208 has no heat spreader.
2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A.
v5.3
2-11
SX-A Family FPGAs
Theta-JA
Junction-to-ambient thermal resistance (θ ) is determined under standard conditions specified by JESD-51 series but
JA
has little relevance in actual performance of the product in real application. It should be employed with caution but is
useful for comparing the thermal performance of one package to another.
A sample calculation to estimate the absolute maximum power dissipation allowed (worst case) for a 329-pin PBGA
package at still air is as follows. i.e.:
θJA = 17.1°C/W is taken from Table 2-12 on page 2-11
TA = 125°C is the maximum limit of ambient (from the datasheet)
Max Junction Temp – Max. Ambient Temp
150°C – 125°C
Max. Allowed Power = ----------------------------------------------------------------------------------------------------------- = --------------------------------------- = 1.46 W
θJA 17.1°C/W
EQ 2-11
The device's power consumption must be lower than the calculated maximum power dissipation by the package.
The power consumption of a device can be calculated using the Actel power calculator. If the power consumption is
higher than the device's maximum allowable power dissipation, then a heat sink can be attached on top of the case or
the airflow inside the system must be increased.
Theta-JC
Junction-to-case thermal resistance (θ ) measures the ability of a device to dissipate heat from the surface of the chip
JC
to the top or bottom surface of the package. It is applicable for packages used with external heat sinks and only
applies to situations where all or nearly all of the heat is dissipated through the surface in consideration. If the power
consumption is higher than the calculated maximum power dissipation of the package, then a heat sink is required.
Calculation for Heat Sink
For example, in a design implemented in a FG484 package, the power consumption value using the power calculator is
3.00 W. The user-dependent data TJ and TA are given as follows:
=
=
TJ
110°C
70°C
TA
From the datasheet:
θ
θ
=
=
18.0°C/W
3.2 °C/W
JA
JC
Max Junction Temp – Max. Ambient Temp
110°C – 70°C
P = ----------------------------------------------------------------------------------------------------------- = ------------------------------------ = 2.22 W
θJA 18.0°C/W
EQ 2-12
The 2.22 W power is less than then required 3.00 W; therefore, the design requires a heat sink or the airflow where the
device is mounted should be increased. The design's junction-to-air thermal resistance requirement can be estimated
by:
Max Junction Temp – Max. Ambient Temp
110°C – 70°C
3.00 W
θJA = ----------------------------------------------------------------------------------------------------------- = ------------------------------------ = 13.33°C/W
P
EQ 2-13
2-12
v5.3
SX-A Family FPGAs
To determine the heat sink's thermal performance, use the following equation:
θJA(TOTAL) = θJC + θCS + θSA
EQ 2-14
where:
θCS
=
=
0.37°C/W
thermal resistance of the interface material between the case and the heat
sink, usually provided by the thermal interface manufacturer
θSA
=
thermal resistance of the heat sink in °C/W
θSA = θJA(TOTAL) – θJC – θCS
EQ 2-15
θSA = 13.33°C/W – 3.20°C/W – 0.37°C/W
θSA = 9.76°C/W
A heat sink with a thermal resistance of 9.76°C/W or better should be used. Thermal resistance of heat sinks is a
function of airflow. The heat sink performance can be significantly improved with the presence of airflow.
Carefully estimating thermal resistance is important in the long-term reliability of an Actel FPGA. Design engineers
should always correlate the power consumption of the device with the maximum allowable power dissipation of the
package selected for that device, using the provided thermal resistance data.
Note: The values may vary depending on the application.
v5.3
2-13
SX-A Family FPGAs
SX-A Timing Model
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
Combinatorial
Cell
t
t
= 0.3 ns
= 0.5 ns
I/O Module
I/O Module
RD1
RD2
t
= 0.6 ns
INYH
t
= 3.9 ns
DHL
t
= 1.1 ns
PD
t
t
t
= 0.3 ns
RD1
= 0.9 ns
RD4
= 1.5 ns
RD8
I/O Module
t
t
t
t
= 3.9 ns
Register
Cell
DHL
D
Q
t
t
RD1
= 0.8 ns
= 0.0 ns
= 0.3 ns
SUD
HD
t
= 1.5 ns
ENZL
Routed
Clock
t
= 3.0 ns
RCKH
t
= 0.8 ns
(100% Load)
RCO
I/O Module
= 3.9 ns
DHL
Register
Cell
I/O Module
t
= 0.6 ns
INYH
D
Q
t
t
t
RD1
= 0.8 ns
= 0.0 ns
= 0.3 ns
SUD
= 1.5 ns
ENZL
HD
Hardwired
Clock
t
t
RCO
= 1.8 ns
= 0.8 ns
HCKH
Note: *Values shown for A54SX72A, –2, worst-case commercial conditions at 5 V PCI with standard place-and-route.
Figure 2-3 • SX-A Timing Model
Sample Path Calculations
Hardwired Clock
Routed Clock
External Setup
= (tINYH + tRD1 + tSUD) – tHCKH
= 0.6 + 0.3 + 0.8 - 1.8 = – 0.1 ns
External Setup
= (tINYH + tRD1 + tSUD) – tRCKH
= 0.6 + 0.3 + 0.8 - 3.0 = –1.3 ns
Clock-to-Out (Pad-to-Pad) = tHCKH + tRCO + tRD1 + tDHL
= 1.8 + 0.8 + 0.3 + 3.9 = 6.8 ns
Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tDHL
= 3.0 + 0.8 + 0.3 + 3.9 = 8.0 ns
2-14
v5.3
SX-A Family FPGAs
Output Buffer Delays
E
D
PAD To AC Test Loads (shown below)
TRIBUFF
VCC
VCC
VCC
In
50% 50%
VOH
En
GND
1.5 V
En
Out
50%
GND
90%
GND
10%
50%
VCC
50%
50%
1.5 V
VOL
Out
1.5 V
Out
GND
1.5 V
VOL
tDLH
tENHZ
tENZH
tENZL
tENLZ
Figure 2-4 • Output Buffer Delays
AC Test Loads
Load 1
(Used to measure
propagation delay)
Load 3
(Used to measure disable delays)
Load 2
(Used to measure enable delays)
VCC
VCC
GND
GND
To the Output
Under Test
t
t
R to VCC for
R to VCC for PZL
R to GND forPtZPLZH
R to GND for PZH
R = 1 kΩ
t
35 pF
To the Output
Under Test
To the Output
Under Test
R = 1 kΩ
35 pF
5 pF
Figure 2-5 • AC Test Loads
v5.3
2-15
SX-A Family FPGAs
Input Buffer Delays
C-Cell Delays
S
A
B
Y
Y
PAD
INBUF
VCC
GND
50%
VCC
S, A, or B 50%
3 V
50%
Out
GND
tPD
50%
In
1.5 V 1.5 V
VCC
0 V
tPD
VCC
50%
50%
Out
GND
50%
Out
GND
tPD
50%
tPD
tINY
tINY
Figure 2-6 • Input Buffer Delays
Figure 2-7 • C-Cell Delays
Cell Timing Characteristics
D
Q
PRESET
CLR
CLK
(Positive Edge Triggered)
tHD
D
tSUD
CLK
tHP
tHPWH
tRPWH
tHPWL
tRPWL
tRCO
Q
tCLR
tWASYN
tPRESET
CLR
PRESET
Figure 2-8 • Flip-Flops
2-16
v5.3
SX-A Family FPGAs
Long Tracks
Timing Characteristics
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6 percent of
nets in a fully utilized device require long tracks. Long
tracks contribute approximately 4 ns to 8.4 ns delay. This
additional delay is represented statistically in higher
fanout routing delays.
Timing characteristics for SX-A devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all SX-A family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. The timing characteristics listed in this
datasheet represent sample timing numbers of the SX-A
devices. Design-specific delay values may be determined
by using Timer or performing simulation after successful
place-and-route with the Designer software.
Timing Derating
SX-A devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case
processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating
temperature, and worst-case processing.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
timing-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to 6 percent of the nets in a design may be designated as
critical, while 90 percent of the nets in a design are
typical.
Temperature and Voltage Derating Factors
Table 2-13 • Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 2.25 V)
Junction Temperature (TJ)
VCCA
–55°C
0.79
–40°C
0.80
0°C
0.87
0.82
0.75
25°C
0.89
0.83
0.77
70°C
1.00
0.94
0.87
85°C
1.04
0.97
0.90
125°C
1.14
2.250 V
2.500 V
2.750 V
0.74
0.75
1.07
0.68
0.69
0.99
v5.3
2-17
SX-A Family FPGAs
Timing Characteristics
Table 2-14 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.25 V VCCI = 3.0 V, TJ = 70°C)
,
–2 Speed
–1 Speed
Std. Speed
–F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
C-Cell Propagation Delays1
tPD
Internal Array Module
0.9
1.1
1.2
1.7
ns
Predicted Routing Delays2
tDC
FO = 1 Routing Delay, Direct Connect
FO = 1 Routing Delay, Fast Connect
FO = 1 Routing Delay
0.1
0.3
0.3
0.5
0.6
0.8
1.4
2
0.1
0.3
0.4
0.5
0.7
0.9
1.5
2.2
0.1
0.4
0.5
0.6
0.8
1
0.1
0.6
0.6
0.8
1.1
1.4
2.5
3.6
ns
ns
ns
ns
ns
ns
ns
ns
tFC
tRD1
tRD2
FO = 2 Routing Delay
tRD3
FO = 3 Routing Delay
tRD4
FO = 4 Routing Delay
tRD8
FO = 8 Routing Delay
1.8
2.6
tRD12
R-Cell Timing
tRCO
FO = 12 Routing Delay
Sequential Clock-to-Q
0.7
0.6
0.7
0.8
0.6
0.7
0.9
0.8
0.9
1.3
1.0
1.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Hold Time
Clock Pulse Width
tPRESET
tSUD
0.7
0.0
1.4
0.4
0.3
1.6
0.8
0.0
1.5
0.4
0.3
1.8
0.9
0.0
1.8
0.5
0.4
2.1
1.2
0.0
2.5
0.7
0.6
2.9
tHD
tWASYN
tRECASYN
tHASYN
tMPW
Input Module Propagation Delays
tINYH Input Data Pad to Y High 2.5 V LVCMOS
tINYL
tINYH
tINYL
tINYH
tINYL
0.8
1.0
0.6
0.7
0.7
1.0
0.9
1.2
0.6
0.8
0.7
1.1
1.0
1.4
0.7
0.9
0.9
1.3
1.4
1.9
1.0
1.3
1.2
1.8
ns
ns
ns
ns
ns
ns
Input Data Pad to Y Low 2.5 V LVCMOS
Input Data Pad to Y High 3.3 V PCI
Input Data Pad to Y Low 3.3 V PCI
Input Data Pad to Y High 3.3 V LVTTL
Input Data Pad to Y Low 3.3 V LVTTL
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2-18
v5.3
SX-A Family FPGAs
–F Speed
Table 2-14 • A54SX08A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, VCCA = 2.25 V VCCI = 3.0 V, TJ = 70°C)
,
–2 Speed
–1 Speed
Std. Speed
Parameter
tINYH
Description
Input Data Pad to Y High 5 V PCI
Input Data Pad to Y Low 5 V PCI
Input Data Pad to Y High 5 V TTL
Input Data Pad to Y Low 5 V TTL
Min. Max. Min. Max. Min. Max. Min. Max. Units
0.5
0.8
0.5
0.8
0.6
0.9
0.6
0.9
0.7
1.1
0.7
1.1
0.9
1.5
0.9
1.5
ns
ns
ns
ns
tINYL
tINYH
tINYL
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
0.3
0.5
0.6
0.8
1.4
2
0.3
0.5
0.7
0.9
1.5
2.2
0.4
0.6
0.8
1
0.6
0.8
1.1
1.4
2.5
3.6
ns
ns
ns
ns
ns
ns
tIRD2
tIRD3
tIRD4
tIRD8
1.8
2.6
tIRD12
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.3
2-19
SX-A Family FPGAs
Table 2-15 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70°C)
–2 Speed –1 Speed Std. Speed
Min. Max. Min. Max. Min. Max. Min. Max. Units
–F Speed
Parameter
Description
Dedicated (Hardwired) Array Clock Networks
tHCKH
tHCKL
Input Low to High
(Pad to R-cell Input)
1.4
1.3
1.6
1.5
1.8
1.7
2.6
2.4
ns
ns
Input High to Low
(Pad to R-cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
0.4
0.4
0.5
0.7
ns
Minimum Period
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
1.0
1.1
1.0
1.1
1.1
1.3
1.1
1.2
1.1
1.2
1.2
1.5
1.3
1.4
1.3
1.4
1.4
1.7
1.8
2.0
1.8
2.0
2.0
2.4
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
0.7
0.7
0.9
0.8
0.8
1.0
0.9
0.9
1.2
1.3
1.3
1.7
2-20
v5.3
SX-A Family FPGAs
–F Speed
Table 2-16 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–2 Speed –1 Speed
Std. Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
tHCKH
tHCKL
Input Low to High
(Pad to R-cell Input)
1.3
1.1
1.5
1.3
1.7
1.5
2.6
2.2
ns
ns
Input High to Low
(Pad to R-cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
0.4
0.5
0.5
0.8
ns
Minimum Period
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
0.8
1.1
0.8
1.1
1.1
1.2
0.9
1.2
0.9
1.2
1.2
1.3
1.1
1.4
1.1
1.4
1.4
1.6
1.5
2
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
1.5
2
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
1.9
2.2
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
0.7
0.7
0.8
0.8
0.8
0.9
0.9
0.9
1.1
1.3
1.3
1.5
v5.3
2-21
SX-A Family FPGAs
Table 2-17 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
–2 Speed –1 Speed Std. Speed
Min. Max. Min. Max. Min. Max. Min. Max. Units
–F Speed
Parameter
Description
Dedicated (Hardwired) Array Clock Networks
tHCKH
tHCKL
Input Low to High
(Pad to R-cell Input)
1.2
1.0
1.3
1.2
1.5
1.4
2.3
2.0
ns
ns
Input High to Low
(Pad to R-cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
0.4
0.4
0.5
0.8
ns
Minimum Period
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
0.9
1.5
0.9
1.5
1.1
1.6
1.0
1.7
1.0
1.7
1.3
1.8
1.2
2.0
1.2
2.0
1.5
2.1
1.7
2.7
1.7
2.7
2.1
2.9
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
0.8
0.8
0.9
0.9
1.0
1.0
1.1
1.1
1.2
1.5
1.5
1.7
2-22
v5.3
SX-A Family FPGAs
–F Speed
Table 2-18 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3 V, TJ = 70°C)
–2 Speed –1 Speed
Std. Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
2.5 V LVCMOS Output Module Timing1,2
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
3.9
3.0
4.4
3.4
5.2
3.9
7.2
5.5
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
13.3
2.8
15.1
3.2
17.7
3.7
24.8
5.2
Data-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
13.7
3.9
15.5
4.4
18.2
5.2
25.5
7.2
Enable-to-Pad, L to Z
2.5
2.8
3.3
4.7
Enable-to-Pad, H to Z
3.0
3.4
3.9
5.5
3
dTLH
Delta Low to High
0.037
0.017
0.06
0.043
0.023
0.071
0.051
0.023
0.086
0.071 ns/pF
0.037 ns/pF
0.117 ns/pF
3
dTHL
Delta High to Low
3
dTHLS
Delta High to Low—low slew
Note:
1. Delays based on 35 pF loading.
2. The equivalent I/O Attribute Editor settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
v5.3
2-23
SX-A Family FPGAs
Table 2-19 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–2 Speed –1 Speed
Min. Max. Min. Max. Min. Max. Min. Max. Units
Std. Speed
–F Speed
Parameter
Description
3.3 V PCI Output Module Timing1
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
2.2
2.3
2.4
2.6
2.9
3.1
4.0
4.3
3.1
4.0
5.3
4.3
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
1.7
1.9
2.2
2.2
2.4
2.9
2.8
3.2
3.8
2.3
2.6
3.1
2
dTLH
0.03
0.015
0.03
0.015
0.04
0.015
0.045 ns/pF
0.025 ns/pF
2
dTHL
Delta High to Low
3.3 V LVTTL Output Module Timing3
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
3.0
3.0
3.4
3.3
4.0
3.9
5.6
5.5
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
10.4
2.6
11.8
2.9
13.8
3.4
19.3
4.8
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
18.9
3
21.3
3.4
25.4
4
34.9
5.6
Enable-to-Pad, L to Z
3.3
3.7
4.4
6.2
Enable-to-Pad, H to Z
3
3.3
3.9
5.5
2
dTLH
Delta Low to High
0.03
0.015
0.053
0.03
0.015
0.067
0.04
0.015
0.073
0.045 ns/pF
0.025 ns/pF
0.107 ns/pF
2
dTHL
Delta High to Low
2
dTHLS
Delta High to Low—low slew
Notes:
1. Delays based on 10 pF loading and 25 Ω resistance.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
3. Delays based on 35 pF loading.
2-24
v5.3
SX-A Family FPGAs
–F Speed
Table 2-20 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
–2 Speed –1 Speed Std. Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
5 V PCI Output Module Timing1
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
2.4
3.2
2.8
3.6
3.2
4.2
4.5
5.9
2.8
4.5
6.4
5.9
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
1.5
1.7
2.0
2.4
2.8
3.2
3.5
3.9
4.6
3.2
3.6
4.2
2
dTLH
0.016
0.03
0.02
0.032
0.022
0.04
0.032 ns/pF
0.052 ns/pF
2
dTHL
Delta High to Low
5 V TTL Output Module Timing3
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
2.4
3.2
2.8
3.6
3.2
4.2
4.5
5.9
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
dTLH
7.6
8.6
10.1
3.2
14.2
4.5
2.4
2.7
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
8.4
9.5
11.0
3.2
15.4
4.5
2.4
2.8
Enable-to-Pad, L to Z
4.2
4.7
5.6
7.8
Enable-to-Pad, H to Z
3.2
3.6
4.2
5.9
Delta Low to High
0.017
0.029
0.046
0.017
0.031
0.057
0.023
0.037
0.066
0.031 ns/pF
0.051 ns/pF
0.089 ns/pF
dTHL
Delta High to Low
dTHLS
Notes:
Delta High to Low—low slew
1. Delays based on 50 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
3. Delays based on 35 pF loading.
v5.3
2-25
SX-A Family FPGAs
Table 2-21 • A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.25 V VCCI = 3.0 V, TJ = 70°C)
,
–3 Speed1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
–2 Speed
–1 Speed
Std. Speed
–F Speed
Parameter
C-Cell Propagation Delays2
tPD Internal Array Module
Predicted Routing Delays3
Description
0.9
0.1
1.0
0.1
1.2
0.1
1.4
0.1
1.9
0.1
ns
ns
tDC
FO
= 1 Routing Delay, Direct
Connect
tFC
FO = 1 Routing Delay, Fast Connect
FO = 1 Routing Delay
0.3
0.3
0.4
0.5
0.7
1.2
1.7
0.3
0.3
0.5
0.6
0.8
1.4
2
0.3
0.4
0.5
0.7
0.9
1.5
2.2
0.4
0.5
0.6
0.8
1
0.6
0.6
0.8
1.1
1.4
2.5
3.6
ns
ns
ns
ns
ns
ns
ns
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
1.8
2.6
FO = 12 Routing Delay
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.6
0.5
0.7
0.7
0.6
0.8
0.8
0.6
0.8
0.9
0.8
1.0
1.3
1.0
1.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Clock Minimum Pulse Width
tPRESET
tSUD
0.7
0.0
1.3
0.3
0.3
1.4
0.8
0.0
1.5
0.4
0.3
1.7
0.9
0.0
1.6
0.4
0.3
1.9
1.0
0.0
1.9
0.5
0.4
2.2
1.4
0.0
2.7
0.7
0.6
3.0
tHD
tWASYN
tRECASYN
tHASYN
tMPW
Input Module Propagation Delays
tINYH Input Data Pad to Y High 2.5 V
0.5
0.8
0.6
0.9
0.7
1.0
0.8
1.1
1.1
1.6
ns
ns
LVCMOS
tINYL
Input Data Pad to Y Low 2.5 V
LVCMOS
tINYH
tINYL
tINYH
Input Data Pad to Y High 3.3 V PCI
Input Data Pad to Y Low 3.3 V PCI
0.5
0.7
0.7
0.6
0.8
0.7
0.6
0.9
0.8
0.7
1.0
1.0
1.0
1.4
1.4
ns
ns
ns
Input Data Pad to Y High 3.3 V
LVTTL
tINYL
Input Data Pad to Y Low 3.3 V LVTTL
0.9
1.1
1.2
1.4
2.0
ns
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2-26
v5.3
SX-A Family FPGAs
Std. Speed –F Speed
Table 2-21 • A54SX16A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, VCCA = 2.25 V VCCI = 3.0 V, TJ = 70°C)
,
–3 Speed1
–2 Speed
–1 Speed
Parameter
tINYH
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Data Pad to Y High 5 V PCI
Input Data Pad to Y Low 5 V PCI
Input Data Pad to Y High 5 V TTL
Input Data Pad to Y Low 5 V TTL
0.5
0.7
0.5
0.7
0.5
0.8
0.5
0.8
0.6
0.9
0.6
0.9
0.7
1.1
0.7
1.1
0.9
1.5
0.9
1.5
ns
ns
ns
ns
tINYL
tINYH
tINYL
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
0.3
0.4
0.5
0.7
1.2
1.7
0.3
0.5
0.6
0.8
1.4
2.0
0.3
0.5
0.7
0.9
1.5
2.2
0.4
0.6
0.8
1.0
0.8
2.6
0.6
0.8
1.1
1.4
2.5
3.6
ns
ns
ns
ns
ns
ns
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.3
2-27
SX-A Family FPGAs
Table 2-22 • A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.2
1.4
1.6
1.8
2.8
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.0
1.1
1.2
1.5
2.2
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.4
1.4
1.7
1.7
1.9
1.9
2.2
2.2
3.0
3.0
ns
ns
0.3
0.3
0.4
0.4
0.7
ns
Minimum Period
2.8
3.4
3.8
4.4
6.0
ns
fHMAX
Maximum Frequency
357
294
263
227
167
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
1.0
1.1
1.1
1.1
1.3
1.3
1.2
1.3
1.3
1.3
1.5
1.5
1.3
1.5
1.5
1.5
1.7
1.7
1.6
1.7
1.7
1.7
2.0
2.0
2.2
2.4
2.4
2.4
2.8
2.8
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.4
1.4
1.7
1.7
1.9
1.9
2.2
2.2
3.0
3.0
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
0.8
0.8
1.0
0.9
0.9
1.1
1.0
1.0
1.3
1.2
1.2
1.5
1.7
1.7
2.1
Note: *All –3 speed grades have been discontinued.
2-28
v5.3
SX-A Family FPGAs
Table 2-23 • A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.2
1.4
1.6
1.8
2.8
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.0
1.1
1.3
1.5
2.2
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.4
1.4
1.7
1.7
1.9
1.9
2.2
2.2
3.0
3.0
ns
ns
0.3
0.3
0.4
0.4
0.6
ns
Minimum Period
2.8
3.4
3.8
4.4
6.0
ns
fHMAX
Maximum Frequency
357
294
263
227
167
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
1.0
1.1
1.1
1.1
1.3
1.3
1.2
1.3
1.3
1.3
1.5
1.5
1.3
1.5
1.4
1.5
1.7
1.7
1.5
1.7
1.7
1.7
2.0
2.0
2.1
2.4
2.3
2.4
2.7
2.8
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.4
1.4
1.7
1.7
1.9
1.9
2.2
2.2
3.0
3.0
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
0.8
0.8
1.0
0.9
0.9
1.1
1.0
1.0
1.3
1.2
1.2
1.5
1.7
1.7
2.1
Note: *All –3 speed grades have been discontinued.
v5.3
2-29
SX-A Family FPGAs
Table 2-24 • A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI =4.75 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.2
1.4
1.6
1.8
2.8
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.0
1.1
1.2
1.5
2.2
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.4
1.4
1.7
1.7
1.9
1.9
2.2
2.2
3.0
3.0
ns
ns
0.3
0.3
0.4
0.4
0.7
ns
Minimum Period
2.8
3.4
3.8
4.4
6.0
ns
fHMAX
Maximum Frequency
357
294
263
227
167
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
1.0
1.1
1.1
1.1
1.3
1.3
1.2
1.3
1.3
1.3
1.5
1.5
1.3
1.5
1.5
1.5
1.7
1.7
1.6
1.7
1.7
1.7
2.0
2.0
2.2
2.4
2.4
2.4
2.8
2.8
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.4
1.4
1.7
1.7
1.9
1.9
2.2
2.2
3.0
3.0
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
0.8
0.8
1.0
0.9
0.9
1.1
1.0
1.0
1.3
1.2
1.2
1.5
1.7
1.7
2.1
Note: *All –3 speed grades have been discontinued.
2-30
v5.3
SX-A Family FPGAs
Table 2-25 • A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2.5 V LVCMOS Output Module Timing 2, 3
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
3.4
2.6
3.9
3.0
4.5
3.3
5.2
3.9
7.3
5.5
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
11.6
2.4
13.4
2.8
15.2
3.2
17.9
3.7
25.0
5.2
Data-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
11.8
3.4
13.7
3.9
15.5
4.5
18.2
5.2
25.5
7.3
Enable-to-Pad, L to Z
2.1
2.5
2.8
3.3
4.7
Enable-to-Pad, H to Z
2.6
3.0
3.3
3.9
5.5
4
dTLH
Delta Low to High
0.031
0.017
0.057
0.037
0.017
0.06
0.043
0.023
0.071
0.051
0.023
0.086
0.071 ns/pF
0.037 ns/pF
0.117 ns/pF
4
dTHL
Delta High to Low
4
dTHLS
Delta High to Low—low slew
Note:
1. All –3 speed grades have been discontinued.
2. Delays based on 35 pF loading.
3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
v5.3
2-31
SX-A Family FPGAs
Table 2-26 • A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Parameter
Description
3.3 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
2.0
2.2
2.3
2.5
2.6
2.8
3.1
3.3
4.3
4.6
3.1
4.3
5.3
4.6
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
1.4
1.7
1.9
2.2
2.0
2.3
2.6
3.1
2.5
2.8
3.2
3.8
2.2
2.5
2.8
3.3
3
dTLH
0.025
0.015
0.03
0.015
0.03
0.015
0.04
0.015
0.045 ns/pF
0.025 ns/pF
3
dTHL
Delta High to Low
3.3 V LVTTL Output Module Timing4
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
2.8
2.7
3.2
3.1
3.6
3.5
4.3
4.1
6.0
5.7
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
9.5
10.9
2.6
12.4
2.9
14.6
3.4
20.4
4.8
2.2
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
15.8
2.8
18.9
3.2
21.3
3.6
25.4
4.3
34.9
6.0
Enable-to-Pad, L to Z
2.9
3.3
3.7
4.4
6.2
Enable-to-Pad, H to Z
2.7
3.1
3.5
4.1
5.7
3
dTLH
Delta Low to High
0.025
0.015
0.053
0.03
0.015
0.053
0.03
0.015
0.067
0.04
0.015
0.073
0.045 ns/pF
0.025 ns/pF
0.107 ns/pF
3
dTHL
Delta High to Low
3
dTHLS
Delta High to Low—low slew
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 10 pF loading and 25 Ω resistance.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
2-32
v5.3
SX-A Family FPGAs
Table 2-27 • A54SX16A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
2.2
2.8
2.5
3.2
2.8
3.6
3.3
4.2
4.6
5.9
2.8
4.6
6.4
5.9
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
1.3
1.5
1.7
2.0
2.2
2.5
2.8
3.3
3.0
3.5
3.9
4.6
2.8
3.2
3.6
4.2
3
dTLH
0.016
0.026
0.016
0.03
0.02
0.032
0.022
0.04
0.032 ns/pF
0.052 ns/pF
3
dTHL
Delta High to Low
5 V TTL Output Module Timing4
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
2.2
2.8
2.5
3.2
2.8
3.6
3.3
4.2
4.6
5.9
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
6.7
7.7
8.7
10.2
3.2
14.3
4.5
2.1
2.4
2.7
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
7.4
8.4
9.5
11.0
2.9
15.4
4.1
1.9
2.2
2.5
Enable-to-Pad, L to Z
3.6
4.2
4.7
5.6
7.8
Enable-to-Pad, H to Z
2.5
2.9
3.3
3.9
5.4
3
dTLH
Delta Low to High
0.014
0.023
0.043
0.017
0.029
0.046
0.017
0.031
0.057
0.023
0.037
0.066
0.031 ns/pF
0.051 ns/pF
0.089 ns/pF
3
dTHL
Delta High to Low
3
dTHLS
Delta High to Low—low slew
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 50 pF loading.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
v5.3
2-33
SX-A Family FPGAs
Table 2-28 • A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.25 V VCCI = 3.0 V, TJ = 70°C)
,
–3 Speed1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
–2 Speed
–1 Speed
Std. Speed
–F Speed
Parameter
C-Cell Propagation Delays2
tPD Internal Array Module
Predicted Routing Delays3
Description
0.8
0.1
0.9
0.1
1.1
0.1
1.2
0.1
1.7
0.1
ns
ns
tDC
FO
= 1 Routing Delay, Direct
Connect
tFC
FO = 1 Routing Delay, Fast Connect
FO = 1 Routing Delay
0.3
0.3
0.4
0.5
0.7
1.2
1.7
0.3
0.3
0.5
0.6
0.8
1.4
2.0
0.3
0.4
0.5
0.7
0.9
1.5
2.2
0.4
0.5
0.6
0.8
1.0
1.8
2.6
0.6
0.6
0.8
1.1
1.4
2.5
3.6
ns
ns
ns
ns
ns
ns
ns
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.6
0.5
0.6
0.7
0.6
0.7
0.8
0.6
0.7
0.9
0.8
0.9
1.3
1.0
1.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Clock Pulse Width
tPRESET
tSUD
0.6
0.0
1.2
0.3
0.3
1.4
0.7
0.0
1.4
0.4
0.3
1.6
0.8
0.0
1.5
0.4
0.3
1.8
0.9
0.0
1.8
0.5
0.4
2.1
1.2
0.0
2.5
0.7
0.6
2.9
tHD
tWASYN
tRECASYN
tHASYN
tMPW
Input Module Propagation Delays
tINYH Input Data Pad to Y High 2.5 V
0.6
1.2
0.7
1.3
0.8
1.5
0.9
1.8
1.2
2.5
ns
ns
LVCMOS
tINYL
Input Data Pad to Y Low 2.5 V
LVCMOS
tINYH
tINYL
tINYH
Input Data Pad to Y High 3.3 V PCI
Input Data Pad to Y Low 3.3 V PCI
0.5
0.6
0.8
0.6
0.7
0.9
0.6
0.8
1.0
0.7
0.9
1.2
1.0
1.3
1.6
ns
ns
ns
Input Data Pad to Y High 3.3 V
LVTTL
tINYL
Input Data Pad to Y Low 3.3 V LVTTL
1.4
1.6
1.8
2.2
3.0
ns
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2-34
v5.3
SX-A Family FPGAs
Std. Speed –F Speed
Table 2-28 • A54SX32A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, VCCA = 2.25 V VCCI = 3.0 V, TJ = 70°C)
,
–3 Speed1
–2 Speed
–1 Speed
Parameter
tINYH
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Data Pad to Y High 5 V PCI
Input Data Pad to Y Low 5 V PCI
Input Data Pad to Y High 5 V TTL
Input Data Pad to Y Low 5 V TTL
0.7
0.9
0.9
1.4
0.8
1.1
1.1
1.6
0.9
1.2
1.2
1.8
1.0
1.4
1.4
2.1
1.4
1.9
1.9
2.9
ns
ns
ns
ns
tINYL
tINYH
tINYL
Input Module Predicted Routing Delays3
tIRD1
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
0.3
0.4
0.5
0.7
1.2
1.7
0.3
0.5
0.6
0.8
1.4
2
0.3
0.5
0.7
0.9
1.5
2.2
0.4
0.6
0.8
1
0.6
0.8
1.1
1.4
2.5
3.6
ns
ns
ns
ns
ns
ns
tIRD2
tIRD3
tIRD4
tIRD8
1.8
2.6
tIRD12
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.3
2-35
SX-A Family FPGAs
Table 2-29 • A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
0.6
0.6
0.7
0.8
1.3
ns
Minimum Period
2.8
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
357
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.1
2.4
2.2
2.5
2.4
2.5
2.4
2.7
2.5
2.9
2.7
2.9
2.7
3.1
2.8
3.2
3.1
3.4
3.2
3.6
3.3
3.8
3.6
4.7
4.4
5.1
4.6
5.3
5.0
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
1.0
0.9
0.9
1.1
1.0
1.0
1.3
1.2
1.2
1.5
1.4
1.4
2.1
1.9
1.9
Note: *All –3 speed grades have been discontinued.
2-36
v5.3
SX-A Family FPGAs
Table 2-30 • A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
0.6
0.6
0.7
0.8
1.3
ns
Minimum Period
2.8
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
357
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.1
2.3
2.2
2.4
2.4
2.5
2.4
2.7
2.5
2.8
2.8
2.8
2.7
3.1
2.9
3.2
3.1
3.3
3.2
3.6
3.4
3.7
3.7
4.6
4.5
5
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
4.7
5.2
5.1
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
1.0
0.9
0.9
1.1
1.0
1.0
1.3
1.2
1.2
1.5
1.4
1.4
2.1
1.9
1.9
Note: *All –3 speed grades have been discontinued.
v5.3
2-37
SX-A Family FPGAs
Table 2-31 • A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.7
1.9
2.2
2.6
4.0
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
0.6
0.6
0.7
0.8
1.3
ns
Minimum Period
2.8
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
357
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.1
2.4
2.2
2.5
2.4
2.5
2.5
2.7
2.6
2.8
2.8
2.8
2.8
3.1
2.9
3.2
3.1
3.3
3.3
3.6
3.4
3.8
3.7
4.7
4.5
5.1
4.7
5.3
5.2
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.4
1.4
1.6
1.6
1.8
1.8
2.1
2.1
2.9
2.9
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
1.0
1.0
1.0
1.1
1.1
1.1
1.3
1.3
1.3
1.5
1.5
1.5
2.1
2.1
2.1
Note: *All –3 speed grades have been discontinued.
2-38
v5.3
SX-A Family FPGAs
Table 2-32 • A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
2.5 V LVCMOS Output Module Timing 2,3
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
3.3
2.5
3.8
2.9
4.2
3.2
5.0
3.8
7.0
5.3
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
11.1
2.4
12.8
2.8
14.5
3.2
17.0
3.7
23.8
5.2
Data-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
11.8
3.3
13.7
3.8
15.5
4.2
18.2
5.0
25.5
7.0
Enable-to-Pad, L to Z
2.1
2.5
2.8
3.3
4.7
Enable-to-Pad, H to Z
2.5
2.9
3.2
3.8
5.3
4
dTLH
Delta Low to High
0.031
0.017
0.057
0.037
0.017
0.06
0.043
0.023
0.071
0.051
0.023
0.086
0.071 ns/pF
0.037 ns/pF
0.117 ns/pF
4
dTHL
Delta High to Low
4
dTHLS
Delta High to Low—low slew
Note:
1. All –3 speed grades have been discontinued.
2. Delays based on 35 pF loading.
3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
v5.3
2-39
SX-A Family FPGAs
Table 2-33 • A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Parameter
Description
3.3 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
1.9
2.0
2.2
2.3
2.4
2.6
2.9
3.1
4.0
4.3
3.1
4.0
5.3
4.3
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
1.4
1.7
1.9
2.2
1.9
2.2
2.4
2.9
2.5
2.8
3.2
3.8
2.0
2.3
2.6
3.1
3
dTLH
0.025
0.015
0.03
0.015
0.03
0.015
0.04
0.015
0.045 ns/pF
0.025 ns/pF
3
dTHL
Delta High to Low
3.3 V LVTTL Output Module Timing4
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
2.6
2.6
3.0
3.0
3.4
3.3
4.0
3.9
5.6
5.5
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
9.0
10.4
2.6
11.8
2.9
13.8
3.4
19.3
4.8
2.2
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
15.8
2.6
18.9
3.0
21.3
3.4
25.4
4.0
34.9
5.6
Enable-to-Pad, L to Z
2.9
3.3
3.7
4.4
6.2
Enable-to-Pad, H to Z
2.6
3.0
3.3
3.9
5.5
3
dTLH
Delta Low to High
0.025
0.015
0.053
0.03
0.015
0.053
0.03
0.015
0.067
0.04
0.015
0.073
0.045 ns/pF
0.025 ns/pF
0.107 ns/pF
3
dTHL
Delta High to Low
3
dTHLS
Delta High to Low—low slew
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 10 pF loading and 25 Ω resistance.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
2-40
v5.3
SX-A Family FPGAs
Table 2-34 • A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
2.1
2.8
2.4
3.2
2.8
3.6
3.2
4.2
4.5
5.9
2.8
4.5
6.4
5.9
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
1.3
1.5
1.7
2.0
2.1
2.4
2.8
3.2
3.0
3.5
3.9
4.6
2.8
3.2
3.6
4.2
3
dTLH
0.016
0.026
0.016
0.03
0.02
0.032
0.022
0.04
0.032 ns/pF
0.052 ns/pF
3
dTHL
Delta High to Low
5 V TTL Output Module Timing4
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
1.9
2.5
2.2
2.9
2.5
3.3
2.9
3.9
4.1
5.4
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
6.6
7.6
8.6
10.1
3.2
14.2
4.5
2.1
2.4
2.7
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
7.4
8.4
9.5
11.0
2.9
15.4
4.1
1.9
2.2
2.5
Enable-to-Pad, L to Z
3.6
4.2
4.7
5.6
7.8
Enable-to-Pad, H to Z
2.5
2.9
3.3
3.9
5.4
3
dTLH
Delta Low to High
0.014
0.023
0.043
0.017
0.029
0.046
0.017
0.031
0.057
0.023
0.037
0.066
0.031 ns/pF
0.051 ns/pF
0.089 ns/pF
3
dTHL
Delta High to Low
3
dTHLS
Delta High to Low—low slew
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 50 pF loading.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
v5.3
2-41
SX-A Family FPGAs
Table 2-35 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.25 V VCCI = 3.0 V, TJ = 70°C)
,
–3 Speed1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
–2 Speed
–1 Speed
Std. Speed
–F Speed
Parameter
C-Cell Propagation Delays2
tPD Internal Array Module
Predicted Routing Delays3
Description
1.0
0.1
1.1
0.1
1.3
0.1
1.5
0.1
2.0
0.1
ns
ns
tDC
FO
= 1 Routing Delay, Direct
Connect
tFC
FO = 1 Routing Delay, Fast Connect
FO = 1 Routing Delay
0.3
0.3
0.4
0.5
0.7
1.2
1.7
0.3
0.3
0.5
0.7
0.9
1.5
2.2
0.3
0.4
0.6
0.8
1
0.4
0.5
0.7
0.9
1.1
2.1
3
0.6
0.7
1
ns
ns
ns
ns
ns
ns
ns
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
FO = 2 Routing Delay
FO = 3 Routing Delay
1.3
1.5
2.9
4.2
FO = 4 Routing Delay
FO = 8 Routing Delay
1.7
2.5
FO = 12 Routing Delay
R-Cell Timing
tRCO
Sequential Clock-to-Q
0.7
0.6
0.7
0.8
0.7
0.8
0.9
0.7
0.8
1.1
0.9
1.0
1.5
1.2
1.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Hold Time
Clock Minimum Pulse Width
tPRESET
tSUD
0.7
0.0
1.3
0.3
0.3
1.5
0.8
0.0
1.5
0.4
0.3
1.7
0.9
0.0
1.7
0.4
0.3
2.0
1.0
0.0
2.0
0.5
0.4
2.3
1.4
0.0
2.8
0.7
0.6
3.2
tHD
tWASYN
tRECASYN
tHASYN
tMPW
Input Module Propagation Delays
tINYH Input Data Pad to Y High 2.5 V
0.6
0.8
0.7
1.0
0.8
1.1
0.9
1.3
1.3
1.7
ns
ns
LVCMOS
tINYL
Input Data Pad to Y Low 2.5 V
LVCMOS
tINYH
tINYL
tINYH
Input Data Pad to Y High 3.3 V PCI
Input Data Pad to Y Low 3.3 V PCI
0.6
0.7
0.7
0.7
0.8
0.7
0.7
0.9
0.8
0.9
1.0
1.0
1.2
1.4
1.4
ns
ns
ns
Input Data Pad to Y High 3.3 V
LVTTL
tINYL
Input Data Pad to Y Low 3.3 V LVTTL
1.0
1.2
1.3
1.5
2.1
ns
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2-42
v5.3
SX-A Family FPGAs
Std. Speed –F Speed
Table 2-35 • A54SX72A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, VCCA = 2.25 V VCCI = 3.0 V, TJ = 70°C)
,
–3 Speed1
–2 Speed
–1 Speed
Parameter
tINYH
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Data Pad to Y High 5 V PCI
Input Data Pad to Y Low 5 V PCI
Input Data Pad to Y High 5 V TTL
Input Data Pad to Y Low 5 V TTL
0.5
0.8
0.7
0.9
0.6
0.9
0.8
1.1
0.7
1.0
0.9
1.2
0.8
1.2
1.0
1.4
1.1
1.6
1.4
1.9
ns
ns
ns
ns
tINYL
tINYH
tINYL
Input Module Predicted Routing Delays3
tIRD1
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
0.3
0.4
0.5
0.7
1.2
1.7
0.3
0.5
0.7
0.9
1.5
2.2
0.4
0.6
0.8
1
0.5
0.7
0.9
1.1
2.1
3
0.7
1
ns
ns
ns
ns
ns
ns
tIRD2
tIRD3
1.3
1.5
2.9
4.2
tIRD4
tIRD8
1.7
2.5
tIRD12
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.3
2-43
SX-A Family FPGAs
Table 2-36 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Std. Speed
–F Speed
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.6
1.9
2.1
2.5
3.8
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.6
1.9
2.1
2.5
3.8
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
1.4
1.6
1.8
2.1
3.3
Minimum Period
3.0
3.4
4.0
4.6
6.4
fHMAX
Maximum Frequency
333
294
250
217
156 MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
2.3
2.8
2.4
2.9
2.6
3.1
2.6
3.2
2.8
3.3
3.0
3.6
2.9
3.7
3.2
3.8
3.4
4.0
3.4
4.3
3.7
4.5
4.0
4.7
4.8
6.0
5.2
6.2
5.6
6.6
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
1.9
1.8
1.8
2.2
2.1
2.1
2.5
2.4
2.4
3.0
2.8
2.8
4.1
3.9
3.9
Quadrant Array Clock Networks
tQCKH
tQCHKL
tQCKH
tQCHKL
Input Low to High (Light Load)
(Pad to R-cell Input)
2.6
2.6
2.8
2.8
3.0
3.0
3.2
3.2
3.4
3.3
3.6
3.6
4.0
3.9
4.3
4.2
5.6
5.5
6.0
5.9
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Note: *All –3 speed grades have been discontinued.
2-44
v5.3
SX-A Family FPGAs
Std. Speed –F Speed
Table 2-36 • A54SX72A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.25 V, TJ = 70°C)
–3 Speed*
–2 Speed
–1 Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tQCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
3.0
3.4
3.9
4.6
6.4
ns
tQCHKL
Input High to Low (100% Load)
(Pad to R-cell Input)
2.9
3.4
3.8
4.5
6.3
ns
tQPWH
tQPWL
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
ns
tQCKSW
tQCKSW
tQCKSW
0.2
0.4
0.4
0.3
0.5
0.5
0.3
0.5
0.5
0.3
0.6
0.6
0.5
0.9
0.9
Note: *All –3 speed grades have been discontinued.
v5.3
2-45
SX-A Family FPGAs
Table 2-37 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Std. Speed
–F Speed
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.6
1.9
2.1
2.5
3.8
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.7
1.9
2.1
2.5
3.8
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
1.4
1.6
1.8
2.1
3.3
Minimum Period
3.0
3.4
4.0
4.6
6.4
fHMAX
Maximum Frequency
333
294
250
217
156 MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.8
2.4
2.9
2.6
3.1
2.6
3.3
2.8
3.4
3.0
3.6
2.9
3.7
3.2
3.8
3.4
4.1
3.4
4.3
3.7
4.5
4.0
4.8
4.8
6.0
5.2
6.2
5.6
6.7
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
1.9
1.9
1.9
2.2
2.1
2.1
2.5
2.4
2.4
3
4.1
3.9
3.9
2.8
2.8
Quadrant Array Clock Networks
tQCKH
tQCHKL
tQCKH
tQCHKL
Input Low to High (Light Load)
(Pad to R-cell Input)
1.3
1.3
1.5
1.5
1.5
1.5
1.7
1.8
1.7
1.7
1.9
2
1.9
2
2.7
2.8
3.1
3.2
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
2.2
2.3
Input High to Low (50% Load)
(Pad to R-cell Input)
Note: *All –3 speed grades have been discontinued.
2-46
v5.3
SX-A Family FPGAs
Std. Speed –F Speed
Table 2-37 • A54SX72A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–3 Speed*
–2 Speed
–1 Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tQCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
1.7
1.9
2.2
2.5
3.5
ns
tQCHKL
Input High to Low (100% Load)
(Pad to R-cell Input)
1.7
2
2.2
2.6
3.6
ns
tQPWH
tQPWL
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
ns
tQCKSW
tQCKSW
tQCKSW
0.2
0.4
0.4
0.3
0.5
0.5
0.3
0.5
0.5
0.3
0.6
0.6
0.5
0.9
0.9
Note: *All –3 speed grades have been discontinued.
v5.3
2-47
SX-A Family FPGAs
Table 2-38 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
–3 Speed* –2 Speed –1 Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
Std. Speed
–F Speed
Parameter
Description
tHCKH
Input Low to High
(Pad to R-cell Input)
1.6
1.8
2.1
2.4
3.8
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.6
1.9
2.1
2.5
3.8
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
1.4
1.6
1.8
2.1
3.3
Minimum Period
3.0
3.4
4.0
4.6
6.4
fHMAX
Maximum Frequency
333
294
250
217
156 MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-cell Input)
2.3
2.8
2.5
3.0
2.6
3.2
2.6
3.2
2.9
3.4
3.0
3.6
3.0
3.6
3.2
3.9
3.4
4.1
3.5
4.3
3.8
4.6
3.9
4.8
4.9
6.0
5.3
6.4
5.5
6.8
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
tRPWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
ns
tRPWL
tRCKSW
tRCKSW
tRCKSW
1.9
1.9
1.9
2.2
2.2
2.2
2.5
2.5
2.5
3.0
3.0
3.0
4.1
4.1
4.1
Quadrant Array Clock Networks
tQCKH
tQCHKL
tQCKH
tQCHKL
Input Low to High (Light Load)
(Pad to R-cell Input)
1.2
1.3
1.4
1.4
1.4
1.4
1.6
1.7
1.6
1.6
1.8
1.9
1.8
1.9
2.1
2.2
2.6
2.7
3.0
3.1
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Note: *All –3 speed grades have been discontinued.
2-48
v5.3
SX-A Family FPGAs
Std. Speed –F Speed
Table 2-38 • A54SX72A Timing Characteristics (Continued)
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
–3 Speed*
–2 Speed
–1 Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tQCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
1.6
1.8
2.1
2.4
3.4
ns
tQCHKL
Input High to Low (100% Load)
(Pad to R-cell Input)
1.6
1.9
2.1
2.5
3.5
ns
tQPWH
tQPWL
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.5
1.5
1.7
1.7
2.0
2.0
2.3
2.3
3.2
3.2
ns
ns
ns
ns
ns
tQCKSW
tQCKSW
tQCKSW
0.2
0.4
0.4
0.3
0.5
0.5
0.3
0.5
0.5
0.3
0.6
0.6
0.5
0.9
0.9
Note: *All –3 speed grades have been discontinued.
v5.3
2-49
SX-A Family FPGAs
Table 2-39 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Parameter
Description
2.5 V LVCMOS Output Module Timing2, 3
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
3.9
3.1
4.5
3.6
5.1
4.1
6.0
4.8
8.4
6.7
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
12.7
2.4
14.6
2.8
16.5
3.2
19.4
3.7
27.2
5.2
Data-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
11.8
3.9
13.7
4.5
15.5
5.1
18.2
6.0
25.5
8.4
Enable-to-Pad, L to Z
2.1
2.5
2.8
3.3
4.7
Enable-to-Pad, H to Z
3.1
3.6
4.1
4.8
6.7
4
dTLH
Delta Low to High
0.031
0.017
0.057
0.037
0.017
0.06
0.043
0.023
0.071
0.051
0.023
0.086
0.071 ns/pF
0.037 ns/pF
0.117 ns/pF
4
dTHL
Delta High to Low
4
dTHLS
Delta High to Low—low slew
Note:
1. All –3 speed grades have been discontinued.
2. Delays based on 35 pF loading.
3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
2-50
v5.3
SX-A Family FPGAs
Table 2-40 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
3.3 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
2.3
2.5
2.7
2.9
3.0
3.2
3.6
3.8
5.0
5.3
3.1
5.0
5.3
5.3
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
1.4
1.7
1.9
2.2
2.3
2.7
3.0
3.6
2.5
2.8
3.2
3.8
2.5
2.9
3.2
3.8
3
dTLH
0.025
0.015
0.03
0.015
0.03
0.015
0.04
0.015
0.045 ns/pF
0.025 ns/pF
3
dTHL
Delta High to Low
3.3 V LVTTL Output Module Timing4
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
3.2
3.2
3.7
3.7
4.2
4.2
5.0
4.9
6.9
6.9
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
10.3
2.2
11.9
2.6
13.5
2.9
15.8
3.4
22.2
4.8
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
15.8
3.2
18.9
3.7
21.3
4.2
25.4
5.0
34.9
6.9
Enable-to-Pad, L to Z
2.9
3.3
3.7
4.4
6.2
Enable-to-Pad, H to Z
3.2
3.7
4.2
4.9
6.9
3
dTLH
Delta Low to High
0.025
0.015
0.053
0.03
0.015
0.053
0.03
0.015
0.067
0.04
0.015
0.073
0.045 ns/pF
0.025 ns/pF
0.107 ns/pF
3
dTHL
Delta High to Low
3
dTHLS
Delta High to Low—low slew
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 10 pF loading and 25 Ω resistance.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
v5.3
2-51
SX-A Family FPGAs
Table 2-41 • A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
–3 Speed1
–2 Speed –1 Speed Std. Speed –F Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Parameter
Description
5 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
2.7
3.4
3.1
3.9
3.5
4.4
4.1
5.1
5.7
7.2
2.8
5.7
6.4
7.2
ns
ns
ns
ns
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
1.3
1.5
1.7
2.0
2.7
3.1
3.5
4.1
3.0
3.5
3.9
4.6
3.4
3.9
4.4
5.1
3
dTLH
0.016
0.026
0.016
0.03
0.02
0.032
0.022
0.04
0.032 ns/pF
0.052 ns/pF
3
dTHL
Delta High to Low
5 V TTL Output Module Timing4
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
2.4
3.1
2.8
3.5
3.1
4.0
3.7
4.7
5.1
6.6
ns
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
7.4
8.5
9.7
11.4
3.2
15.9
4.5
2.1
2.4
2.7
Enable-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
7.4
8.4
9.5
11.0
3.7
15.4
5.1
2.4
2.8
3.1
Enable-to-Pad, L to Z
3.6
4.2
4.7
5.6
7.8
Enable-to-Pad, H to Z
3.1
3.5
4.0
4.7
6.6
3
dTLH
Delta Low to High
0.014
0.023
0.043
0.017
0.029
0.046
0.017
0.031
0.057
0.023
0.037
0.066
0.031 ns/pF
0.051 ns/pF
0.089 ns/pF
3
dTHL
Delta High to Low
3
dTHLS
Delta High to Low—low slew
Notes:
1. All –3 speed grades have been discontinued.
2. Delays based on 50 pF loading.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI – 0.9*VCCI)/ (Cload * dT[LH|HL|HLS]
where Cload is the load capacitance driven by the I/O in pF
)
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
2-52
v5.3
SX-A Family FPGAs
Package Pin Assignments
208-Pin PQFP
208
1
208-Pin
PQFP
Figure 3-1 • 208-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v5.3
3-1
SX-A Family FPGAs
208-Pin PQFP
A54SX08A A54SX16A A54SX32A A54SX72A
208-Pin PQFP
Pin
Number Function Function Function Function
Pin
A54SX08A A54SX16A A54SX32A A54SX72A
Number Function Function Function Function
1
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
3
I/O
4
NC
I/O
I/O
I/O
NC
VCCI
VCCA
I/O
5
I/O
I/O
I/O
I/O
6
NC
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
TMS
VCCI
I/O
TMS
VCCI
I/O
TMS
VCCI
I/O
TMS
VCCI
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
VCCA
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
VCCI
NC
I/O
GND
VCCA
GND
I/O
GND
VCCA
GND
I/O
GND
VCCA
GND
I/O
GND
VCCA
GND
I/O
I/O
NC
I/O
TRST, I/O
NC
TRST, I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
3-2
v5.3
SX-A Family FPGAs
208-Pin PQFP
208-Pin PQFP
A54SX08A A54SX16A A54SX32A A54SX72A
Pin
A54SX08A A54SX16A A54SX32A A54SX72A
Number Function Function Function Function
Pin
Number Function Function Function Function
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKA
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCA
GND
NC
PRB, I/O
GND
VCCA
GND
NC
PRB, I/O
GND
VCCA
GND
NC
PRB,I/O
GND
VCCA
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
NC
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
GND
VCCA
I/O
I/O
I/O
I/O
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
HCLK
VCCI
QCLKB
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
GND
VCCA
GND
NC
I/O
GND
VCCA
GND
NC
I/O
GND
VCCA
GND
NC
I/O
GND
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
I/O
I/O
I/O
I/O
v5.3
3-3
SX-A Family FPGAs
208-Pin PQFP
A54SX08A A54SX16A A54SX32A A54SX72A
208-Pin PQFP
Pin
Number Function Function Function Function
Pin
A54SX08A A54SX16A A54SX32A A54SX72A
Number Function Function Function Function
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
I/O
VCCA
GND
I/O
VCCA
GND
I/O
VCCA
GND
I/O
CLKA
CLKB
NC
CLKA
CLKB
NC
CLKA
CLKB
NC
CLKA
CLKB
NC
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
GND
VCCA
GND
PRA, I/O
I/O
GND
VCCA
GND
PRA, I/O
I/O
GND
VCCA
GND
PRA, I/O
I/O
GND
VCCA
GND
PRA, I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
NC
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
NC
VCCI
I/O
VCCI
I/O
VCCI
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
TCK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3-4
v5.3
SX-A Family FPGAs
100-Pin TQFP
100
1
100-Pin
TQFP
Figure 3-2 • 100-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v5.3
3-5
SX-A Family FPGAs
100-TQFP
A54SX08A A54SX16A
100-TQFP
A54SX32A
Function
A54SX08A
A54SX16A
Function
A54SX32A
Function
Pin Number
Function
GND
TDI, I/O
I/O
Function
GND
TDI, I/O
I/O
Pin Number
Function
GND
NC
1
GND
TDI, I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
GND
NC
GND
NC
2
3
I/O
I/O
I/O
4
I/O
I/O
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
5
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
7
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
9
VCCI
I/O
VCCI
I/O
VCCI
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
I/O
I/O
I/O
PRB, I/O
VCCA
PRB, I/O
VCCA
PRB, I/O
VCCA
3-6
v5.3
SX-A Family FPGAs
100-TQFP
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
Pin Number
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
NC
CLKA
CLKB
NC
CLKA
CLKB
NC
VCCA
GND
PRA, I/O
I/O
VCCA
GND
PRA, I/O
I/O
VCCA
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
v5.3
3-7
SX-A Family FPGAs
144-Pin TQFP
144
1
144-Pin
TQFP
Figure 3-3 • 144-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
3-8
v5.3
SX-A Family FPGAs
144-Pin TQFP
144-Pin TQFP
A54SX08A A54SX16A
A54SX08A
A54SX16A
Function
A54SX32A
Function
A54SX32A
Function
Pin Number
Function
GND
TDI, I/O
I/O
Pin Number
38
Function
Function
1
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
2
39
I/O
I/O
3
40
I/O
I/O
I/O
4
I/O
I/O
I/O
41
I/O
I/O
I/O
5
I/O
I/O
I/O
42
I/O
I/O
I/O
6
I/O
I/O
I/O
43
I/O
I/O
I/O
7
I/O
I/O
I/O
44
VCCI
I/O
VCCI
I/O
VCCI
I/O
8
I/O
I/O
I/O
45
9
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
46
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
47
I/O
I/O
I/O
48
I/O
I/O
I/O
49
I/O
I/O
I/O
I/O
I/O
I/O
50
I/O
I/O
I/O
I/O
I/O
I/O
51
I/O
I/O
I/O
I/O
I/O
I/O
52
I/O
I/O
I/O
I/O
I/O
I/O
53
I/O
I/O
I/O
I/O
I/O
I/O
54
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
55
NC
NC
NC
56
VCCA
GND
NC
VCCA
GND
NC
VCCA
GND
NC
VCCA
I/O
VCCA
I/O
VCCA
I/O
57
58
TRST, I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
59
I/O
I/O
I/O
60
HCLK
I/O
HCLK
I/O
HCLK
I/O
I/O
I/O
I/O
61
I/O
I/O
I/O
62
I/O
I/O
I/O
I/O
I/O
I/O
63
I/O
I/O
I/O
I/O
I/O
I/O
64
I/O
I/O
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
GND
VCCI
VCCA
I/O
65
I/O
I/O
I/O
66
I/O
I/O
I/O
67
I/O
I/O
I/O
68
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
69
I/O
I/O
I/O
70
I/O
I/O
I/O
I/O
I/O
I/O
71
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
72
GND
I/O
GND
I/O
GND
I/O
73
GND
I/O
GND
I/O
GND
I/O
74
v5.3
3-9
SX-A Family FPGAs
144-Pin TQFP
A54SX08A A54SX16A
144-Pin TQFP
A54SX32A
Function
A54SX08A
A54SX16A
Function
A54SX32A
Function
Pin Number
75
Function
Function
Pin Number
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
76
I/O
I/O
I/O
77
I/O
I/O
I/O
I/O
I/O
I/O
78
I/O
I/O
I/O
I/O
I/O
I/O
79
VCCA
VCCI
GND
I/O
VCCA
VCCI
GND
I/O
VCCA
VCCI
GND
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
80
81
I/O
I/O
I/O
82
I/O
I/O
I/O
83
I/O
I/O
I/O
I/O
I/O
I/O
84
I/O
I/O
I/O
I/O
I/O
I/O
85
I/O
I/O
I/O
I/O
I/O
I/O
86
I/O
I/O
I/O
I/O
I/O
I/O
87
I/O
I/O
I/O
I/O
I/O
I/O
88
I/O
I/O
I/O
I/O
I/O
I/O
89
VCCA
NC
VCCA
NC
VCCA
NC
I/O
CLKA
CLKB
NC
CLKA
CLKB
NC
CLKA
CLKB
NC
90
91
I/O
I/O
92
I/O
I/O
I/O
GND
VCCA
I/O
GND
VCCA
I/O
GND
VCCA
I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
PRA, I/O
I/O
PRA, I/O
I/O
PRA, I/O
I/O
96
I/O
I/O
I/O
97
I/O
I/O
I/O
I/O
I/O
I/O
98
VCCA
GND
I/O
VCCA
GND
I/O
VCCA
GND
I/O
I/O
I/O
I/O
99
I/O
I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
I/O
I/O
I/O
GND
VCCI
I/O
GND
VCCI
I/O
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
GND
I/O
GND
I/O
GND
I/O
3-10
v5.3
SX-A Family FPGAs
176-Pin TQFP
176
1
176-Pin
TQFP
Figure 3-4 • 176-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v5.3
3-11
SX-A Family FPGAs
176-Pin TQFP
176-Pin TQFP
176-Pin TQFP
176-Pin TQFP
Pin
Number
A54SX32A
Pin
A54SX32A
Function
Pin
Number
A54SX32A
Function
Pin
A54SX32A
Function
Function
GND
TDI, I/O
I/O
Number
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Number
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
1
I/O
I/O
73
I/O
I/O
VCCA
GND
I/O
2
74
3
I/O
75
I/O
4
I/O
I/O
76
I/O
I/O
5
I/O
I/O
77
I/O
I/O
6
I/O
I/O
78
I/O
I/O
7
I/O
I/O
79
I/O
I/O
8
I/O
GND
I/O
80
I/O
I/O
9
I/O
81
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TMS
VCCI
I/O
I/O
82
VCCI
I/O
I/O
I/O
83
I/O
I/O
84
I/O
I/O
I/O
I/O
85
I/O
I/O
I/O
I/O
86
I/O
VCCA
GND
VCCI
I/O
I/O
I/O
87
TDO, I/O
I/O
I/O
VCCI
I/O
88
I/O
89
GND
I/O
I/O
I/O
90
I/O
I/O
I/O
91
I/O
I/O
I/O
I/O
92
I/O
I/O
GND
VCCA
GND
I/O
I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
I/O
I/O
TRST, I/O
I/O
I/O
97
I/O
GND
I/O
I/O
98
VCCA
VCCI
I/O
I/O
I/O
99
I/O
I/O
PRB, I/O
GND
VCCA
NC
I/O
100
101
102
103
104
105
106
107
108
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCA
I/O
I/O
VCCI
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
3-12
v5.3
SX-A Family FPGAs
176-Pin TQFP
Pin
A54SX32A
Function
Number
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
NC
GND
VCCA
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
v5.3
3-13
SX-A Family FPGAs
329-Pin PBGA
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Figure 3-5 • 329-Pin PBGA (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
3-14
v5.3
SX-A Family FPGAs
329-Pin PBGA
329-Pin PBGA
329-Pin PBGA
329-Pin PBGA
Pin
Number
A54SX32A
Function
Pin
A54SX32A
Function
Pin
A54SX32A
Function
Pin
A54SX32A
Function
Number
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB1
Number
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
B1
Number
B20
B21
B22
B23
C1
A1
GND
GND
VCCI
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2
A3
I/O
I/O
GND
VCCI
NC
A4
I/O
VCCI
I/O
A5
I/O
A6
I/O
TDO, I/O
VCCI
I/O
I/O
C2
TDI, I/O
GND
I/O
A7
VCCI
NC
I/O
I/O
C3
A8
I/O
C4
A9
VCCI
I/O
I/O
C5
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
I/O
NC
I/O
C6
I/O
I/O
AB2
GND
I/O
C7
I/O
I/O
AB3
I/O
C8
I/O
CLKB
I/O
AB4
I/O
I/O
C9
I/O
AB5
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
D1
I/O
I/O
AB6
I/O
I/O
I/O
I/O
AB7
I/O
NC
VCCI
GND
VCCI
GND
I/O
I/O
I/O
AB8
I/O
I/O
I/O
AB9
I/O
I/O
I/O
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
I/O
I/O
I/O
PRB, I/O
I/O
B2
I/O
NC
VCCI
GND
VCCI
I/O
B3
I/O
HCLK
I/O
B4
I/O
I/O
B5
I/O
I/O
I/O
B6
I/O
I/O
I/O
B7
I/O
VCCI
GND
NC
GND
I/O
I/O
B8
I/O
I/O
B9
I/O
I/O
I/O
B10
I/O
I/O
I/O
I/O
B11
I/O
D2
I/O
I/O
I/O
B12
PRA, I/O
CLKA
I/O
D3
I/O
I/O
GND
I/O
B13
D4
TCK, I/O
I/O
I/O
B14
D5
I/O
GND
VCCI
NC
B15
I/O
D6
I/O
I/O
AC2
B16
I/O
D7
I/O
I/O
AC3
B17
I/O
D8
I/O
I/O
AC4
I/O
B18
I/O
D9
I/O
I/O
AC5
I/O
B19
I/O
D10
I/O
v5.3
3-15
SX-A Family FPGAs
329-Pin PBGA
329-Pin PBGA
329-Pin PBGA
329-Pin PBGA
Pin
Number
A54SX32A
Pin
Number
A54SX32A
Function
Pin
A54SX32A
Function
Pin
A54SX32A
Function
Function
VCCA
NC
I/O
Number
L14
L20
L21
L22
L23
M1
Number
P12
P13
P14
P20
P21
P22
P23
R1
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
E1
H1
I/O
I/O
GND
NC
GND
GND
GND
I/O
H2
H3
I/O
I/O
I/O
H4
I/O
I/O
I/O
H20
H21
H22
H23
J1
VCCA
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
M2
I/O
I/O
I/O
I/O
M3
I/O
I/O
I/O
NC
M4
VCCA
GND
GND
GND
GND
GND
VCCA
I/O
R2
I/O
I/O
J2
I/O
M10
M11
M12
M13
M14
M20
M21
M22
M23
N1
R3
I/O
I/O
J3
I/O
R4
I/O
I/O
J4
I/O
R20
R21
R22
R23
T1
I/O
I/O
J20
J21
J22
J23
K1
I/O
I/O
VCCI
I/O
I/O
I/O
E2
I/O
I/O
E3
I/O
I/O
I/O
E4
I/O
I/O
I/O
T2
I/O
E20
E21
E22
E23
F1
I/O
K2
I/O
VCCI
I/O
T3
I/O
I/O
K3
I/O
T4
I/O
I/O
K4
I/O
N2
TRST, I/O
I/O
T20
T21
T22
T23
U1
I/O
I/O
K10
K11
K12
K13
K14
K20
K21
K22
K23
L1
GND
GND
GND
GND
GND
I/O
N3
I/O
I/O
N4
I/O
I/O
F2
TMS
I/O
N10
N11
N12
N13
N14
N20
N21
N22
N23
P1
GND
GND
GND
GND
GND
NC
I/O
F3
I/O
F4
I/O
U2
I/O
F20
F21
F22
F23
G1
I/O
U3
VCCA
I/O
I/O
I/O
U4
I/O
I/O
U20
U21
U22
U23
V1
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
G2
I/O
L2
I/O
I/O
I/O
G3
I/O
L3
I/O
I/O
VCCI
I/O
G4
I/O
L4
NC
P2
I/O
V2
G20
G21
G22
G23
I/O
L10
L11
L12
L13
GND
GND
GND
GND
P3
I/O
V3
I/O
I/O
P4
I/O
V4
I/O
I/O
P10
P11
GND
GND
V20
V21
I/O
GND
I/O
3-16
v5.3
SX-A Family FPGAs
329-Pin PBGA
Pin
A54SX32A
Function
Number
V22
V23
W1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
NC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
W2
W3
W4
W20
W21
W22
W23
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
v5.3
3-17
SX-A Family FPGAs
144-Pin FBGA
4
1
2
3
5
6
7
8
10 11 12
9
A
B
C
D
E
F
G
H
J
K
L
M
Figure 3-6 • 144-Pin FBGA (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
3-18
v5.3
SX-A Family FPGAs
144-Pin FBGA
144-Pin FBGA
A54SX08A A54SX16A
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
A54SX32A
Function
Pin Number
A1
Pin Number
D1
Function
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
TDI, I/O
I/O
A2
I/O
D2
VCCI
TDI, I/O
I/O
VCCI
TDI, I/O
I/O
A3
I/O
I/O
I/O
D3
A4
I/O
I/O
I/O
D4
A5
VCCA
GND
CLKA
I/O
VCCA
GND
CLKA
I/O
VCCA
GND
CLKA
I/O
D5
I/O
I/O
I/O
A6
D6
I/O
I/O
I/O
A7
D7
I/O
I/O
I/O
A8
D8
I/O
I/O
I/O
A9
I/O
I/O
I/O
D9
I/O
I/O
I/O
A10
A11
A12
B1
I/O
I/O
I/O
D10
D11
D12
E1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B2
GND
I/O
GND
I/O
GND
I/O
E2
I/O
I/O
I/O
B3
E3
I/O
I/O
I/O
B4
I/O
I/O
I/O
E4
I/O
I/O
I/O
B5
I/O
I/O
I/O
E5
TMS
VCCI
VCCI
VCCI
VCCA
I/O
TMS
VCCI
VCCI
VCCI
VCCA
I/O
TMS
VCCI
VCCI
VCCI
VCCA
I/O
B6
I/O
I/O
I/O
E6
B7
CLKB
I/O
CLKB
I/O
CLKB
I/O
E7
B8
E8
B9
I/O
I/O
I/O
E9
B10
B11
B12
C1
I/O
I/O
I/O
E10
E11
E12
F1
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C2
I/O
I/O
I/O
F2
I/O
I/O
I/O
C3
TCK, I/O
I/O
TCK, I/O
I/O
TCK, I/O
I/O
F3
NC
NC
NC
C4
F4
I/O
I/O
I/O
C5
I/O
I/O
I/O
F5
GND
GND
GND
VCCI
I/O
GND
GND
GND
VCCI
I/O
GND
GND
GND
VCCI
I/O
C6
PRA, I/O
I/O
PRA, I/O
I/O
PRA, I/O
I/O
F6
C7
F7
C8
I/O
I/O
I/O
F8
C9
I/O
I/O
I/O
F9
C10
C11
C12
I/O
I/O
I/O
F10
F11
F12
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
v5.3
3-19
SX-A Family FPGAs
144-Pin FBGA
A54SX08A A54SX16A
144-Pin FBGA
A54SX32A
Function
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
Pin Number
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
Function
Function
Pin Number
K1
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
K2
I/O
K3
I/O
I/O
I/O
I/O
I/O
I/O
K4
I/O
I/O
I/O
GND
GND
GND
VCCI
I/O
GND
GND
GND
VCCI
I/O
GND
GND
GND
VCCI
I/O
K5
I/O
I/O
I/O
K6
I/O
I/O
I/O
K7
GND
I/O
GND
I/O
GND
I/O
K8
K9
I/O
I/O
I/O
I/O
I/O
I/O
K10
K11
K12
L1
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
GND
I/O
GND
I/O
GND
I/O
H2
L2
H3
I/O
I/O
I/O
L3
I/O
I/O
I/O
H4
I/O
I/O
I/O
L4
I/O
I/O
I/O
H5
VCCA
VCCA
VCCI
VCCI
VCCA
I/O
VCCA
VCCA
VCCI
VCCI
VCCA
I/O
VCCA
VCCA
VCCI
VCCI
VCCA
I/O
L5
I/O
I/O
I/O
H6
L6
I/O
I/O
I/O
H7
L7
HCLK
I/O
HCLK
I/O
HCLK
I/O
H8
L8
H9
L9
I/O
I/O
I/O
H10
H11
H12
J1
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J2
I/O
I/O
I/O
I/O
I/O
I/O
J3
I/O
I/O
I/O
I/O
I/O
I/O
J4
I/O
I/O
I/O
I/O
I/O
I/O
J5
I/O
I/O
I/O
I/O
I/O
I/O
J6
PRB, I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
J7
VCCA
I/O
VCCA
I/O
VCCA
I/O
J8
I/O
I/O
I/O
J9
I/O
I/O
I/O
I/O
I/O
I/O
J10
J11
J12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
VCCA
VCCA
VCCA
3-20
v5.3
SX-A Family FPGAs
256-Pin FBGA
1
2
3
4
6
7
8
9 10 11 12
13 14
5
15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Figure 3-7 • 256-Pin FBGA (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v5.3
3-21
SX-A Family FPGAs
256-Pin FBGA
A54SX16A A54SX32A
256-Pin FBGA
A54SX72A
Function
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
Pin Number
A1
Function
GND
TCK, I/O
I/O
Function
GND
TCK, I/O
I/O
Pin Number
C6
GND
TCK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2
C7
I/O
A3
C8
I/O
I/O
I/O
A4
I/O
I/O
I/O
C9
CLKA
I/O
CLKA
I/O
CLKA
I/O
A5
I/O
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
D1
A6
I/O
I/O
I/O
I/O
I/O
I/O
A7
I/O
I/O
I/O
I/O
I/O
I/O
A8
I/O
I/O
I/O
I/O
I/O
I/O
A9
CLKB
I/O
CLKB
I/O
CLKB
I/O
I/O
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D2
I/O
I/O
I/O
I/O
I/O
I/O
D3
I/O
I/O
I/O
GND
GND
I/O
GND
GND
I/O
GND
GND
I/O
D4
I/O
I/O
I/O
D5
I/O
I/O
I/O
D6
I/O
I/O
I/O
B2
GND
I/O
GND
I/O
GND
I/O
D7
I/O
I/O
I/O
B3
D8
PRA, I/O
I/O
PRA, I/O
I/O
PRA, I/O
QCLKD
I/O
B4
I/O
I/O
I/O
D9
B5
I/O
I/O
I/O
D10
D11
D12
D13
D14
D15
D16
E1
I/O
I/O
B6
NC
I/O
I/O
NC
I/O
I/O
I/O
B7
I/O
I/O
I/O
I/O
I/O
B8
VCCA
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
B9
I/O
I/O
I/O
B10
B11
B12
B13
B14
B15
B16
C1
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
E2
I/O
I/O
I/O
I/O
I/O
I/O
E3
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
E4
I/O
I/O
I/O
E5
I/O
I/O
I/O
I/O
I/O
I/O
E6
I/O
I/O
I/O
C2
TDI, I/O
GND
I/O
TDI, I/O
GND
I/O
TDI, I/O
GND
I/O
E7
I/O
I/O
I/O
QCLKC
I/O
C3
E8
I/O
C4
E9
I/O
I/O
I/O
C5
NC
I/O
I/O
E10
I/O
I/O
I/O
3-22
v5.3
SX-A Family FPGAs
256-Pin FBGA
256-Pin FBGA
A54SX16A A54SX32A
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
A54SX72A
Function
Pin Number
E11
E12
E13
E14
E15
E16
F1
Pin Number
G16
H1
Function
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
H2
I/O
I/O
I/O
I/O
I/O
I/O
H3
VCCA
TRST, I/O
I/O
VCCA
TRST, I/O
I/O
VCCA
TRST, I/O
I/O
I/O
I/O
I/O
H4
I/O
I/O
I/O
H5
I/O
I/O
I/O
H6
VCCI
GND
GND
GND
GND
VCCI
I/O
VCCI
GND
GND
GND
GND
VCCI
I/O
VCCI
GND
GND
GND
GND
VCCI
I/O
F2
I/O
I/O
I/O
H7
F3
I/O
I/O
I/O
H8
F4
TMS
I/O
TMS
I/O
TMS
I/O
H9
F5
H10
H11
H12
H13
H14
H15
H16
J1
F6
I/O
I/O
I/O
F7
VCCI
VCCI
VCCI
VCCI
I/O
VCCI
VCCI
VCCI
VCCI
I/O
VCCI
VCCI
VCCI
VCCI
I/O
F8
I/O
I/O
I/O
F9
I/O
I/O
I/O
F10
F11
F12
F13
F14
F15
F16
G1
I/O
I/O
I/O
NC
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
NC
I/O
I/O
J2
NC
I/O
I/O
I/O
I/O
I/O
J3
NC
I/O
I/O
I/O
I/O
I/O
J4
I/O
I/O
I/O
I/O
I/O
I/O
J5
I/O
I/O
I/O
NC
I/O
I/O
J6
VCCI
GND
GND
GND
GND
VCCI
I/O
VCCI
GND
GND
GND
GND
VCCI
I/O
VCCI
GND
GND
GND
GND
VCCI
I/O
G2
I/O
I/O
I/O
J7
G3
NC
I/O
I/O
J8
G4
I/O
I/O
I/O
J9
G5
I/O
I/O
I/O
J10
J11
J12
J13
J14
J15
J16
K1
G6
VCCI
GND
GND
GND
GND
VCCI
I/O
VCCI
GND
GND
GND
GND
VCCI
I/O
VCCI
GND
GND
GND
GND
VCCI
I/O
G7
G8
I/O
I/O
I/O
G9
I/O
I/O
I/O
G10
G11
G12
G13
G14
G15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
GND
I/O
GND
I/O
K2
I/O
I/O
I/O
K3
NC
I/O
I/O
VCCA
VCCA
VCCA
K4
VCCA
VCCA
VCCA
v5.3
3-23
SX-A Family FPGAs
256-Pin FBGA
A54SX16A A54SX32A
256-Pin FBGA
A54SX72A
Function
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
Pin Number
K5
Function
Function
Pin Number
M10
M11
M12
M13
M14
M15
M16
N1
I/O
I/O
I/O
VCCI
GND
GND
GND
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
K6
VCCI
GND
GND
GND
GND
VCCI
I/O
VCCI
GND
GND
GND
GND
VCCI
I/O
I/O
K7
NC
I/O
K8
K9
NC
I/O
K10
K11
K12
K13
K14
K15
K16
L1
I/O
I/O
I/O
I/O
I/O
N2
I/O
I/O
I/O
I/O
N3
I/O
NC
I/O
I/O
N4
I/O
I/O
I/O
I/O
N5
I/O
I/O
I/O
I/O
N6
I/O
L2
I/O
I/O
I/O
N7
I/O
L3
I/O
I/O
I/O
N8
I/O
L4
I/O
I/O
I/O
N9
I/O
L5
I/O
I/O
I/O
N10
N11
N12
N13
N14
N15
N16
P1
I/O
L6
I/O
I/O
I/O
I/O
L7
VCCI
VCCI
VCCI
VCCI
I/O
VCCI
VCCI
VCCI
VCCI
I/O
VCCI
VCCI
VCCI
VCCI
I/O
I/O
L8
I/O
L9
I/O
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P2
GND
I/O
I/O
I/O
I/O
P3
I/O
I/O
I/O
P4
I/O
NC
I/O
I/O
P5
NC
I/O
I/O
I/O
I/O
P6
I/O
I/O
I/O
P7
I/O
I/O
I/O
I/O
P8
I/O
I/O
I/O
I/O
P9
I/O
I/O
I/O
I/O
P10
P11
P12
P13
P14
NC
I/O
I/O
I/O
I/O
I/O
I/O
QCLKA
PRB, I/O
I/O
I/O
PRB, I/O
I/O
PRB, I/O
I/O
VCCA
I/O
3-24
v5.3
SX-A Family FPGAs
256-Pin FBGA
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
Pin Number
P15
P16
R1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R2
GND
I/O
GND
I/O
GND
I/O
R3
R4
NC
I/O
I/O
R5
I/O
I/O
I/O
R6
I/O
I/O
I/O
R7
I/O
I/O
I/O
R8
I/O
I/O
I/O
R9
HCLK
I/O
HCLK
I/O
HCLK
QCLKB
I/O
R10
R11
R12
R13
R14
R15
R16
T1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
I/O
GND
GND
GND
I/O
GND
GND
GND
I/O
T2
T3
I/O
I/O
I/O
T4
NC
I/O
I/O
T5
I/O
I/O
I/O
T6
I/O
I/O
I/O
T7
I/O
I/O
I/O
T8
I/O
I/O
I/O
T9
VCCA
I/O
VCCA
I/O
VCCA
I/O
T10
T11
T12
T13
T14
T15
T16
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
GND
TDO, I/O
GND
TDO, I/O
GND
v5.3
3-25
SX-A Family FPGAs
484-Pin FBGA
1
3 4 5 6 7 8 9 10 11121314 15161718 19 20212223 242526
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Figure 3-8 • 484-Pin FBGA (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
3-26
v5.3
SX-A Family FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
A54SX32A A54SX72A
Pin
A54SX32A A54SX72A
Pin
A54SX32A A54SX72A
Pin
Number
Function
NC*
NC*
NC*
NC*
NC*
I/O
Function
NC
NC
I/O
Number
Function
NC*
NC*
VCCI
I/O
Function
Number
Function
Function
A1
A2
AA26
AB1
I/O
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
I/O
I/O
NC
I/O
I/O
A3
AB2
VCCI
I/O
I/O
I/O
A4
I/O
AB3
I/O
QCLKA
I/O
A5
I/O
AB4
I/O
I/O
I/O
A6
I/O
AB5
NC*
I/O
I/O
I/O
I/O
A7
I/O
I/O
AB6
I/O
I/O
I/O
A8
I/O
I/O
AB7
I/O
I/O
I/O
I/O
A9
I/O
I/O
AB8
I/O
I/O
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
AA1
AA2
AA3
AA4
AA5
AA22
AA23
AA24
AA25
I/O
I/O
AB9
I/O
I/O
I/O
I/O
NC*
NC*
I/O
I/O
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
PRB, I/O
VCCA
I/O
PRB, I/O
VCCA
I/O
NC*
NC*
NC*
I/O
NC
I/O
I/O
I/O
NC*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC*
NC*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD2
I/O
I/O
NC*
NC*
NC*
NC*
NC*
NC*
NC*
NC*
VCCA
I/O
I/O
TDO, I/O
GND
NC*
I/O
TDO, I/O
GND
I/O
AD3
GND
I/O
GND
I/O
I/O
AD4
I/O
AD5
I/O
I/O
I/O
I/O
AD6
I/O
I/O
NC
NC
I/O
I/O
I/O
AD7
I/O
I/O
NC*
NC*
I/O
I/O
AD8
I/O
I/O
I/O
AD9
VCCI
I/O
VCCI
I/O
I/O
I/O
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
VCCA
I/O
AC2
I/O
I/O
I/O
I/O
AC3
I/O
I/O
I/O
I/O
I/O
I/O
AC4
NC*
VCCI
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
AC5
VCCI
I/O
I/O
I/O
AC6
I/O
I/O
I/O
I/O
AC7
VCCI
I/O
VCCI
I/O
I/O
I/O
NC*
I/O
AC8
VCCI
VCCI
Note: *These pins must be left floating on the A54SX32A device.
v5.3
3-27
SX-A Family FPGAs
484-Pin FBGA
A54SX32A A54SX72A
484-Pin FBGA
484-Pin FBGA
Pin
Pin
A54SX32A A54SX72A
Pin
A54SX32A A54SX72A
Number
Function
Function
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
Number
Function
NC*
NC*
NC
Function
NC
NC
I/O
Number
Function
Function
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
I/O
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
B1
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
I/O
I/O
I/O
NC*
NC*
VCCI
CLKA
NC*
NC*
I/O
I/O
I/O
I/O
I/O
NC*
NC*
NC*
I/O
I/O
VCCI
CLKA
I/O
I/O
I/O
VCCI
NC*
NC*
NC*
NC*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
AE2
NC*
NC*
HCLK
I/O
I/O
I/O
I/O
AE3
NC*
NC*
NC*
NC*
I/O
NC
HCLK
QCLKB
I/O
NC*
NC*
NC*
NC*
I/O
I/O
AE4
I/O
AE5
I/O
AE6
NC*
NC*
I/O
I/O
AE7
I/O
I/O
AE8
I/O
I/O
NC*
NC*
NC*
NC*
NC*
I/O
NC
AE9
I/O
I/O
I/O
I/O
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
I/O
I/O
I/O
C2
I/O
NC*
I/O
NC*
NC*
NC*
NC*
NC*
NC*
NC*
NC*
NC*
NC*
NC*
NC*
I/O
I/O
C3
I/O
I/O
C4
I/O
I/O
I/O
C5
I/O
I/O
I/O
C6
VCCI
I/O
VCCI
I/O
NC*
NC*
I/O
I/O
C7
NC
NC
NC
NC
I/O
C8
I/O
I/O
C9
VCCI
I/O
VCCI
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
I/O
B2
I/O
I/O
I/O
B3
I/O
I/O
NC*
NC*
NC*
NC*
NC*
NC*
B4
I/O
PRA, I/O
I/O
PRA, I/O
I/O
B5
I/O
B6
I/O
I/O
QCLKD
I/O
B7
I/O
I/O
I/O
B8
I/O
I/O
I/O
I/O
B9
I/O
I/O
I/O
I/O
Note: *These pins must be left floating on the A54SX32A device.
3-28
v5.3
SX-A Family FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
A54SX32A A54SX72A
Pin
A54SX32A A54SX72A
Pin
A54SX32A A54SX72A
Pin
Number
Function
Function
Number
Function
NC*
I/O
Function
Number
Function
NC*
NC*
NC*
I/O
Function
C19
C20
C21
C22
C23
C24
C25
C26
D1
I/O
I/O
E2
E3
I/O
G1
G2
G3
G4
G5
G22
G23
G24
G25
G26
H1
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
E4
I/O
I/O
I/O
I/O
I/O
E5
GND
TDI, IO
I/O
GND
TDI, IO
I/O
I/O
I/O
I/O
E6
I/O
I/O
I/O
I/O
E7
I/O
I/O
NC*
NC*
NC*
TMS
I/O
I/O
E8
I/O
I/O
VCCA
I/O
VCCA
I/O
I/O
E9
I/O
I/O
I/O
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
I/O
I/O
NC*
NC*
NC*
NC*
I/O
I/O
D2
TMS
I/O
I/O
I/O
I/O
D3
I/O
I/O
I/O
D4
VCCI
NC*
TCK, I/O
I/O
VCCI
I/O
VCCA
CLKB
I/O
VCCA
CLKB
I/O
H2
I/O
D5
H3
I/O
D6
TCK, I/O
I/O
H4
I/O
I/O
D7
I/O
I/O
H5
I/O
I/O
D8
I/O
I/O
I/O
I/O
H22
H23
H24
H25
H26
J1
I/O
I/O
D9
I/O
I/O
I/O
I/O
I/O
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC*
NC*
NC*
NC*
I/O
I/O
I/O
QCLKC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J2
I/O
I/O
I/O
I/O
I/O
J3
I/O
I/O
I/O
VCCI
GND
VCCI
NC*
NC*
I/O
VCCI
GND
VCCI
I/O
J4
I/O
I/O
I/O
I/O
J5
I/O
I/O
I/O
I/O
J22
J23
J24
J25
J26
K1
I/O
I/O
I/O
I/O
F2
I/O
I/O
I/O
I/O
F3
I/O
I/O
I/O
VCCI
GND
I/O
VCCI
GND
I/O
F4
I/O
VCCI
NC*
I/O
VCCI
I/O
F5
I/O
I/O
F22
F23
F24
F25
F26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K2
VCCI
I/O
VCCI
I/O
NC*
NC*
NC*
I/O
I/O
I/O
K3
I/O
I/O
I/O
K4
I/O
I/O
I/O
NC*
I/O
K5
VCCA
VCCA
Note: *These pins must be left floating on the A54SX32A device.
v5.3
3-29
SX-A Family FPGAs
484-Pin FBGA
A54SX32A A54SX72A
484-Pin FBGA
484-Pin FBGA
Pin
Pin
A54SX32A A54SX72A
Pin
A54SX32A A54SX72A
Number
Function
GND
GND
GND
GND
GND
GND
GND
GND
I/O
Function
GND
GND
GND
GND
GND
GND
GND
GND
I/O
Number
Function
Function
Number
Function
Function
K10
K11
K12
K13
K14
K15
K16
K17
K22
K23
K24
K25
K26
L1
M5
M10
M11
M12
M13
M14
M15
M16
M17
M22
M23
M24
M25
M26
N1
I/O
I/O
P4
I/O
I/O
GND
GND
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
GND
GND
I/O
P5
VCCA
GND
GND
GND
GND
GND
GND
GND
GND
I/O
VCCA
GND
GND
GND
GND
GND
GND
GND
GND
I/O
P10
P11
P12
P13
P14
P15
P16
P17
P22
P23
P24
P25
P26
R1
I/O
I/O
NC*
NC*
NC*
NC*
NC*
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC*
NC*
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
L2
I/O
I/O
I/O
I/O
L3
I/O
N2
VCCI
I/O
VCCI
I/O
NC*
NC*
I/O
I/O
L4
I/O
I/O
N3
R2
I/O
L5
I/O
I/O
N4
I/O
I/O
R3
I/O
L10
L11
L12
L13
L14
L15
L16
L17
L22
L23
L24
L25
L26
M1
M2
M3
M4
GND
GND
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
GND
GND
I/O
N5
I/O
I/O
R4
I/O
I/O
N10
N11
N12
N13
N14
N15
N16
N17
N22
N23
N24
N25
N26
P1
GND
GND
GND
GND
GND
GND
GND
GND
VCCA
I/O
GND
GND
GND
GND
GND
GND
GND
GND
VCCA
I/O
R5
TRST, I/O
GND
GND
GND
GND
GND
GND
GND
GND
I/O
TRST, I/O
GND
GND
GND
GND
GND
GND
GND
GND
I/O
R10
R11
R12
R13
R14
R15
R16
R17
R22
R23
R24
R25
R26
T1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC*
I/O
NC
NC*
NC*
NC*
I/O
NC
NC*
NC*
NC*
NC*
I/O
I/O
I/O
I/O
I/O
I/O
P2
I/O
I/O
I/O
I/O
P3
I/O
T2
I/O
Note: *These pins must be left floating on the A54SX32A device.
3-30
v5.3
SX-A Family FPGAs
484-Pin FBGA
484-Pin FBGA
Pin
A54SX32A A54SX72A
Pin
A54SX32A A54SX72A
Number
Function
Function
Number
Function
NC*
I/O
Function
T3
I/O
I/O
V2
V3
I/O
T4
I/O
I/O
I/O
T5
I/O
I/O
V4
I/O
I/O
T10
T11
T12
T13
T14
T15
T16
T17
T22
T23
T24
T25
T26
U1
GND
GND
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
GND
GND
I/O
V5
I/O
I/O
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W22
W23
W24
W25
W26
Y1
VCCA
I/O
VCCA
I/O
I/O
I/O
NC*
NC*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC*
NC*
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
I/O
U2
VCCI
I/O
VCCI
I/O
NC*
NC*
NC*
NC*
I/O
I/O
U3
I/O
U4
I/O
I/O
I/O
U5
I/O
I/O
Y2
I/O
U10
U11
U12
U13
U14
U15
U16
U17
U22
U23
U24
U25
U26
V1
GND
GND
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
GND
GND
I/O
Y3
I/O
Y4
I/O
I/O
Y5
NC*
I/O
I/O
Y22
Y23
Y24
Y25
Y26
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
NC*
I/O
Note: *These pins must be left floating on the A54SX32A device.
v5.3
3-31
SX-A Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v5.3)
Page
N/A
2-14
ii
v5.2
–3 speed grades have been discontinued.
(June 2006)
The "SX-A Timing Model" was updated with –2 data.
RoHS information was added to the "Ordering Information".
The "Programming" section was updated.
v5.1
February 2005
v5.0
1-13
Revised Table 1 and the timing data to reflect the phase out of the –3 speed grade for the
A54SX08A device.
i
The "Thermal Characteristics" section was updated.
The "176-Pin TQFP" was updated to add pins 81 to 90.
The "484-Pin FBGA" was updated to add pins R4 to Y26
The "Temperature Grade Offering" is new.
The "Speed Grade and Temperature Grade Matrix" is new.
"SX-A Family Architecture" was updated.
"Clock Resources" was updated.
"User Security" was updated.
2-11
3-11
3-26
1-iii
1-iii
1-1
v4.0
1-5
1-7
"Power-Up/Down and Hot Swapping" was updated.
"Dedicated Mode" is new
1-7
1-9
Table 1-5 is new.
1-9
"JTAG Instructions" is new
1-10
1-12
1-13
1-13
1-15
2-1
"Design Considerations" was updated.
The "Programming" section is new.
"Design Environment" was updated.
"Pin Description" was updated.
Table 2-1 was updated.
Table 2-2 was updated.
2-1
Table 2-3 is new.
2-1
Table 2-4 is new.
2-1
Table 2-5 was updated.
2-2
Table 2-6 was updated.
2-2
"Power Dissipation" is new.
2-8
Table 2-11 was updated.
2-9
v5.3
4-1
SX-A Family FPGAs
Previous Version Changes in Current Version (v5.3)
Page
2-11
2-14
2-14
2-17
2-17
v4.0
Table 2-12 was updated.
(continued)
The was updated.
The "Sample Path Calculations" were updated.
Table 2-13 was updated.
Table 2-13 was updated.
All timing tables were updated.
2-18 to
2-52
v3.0
The "Actel Secure Programming Technology with FuseLock™ Prevents Reverse Engineering and 1-i
Design Theft" section was updated.
The "Ordering Information" section was updated.
1-ii
The "Temperature Grade Offering" section was updated.
The Figure 1-1 • SX-A Family Interconnect Elements was updated.
The “"Clock Resources" section“was updated
1-iii
1-1
1-5
The Table 1-1 • SX-A Clock Resources is new.
1-5
The "User Security" section is new.
1-7
The "I/O Modules" section was updated.
1-7
The Table 1-2 • I/O Features was updated.
1-8
The Table 1-3 • I/O Characteristics for All I/O Configurations is new.
The Table 1-4 • Power-Up Time at which I/Os Become Active is new
The Figure 1-12 • Device Selection Wizard is new.
1-8
1-8
1-9
The "Boundary-Scan Pin Configurations and Functions" section is new.
The Table 1-9 • Device Configuration Options for Probe Capability (TRST Pin Reserved) is new.
The "SX-A Probe Circuit Control Pins" section was updated.
The "Design Considerations" section was updated.
1-9
1-11
1-12
1-12
1-12
1-13
1-11
1-12
1-12
1-12
1-13
1-23
1-15
1-13
1-8
The Figure 1-13 • Probe Setup was updated.
The Design Environment was updated.
The Figure 1-13 • Design Flow is new.
The "Absolute Maximum Ratings*" section was updated.
The "Recommended Operating Conditions" section was updated.
The "Electrical Specifications" section was updated.
The "2.5V LVCMOS2 Electrical Specifications" section was updated.
The "SX-A Timing Model" and "Sample Path Calculations" equations were updated.
The "Pin Description" section was updated.
v2.0.1
The "Design Environment" section has been updated.
The "I/O Modules" section, and Table 1-2 • I/O Features have been updated.
The "SX-A Timing Model" section and the "Timing Characteristics" section have new timing 1-23
numbers.
4-2
v5.3
SX-A Family FPGAs
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
International Traffic in Arms Regulations (ITAR) and Export
Administration Regulations (EAR)
The products described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR) or the
Export Administration Regulations (EAR). They may require an approved export license prior to their export. An export
can include a release or disclosure to a foreign national inside or outside the United States.
v5.3
4-3
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Hong Kong
Actel Japan
2061 Stierlin Court
Mountain View, CA
94043-4655 USA
River Court, Meadows Business Park
Station Approach, Blackwater
Camberley, Surrey GU17 9AB
United Kingdom
Suite 2114, Two Pacific Place
88 Queensway, Admiralty
Hong Kong
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Phone 650.318.4200
Fax 650.318.4600
Phone +852 2185 6460
Fax +852 2185 6488
www.actel.com.cn
Phone +81.03.3445.7671
Fax +81.03.3445.7668
www.jp.actel.com
Phone +44 (0) 1276 609 300
Fax +44 (0) 1276 607 540
5172147-10/2.07
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