APA150-1FGG256 [ACTEL]
Field Programmable Gate Array, 150000 Gates, CMOS, PBGA256, FBGA-256;
| 型号： | APA150-1FGG256 |
| 厂家： | 
Actel Corporation |
| 描述： | Field Programmable Gate Array, 150000 Gates, CMOS, PBGA256, FBGA-256 栅 |
| 文件： | 总120页 (文件大小：2581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advanced v0.6
PLUS
™
ProASIC Family Flash FPGAs
I/O
Features and Benefits
High Capacity
• Schmitt Trigger option on Every Input
• 150,000 to 1 million System Gates
• 36k to 198 kbits of Two-Port SRAM
• 106 to 712 User I/Os
• Mixed 2.5V/3.3V Support with Individually-Selectable
Voltage and Slew Rate
• Bidirectional Global I/Os
• Compliance with PCI Specification Revision 2.2
• Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
• Pin Compatible Packages across ProASICPLUS Family
Performance
• 3.3V, 32-bit PCI (up to 50 MHz)
• Internal System Performance up to 350 MHz
• External System Performance up to 150 MHz
Reprogrammable Flash Technology
• 0.22µ 4LM Flash-based CMOS Process
Unique Clock Conditioning Circuitry
• Two Integrated PLLs (1.5 to 240 MHz Input and Output
Ranges)
• Live at Power Up, Single-Chip Solution
• PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
• No Configuration Device Required
• Internal and/or External Dynamic PLL Configuration
• Two LVPECL Differential Pairs for Clock or Data Inputs
• Retains Programmed Design During Power-Down/
Power-Up Cycles
Secure Programming
Standard FPGA and ASIC Design Flow
• Flexibility with Choice of Industry-Standard Front-End
Tools
• The Industry’s Most Effective Security Key Prevents Read
Back of Programming Bit Stream
Low Power
• Efficient Design through Front-End Timing and Gate
Optimization
• Low Impedance Flash Switches
• Segmented Hierarchical Routing Structure
ISP Support
• In-System Programming (ISP) via JTAG Port
• Small, Efficient, Configurable (Combinatorial or
Sequential) Logic Cells
SRAMs and FIFOs
High Performance Routing Hierarchy
• Ultra Fast Local and Long Line Network
• High Speed Very Long Line Network
• High Performance, Low Skew, Splitable Global Network
• 100% Routability and Utilization
ProASICPLUS Product Profile
• Netlist Generation Ensures Optimal Usage of Embedded
Memory Blocks
• Synchronous and Asynchronous Operation of 24 RAM and
FIFO Configurations (Up to 150 MHz)
Device
APA150
APA300
APA450
APA600
APA750
APA1000
Maximum System Gates
Maximum Registers
Embedded RAM Bits
Embedded RAM Blocks (256 X 9)
LVPECL
150,000
6,144
36k
16
300,000
8,192
72k
32
450,000
12,288
108k
48
600,000
21,504
126k
56
750,000
32,768
144k
64
1,000,000
56,320
198k
88
2
2
2
2
2
2
PLL
2
2
2
2
2
2
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG
4
32
242
Yes
Yes
4
32
304
Yes
Yes
4
48
356
Yes
Yes
4
56
456
Yes
Yes
4
64
642
Yes
Yes
4
88
712
Yes
Yes
PCI
Package (by pin count)
PQFP
PBGA
208
456
208
456
208
456
208
456
208
456
208
456
FBGA
144, 256
144, 256
144, 256
256, 676
676, 896
896, 1152
April 2002
1
© 2002 Actel Corporation
ProASICPLUS Family Flash FPGAs
General Description
frequency dividers which allow the incoming clock signal to
be divided by a wide range of factors from 1 to 64. The clock
conditioning circuit also delays or advances the incoming
reference clock up to 4ns (in increments of 0.25ns). The
PLL can be configured internally or externally during
operation without redesigning or reprogramming the part.
In addition to the PLL, there are two LVPECL differential
input pairs to accommodate high speed clock and data
inputs.
The ProASICPLUS family of devices offers enhanced
performance over Actel’s ProASIC family. It combines the
advantages of ASICs with the benefits of programmable
devices through nonvolatile Flash technology. This enables
engineers to create high-density systems using existing ASIC
or FPGA design flows and tools. In addition, the
ProASICPLUS family offers a unique clock conditioning
circuit based on two on-board phase lock loops (PLLs). The
family offers up to 1 million system gates, supported with up
to 198 kbits of 2-port SRAM and up to 712 user I/Os, all
providing 50 MHz PCI performance.
To support customers’ needs for more comprehensive, lower
cost board-level testing, Actel’s ProASICPLUS devices are
fully compatible with IEEE Standard 1149.1 for test access
port and boundary-scan test architecture. For more details
on the Flash FPGA implementation please refer to the
“Boundary Scan” section on page 12.
Advantages to the designer extend beyond performance.
Four levels of routing hierarchy simplify routing, while the
use of Flash technology allows all functionality to be live at
power up, unlike SRAM-based FPGAs. No external Boot
PROM is required to support device programming. While
on-board security mechanisms prevent all access to the
program information, reprogramming can be performed
in-system to support future design iterations and field
upgrades. The device’s architecture mitigates the
complexity of ASIC migration at higher user volume. This
ProASICPLUS devices are available in
a variety of
high-performance plastic packages. Those packages, and the
performance features discussed above, are described in
more detail in the following sections of this document:
• “Features and Benefits” section on page 1
• “ProASICPLUS Architecture” section on page 5
• “Routing Resources” section on page 6
• “Clock Trees” section on page 9
makes ProASICPLUS
a
cost-effective solution for
applications in the networking, communications,
computing, and avionics markets.
• “Input/Output Blocks” section on page 10
• “LVPECL Input Pads” section on page 11
• “Boundary Scan” section on page 12
The ProASICPLUS family achieves its nonvolatility and
reprogrammability through an advanced Flash-based 0.22m
LVCMOS process with four-layer metal. Standard CMOS
design techniques are used to implement logic and control
functions, including the PLLs and LVPECL inputs. The
result is predictable performance fully compatible with gate
arrays.
• “User Security” section on page 14
• “Embedded Memory Floorplan” section on page 14
• “Design Environment” section on page 17
• “Package Thermal Characteristics” section on page 19
• “Operating Conditions” section on page 22
The ProASICPLUS architecture provides
granularity
comparable to gate arrays. The device core consists of a
Sea-of-TilesTM. Each tile can be configured as a flip-flop,
latch, or 3-input/1-output logic function by programming the
appropriate Flash switches. The combination of fine
granularity, flexible routing resources, and abundant Flash
switches allow 100% utilization and over 95% routability for
highly congested designs. Tiles and larger functions are
interconnected through a 4-level routing hierarchy.
• “DC Electrical Specifications (VDDP = 2.5V +/-0.2V)”
section on page 23 – page 25
• “AC Specifications (3.3V PCI Revision 2.2 Operation)”
section on page 26
• “Clock Conditioning Circuit” section on page 27
• “Embedded Memory Specifications” section on page 35
• “Package Pin Assignments” section on page 55 – page 109
Embedded 2-port SRAM blocks with built-in FIFO/RAM
control logic can have user-defined depth and width. Users
can also select programming for synchronous or
asynchronous operation, as well as parity generations or
checking.
• For more information concerning In-System Programming
with ProASICPLUS, refer to the application note,
Performing Internal In-System Programming Using
Actel’s ProASICPLUS Devices.
The clock conditioning circuitry is unique. Devices contain
two clock conditioning blocks, each with a PLL core, delay
lines, phase shifts (0×, 90×, 180×, 270×), and clock
multipliers/dividers. In short, this is all the circuitry needed
to provide bidirectional access to the PLL, and operation up
to 240 MHz. The PLL block contains four programmable
http://www.actel.com/appnotes/PAplusISPAN.pdf
2
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Ordering Information
_
APA1000
FG
1152
ES
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚ C)
I = Industrial (-40 to +85˚ C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
=
=
=
PQ
FG
PB
Plastic Quad Flat Pack
FineBall Grid Array
Plastic Ball Grid Array
Speed Grade
=
Blank
Standard Speed
=
1
TBD
Part Number
APA150
APA300
APA450
APA600
APA750
=
=
=
=
=
150,000 Equivalent System Gates
300,000 Equivalent System Gates
450,000 Equivalent System Gates
600,000 Equivalent System Gates
750,000 Equivalent System Gates
APA1000 = 1,000,000 Equivalent System Gates
Product Plan
Speed Grade
Application
Std
–1
C
I
APA150 Device
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
144-Pin Fine Ball Grid Array (FBGA)
256-Pin Fine Ball Grid Array (FBGA)
APA300 Device
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
144-Pin Fine Ball Grid Array (FBGA)
256-Pin Fine Ball Grid Array (FBGA)
APA450 Device
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
144-Pin Fine Ball Grid Array (FBGA)
256-Pin Fine Ball Grid Array (FBGA)
APA600 Device
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
256-Pin Fine Ball Grid Array (FBGA)
676-Pin Fine Ball Grid Array (FBGA)
APA750 Device
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
✔
✔
P
P
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Fine Ball Grid Array (PBGA)
676-Pin Fine Ball Grid Array (FBGA)
896-Pin Plastic Ball Grid Array (FBGA)
APA1000 Device
P
P
P
P
P
P
P
P
P
P
P
P
✔
✔
P
P
208-Pin Plastic Quad Flat Pack (PQFP)
456-Pin Plastic Ball Grid Array (PBGA)
896-Pin Plastic Ball Grid Array (FBGA)
1152-Pin Plastic Ball Grid Array (FBGA)
P
P
P
P
P
P
P
P
P
P
P
P
Applications:
C
I
=
=
Commercial
Industrial
Availability:
P = Planned
✔ = Limited Availability – Contact your Actel Sales representative for the latest availability
information.
Advanced v0.6
3
ProASICPLUS Family Flash FPGAs
Plastic Device Resources
User I/Os
PQFP
208-Pin
PBGA
456-Pin
FBGA
144-Pin
FBGA
256-Pin
FBGA
676-Pin
FBGA
896-Pin
FBGA
1152-Pin
Device
APA150
158
158
158
158
158
158
242
290
344
356
356
356
100
100
100
186
186
186
186
APA300
APA450
APA600
454
454
APA750
562
642
APA1000
Package Definitions
712
PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Ball Grid Array
4
Advanced v0.6
ProASICPLUS Family Flash FPGAs
ProASICPLUS Architecture
Flash Switch
The proprietary ProASICPLUS architecture provides
granularity comparable to gate arrays.
Unlike SRAM FPGAs, ProASICPLUS uses a live on
power-up ISP Flash switch as its programming element.
The ProASICPLUS device core (Figure 1) consists of a
Sea-of-Tiles™. Each tile can be configured as a 3-input logic
function (e.g., NAND gate, D-Flip-Flop, etc.) by
In the ProASICPLUS Flash switch, two transistors share the
floating gate, which stores the programming information.
One is the sensing transistor, which is only used for writing
and verification of the floating gate voltage. The other is the
switching transistor. It can be used in the architecture to
connect/separate routing nets or to configure logic. It is also
used to erase the floating gate (Figure 2 on page 6).
programming
the
appropriate
Flash
switch
interconnections (Figure 2 on page 6 and Figure 3 on
page 6). Tiles and larger functions are connected with any
of the four levels of routing hierarchy. Flash cells are
distributed throughout the device to provide nonvolatile,
reconfigurable interconnect programming. Flash switches
are programmed to connect signal lines to the appropriate
logic cell inputs and outputs. Dedicated high-performance
lines are connected as needed for fast, low-skew global
signal distribution throughout the core. Maximum core
utilization is possible for virtually any design.
ProASICPLUS devices also contain embedded two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming options include synchronous or asynchronous
operation, two-port RAM configurations, user defined depth
and width, and parity generation or checking. Table 3 on
page 14 lists the 24 basic memory configurations.
Logic Tile
The logic tile cell (Figure 3 on page 6) has three inputs (any
or all of which can be inverted) and one output (which can
connect to both ultra fast local and efficient long line
routing resources). Any three-input one-output logic
function, except a three input XOR, can be configured as
one tile. The tile can be configured as a latch with clear or
set or as a flip-flop with clear or set. Thus the tiles can
flexibly map logic and sequential gates of a design.
256x9 Two-Port SRAM
or FIFO Block
Logic Tile
Figure 1 • The ProASICPLUS Device Architecture
Advanced v0.6
5
ProASICPLUS Family Flash FPGAs
S Col D Col
Sensing
Switch In
Floating Gate
Switching
Word
Switch Out
Figure 2 • Flash Switch
Local Routing
In 1
Efficient Long
Line Routing
In 2 (CLK)
In 3 (Reset)
Figure 3 • Core Logic Tile
Routing Resources
The routing structure of the ProASICPLUS devices is
designed to provide high performance through a flexible
four-level hierarchy of routing resources: ultra fast local
resources, efficient long line resources, high speed very long
line resources, and high performance global networks.
The high speed very long line resources which span the
entire device with minimal delay, are used to route very long
or very high fanout nets. (Figure 6 on page 8).
The high performance global networks are low skew, high
fanout nets that are accessible from external pins or from
internal logic (Figure 7 on page 9). These nets are typically
used to distribute clocks, resets, and other high fanout nets
requiring a minimum skew. The global networks are
implemented as clock trees, and signals can be introduced
at any junction. These can be employed hierarchically, with
signals accessing every input on all tiles.
The ultra fast local resources are dedicated lines that allow
the output of each tile to connect directly to every input of
the eight surrounding tiles (Figure 4 on page 7).
The efficient long line resources provide routing for longer
distances and higher fanout connections. These resources
vary in length (spanning 1, 2, or 4 tiles), run both vertically
and horizontally, and cover the entire ProASICPLUS device
(Figure 5 on page 7). Each tile can drive signals onto the
efficient long line resources, which can, in turn, access
every input of every tile. Active buffers are inserted
automatically by routing software to limit the loading effects
due to distance and fanout.
6
Advanced v0.6
ProASICPLUS Family Flash FPGAs
L
L
L
L
L
Inputs
L
L
Ultra Fast
Local Lines
(connects a tile to the
adjacent tile, I/O buffer,
or memory block)
L
L
Figure 4 • Ultra Fast Local Resources
Spans 4 Tile
Spans 1 Tile
Spans 2 Tiles
Logic Tile
L
L
L
L
L
L
L
L
L
L
L
L
Spans 1 Tile
L
L
L
L
L
L
Spans 2 Tiles
Spans 4 Tile
L
L
L
L
L
L
Logic Cell
L
L
L
L
L
L
Figure 5 • Efficient Long Line Resources
Advanced v0.6
7
ProASICPLUS Family Flash FPGAs
High Speed Very Long Line Resouces
PAD RING
PAD RING
Figure 6 • High Speed Very Long Line Resources
8
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Clock Resources
The ProASICPLUS family offers powerful and flexible
control of circuit timing through the use of analog circuitry.
Each chip has two clock conditioning blocks, containing a
240 MHz phase lock loop (PLL) core, delay lines, phase
shifter(0°, 90°, 180°, 270°), clock multiplier/dividers and
all the circuitry needed for the selection and
interconnection of inputs to the global network (thus
providing bidirectional access to the PLL). This permits the
PLL block to drive inputs and/or outputs via the two global
lines on each side of the chip (four total lines). This
circuitry is discussed in more detail later in the data sheet.
Clock Trees
One of the main architectural benefits of ProASICPLUS is
the set of power and delay friendly global networks.
ProASICPLUS offers 4 global trees. Each of these trees is
based on a network of spines and ribs that reach all the tiles
in their regions (Figure 7). This flexible clock tree
architecture allows users to map up to 88 different
internal/external clocks in an APA1000 device. Details on
the clock spines and various numbers of the family are given
in Table 1 on page 10.
The flexible use of the ProASICPLUS clock spine allows the
designer to cope with several design requirements. Users
implementing clock resource intensive applications can
easily route external or gated internal clocks using global
routing spines. Users can also drastically reduce delay
penalties and save buffering resources by mapping critical
high-fanout nets to spines. For design hints on using these
features, refer to Actel’s Efficient Use of ProASIC Clock
Trees application note.
High Performace
Global Network
PAD RING
Low Skew
Global Networks
Global
Pads
Global
Pads
Global Spine
Global Ribs
Scope of Spine
PAD RING
Note: This figure shows routing for only one global path.
Figure 7 • High Performance Global Network
Advanced v0.6
9
ProASICPLUS Family Flash FPGAs
Table 1 • Number of Clock Spines
APA150
APA300
APA450
APA600
APA750
APA1000
Top Spine Height
24
768
24
32
1,024
32
32
1,024
32
48
1,536
48
64
2,048
64
80
2,560
80
Tiles in Each Top Spine
Bottom Spine Height
Tiles in Each Bottom Spine
Global Clock Networks (Trees)
Clock Spines/Tree
Total Spines
768
4
1,024
4
1,024
4
1,536
4
2,048
4
2,560
4
8
8
12
14
16
22
32
32
48
56
64
88
Total Tiles
6,144
8,192
12,288
21,504
32,768
56,320
Input/Output Blocks
Six or seven standard I/O pads are grouped with a GND pad
and either a VDD or VDDP pad. Two reference bias signals
ring the chip. One protects the cascaded output drivers
while the other creates a virtual VDD supply for the I/O
ring.
To meet complex system demands, the ProASICPLUS family
offers devices with a large number of user I/O pins, up to 712
on the APA1000. If the I/O pad is powered at 3.3V, each I/O
can be selectively configured at the 2.5V and 3.3V threshold
levels. Table 2 shows the available supply voltage
configurations (the PLL block uses an independent 2.5V
supply). Figure 8 illustrates I/O interfaces with global
networks. All I/Os include ESD protection circuits. Each I/O
has been tested to 2000V to the human body model (per
MIL-STD-883, Method 3015).
Table 2 • ProASICPLUS Power Supply Voltages
VDDP
2.5V
2.5V
2.5V
3.3V
Input Tolerance
3.3V, 2.5V
3.3V, 2.5V
Output Drive
Notes:
1. VDD is always 2.5V.
2. There is no requirement for power-supply sequencing for
ProASICPLUS devices.
PC<0:4>
I/O Tile
X
P<1,2>
P<0>
I/O
PAD
Standard I/O Pad Cell
PC<0:4>
P<1,2>
P<0>
Global MUX
Driver
I/O Tile
A
HC<A>
PC<0:4>
P<1,2>
P<0>
I/O Tile
GA
GL<A>
GL<B>
PAD
PAD
Standard I/O Pad Cell
Standard I/O Pad Cell
PC<0:4>
P<1,2>
P<0>
I/O Tile
GB
PC<0:4>
P<1,2>
P<0>
Global MUX
Driver
I/O Tile
B
HC<B>
GL<B>
PPECL
PAD
PAD
PECL Input Pad
Cell
GL<B>
NPECL
Figure 8 • ProASICPLUS Global I/O Scheme with Multiplexed Global Pads
10
Advanced v0.6
ProASICPLUS Family Flash FPGAs
LVPECL Input Pads
I/O pads are fully configurable to provide the maximum
flexibility and speed. Each pad can be configured as an
input, an output, a tristate driver, or a bidirectional buffer
(Figure 9). I/O pads configured as inputs have the following
features:
In addition to standard I/O pads and power pads,
ProASICPLUS devices have a PECL input pad at each end of
each of the global MUX lines, along with AVDD and AGND
pins to power the PLL block. The PECL input pad cell is
different from the standard I/O cell. It is operated from VDD
only. Since it is exclusively an input, it requires no output
signal, output enable signal or output configuration bits. As
a special high-speed differential input, it also does not
require pull ups.
• Individually selectable 2.5V or 3.3V threshold levels1
• Optional pull-up resistor
I/O pads configured as outputs have the following features:
• Individually selectable 2.5V or 3.3V compliant output
signals1
The PECL pad cell (Figure 10) consists of an input buffer
(containing a low voltage differential amplifier, whose
power is enabled by the PC<0> and CL<1> signals, and a
cascaded buffer), and a signal and its compliment (PPECL
and NPECL). The PECL pad cell compares voltages on the
PPECL pad and the NPECL pad and sends the results to the
global MUX over the P<0> wire. This high speed, low skew
output essentially controls the clock conditioning circuit.
• 3.3V PCI compliant
• Ability to drive LVTTL and LVCMOS levels
• Selectable drive strengths
• Selectable slew rates
• Tristate
I/O pads configured as bidirectional buffers have the
following features:
• Individually selectable 2.5V or 3.3V output signals and
PPECL
pad
+
ESD
protection
+
threshold levels1
CL<1>
• 3.3V PCI compliant
PPECL
PAD
• Optional pull-up resistor
• Optionally configurable as Schmitt Trigger input2
• Selectable drive strengths
• Selectable slew rates
P<0>
clamp
input
buffer
PC<0>
NPECL
PAD
NPECL
pad
• Tristate
+
ESD
protection
+
clamp
3.3V/2.5V
Signal Control
Pull-up
Control
Figure 10 • High Speed PECL Pad Cell Block Diagram
Y
EN
Pad
A
3.3V/2.5V Signal Control
Drive Strength and Slew
Rate Control
Figure 9 • I/O Block Schematic Representation
1. If pads are configured for 2.5V operation, they are compliant with 2.5V
level signals as defined by JEDEC JESD 8-5. If pads are configured for 3.3V
operation, they are compliant with the standard as defined by JEDEC JESD
8-A (LVTTL and LVCMOS).
2. The Schmitt Trigger input option can be configured as an input only, not a
bidirectional buffer. This input type may be slower than a standard input
under certain conditions and has typical hysteresis of about 0.3V.
Advanced v0.6
11
ProASICPLUS Family Flash FPGAs
Boundary Scan
(test data input and output), TMS (test mode selector) and
TRST (test reset input). TMS, TDI and TRST are equipped
with pull-up resistors to ensure proper operation when no
input data is supplied to them. These pins are dedicated for
boundary-scan test usage.
ProASICPLUS devices are compatible with IEEE Standard
1149.1, which defines a set of hardware architecture and
mechanisms for cost-effective board-level testing. The basic
ProASICPLUS boundary-scan logic circuit is composed of the
TAP (test access port), TAP controller, test data registers,
and instruction register (Figure 11). This circuit supports
all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD and BYPASS), the optional IDCODE
instructions and private instructions used for device
programming and factory testing.
The TAP controller is a four-bit state machine (16 states)
that operates as shown in Figure 12 on page 13. The ‘1’s and
‘0’s represent the values that must be present at TMS at a
rising edge of TCK for the given state transition to occur. IR
and DR indicate that the instruction register or the data
register is operating in that state.
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI, and TDO
I/O
I/O
I/O
I/O
I/O
Test Data
Registers
Bypass Register
Instruction
Register
TAP
Controller
Device
Logic
I/O
I/O
I/O
I/O
I/O
Figure 11 • ProASICPLUS JTAG Boundary Scan Test Logic Circuit
12
Advanced v0.6
ProASICPLUS Family Flash FPGAs
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest of
the test logic architecture. On power up, the TAP controller
enters the Test-Logic-Reset state. To guarantee a reset of
the controller from any of the possible states, TMS must
remain high for five TCK cycles. The TRST pin may also be
used to asynchronously place the TAP controller in the
Test-Logic-Reset state.
ProASICPLUS devices support three types of test data
registers: bypass, device identification, and boundary scan.
The bypass register is selected when no other register needs
to be accessed in a device. This speeds up test data transfer
to other devices in a test data path. The 32-bit device
identification register is a shift register with four fields
(LSB, ID number, part number and version). The
boundary-scan register observes and controls the state of
each I/O pin.
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out pins.
The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary
scan register chain which starts at the TDI pin and ends at
the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output, and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Test-Logic
1
Reset
0
1
0
1
0
1
Run-Test/
Idle
Select-DR-
Scan
Select-IR-
Scan
0
0
0
Capture-DR
0
Capture-IR
0
1
1
Shift-IR
1
Shift-DR
1
1
1
Exit-DR
Exit-IR
0
Pause-DR
1
0
Pause-IR
1
0
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
0
0
1
1
Figure 12 • TAP Controller State Diagram
Advanced v0.6
13
ProASICPLUS Family Flash FPGAs
User Security
Embedded Memory Configurations
The ProASICPLUS devices have read-protect bits that, once
programmed, block the entire programmed contents from
being read externally. If locked, the user can only reprogram
the device using the security key. This protects it from being
read back and duplicated. Since programmed data is stored
in nonvolatile memory cells (which are actually very small
capacitors), rather than in the wiring, physical
deconstruction cannot be used to compromise data. This
approach is further hampered by the placement of the
memory cells, beneath the four metal layers (whose removal
cannot be accomplished without disturbing the charge in
the capacitor). This is the highest security provided in the
industry. For more information, refer to Actel’s Design
Security in Nonvolatile Flash and Antifuse FPGAs white
paper.
The embedded memory in the ProASICPLUS family provides
great configuration flexibility. Other programmable vendors
typically use single port memories that can only be
transformed into two-port memories by sacrificing half the
memory. Each ProASICPLUS block is designed and
optimized as a two-port memory (1 read, 1 write). This
provides 198k bits of total memory for two-port and single
port usage in the APA1000 device.
Each memory can be configured as FIFO or SRAM, with
independent selection of synchronous or asynchronous read
and write ports (Table 3). Additional characteristics include
programmable flags as well as parity checking and
generation. Figure 13 on page 15 and Figure 14 on page 16
show the block diagrams of the basic SRAM and FIFO
blocks. These memories are designed to operate at up to
150 MHz when operated individually. Each block contains a
256 word, 9-bit wide (1 read, 1 write) memory. The memory
blocks may be combined in parallel to form wider memories
or stacked to form deeper memories (Figure 15 on page 16).
This provides optimal bit widths of 9 (1 block), 18, 36, and
72, and optimal depths of 256, 512, 768, and 1024. Refer to
the Actel’s Macro Library Guide for more information.
Embedded Memory Floorplan
The embedded memory is located across the top of the
device (see Figure 1 on page 5) in 256x9 blocks. Depending
upon the device, up to 88 blocks are available to support a
variety of memory configurations. Each block can be
programmed as an independent memory or combined (using
dedicated memory routing resources) to form larger, more
complex memories. A single memory configuration cannot
include blocks from both the top and bottom memory
locations.
Figure 16 on page 17 gives an example of optimal memory
usage. Ten blocks with 23,040 bits have been used to
generate three memories of various widths and depths.
Figure 17 on page 17 shows how memory can be used in
parallel to create extra read ports. In this example, using
only 10 of the 88 available blocks of the APA1000 yields an
effective 6,912 bits of multiple port memories. The Actel
ACTgen software facilitates building wider and deeper
memories for optimal memory usage.
Table 3 • Basic Memory Configurations
Type
Write Access
Read Access
Parity
Library Cell Name
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
FIFO
FIFO
FIFO
FIFO
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
RAM256x9AA
Asynchronous
RAM256x9AAP
RAM256x9AST
RAM256x9ASTP
RAM256x9ASR
RAM256x9ASRP
RAM256x9SA
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Asynchronous
RAM256xSAP
RAM256x9SST
RAM256x9SSTP
RAM256x9SSR
RAM256x9SSRP
FIFO256x9AA
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Asynchronous
FIFO256x9AAP
FIFO256x9AST
FIFO256x9ASTP
Synchronous Transparent
Synchronous Transparent
14
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Table 3 • Basic Memory Configurations (Continued)
Type
Write Access
Read Access
Parity
Library Cell Name
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous Pipelined
Synchronous Pipelined
Asynchronous
Checked
Generated
Checked
Generated
Checked
Generated
Checked
Generated
FIFO256x9ASR
FIFO256x9ASRP
FIFO256x9SA
Asynchronous
FIFO256x9SAP
FIFO256x9SST
FIFO256x9SSTP
FIFO256x9SSR
FIFO256x9SSRP
Synchronous Transparent
Synchronous Transparent
Synchronous Pipelined
Synchronous Pipelined
DI <0:8>
WADDR <0:7>
DO <0:8>
DI <0:8>
DO <0:8>
SRAM
(256 X 9)
SRAM
(256 X 9)
RADDR <0:7>
WADDR <0:7>
RADDR <0:7>
WRB
Async Write
&
Async Read
RDB
WRB
Sync Write &
Sync Read
Ports
RDB
WBLKB
RBLKB
RCLKS
RBLKB
Ports
WCLKS
WBLKB
WPE
RPE
RPE
WPE
PARODD
PARODD
DI <0:8>
DO <0:8>
DI <0:8>
DO <0:8>
SRAM
(256 X 9)
SRAM
(256 X 9)
WADDR <0:7>
RADDR <0:7>
WADDR <0:7>
RADDR <0:7>
WRB
WRB
Sync Write
&
RDB
RDB
Async Write
&
Sync Read
WBLKB
WBLKB
RBLKB
RBLKB
Async Read
WCLKS
WPE
Ports
RCLKS
Ports
RPE
RPE
WPE
PARODD
PARODD
Note: For memory block interface signal definitions, see Table 4 on page 35
Figure 13 • Example SRAM Block Diagrams
Advanced v0.6
15
ProASICPLUS Family Flash FPGAs
DI <0:8>
LEVEL <0:7>
LGDEP<0:2>
WRB
DI<0:8>
DO <0:8>
LEVEL<0:7>
DO <0:8>
WPE
LGDEP<0:2>
WRB
WPE
FIFO
FIFO
(256 X 9)
Sync Write &
Sync Read
Ports
WBLKB
RPE
RPE
WBLKB
(256 X 9)
Sync Write &
Async Read
Ports
FULL
EMPTY
FULL
RDB
RBLKB
EMPTY
RDB
RBLKB
EQTH
EQTH
PARODD
PARODD
GEQTH
GEQTH
WCLKS
WCLKS
RESET
RCLKS
DO <0:8>
WPE
DI <0:8>
LEVEL <0:7>
LGDEP<0:2>
DO <0:8>
DI <0:8>
LEVEL <0:7>
LGDEP<0:2>
WRB
WBLKB
WRB
WBLKB
WPE
FIFO
(256 X 9)
Async Write &
Sync Read
Ports
FIFO
(256 X 9)
Async Write &
Async.Read
Ports
RPE
RPE
FULL
FULL
EMPTY
RDB
RBLKB
EMPTY
EQTH
RDB
EQTH
RBLKB
PARODD
GEQTH
GEQTH
PARODD
RCLKS
RESET
Note: For memory block FIFO signal definitions, see Table 5 on page 46.
Figure 14 • Basic FIFO Block Diagrams
9
Word Width
9
9
9
9
256
9
256
256
9
256
256
…
9
256
9
256
256
Word
256
Depth
88 blocks
Figure 15 • APA1000 Memory Block Architecture
16
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Word Width
9
9
9
9
9
Word
Depth
256
256
256
256 words x 18 bits, 1 read, 1 write
256
512 words x 18 bits, 1 read, 1 write
256
256
256
1,024 words x 9 bits, 1 read, 1 write
Total Memory Blocks Used = 10
Total Memory Bits = 23,040
Figure 16 • Example Showing Memories with Different Widths and Depths
Word Width
9
9
Write Port
Write Port
9
9
Word
Depth
256
256
Read Ports
256 words x 9 bits, 2 read, 1 write
Read Ports
1,024 words x 9 bits, 4 read, 1 write
Total Memory Blocks Used = 10
Total Memory Bits = 6,912
Figure 17 • Multiport Memory Usage
Design Environment
ACTgen, included in Actel’s Designer Series, can be used to
automatically generate memories based on user inputs. The
design engineer can select the depth and width, usage of
parity generation or check, and synchronous or
asynchronous functionality of the ports. For a synchronous
read port, the user can choose whether the output is
pipelined or transparent. Designer allows any bit width up
to 252. However, when an intermediate bit width, such as 16
bits, is chosen, the remaining two bits are not accessible for
other memories. Actel’s Designer also enables optimal
memory stacking in 256 word increments. However, any
word depth may be combined for up to 22,528 words.
ACTgen also allows the user to generate distributed
memory.
ProASICPLUS devices are supported by Actel’s Designer
Series, as well as third party CAE tools. Unlike some FPGA
vendors, no special HDL design techniques are needed
when using the standard VHDL or Verilog HDL descriptions.
As a result, designers may utilize technology independent of
HDL code for ProASICPLUS devices. This feature and the
ASIC-like design flow ensure a seamless transition to an
ASIC implementation, if desired (Figure 18 on page 18).
Advanced v0.6
17
ProASICPLUS Family Flash FPGAs
Place and route is also performed by Actel’s Designer
software. Available for UNIX workstations and PC platforms,
Designer accepts standard netlists in Verilog, VHDL, and
EDIF formats, performs place and route of the design into
the selected device, and provides postlayout delay
information for back-annotation simulation and static
timing analysis.
Actel’s Designer can also generate the BSDL
(boundary-scan description language) files required for
documenting the IEEE 1149.1 components which can be
used by automatic test equipment software.
Actel’s Designer also contains the necessary information for
the placing, routing, and configuration of the clock
conditioning circuit.
ACTgen provides all the software needed for configuration
of the PLL clock conditioning circuit. While the PLL has no
placement mobility, ACTgen allows users to use placement
and routing floorplan constraints hierarchically, in order to
more easily and efficiently explore floorplan alternatives.
This allows the power of the PLL circuitry to be utilized with
minimal top level timing loop iterations.
Once the design is finalized, the programming bitstream is
downloaded into the device programmer for programming
the ProASICPLUS part. ProASICPLUS devices can be
programmed with the Silicon Sculptor II and Flash Pro
programmers. Additionally, in-system programming is
available. For details on ProASICPLUS programming, refer to
the application note, Performing Internal In-System
Programming Using Actel’s ProASICPLUS Devices.
Design Creation/Verification
High-Level
Simulation
Verilog orVHDL Simulator
Library
Design
(Verilog orVHDL)
Synthesis
Library
SynthesisTool
Forward
Constraints
Structural
Netlist
Design Implementation
P&R User
Constraints
Designer
(P&RTool)
ACTgen
Backannotation
SDF
Timing
File
Programming
Data
Timing and Simulation
Programming
Simulation
Library
Silicon
Sculptor II
Timing
Libraries
Verilog orVHDL Simulator
Flash
Pro
Timing
Analyzer
Figure 18 • Design Flow
18
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Package Thermal Characteristics
The ProASICPLUS family is available in several package
types with a range of pin counts. Actel has selected
packages based on high pin count, reliability factors, and
superior thermal characteristics.
thermal resistance Θ . Maximum junction temperature is
the maximum allowable temperature on the active surface
of the IC and is 110° C. P is defined as:
ja
TJ – TA
----------------
P =
Thermal resistance defines the ability of a package to
conduct heat away from the silicon, through the package, to
the surrounding air. Junction-to-ambient thermal
resistance is measured in degrees Celsius/Watt and is
Θja
Θ is a function of the rate (in linear feet per minute - lfpm)
ja
of airflow in contact with the package. When the estimated
power consumption exceeds the maximum allowed power,
other means of cooling, such as increasing the airflow rate,
must be used.
represented as Theta ja (Θ ). The lower thermal resistance,
ja
the more efficiently a package will dissipate heat.
A package’s maximum allowed power (P) is a function of
maximum junction temperature (TJ), maximum ambient
operating temperature (TA), and junction-to-ambient
Package Type
Pin Count
Θjc
Θja Still Air
Θja 300 ft./min
Units
Plastic Quad Flat Pack (PQFP)
PQFP with Heatspreader
208
208
144
256
456
676
896
1152
8
30
20
23
17
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
3.8
3.8
3.0
3
Fine Ball Grid Array (FBGA)
Fine Ball Grid Array (FBGA)
Plastic Ball Grid Array (PBGA)
Fine Ball Grid Array (FBGA)
Fine Ball Grid Array (FBGA)
Fine Ball Grid Array (FBGA)
38.8
30
26.7
25
18
14.5
11.5
7.9
3.2
2.0
2.0
15
10.9
11.2
7.0
Advanced v0.6
19
ProASICPLUS Family Flash FPGAs
Calculating Power Dissipation
ProASICPLUS device power is calculated with both a static
and an active component. The active component is a
function of both the number of tiles utilized and the system
speed. Power dissipation can be calculated using the
following formula:
P
logic, the logic-tile component of AC power dissipation, is
given by
Plogic = P3 * mc * Fs
where:
• P3 = 3.0 uW/MHz, is the average power consumption
of a logic-tile normalized per MHz of its output
frequency
P
total = Pdc + Pac
where:
• mc = the number of logic tiles switching during each
• Pdc
• Pac
=
=
10 mW
Pclock + Pstorage + Plogic + Pios + Pmemory
Fs cycle
• Fs = the clock frequency
Pclock, the clock component of power dissipation, is given by
clock = (P1 + P2 * s) * Fs
P
ios, the I/O component of AC power dissipation, is given by
ios = (P4 + Cload * Vddp^2) * p * Fp
P
P
where:
where:
• P1 = 2500 uW/MHz is the basic power consumption of
• P4 = 60.0 uW/MHz is the average power consumption
of an output pad normalized per MHz of its
output frequency (internal power-load is not
included)
the clock tree normalized per MHz of the clock.
• P2 = 1.0 uW/MHz is the extra power consumption of
the clock tree per storage tile – also normalized
per MHz of the clock
• Cload = the output load
• s
• Fs = the clock frequency
storage, the storage-tile component of AC power dissipation,
= the number of storage tiles clocked by this clock
• p = the number of outputs
• Fp = the average output frequency
P
Finally, Pmemory, the memory component of AC power
consumption, is given by
is given by
P
storage = P5 * ms * Fs
Pmemory = P6 * Nmem * Fmem
where:
where:
• P5 = 1.0 uW/MHz is the average power consumption of a
storage-tile normalized per MHz of its output
frequency
• P6 = 100.0 uW/MHz is the average power
consumption of a memory block normalized per
MHz of the clock
• ms = the number of storage tiles switching during each
• Nmem = the number of RAM/FIFO blocks
Fs cycle
(1 block = 256 words * 9 bits)
• Fs = the clock frequency
• Fmem = the clock frequency of the memory
20
Advanced v0.6
ProASICPLUS Family Flash FPGAs
The following is an APA750 example using a shift register
design with 13,440 storage tiles and 0 logic tiles. This design
has one clock at 10 MHz, and 24 outputs toggling at 5 MHz.
We then calculate the various components as follows:
Pios
• Fp = 5 MHz
=> Pios = (P4 + Cload * Vddp^2) * p * Fp = 54.1 mW
Pmemory
Pclock
Nmem
=
0 (no RAM/FIFO in this shift-register)
• Fs = 10 MHz
• s = 13,440
=> Pmemory = 0 mW
Pac
=> Pclock = (P1 + P2 * s) * Fs = 159.4 mW
Pstorage
=> 347.9 mW
Ptotal
Pdc + Pac = 357.9mW
• ms = 13,440 (in a shift register 100% of storage-tiles are
toggling at each clock cycle and Fs = 10 MHz)
• mc = 0 (no logic tile in this shift-register)
Power Consumption of an APA Device
=> Pstorage = P5 * ms * Fs = 134.4 mW
1000
ProASIC
Plogic
900
SRAM
• C
• Vddp
=
=
=
40 pF
3.3 V
24
800
700
600
500
400
300
200
load
•
p
=> Plogic = 0 mW
P
110 instances of 16-bit binary counters
100
0
90
80
20
70
100 120
50
60
30
40
Frequency (MHz)
Advanced v0.6
21
ProASICPLUS Family Flash FPGAs
Operating Conditions
Absolute Maximum Ratings
Parameter
Condition
Minimum
Maximum
Units
Supply Voltage (VDD
)
–0.3
–0.3
–0.3
–0.5
–10
0
3.0
4.0
V
V
Supply Voltage I/O Ring (VDDP
DC Input Voltage
)
VDDP + 0.3
V
PCI DC Input Voltage
DC Input Clamp Current
PECL Input Voltage
V
DDP + 0.5
V
VIN < 0 or VIN> VDDP
+10
mA
V
2.5
Programming and Storage Temperature Limits
Storage Temperature
Min. Max.
Product Grade
Commercial
Programming Cycles
Program Retention
100
100
20 years
20 years
–55°C
–55°C
110°C
110°C
Industrial
Supply Voltages
Mode
VDD
VDDP
VPP
VPN
Single Voltage
Mixed Voltage
2.5V
2.5V
2.5V
3.3V
0 ≤ VPP ≤ 16.5V
0 ≤ VPP ≤ 16.5V
–13.8V ≤ VPN ≤0V
–13.8V ≤ VPN ≤ 0V
Recommended Operating Conditions
Parameter
Symbol
Limits
Commercial
DC Supply Voltage (2.5V I/Os)
DC Supply Voltage (Mixed 2.5V, 3.3V I/Os)
VDD & VDDP
VDDP
VDD
2.3V to 2.7V
3.0V to 3.6V
2.3V to 2.7V
0°C to 70°C
110°C
Operating Ambient Temperature Range
Maximum Operating Junction Temperature
Maximum Clock Frequency
Maximum RAM Frequency
Industrial
TA
TJ
fCLOCK
fRAM
240 MHz
150 MHz
DC Supply Voltage (2.5V I/Os)
DC Supply Voltage (2.5V, 3.3V I/Os)
VDD & VDDP
VDDP
VDD
2.3V to 2.7V
3.0V to 3.6V
2.3V to 2.7V
–40°C to 85°C
110°C
Operating Ambient Temperature Range
Maximum Operating Junction Temperature
Maximum Clock Frequency
TA
TJ
fCLOCK
fRAM
240 MHz
150 MHz
Maximum RAM Frequency
22
Advanced v0.6
ProASICPLUS Family Flash FPGAs
DC Electrical Specifications (VDDP = 2.5V +/-0.2V)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Output High Voltage
IOH = –6 mA
2.1
2.0
1.7
I
OH = –12 mA
High Drive (OB25LPH)
IOH = –24 mA
VOH
V
I
I
OH = –4 mA
OH = –6 mA
2.1
2.0
1.7
Low Drive (OB25LPL)
IOH = –10 mA
Output Low Voltage
IOL = 8 mA
0.2
0.4
0.7
High Drive (OB25LPH)
I
I
OL = 15 mA
OL = 24 mA
VOL
V
IOL = 4 mA
0.2
0.4
0.7
Low Drive (OB25LPL)
I
I
OL = 8 mA
OL = 15 mA
VIH
VIL
Input High Voltage
Input Low Voltage
1.7
VDDP + 0.3
0.7
V
V
–0.3
Weak Pull-up Resistance
(OTB25LPU)
RWEAKPULLUP
VIN ≥ 1.25
10
30
kΩ
with pull up (VIN = VSS
without pull up
)
Input Current
Input Current
–250
–10
– 80
µA
µA
IIN
(VIN = VSS or VDD
)
10
Quiescent Supply Current
(standby)
IDDQ
IOZ
VIN = VSS2 or VDD
VOH = VSS or VDD
5.0
10
10
mA
µA
3-State Output Leakage Current
–10
Output Short Circuit Current High
High Drive (OB25LPH)
IOSH
VIN = VSS
VIN = VSS
–120
–100
mA
Low Drive (OB25LPL)
Output Short Circuit Current Low
High Drive (OB25LPH)
IOSL
VIN = VDDP
VIN = VDDP
100
30
mA
Low Drive (OB25LPL)
CI/O
I/O Pad Capacitance
10
10
pF
pF
CCLK
Notes:
Clock Input Pad Capacitance
1. All process conditions. Junction Temperature: –40 to +110°C.
2. No pull-up resistor.
Advanced v0.6
23
ProASICPLUS Family Flash FPGAs
DC Electrical Specifications (VDDP = 3.3V +/-0.3V and VDD 2.5+/-0.2V)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Output High Voltage
3.3V I/O, High Drive (OB33P)
IOH = –15 mA
0.9∗VDDP
I
OH = –30 mA
2.4
V
IOH = –7 mA
OH = –14 mA
0.9∗VDDP
3.3V I/O, Low Drive (OB33L)
I
2.4
VOH
Output High Voltage
2.5V I/O, High Drive (OB25H)
IOH = –0.1 mA
2.1
2.0
1.7
I
I
OH = –0.5 mA
OH = –4 mA
V
V
IOH = –0.1 mA
IOH = –0.5 mA
IOH = –2.5 mA
2.1
2.0
1.7
2.5V I/O, Low Drive (OB25L)
Output Low Voltage
3.3V I/O, High Drive (OB33P)
IOL = 15 mA
IOL = 20 mA
0.1VDDP
0.4
I
OL = 7 mA
0.1VDDP
0.4
3.3V I/O, Low Drive (OB33L)
IOL = 10 mA
VOL
Output Low Voltage
2.5V I/O, High Drive (OB25H)
IOL = 7 mA
IOL = 14 mA
IOL = 28 mA
0.2
0.4
0.7
V
V
I
OL = 5 mA
0.2
0.4
0.7
2.5V I/O, Low Drive (OB25L)
IOL = 10 mA
IOL = 15 mA
Input High Voltage
3.3V LVTTL/LVCMOS
2.5V Mode
Input Low Voltage
3.3V LVTTL/LVCMOS
2.5V Mode
VIH
VIL
2
1.7
VDDP + 0.3
VDDP + 0.3
0.3
0.3
0.8
0.7
V
Weak Pull-up Resistance
(OTB33U)
Weak Pull-up Resistance
(OTB25U)
RWEAKPULLUP
VIN ≥ 1.5
VIN ≥ 1.5
15k
10k
25k
20k
kΩ
kΩ
RWEAKPULLUP
Input Current
with pull up (VIN = VSS
without pull up
)
IIN
–300
–-10
–80
10
µA
µA
(VIN = VSS or VDD
)
Quiescent Supply Current
(standby)
3-State Output Leakage Current
Output Short Circuit Current High
3.3V High Drive (OB33P)
3.3V Low Drive (OB33L)
IDDQ
IOZ
VIN = VSS2 or VDD
VOH = VSS or VDD
5.0
10
10
mA
µA
–-10
VIN = VSS
VIN = VSS
200
100
IOSH
mA
VIN = VSS
VIN = VSS
2.5V High Drive (OB25H)
2.5V Low Drive (OB25L)
20
10
Notes:
1. All process conditions. Junction Temperature: –40 to +110°C.
2. No pull-up resistor.
24
Advanced v0.6
ProASICPLUS Family Flash FPGAs
DC Electrical Specifications (VDDP = 3.3V +/-0.3V and VDD 2.5+/-0.2V) (Continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Output Short Circuit Current Low
3.3V High Drive
3.3V Low Drive
V
IN = VDD
2 00
100
VIN = VDD
IOSL
mA
VIN = VDD
VIN = VDD
2.5V High Drive
2.5V Low Drive
I/O Pad Capacitance
Clock Input Pad Capacitance
2 00
100
10
CI/O
CCLK
Notes:
pF
pF
10
1. All process conditions. Junction Temperature: –40 to +110°C.
2. No pull-up resistor.
DC Specifications (3.3V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
VDD
VDDP
VIH
Supply Voltage for Core
Supply Voltage for I/O Ring
Input High Voltage
2.3
3.0
2.7
3.6
V
V
0.5VDPP VDPP + 0.5
V
VIL
Input Low Voltage
–0.5
0.7VDDP
–10
0.3VDDP
V
IIPU
Input Pull-up Voltage1
Input Leakage Current2
Output High Voltage
Output Low Voltage
V
IIL
0 < VIN < VCCI
IOUT = –500 µA
IOUT = 1500 µA
+10
µA
V
VOH
VOL
CIN
0.9VDPP
0.1VDPP
10
V
Input Pin Capacitance3
pF
pF
CCLK
Notes:
CLK Pin Capacitance
5
12
1. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network.
Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
Advanced v0.6
25
ProASICPLUS Family Flash FPGAs
AC Specifications (3.3V PCI Revision 2.2 Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
0 < VOUT ≤ 0.3VCCI
*
–12VCCI
mA
mA
Switching Current High
0.3VCCI ≤ VOUT < 0.9VCCI
*
(–17.1 + (VDDP – VOUT))
IOH(AC)
0.7VCCI < VOUT < VCCI
VOUT = 0.7VCC *
*
(Test Point)
–32VCCI
mA
mA
mA
VCCI > VOUT ≥ 0.6VCCI
*
16VDDP
0.6VCCI > VOUT > 0.1VCCI
1
(26.7VOUT)
See page
21, equa-
tion B of
PCI rev. 2.2
spec
Switching Current Low
IOL(AC)
0.18VCCI > VOUT > 0 *
(Test Point)
V
OUT = 0.18VCC
*
38VCCI
mA
mA
ICL
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
ICH
VCCI + 4 > VIN ≥ VCCI + 1
0.2VCCI to 0.6VCCI load *
0.6VCCI to 0.2VCCI load *
25 + (VIN – VDDP – 1)/0.015
mA
slewR
slewF
1
1
4
4
V/ns
V/ns
Note: * Refer to the PCI Specification document rev. 2.2.
pin
1/2 in. max.
10 pF
output
buffer
1k Ω
pin
1k Ω
output
buffer
10 pF
26
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Timing Control and Characteristics
Clock Conditioning Circuit
Each PLL block contains four programmable dividers as
shown in Figure 20 on page 28. The first (n) provides all
integer divisors from 1 to 16. The second and third (u and v)
permit the signal applied to the global network to be further
divided by factors of 2, 3 or 4. The fourth divider (m, located
in the direct feedback path) is controlled by 6 bits, allowing
the incoming clock signal to be multiplied by integer factors
from 1 to 64. The implementations m/(n*u) and m/(n*v)
enable the user to define a wide range of multipliers and
divisors factors.
ProASICPLUS devices provide designers with very flexible
clocking capabilities. Each side of the chip contains a clock
conditioning circuit based upon a 240 MHz phase-locked
loop (PLL) block (Figure 19 on page 28). Two global
multiplexed lines extend along each side of the chip to
provide bidirectional access to the PLL on that side
(neither MUX can be connected to the opposite side’s PLL).
Each global line has optional PECL input pads (described
below). The global lines may be driven by either the PECL
global input pad or the outputs from the PLL block or both.
Each can be driven by a different output from the PLL.
The clock conditioning circuit can advance or delay the
clock up to 4ns (in increments of 0.25ns) relative to the
positive edge of the incoming reference clock. The system
also allows for the selection of output frequency clock
phases of 0°, 90°, 180°, and 270°. A “lock” signal is
provided to indicate that the PLL has locked to the
incoming signal, and a “standby” signal switches the PLL
block off when it is not locked to a signal. That allows
pre-selected signals to be passed directly through, at least
to the corresponding rib drivers.
The 2 signals available to drive the global networks are as
follows:
Global A:
• Output from Global MUX A
• Conditioned version of PLL output (fOUT
)
– Delayed or advanced
– 0°, 90°, 180°, and 270° phase shift (with optional
Prior to the application of signals to the rib drivers, they
pass through programmable delay units, one per global
network. These units permit the delaying of global signals
relative to other signals to assist in the control of input
set-up times. Not all possible combinations of input and
output mode can be used. The degrees of freedom available
in the bidirectional global pad system and in the clock
conditioning circuit have been restricted. This avoids
unnecessary and unwieldy design kit and software work.
time advance)
• Divided version of either of the above
• Delayed version of either of the above (0.25ns, 0.50ns, or
4.00ns delay).3
Global B:
• Output from Global MUX B
• Delayed or advanced version of fOUT
• Divided version of either of the above
The PLL can be configured internally during design (via
Flash-configuration bits set in the programming bitstream)
or externally during operation. This is done through a
simple, dynamically accessible asynchronous interface – a
dedicated register file, which allows user signals to initiate
parameter changes, such as PLL divide/multiply ratios.
• Delayed version of either of the above (0.25ns, 0.50ns, or
4.00ns delay).3
For information on the clock conditioning circuit, refer to
the, Using ProASICPLUS Clock Conditioning Circuits
application note.
3. This mode is available through the delay feature of the Global MUX driver.
Advanced v0.6
27
ProASICPLUS Family Flash FPGAs
AVDD
VDD
AGND
GND
+
-
LVPECL
Output A
Output B
Global MUX A OUT
Clock from Core
PLL Block
Global MUX B OUT
External Feedback Signal
8
4
24
Dynamic
Configuration Bits
To/From
Mask Programmable
Delay
Flash
Configuration Bits
Dynamic Configuration Bit Outputs
Dynamic Configuration Bit Inputs
Lock Detect
Data Out
Stand-by mode of Core
Data In
GND ( Spare 1)
GND (Spare 2)
Shift Clock
Shift Enable
Update
NVM/Register Mode
(Other three bits used for flash configuration)
Figure 19 • PLL Block – Top-Level View
Global MUX A OUT
÷n
270˚
180˚
90˚
0˚
Output A
D
PLL Core
÷u
÷m
D
D
External Feedback
Global MUX B OUT
÷v
D
Output B
Figure 20 • PLL Block – Detailed Block Diagram
28
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Logic Tile Timing Characteristics
High Speed Very Long Lines
Timing characteristics for ProASICPLUS devices fall into
three categories: family dependent, device dependent, and
design dependent. The input and output buffer
characteristics are common to all ProASICPLUS family
members. Internal routing delays are device dependent.
Design dependency means that actual delays are not
determined until after placement and routing of the user’s
design are complete. Delay values may then be determined
by using the Timer utility or performing simulation with
post-layout delays.
Some nets in the design are very long lines, which are
special routing resources that span multiple rows, columns
or modules. This increases capacitance and resistance,
resulting in longer net delays for macros connected to long
tracks. Typically, up to 6 percent of nets in a fully utilized
device require very long lines. Very long lines contribute
from 4ns to 8.4ns routing delay. This additional delay is
represented statistically in higher fanout routing delays.
Timing Derating
Since ProASICPLUS devices are manufactured with a CMOS
process, device performance will vary with temperature,
voltage, and process. Minimum timing parameters reflect
maximum operating voltage, minimum operating
temperature, and optimal process variations. Maximum
timing parameters reflect minimum operating voltage,
maximum operating temperature, and worst-case process
variations (within process specifications).
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net property
assignment prior to placement and routing. Up to 6 percent
of the nets in a design may be designated as critical, while
90% of the nets in a design are typical. Refer to the Actel
Designer User’s Guide for details on using constraints.
Advanced v0.6
29
ProASICPLUS Family Flash FPGAs
Tristate Buffer Delays
EN
A
PAD
OTBx
A
50%
VOH
EN
50%
EN
50%
50%
VCC
50%
VOH
50%
50%
50%
VOL
90%
PAD
VOL
PAD
PAD
GND
50%
10%
50%
tDLH
tDHL
tENZL
tENZH
Tristate Buffer Delays
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70°C)
Max
tDLH
Max
tDHL
Max
tENZH
Max
tENZL
Macro Type Description
Units
OTB33PH
OTB33PN
OTB33PL
OTB33LH
OTB33LN
OTB33LL
OTB25HH
OTB25HN
OTB25HL
OTB25LH
OTB25LN
OTB25LL
3.3V, PCI Output Current, High Slew Rate
2.4
2.9
3.5
3.4
4.3
4.9
2.7
3.5
4.2
3.9
5.7
7.1
6.0
5.9
5.9
9.2
9.2
9.2
2.2
2.7
3.4
3.8
4.5
6.3
2.2
3.2
3.6
4.9
4.6
6.0
1.9
2.8
4.3
2.7
3.8
5.4
4.4
5.0
5.5
6.2
7.0
7.8
7.2
7.5
8.5
10.8
11.5
12.4
5.3
6.2
7.1
7.7
8.9
10.2
3.7
5.5
6.9
6.1
9.3
12.3
3.5
5.1
6.4
5.4
8.4
11.1
4.6
7.7
9.7
8.1
12.8
17.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.3V, PCI Output Current, Nominal Slew Rate
3.3V, PCI Output Current, Low Slew Rate
3.3V, Low Output Current, High Slew Rate
3.3V, Low Output Current, Nominal Slew Rate
3.3V, Low Output Current, Low Slew Rate
2.5V, High Output Current, High Slew Rate
2.5V, High Output Current, Nominal Slew Rate
2.5V, High Output Current, Low Slew Rate
2.5V, Low Output Current, High Slew Rate
2.5V, Low Output Current, Nominal Slew Rate
2.5V, Low Output Current, Low Slew Rate
OTB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate
OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate
OTB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate
OTB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate
OTB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate
OTB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate
Notes:
1.
tDLH = Data-to-Pad HIGH
2. tDHL = Data-to-Pad LOW
3. tENZH = Enable-to-Pad, Z to HIGH
4. tENZL = Enable-to-Pad, Z to LOW
30
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Output Buffer Delays
A
50%
VOH
50%
A
PAD
50%
PAD
VOL
50%
OBx
tDLH
tDHL
Output Buffer Delays
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70°C)
Max
tDLH
Max
tDHL
Max
tENZH
Max
tENZL
Macro Type Description
Units
OTB33PH
OTB33PN
OTB33PL
OTB33LH
OTB33LN
OTB33LL
OTB25HH
OTB25HN
OTB25HL
OTB25LH
OTB25LN
OTB25LL
3.3V, PCI Output Current, High Slew Rate
2.4
2.2
2.7
3.4
3.8
4.5
6.3
2.2
3.2
3.6
4.9
4.6
6.0
1.9
2.8
4.3
2.7
3.8
5.4
2.6
3.1
3.7
3.6
4.5
5.1
2.9
3.7
4.4
4.1
5.9
7.4
6.2
6.1
6.1
9.4
9.4
9.4
2.7
3.3
3.9
4.3
5.1
6.8
2.8
3.8
4.1
5.4
5.2
6.5
2.4
3.4
4.9
3.2
4.3
5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.3V, PCI Output Current, Nominal Slew Rate
3.3V, PCI Output Current, Low Slew Rate
3.3V, Low Output Current, High Slew Rate
3.3V, Low Output Current, Nominal Slew Rate
3.3V, Low Output Current, Low Slew Rate
2.5V, High Output Current, High Slew Rate
2.5V, High Output Current, Nominal Slew Rate
2.5V, High Output Current, Low Slew Rate
2.5V, Low Output Current, High Slew Rate
2.5V, Low Output Current, Nominal Slew Rate
2.5V, Low Output Current, Low Slew Rate
2.9
3.5
3.4
4.3
4.9
2.7
3.5
4.2
3.9
5.7
7.1
6.0
OTB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate
OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate 5.9
OTB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate
OTB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate
OTB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate
OTB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate
Notes:
5.9
9.2
9.2
9.2
1.
tDLH = Data-to-Pad HIGH
2. tDHL = Data-to-Pad LOW
3. tENZH = Enable-to-Pad, Z to HIGH
4. tENZL = Enable-to-Pad, Z to LOW
Advanced v0.6
31
ProASICPLUS Family Flash FPGAs
Input Buffer Delays
VCC
50%
PAD
0V
50%
50%
Y
VCC
PAD
Y
GND
50%
IBx
tINYH
tINYL
Input Buffer Delays
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Max.
tINYH
Max.
tINYL
Macro Type
Description
Units
IB25
2.5V, CMOS Input Levels, No Pull-up Resistor
2.5V, CMOS Input Levels, No Pull-up Resistor
2.5V, CMOS Input Levels, Low Power
0.5
0.8
1.1
0.9
0.9
1.2
0.8
0.8
0.7
0.9
0.6
0.5
ns
ns
ns
ns
ns
ns
IB25
IB25LP
IB25LPS
IB33
2.5V, CMOS Input Levels, Low Power
3.3V, CMOS Input Levels, No Pull-up Resistor
3.3V, CMOS Input Levels, No Pull-up Resistor
IB33S
Notes:
1.
tINYH = Input Pad-to-Y HIGH
2. tINYL = Input Pad-to-Y LOW
Global Input Buffer Delays
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70°, fCLOCK = 250 MHz)
Max.
tINYH
Max.
tINYL
Macro Type
Description
Units
GL25
2.5V, CMOS Input Levels
2.5V, CMOS Input Levels
2.5V, CMOS Input Levels
2.5V, CMOS Input Levels
3.3V, CMOS Input Levels
3.3V, CMOS Input Levels
1.9
1.8
1.7
1.9
1.9
2.2
1.6
1.8
2.2
1.9
1.6
1.5
ns
ns
ns
ns
ns
ns
GL25S
GL25LP
GL25LPS
GL33
GL33S
Predicted Global Routing Delay*
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Parameter
Description
Max.
Units
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (fully loaded row—32 inputs)
Input High to Low (fully loaded row—32 inputs)
Input Low to High (minimally loaded row—1 input)
Input High to Low (minimally loaded row—1 input)
1.2
1.1
0.9
0.9
ns
ns
ns
ns
* The timing delay difference between tile locations is less than 15ps.
Global Routing Skew
(Worst-Case Commercial Conditions, VDDP = 3.0V, VDD = 2.3V, TJ = 70°C, fCLOCK = 250 MHz)
Parameter
Description
Max.
Units
tRCKSWH
tRCKSHH
Maximum Skew Low to High
Maximum Skew High to Low
0.3
0.3
ns
ns
32
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Module Delays
A
B
C
Y
A
B
50% 50%
50% 50%
C
Y
50% 50%
50%
50%
50%
50%
50%
50%
tDCLH
tDCHL
tDBLH
tDBHL
tDALH
tDAHL
Sample Macrocell Library Listing
(Worst-Case Commercial Conditions, VDD = 2.3V, TJ = 70º C)
Maximum
Intrinsic Delay
Minimum
Setup/Hold
Cell Name
Description
Units
NAND2
AND2
NOR3
MUX2L
OA21
XOR2
LDL
2-Input NAND
0.4
0.4
ns
ns
ns
ns
ns
ns
2-Input AND
3-Input NOR
0.4
2-1 Mux with Active Low Select
2-Input OR into a 2-Input AND
2-Input Exclusive OR
Active Low Latch (LH/HL)
0.4
0.4
0.3
D: 0.3/0.2
tsetup 0.5
thold 0.2
ns
ns
DFFL
Negative Edge-Triggered D-type Flip-Flop (LH/HL)
CLK-Q:
0.4/0.4
tsetup 0.4
thold 0.2
Note: Assumes fanout of two.
Advanced v0.6
33
ProASICPLUS Family Flash FPGAs
Slew Rates Measured at C = 10pF, Nominal Power Supplies and 25°C
Type
Trig. Lev.
Rising Edge
pS
Slew Rate
V/nS
Falling Edge
pS
Slew Rate
V/nS
OB33PH
OB33PN
OB33PL
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
20%-60%
397
463
567
467
620
813
750
850
1310
793
870
1287
470
533
770
597
873
1153
3.33
2.85
2.33
2.83
2.13
1.62
1.33
1.18
0.76
1.26
1.15
0.78
2.13
1.81
1.30
1.68
1.15
0.87
390
450
527
700
767
1100
310
390
510
430
730
1037
433
527
753
707
760
1563
-3.38
-2.93
-2.51
-1.89
-1.72
-1.20
-3.23
-2.56
-1.96
-2.33
-1.37
-0.96
-2.31
-1.90
-1.33
-1.42
-1.32
-0.54
OB33LH
OB33LN
OB33LL
OB25HH
OB25HN
OB25HL
OB25LH
OB25LN
OB25LL
OB25LPHH
OB25LPHN
OB25LPHL
OB25LPLH
OB25LPLN
OB25LPLL
34
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Embedded Memory Specifications
This section discusses ProASICPLUS SRAM/FIFO embedded
memory and its interface signals, including timing diagrams
that show the relationships of signals as they pertain to
single embedded memory blocks (Table 4). Table 3 on
page 14 shows basic RAM and FIFO configurations.
Simultaneous Read and Write to the same location must be
done with care. On such accesses the DI bus is output to
the DO bus.
Note: The difference between synchronous transparent
and pipeline modes is the timing of all the output
signals from the memory. In transparent mode,
the outputs will change within the same clock
cycle to reflect the data requested by the currently
valid access to the memory. If clock cycles are
short (high clock speed), the data requires most of
the clock cycle to change to valid values (stable
signals). Processing of this data in the same clock
cycle is thus nearly impossible. Most designers
add registers at all outputs of the memory to push
the data processing into the next clock cycle. An
entire clock cycle can then be used to process the
data. To simplify use of this memory setup,
suitable registers have been implemented as part
of the memory primitive and are available to the
user in the synchronous pipeline mode. In this
mode, the output signals will change shortly after
the second rising edge, following the initiation of
the read access.
Enclosed Timing Diagrams—SRAM Mode:
• Synchronous RAM Read, Access Timed Output Strobe
(Synchronous Transparent)
• Synchronous RAM Read, Pipeline Mode Outputs
(Synchronous Pipelined)
• Asynchronous RAM Write
• Asynchronous RAM Read, Address Controlled, RDB=0
• Asynchronous RAM Read, RDB Controlled
• Synchronous RAM Write
• Embedded Memory Specifications
Table 4 • Memory Block SRAM Interface Signals
SRAM Signal
Bits
In/Out
Description
WCLKS
RCLKS
RADDR<0:7>
RBLKB
RDB
1
1
8
1
1
8
1
9
1
9
1
1
1
IN
IN
Write clock used on synchronization on write side
Read clock used on synchronization on read side
Read address
IN
IN
Negative true read block select
Negative true read pulse
IN
WADDR<0:7>
WBLKB
DI<0:8>
WRB
IN
Write address
IN
Negative true write block select
Input data bits <0:8>, <8> can be used for parity in
Negative true write pulse
IN
IN
DO<0:8>
RPE
OUT
OUT
OUT
IN
Output data bits <0:8>, <8> can be used for parity out
Read parity error
WPE
Write parity error
PARODD
Selects odd parity generation/detect when high, even when low
Note: Not all signals shown are used in all modes.
Advanced v0.6
35
ProASICPLUS Family Flash FPGAs
Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent)
RCLKS
RBD, RBLKB
RADDR
DO
Cycle Start
New Valid
Address
Old Data Out
New Valid Data Out
RPE
t
RACS
t
RDCS
t
RDCH
t
RACH
t
OCH
t
RPCH
t
t
CMH
CML
t
OCA
t
RPCA
t
CCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
3.0
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
CML
Clock low phase
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RADDR hold from RCLKS ↑
RADDR setup to RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
OCH
3.0
RACH
RACS
RDCH
RDCS
RPCA
RPCH
0.5
1.0
0.5
1.0
9.5
3.0
36
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
RCLKS
Cycle Start
RDB, RBLKB
New Valid
RADDR
Address
DO
New Valid Data Out
New RPE Out
Old Data Out
RPE
Old RPE Out
t
t
RACS
OCA
t
t
RACH
RPCH
t
t
RDCH
OCH
t
t
RPCA
RDCS
t
t
CML
CMH
t
CCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
3.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
CML
Clock low phase
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RADDR hold from RCLKS ↑
RADDR setup to RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
OCH
0.75
RACH
RACS
RDCH
RDCS
RPCA
RPCH
0.5
1.0
0.5
1.0
4.0
1.0
Advanced v0.6
37
ProASICPLUS Family Flash FPGAs
Asynchronous RAM Write
WADDR
WRB, WBLKB
DI
WPE
t
t
AWRS
AWRH
t
DWRH
t
t
WPDA
WPDH
t
DWRS
t
t
WRMH
WRML
t
WRCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
AWRH
AWRS
DWRH
DWRS
DWRS
WPDA
WPDH
WRCYC
WRMH
WRML
WADDR hold from WB ↑
WADDR setup to WB ↓
DI hold from WB ↑
DI setup to WB ↑
DI setup to WB ↑
WPE access from DI
WPE hold from DI
Cycle time
1.0
0.5
1.5
0.5
2.5
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARGEN is inactive
PARGEN is active
WPE is invalid while
PARGEN is active
1.0
7.5
3.0
3.0
WB high phase
Inactive
Active
WB low phase
38
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Asynchronous RAM Read, Address Controlled, RDB=0
RADDR
DO
RPE
t
OAH
t
RPAH
t
OAA
t
RPAA
t
ACYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
ACYC
OAA
Read cycle time
7.5
7.5
ns
ns
ns
ns
ns
New DO access from RADDR stable
Old DO hold from RADDR stable
New RPE access from RADDR stable
Old RPE hold from RADDR stable
OAH
3.0
3.0
RPAA
RPAH
10.0
Advanced v0.6
39
ProASICPLUS Family Flash FPGAs
Asynchronous RAM Read, RDB Controlled
RB=(RDB+RBLKB)
DO
RPE
t
ORDH
t
RPRDH
t
ORDA
t
RPRDA
t
t
RDML
RDMH
t
RDCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
ORDA
New DO access from RB ↓
Old DO valid from RB ↓
Read cycle time
7.5
ns
ns
ns
ns
ns
ns
ns
ORDH
RDCYC
RDMH
RDML
3.0
7.5
3.0
3.0
9.5
RB high phase
Inactive setup to new cycle
Active
RB low phase
RPRDA
RPRDH
New RPE access from RB ↓
Old RPE valid from RB ↓
3.0
40
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Synchronous RAM Write
WCLKS
WRB, WBLKB
WADDR, DI
WPE
Cycle Start
t
, t
WRCH WBCH
t
, t
WRCS WBCS
t
, t
DCS WDCS
t
WPCH
t
, t
DCH WACH
t
WPCA
t
t
CML
CMH
t
CCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
3.0
0.5
1.0
0.5
1.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
CML
Clock low phase
DCH
DI hold from WCLKS ↑
DI setup to WCLKS ↑
DCS
WACH
WDCS
WPCA
WPCH
WADDR hold from WCLKS ↑
WADDR setup to WCLKS ↑
New WPE access from WCLKS ↑
Old WPE valid from WCLKS ↑
WRB & WBLKB hold from WCLKS ↑
WPE is invalid while
PARGEN is active
0.5
WRCH,
WBCH
0.5
1.0
WRCS,
WBCS
WRB & WBLKB setup to WCLKS ↑
ns
Note: On simultaneous read and write accesses to the same location DI is output to DO.
Advanced v0.6
41
ProASICPLUS Family Flash FPGAs
Synchronous Write and Read to the Same Location
RCLKS
DO
New Data*
Last Cycle Data
WCLKS
t
WCLKRCLKH
t
WCLKRCLKS
t
OCH
t
OCA
* New data is read if WCLKS ↑ occurs before setup time.
The data stored is read if WCLKS ↑ occurs after hold time.
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
ns
ns
CMH
Clock high phase
CML
Clock low phase
3.0
WCLKRCLKS
WCLKRCLKH
OCH
WCLKS ↑ to RCLKS ↑ setup time
WCLKS ↑ to RCLKS ↑ hold time
Old DO valid from RCLKS ↑
New DO valid from RCLKS ↑
– 0.1
7.0
3.0
OCA/OCH displayed for
Access Timed Output
OCA
7.5
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock
edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS
driven by the same design signal.
3. If WCLKS changes after the hold time, the data will be read.
4. A setup or hold time violation will result in unknown output data.
42
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Asynchronous Write and Synchronous Read to the Same Location
RCLKS
New Data*
Last Cycle Data
DO
WB = {WRB + WBLKB}
DI
t
WCLKRCLKS
t
WCLKRCLKH
t
OCH
OCA
t
t
t
DWRRCLKS
DWRH
* New data is read if WB ↓ occurs before setup time.
The stored data is read if WB ↓ occurs after hold time.
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
Clock high phase
CML
Clock low phase
3.0
WBRCLKS
WBRCLKH
OCH
WB ↓ to RCLKS ↑ setup time
WB ↓ to RCLKS ↑ hold time
Old DO valid from RCLKS ↑
New DO valid from RCLKS ↑
DI to RCLKS ↑ setup time
DI to WB ↑ hold time
–0.1
7.0
3.0
OCA/OCH displayed for
Access Timed Output
OCA
7.5
0
DWRRCLKS
DWRH
Notes:
1.5
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write signal edge
occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read.
3. A setup or hold time violation will result in unknown output data.
Advanced v0.6
43
ProASICPLUS Family Flash FPGAs
Asynchronous Write and Read to the Same Location
RB, RADDR
NEW
NEWER
DO
OLD
WB = {WRB+WBLKB}
t
t
ORDA
RAWRH
t
ORDH
t
t
t
RAWRS
OWRA
OWRH
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx
Description
Min.
Max.
Units
Notes
ORDA
ORDH
OWRA
OWRH
RAWRS
RAWRH
Notes:
New DO access from RB ↓
Old DO valid from RB ↓
7.5
ns
ns
ns
ns
ns
ns
3.0
0.5
New DO access from WB ↑
Old DO valid from WB ↑
3.0
RB ↓ or RADDR from WB ↓
RB ↑ or RADDR from WB ↑
5.0
5.0
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger
a read operation which updates the read data.
2. Violation or RAWRS will disturb access to the OLD data.
3. Violation of RAWRH will disturb access to the NEWER data.
44
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Synchronous Write and Asynchronous Read to the Same Location
RB, RADDR
NEW
NEWER
DO
OLD
WCLKS
t
t
ORDA
RAWCLKH
t
ORDH
t
OWRA
t
OWRH
t
RAWCLKS
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx
Description
Min.
Max.
Units
Notes
ORDA
New DO access from RB ↓
Old DO valid from RB ↓
7.5
ns
ns
ns
ns
ns
ns
ORDH
3.0
0.5
OWRA
New DO access from WCLKS ↓
Old DO valid from WCLKS ↓
RB ↓ or RADDR from WCLKS ↑
RB ↑ or RADDR from WCLKS ↓
3.0
OWRH
RAWCLKS
RAWCLKH
Notes:
5.0
5.0
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger
a read operation which updates the read data.
2. Violation of RAWCLKS will disturb access to OLD data.
3. Violation of RAWCLKH will disturb access to NEWER data.
Advanced v0.6
45
ProASICPLUS Family Flash FPGAs
Asynchronous FIFO Full and Empty Transitions
The asynchronous FIFO accepts writes and reads while not
full or not empty. When the FIFO is full, all writes are
inhibited. Conversely, when the FIFO is empty, all reads are
inhibited. A problem is created if the FIFO is written during
the transition out of full to not full or read during the
transition out of empty to not empty. The exact time at
which the write (read) operation changes from inhibited to
accepted after the read (write) signal which causes the
transition from full (empty) to not full (empty) is
indeterminate. This indeterminate period starts 1 ns after
the RB (WB) transition, which deactivates full (not empty)
and ends 3 ns after the RB (WB) transition for slow cycles.
For fast cycles, the indeterminate period ends 3 ns (7.5 ns –
RDL (WRL)) after the RB (WB) transition, whichever is
later (Table 5).
The timing diagram for write is shown in Figure 21 on
page 47. The timing diagram for read is shown in Figure 22
on page 47. For basic RAM configurations, see Table 3 on
page 14.
Enclosed Timing Diagrams – FIFO Mode:
• Asynchronous FIFO Read
• Asynchronous FIFO Write
• Synchronous FIFO Read, Access Timed Output
Strobe (Synchronous Transparent)
• Synchronous FIFO Read, Pipeline Mode Outputs
(Synchronous Pipelined)
• Synchronous FIFO Write
• FIFO Reset
Table 5 • Memory Block FIFO Interface Signals
FIFO Signal
Bits
In/Out
Description
WCLKS
RCLKS
1
1
8
1
1
1
1
9
1
2
IN
Write clock used for synchronization on write side
Read clock used for synchronization on read side
Direct configuration implements static flag logic
Negative true read block select
IN
LEVEL <0:7>
RBLKB
IN
IN
RDB
IN
Negative true read pulse
RESET
IN
Negative true reset for FIFO pointers
WBLKB
DI<0:8>
WRB
IN
Negative true write block select
IN
Input data bits <0:8>, <8> will be generated if PARGEN is true
Negative true write pulse
IN
FULL, EMPTY
OUT
FIFO flags. FULL prevents write and EMPTY prevents read
EQTH is true when the FIFO holds the number of words specified by the
LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more
EQTH, GEQTH
2
OUT
DO<0:8>
RPE
9
1
1
3
1
OUT
OUT
OUT
IN
Output data bits <0:8>
Read parity error
WPE
Write parity error
LGDEP <0:2>
PARODD
Configures DEPTH of the FIFO to 2 (LGDEP+1)
IN
Selects odd parity generation/detect when high, even when low
46
Advanced v0.6
ProASICPLUS Family Flash FPGAs
FULL
RB
Write
cycle
Write inhibited
Write accepted
1ns
3ns
WB
Figure 21 • Write Timing Diagram
EMPTY
WB
Read
cycle
Read inhibited
Read accepted
1ns
3ns
RB
Figure 22 • Read Timing Diagram
Advanced v0.6
47
ProASICPLUS Family Flash FPGAs
Asynchronous FIFO Read
Cycle Start
RB=(RDB+RBLKB)
RDATA
(Empty inhibits read)
RPE
WB
EMPTY
FULL
EQTH, GETH
t
t
t
, t
RDWRS
ERDH FRDH
t
, t
ORDH
ERDA FRDA
t
t
RPRDH
THRDH
t
t
ORDA
THRDA
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
ERDH,
FRDH,
THRDH
Old EMPTY, FULL, EQTH, & GETH valid
hold time from RB ↑
0.5
ns
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
ERDA
New EMPTY access from RB ↑
FULL↓ access from RB ↑
New DO access from RB ↓
Old DO valid from RB ↓
Read cycle time
3.01
3.01
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FRDA
ORDA
ORDH
RDCYC
RDWRS
3.0
1.0
7.5
3.02
WB ↑, clearing EMPTY, setup to
RB ↓
Enabling the read operation
Inhibiting the read operation
Inactive
RDH
RB high phase
3.0
3.0
9.5
RDL
RB low phase
Active
RPRDA
RPRDH
THRDA
Notes:
New RPE access from RB ↓
Old RPE valid from RB ↓
EQTH or GETH access from RB↑
4.0
4.5
1. At fast cycles, ERDA & FRDA = MAX (7.5 ns – RDL), 3.0 ns
2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns
48
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Asynchronous FIFO Write
Cycle Start
WB=(WRB+WBLKB)
WDATA
(Full inhibits write)
WPE
RB
FULL
EMPTY
EQTH, GETH
t
t
WRRDS
DWRH
t
t
t
WPDH
WPDA
DWRS
t
, t
EWRH FWRH
t
, t
EWRA FWRA
t
THWRH
t
THWRA
t
t
WRL
WRH
t
WRCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
DWRH
DWRS
DWRS
DI hold from WB ↑
DI setup to WB ↑
DI setup to WB ↑
1.5
0.5
2.5
ns
ns
ns
ns
PARGEN is inactive
PARGEN is active
EWRH,
FWRH,
THWRH
Old EMPTY, FULL, EQTH, & GETH valid
hold time after WB ↑
0.5
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
EWRA
EMPTY ↓ access from WB ↑
New FULL access from WB ↑
EQTH or GETH access from WB ↑
WPE access from DI
WPE hold from DI
3.01
3.01
4.5
ns
ns
ns
ns
ns
ns
ns
FWRA
THWRA
WPDA
3.0
WPE is invalid while
PARGEN is active
WPDH
WRCYC
WRRDS
1.0
1.0
Cycle time
7.5
3.02
RB ↑, clearing FULL, setup to
WB ↓
Enabling the write operation
Inhibiting the write operation
Inactive
WRH
WRL
Notes:
WB high phase
3.0
3.0
ns
ns
WB low phase
Active
1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns
2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns
Advanced v0.6
49
ProASICPLUS Family Flash FPGAs
Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
RCLK
RDB
Cycle Start
RDATA
RPE
Old Data Out
New Valid Data Out (Empty Inhibits Read)
EMPTY
FULL
EQTH, GETH
t
t
t
, t
RDCH
ECBH FCBH
, t
t
ECBA FCBA
RDCS
t
t
THCBH
t
OCH
t
RPCH
HCBA
t
OCA
t
RPCA
t
t
CMH
CML
t
CCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
Clock high phase
Clock low phase
CML
3.0
ECBA
FCBA
New EMPTY access from RCLKS ↓
FULL ↓ access from RCLKS ↓
3.01
3.01
ECBH,
FCBH,
THCBH
Old EMPTY, FULL, EQTH, & GETH valid
hold time from RCLKS ↓
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
1.0
3.0
ns
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
7.5
ns
ns
ns
ns
ns
ns
ns
OCH
RDCH
RDCS
RPCA
RPCH
HCBA
Note:
0.5
1.0
9.5
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
EQTH or GETH access from RCLKS ↓
3.0
4.5
1. At fast cycles, ECBA & FCBA = MAX (7.5 ns – CMH), 3.0 ns
50
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
RCLK
Cycle Start
RDB
RDATA
RPE
Old Data Out
New Valid Data Out
New RPE Out
Old RPE Out
EMPTY
FULL
EQTH, GETH
t
, t
t
ECBH FCBH
OCA
t
t
t
t
, t
RDCH
ECBA FCBA
t
t
RDCS
THCBH
t
RPCH
OCH
HCBA
t
RPCA
t
t
CML
CMH
t
CCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CCYC
CMH
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
Clock high phase
CML
Clock low phase
3.0
ECBA
FCBA
New EMPTY access from RCLKS ↓
FULL ↓ access from RCLKS ↓
3.01
3.01
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid
1.0
ns
THCBH
hold time from RCLKS ↓
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
2.0
ns
ns
ns
ns
ns
ns
ns
OCH
0.75
RDCH
RDCS
RPCA
RPCH
HCBA
Note:
0.5
1.0
4.0
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
EQTH or GETH access from RCLKS ↓
1.0
4.5
1. At fast cycles, ECBA & FCBA = MAX (7.5 ns – CMS), 3.0 ns
Advanced v0.6
51
ProASICPLUS Family Flash FPGAs
Synchronous FIFO Write
WCLKS
Cycle Start
WRB, WBLKB
(Full Inhibits Write)
DI
WPE
FULL
EMPTY
EQTH, GETH
t
, t
WRCH WBCH
t
t
, t
ECBH FCBH
, t
t
, t
ECBA FCBA
WRCS WBCS
t
t
DCS
HCBH
t
t
HCBA
WPCH
t
DCH
t
WPCA
t
t
CML
CMH
t
CCYC
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
CMH
CML
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
Clock low phase
3.0
DCH
DI hold from WCLKS ↑
DI setup to WCLKS ↑
New FULL access from WCLKS ↓
EMPTY↓ access from WCLKS ↓
Old EMPTY, FULL, EQTH, & GETH valid
hold time from WCLKS ↓
0.5
DCS
1.0
FCBA
ECBA
3.01
3.01
ECBH,
FCBH,
THCBH
1.0
0.5
Empty/full/thresh are invalid
from the end of hold until the
new access is complete
HCBA
WPCA
WPCH
EQTH or GETH access from WCLKS ↓
New WPE access from WCLKS ↑
Old WPE valid from WCLKS ↑
4.5
3.0
ns
ns
ns
ns
WPE is invalid while
PARGEN is active
WRCH,
WBCH
WRB & WBLKB hold from WCLKS ↑
0.5
1.0
WRCS,
WBCS
Note:
WRB & WBLKB setup to WCLKS ↑
ns
1. At fast cycles, ECBA & FCBA = MAX (7.5 ns – CMH), 3.0 ns
52
Advanced v0.6
ProASICPLUS Family Flash FPGAs
FIFO Reset
RESETB
Cycle Start
WB*
WCLKS, RCLKS
FULL
Cycle Start
EMPTY
EQTH, GETH
t
CBRSS
t
, t
t
ERSA FRSA
CBRSH
t
WBRSH
t
THRSA
t
RSL
t
WBRSS
Note: The plot shows the normal operation status.
TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description
Min.
Max.
Units
Notes
CBRSH
CBRSS
ERSA
WCLKS or RCLKS ↑ hold from RESETB ↑
1.5
1.5
3.0
3.0
7.5
4.5
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
ns
Synchronous mode only
Synchronous mode only
WCLKS or RCLKS ↓ setup to RESETB ↑
New EMPTY ↑ access from RESETB ↓
FULL ↓ access from RESETB ↓
RESETB low phase
FRSA
RSL
THRSA
WBRSH
WBRSS
EQTH or GETH access from RESETB ↓
WB ↓ hold from RESETB ↑
Asynchronous mode only
Asynchronous mode only
WB ↑ setup to RESETB ↑
Advanced v0.6
53
ProASICPLUS Family Flash FPGAs
Programming Supply Pin
Pin Description
I/O
User Input/Output
VPN
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with standard LVTTL and LVCMOS
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
This pin may be connected to any voltage between GND and
13.8V during normal operation, or it can be left
unconnected. For information on using this pin during
programming, see the Performing Internal In-System
Programming Using Actel’s ProASICPLUS Devices
application note.
NC
No Connect
TMS
Test Mode Select
To maintain compatibility with other Actel ProASIC
products it is recommended that this pin not be connected
to the circuitry on the board.
The TMS pin controls the use of boundary-scan circuitry.
TCK
Test Clock
GL
Global Input Pin
Clock input pin for boundary scan.
Low skew input pin for clock or other global signals. Input
only. This pin can be configured with a pull-up resistor.
TDI
Test Data In
Serial input for boundary scan.
GND
Ground
TDO
Test Data Out
Common ground supply voltage.
Serial output for boundary scan.
VDD
Logic Array Power Supply Pin
TRST
Test Reset Input
2.5V supply voltage.
Asynchronous,
boundary-scan circuitry.
active low input pin for resetting
VDDP
I/O Pad Power Supply Pin
2.5V or 3.3V supply voltage.
RCK
Running Clock
VPP
Programming Supply Pin
A free running clock is needed during programming if the
programmer cannot guarantee that TCK will be
uninterrupted.
This pin may be connected to any voltage between GND and
16.5V during normal operation, or it can be left
unconnected. For information on using this pin during
programming, see the Performing Internal In-System
Programming Using Actel’s ProASICPLUS Devices
application note.
NPECL
PECL Negative Input
Provides high speed clock or data signals to the PLL block.
If unused, leave the pin unconnected.
PPECL
PECL Positive input
Provides high speed clock or data signals to the PLL block.
If unused, leave the pin unconnected.
AVDD
AGND
PLL Power Supply
PLL Power Ground
54
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Package Pin Assignments
208-Pin PQFP
208
1
208-Pin PQFP
Advanced v0.6
55
ProASICPLUS Family Flash FPGAs
208-Pin PQFP
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
1
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
2
3
I/O
I/O
I/O
I/O
I/O
I/O
4
I/O
I/O
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
GND
I/O
VDD
GND
I/O
VDD
GND
I/O
VDD
GND
I/O
VDD
GND
I/O
VDD
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
GL
GL
GL
GL
GL
GL
AGND
NPECL
AVDD
PPECL
GND
GL
AGND
NPECL
AVDD
PPECL
GND
GL
AGND
NPECL
AVDD
PPECL
GND
GL
AGND
NPECL
AVDD
PPECL
GND
GL
AGND
NPECL
AVDD
PPECL
GND
GL
AGND
NPECL
AVDD
PPECL
GND
GL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
VDD
I/O
VDD
I/O
VDD
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
56
Advanced v0.6
ProASICPLUS Family Flash FPGAs
208-Pin PQFP (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VDDP
GND
I/O
VDDP
GND
I/O
VDDP
GND
I/O
VDDP
GND
I/O
VDDP
GND
I/O
VDDP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
57
ProASICPLUS Family Flash FPGAs
208-Pin PQFP (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
79
80
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
81
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
82
83
I/O
I/O
I/O
I/O
I/O
I/O
84
I/O
I/O
I/O
I/O
I/O
I/O
85
I/O
I/O
I/O
I/O
I/O
I/O
86
I/O
I/O
I/O
I/O
I/O
I/O
87
I/O
I/O
I/O
I/O
I/O
I/O
88
VDD
VDDP
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
VDD
VDDP
I/O
89
90
91
I/O
I/O
I/O
I/O
I/O
I/O
92
I/O
I/O
I/O
I/O
I/O
I/O
93
I/O
I/O
I/O
I/O
I/O
I/O
94
I/O
I/O
I/O
I/O
I/O
I/O
95
I/O
I/O
I/O
I/O
I/O
I/O
96
I/O
I/O
I/O
I/O
I/O
I/O
97
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
98
99
I/O
I/O
I/O
I/O
I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
I/O
I/O
I/O
I/O
I/O
I/O
TCK
TDI
TMS
VDDP
GND
VPP
VPN
TDO
TRST
RCK
I/O
TCK
TDI
TMS
VDDP
GND
VPP
VPN
TDO
TRST
RCK
I/O
TCK
TDI
TMS
VDDP
GND
VPP
VPN
TDO
TRST
RCK
I/O
TCK
TDI
TMS
VDDP
GND
VPP
VPN
TDO
TRST
RCK
I/O
TCK
TDI
TMS
VDDP
GND
VPP
VPN
TDO
TRST
RCK
I/O
TCK
TDI
TMS
VDDP
GND
VPP
VPN
TDO
TRST
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
58
Advanced v0.6
ProASICPLUS Family Flash FPGAs
208-Pin PQFP (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
GND
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
VDD
I/O
VDD
I/O
VDD
I/O
VDD
I/O
GL
GL
GL
GL
GL
GL
PPECL
GND
AVDD
NPECL
AGND
GL
PPECL
GND
AVDD
NPECL
AGND
GL
PPECL
GND
AVDD
NPECL
AGND
GL
PPECL
GND
AVDD
NPECL
AGND
GL
PPECL
GND
AVDD
NPECL
AGND
GL
PPECL
GND
AVDD
NPECL
AGND
GL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VDD
I/O
GND
VDD
I/O
GND
VDD
I/O
GND
VDD
I/O
GND
VDD
I/O
GND
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
Advanced v0.6
59
ProASICPLUS Family Flash FPGAs
208-Pin PQFP (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
VDDP
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
60
Advanced v0.6
ProASICPLUS Family Flash FPGAs
208-Pin PQFP (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
196
197
198
199
200
201
202
203
204
205
206
207
208
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
Advanced v0.6
61
ProASICPLUS Family Flash FPGAs
Package Pin Assignments (Continued)
456-Pin PBGA (Bottom View)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
62
Advanced v0.6
ProASICPLUS Family Flash FPGAs
456-Pin PBGA
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
A1
A2
VDDP
VDDP
NC
NC
NC
NC
NC
I/O
VDDP
VDDP
NC
NC
NC
NC
NC
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
A3
A4
I/O
I/O
I/O
I/O
A5
I/O
I/O
I/O
I/O
A6
I/O
I/O
I/O
I/O
A7
I/O
I/O
I/O
I/O
A8
I/O
I/O
I/O
I/O
A9
I/O
I/O
I/O
I/O
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
VDDP
VDDP
VDDP
VDDP
NC
NC
NC
NC
NC
I/O
NC
NC
NC
NC
NC
VDDP
VDDP
VDDP
VDDP
NC
NC
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
VDDP
VDDP
NC
I/O
VDDP
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
VDDP
I/O
B2
B3
B4
I/O
I/O
I/O
B5
I/O
I/O
I/O
I/O
B6
I/O
I/O
I/O
I/O
B7
I/O
I/O
I/O
I/O
B8
I/O
I/O
I/O
I/O
B9
I/O
I/O
I/O
I/O
I/O
I/O
B10
B11
B12
B13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
63
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
VDDP
VDDP
VDDP
NC
VDDP
NC
NC
NC
I/O
NC
NC
NC
NC
NC
VDDP
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
C2
C3
VDDP
NC
NC
NC
I/O
VDDP
NC
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
C4
C5
I/O
I/O
I/O
C6
I/O
I/O
I/O
I/O
C7
I/O
I/O
I/O
I/O
C8
I/O
I/O
I/O
I/O
I/O
I/O
C9
I/O
I/O
I/O
I/O
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
VDDP
NC
NC
NC
NC
NC
VDDP
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
NC
NC
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
64
Advanced v0.6
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
D1
D2
NC
NC
NC
VDDP
NC
NC
I/O
NC
NC
I/O
NC
NC
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
NC
NC
I/O
I/O
I/O
I/O
VDD
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
D3
D4
VDDP
NC
NC
I/O
D5
D6
D7
D8
I/O
I/O
D9
I/O
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
VDDP
NC
NC
NC
NC
NC
NC
NC
VDD
VDD
VDD
VDD
I/O
NC
VDDP
I/O
NC
NC
I/O
E2
I/O
E3
I/O
E4
I/O
E5
VDD
VDD
VDD
VDD
I/O
E6
E7
E8
E9
E10
E11
E12
E13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
65
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
VDD
VDD
VDD
NC
NC
NC
NC
NC
NC
NC
NC
VDD
VDD
NC
NC
NC
NC
I/O
F2
F3
F4
F5
F22
F23
F24
F25
F26
G1
G2
I/O
G3
NC
NC
VDD
VDD
NC
NC
NC
I/O
G4
G5
G22
G23
G24
G25
G26
H1
I/O
H2
I/O
H3
I/O
H4
I/O
H5
VDD
VDD
H22
66
Advanced v0.6
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
H23
H24
H25
H26
J1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J2
I/O
I/O
I/O
I/O
I/O
I/O
J3
I/O
I/O
I/O
I/O
I/O
I/O
J4
I/O
I/O
I/O
I/O
I/O
I/O
J5
I/O
I/O
I/O
I/O
I/O
I/O
J22
J23
J24
J25
J26
K1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K2
I/O
I/O
I/O
I/O
I/O
I/O
K3
I/O
I/O
I/O
I/O
I/O
I/O
K4
I/O
I/O
I/O
I/O
I/O
I/O
K5
I/O
I/O
I/O
I/O
I/O
I/O
K22
K23
K24
K25
K26
L1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L2
I/O
I/O
I/O
I/O
I/O
I/O
L3
I/O
I/O
I/O
I/O
I/O
I/O
L4
I/O
I/O
I/O
I/O
I/O
I/O
L5
I/O
I/O
I/O
I/O
I/O
I/O
L11
L12
L13
L14
L15
L16
L22
L23
L24
L25
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
67
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
L26
M1
I/O
GL
I/O
GL
I/O
GL
I/O
GL
I/O
GL
I/O
GL
M2
GL
GL
GL
GL
GL
GL
M3
I/O
I/O
I/O
I/O
I/O
I/O
M4
I/O
I/O
I/O
I/O
I/O
I/O
M5
I/O
I/O
I/O
I/O
I/O
I/O
M11
M12
M13
M14
M15
M16
M22
M23
M24
M25
M26
N1
GND
GND
GND
GND
GND
GND
GL
GND
GND
GND
GND
GND
GND
GL
GND
GND
GND
GND
GND
GND
GL
GND
GND
GND
GND
GND
GND
GL
GND
GND
GND
GND
GND
GND
GL
GND
GND
GND
GND
GND
GND
GL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N2
I/O
I/O
I/O
I/O
I/O
I/O
N3
AGND
PPECL
AVDD
GND
GND
GND
GND
GND
GND
NPECL
GL
AGND
PPECL
AVDD
GND
GND
GND
GND
GND
GND
NPECL
GL
AGND
PPECL
AVDD
GND
GND
GND
GND
GND
GND
NPECL
GL
AGND
PPECL
AVDD
GND
GND
GND
GND
GND
GND
NPECL
GL
AGND
PPECL
AVDD
GND
GND
GND
GND
GND
GND
NPECL
GL
AGND
PPECL
AVDD
GND
GND
GND
GND
GND
GND
NPECL
GL
N4
N5
N11
N12
N13
N14
N15
N16
N22
N23
N24
N25
N26
P1
AVDD
I/O
AVDD
I/O
AVDD
I/O
AVDD
I/O
AVDD
I/O
AVDD
I/O
AGND
I/O
AGND
I/O
AGND
I/O
AGND
I/O
AGND
I/O
AGND
I/O
P2
I/O
I/O
I/O
I/O
I/O
I/O
P3
I/O
I/O
I/O
I/O
I/O
I/O
P4
I/O
I/O
I/O
I/O
I/O
I/O
P5
NPECL
GND
NPECL
GND
NPECL
GND
NPECL
GND
NPECL
GND
NPECL
GND
P11
68
Advanced v0.6
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
P12
P13
P14
P15
P16
P22
P23
P24
P25
P26
R1
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PPECL
I/O
PPECL
I/O
PPECL
I/O
PPECL
I/O
PPECL
I/O
PPECL
I/O
R2
I/O
I/O
I/O
I/O
I/O
I/O
R3
I/O
I/O
I/O
I/O
I/O
I/O
R4
I/O
I/O
I/O
I/O
I/O
I/O
R5
I/O
I/O
I/O
I/O
I/O
I/O
R11
R12
R13
R14
R15
R16
R22
R23
R24
R25
R26
T1
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T2
I/O
I/O
I/O
I/O
I/O
I/O
T3
I/O
I/O
I/O
I/O
I/O
I/O
T4
I/O
I/O
I/O
I/O
I/O
I/O
T5
I/O
I/O
I/O
I/O
I/O
I/O
T11
T12
T13
T14
T15
T16
T22
T23
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
69
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
T24
T25
T26
U1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
U2
U3
U4
U5
U22
U23
U24
U25
U26
V1
V2
V3
V4
V5
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W22
W23
W24
W25
W26
Y1
Y2
Y3
Y4
Y5
Y22
70
Advanced v0.6
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
Y23
Y24
NC
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
I/O
I/O
I/O
Y25
Y26
AA1
AA2
NC
NC
NC
VDD
VDD
NC
NC
NC
NC
NC
NC
NC
NC
VDD
VDD
VDD
I/O
AA3
AA4
AA5
AA22
AA23
AA24
AA25
AA26
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
I/O
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
VDD
VDD
NC
NC
NC
Advanced v0.6
71
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
AB26
AC1
NC
NC
NC
NC
VDDP
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AC2
I/O
I/O
I/O
I/O
I/O
AC3
I/O
I/O
I/O
I/O
I/O
AC4
VDDP
NC
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
AC5
AC6
I/O
I/O
I/O
I/O
AC7
I/O
I/O
I/O
I/O
I/O
I/O
AC8
I/O
I/O
I/O
I/O
I/O
I/O
AC9
I/O
I/O
I/O
I/O
I/O
I/O
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
TDO
VDDP
RCK
NC
NC
NC
NC
VDDP
NC
NC
NC
I/O
TMS
TDO
VDDP
RCK
NC
I/O
TMS
TDO
VDDP
RCK
I/O
TMS
TDO
VDDP
RCK
I/O
TMS
TDO
VDDP
RCK
I/O
TMS
TDO
VDDP
RCK
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
AD2
I/O
I/O
I/O
AD3
VDDP
NC
NC
NC
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
AD4
AD5
I/O
I/O
I/O
I/O
AD6
I/O
I/O
I/O
I/O
AD7
I/O
I/O
I/O
I/O
AD8
I/O
I/O
I/O
I/O
I/O
I/O
AD9
I/O
I/O
I/O
I/O
I/O
I/O
AD10
AD11
AD12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
72
Advanced v0.6
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
TCK
VPP
NC
VDDP
NC
NC
VDDP
VDDP
NC
NC
NC
NC
NC
I/O
NC
TCK
VPP
NC
VDDP
NC
NC
VDDP
VDDP
NC
NC
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
TCK
VPP
NC
VDDP
I/O
TCK
VPP
I/O
TCK
VPP
I/O
TCK
VPP
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
AE2
AE3
AE4
I/O
I/O
I/O
I/O
AE5
I/O
I/O
I/O
I/O
AE6
I/O
I/O
I/O
I/O
AE7
I/O
I/O
I/O
I/O
AE8
I/O
I/O
I/O
I/O
AE9
I/O
I/O
I/O
I/O
I/O
I/O
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
VPN
TRST
VDDP
NC
NC
NC
VPN
TRST
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VPN
TRST
VDDP
VPN
TRST
VDDP
VPN
TRST
VDDP
VPN
TRST
VDDP
Advanced v0.6
73
ProASICPLUS Family Flash FPGAs
456-Pin PBGA (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
APA600
Function
APA750
Function
APA1000
Function
AE26
AF1
VDDP
VDDP
VDDP
NC
NC
NC
NC
NC
NC
I/O
VDDP
VDDP
VDDP
NC
NC
NC
NC
NC
NC
I/O
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
VDDP
VDDP
VDDP
I/O
AF2
AF3
AF4
I/O
I/O
I/O
I/O
AF5
I/O
I/O
I/O
I/O
AF6
I/O
I/O
I/O
I/O
AF7
I/O
I/O
I/O
I/O
AF8
NC
I/O
I/O
I/O
I/O
AF9
I/O
I/O
I/O
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
TDI
NC
VDDP
VDDP
NC
NC
NC
NC
NC
TDI
NC
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
TDI
I/O
TDI
I/O
TDI
I/O
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
74
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Package Assignments (Continued)
144-FBGA (Bottom View)
2
12 11 10
9
8
7
6
5
4
3
1
A
B
C
D
E
F
G
H
J
K
L
M
Advanced v0.6
75
ProASICPLUS Family Flash FPGAs
144-FBGA Pin
144-FBGA Pin (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
Pin
Number
APA150
Function
APA300
Function
APA450
Function
A1
A2
I/O
I/O
I/O
I/O
I/O
GND
I/O
VDD
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
GL
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VDD
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
GL
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VDD
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
GL
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
I/O
I/O
I/O
I/O
I/O
I/O
A3
I/O
I/O
I/O
A4
I/O
I/O
I/O
A5
I/O
I/O
I/O
A6
I/O
I/O
I/O
A7
I/O
I/O
I/O
A8
I/O
I/O
I/O
A9
I/O
I/O
I/O
A10
A11
A12
B1
VDD
I/O
VDD
VDD
E2
I/O
I/O
E3
I/O
I/O
I/O
E4
VDDP
I/O
VDDP
I/O
VDDP
I/O
B2
E5
B3
E6
VDDP
VDDP
AVDD
VDDP
VDD
NPECL
AGND
GL
VDDP
VDDP
AVDD
VDDP
VDD
VDDP
VDDP
AVDD
VDDP
VDD
B4
E7
B5
E8
B6
E9
B7
E10
E11
E12
F1
B8
NPECL
AGND
GL
NPECL
AGND
GL
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
F2
AGND
I/O
AGND
I/O
AGND
I/O
F3
F4
I/O
I/O
I/O
F5
GND
GND
GND
I/O
GND
GND
GND
I/O
GND
GND
GND
I/O
F6
F7
F8
F9
GL
GL
GL
F10
F11
F12
G1
G2
G3
G4
G5
G6
GND
PPECL
GL
GND
PPECL
GL
GND
PPECL
GL
PPECL
GND
AVDD
NPECL
GND
GND
PPECL
GND
AVDD
NPECL
GND
GND
PPECL
GND
AVDD
NPECL
GND
GND
76
Advanced v0.6
ProASICPLUS Family Flash FPGAs
144-FBGA Pin (Continued)
144-FBGA Pin (Continued)
Pin
Number
APA150
Function
APA300
Function
APA450
Function
Pin
Number
APA150
Function
APA300
Function
APA450
Function
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
GND
I/O
GND
I/O
GND
I/O
K10
K11
K12
L1
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
L2
I/O
I/O
I/O
L3
I/O
I/O
I/O
VDD
I/O
VDD
I/O
VDD
I/O
L4
I/O
I/O
I/O
L5
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
L6
I/O
I/O
I/O
L7
I/O
I/O
I/O
VDD
I/O
VDD
I/O
VDD
I/O
L8
I/O
I/O
I/O
L9
TMS
RCK
I/O
TMS
RCK
I/O
TMS
RCK
I/O
I/O
I/O
I/O
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
I/O
I/O
I/O
I/O
I/O
I/O
TRST
I/O
TRST
I/O
TRST
I/O
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J2
I/O
I/O
I/O
I/O
I/O
I/O
J3
VDDP
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
J4
I/O
I/O
I/O
J5
I/O
I/O
I/O
I/O
I/O
I/O
J6
I/O
I/O
I/O
TDI
VDDP
VPP
VPN
TDI
VDDP
VPP
VPN
TDI
VDDP
VPP
VPN
J7
VDD
TCK
I/O
VDD
TCK
I/O
VDD
TCK
I/O
J8
J9
J10
J11
J12
K1
TDO
I/O
TDO
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K2
I/O
I/O
I/O
K3
I/O
I/O
I/O
K4
I/O
I/O
I/O
K5
I/O
I/O
I/O
K6
I/O
I/O
I/O
K7
GND
I/O
GND
I/O
GND
I/O
K8
K9
I/O
I/O
I/O
Advanced v0.6
77
ProASICPLUS Family Flash FPGAs
Package Assignments (Continued)
256-FBGA (Bottom View)
Pin one corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
78
Advanced v0.6
ProASICPLUS Family Flash FPGAs
256-Pin FBGA
APA150
Function
APA300
Function
APA450
Function
APA600
Function
Pin Number
A1
A2
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
C1
C2
C3
C4
C5
C6
C7
Advanced v0.6
79
ProASICPLUS Family Flash FPGAs
256-Pin FBGA (Continued)
APA150
Function
APA300
Function
APA450
Function
APA600
Function
Pin Number
C8
C9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
I/O
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
I/O
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
I/O
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
I/O
VDDP
VDDP
I/O
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
80
Advanced v0.6
ProASICPLUS Family Flash FPGAs
256-Pin FBGA (Continued)
APA150
Function
APA300
Function
APA450
Function
APA600
Function
Pin Number
E15
E16
F1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
F2
I/O
I/O
I/O
I/O
F3
I/O
I/O
I/O
I/O
F4
I/O
I/O
I/O
I/O
F5
VDDP
GND
VDD
VDD
VDD
VDD
GND
VDDP
I/O
VDDP
GND
VDD
VDD
VDD
VDD
GND
VDDP
I/O
VDDP
GND
VDD
VDD
VDD
VDD
GND
VDDP
I/O
VDDP
GND
VDD
VDD
VDD
VDD
GND
VDDP
I/O
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
G1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G2
I/O
I/O
I/O
I/O
G3
I/O
I/O
I/O
I/O
G4
I/O
I/O
I/O
I/O
G5
VDDP
VDD
GND
GND
GND
GND
VDD
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
VDD
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
VDD
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
VDD
VDDP
I/O
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
H1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GL
GL
GL
GL
H2
NPECL
I/O
NPECL
I/O
NPECL
I/O
NPECL
I/O
H3
H4
AGND
I/O
AGND
I/O
AGND
I/O
AGND
I/O
H5
Advanced v0.6
81
ProASICPLUS Family Flash FPGAs
256-Pin FBGA (Continued)
APA150
Function
APA300
Function
APA450
Function
APA600
Function
Pin Number
H6
H7
VDD
GND
GND
GND
GND
VDD
I/O
VDD
GND
GND
GND
GND
VDD
VDD
GND
GND
GND
GND
VDD
VDD
GND
GND
GND
GND
VDD
H8
H9
H10
H11
H12
H13
H14
H15
H16
J1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NPECL
AGND
GL
NPECL
AGND
GL
NPECL
AGND
GL
NPECL
AGND
GL
GL
GL
GL
GL
J2
PPECL
AVDD
I/O
PPECL
AVDD
I/O
PPECL
AVDD
I/O
PPECL
AVDD
I/O
J3
J4
J5
I/O
I/O
I/O
I/O
J6
VDD
GND
GND
GND
GND
VDD
I/O
VDD
VDD
VDD
J7
GND
GND
GND
GND
VDD
GND
GND
GND
GND
VDD
GND
GND
GND
GND
VDD
J8
J9
J10
J11
J12
J13
J14
J15
J16
K1
I/O
I/O
I/O
PPECL
I/O
PPECL
I/O
PPECL
I/O
PPECL
I/O
AVDD
GL
AVDD
GL
AVDD
GL
AVDD
GL
I/O
I/O
I/O
I/O
K2
I/O
I/O
I/O
I/O
K3
I/O
I/O
I/O
I/O
K4
I/O
I/O
I/O
I/O
K5
VDDP
VDD
GND
GND
GND
GND
VDD
VDDP
VDDP
VDD
VDDP
VDD
VDDP
VDD
K6
K7
GND
GND
GND
GND
VDD
GND
GND
GND
GND
VDD
GND
GND
GND
GND
VDD
K8
K9
K10
K11
K12
VDDP
VDDP
VDDP
82
Advanced v0.6
ProASICPLUS Family Flash FPGAs
256-Pin FBGA (Continued)
APA150
Function
APA300
Function
APA450
Function
APA600
Function
Pin Number
K13
K14
K15
K16
L1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L2
I/O
I/O
I/O
I/O
L3
I/O
I/O
I/O
I/O
L4
I/O
I/O
I/O
I/O
L5
VDDP
GND
VDD
VDD
VDD
VDD
GND
VDDP
I/O
VDDP
GND
VDD
VDD
VDD
VDD
GND
VDDP
I/O
VDDP
GND
VDD
VDD
VDD
VDD
GND
VDDP
I/O
VDDP
GND
VDD
VDD
VDD
VDD
GND
VDDP
I/O
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
VDDP
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N2
I/O
I/O
I/O
I/O
N3
I/O
I/O
I/O
I/O
Advanced v0.6
83
ProASICPLUS Family Flash FPGAs
256-Pin FBGA (Continued)
APA150
Function
APA300
Function
APA450
Function
APA600
Function
Pin Number
N4
N5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
VPP
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
84
Advanced v0.6
ProASICPLUS Family Flash FPGAs
256-Pin FBGA (Continued)
APA150
Function
APA300
Function
APA450
Function
APA600
Function
Pin Number
R11
R12
R13
R14
R15
R16
T1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
VPN
TDO
GND
I/O
TDI
VPN
TDO
GND
I/O
TDI
VPN
TDO
GND
I/O
TDI
VPN
TDO
GND
I/O
T2
T3
I/O
I/O
I/O
I/O
T4
I/O
I/O
I/O
I/O
T5
I/O
I/O
I/O
I/O
T6
I/O
I/O
I/O
I/O
T7
I/O
I/O
I/O
I/O
T8
I/O
I/O
I/O
I/O
T9
I/O
I/O
I/O
I/O
T10
T11
T12
T13
T14
T15
T16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
GND
TMS
GND
TMS
GND
TMS
GND
Advanced v0.6
85
ProASICPLUS Family Flash FPGAs
Package Pin Assignments (Continued)
676-Pin FBGA (Bottom View)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
86
Advanced v0.6
ProASICPLUS Family Flash FPGAs
676-FBGA Pin
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
A1
A2
GND
GND
I/O
GND
GND
I/O
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
I/O
I/O
I/O
I/O
A3
I/O
I/O
A4
I/O
I/O
I/O
I/O
A5
I/O
I/O
I/O
I/O
A6
I/O
I/O
I/O
I/O
A7
I/O
I/O
I/O
I/O
A8
I/O
I/O
I/O
I/O
A9
I/O
I/O
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C2
I/O
I/O
C3
I/O
I/O
C4
I/O
I/O
C5
I/O
I/O
C6
I/O
I/O
I/O
I/O
C7
I/O
I/O
I/O
I/O
C8
I/O
I/O
I/O
I/O
C9
I/O
I/O
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B2
I/O
I/O
B3
I/O
I/O
B4
I/O
I/O
B5
I/O
I/O
B6
I/O
I/O
I/O
I/O
B7
I/O
I/O
I/O
I/O
B8
I/O
I/O
I/O
I/O
B9
I/O
I/O
I/O
I/O
B10
B11
B12
B13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
87
ProASICPLUS Family Flash FPGAs
676-FBGA Pin (Continued)
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
D1
D2
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
88
Advanced v0.6
ProASICPLUS Family Flash FPGAs
676-FBGA Pin (Continued)
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
G1
G2
I/O
I/O
I/O
I/O
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
J1
VDDP
VDDP
VDDP
VDDP
VDDP
VDD
VDD
I/O
VDDP
VDDP
VDDP
VDDP
VDDP
VDD
VDD
I/O
G3
I/O
I/O
G4
I/O
I/O
G5
I/O
I/O
G6
I/O
I/O
G7
I/O
I/O
G8
VDD
NC
I/O
VDD
NC
I/O
G9
I/O
I/O
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
H1
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
J2
I/O
I/O
J3
I/O
I/O
NC
I/O
NC
I/O
J4
I/O
I/O
J5
I/O
I/O
VDDP
NC
I/O
VDDP
NC
I/O
J6
I/O
I/O
J7
NC
NC
J8
VDDP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDP
NC
VDDP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDP
NC
I/O
I/O
J9
I/O
I/O
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H2
I/O
I/O
H3
I/O
I/O
H4
I/O
I/O
H5
I/O
I/O
H6
I/O
I/O
H7
VDDP
VDD
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDD
VDDP
VDDP
VDDP
VDDP
VDDP
H8
I/O
I/O
H9
I/O
I/O
H10
H11
H12
H13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
89
ProASICPLUS Family Flash FPGAs
676-FBGA Pin (Continued)
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
K1
K2
I/O
I/O
I/O
I/O
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
M1
GND
GND
GND
GND
VDD
VDDP
NC
GND
GND
GND
GND
VDD
VDDP
NC
K3
I/O
I/O
K4
I/O
I/O
K5
I/O
I/O
K6
I/O
I/O
K7
I/O
I/O
K8
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
I/O
K9
I/O
I/O
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
L1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M2
I/O
I/O
M3
I/O
I/O
M4
I/O
I/O
M5
I/O
I/O
M6
I/O
I/O
M7
I/O
I/O
I/O
I/O
M8
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
I/O
M9
I/O
I/O
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L2
I/O
I/O
L3
I/O
I/O
L4
I/O
I/O
L5
I/O
I/O
L6
I/O
I/O
L7
NC
NC
L8
VDDP
VDD
GND
GND
GND
GND
VDDP
VDD
GND
GND
GND
GND
I/O
I/O
L9
I/O
I/O
L10
L11
L12
L13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
90
Advanced v0.6
ProASICPLUS Family Flash FPGAs
676-FBGA Pin (Continued)
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
N1
N2
GL
AGND
I/O
GL
AGND
I/O
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
R1
GND
GND
GND
GND
VDD
VDDP
I/O
GND
GND
GND
GND
VDD
VDDP
I/O
N3
N4
I/O
I/O
N5
NPECL
I/O
NPECL
I/O
N6
N7
NC
NC
N8
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
I/O
I/O
N9
I/O
I/O
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
P1
I/O
I/O
PPECL
AVDD
AGND
I/O
PPECL
AVDD
AGND
I/O
R2
I/O
I/O
R3
I/O
I/O
R4
I/O
I/O
R5
I/O
I/O
R6
I/O
I/O
R7
NC
NC
I/O
I/O
R8
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
GL
GL
R9
I/O
I/O
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
NPECL
GL
NPECL
GL
I/O
I/O
GL
GL
P2
AVDD
I/O
AVDD
I/O
P3
P4
I/O
I/O
P5
PPECL
I/O
PPECL
I/O
P6
P7
I/O
I/O
P8
VDDP
VDD
GND
GND
GND
GND
VDDP
VDD
GND
GND
GND
GND
I/O
I/O
P9
I/O
I/O
P10
P11
P12
P13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
91
ProASICPLUS Family Flash FPGAs
676-FBGA Pin (Continued)
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
T1
T2
I/O
I/O
I/O
I/O
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V1
GND
GND
GND
GND
VDD
VDDP
NC
GND
GND
GND
GND
VDD
VDDP
NC
T3
I/O
I/O
T4
I/O
I/O
T5
I/O
I/O
T6
I/O
I/O
T7
I/O
I/O
T8
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
I/O
T9
I/O
I/O
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
U1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V2
I/O
I/O
V3
I/O
I/O
V4
I/O
I/O
V5
I/O
I/O
V6
I/O
I/O
V7
I/O
I/O
I/O
I/O
V8
VDDP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDP
I/O
VDDP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDP
I/O
I/O
I/O
V9
I/O
I/O
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U2
I/O
I/O
U3
I/O
I/O
U4
I/O
I/O
U5
I/O
I/O
U6
I/O
I/O
U7
NC
NC
U8
VDDP
VDD
GND
GND
GND
GND
VDDP
VDD
GND
GND
GND
GND
I/O
I/O
U9
I/O
I/O
U10
U11
U12
U13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
92
Advanced v0.6
ProASICPLUS Family Flash FPGAs
676-FBGA Pin (Continued)
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
W1
W2
I/O
I/O
I/O
I/O
Y14
Y15
I/O
NC
I/O
NC
I/O
VDD
VPP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO
GND
GND
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
VDD
VPP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO
GND
GND
I/O
I/O
I/O
W3
I/O
I/O
Y16
W4
I/O
I/O
Y17
W5
I/O
I/O
Y18
W6
I/O
I/O
Y19
W7
VDD
VDD
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDD
VDDP
I/O
VDD
VDD
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDD
VDDP
I/O
Y20
W8
Y21
W9
Y22
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
Y1
Y23
Y24
Y25
Y26
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
I/O
I/O
AA9
I/O
I/O
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Y2
I/O
I/O
Y3
I/O
I/O
Y4
I/O
I/O
Y5
I/O
I/O
Y6
I/O
I/O
Y7
I/O
I/O
Y8
VDDP
NC
VDDP
NC
Y9
Y10
Y11
Y12
Y13
I/O
I/O
NC
NC
I/O
I/O
NC
NC
Advanced v0.6
93
ProASICPLUS Family Flash FPGAs
676-FBGA Pin (Continued)
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
AB1
AB2
I/O
I/O
I/O
I/O
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
VPN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
RCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
VPN
I/O
I/O
AB3
I/O
I/O
AB4
I/O
I/O
AB5
I/O
I/O
AB6
GND
GND
I/O
GND
GND
I/O
AB7
AB8
AB9
I/O
I/O
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD2
I/O
I/O
AD3
I/O
I/O
AD4
I/O
I/O
AD5
I/O
I/O
AD6
I/O
I/O
AD7
TCK
TRST
I/O
TCK
TRST
I/O
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AC2
I/O
I/O
AC3
I/O
I/O
AC4
I/O
I/O
AC5
GND
I/O
GND
I/O
AC6
AC7
I/O
I/O
AC8
I/O
I/O
AC9
GND
I/O
GND
I/O
AC10
AC11
AC12
AC13
I/O
I/O
I/O
I/O
I/O
I/O
94
Advanced v0.6
ProASICPLUS Family Flash FPGAs
676-FBGA Pin (Continued)
676-FBGA Pin (Continued)
Pin
Number
APA600
Function
APA750
Function
Pin
Number
APA600
Function
APA750
Function
AE1
AE2
GND
GND
GND
I/O
GND
GND
GND
I/O
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
I/O
I/O
I/O
I/O
AE3
I/O
I/O
AE4
I/O
I/O
AE5
I/O
I/O
I/O
I/O
AE6
I/O
I/O
I/O
I/O
AE7
I/O
I/O
I/O
I/O
AE8
I/O
I/O
I/O
I/O
AE9
I/O
I/O
I/O
I/O
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
I/O
GND
GND
GND
GND
GND
GND
I/O
AF2
AF3
AF4
AF5
AF6
I/O
I/O
AF7
I/O
I/O
AF8
I/O
I/O
AF9
I/O
I/O
AF10
AF11
AF12
AF13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
95
ProASICPLUS Family Flash FPGAs
Package Pin Assignments (Continued)
896-Pin FBGA (Bottom View)
30 29 28 27 26 25 2423 22 21 20 191817 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
96
Advanced v0.6
ProASICPLUS Family Flash FPGAs
896 FBGA Pin
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
A2
A3
GND
GND
I/O
GND
GND
I/O
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
C1
I/O
I/O
I/O
I/O
A4
I/O
I/O
A5
GND
I/O
GND
I/O
I/O
I/O
A6
I/O
I/O
A7
GND
I/O
GND
I/O
I/O
I/O
A8
I/O
I/O
A9
I/O
I/O
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
I/O
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C2
I/O
I/O
C3
VDD
I/O
VDD
I/O
GND
I/O
GND
I/O
C4
C5
VDDP
I/O
VDDP
I/O
GND
I/O
GND
I/O
C6
C7
I/O
I/O
GND
GND
GND
GND
I/O
GND
GND
GND
GND
I/O
C8
I/O
I/O
C9
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
I/O
I/O
B2
I/O
I/O
B3
I/O
I/O
B4
VDD
I/O
VDD
I/O
I/O
I/O
B5
I/O
I/O
B6
VDD
I/O
VDD
I/O
I/O
I/O
B7
I/O
I/O
B8
I/O
I/O
I/O
I/O
B9
I/O
I/O
I/O
I/O
B10
B11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
97
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
D1
I/O
I/O
I/O
I/O
D30
E1
I/O
GND
I/O
I/O
GND
I/O
I/O
I/O
E2
I/O
I/O
E3
VDDP
I/O
VDDP
I/O
I/O
I/O
E4
VDDP
I/O
VDDP
I/O
E5
VDD
I/O
VDD
I/O
E6
VDD
NC
GND
I/O
VDD
I/O
E7
VDDP
I/O
VDDP
I/O
E8
GND
I/O
E9
I/O
I/O
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
F1
I/O
I/O
D2
VDD
I/O
VDD
I/O
I/O
I/O
D3
I/O
I/O
D4
GND
I/O
GND
I/O
I/O
I/O
D5
I/O
I/O
D6
I/O
I/O
I/O
I/O
D7
I/O
I/O
I/O
I/O
D8
I/O
I/O
I/O
I/O
D9
I/O
I/O
I/O
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
F2
VDD
I/O
VDD
I/O
I/O
I/O
F3
I/O
I/O
F4
I/O
I/O
I/O
I/O
F5
I/O
I/O
GND
I/O
GND
I/O
F6
GND
I/O
GND
I/O
F7
VDD
VDD
F8
I/O
I/O
98
Advanced v0.6
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
F9
I/O
I/O
I/O
I/O
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
H1
I/O
I/O
I/O
I/O
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
G1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
H2
I/O
I/O
I/O
I/O
H3
I/O
I/O
GND
I/O
GND
I/O
H4
I/O
I/O
H5
I/O
I/O
I/O
I/O
H6
I/O
I/O
I/O
I/O
H7
I/O
I/O
VDD
I/O
VDD
I/O
H8
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
I/O
GND
I/O
H9
GND
I/O
GND
I/O
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
I/O
G2
I/O
G3
I/O
I/O
I/O
G4
I/O
I/O
I/O
G5
VDDP
I/O
VDDP
I/O
I/O
G6
I/O
G7
VDD
I/O
VDD
I/O
I/O
G8
I/O
G9
VDDP
I/O
VDDP
I/O
I/O
G10
G11
G12
G13
G14
G15
G16
G17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
99
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
H27
H28
H29
H30
J1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
K6
K7
I/O
I/O
I/O
I/O
K8
I/O
I/O
K9
NC
I/O
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
L1
VDD
NC
VDD
I/O
J2
J3
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
NC
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
I/O
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K1
VDD
NC
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L2
I/O
I/O
L3
I/O
I/O
L4
I/O
I/O
L5
I/O
I/O
L6
I/O
I/O
L7
I/O
I/O
L8
I/O
I/O
L9
NC
I/O
L10
L11
L12
L13
L14
NC
I/O
K2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
K3
K4
K5
100
Advanced v0.6
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
M1
VDD
VDD
VDD
VDD
VDD
VDD
NC
VDD
VDD
VDD
VDD
VDD
VDD
I/O
M24
M25
M26
M27
M28
M29
M30
N1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
N2
I/O
I/O
I/O
I/O
N3
I/O
I/O
I/O
I/O
N4
I/O
I/O
I/O
I/O
N5
I/O
I/O
I/O
I/O
N6
I/O
I/O
I/O
I/O
N7
I/O
I/O
I/O
I/O
N8
I/O
I/O
I/O
I/O
N9
NC
I/O
I/O
I/O
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
P1
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
M2
I/O
I/O
M3
I/O
I/O
M4
I/O
I/O
M5
I/O
I/O
M6
I/O
I/O
M7
I/O
I/O
M8
I/O
I/O
M9
NC
I/O
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P2
I/O
I/O
Advanced v0.6
101
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
P3
P4
I/O
I/O
I/O
I/O
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
T1
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
P5
I/O
I/O
P6
I/O
I/O
P7
I/O
I/O
P8
I/O
I/O
P9
I/O
I/O
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
R1
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NPECL
AGND
I/O
NPECL
AGND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T2
AVDD
GL
AVDD
GL
I/O
I/O
T3
I/O
I/O
T4
PPECL
I/O
PPECL
I/O
I/O
I/O
T5
I/O
I/O
T6
I/O
I/O
I/O
I/O
T7
I/O
I/O
I/O
I/O
T8
I/O
I/O
I/O
I/O
T9
I/O
I/O
I/O
I/O
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
R2
I/O
I/O
R3
AGND
NPECL
GL
AGND
NPECL
GL
R4
R5
R6
I/O
I/O
R7
I/O
I/O
R8
I/O
I/O
R9
NC
I/O
R10
R11
VDDP
VDD
VDDP
VDD
102
Advanced v0.6
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
U1
VDDP
I/O
VDDP
I/O
U30
V1
I/O
I/O
I/O
I/O
I/O
I/O
V2
I/O
I/O
I/O
I/O
V3
I/O
I/O
I/O
I/O
V4
I/O
I/O
PPECL
GL
PPECL
GL
V5
I/O
I/O
V6
I/O
I/O
GL
GL
V7
I/O
I/O
AVDD
I/O
AVDD
I/O
V8
I/O
I/O
V9
NC
I/O
I/O
I/O
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
W1
W2
W3
W4
W5
W6
W7
W8
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
U2
I/O
I/O
U3
I/O
I/O
U4
I/O
I/O
U5
I/O
I/O
U6
I/O
I/O
U7
I/O
I/O
U8
I/O
I/O
U9
NC
I/O
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
103
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
Y1
NC
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
NC
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
Y18
Y19
VDD
VDD
VDD
NC
VDD
VDD
VDD
I/O
Y20
Y21
Y22
NC
I/O
Y23
I/O
I/O
Y24
I/O
I/O
Y25
I/O
I/O
Y26
I/O
I/O
Y27
I/O
I/O
Y28
I/O
I/O
Y29
I/O
I/O
Y30
I/O
I/O
AA1
I/O
I/O
I/O
I/O
AA2
I/O
I/O
I/O
I/O
AA3
I/O
I/O
I/O
I/O
AA4
I/O
I/O
I/O
I/O
AA5
I/O
I/O
I/O
I/O
AA6
I/O
I/O
I/O
I/O
AA7
I/O
I/O
I/O
I/O
AA8
I/O
I/O
I/O
I/O
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
NC
I/O
I/O
I/O
VDD
NC
VDD
I/O
Y2
I/O
I/O
Y3
I/O
I/O
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
NC
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
I/O
Y4
I/O
I/O
Y5
I/O
I/O
Y6
I/O
I/O
Y7
I/O
I/O
Y8
I/O
I/O
Y9
NC
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
NC
I/O
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
104
Advanced v0.6
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
AA27
AA28
AA29
AA30
AB1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AC6
AC7
I/O
I/O
I/O
I/O
AC8
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
I/O
GND
I/O
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AD1
I/O
AB2
I/O
AB3
I/O
AB4
I/O
AB5
I/O
AB6
I/O
AB7
I/O
AB8
I/O
AB9
I/O
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC1
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
AD2
AD3
I/O
I/O
AD4
I/O
I/O
AD5
VDDP
I/O
VDDP
I/O
AD6
AD7
VDD
I/O
VDD
I/O
AD8
AD9
VDDP
I/O
VDDP
I/O
AD10
AD11
AD12
AD13
AD14
AC2
I/O
I/O
AC3
I/O
I/O
AC4
I/O
I/O
AC5
I/O
I/O
Advanced v0.6
105
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AE1
I/O
I/O
I/O
I/O
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AF1
I/O
GND
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
I/O
I/O
VDDP
TCK
VDD
TRST
VDDP
I/O
VDDP
TCK
VDD
TRST
VDDP
I/O
GND
I/O
GND
I/O
AF2
AF3
VDDP
I/O
VDDP
I/O
AF4
AF5
VDD
I/O
VDD
I/O
AF6
I/O
I/O
AF7
VDDP
I/O
VDDP
I/O
I/O
I/O
AF8
GND
I/O
GND
I/O
AF9
I/O
I/O
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AG1
I/O
I/O
AE2
VDD
I/O
VDD
I/O
I/O
I/O
AE3
I/O
I/O
AE4
I/O
I/O
I/O
I/O
AE5
I/O
I/O
I/O
I/O
AE6
GND
I/O
GND
I/O
I/O
I/O
AE7
I/O
I/O
AE8
I/O
I/O
I/O
I/O
AE9
I/O
I/O
I/O
I/O
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
VDD
TDO
VDDP
VPN
GND
I/O
VDD
TDO
VDDP
VPN
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AG2
VDD
VDD
106
Advanced v0.6
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
APA750
Function
APA1000
Function
Pin Number
Pin Number
AG3
AG4
I/O
GND
I/O
I/O
GND
I/O
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AJ1
I/O
I/O
I/O
I/O
AG5
I/O
I/O
AG6
I/O
I/O
I/O
I/O
AG7
I/O
I/O
I/O
I/O
AG8
I/O
I/O
I/O
I/O
AG9
I/O
I/O
I/O
I/O
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
TDI
VDD
VPP
GND
GND
GND
I/O
VDDP
TDI
VDD
VPP
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AJ2
I/O
I/O
AJ3
I/O
I/O
AJ4
VDD
I/O
VDD
I/O
I/O
I/O
AJ5
GND
RCK
VDD
I/O
GND
RCK
VDD
I/O
AJ6
VDD
I/O
VDD
I/O
AJ7
AJ8
I/O
I/O
AJ9
I/O
I/O
GND
I/O
GND
I/O
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
I/O
I/O
AH2
I/O
I/O
AH3
VDD
I/O
VDD
I/O
I/O
I/O
AH4
I/O
I/O
AH5
VDDP
I/O
VDDP
I/O
I/O
I/O
AH6
I/O
I/O
AH7
I/O
I/O
I/O
I/O
AH8
I/O
I/O
I/O
I/O
AH9
I/O
I/O
I/O
I/O
AH10
AH11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Advanced v0.6
107
ProASICPLUS Family Flash FPGAs
896 FBGA Pin (Continued)
APA750
Function
APA1000
Function
Pin Number
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
VDD
I/O
VDD
TMS
GND
GND
GND
GND
I/O
VDD
TMS
GND
GND
GND
GND
I/O
AK3
AK4
AK5
GND
I/O
GND
I/O
AK6
AK7
GND
I/O
GND
I/O
AK8
AK9
I/O
I/O
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
GND
GND
GND
108
Advanced v0.6
ProASICPLUS Family Flash FPGAs
Package Pin Assignments (Continued)
1152-Pin FBGA (Bottom View)
A1 Ball Pad
Corner
34 33 32 313029 282726 25 2423 2221 201918 171615 1413 121110 9 8 7 6 5 4
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
Advanced v0.6
109
ProASICPLUS Family Flash FPGAs
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
A2
A3
NC
GND
GND
GND
I/O
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
C1
VDDP
VDDP
I/O
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
D1
I/O
GND
I/O
E2
E3
GND
GND
I/O
A4
E4
A5
GND
GND
I/O
GND
I/O
E5
VDD
I/O
A6
E6
A7
VDD
VDD
VDD
VDD
I/O
GND
GND
NC
E7
VDDP
I/O
A8
VDDP
VDDP
I/O
E8
A9
E9
I/O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
B1
GND
GND
GND
GND
GND
GND
I/O
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
F1
I/O
GND
I/O
I/O
GND
I/O
I/O
NC
D2
I/O
VDDP
VDDP
I/O
I/O
D3
I/O
NC
D4
I/O
I/O
D5
I/O
GND
GND
I/O
NC
D6
VDD
I/O
I/O
GND
GND
GND
NC
D7
I/O
D8
VDD
I/O
I/O
VDDP
VDDP
I/O
D9
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
E1
I/O
I/O
NC
I/O
I/O
GND
I/O
GND
GND
NC
I/O
I/O
C2
I/O
I/O
VDD
VDD
VDD
VDD
I/O
C3
I/O
I/O
C4
GND
GND
I/O
I/O
I/O
C5
I/O
I/O
C6
I/O
VDDP
I/O
C7
GND
I/O
I/O
GND
GND
GND
NC
C8
I/O
VDD
I/O
C9
GND
I/O
I/O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
I/O
GND
GND
GND
I/O
I/O
I/O
NC
I/O
I/O
B2
NC
I/O
I/O
B3
GND
GND
GND
NC
I/O
I/O
F2
NC
I/O
B4
I/O
I/O
F3
B5
I/O
VDD
I/O
F4
VDD
I/O
B6
I/O
F5
B7
I/O
I/O
VDD
I/O
F6
GND
I/O
B8
NC
I/O
F7
B9
I/O
I/O
GND
GND
GND
GND
GND
F8
I/O
B10
B11
B12
B13
NC
I/O
F9
I/O
I/O
I/O
F10
F11
F12
I/O
GND
I/O
I/O
I/O
I/O
I/O
110
Advanced v0.6
ProASICPLUS Family Flash FPGAs
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
G1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VDD
I/O
NC
NC
VDD
I/O
GND
I/O
VDDP
I/O
VDD
I/O
VDDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
H1
I/O
I/O
J1
J2
VDD
I/O
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
L1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDP
I/O
J3
GND
I/O
J4
VDD
I/O
J5
I/O
J6
I/O
VDDP
I/O
J7
VDDP
I/O
J8
GND
I/O
J9
VDD
I/O
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
K1
VDD
VDD
NC
I/O
VDDP
I/O
H2
I/O
H3
I/O
H4
VDD
I/O
I/O
H5
I/O
H6
I/O
I/O
H7
I/O
I/O
H8
GND
I/O
I/O
H9
I/O
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
I/O
I/O
I/O
I/O
I/O
I/O
G2
I/O
VDDP
I/O
G3
I/O
L2
G4
I/O
VDD
I/O
L3
G5
I/O
L4
G6
I/O
VDDP
I/O
L5
G7
I/O
L6
G8
I/O
I/O
L7
G9
I/O
I/O
L8
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
I/O
GND
I/O
L9
I/O
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
I/O
VDD
VDD
NC
I/O
I/O
I/O
K2
I/O
K3
GND
I/O
K4
I/O
K5
I/O
I/O
K6
I/O
I/O
K7
I/O
VDD
I/O
K8
I/O
K9
I/O
NC
VDD
K10
K11
GND
I/O
Advanced v0.6
111
ProASICPLUS Family Flash FPGAs
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
M1
I/O
VDD
I/O
M34
N1
GND
I/O
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
R1
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
T1
VDD
VDDP
I/O
N2
I/O
VDDP
I/O
N3
I/O
I/O
N4
I/O
I/O
I/O
N5
I/O
I/O
I/O
N6
I/O
I/O
I/O
N7
I/O
I/O
I/O
N8
I/O
I/O
I/O
N9
I/O
I/O
I/O
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
N31
N32
N33
N34
P1
I/O
I/O
I/O
I/O
VDDP
VDDP
I/O
GND
GND
I/O
I/O
M2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
I/O
M3
I/O
T2
I/O
M4
I/O
I/O
T3
I/O
M5
I/O
I/O
T4
I/O
M6
I/O
I/O
T5
I/O
M7
I/O
I/O
T6
I/O
M8
I/O
I/O
T7
I/O
M9
I/O
I/O
T8
I/O
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
I/O
I/O
T9
I/O
I/O
VDDP
VDDP
VDDP
VDDP
I/O
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
I/O
VDD
I/O
I/O
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
I/O
I/O
R2
I/O
R3
I/O
R4
I/O
I/O
R5
I/O
I/O
R6
I/O
I/O
R7
I/O
I/O
R8
I/O
I/O
R9
I/O
I/O
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
I/O
VDD
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
I/O
P2
I/O
P3
I/O
I/O
P4
I/O
I/O
I/O
P5
I/O
I/O
I/O
P6
I/O
I/O
I/O
P7
I/O
I/O
I/O
P8
I/O
I/O
I/O
P9
I/O
I/O
GND
P10
I/O
I/O
112
Advanced v0.6
ProASICPLUS Family Flash FPGAs
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
T33
T34
U1
I/O
I/O
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
W1
I/O
I/O
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
Y1
GND
VDD
VDDP
I/O
Y32
Y33
I/O
VDDP
VDDP
VDDP
VDDP
I/O
GND
GND
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
Y34
U2
AA1
U3
I/O
AA2
U4
I/O
I/O
AA3
U5
AGND
NPECL
GL
I/O
AA4
I/O
U6
I/O
AA5
I/O
U7
I/O
AA6
I/O
U8
I/O
I/O
AA7
I/O
U9
I/O
I/O
AA8
I/O
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
V1
I/O
I/O
AA9
I/O
I/O
I/O
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AB1
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
Y2
I/O
Y3
I/O
Y4
I/O
PPECL
GL
Y5
I/O
Y6
I/O
GL
Y7
I/O
AVDD
I/O
Y8
I/O
Y9
I/O
GND
GND
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
I/O
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDDP
I/O
I/O
W2
I/O
I/O
W3
I/O
I/O
I/O
W4
I/O
I/O
I/O
W5
I/O
I/O
NPECL
AGND
I/O
W6
I/O
I/O
W7
I/O
I/O
W8
I/O
I/O
I/O
W9
I/O
I/O
GND
GND
GND
GND
I/O
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
I/O
I/O
I/O
VDDP
VDDP
I/O
VDDP
VDD
GND
GND
GND
GND
GND
GND
GND
V2
V3
I/O
AB2
I/O
V4
AVDD
GL
I/O
AB3
I/O
V5
I/O
AB4
I/O
V6
PPECL
I/O
I/O
AB5
I/O
V7
I/O
AB6
I/O
V8
I/O
I/O
AB7
I/O
V9
I/O
I/O
AB8
I/O
Advanced v0.6
113
ProASICPLUS Family Flash FPGAs
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AC1
I/O
I/O
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AD1
VDDP
VDDP
I/O
AD31
AD32
AD33
AD34
AE1
I/O
I/O
I/O
I/O
VDD
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
VDD
VDD
I/O
GND
I/O
I/O
I/O
VDDP
AF8
AF9
I/O
VDD
I/O
I/O
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AG1
I/O
VDD
I/O
VDDP
I/O
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
I/O
I/O
AE2
I/O
I/O
AE3
I/O
I/O
AE4
I/O
I/O
AE5
I/O
I/O
AE6
I/O
I/O
AE7
I/O
I/O
AE8
I/O
I/O
AE9
I/O
GND
GND
I/O
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AF1
I/O
I/O
I/O
I/O
I/O
AD2
I/O
VDDP
TCK
VDD
TRST
VDDP
I/O
I/O
AD3
I/O
I/O
AD4
I/O
I/O
AD5
I/O
I/O
AD6
I/O
I/O
AD7
I/O
I/O
AD8
I/O
I/O
I/O
AD9
VDDP
I/O
I/O
I/O
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
GND
I/O
I/O
VDD
I/O
GND
GND
I/O
VDD
VDD
NC
I/O
AC2
I/O
AC3
I/O
AG2
AC4
I/O
I/O
AG3
AC5
I/O
I/O
AG4
VDD
I/O
AC6
I/O
I/O
AG5
AC7
I/O
I/O
AG6
I/O
AC8
I/O
I/O
AG7
I/O
AC9
I/O
I/O
AG8
GND
I/O
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
I/O
I/O
AG9
I/O
I/O
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
I/O
VDD
I/O
I/O
I/O
VDD
I/O
I/O
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
AF2
I/O
VDDP
I/O
AF3
I/O
AF4
I/O
I/O
AF5
I/O
I/O
AF6
I/O
I/O
AF7
I/O
114
Advanced v0.6
ProASICPLUS Family Flash FPGAs
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
1152-Pin FBGA
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AG31
AG32
AG33
AG34
AH1
I/O
I/O
AH30
AH31
AH32
AH33
AH34
AJ1
VDDP
VPN
GND
I/O
AK7
AK8
VDDP
I/O
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AM1
I/O
I/O
I/O
AK9
I/O
I/O
I/O
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AL1
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AJ2
NC
I/O
I/O
I/O
I/O
AJ3
I/O
I/O
GND
I/O
AJ4
VDD
I/O
I/O
I/O
AJ5
I/O
VDD
I/O
I/O
AJ6
GND
I/O
I/O
I/O
AJ7
I/O
VDD
TMS
GND
GND
GND
GND
GND
GND
NC
VDD
I/O
AJ8
I/O
I/O
AJ9
I/O
I/O
NC
VDD
VDD
I/O
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AK1
I/O
I/O
I/O
I/O
I/O
I/O
AH2
I/O
I/O
AH3
GND
I/O
I/O
I/O
AM2
AH4
I/O
I/O
AM3
AH5
VDDP
I/O
I/O
I/O
AM4
GND
GND
I/O
AH6
I/O
VDDP
TDI
VDD
VPP
GND
GND
GND
GND
GND
GND
GND
I/O
AM5
AH7
VDD
I/O
I/O
AM6
AH8
I/O
AM7
GND
I/O
AH9
VDDP
I/O
I/O
AM8
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
I/O
AM9
GND
I/O
I/O
I/O
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AL2
I/O
I/O
I/O
AL3
I/O
I/O
I/O
AL4
I/O
I/O
I/O
AL5
I/O
I/O
GND
RCK
VDD
I/O
AL6
VDD
I/O
I/O
I/O
AL7
I/O
I/O
AL8
VDD
I/O
I/O
I/O
AL9
I/O
I/O
NC
NC
GND
GND
GND
I/O
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AK2
I/O
I/O
VDDP
I/O
AK3
I/O
I/O
AK4
I/O
GND
I/O
VDD
TDO
AK5
VDD
I/O
I/O
AK6
I/O
GND
Advanced v0.6
115
ProASICPLUS Family Flash FPGAs
1152-Pin FBGA
1152-Pin FBGA
Pin
Number
APA1000
Function
Pin
Number
APA1000
Function
AM29
AM30
AM31
AM32
AM33
AM34
AN1
I/O
GND
GND
NC
AP7
AP8
VDD
VDD
VDD
VDD
I/O
AP9
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
GND
GND
NC
GND
I/O
AN2
NC
VDDP
VDDP
I/O
AN3
GND
GND
GND
NC
AN4
AN5
GND
GND
I/O
AN6
AN7
I/O
AN8
NC
VDDP
VDDP
I/O
AN9
I/O
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AP2
NC
I/O
GND
I/O
GND
I/O
VDD
VDD
VDD
VDD
I/O
VDDP
VDDP
I/O
GND
GND
I/O
GND
GND
GND
NC
VDDP
VDDP
I/O
GND
I/O
NC
I/O
NC
I/O
NC
GND
GND
GND
NC
NC
NC
AP3
GND
GND
GND
I/O
AP4
AP5
AP6
116
Advanced v0.6
ProASICPLUS Family Flash FPGAs
List of Changes
The following table lists critical changes that were made in
the current version of the document.
Previous version Changes in current version (Advanced v0.6)
Page
Advanced v0.5
The description for the VPN pin has changed.
page 54
page 4
The “Plastic Device Resources” table on page 4 has been updated.
Figure 19 and Figure 20 on page 28 have been updated.
The “Tristate Buffer Delays” table on page 30 has been updated.
The “Output Buffer Delays” table on page 31 has been updated.
The “Input Buffer Delays” table on page 32 has been updated.
The “Global Input Buffer Delays” table on page 32 has been updated.
The “456-Pin PBGA” table on page 63 has been updated.
The “676-FBGA Pin” table on page 87 has been updated.
The “ProASICPLUS Product Profile” section on page 1 has been changed.
The “Plastic Device Resources” section on page 4 has been updated.
The Supply Voltages table on page 10 has been updated.
page 28
page 30
page 31
page 32
page 32
page 63
page 87
page 1
Advanced v0.4
page 4
page 10
WDATA has ben changed to DI, and RDATA has been changed to DO to make them
consistent with the signal names found in the Macro Library Guide.
page 15
and page 16
Figure 13 on page 15 and Figure 14 on page 16 have been updated.
The “Design Environment” section on page 17 and Figure 18 on page 18 have been page 17
updated.
and page 18
The table in the “Package Thermal Characteristics” section on page 19 has been
updated.
page 19
The “Calculating Power Dissipation” section on page 20 is new.
The “Programming and Storage Temperature Limits” section on page 22 is new.
The “Supply Voltages” section on page 22 has been updated.
page 20
page 22
page 22
The “DC Electrical Specifications (VDDP = 2.5V +/-0.2V)” section on page 23 was
updated.
page 23
page 24
page 26
Advanced v0.3
The “DC Electrical Specifications (VDDP = 3.3V +/-0.3V and VDD 2.5+/-0.2V)”
section on page 24 was updated.
The “AC Specifications (3.3V PCI Revision 2.2 Operation)” section on page 26 was
updated.
The “Clock Conditioning Circuit” section on page 27 was updated.
Figure 19 on page 28 was updated.
page 27
page 28
page 28
Figure 20 on page 28 is new.
Tables 5, 6, and 7 from Advanced v0.3 were removed.
The “Memory Block SRAM Interface Signals” section on page 35 was updated.
The “Memory Block FIFO Interface Signals” section on page 46 was updated.
All pinout tables have been updated, and several packages are new:
page 35
page 46
208-Pin PQFP – APA150, APA300, APA450, APA600
456-Pin PBGA – APA150, APA300, APA450, APA600
144-Pin FBGA – APA150, APA300, APA450
256-Pin FBGA – APA150, APA300, APA450, APA600
676-Pin FBGA – APA600
Advanced v0.1
Figure 15 on page 16 has been updated
page 16
Advanced v0.6
117
ProASICPLUS Family Flash FPGAs
Data Sheet Categories
In order to provide the latest information to designers, some data sheets are published before data has been fully
characterized. Product Briefs are modified versions of data sheets. Data sheets are marked as “Advanced,” “Preliminary,” and
“Web-only.” The definition of these categories are as follows:
Product Brief
The product brief is a modified version of an Advanced data sheet containing general product information. This brief
summarizes specific device and family information for non-release products.
Advanced
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This
information can be used as estimates, but not for production.
Preliminary
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be
correct, but changes are possible.
Unmarked (production)
The data sheet contains information that is considered to be final.
Web-only Versions
Web-only versions have three numbers in the version number (example: v2.0.1). A web-only version means Actel is posting
the data sheet so customers have the latest information, but we are not printing the version because some information is
going to change shortly after posting.
118
Advanced v0.6
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
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