APA150-PQG208A [ACTEL]
Field Programmable Gate Array, 6144-Cell, CMOS, PQFP208,;
| 型号： | APA150-PQG208A |
| 厂家： | 
Actel Corporation |
| 描述： | Field Programmable Gate Array, 6144-Cell, CMOS, PQFP208, 栅 |
| 文件： | 总10页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Au t o m o t ive Su p p le m e n t
TM
Automotive-Grade ProASICPLUS Flash Family FPGAs
•
•
•
High-Speed, Very Long-Line Network
High Performance, Low-Skew, Splittable Global Network
100% Utilization and >95% Routability
Features and Benefits
High Capacity
•
•
•
75,000 to 1 Million System Gates
27k to 198kbits of Two-Port SRAM
66 to 642 User I/Os
I/O
•
•
Schmitt-Trigger Option on Every Input
2.5V/3.3V Support with Individually-Selectable Voltage and
Slew Rate
Reprogrammable Flash Technology
•
•
•
•
Bidirectional Global I/Os
•
•
•
•
0.22µ 4LM Flash-based CMOS Process
Live at Power-Up, Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during
Power-Down/Power-Up Cycles
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin Compatible Packages across ProASICPLUS Family
Unique Clock Conditioning Circuitry
•
PLLs with Flexible Phase, Multiply/Divide and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Extended Temperature Range
•
Supports Automotive Temperature Range -40 to 125°C (Junction)
•
•
Performance
•
•
•
3.3V, 32-Bit PCI (up to 50 MHz)
Two Integrated PLLs
External System Performance up to 150 MHz
Standard FPGA and ASIC Design Flow
•
•
Flexibility with Choice of Industry-Standard Frontend Tools
Efficient Design through Front-End Timing and Gate
Optimization
Secure Programming
•
Industry’s Most Effective Security Key (FlashLock™)
Prevents Read Back of Programming Bitstream
ISP Support
•
In-System Programming (ISP) via JTAG Port
Low Pow er
SRAMs and FIFOs
•
•
•
Low Impedance Flash Switches
•
ACTgen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
•
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
High Performance Routing Hierarchy
•
Ultra-Fast Local and Long-Line Network
Table 1 • Automotive-Grade ProASICPLUS Product Profile
De vice
APA075
75,000
3,072
APA150
150,000
6,144
APA300
300,000
8,192
APA450
450,000
12,288
108k
APA600
600,000
21,504
126k
APA750 APA1000
Maximum System Gates
Maximum Tiles (Registers)
750,000
32,768
144k
1,000,000
56,320
198k
Embedded RAM Bits (k=1,024
bits)
27k
36k
72k
Embedded RAM Blocks (256x9)
12
2
16
2
32
2
48
2
56
2
64
2
88
2
LVPECL
PLL
2
2
2
2
2
2
2
Global Netw orks
Maximum Clocks
Maximum User I/Os
JTAG ISP
4
4
4
4
4
4
4
24
158
Yes
Yes
32
186
Yes
Yes
32
186
Yes
Yes
48
344
Yes
Yes
56
370
Yes
Yes
64
562
Yes
Yes
88
642
Yes
Yes
PCI
Package (by pin count)
TQFP
100
208
144
100
208
–
–
–
–
–
PQFP
208
208
208
208
896
208
896
FBGA
144, 256
144, 256 144, 256, 484
256, 484
Fe b ru a ry 2004
1
© 2004 Actel Corporation
Au t o m o t ive -Gra d e Pro ASICPLUS Fla sh Fa m ily FPGAs
Ordering Information
APA1000
FG
896
A
Application
A = Automotive (-40 to 125˚C)
Package Lead Count
Package Type
=
=
=
TQ
PQ
FG
Thin Quad Flat Pack (1.4mm pitch)
Plastic Quad Flat Pack (0.5mm pitch)
Fine Pitch Ball Grid Array (1.0mm pitch)
Part Number
APA075 = 75,000 Equivalent System Gates
APA150 = 150,000 Equivalent System Gates
APA300 = 300,000 Equivalent System Gates
APA450 = 450,000 Equivalent System Gates
APA600 = 600,000 Equivalent System Gates
APA750 = 750,000 Equivalent System Gates
APA1000 = 1,000,000 Equivalent System Gates
Plastic Device Resources
Use r I/Os*
TQFP
PQFP
FBGA
FBGA
FBGA
FBGA
De vice
APA075
APA150
APA300
APA450
APA600
APA750
100-Pin
208-Pin
144-Pin
256-Pin
484-Pin
896-Pin
66
158
158
158
158
158
158
158
100
100
100
100
66
186
186
186
186
344
370
562
642
APA1000
Package Definitions
TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, FBGA = Fine Pitch Ball Grid Array
*Each pair of PECL I/Os were counted as one user I/O.
Speed Grade Matrix
St d
Automotive-Grade
✔
Contact your local Actel sales representative for device availability.
2
A u t o m o t i v e S u p p l e m e n t
Au t o m o t ive -Gra d e Pro ASICPLUS Fla sh Fa m ily FPGAs
General Description
PLUS
ProASIC
devices offer a reprogrammable design
resources, and abundant Flash switches allows 100%
utilization and over 95% routability for highly congested
designs. Tiles and larger functions are interconnected
through a four-level routing hierarchy.
integration solution at the automotive temperature
range (-40°C to +125°C) through the use of nonvolatile
Flash technology. ProASIC
PLUS
devices have a fine-grain
PLUS
architecture, similar to ASICs, and enable engineers to
design high-density systems using existing ASIC or FPGA
design flows and tools. Automotive-grade ProASIC
devices offer up to 1 million system gates, support up to
198kbits of two-port SRAM and 642 user I/Os and provide
50 MHz PCI performance.
Automotive-grade
ProASIC
devices
feature
embedded two-port SRAM blocks with built-in FIFO/RAM
control logic and user-defined depth and width. Users
PLUS
can
select
programming
for
synchronous
or
asynchronous operation, as well as parity generation or
checking.
PLUS
The nonvolatile and reprogrammable Flash technology
The automotive-grade ProASIC
devices offer
a
PLUS
enables ProASIC
devices to be live at power-up, and
unique clock conditioning circuit (CCC), with two clock
conditioning blocks in each device. Each block provides a
phase-locked loop (PLL) core, delay lines, phase shifts (0°,
90°, 180°, 270°), and clock multipliers/dividers, as well as
the circuitry required to provide bidirectional access to
the PLL. The PLL block contains four programmable
frequency dividers, which allow the incoming clock
signal to be divided by a wide range of factors from 1 to
64. The clock conditioning circuit can perform a positive/
negative clock delay operation in increments of 0.25 ns
by up to 8 ns. The PLL can be configured internally or
externally during operation without redesigning or
reprogramming the part. In addition to the PLL, there
are two LVPECL differential input pairs to accommodate
high speed clock and data inputs.
no external boot PROM is required to support device
programming. While on-board security mechanisms
prevent any access to the programmed information,
reprogramming can be performed in-system to support
future design iterations and field upgrades. The
PLUS
ProASIC
device architecture mitigates the complexity
of ASIC migration at higher user volume, making the
PLUS
automotive-grade ProASIC
a cost-effective solution
for in-cabin telematics and automobile interconnect
applications.
PLUS
The ProASIC
family is built on an advanced Flash-
based 0.22µm LVCMOS process with four layers of metal.
Standard CMOS design techniques are used to
implement logic and control functions, including the
PLLs and LVPECL inputs, resulting in predictable
performance fully compatible with gate arrays.
PLUS
PLUS
The automotive-grade ProASIC
devices are available
in a variety of high-performance plastic packages to
simplify the system board design.
The ProASIC
architecture provides granularity
comparable to gate arrays. The device core consists of a
Sea-of-Tiles . Each tile can be configured as a flip-flop,
latch, or three-input/one-output logic function by
programming the appropriate Flash switches. The
combination of fine granularity, flexible routing
To support for comprehensive, lower cost board-level
PLUS
testing, Actel’s ProASIC
devices are fully compatible
with IEEE Standard 1149.1 for test access port and
boundary-scan test architecture.
Au t o m o t iv e Su p p le m e n t
3
Au t o m o t ive -Gra d e Pro ASICPLUS Fla sh Fa m ily FPGAs
Operating Conditions
Table 1 • Absolute Maximum Ratings*
Pa ra m e t e r
Supply Voltage Core (VDD
Co n d it io n
Min im u m
–0.3
–0.3
–0.3
–1.0
10
Ma xim u m
3.0
Un it s
V
)
Supply Voltage I/O Ring (VDDP
)
4.0
V
DC Input Voltage
VDDP + 0.3
VDDP + 1.0
V
PCI DC Input Voltage
PCI DC Input Clamp Current (absolute)
LVPECL Input Voltage
GND
V
V
IN < –1V or VIN = VDDP + 1V
mA
V
–0.3
0
VDDP + 0.5
0
V
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Performance Retention
Actel guarantees the performance numbers presented in the Actel Designer timing analysis software and in this
datasheet, as long as the specified device performance retention period is not exceeded. For devices operated and
stored at 110°C or less, the performance retention period is 20 years after programming. For devices operated and
stored at temperatures greater than 110°C, refer to Table 2 on page 5 to determine the performance retention period.
Actel does not guarantee performance if the performance retention period is exceeded. Evaluate the percentage of
time spent at the highest temperature, then determine the next highest temperature to which the device will be
exposed. In Table 2 on page 5, find the temperature profile that most closely matches the application.
For example, the ambient temperature of a system cycles between 100°C (25% of the time) and 50°C (75% of the
time). No forced ventilation cooling system is in use. An APA600-PQ208A FPGA operates in the system, dissipating 1W.
The package thermal resistance (junction-to-ambient) in still air is 20°C/W, indicating that the junction temperature of
the FPGA will be 120°C (25% of the time) and 70°C (75% of the time). The entry in Table 2 on page 5, which most
closely matches the application, is 25% at 125°C with 75% at 110°C. Performance retention in this example is at least
16.0 years.
Note that exceeding the stated retention period may result in a performance degradation in the FPGA below the
worst-case performance indicated in the Actel Timer. To ensure that performance does not degrade below the worst-
case values in the Actel Timer, the FPGA must be reprogrammed within the performance retention period. In addition,
note that performance retention is independent of whether or not the FPGA is operating. The retention period of a
device in storage at a given temperature will be the same as the retention period of a device operating at that
junction temperature.
4
A u t o m o t i v e S u p p l e m e n t
Au t o m o t ive -Gra d e Pro ASICPLUS Fla sh Fa m ily FPGAs
Table 2 • Performance Retention
Tim e a t TJ 110°C o r b e lo w
Tim e a t TJ 125°C o r b e lo w
Min im u m Pro g ra m Re t e n t io n (Ye a rs)
100%
99%
98%
95%
90%
85%
80%
75%
70%
60%
50%
25%
0%
0%
1%
20.0
19.8
19.6
19.0
18.2
17.4
16.7
16.0
15.4
14.3
13.3
11.4
10.0
2%
5%
10%
15%
20%
25%
30%
40%
50%
75%
100%
Table 3 • Nominal Supply Voltages
Mo d e
VDD
2.5V
2.5V
VDDP
2.5V
3.3V
2.5V Output
3.3V Output*
PLUS
Note: *Automotive-grade ProASIC
devices do not support mixed-mode I/Os.
Table 4 • Recommended Maximum Operating Conditions for Programming and PLL Supplies*
Au t o m o t ive
Pa ra m e t e r
Co n d it io n
During Programming
Min im u m
15.8
Ma xim u m
Un it s
V
V
16.5
16.5
–13.2
0
PP
Normal Operation
0
V
V
During Programming
Normal Operation
–13.8
–13.8
V
PN
V
I
During Programming
During Programming
25
mA
mA
V
PP
I
10
PN
AVDD
AGND
V
V
DD
DD
GND
GND
V
Note: *Devices should not be operated outside the Recommended Operating Conditions.
Au t o m o t iv e Su p p le m e n t
5
Au t o m o t ive -Gra d e Pro ASICPLUS Fla sh Fa m ily FPGAs
Table 5 • Recommended Operating Conditions*
Lim it s
Pa ra m e t e r
Sym b o l
Au t o m o t ive
2.5V ± 5%
DC Supply Voltage (2.5V I/Os)
DC Supply Voltage (3.3V I/Os)
VDD & VDDP
VDDP
VDD
3.3V ± 5%
2.5V ± 5%
Operating Junction Temperature Range
T
-40°C to125°C
J
Note: *Devices should not be operated outside the Recommended Operating Conditions.
Table 6 • DC Electrical Specifications (VDD and VDDP = 2.5V ±5%)
Au t o m o t ive 1
Sym b o l
Pa ra m e t e r
Co n d it io n s
Min .
Typ .
Ma x.
Un it s
VOH
Output High Voltage
High Drive (OB25LPH)
IOH = –6 mA
IOH = –12 mA
2.1
2.0
1.7
IOH = –24 mA
V
IOH = –3 mA
IOH = –6 mA
2.1
1.9
1.7
Low Drive (OB25LPL)
IOH = –8 mA
VOL
Output Low Voltage
High Drive (OB25LPH)
IOL = 8 mA
IOL = 15 mA
IOL = 24 mA
0.2
0.4
0.7
V
IOL = 4 mA
IOL = 8 mA
0.2
0.4
0.7
Low Drive (OB25LPL)
IOL = 15 mA
V
Input High Voltage
Input Low Voltage
1.7
VDDP
0.3
+
V
IH
V
–0.3
6
0.7
56
V
IL
RWEAKPULLUP Weak Pull-up Resistance
(OTB25LPU)
V ≥ 1.25V
kΩ
IN
HYST
Input Hysteresis Schmitt
Input Current
0.3
–240
–50
0.35
5.0
0.45
– 20
50
V
I
with pull up (VIN = GND)
µA
µA
mA
IN
without pull up (VIN = GND or VDD
)
IDDQ
Quiescent Supply Current
(standby)
V
IN = GND2 or VDD
20
IOZ
Tristate Output Leakage Current VOH = GND or VDD
Output Short Circuit Current High
–50
50
µA
IOSH
High Drive (OB25LPH)
Low Drive (OB25LPL)
V
IN = VSS
–120
–100
mA
VIN = VSS
IOSL
Output Short Circuit Current Low
High Drive (OB25LPH)
V
IN = VDDP
100
30
mA
Low Drive (OB25LPL)
VIN = VDDP
CI/O
I/O Pad Capacitance
10
10
pF
pF
CCLK
Clock Input Pad Capacitance
No t e s:
1. All process conditions. Junction Temperature: –40 to +125°C.
2. No pull-up resistor.
6
A u t o m o t i v e S u p p l e m e n t
Au t o m o t ive -Gra d e Pro ASICPLUS Fla sh Fa m ily FPGAs
Table 7 • DC Electrical Specifications (VDDP = 3.3V ±5% and VDD 2.5V ±5% )
Au t o m o t ive 1
Typ .
Sym b o l
Pa ra m e t e r
Co n d it io n s
Min .
Ma x.
Un it s
VOH
Output High Voltage
3.3V I/O, High Drive (OB33P) IOH = –24 mA
IOH = –14 mA
0.9 VDDP
2.4
V
IOH = –6 mA
0.9 VDDP
2.4
3.3V I/O, Low Drive (OB33L)
Output Low Voltage
3.3V I/O, High Drive (OB33P) IOL = 20 mA
OL = 28 mA
IOH = –12 mA
VOL
IOL = 15 mA
0.1VDDP
0.4
0.7
I
V
V
3.3V I/O, Low Drive (OB33L) IOL = 7 mA
OL = 10 mA
OL = 15 mA
0.1VDDP
0.4
0.7
I
I
V
Input High Voltage
3.3V LVTTL/LVCMOS
IH
2
VDDP + 0.3
V
Input Low Voltage
IL
3.3V LVTTL/LVCMOS
–0.3
7
0.8
43
V
RWEAKPULLUP Weak
(IOB33U)
Pull-up
Resistance V ≥ 1.5V
kΩ
IN
RWEAKPULLUP Weak
(IOB25U)
Pull-up
Resistance V ≥ 1.5V
7
43
kΩ
IN
I
Input Current
with pull up (VIN = GND)
without pull up (VIN = GND or VDD
IN = GND2 or VDD
–300
–50
–40
50
µA
µA
IN
)
IDDQ
IOZ
Quiescent Supply Current
(standby)
V
5.0
20
mA
Tristate
Current
Output
Leakage VOH = GND or VDD
–10
10
µA
mA
mA
IOSH
Output Short Circuit Current
High
3.3V High Drive (OB33P)
3.3V Low Drive (OB33L)
VIN = GND
–200
–100
VIN = GND
IOSL
Output Short Circuit Current
Low
3.3V High Drive
3.3V Low Drive
VIN = VDD
200
100
VIN = VDD
CI/O
I/O Pad Capacitance
10
10
pF
pF
CCLK
Clock Input Pad Capacitance
No t e s:
1. All process conditions. Junction Temperature: –40 to +125°C.
2. No pull-up resistor.
Au t o m o t iv e Su p p le m e n t
7
Au t o m o t ive -Gra d e Pro ASICPLUS Fla sh Fa m ily FPGAs
Table 8 • DC Specifications (3.3V PCI Revision 2.2 Operation)1
Au t o m o t ive 2
Ma x.
Sym b o l
VDD
Pa ra m e t e r
Co n d it io n
Min .
2.375
Un it s
V
Supply Voltage for Core
Supply Voltage for I/O Ring
Input High Voltage
2.625
3.465
VDDP
3.135
V
V
0.5VDDP
–0.5
VDDP + 0.5
0.3VDDP
V
IH
V
Input Low Voltage
V
IL
I
Input Pull-up Voltage3
Input Leakage Current4
Output High Voltage
Output Low Voltage
Input Pin Capacitance (except CLK)
CLK Pin Capacitance
0.7VDDP
–50
V
IPU
I
0 < VIN < VCCI
IOUT = –500 µA
IOUT = 1500 µA
50
µA
V
IL
VOH
0.9VDDP
VOL
0.1VDDP
10
V
CIN
pF
pF
CCLK
No t e s:
5
12
1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cells only.
2. All process conditions. Junction Temperature: –40 to +125°C.
3. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a
floated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is
conducting minimum current at this input voltage.
4. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
8
A u t o m o t i v e S u p p l e m e n t
Au t o m o t ive -Gra d e Pro ASICPLUS Fla sh Fa m ily FPGAs
Table 9 • AC Specifications (3.3V PCI Revision 2.2 Operation)
Au t o m o t ive
Sym b o l Pa ra m e t e r
Co n d it io n
Min .
–12VCCI
Ma x.
Un it s
mA
*
IOH(AC) Switching Current High 0 < VOUT ≤ 0.3VCCI
*
0.3VCCI ≤ VOUT < 0.9VCCI
(–17.1 + (VDDP – VOUT))
mA
*
0.7VCCI < VOUT < VCCI
See equation C – page 124 of
the PCI Specification
document rev. 2.2
*
(Test Point)
V
OUT = 0.7VCC
–32VCCI
mA
mA
mA
*
IOL(AC)
Switching Current Low VCCI > VOUT ≥ 0.6VCCI
16VDDP
1
0.6VCCI > VOUT > 0.1VCCI
(26.7VOUT
)
0.18VCCI > VOUT > 0*
See equation D – page 124 of
the PCI Specification
document rev. 2.2
(Test Point)
VOUT = 0.18VCC
38VCCI
mA
mA
mA
V/ns
V/ns
ICL
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
ICH
VCCI + 4 > VIN ≥ VCCI + 1
0.2VCCI to 0.6VCCI load*
0.6VCCI to 0.2VCCI load*
25 + (VIN – VDDP – 1)/0.015
slewR
slewF
1
1
4
4
Note: * Refer to the PCI Specification document rev. 2.2.
Pad Loading Applicable to the Rising Edge PCI
pin
1/2 in. max
output
buffer
10 pF
1kΩ
Pad Loading Applicable to the Falling Edge PCI
pin
1kΩ
output
buffer
10 pF
Au t o m o t iv e Su p p le m e n t
9
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
2061 Stierlin Court
Mountain View, CA
94043-4655 USA
Dunlop House, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
39th Floor, One Pacific Place
88 Queensway, Admiralty
Hong Kong
Phone 650.318.4200
Fax 650.318.4600
Phone +44 (0)1276.401450
Fax +44 (0)1276.401490
Phone +81.03.3445.7671
Fax +81.03.3445.7668
Phone 852.227.35712
Fax 852.227.35999
51700051-0/2.04
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