APA300-FFG144I [ACTEL]

Field Programmable Gate Array, 180MHz, 8192-Cell, CMOS, PBGA144,;


型号：	APA300-FFG144I
厂家：	Actel Corporation
描述：	Field Programmable Gate Array, 180MHz, 8192-Cell, CMOS, PBGA144, 栅
文件：	总70页 (文件大小：638K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

v 3 . 5

ProASIC^PLUSFlash Family FPGAs

•

High Performance, Low Skew, Splittable Global Network

100% Routability and Utilization

Features and Benefits

High Capacity

I/O

•

75,000 to 1 Million System Gates

27k to 198kbits of Two-Port SRAM

66 to 712 User I/Os

•

Schmitt-Trigger Option on Every Input

2.5V/3.3V Support with Individually-Selectable Voltage and

Slew Rate

•

Bidirectional Global I/Os

Reprogrammable Flash Technology

Compliance with PCI Specification Revision 2.2

Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant

Pin Compatible Packages across the ProASIC^PLUSFamily

•

0.22µ 4LM Flash-Based CMOS Process

Live at Power-Up, Single-Chip Solution

No Configuration Device Required

Retains Programmed Design during Power-Down/Up Cycles

Unique Clock Conditioning Circuitry

•

PLL with Flexible Phase, Multiply/Divide and Delay

Capabilities

Internal and/or External Dynamic PLL Configuration

Two LVPECL Differential Pairs for Clock or Data Inputs

Performance

•

3.3V, 32-Bit PCI (up to 50 MHz)

Two Integrated PLLs

External System Performance up to 150 MHz

•

Standard FPGA and ASIC Design Flow

Secure Programming

•

Flexibility with Choice of Industry-Standard Front-End Tools

Efficient Design through Frontend Timing and Gate Optimization

•

The Industry’s Most Effective Security Key (FlashLock™)

Prevents Read Back of Programming Bitstream

ISP Support

Low Pow er

•

In-System Programming (ISP) via JTAG Port

•

Low Impedance Flash Switches

Segmented Hierarchical Routing Structure

Small, Efficient, Configurable (Combinatorial or Sequential)

Logic Cells

SRAMs and FIFOs

•

ACTgen Netlist Generation Ensures Optimal Usage of

Embedded Memory Blocks

•

24 SRAM and FIFO Configurations with Synchronous and

Asynchronous Operation up to 150 MHz (typical)

High Performance Routing Hierarchy

•

Ultra-Fast Local and Long-Line Network

High Speed Very Long-Line Network

Table 1 • ProASIC^PLUSProduct Profile

De vice

APA075

75,000

3,072

APA150

150,000

6,144

APA300

300,000

8,192

APA450

450,000

12,288

108k

APA600

600,000

21,504

126k

APA750 APA1000

Maximum System Gates

Maximum Tiles (Registers)

750,000

32,768

144k

1,000,000

56,320

198k

Embedded RAM Bits

(k=1,024 bits)

27k

36k

72k

Embedded RAM Blocks (256x9)

LVPECL

PLL

Global Netw orks

Maximum Clocks

Maximum User I/Os

JTAG ISP

158

Yes

242

Yes

290

Yes

344

Yes

454

Yes

562

Yes

712

Yes

PCI

Package (by pin count)

TQFP

100, 144

208

100

208

–

PQFP

208

456

208

456

208

456

208

456

208

456

PBGA

–

456

FBGA

144

144, 256

144, 256 144, 256, 484 256, 484, 676 676, 896 896, 1152

Ap ril 2004

PLUS

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Ordering Information

APA1000

1152

Application (Ambient Temperature Range)

Blank = Commercial (0 to +70˚ C)

I = Industrial (-40 to +85˚ C)

PP = Pre-production

ES = Engineering Silicon (Room Temperature Only)

Package Lead Count

Package Type

Thin Quad Flat Pack (0.5mm pitch)

Plastic Quad Flat Pack (0.5mm pitch)

Fine Pitch Ball Grid Array (1.0mm pitch)

Plastic Ball Grid Array (1.27mm pitch)

Speed Grade

Blank

Standard Speed

= 20% Slower than Standard

Part Number

APA075 = 75,000 Equivalent System Gates

APA150 = 150,000 Equivalent System Gates

APA300 = 300,000 Equivalent System Gates

APA450 = 450,000 Equivalent System Gates

APA600 = 600,000 Equivalent System Gates

APA750 = 750,000 Equivalent System Gates

APA1000 = 1,000,000 Equivalent System Gates

Plastic Device Resources

Use r I/Os*

TQFP

PQFP

PBGA

FBGA

De vice

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

100-Pin

144-Pin

208-Pin

456-Pin

144-Pin

256-Pin

484-Pin

676-Pin

896-Pin 1152-Pin

107

158

100

242

290

344

356

186

344

370

454

562

642

712

Package Definitions

TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array

*Each pair of PECL I/Os were counted as one user I/O.

General Guideline

Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee

performance beyond the limits specified within the datasheet.

i i

v 3 . 5

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Temperature Grade Offerings

Pa cka g e

TQ100

TQ144

PQ208

BG456

FG144

FG256

FG484

FG676

FG896

FG1152

APA075

APA150

APA300

APA450

APA600

APA750 APA1000

C, I

Speed Grade and Temperature Matrix

-F

St d

v 3 . 5

iii

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Table of Contents

General Description

PLUS

ProASIC

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

Tristate Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37

Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39

Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40

Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41

Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41

Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-63

Recommended Design Practice for V /V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64

PN PP

Package Pin Assignments

100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

v3.5

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General Description

The ProASIC^PLUSfamily of devices, Actel’s second

generation Flash FPGAs, offers enhanced performance

over Actel’s ProASIC family. It combines the advantages

of ASICs with the benefits of programmable devices

through nonvolatile Flash technology. This enables

engineers to create high-density systems using existing

ASIC or FPGA design flows and tools. In addition, the

ProASIC^PLUSfamily offers a unique clock conditioning

circuit based on two on-board phase-locked loops (PLLs).

The family offers up to 1 million system gates, supported

with up to 198kbits of two-port SRAM and up to 712 user

I/Os, all providing 50 MHz PCI performance.

combination of fine granularity, flexible routing

resources, and abundant Flash switches allow 100%

utilization and over 95% routability for highly congested

designs. Tiles and larger functions are interconnected

through a four-level routing hierarchy.

Embedded two-port SRAM blocks with built-in FIFO/RAM

control logic can have user-defined depth and width.

Users can also select programming for synchronous or

asynchronous operation, as well as parity generations or

checking.

The unique clock conditioning circuitry in each device

includes two clock conditioning blocks. Each block

provides a PLL core, delay lines, phase shifts (0° , 90° ,

180° , 270° ), and clock multipliers/dividers, as well as the

circuitry needed to provide bidirectional access to the

PLL. The PLL block contains four programmable

frequency dividers, which allow the incoming clock

signal to be divided by a wide range of factors from 1 to

64. The clock conditioning circuit also delays or advances

the incoming reference clock up to 8 ns (in increments of

0.25 ns). The PLL can be configured internally or

externally during operation without redesigning or

reprogramming the part. In addition to the PLL, there

are two LVPECL differential input pairs to accommodate

high speed clock and data inputs.

Advantages

the

designer

extend

beyond

performance. Unlike SRAM-based FPGAs, four levels of

routing hierarchy simplify routing, while the use of Flash

technology allows all functionality to be live at power-

up. No external boot PROM is required to support device

programming. While on-board security mechanisms

prevent

access

the

program

information,

reprogramming can be performed in-system to support

future design iterations and field upgrades. The device’s

architecture mitigates the complexity of ASIC migration

at higher user volume. This makes ProASIC^PLUSa cost-

effective solution for applications in the networking,

communications, computing, and avionics markets.

The ProASIC^PLUSfamily achieves its nonvolatility and

reprogrammability through an advanced Flash-based

0.22µm LVCMOS process with four layers of metal.

Standard CMOS design techniques are used to

implement logic and control functions, including the

PLLs and LVPECL inputs. This results in predictable

performance compatible with gate arrays.

To support customer needs for more comprehensive,

lower cost, board-level testing, Actel’s ProASIC^PLUS

devices are fully compatible with IEEE Standard 1149.1

for test access port and boundary-scan test architecture.

For more information concerning the Flash FPGA

implementation, please refer to the "Boundary Scan

(JTAG)" section on page 1-10.

The ProASIC^PLUSarchitecture provides granularity

comparable to gate arrays. The device core consists of a

^Sea-of-Tilesꢀ. Each tile can be configured as a flip-flop,

latch, or three-input/one-output logic function by

programming the appropriate Flash switches. The

ProASIC^PLUSdevices are available in a variety of high-

performance plastic packages. Those packages and the

performance features discussed above are described in

more detail in the following sections.

v 3 . 5

1-1

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PLUS

Flash Sw itch

ProASIC

Architecture

Unlike SRAM FPGAs, ProASIC^PLUSuses a live-on-power-up

ISP Flash switch as its programming element.

The proprietary ProASIC^PLUSarchitecture provides

granularity comparable to gate arrays.

The ProASIC^PLUSdevice core consists of a Sea-of-Tiles

(Figure 1-1). Each tile can be configured as a three-input

logic function (e.g., NAND gate, D-Flip-Flop, etc.) by

In the ProASIC^PLUSFlash switch, two transistors share the

floating gate, which

stores the

programming

information. One is the sensing transistor, which is only

used for writing and verification of the floating gate

voltage. The other is the switching transistor. It can be

used in the architecture to connect/separate routing nets

or to configure logic. It is also used to erase the floating

gate (Figure 1-2 on page 1-3).

programming

the

appropriate

Flash

switch

interconnections (Figure 1-2 on page 1-3 and Figure 1-3

on page 1-3). Tiles and larger functions are connected

with any of the four levels of routing hierarchy. Flash

switches are distributed throughout the device to

provide

nonvolatile,

reconfigurable

interconnect

programming. Flash switches are programmed to

connect signal lines to the appropriate logic cell inputs

and outputs. Dedicated high-performance lines are

connected as needed for fast, low-skew global signal

distribution throughout the core. Maximum core

utilization is possible for virtually any design.

Logic Tile

The logic tile cell (Figure 1-3 on page 1-3) has three

inputs (any or all of which can be inverted) and one

output (which can connect to both ultra-fast local and

efficient long-line routing resources). Any three-input,

one-output logic function (except a three-input XOR) can

be configured as one tile. The tile can be configured as a

latch with clear or set or as a flip-flop with clear or set.

Thus, the tiles can flexibly map logic and sequential gates

of a design.

ProASIC^PLUSdevices also contain embedded, two-port

SRAM blocks with built-in FIFO/RAM control logic.

Programming

options

include

synchronous

asynchronous operation, two-port RAM configurations,

user defined depth and width, and parity generation or

checking. Please see the "Embedded Memory

Configurations" section on page 1-20 for more

information.

RAM Block

256x9 Two-Port SRAM

or FIFO Block

I/Os

Logic Tile

RAM Block

256x9 Two Port SRAM

or FIFO Block

Figure 1-1 • The ProASIC^PLUSDevice Architecture

1 -2

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Switch In

Switching

Floating Gate

Sensing

Word

Switch Out

Figure 1-2 • Flash Sw itch

Local Routing

Efficient Long-Line Routing

In 1

In 2 (CLK)

In 3 (Reset)

Figure 1-3 • Core Logic Tile

drive signals onto the efficient long-line resources, which

can in turn, access every input of every tile. Active buffers

are inserted automatically by routing software to limit

the loading effects due to distance and fanout.

Routing Resources

The routing structure of ProASIC^PLUSdevices is designed

to provide high performance through a flexible four-

level hierarchy of routing resources: ultra-fast local

resources, efficient long-line resources, high-speed, very

long-line resources, and high performance global

networks.

The high-speed, very long-line resources, which span the

entire device with minimal delay, are used to route very

long or very high fanout nets. (Figure 1-6 on page 1-5).

The high-performance global networks are low-skew,

high fanout nets that are accessible from external pins or

from internal logic (Figure 1-7 on page 1-6). These nets

are typically used to distribute clocks, resets, and other

high fanout nets requiring a minimum skew. The global

networks are implemented as clock trees, and signals can

be introduced at any junction. These can be employed

hierarchically with signals accessing every input on all

tiles.

The ultra-fast local resources are dedicated lines that

allow the output of each tile to connect directly to every

input of the eight surrounding tiles (Figure 1-4 on page

1-4).

The efficient long-line resources provide routing for

longer distances and higher fanout connections. These

resources vary in length (spanning 1, 2, or 4 tiles), run

both vertically and horizontally, and cover the entire

ProASIC^PLUSdevice (Figure 1-5 on page 1-4). Each tile can

v 3 . 5

1-3

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Inputs

Ultra-Fast

Local Lines

(connects a tile to the

adjacent tile, I/O buffer,

or memory block)

Figure 1-4 • Ultra-Fast Local Resources

Spans 4 Tiles

Spans 2 Tiles

Spans 1 Tile

Logic Tile

Spans 1 Tile

Spans 2 Tiles

Spans 4 Tiles

Logic Cell

Figure 1-5 • Efficient Long-Line Resources

1 -4

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High Speed Very Long-Line Resouces

PAD RING

SRAM

PAD RING

Figure 1-6 • High-Speed, Very Long-Line Resources

Clock Resources

Clock Trees

The ProASIC^PLUSfamily offers powerful and flexible

control of circuit timing through the use of analog

circuitry. Each chip has two clock conditioning blocks

containing a phase-locked loop (PLL) core, delay lines,

^{phase shifter (0}°, 90°, 180° , 270°), clock multiplier/

dividers and all the circuitry needed for the selection and

interconnection of inputs to the global network (thus

providing bidirectional access to the PLL). This permits

the PLL block to drive inputs and/or outputs via the two

global lines on each side of the chip (four total lines).

This circuitry is discussed in more detail in the

"ProASICPLUS Clock Management System" section on

page 1-12.

One of the main architectural benefits of ProASIC^PLUSis

the set of power and delay friendly global networks.

ProASIC^PLUSoffers four global trees. Each of these trees

is based on a network of spines and ribs that reach all

the tiles in their regions (Figure 1-7 on page 1-6). This

flexible clock tree architecture allows users to map up to

88 different internal/external clocks in an APA1000

device. Details on the clock spines and various numbers

of the family are given in Table 1-1 on page 1-6.

The flexible use of the ProASIC^PLUSclock spine allows the

designer to cope with several design requirements. Users

implementing clock-resource intensive applications can

easily route external or gated internal clocks using global

routing spines. Users can also drastically reduce delay

penalties and save buffering resources by mapping

critical high-fanout nets to spines. For design hints on

using these features, refer to Actel’s Efficient Use of

ProASIC Clock Trees application note.

v 3 . 5

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High Performace

Global Network

PAD RING

Top Spine

Global Networks

Global

Pads

Global

Pads

Global Spine

Global Ribs

Bottom Spine

Scope of Spine

(Shaded area

plus local RAMs

and I/Os)

PAD RING

Note: This figure shows routing for only one global path.

Figure 1-7 • High-Performance Global Netw ork

Table 1-1 • Clock Spines

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Global Clock Networks (Trees)

Clock Spines/Tree

Total Spines

Top or Bottom Spine Height (Tiles)

Tiles in Each Top or Bottom Spine

Total Tiles

512

3,072

768

6,144

1,024

8,192

1,024

12,288

1,536

21,504

2,048

32,768

2,560

56,320

1 -6

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Array Coordinates

During many place-and-route operations in Actel’s

Designer software tool, it is possible to set constraints

that require array coordinates.

cells and core cells. In addition, the I/O coordinate system

changes depending on the die/package combination.

Core cell coordinates start at the lower left corner (1,1)

or (1,5) if memories are present at the bottom. Memory

coordinates use the same system and are indicated in

Table 1-2. The memory coordinates for an APA1000 are

illustrated in Figure 1-8. For more information on how to

use constraints, see the Designer User’s Guide or online

help for ProASIC^PLUSsoftware tools.

Table 1-2 is provided as a reference. The array coordinates

are measured from the lower left (0,0). They can be used in

region constraints for specific groups, designated by a

wildcard, and containing core cells, I/Os, and memories.

I/O and cell coordinates are used for placement

constraints. Two coordinate systems are needed because

there is not a one-to-one correspondence between I/O

Table 1-2 • Array Coordinates

Lo g ic Tile

Me m o ry Ro w s

Min .

Ma x.

Bo t t o m

To p

All

De vice

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Min .

0,0

Ma x.

97, 37

–

(33,33) or (33, 35)

(49,49) or (49, 51)

(69,69) or (69, 71)

(101,101) or (101, 103)

(133,133) or (133, 135)

(165,165) or (165, 167)

128

192

224

256

352

–

129, 53

129, 73

193, 73

225, 105

257, 137

353, 169

(1,1) or (1,3)

100

132

164

Memory

Blocks

(1,169)

(1,167)

(1,165)

(1,164)

(353,169)

(352,167)

(352,165)

(352,164)

Core

(1,5)

(1,3)

(1,1)

(352,5)

(352,3)

(352,1)

(0,0)

(353,0)

Memory

Blocks

Figure 1-8 • Core Cell Coordinates for the APA1000

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Table 1-3 • ProASIC^PLUSI/O Pow er Supply Voltages

Input/Output Blocks

V_DDP

To meet complex system demands, the ProASIC^PLUS

family offers devices with a large number of user I/O

pins, up to 712 on the APA1000. If the I/O pad power

2.5V

3.3V

In p u t Co m p a t ib ilit y

Ou t p u t Drive

3.3V, 2.5V

3.3V, 2.5V¹

supply (V_DDP

configured at the 2.5V and 3.3V threshold levels¹.

Table 1-3 shows the available supply voltage

) is 3.3V, each I/O can be selectively

Note: V_DDis always 2.5V.

configurations (the PLL block uses an independent 2.5V

supply on the AVDD and AGND pins). All I/Os include ESD

protection circuits. Each I/O has been tested to 2000V to

the human body model (per JESD22 (HBM)).

3.3V/2.5V

Signal Control

Six or seven standard I/O pads are grouped with a GND

pad and either a V_DD(core power) or V_DDP(I/O power)

pad. Two reference bias signals circle the chip. One

protects the cascaded output drivers, while the other

creates a virtual V_DDsupply for the I/O ring.

Pull-up

Control

Pad

I/O pads are fully configurable to provide the maximum

flexibility and speed. Each pad can be configured as an

input, an output, a tristate driver, or a bidirectional

buffer (Figure 1-9 and Table 1-4).

3.3V/2.5V Signal Control Drive

Strength and Slew-Rate Control

Figure 1-9 • I/O Block Schematic Representation

De scrip t io n

Table 1-4 • I/O Features

Fu n ct io n

I/O pads configured as inputs

•

Individually selectable 2.5V or 3.3V threshold levels

Optional pull-up resistor

Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be

configured as an input only, not a bidirectional buffer. This input type may be slower than

a standard input under certain conditions and has a typical hysteresis of 0.35V. I/O macros

with an “S” in the standard I/O library have added Schmitt capabilities

•

3.3V PCI Compliant

I/O pads configured as outputs

Individually selectable 2.5V or 3.3V compliant output signals

2.5V – JEDEC JESD 8-5

3.3V – JEDEC JESD 8-A (LVTTL and LVCMOS)

3.3V PCI compliant

Ability to drive LVTTL and LVCMOS levels

Selectable drive strengths

Selectable slew rates

Tristate

I/O pads configured as bidirectional • Individually selectable 2.5V or 3.3V compliant output signals

buffers

•

2.5V – JEDEC JESD 8-5

3.3V – JEDEC JESD 8-A (LVTTL and LVCMOS)

3.3V PCI compliant

Optional pull-up resistor

Selectable drive strengths

Selectable slew rates

Tristate

1. Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC^PLUSFlash FPGAs application note for details.

1 -8

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low voltage differential amplifier) and a signal and its

complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).

The LVPECL input pad cell differs from the standard I/O

cell in that it is operated from V_DDonly.

Pow er-Up Sequencing

While ProASIC^PLUSdevices are live at power-up, the order

of V_DDand V_DDPpower-up is important during system

start-up. V_DDshould be powered up before (or

simultaneously with) V_DDPon ProASIC^PLUSdevices.

Failure to follow these guidelines may result in

undesirable pin behavior during system start-up. For

more information, refer to Actel’s ProASIC^PLUSFamily

Devices Power-Up Behavior application note.

Since it is exclusively an input, it requires no output

signal, output enable signal, or output configuration

bits. As a special high-speed differential input, it also

does not require pull ups. Recommended termination for

LVPECL inputs is shown in Figure 1-10. The LVPECL pad

cell compares voltages on the PPECL (I/P) pad (as

illustrated in Figure 1-11) and the NPECL pad and sends

the results to the global MUX (Figure 1-14 on page 1-13).

This high-speed, low-skew output essentially controls the

clock conditioning circuit.

LVPECL Input Pads

In addition to standard I/O pads and power pads,

ProASIC^PLUSdevices have a single LVPECL input pad on

both the east and west sides of the device, along with

AVDD and AGND pins to power the PLL block. The

LVPECL pad cell consists of an input buffer (containing a

LVPECLs are designed to meet LVPECL JEDEC receiver

standard levels (Table 1-5).

Z₀= 50Ω

PPECL

From LVPECL Driver

R = 100Ω

Data

Z ₀= 50Ω

NPECL

Figure 1-10 • Recommended Termination for LVPECL Inputs

Voltage

2.72

2.125

1.49

0.86

Figure 1-11 • LVPECL High and Low Threshold Values

Table 1-5 • LVPECL Receiver Specifications

Sym b o l

Pa ra m e t e r

Input High Voltage

Min .

Ma x

2.72

2.125

V_DD

Un it s

1.49

0.86

0.3

Input Low Voltage

Differential Input Voltage

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operation when no input data is supplied to them. These

pins are dedicated for boundary-scan test usage. Actel

recommends that a nominal 20kΩ pull-up resistor is

added to TDO and TCK pins.

Boundary Scan (JTAG)

ProASIC^PLUSdevices are compatible with IEEE Standard

1149.1, which defines a set of hardware architecture and

mechanisms for cost-effective, board-level testing. The

basic ProASIC^PLUSboundary-scan logic circuit is composed

of the TAP (test access port), TAP controller, test data

registers, and instruction register (Figure 1-12). This

circuit supports all mandatory IEEE 1149.1 instructions

(EXTEST, SAMPLE/PRELOAD and BYPASS) and the

optional IDCODE instruction (Table 1-6).

The TAP controller is a four-bit state machine (16 states)

that operates as shown in Figure 1-13 on page 1-11. The

’1’s and ‘0’s represent the values that must be present at

TMS at a rising edge of TCK for the given state transition

to occur. IR and DR indicate that the instruction register

or the data register is operating in that state.

ProASIC^PLUSdevices have to be programmed at least

once for complete boundary-scan functionality to be

available. If boundary-scan functionality is required prior

to partial programming, refer to online technical support

on the Actel website and search for ProASIC^PLUSBSDL.

Each test section is accessed through the TAP, which has

five associated pins: TCK (test clock input), TDI and TDO

(test data input and output), TMS (test mode selector)

and TRST (test reset input). TMS, TDI and TRST are

equipped with pull-up resistors to ensure proper

I/O

Test Data

Registers

Bypass Register

Instruction

TAP

Controller

Device

Logic

I/O

Figure 1-12 • ProASIC^PLUSJTAG Boundary Scan Test Logic Circuit

Table 1-6 • Boundary-Scan Opcodes

He x Op co d e

EXTEST

SAMPLE/PRELOAD

IDCODE

CLAMP

BYPASS

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The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals for the rest

of the test logic architecture. On power-up, the TAP

controller enters the Test-Logic-Reset state. To guarantee

a reset of the controller from any of the possible states,

TMS must remain high for five TCK cycles. The TRST pin

may also be used to asynchronously place the TAP

controller in the Test-Logic-Reset state.

ProASIC^PLUSdevices support three types of test data

registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other

test data transfer to other devices in a test data path.

The 32-bit device identification register is a shift register

with four fields (lowest significant byte (LSB), ID number,

part number and version). The boundary-scan register

observes and controls the state of each I/O pin.

Each I/O cell has three boundary-scan register cells, each

with a serial-in, serial-out, parallel-in, and parallel-out

pin. The serial pins are used to serially connect all the

boundary-scan register cells in a device into a boundary-

scan register chain, which starts at the TDI pin and ends

at the TDO pin. The parallel ports are connected to the

internal core logic tile and the input, output, and control

ports of an I/O buffer to capture and load data into the

Test-Logic

Reset

Run-Test/

Idle

Select-DR-

Scan

Select-IR-

Scan

Capture-DR

Capture-IR

Shift-IR

Shift-DR

Exit-DR

Exit-IR

Pause-DR

Pause-IR

Exit2-DR

Exit2-IR

Update-DR

Update-IR

Figure 1-13 • TAP Controller State Diagram

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unconnected. They default to an input with pull-up. The

two signals available to drive the global networks are as

follows (Figure 1-15 on page 1-14, Table 1-7 on page 1-

14, and Table 1-8 on page 1-15):

Timing Control and

Characteristics

PLUS

Global A (secondary clock)

ProASIC

Clock Management System

•

Output from Global MUX A

•

Conditioned version of PLL output (f_OUT) – delayed or

advanced

Introduction

ProASIC^PLUSdevices provide designers with very flexible

clock conditioning capabilities. Each member of the

ProASIC^PLUSfamily contains two phase-locked loop (PLL)

blocks which perform the following functions:

•

Divided version of either of the above

Further delayed version of either of the above (0.25

ns, 0.50 ns, or 4.00 ns delay)²

•

Clock Phase Adjustment via Programmable Delay

(250 ps steps from –8 ns to +8 ns)

Global B

•

Output from Global MUX B

•

Clock Skew Minimization

Clock Frequency Synthesis

Delayed or advanced version of f_OUT

Divided version of either of the above

Each PLL has the following key features:

Further delayed version of either of the above

(0.25 ns, 0.50 ns, or 4.00 ns delay)¹

•

Input Frequency Range (f_IN) = 1.5 to 180 MHz

Feedback Frequency Range (f_VCO) = 1.5 to 180 MHz

Output Frequency Range (f_OUT) = 6 to 180 MHz

Output Phase Shift = 0 °, 90 °, 180 °, and 270 °

Output Duty Cycle = 50%

Functional Description

Each PLL block contains four programmable dividers as

shown in Figure 1-14 on page 1-13. These allow

frequency scaling of the input clock signal as follows:

Low Output Jitter (max at 25°C)

•

The n divider divides the input clock by integer

factors from 1 to 32.

–

f_VCO<10 MHz. Jitter ±1% or better

10 MHz < f_VCO< 60 MHz. Jitter ±2% or better

f_VCO> 60 MHz. Jitter ±1% or better

•

The

divider in the feedback path allows

multiplication of the input clock by integer factors

ranging from 1 to 64.

Note: Jitter(ps) = Jitter(%)*(1/Frequency (MHz)) * 10,000)

For Example:

•

The two dividers together can implement any

combination of multiplication and division resulting

in a clock frequency between 24 and 180 MHz exiting

the PLL core. This clock has a fixed 50% duty cycle.

Jitter in picoseconds at 100 MHz = 1(%)*(1/10 MHz)*10,000

= 100 ps

The output frequency of the PLL core is given by the

following formula (f_REFis the reference clock

frequency):

•

Maximum Acquisition Time = 80µs for Fvco > 40MHz

= 30µs for Fvco < 40MHz

•

Low Power Consumption – 6.9 mW (max – analog

supply) + 7.0µW/MHz (max – digital supply)

_OUT= f_REF* m/n

•

The third and fourth dividers (u and v) permit the

signals applied to the global network to each be

further divided by integer factors ranging from 1 to 4.

Physical Implementation

Each side of the chip contains a clock conditioning circuit

based upon a 180 MHz PLL block (Figure 1-14 on page 1-

13). Two global multiplexed lines extend along each side

of the chip to provide bidirectional access to the PLL on

that side (neither MUX can be connected to the opposite

side's PLL). Each global line has optional LVPECL input

pads (described below). The global lines may be driven

by either the LVPECL global input pad or the outputs

from the PLL block or both. Each global line can be

driven by a different output from the PLL. Unused global

pins can be configured as regular I/Os or left

The implementations:

_GLB= m/(n*u)

f_GLA= m/(n*v)

enable the user to define a wide range of frequency

multipliers and divisors. The clock conditioning circuit can

advance or delay the clock up to 8 ns (in increments of

0.25 ns) relative to the positive edge of the incoming

reference clock. The system also allows for the selection of

output frequency clock phases of 0°, 90°, 180°, and 270°.

2. This mode is available through the delay feature of the Global MUX driver.

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Prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global

network. These units permit the delaying of global signals relative to other signals to assist in the control of input set-

up times. Not all possible combinations of input and output modes can be used. The degrees of freedom available in

the bidirectional global pad system and in the clock conditioning circuit have been restricted. This avoids unnecessary

and unwieldy design kit and software work.

AVDD AGND

GND

GLA

GLB

Global MUX B OUT

Input Pins to the PLL

See Figure 15

Clock Conditioning

Circuitry

(Top level view)

External Feedback Signal

Global MUX A OUT

Flash

Configuration Bits

Dynamic

on page 15

Configuration Bits

Clock Conditioning Circuitry Detailed Block Diagram

CLK

Bypass Primary

OBMUX[2:0]

P+

P-

FIVDIV[4:0]

DLYB[1:0]

Delay Line 0.0ns, 0.25ns,

0.50ns and 4.00ns

270˚

180˚

90˚

0˚

÷n

GLB

PLL Core

÷u

÷m

OBDIV[1:0]

FBDIV[5:0]

Clock from Core

(GLINT mode)

Delay Line

0.25ns to

4.00ns,

16 steps,

0.25ns

increments

Deskew

Delay

2.95 ns

OADIV[1:0]

XDLYSEL

÷v

EXTFB

Delay Line 0.0ns, 0.25ns,

0.50ns and 4.00ns

DLYA[1:0]

FBDLY[3:0]

GLA

FBSEL[1:0]

OAMUX[1:0]

CLKA

Bypass Secondary

Clock from Core

(GLINT mode)

1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.

2. DLYA, DLYB, DLYAFB are programmable delay lines, each with selectable values 0, 250 ps, 500 ps, and 4 ns.

3. OBDIV will also divide the phase-shift since it takes place after the PLL Core.

Figure 1-14 • PLL Block – Top-Level View and Detailed PLL Block Diagram

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Package Pins

Physical I/O

Global MUX

Buffers

Configuration Tile

Std. Pad Cell

Global MUX B

OUT

NPECL

PECL Pad Cell

PPECL

External

Feedback

Global MUX A

OUT

GLMX

Std. Pad Cell

Configuration Tile

CORE

Legend

Physical Pin

DATA Signals to the Global MUX

DATA Signals to the Core

Control Signals to the Global MUX

DATA Signals to the PLL Block

Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time.

Figure 1-15 • Input Connectors to ProASIC^PLUSClock Conditioning Circuitry

Table 1-7 • Clock-Conditioning Circuitry MUX Settings

MUX

Da t a p a t h

Co m m e n t s

FBSEL

Internal Feedback

Internal Feedback and Advance Clock Using FBDLY

External Feedback (EXTFB)

–0.25 to –4 ns in 0.25ns increments

XDLYSEL

Feedback Unchanged

Deskew feedback by advancing clock by system delay

GLB

Fixed delay of -2.95 ns

OBMUX

Primary bypass, no divider

Primary bypass, use divider

Delay Clock Using FBDLY

Phase Shift Clock by 0°

Phase Shift Clock by +90°

Phase Shift Clock by +180°

Phase Shift Clock by +270°

GLA

+0.25 to +4 ns in 0.25ns increments

OAMUX

Secondary bypass, no divider

Secondary bypass, use divider

Delay Clock Using FBDLY

Phase Shift Clock by 0°

+0.25 to +4 ns in 0.25ns increments

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Table 1-8 • Clock-Conditioning Circuitry Delay-Line Settings

used, a given ratio can be generated in multiple ways,

allowing the user to stay within the operating frequency

ranges of the PLL. For example, in this case the input

divider could have been two and the output divider also

two, giving us a division of the input frequency by four

to go with the feedback loop division (effective

multiplication) by five.

De la y Lin e

De la y Va lu e (n s)

DLYB

+0.25

+0.50

+4.0

DLYA

Adjustable Clock Delay

Figure 1-18 on page 1-17 illustrates the delay of the

input clock by employing one of the adjustable delay

lines. This is easily done in ProASIC^PLUSby bypassing the

PLL core entirely and using the output delay line. Notice

also that the output clock can be effectively advanced

relative to the input clock by using the delay line in the

feedback path. This is shown in Figure 1-19 on page 1-17.

+0.25

+0.50

+4.0

Lock Signal

An active-high Lock signal (added via the ACTgen PLL

development tool) indicates that the PLL has locked to

the incoming clock signal. Users can employ the Lock

signal as a soft reset of the logic driven by GLB and/or

GLA. Note if F_INis not within specified frequencies then

both the F_OUTand lock signal are indeterminate.

Clock Skew Minimization

Figure 1-20 on page 1-18 indicates how feedback from

the clock network can be used to create minimal skew

between the distributed clock network and the "input"

clock. The input clock is fed to the reference clock input

of the PLL. The output clock (GLA) feeds a clock network.

The feedback input to the PLL uses a clock input delayed

by a routing network. The PLL then adjusts the phase of

the input clock to match the delayed clock, thus

providing nearly zero effective skew between the two

clocks. Refer to Actel's Using ProASIC^PLUSClock

Conditioning Circuits application note for more

information.

PLL Configuration Options

The PLL can be configured during design (via Flash-

configuration bits set in the programming bitstream) or

dynamically during device operation, thus eliminating

the need for complete reprogramming. The dynamic

configuration bits are loaded into a serial-in/parallel-out

shift register provided in the clock conditioning circuit of

each PLL and then latched into the PLL block. The JTAG

ports can be used along with a built-in user JTAG

interface hardware to load the configuration shift

configuration via user-designed hardware. Refer to

Actel's ProASIC^PLUSPLL Dynamic Reconfiguration Using

JTAG application note for more information.

Logic Tile Timing Characteristics

Timing characteristics for ProASIC^PLUSdevices fall into

three categories: family dependent, device dependent,

and design dependent. The input and output buffer

characteristics are common to all ProASIC^PLUSfamily

members. Internal routing delays are device dependent.

Design dependency means that actual delays are not

determined until after placement and routing of the

user’s design are complete. Delay values may then be

determined by using the Timer utility or performing

simulation with post-layout delays.

For information on the clock conditioning circuit, refer

to Actel’s Using ProASIC^PLUSClock Conditioning Circuits

application note.

Sample Implementations

Frequency Synthesis

Critical Nets and Typical Nets

Figure 1-16 on page 1-16 illustrates an example where

the PLL is used to multiply a 33 MHz external clock up to

133 MHz. Figure 1-17 on page 1-16 uses two dividers to

synthesize a 50 MHz output clock from a 40 MHz input

reference clock. The input frequency of 40 MHz is

multiplied by five and divided by four, giving an output

clock (GLB) frequency of 50 MHz. When dividers are

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most timing

critical paths. Critical nets are determined by net

property assignment prior to placement and routing.

Refer to the Actel Designer User’s Guide or online help

for details on using constraints.

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Timing Derating

Since ProASIC^PLUSdevices are manufactured with a CMOS process, device performance will vary with temperature,

voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating

temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage,

maximum operating temperature, and worst-case process variations (within process specifications).

÷1

Global MUX B OUT

33 MHz

÷n

270

180

GLB

PLL Core

÷u

÷1

133 MHz

÷m

÷4

External Feedback

Global MUX A OUT

÷v

GLA

Figure 1-16 • Using the PLL 33 MHz In, 133 MHz Out

÷4

Global MUX B OUT

40 MHz

÷n

270

180

GLB

PLL Core

÷u

÷1

50 MHz

÷m

÷5

External Feedback

Global MUX A OUT

÷v

GLA

Figure 1-17 • Using the PLL 40 MHz In, 50 MHz Out

1 -1 6

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÷1

÷n

Global MUX B OUT

133 MHz

270

180

GLB

PLL Core

÷u

÷1

133 MHz

÷m

÷1

External Feedback

Global MUX A OUT

÷v

GLA

Figure 1-18 • Using the PLL to Delay the Input Clock

÷1

Global MUX B OUT

133 MHz

÷n

270

180

GLB

PLL Core

÷u

÷1

133 MHz

÷m

÷1

External Feedback

Global MUX A OUT

÷v

GLA

Figure 1-19 • Using the PLL to "Advance" the Input Clock

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÷1

÷n

Global MUX B OUT

270

180

GLB

133 MHz

PLL Core

÷u

÷1

÷m

÷1

External Feedback

Global MUX A OUT

133 MHz

÷v

GLA

SET

CLR

Figure 1-20 • Using the PLL for Clock Deskew ing

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PLL Electrical Specifications

Pa ra m e t e r

Va lu e

No t e s

Fre q u e n cy Ra n g e s

Reference Frequency f_IN(min.)

Reference Frequency f_IN(max.)

OSC Frequency f_VCO(min.)

OSC Frequency f_VCO(max.)

Clock Conditioning Circuitry f_OUT(min.)

Clock Conditioning Circuitry f_OUT(max.)

Lo n g Te rm Jit t e r Pe a k-t o -Pe a k Ma x.*

Te m p e ra t u re

1.5 MHz

180 MHz

24 MHz

180 MHz

6 MHz

Clock conditioning circuitry (min.) lowest input frequency

Clock conditioning circuitry (max.) highest input frequency

Lowest output frequency voltage controlled oscillator

Highest output frequency voltage controlled oscillator

Lowest output frequency clock conditioning circuitry

Highest output frequency clock conditioning circuitry

180 MHz

Fre q u e n cy MHz

_VCO<10

10<f_VCO<60 f_VCO>60

25°C (or higher)

±1%

±2%

±1%

Jitter(ps) = Jitter(% )*(1/Frequency (MHz) * 1000

For Example:

Jitter in picoseconds at 1 MHz

= 1(% )*(10/1 (MHz)) = 10ps

0°C

±1.5%

±2.5%

±3.5%

±1%

–40°C

Acq u isit io n Tim e fro m Co ld St a rt

Acquisition Time (max.)

Po w e r Co n su m p t io n

Analog Supply Power (max^*)

Digital Supply Current (max)

Du t y Cycle

³⁰µs

80 µs

f_VCO≤40 MHz

f_VCO> 40 MHz

6.9 mW

7 µW/MHz

50% ±0.5%

Note: *High clock frequencies (>60 MHz) under typical set up conditions

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Each memory can be configured as FIFO or SRAM, with

independent selection of synchronous or asynchronous

User Security

ProASIC^PLUSdevices have FlashLock protection bits that,

once programmed, block the entire programmed

contents from being read externally. Please refer to

Table 1-9 for details on the number of bits in the key for

each device. If locked, the user can only reprogram the

device employing the user-defined security key. This

protects the device from being read back and duplicated.

Since programmed data is stored in nonvolatile memory

cells (which are actually very small capacitors), rather

than in the wiring, physical deconstruction cannot be

used to compromise data. This approach is further

hampered by the placement of the memory cells

beneath the four metal layers (whose removal cannot be

accomplished without disturbing the charge in the

capacitor). This is the highest security provided in the

industry. For more information, refer to Actel’s Design

Security in Nonvolatile Flash and Antifuse FPGAs white

paper.

read

and

write

ports (Table 1-11). Additional

characteristics include programmable flags as well as

parity checking and generation. Figure 1-21 on page 1-

22 and Figure 1-22 on page 1-23 show the block

diagrams of the basic SRAM and FIFO blocks. Table 1-12

on page 1-22 and Table 1-13 on page 1-23 describe

memory block SRAM and FIFO interface signals,

respectively. A single memory is designed to operate at

up to 150 MHz (standard speed grade typical conditions).

Each block contains a 256 word, 9-bit wide (1 read port, 1

write port) memory. The memory blocks may be

combined in parallel to form wider memories or stacked

to form deeper memories (Figure 1-23 on page 1-24).

This provides optimal bit widths of 9 (1 block), 18, 36,

and 72, and optimal depths of 256, 512, 768, and 1,024.

Refer to Actel’s ACTgen User’s Guide for more

information.

Figure 1-24 on page 1-24 gives an example of optimal

memory usage. Ten blocks with 23,040 bits have been

used to generate three memories of various widths and

depths. Figure 1-25 on page 1-24 shows how memory

can be used in parallel to create extra read ports. In this

example, using only 10 of the 88 available blocks of the

APA1000 yields an effective 6,912 bits of multiple port

memories. The Actel ACTgen software facilitates

building wider and deeper memories for optimal

memory usage.

Embedded Memory Floorplan

The embedded memory is located across the top and

bottom of the device in 256x9 blocks (Figure 1-1 on page

1-2). Depending upon the device, up to 88 blocks are

available to support a variety of memory configurations.

Each block can be programmed as an independent

memory or combined (using dedicated memory routing

resources) to form larger, more complex memories. A

single memory configuration could include blocks from

both the top and bottom memory locations.

Table 1-9 • Flashlock Key Size by Device

De vice

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Ke y Size

79 bits

Embedded Memory Configurations

79 bits

The embedded memory in the ProASIC^PLUSfamily

provides great configuration flexibility (Table 1-10).

Unlike many other programmable vendors, each

ProASIC^PLUSblock is designed and optimized as a two-

port memory (1 read, 1 write). This provides 198kbits of

total memory for two-port and single port usage in the

APA1000 device.

79 bits

119 bits

167 bits

191 bits

263 bits

Table 1-10 • ProASIC^PLUSMemory Configurations by Device

Ma xim u m Wid t h

Ma xim u m De p t h

De vice

APA075

APA150

APA300

APA450

APA600

APA750

APA1000

Bo t t o m

To p

256

108

144

216

252

288

396

1,536

2,048

3,072

3,584

4,096

5,632

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Table 1-11 • Basic Memory Configurations

Writ e Acce ss

Asynchronous

Typ e

RAM

FIFO

Re a d Acce ss

Asynchronous

Pa rit y

Lib ra ry Ce ll Na m e

RAM256x9AA

Checked

Asynchronous

Synchronous

Asynchronous

Synchronous

Asynchronous

Generated

Checked

RAM256x9AAP

RAM256x9AST

RAM256x9ASTP

RAM256x9ASR

RAM256x9ASRP

RAM256x9SA

RAM256xSAP

RAM256x9SST

RAM256x9SSTP

RAM256x9SSR

RAM256x9SSRP

FIFO256x9AA

FIFO256x9AAP

FIFO256x9AST

FIFO256x9ASTP

FIFO256x9ASR

FIFO256x9ASRP

FIFO256x9SA

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

Synchronous Transparent

Synchronous Pipelined

Asynchronous

Generated

Checked

Generated

Checked

Asynchronous

Generated

Checked

FIFO256x9SAP

FIFO256x9SST

FIFO256x9SSTP

FIFO256x9SSR

FIFO256x9SSRP

Synchronous Transparent

Synchronous Pipelined

Generated

Checked

Generated

v 3 . 5

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DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

DO <0:8>

RADDR <0:7>

DI <0:8>

WADDR <0:7>

SRAM

(256 X 9)

SRAM

(256 X 9)

WRB

WBLKB

Async Write

RDB

WRB

Sync Write &

Sync Read

Ports

RBLKB

RCLKS

RBLKB

RCLKS

Async Read

Ports

WCLKS

WBLKB

WPE

RPE

WPE

PARODD

DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

DI <0:8>

WADDR <0:7>

DO <0:8>

RADDR <0:7>

SRAM

(256 X 9)

SRAM

(256 X 9)

WRB

WBLKB

WRB

Sync Write

RDB

RBLKB

Async Write

WBLKB

RBLKB

Async Read

Sync Read

WCLKS

WPE

Ports

RCLKS

Ports

RPE

WPE

PARODD

Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These

DMUX cells do not consume any core logic tiles and connect directly to high speed routing resources between the memory blocks.

They are used when memories are cascaded and are automatically inserted by the software tools.

Figure 1-21 • Example SRAM Block Diagrams

Table 1-12 • Memory Block SRAM Interface Signals

De scrip t io n

Write clock used on synchronization on write side

Read clock used on synchronization on read side

Read address

SRAM Sig n a l

WCLKS

RCLKS

Bit s

In /Ou t

RADDR<0:7>

RBLKB

Read block select (active LOW)

RDB

Read pulse (active LOW)

WADDR<0:7>

WBLKB

DI<0:8>

WRB

Write address

Write block select (active LOW)

Input data bits <0:8>, <8> can be used for parity in

Write pulse (active LOW)

DO<0:8>

RPE

OUT

Output data bits <0:8>, <8> can be used for parity out

Read parity error (active HIGH)

WPE

Write parity error (active HIGH)

PARODD

Selects odd parity generation/detect when high, even when low

Note: Not all signals shown are used in all modes.

1 -2 2

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DI<0:8>

LEVEL<0:7>

LGDEP<0:2>

DI<0:8>

LEVEL<0:7>

LGDEP<0:2>

DO <0:8>

WPE

RPE

WRB

WBLKB

WRB

WBLKB

FIFO

(256 X 9)

Sync Write &

Sync Read

Ports

FIFO

RPE

(256 X 9)

Sync Write &

Async Read

Ports

FULL

EMPTY

FULL

EMPTY

RDB

RBLKB

RDB

RBLKB

EQTH

PARODD

GEQTH

WCLKS

RESET

RCLKS

RESET

DI <0:8>

LEVEL <0:7>

LGDEP<0:2>

DI <0:8>

LEVEL <0:7>

LGDEP<0:2>

DO <0:8>

WPE

DO <0:8>

WRB

WBLKB

WRB

WBLKB

WPE

RPE

FIFO

(256 X 9)

Async Write &

Sync Read

Ports

FIFO

(256 X 9)

Async Write &

Async Read

Ports

RPE

FULL

EMPTY

RDB

RBLKB

EMPTY

EQTH

RDB

PARODD

RBLKB

GEQTH

RESET

RCLKS

GEQTH

PARODD

RESET

Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These

DMUX cells do not consume any core logic tiles and connect directly to high speed routing resources between the memory blocks.

They are used when memories are cascaded and are automatically inserted by the software tools.

Figure 1-22 • Basic FIFO Block Diagrams

Table 1-13 • Memory Block FIFO Interface Signals

FIFO Sig n a l

WCLKS

Bit s

In /Ou t

De scrip t io n

Write clock used for synchronization on write side

Read clock used for synchronization on read side

Direct configuration implements static flag logic

Read block select (active LOW)

RCLKS

LEVEL <0:7>

RBLKB

RDB

Read pulse (active LOW)

RESET

Reset for FIFO pointers (active LOW)

WBLKB

Write block select (active LOW)

DI<0:8>

WRB

Input data bits <0:8>, <8> will be generated if PARGEN is true

Write pulse (active LOW)

FULL, EMPTY

EQTH, GEQTH

OUT

FIFO flags. FULL prevents write and EMPTY prevents read

EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.

GEQTH is true when the FIFO holds (LEVEL) words or more

DO<0:8>

RPE

OUT

Output data bits <0:8>

Read parity error (active HIGH)

WPE

Write parity error (active HIGH)

Configures DEPTH of the FIFO to 2 ^(LGDEP+1)

LGDEP <0:2>

PARODD

Parity generation/detect – Even when low, odd when high

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Word Width

256

Word

Depth

256

88 blocks

Figure 1-23 • APA1000 Memory Block Architecture

Word Width

Word

256

256 256

Depth

256 w ords x 18 bits, 1 read, 1 w rite

256

512 w ords x 18 bits, 1 read, 1 w rite

256

1,024 w ords x 9 bits, 1 read, 1 w rite

Total Memory Blocks Used = 10

Total Memory Bits = 23,040

Figure 1-24 • Example Show ing Memories w ith Different Widths and Depths

Word Width

Write Port

Word

Depth

256 256

256 256 256 256

Read Ports

256 w ords x 9 bits, 2 read, 1 w rite

Read Ports

512 w ords x 9 bits, 4 read, 1 w rite

Total Memory Blocks Used = 10

Total Memory Bits = 6,912

Figure 1-25 • Multiport Memory Usage

1 -2 4

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Design Environment

The ProASIC^PLUSfamily of FPGAs is fully supported by

both Actel's Libero™ Integrated Design Environment

(IDE) and Designer FPGA Development software. Actel

Libero IDE is an integrated design manager that

seamlessly integrates design tools while guiding the user

through the design flow, managing all design and log

files, and passing necessary design data among tools.

Additionally, Libero IDE allows users to integrate both

schematic and HDL synthesis into a single flow and verify

the entire design in a single environment (see the Libero

IDE Flow diagram located on Actel’s website). Libero IDE

includes Synplify^®AE from Synplicity®, ViewDraw^®AE

from Mentor Graphics^®, ModelSim^®HDL Simulator from

Mentor Graphics, WaveFormer Lite™ AE from

SynaptiCAD^®, PALACE™ AE Physical Synthesis from

Magma, and Designer software from Actel.

With the Designer software, a user can lock the design

pins before layout while minimally impacting the results

of place-and-route. Additionally, Actel’s back-annotation

flow is compatible with all the major simulators. Another

tool included in the Designer software is the ACTgen

macro builder, which easily creates popular and

commonly used logic functions for implementation into

your schematic or HDL design.

Actel's Designer software is compatible with the most

popular FPGA design entry and verification tools from

EDA vendors, such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

PALACE is an effective tool when designing with

ProASICPLUS. PALACE AE Physical Synthesis from Magma

takes an EDIF netlist and optimizes the performance of

ISP

The user can generate *.bit or *.stp programming files

from the Designer software and can use these files to

program a device.

ProASICPLUS devices through

a physical placement

driven process, ensuring that timing closure is easily

achieved.

ProASIC^PLUSdevices can be programmed in system. For

more information on ISP of ProASIC^PLUSdevices, refer to

the In-System Programming ProASIC^PLUSDevices and

Performing Internal In-System Programming Using Actel’s

ProASIC^PLUSDevices application notes. Prior to being

programmed for the first time, the ProASIC^PLUSdevice I/Os

are in a tristate condition with the pull-up resistor option

enabled.

Actel's Designer software is a place-and-route tool and

provides a comprehensive suite of back-end support

tools for FPGA development. The Designer software

includes the following:

•

Timer – a world-class integrated static timing analyzer

and constraints editor which support timing-driven

place-and-route

•

NetlistViewer – a design netlist schematic viewer

ChipPlanner – a graphical floorplanner viewer and editor

SmartPower – allows the designer to quickly estimate

the power consumption of a design

•

PinEditor – a graphical application for editing pin

assignments and I/O attributes

I/O Attribute Editor – displays all assigned and

unassigned I/O macros and their attributes in

spreadsheet format

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Related Documents

Application Notes

Efficient Use of ProASIC Clock Trees

http://www.actel.com/documents/clocktree.pdf

I/O Features in ProASIC^PLUSFlash FPGAs

http://www.actel.com/documents/PAPLUSLVPECL.pdf

ProASIC^PLUSFamily Devices Power-Up Behavior

http://www.actel.com/documents/PAPLUS_PowerUp.pdf

ProASIC^PLUSPLL Dynamic Reconfiguration Using JTAG

http://www.actel.com/documents/

PAPLUSPLLdynamicAN.pdf

Using ProASIC^PLUSClock Conditioning Circuits

http://www.actel.com/documents/PAPLUSPLLan.pdf

In-System Programming ProASIC^PLUSDevices

http://www.actel.com/documents/External_ISP_AN.pdf

Performing Internal In-System Programming Using

Actel’s ProASIC^PLUSDevices

http://www.actel.com/documents/PAplusISPAN.pdf

White Paper

Design Security in Nonvolatile Flash and Antifuse FPGAs

http://www.actel.com/documents/DesignSecurity.pdf

User’s Guide

Designer User’s Guide

http://www.actel.com/documents/designerUG.pdf

ACTgen User’s Guide

http://www.actel.com/documents/genguide.pdf

Flash Macro Library Guide

http://www.actel.com/documents/PA_libguide.pdf

1 -2 6

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A package’s maximum allowed power (P) is a function of

maximum junction temperature (T_J), maximum ambient

operating temperature (T_A), and junction-to-ambient

Package Thermal Characteristics

The ProASIC^PLUSfamily is available in several package

types with a range of pin counts. Actel has selected

packages based on high pin count, reliability factors, and

superior thermal characteristics.

thermal resistance Θ . Maximum junction temperature is

the maximum allowable temperature on the active

surface of the IC and is 110° C. P is defined as:

Thermal resistance defines the ability of a package to

conduct heat away from the silicon, through the

package to the surrounding air. Junction-to-ambient

thermal resistance is measured in degrees Celsius/Watt

T_J– T_A

P = ------------------

Θ_ja

is a function of the rate (in linear feet per minute –

and is represented as Theta ja (Θ ). The lower the

thermal resistance, the more efficiently a package will

dissipate heat.

lfpm) of airflow in contact with the package. When the

estimated power consumption exceeds the maximum

allowed power, other means of cooling, such as

increasing the airflow rate, must be used.

Table 1-14 • Package Thermal Characteristics

θ_ja

1.0 m /s

2.5 m /s

Pla st ic Pa cka g e s

Pin Co u n t

100

θ_jc

14.0

11.0

8.0

3.8

3.0

3.8

3.2

2.4

1.8

St ill Air

33.5

26.1

16.2

15.6

26.9

26.6

18.0

20.5

16.4

13.6

12.0

200 ft ./m in . 500 ft ./m in .

Un it s

°C/W

Thin Quad Flat Pack (TQFP)

Plastic Quad Flat Pack (PQFP)

PQFP with Heatspreader

27.4

28.0

22.5

13.3

12.5

22.9

22.8

14.7

17.0

13.0

10.4

8.9

25.0

25.7

20.8

11.9

11.6

21.5

13.6

15.9

12.0

9.4

144

208

Plastic Ball Grid Array (PBGA)

Fine Pitch Ball Grid Array (FBGA)

Fine Pitch Ball Grid Array (FBGA)¹

Fine Pitch Ball Grid Array (FBGA)²

Fine Pitch Ball Grid Array (FBGA)

456

144

256

484

676

896

1152

7.9

Notes:

1. Depopulated Array

2. Full Array

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where:

Calculating Typical Pow er

Dissipation

•

1.4 µW/MHz, is the average power

consumption of a logic tile per MHz of its

output toggling rate. The maximum output

toggling rate is Fs/2

ProASIC^PLUSdevice power is calculated with both a static

and an active component. The active component is a

function of both the number of tiles utilized and the

system speed. Power dissipation can be calculated using

the following formula:

•

the number of logic tiles switching during

each Fs cycle

the clock frequency

P_total= P_dc+ P_ac

_outputs, the I/O component of AC power dissipation, is

where:

given by

P_outputs= (P4 + (C_load* V_DDP²)) * p * Fp

•

P_dc

12.5 mW (Typically 2.5V x 5mA)

_dcincludes the static components of:

_VDDP+ P_VDD+ P_AVDD

where:

•

326 µW/MHz is the intrinsic power

consumption of an output pad

normalized per MHz of the output

frequency. This is the total I/O current V_DD

+ V_DDP

•

P_ac

P_{clock +}P_{storage +}P_{logic +}P_{inputs +}P_{outputs +}

P_{memory +}P_pll

P_CLOCK, the clock component of power dissipation, is

given by

P_clock= (P1 + P2 * R - P7*R²) * Fs

•

C_load

the output load

the number of outputs

the average output frequency

where:

•

P1 = 100 µW/MHz is the basic power consumption

of the clock tree per MHz of the clock

The input’s component of AC power dissipation is given

•

P2 = 1.3 µW/MHz is the incremental power

consumption of the clock tree per storage

tile – also per MHz of the clock

P_inputs= P8 * q * Fq

where:

•

P7 = 0.00003 µW/MHz is a correction factor for

highly loaded clock-trees

•

P8 =

µ_{W/MHz is the intrinsic power consumption of an}

input pad normalized per MHz of the input frequency

the number of storage tiles clocked by this

clock

•

the number of inputs

the clock frequency

Fq = the average input frequency

_storage, the storage-tile (Register) component of AC

P_pll= P9 * N_pll

power dissipation, is given by

where:

P_storage= P5 * ms * Fs

•

7.5 mW. This value has been estimated at

maximum PLL clock frequency

where:

•

N_Pll

number of PLLs used

•

P5 = 1.1 µW/MHz is the average power

consumption of a storage-tile per MHz of its

output toggling rate. The maximum output

toggling rate is Fs/2

Finally, P_memory, the memory component of AC power

consumption, is given by

P_memory= P6 * N_memory* F_memory* E_memory

•

ms = the number of storage tiles (Register)

switching during each Fs cycle

where:

Fs =

the clock frequency

•

175 µW/MHz is the average power

consumption of a memory block per

MHz of the clock

P_logic, the logic-tile component of AC power dissipation,

is given by

•

N_memory

the number of RAM/FIFO blocks

(1 block = 256 words * 9 bits)

P_logic= P3 * mc * Fs

1 -2 8

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•

F_memory

E_memory

the clock frequency of the memory

logic

the average number of active blocks

divided by the total number of blocks

(N) of the memory.

•

mc = 0 (no logic tile in this shift-register)

=> P_logic= 0 mW

•

Typical values for E_memorywould be

1/4 for a 1k x 8,9,16, 32 memory and

outputs

•

C_load

V_DDP

40 pF

3.3 V

1/16 for

4kx8, 9, 16, and 32

•

memory

•

addition, an application-

5 MHz

dependent component to E_memory

can be considered. For example, for

a 1kx8 memory using only 1 cycle

out of 3, E_memory= 1/4*1/3 = 1/12

=> P_outputs= (P4 + C_load* V_DDP²) * p * Fp = 87.3 mW

inputs

•

The following is an APA750 example using

a shift

logic tiles. This design has one clock at 10 MHz, and 24

outputs toggling at 5 MHz. We then calculate the various

components as follows:

10 MHz

=> P_inputs= P8 * q * Fq = 0.3 mW

memory

clock

N_memory

0 (no RAM/FIFO in this shift-register)

•

10 MHz

13,440

=> P_memory= 0 mW

P_ac

=> P_clock= (P1 + P2 * R - P7*R²) * Fs = 124.2 mW

=> 360 mW

P_total

storage

P_dc+ P_ac= 372 mW (Typical)

•

ms = 13,440 (in a shift register 100% of storage-

tiles are toggling at each clock cycle and Fs =

10 MHz)

=> P_storage= P5 * ms * Fs = 147.8 mW

v 3 . 5

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Operating Conditions

Standard and –F parts are the same unless otherwise noted. –F parts are only available as commercial.

Table 1-15 • Absolute Maximum Ratings*

Pa ra m e t e r

Supply Voltage Core (V_DD

Co n d it io n

Min im u m

–0.3

–1.0

Ma xim u m

3.0

Un it s

)

Supply Voltage I/O Ring (V_DDP

)

4.0

DC Input Voltage

V_DDP+ 0.3

V_DDP+ 1.0

PCI DC Input Voltage

PCI DC Input Clamp Current (absolute)

LVPECL Input Voltage

GND

_IN< –1 or V_IN= V_{DDP + 1V}

–0.3

V_{DDP + 0.5}

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to

absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the

Recommended Operating Conditions.

Table 1-16 • Programming, Storage and Operating Limits

St o ra g e Te m p e ra t u re

Op e ra t in g

T_JMa x

Ju n ct io n

Pro d u ct Gra d e

Commercial

Industrial

Pro g ra m m in g Cycle s (m in .)

Pro g ra m Re t e n t io n (m in .)

Min .

–55°C

Ma x.

110°C

Te m p e ra t u re

500

20 years

110°C

Note: This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and

programming specification is not implied.

Table 1-17 • Supply Voltages

Mo d e

V_DD

2.5V

V_DDP

2.5V

3.3V

Single Voltage

Mixed Voltage*

Note: *Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC^PLUSFlash FPGAs application note for more

information.

Table 1-18 • Recommended Maximum Operating Conditions Programming and PLL Supplies

Co m m e rcia l/In d u st ria l

Pa ra m e t e r

Co n d it io n

During Programming

Min im u m

15.8

Ma xim u m

Un it s

V_PP

16.5

–13.2

Normal Operation¹

During Programming

Normal Operation²

During Programming

V_PN

–13.8

I_PP

I_PN

AVDD

V_DD

AGND

GND

No t e s:

1. Please refer to the "V_PPProgramming Supply Pin" section on page 1-64 for more information.

2. Please refer to the "V_PNProgramming Supply Pin" section on page 1-64 for more information.

1 -3 0

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Table 1-19 • Recommended Operating Conditions

Lim it s

Pa ra m e t e r

Sym b o l

Co m m e rcia l

In d u st ria l

DC Supply Voltage (2.5V I/Os)

DC Supply Voltage (2.5V, 3.3V I/Os*)

V_DD& V_DDP

2.5V 0.2V

V_DDP

V_DD

3.3V 0.3V

2.5V 0.2V

3.3V 0.3V

2.5V 0.2V

Operating Ambient Temperature Range

Maximum Operating Junction Temperature

T_A

0°C to 70°C

110°C

–40°C to 85°C

110°C

Note: *Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC^PLUSFlash FPGAs application note for more

information.

Table 1-20 • DC Electrical Specifications (V_DDP= 2.5V 0.2V)¹

Co m m e rcia l / In d u st ria l^1,2

Sym b o l

Pa ra m e t e r

Co n d it io n s

Min .

Typ .

Ma x.

Un it s

V_OH

Output High Voltage

High Drive (OB25LPH)

I_OH= –6 mA

I_OH= –12 mA

I_OH= –24 mA

2.1

2.0

1.7

I_OH= –3 mA

I_OH= –6 mA

I_OH= –8 mA

2.1

1.9

1.7

Low Drive (OB25LPL)

V_OL

Output Low Voltage

High Drive (OB25LPH)

I_OL= 8 mA

I_OL= 15 mA

I_OL= 24 mA

0.2

0.4

0.7

I_OL= 4 mA

I_OL= 8 mA

I_OL= 15 mA

0.2

0.4

0.7

Low Drive (OB25LPL)

Input High Voltage

Input Low Voltage

1.7

V_DDP

0.3

–0.3

0.7

R_WEAKPULLUPWeak Pull-up Resistance

(OTB25LPU)

V ≥ 1.25V

kΩ

HYST

Input Hysteresis Schmitt

Input Current

See Table 1-4 on page 1-8

with pull up (V_IN= GND)

0.3

–240

–10

0.35

0.45

– 20

µA

without pull up (V_IN= GND or V_DD

)

I_DDQ

Quiescent Supply Current

(standby)

Commercial

VIN = GND³or VDD

Std.

–F

5.0

I_DDQ

Quiescent Supply Current

(standby)

_IN= GND³or V_DD

Std.

5.0

Industrial

Notes:

1. All process conditions. Junction Temperature: –40 to +110°C.

2. –F parts are only available as commercial.

3. No pull-up resistor.

4. This will not exceed 2mA total per device.

v 3 . 5

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Table 1-20 • DC Electrical Specifications (V_DDP= 2.5V 0.2V)¹(Continued)

Co m m e rcia l / In d u st ria l^1,2

Sym b o l

Pa ra m e t e r

Co n d it io n s

Min .

–10

Typ .

Ma x.

Un it s

µA

I_OZ

3-State Output Leakage Current V_OH= GND or V_DD

Std.

–F⁴

–10

100

µA

I_OSH

Output Short Circuit Current High

High Drive (OB25LPH)

Low Drive (OB25LPL)

_IN= V_SS

–120

–100

V_IN= V_SS

I_OSL

Output Short Circuit Current Low

High Drive (OB25LPH)

Low Drive (OB25LPL)

_IN= V_DDP

100

V_IN= V_DDP

C_I/O

I/O Pad Capacitance

C_CLK

Notes:

Clock Input Pad Capacitance

1. All process conditions. Junction Temperature: –40 to +110°C.

2. –F parts are only available as commercial.

3. No pull-up resistor.

4. This will not exceed 2mA total per device.

1 -3 2

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Table 1-21 • DC Electrical Specifications (V_DDP= 3.3V 0.3V and V_DD2.5V 0.2V)¹

Co m m e rcia l / In d u st ria l^1,2

Sym b o l

Pa ra m e t e r

Co n d it io n s

Min .

Typ .

Ma x.

Un it s

V_OH

Output High Voltage

3.3V I/O, High Drive (OB33P) I_OH= –24 mA

I_OH= –14 mA

0.9∗V_DDP

2.4

I_OH= –6 mA

3.3V I/O, Low Drive (OB33L) I_OH= –12 mA

0.9∗V_DDP

2.4

Output High Voltage

I_OH= –0.1 mA

Drive I_OH= –0.5 mA

I_OH= –3.0 mA

2.1

2.0

1.7

2.5V I/O,

High

(OB25H)³

I_OH= –0.1 mA

I_OH= –0.5 mA

2.1

2.0

1.7

2.5V I/O, Low Drive (OB25L)³I_OH= –1.0 mA

V_OL

Output Low Voltage

I_OL= 15 mA

3.3V I/O, High Drive (OB33P) I_OL= 20 mA

I_OL= 28 mA

0.1V_DDP

0.4

0.7

3.3V I/O, Low Drive (OB33L) I_OL= 7 mA

I_OL= 10 mA

0.1V_DDP

0.4

I_OL= 15 mA

0.7

Output Low Voltage

I_OL= 7 mA

Drive I_OL= 14 mA

I_OL= 28 mA

0.2

0.4

0.7

2.5V I/O,

High

(OB25H)³

_OL= 5 mA

0.2

0.4

0.7

I_OL= 10 mA

2.5V I/O, Low Drive (OB25L)³I_OL= 15 mA

Input High Voltage

3.3V LVTTL/LVCMOS

2.5V Mode

1.7

V_DDP

0.3

V_DDP

0.3

Input Low Voltage

3.3V LVTTL/LVCMOS

2.5V Mode

–0.3

0.8

0.7

R_WEAKPULLUPWeak

(IOB33U)

Pull-up

Resistance V ≥ 1.5V

kΩ

R_WEAKPULLUPWeak

(IOB25U)

Pull-up

Resistance V ≥ 1.5V

kΩ

Input Current

with pull up (V_IN= GND)

without pull up (V_IN= GND or V_DD

–300

–10

–40

µA

)

Notes:

1. All process conditions. Junction Temperature: –40 to +110°C.

2. –F parts are only available as commercial.

3. Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC^PLUSFlash FPGAs application note for guidelines

and usage.

4. No pull-up resistor.

5. This will not exceed 2mA total per device.

v 3 . 5

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Table 1-21 • DC Electrical Specifications (V_DDP= 3.3V 0.3V and V_DD2.5V 0.2V)¹(Continued)

Co m m e rcia l / In d u st ria l^1,2

Sym b o l

Pa ra m e t e r

Co n d it io n s

_IN= GND⁴or V_DD

Min .

Typ .

5.0

Ma x.

Un it s

I_DDQ

Quiescent Supply Current

(standby)

Commercial

Std.

–F

5.0

I_DDQ

Quiescent Supply Current

(standby)

_IN= GND⁴or V_DD

Std.

5.0

Industrial

I_OZ

3-State

Current

Output

Leakage V_OH= GND or V_DD

Std.

–F⁴

–10

µA

100

I_OSH

Output Short Circuit Current V_IN= GND

High

_IN= GND

–200

–100

3.3V High Drive (OB33P)

3.3V Low Drive (OB33L)

V_IN= GND

–20

–10

2.5V High Drive (OB25H)³

2.5V Low Drive (OB25L)³

I_OSL

Output Short Circuit Current V_IN= V_DD

Low

3.3V High Drive

3.3V Low Drive

_IN= V_DD

200

100

V_IN= V_DD

200

100

2.5V High Drive³

2.5V Low Drive³

C_I/O

I/O Pad Capacitance

C_CLK

Notes:

Clock Input Pad Capacitance

1. All process conditions. Junction Temperature: –40 to +110°C.

2. –F parts are only available as commercial.

3. Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC^PLUSFlash FPGAs application note for guidelines

and usage.

4. No pull-up resistor.

5. This will not exceed 2mA total per device.

1 -3 4

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Table 1-22 • DC Specifications (3.3V PCI Operation)¹

Co m m e rcia l / In d u st ria l^2,3

Sym b o l

V_DD

Pa ra m e t e r

Co n d it io n

Min .

2.3

Ma x.

2.7

Un it s

Supply Voltage for Core

Supply Voltage for I/O Ring

Input High Voltage

V_DDP

3.0

3.6

0.5V_DDP

–0.5

V_DDP+ 0.5

0.3V_DDP

Input Low Voltage

Input Pull-up Voltage⁴

Input Leakage Current⁵

0.7V_DDP

–10

IPU

0 < V_IN< V_CCI

Std.

–F⁶

µA

–10

100

V_OH

Output High Voltage

I_OUT= –500 µA

I_OUT= 1500 µA

0.9V_DDP

V_OL

Output Low Voltage

0.1V_DDP

C_IN

Input Pin Capacitance (except CLK)

CLK Pin Capacitance

C_CLK

Notes:

1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only.

2. All process conditions. Junction Temperature: –40 to +110°C.

3. –F parts are available as commercial only.

4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated

network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum

current at this input voltage.

5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.

v 3 . 5

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Table 1-23 • AC Specifications (3.3V PCI Revision 2.2 Operation)

Co m m e rcia l / In d u st ria l

Sym b o l Pa ra m e t e r

I_OH(AC)Switching Current High 0 < V_OUT≤0.3V_CCI

0.3V_CCI≤V_OUT< 0.9V_CCI

Co n d it io n

Min .

Ma x.

Un it s

–12V_CCI

(–17.1 + (V_DDP– V_OUT))

0.7V_CCI< V_OUT< V_CCI

See equation C – page 124 of

the PCI Specification

document rev. 2.2

(Test Point)

V_OUT= 0.7V_CC

–32V_CCI

I_OL(AC)

Switching Current Low V_CCI> V_OUT≥ 0.6V_CCI

0.6V_CCI> V_OUT> 0.1V_CCI

16V_DDP

(26.7V_OUT

)

0.18V_CCI> V_OUT> 0^*

See equation D – page 124 of

the PCI Specification

document rev. 2.2

(Test Point)

V_OUT= 0.18V_CC

38V_CCI

V/ns

I_CL

Low Clamp Current

High Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–3 < V_IN≤–1

–25 + (V_IN+ 1)/0.015

I_CH

V_CCI+ 4 > V_IN≥ ς _CCI+1

0.2V_CCIto 0.6V_CCIload^*

0.6V_CCIto 0.2V_CCIload^*

25 + (V_IN– V_DDP– 1)/0.015

slew_R

slew_F

Note: * Refer to the PCI Specification document rev. 2.2.

Pad Loading Applicable to the Rising Edge PCI

1/2 in. max

output

buffer

10 pF

1kΩ

Pad Loading Applicable to the Falling Edge PCI

1kΩ

output

buffer

10 pF

1 -3 6

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Tristate Buffer Delays

PA D

OTBx

50% 50%

35pF

50% 50%

PAD

50% 50%

50%

90%

50%

PAD

50%

PAD

GND

10%

50%

ENZL

DLH

DHL

ENZH

Figure 1-26 • Tristate Buffer Delays

Table 1-24 • Worst-Case Commercial Conditions

V_DDP= 3.0V, V_DD= 2.3V, 35 pF load, T_J= 70°C

Ma x

t _DLH

Ma x

t _DHL

Ma x

t _ENZH

Ma x

t _ENZL

Ma cro Typ e

OTB33PH

OTB33PN

OTB33PL

OTB33LH

OTB33LN

OTB33LL

OTB25HH

OTB25HN

OTB25HL

OTB25LH

OTB25LN

OTB25LL

De scrip t io n

3.3V, PCI Output Current, High Slew Rate

STD –F STD –F STD –F STD –F Un it s

2.0 2.4 2.2 2.6 2.2 2.6 2.0 2.4

2.2 2.6 2.9 3.5 2.4 2.9 2.1 2.5

2.5 3.0 3.2 3.9 2.7 3.3 2.8 3.4

2.6 3.1 4.0 4.8 2.8 3.4 3.0 3.6

2.9 3.5 4.3 5.2 3.2 3.8 4.1 4.9

3.0 3.6 5.6 6.7 3.3 3.9 5.5 6.6

3.1 3.8 1.8 2.2 2.8 3.4 1.7 2.0

3.1 3.7 2.7 3.3 2.9 3.5 2.7 3.2

3.1 3.7 3.9 4.7 2.9 3.5 3.8 4.6

4.6 5.6 2.9 3.5 4.6 5.5 2.9 3.4

4.6 5.6 3.7 4.5 4.6 5.5 3.6 4.3

4.6 5.6 5.1 6.1 4.5 5.4 4.8 5.8

2.0 2.4 2.1 2.5 2.3 2.7 2.0 2.4

3.3V, High Output Current, Nominal Slew Rate

3.3V, High Output Current, Low Slew Rate

3.3V, Low Output Current, High Slew Rate

3.3V, Low Output Current, Nominal Slew Rate

3.3V, Low Output Current, Low Slew Rate

2.5V, High Output Current, High Slew Rate⁵

2.5V, High Output Current, Nominal Slew Rate⁵

2.5V, High Output Current, Low Slew Rate⁵

2.5V, Low Output Current, High Slew Rate⁵

2.5V, Low Output Current, Nominal Slew Rate⁵

2.5V, Low Output Current, Low Slew Rate⁵

OTB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate⁶

OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate⁶2.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5

OTB25LPHL

OTB25LPLH

OTB25LPLN

OTB25LPLL

Notes:

2.5V, Low Power, High Output Current, Low Slew Rate⁶

2.5V, Low Power, Low Output Current, High Slew Rate⁶

2.9 3.5 3.2 3.8 3.1 3.8 2.7 3.2

2.7 3.3 4.6 5.5 3.0 3.6 2.6 3.1

2.5V, Low Power, Low Output Current, Nominal Slew Rate⁶3.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6

2.5V, Low Power, Low Output Current, Low Slew Rate⁶

4.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1

t_DLH=Data-to-Pad HIGH

2. t_DHL=Data-to-Pad LOW

3. t_ENZH=Enable-to-Pad, Z to HIGH

t_ENZL= Enable-to-Pad, Z to LOW

5. Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC^PLUSFlash FPGAs application note for guidelines

and usage.

6. Low power I/O work with V_DDP=2.5V ±10% only. V_DDP=2.3V for delays.

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Output Buffer Delays

50%

DLH

50%

V_OH

PAD

50%

PAD

V_OL

50%

35pF

OBx

DHL

Figure 1-27 • Output Buffer Delays

Table 1-25 • Worst-Case Commercial Conditions

V_DDP= 3.0V, V_DD= 2.3V, 35 pF load, T_J= 70°C

Ma x t _DLH

STD

Ma x t _DHL

Ma cro Typ e

OB33PH

OB33PN

OB33PL

De scrip t io n

3.3V, PCI Output Current, High Slew Rate

–F

2.4

2.6

3.0

3.1

3.5

3.6

3.8

3.7

5.6

2.4

2.9

3.5

3.3

4.2

4.8

STD

2.2

2.9

3.2

4.0

4.3

5.6

1.8

2.7

3.9

2.9

3.7

5.1

2.1

3.0

3.2

4.6

4.2

5.3

–F

2.6

3.5

3.9

4.8

5.2

6.7

2.2

3.3

4.7

3.5

4.5

6.1

2.6

3.6

3.8

5.5

5.1

6.4

Un it s

2.0

2.2

2.5

2.6

2.9

3.0

3.1

4.6

2.0

2.4

2.9

2.7

3.5

4.0

3.3V, High Output Current, Nominal Slew Rate

3.3V, High Output Current, Low Slew Rate

3.3V, Low Output Current, High Slew Rate

3.3V, Low Output Current, Nominal Slew Rate

3.3V, Low Output Current, Low Slew Rate

2.5V, High Output Current, High Slew Rate³

2.5V, High Output Current, Nominal Slew Rate³

2.5V, High Output Current, Low Slew Rate³

2.5V, Low Output Current, High Slew Rate³

2.5V, Low Output Current, Nominal Slew Rate³

2.5V, Low Output Current, Low Slew Rate³

2.5V, Low Power, High Output Current, High Slew Rate⁴

OB33LH

OB33LN

OB33LL

OB25HH

OB25HN

OB25HL

OB25LH

OB25LN

OB25LL

OB25LPHH

OB25LPHN

OB25LPHL

OB25LPLH

OB25LPLN

OB25LPLL

Notes:

2.5V, Low Power, High Output Current, Nominal Slew Rate⁴

2.5V, Low Power, High Output Current, Low Slew Rate⁴

2.5V, Low Power, Low Output Current, High Slew Rate⁴

2.5V, Low Power, Low Output Current, Nominal Slew Rate⁴

2.5V, Low Power, Low Output Current, Low Slew Rate⁴

1. t_DLH= Data-to-Pad HIGH

2. t_DHL= Data-to-Pad LOW

3. Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC^PLUSFlash FPGAs application note for guidelines

and usage.

4. Low power I/O work with V_DDP=2.5V ±10% only. V_DDP=2.3V for delays.

1 -3 8

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Input Buffer Delays

PAD

50%

50% 50%

PAD

50%

IBx

GND

INYH

INYL

Figure 1-28 • Input Buffer Delays

Table 1-26 • Worst-Case Commercial Conditions

_DDP= 3.0V, V_DD= 2.3V, T_J= 70°C

Ma x. t _INYH

Ma x. t _INYL

Ma cro Typ e

IB25

De scrip t io n

St d .

0.7

0.9

0.7

0.4

0.6

–F

0.9

1.1

0.9

0.5

0.7

St d .

0.8

0.6

0.9

0.6

0.8

–F

1.0

0.8

1.1

0.7

0.9

Un it s

2.5V, CMOS Input Levels³, No Pull-up Resistor

IB25S

2.5V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

2.5V, CMOS Input Levels³, Low Power

IB25LP

IB25LPS

IB33

2.5V, CMOS Input Levels³, Low Power, Schmitt Trigger

3.3V, CMOS Input Levels³, No Pull-up Resistor

IB33S

3.3V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

No t e s:

t_INYH= Input Pad-to-Y HIGH

2. t_INYL= Input Pad-to-Y LOW

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

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Global Input Buffer Delays

Table 1-27 • Worst-Case Commercial Conditions

V_DDP= 3.0V, V_DD= 2.3V, T_J= 70°

Ma x. t _INYH

Ma x. t _INYL

Un it s

Ma cro Typ e

GL25

De scrip t io n

St d .

1.3

1.1

1.3

1.0

–F

St d .

1.0

1.1

–F

1.2

1.3

1.1

1.3

2.5V, CMOS Input Levels³, No Pull-up Resistor

2.5V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

2.5V, CMOS Input Levels³, Low Power

1.6

1.2

1.6

1.2

GL25S

GL25LP

GL25LPS

GL33

2.5V, CMOS Input Levels³, Low Power, Schmitt Trigger

3.3V, CMOS Input Levels³, No Pull-up Resistor

3.3V, CMOS Input Levels³, No Pull-up Resistor, Schmitt Trigger

PPECL Input Levels

GL33S

PECL

Notes:

t_INYH= Input Pad-to-Y HIGH

2. t_INYL= Input Pad-to-Y LOW

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, V_DDP=2.3V for delays.

Predicted Global Routing Delay

Table 1-28 • Worst-Case Commercial Conditions¹

V_DDP= 3.0V, V_DD= 2.3V, T_J= 70°C

Ma x.

Pa ra m e t e r

t_RCKH

De scrip t io n

St d .

1.1

1.0

0.8

–F

1.3

1.2

1.0

Un it s

Input Low to High²

Input High to Low²

Input Low to High³

Input High to Low³

t_RCKL

t_RCKH

t_RCKL

Notes:

1. The timing delay difference between tile locations is less than 15ps.

2. Highly loaded row 50%.

3. Minimally loaded row.

Global Routing Skew

Table 1-29 • Worst-Case Commercial Conditions

V_DDP= 3.0V, V_DD= 2.3V, T_J= 70°C

Ma x.

Pa ra m e t e r

t_RCKSWH

De scrip t io n

Maximum Skew Low to High

Maximum Skew High to Low

St d .

–F

Un it s

270

320

t_RCKSHH

1 -4 0

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Module Delays

50% 50%

50%

DBLH

DCLH

DCHL

DBHL

DAHL

DALH

Figure 1-29 • Module Delays

Sample Macrocell Library Listing

Table 1-30 • Worst-Case Commercial Conditions¹

V_{DD = 2.3V, TJ}= 70º C

St a n d a rd

–F

Ce ll Na m e

NAND2

AND2

De scrip t io n

Ma x

Min

Ma x

0.6

0.8

1.0

0.6

1.0

0.8

Min

Un it s

2-Input NAND

2-Input AND

3-Input NOR

0.5

0.7

0.8

0.5

0.8

0.6

NOR3

MUX2L

OA21

2-1 MUX with Active Low Select

2-Input OR into a 2-Input AND

2-Input Exclusive OR

XOR2

LDL

Active Low Latch (LH/HL)

LH²

0.9

0.8

1.1

0.9

CLK-Q

t_setup

0.7

0.1

0.8

0.2

t_hold

DFFL

Negative Edge-Triggered D-type Flip-Flop (LH/HL)

LH²

0.9

0.8

1.1

1.0

CLK-Q

t_setup

t_hold

0.6

0.0

0.7

0.0

Notes:

1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of

local interconnect.

2. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.

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Table 1-31 • Recommended Operating Conditions

Lim it s

Co m m e rcia l/In d u st ria l

180 MHz

Pa ra m e t e r

Sym b o l

f_CLOCK

f_RAM

Maximum Clock Frequency*

Maximum RAM Frequency*

Maximum Rise/Fall Time on Inputs*

150 MHz

•

Schmitt Mode (10% to 90% )

t_R/t_F

100 ns

10 ns

Non-schmitt Mode (10% to 90% )

Maximum LVPECL Frequency*

180 MHz

10 MHz

Maximum t_CKFrequency (JTAG)

t_CK

Note: *–F parts will be 20% slower than standard commercial devices.

Table 1-32 • Slew Rates Measured at C = 30pF, Nominal Pow er Supplies and 25°C

Typ e

Trig . Le ve l Risin g Ed g e (n S) Sle w Ra t e (V/n S) Fa llin g Ed g e (n S) Sle w Ra t e (V/n S)

PCI Mo d e

Yes

OB33PH

OB33PN

OB33PL

OB33LH

OB33LN

OB33LL

OB25HH²

OB25HN²

10% -90%

20% -60%

1.60

1.57

3.80

4.19

5.49

3.31

3.20

3.27

8.41

8.54

8.50

1.55

1.70

1.97

3.57

4.65

5.52

1.65

1.68

0.70

0.63

0.48

0.30

0.32

0.31

0.12

1.29

1.18

1.02

0.56

0.43

0.36

1.65

3.32

1.99

4.84

3.37

2.98

0.75

0.77

1.38

1.15

1.19

1.56

2.08

2.09

3.93

3.28

3.44

1.60

0.80

1.32

0.55

0.78

0.89

1.33

1.30

0.72

0.87

0.84

1.28

0.96

0.51

0.61

0.58

OB25HL

OB25LH²

OB25LN²

OB25LL

OB25LPHH 10% -90%

OB25LPHN 10% -90%

OB25LPHL 10% -90%

OB25LPLH 10% -90%

OB25LPLN 10% -90%

OB25LPLL

10% -90%

Notes:

1. Standard and –F parts.

2. Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC^PLUSFlash FPGAs application note for guidelines

and usage.

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Embedded Memory Specifications

This section discusses ProASIC^PLUSSRAM/FIFO embedded

memory and its interface signals, including timing

diagrams that show the relationships of signals as they

pertain to single embedded memory blocks (Table 1-33).

Table 1-11 on page 1-21 shows basic SRAM and FIFO

configurations. Simultaneous Read and Write to the

same location must be done with care. On such accesses

the DI bus is output to the DO bus.

•

Embedded Memory Specifications

The difference between synchronous transparent and

pipeline modes is the timing of all the output signals

from the memory. In transparent mode, the outputs will

change within the same clock cycle to reflect the data

requested by the currently valid access to the memory. If

clock cycles are short (high clock speed), the data

requires most of the clock cycle to change to valid values

(stable signals). Processing of this data in the same clock

cycle is nearly impossible. Most designers add registers at

all outputs of the memory to push the data processing

into the next clock cycle. An entire clock cycle can then

be used to process the data. To simplify use of this

Enclosed Timing Diagrams—SRAM Mode:

•

"Synchronous SRAM Read, Access Timed Output

Strobe (Synchronous Transparent)"

•

"Synchronous SRAM Read, Pipeline Mode Outputs

(Synchronous Pipelined)"

memory

setup,

suitable

registers

have

been

implemented as part of the memory primitive and are

available to the user in the synchronous pipeline mode.

In this mode, the output signals will change shortly after

the second rising edge, following the initiation of the

read access.

•

"Asynchronous SRAM Write"

"Asynchronous SRAM Read, Address Controlled,

RDB=0"

•

"Asynchronous SRAM Read, RDB Controlled"

"Synchronous SRAM Write"

Table 1-33 • Memory Block SRAM Interface Signals

SRAM Sig n a l

WCLKS

RCLKS

Bit s

In /Ou t

De scrip t io n

Write clock used on synchronization on write side

Read clock used on synchronization on read side

Read address

RADDR<0:7>

RBLKB

True read block select (active LOW)

True read pulse (active LOW)

RDB

WADDR<0:7>

WBLKB

DI<0:8>

WRB

Write address

Write block select (active LOW)

Input data bits <0:8>, <8> can be used for parity in

Negative true write pulse

DO<0:8>

RPE

OUT

Output data bits <0:8>, <8> can be used for parity out

Read parity error (active HIGH)

WPE

Write parity error (active HIGH)

PARODD

Selects odd parity generation/detect when high, even when low

Note: Not all signals shown are used in all modes.

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Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)

RCLKS

Cycle Start

RBD, RBLKB

New Valid

Address

RADDR

Old Data Out

New Valid Data Out

RPE

RACS

RDCS

RDCH

RACH

OCH

RPCH

CMH

CML

OCA

RPCA

CCYC

Note: The plot shows the normal operation status.

Figure 1-30 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)

Table 1-34 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CCYC

CMH

De scrip t io n

Min .

7.5

Ma x.

Un it s

No t e s

Cycle time

Clock high phase

3.0

CML

Clock low phase

3.0

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RADDR hold from RCLKS ↑

RADDR setup to RCLKS ↑

RDB hold from RCLKS ↑

RDB setup to RCLKS ↑

7.5

OCH

3.0

RACH

RACS

0.5

1.0

0.5

1.0

9.5

RDCH

RDCS

RPCA

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

RPCH

3.0

Note: –F speed grade devices are 20% slower than the standard numbers.

1 -4 4

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Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)

RCLKS

Cycle Start

RDB, RBLKB

New Valid

Address

RADDR

New Valid Data Out

New RPE Out

Old Data Out

RPE

Old RPE Out

RACS

OCA

RACH

RPCH

RDCH

OCH

RPCA

RDCS

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-31 • Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)

Table 1-35 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CCYC

CMH

De scrip t io n

Min .

7.5

Ma x.

Un it s

No t e s

Cycle time

Clock high phase

3.0

CML

Clock low phase

3.0

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RADDR hold from RCLKS ↑

RADDR setup to RCLKS ↑

RDB hold from RCLKS ↑

RDB setup to RCLKS ↑

2.0

OCH

0.75

RACH

RACS

0.5

1.0

0.5

1.0

4.0

RDCH

RDCS

RPCA

RPCH

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

1.0

Note: –F speed grade devices are 20% slower than the standard numbers.

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Asynchronous SRAM Write

WADDR

WRB, WBLKB

WPE

AWRS

AWRH

DWRH

WPDH

WPDA

DWRS

WRMH

WRML

WRCYC

Note: The plot shows the normal operation status.

Figure 1-32 • Asynchronous SRAM Write

Table 1-36 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

AWRH

De scrip t io n

WADDR hold from WB ↑

Min .

1.0

0.5

1.5

0.5

2.5

3.0

Ma x.

Un it s

No t e s

AWRS

WADDR setup to WB ↓

DI hold from WB ↑

DI setup to WB ↑

WPE access from DI

WPE hold from DI

Cycle time

DWRH

DWRS

PARGEN is inactive

PARGEN is active

DWRS

WPDA

WPE is invalid while

PARGEN is active

WPDH

1.0

WRCYC

WRMH

WRML

7.5

3.0

WB high phase

Inactive

Active

WB low phase

Note: –F speed grade devices are 20% slower than the standard numbers.

1 -4 6

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Asynchronous SRAM Read, Address Controlled, RDB=0

RADDR

RPE

OAH

RPAH

OAA

RPAA

ACYC

Note: The plot shows the normal operation status.

Figure 1-33 • Asynchronous SRAM Read, Address Controlled, RDB=0

Table 1-37 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

ACYC

De scrip t io n

Read cycle time

Min .

7.5

Ma x.

Un it s

No t e s

OAA

New DO access from RADDR stable

Old DO hold from RADDR stable

New RPE access from RADDR stable

Old RPE hold from RADDR stable

7.5

OAH

3.0

RPAA

10.0

RPAH

Note: –F speed grade devices are 20% slower than the standard numbers.

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Asynchronous SRAM Read, RDB Controlled

RB=(RDB+RBLKB)

RPE

ORDH

RPRDH

ORDA

RPRDA

RDML

RDMH

RDCYC

Note: The plot shows the normal operation status.

Figure 1-34 • Asynchronous SRAM Read, RDB Controlled

Table 1-38 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

ORDA

De scrip t io n

New DO access from RB ↓

Old DO valid from RB ↓

Read cycle time

Min .

Ma x.

Un it s

No t e s

7.5

ORDH

3.0

RDCYC

RDMH

7.5

3.0

9.5

RB high phase

Inactive setup to new cycle

Active

RDML

RB low phase

RPRDA

RPRDH

New RPE access from RB ↓

Old RPE valid from RB ↓

3.0

Note: –F speed grade devices are 20% slower than the standard numbers.

1 -4 8

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Synchronous SRAM Write

WCLKS

WRB, WBLKB

WADDR, DI

WPE

Cycle Start

, t

WRCH WBCH

, t

WRCS WBCS

, t

DCS WDCS

WPCH

, t

DCH WACH

WPCA

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-35 • Synchronous SRAM Write

Table 1-39 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CCYC

CMH

De scrip t io n

Min .

7.5

3.0

0.5

1.0

0.5

1.0

3.0

Ma x.

Un it s

No t e s

Cycle time

Clock high phase

CML

Clock low phase

DCH

DI hold from WCLKS ↑

DI setup to WCLKS ↑

DCS

WACH

WDCS

WPCA

WPCH

WADDR hold from WCLKS ↑

WADDR setup to WCLKS ↑

New WPE access from WCLKS ↑

Old WPE valid from WCLKS ↑

WPE is invalid while

PARGEN is active

0.5

WRCH, WBCH WRB & WBLKB hold from WCLKS ↑

WRCS, WBCS WRB & WBLKB setup to WCLKS ↑

Notes:

0.5

1.0

1. On simultaneous read and write accesses to the same location DI is output to DO.

2. –F speed grade devices are 20% slower than the standard numbers.

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Synchronous Write and Read to the Same Location

CCYC

CMH

CML

RCLKS

New Data*

Last Cycle Data

WCLKS

WCLKRCLKH

WCLKRCLKS

OCH

OCA

* New data is read if WCLKS ↑ occurs before setup time.

The data stored is read if WCLKS ↑ occurs after hold time.

Note: The plot shows the normal operation status.

Figure 1-36 • Synchronous Write and Read to the Same Location

Table 1-40 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CCYC

De scrip t io n

Min .

7.5

Ma x.

Un it s

No t e s

Cycle time

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

WCLKRCLKS

WCLKRCLKH

OCH

WCLKS ↑ to RCLKS ↑ setup time

WCLKS ↑ to RCLKS ↑ hold time

Old DO valid from RCLKS ↑

New DO valid from RCLKS ↑

– 0.1

7.0

3.0

OCA/OCH displayed for

Access Timed Output

OCA

7.5

Notes:

1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.

2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write

clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS

and RCLKS driven by the same design signal.

3. If WCLKS changes after the hold time, the data will be read.

4. A setup or hold time violation will result in unknown output data.

5. –F speed grade devices are 20% slower than the standard numbers.

1 -5 0

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Asynchronous Write and Synchronous Read to the Same Location

CMH

CML

RCLKS

New Data*

Last Cycle Data

WB = {WRB + WBLKB}

WRCKS

BRCLKH

OCH

OCA

DWRRCLKS

DWRH

CCYC

* New data is read if WB ↓ occurs before setup time.

The stored data is read if WB ↓ occurs after hold time.

Note: The plot shows the normal operation status.

Figure 1-37 • Asynchronous Write and Synchronous Read to the Same Location

Table 1-41 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CCYC

De scrip t io n

Min .

7.5

Ma x.

Un it s

No t e s

Cycle time

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

WBRCLKS

WBRCLKH

OCH

WB ↓ to RCLKS ↑ setup time

WB ↓ to RCLKS ↑ hold time

Old DO valid from RCLKS ↑

New DO valid from RCLKS ↑

DI to RCLKS ↑ setup time

DI to WB ↑ hold time

–0.1

7.0

3.0

OCA/OCH

Access Timed Output

displayed

for

OCA

7.5

DWRRCLKS

DWRH

1.5

Notes:

1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.

2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write

signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be

read.

3. A setup or hold time violation will result in unknown output data.

4. –F speed grade devices are 20% slower than the standard numbers.

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Asynchronous Write and Read to the Same Location

RB, RADDR

NEW

NEWER

OLD

WB = {WRB+WBLKB}

ORDA

RAWRH

ORDH

RAWRS

OWRA

OWRH

Note: The plot shows the normal operation status.

Figure 1-38 • Asynchronous Write and Read to the Same Location

Table 1-42 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

ORDA

De scrip t io n

New DO access from RB ↓

Old DO valid from RB ↓

Min .

Ma x.

3.0

Un it s

No t e s

7.5

ORDH

OWRA

New DO access from WB ↑

Old DO valid from WB ↑

RB ↓ or RADDR from WB ↓

RB ↑ or RADDR from WB ↑

3.0

OWRH

0.5

RAWRS

RAWRH

Notes:

5.0

1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically

trigger a read operation which updates the read data.

2. Violation or RAWRS will disturb access to the OLD data.

3. Violation of RAWRH will disturb access to the NEWER data.

4. –F speed grade devices are 20% slower than the standard numbers.

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Synchronous Write and Asynchronous Read to the Same Location

RB, RADDR

NEW

NEWER

OLD

WCLKS

ORDA

RAWCLKH

ORDH

OWRA

OWRH

RAWCLKS

Note: The plot shows the normal operation status.

Figure 1-39 • Synchronous Write and Asynchronous Read to the Same Location

Table 1-43 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

ORDA

De scrip t io n

New DO access from RB ↓

Old DO valid from RB ↓

Min .

Ma x.

3.0

Un it s

No t e s

7.5

ORDH

OWRA

New DO access from WCLKS ↓

Old DO valid from WCLKS ↓

RB ↓ or RADDR from WCLKS ↑

RB ↑ or RADDR from WCLKS ↓

3.0

OWRH

0.5

RAWCLKS

RAWCLKH

Notes:

5.0

1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically

trigger a read operation which updates the read data.

2. Violation of RAWCLKS will disturb access to OLD data.

3. Violation of RAWCLKH will disturb access to NEWER data.

4. –F speed grade devices are 20% slower than the standard numbers.

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Asynchronous FIFO Full and Empty Transitions

The asynchronous FIFO accepts writes and reads while

not full or not empty. When the FIFO is full, all writes are

inhibited. Conversely, when the FIFO is empty, all reads

are inhibited. A problem is created if the FIFO is written

during the transition out of full to not full or read during

the transition out of empty to not empty. The exact time

Figure 1-38 on page 1-52. For basic SRAM configurations,

see Table 1-12 on page 1-22. When reset is asserted, the

empty flag will be asserted, the counters will reset, the

outputs go to zero, but the internal RAM is not erased.

Enclosed Timing Diagrams – FIFO Mode:

at which the write or read operation changes from

inhibited to accepted after the read (write) signal which

causes the transition from full or empty to not full or not

empty is indeterminate. This indeterminate period starts

1 ns after the RB (WB) transition, which deactivates full

or not empty and ends 3 ns after the RB (WB) transition

for slow cycles. For fast cycles, the indeterminate period

ends 3 ns (7.5 ns – RDL (WRL)) after the RB (WB)

transition, whichever is later (Table 1-1 on page 1-6).

•

"Asynchronous FIFO Read"

"Asynchronous FIFO Write"

"Synchronous FIFO Read, Access Timed Output

Strobe (Synchronous Transparent)"

•

"Synchronous FIFO Read, Pipeline Mode Outputs

(Synchronous Pipelined)"

•

"Synchronous FIFO Write"

"FIFO Reset"

The timing diagram for write is shown in Figure 1-37 on

page 1-51. The timing diagram for read is shown in

Table 1-44 • Memory Block FIFO Interface Signals

FIFO Sig n a l

WCLKS

Bit s

In /Ou t

De scrip t io n

Write clock used for synchronization on write side

Read clock used for synchronization on read side

Direct configuration implements static flag logic

Read block select (active LOW)

RCLKS

LEVEL <0:7>*

RBLKB

RDB

Read pulse (active LOW)

RESET

Reset for FIFO pointers (active LOW)

WBLKB

Write block select (active LOW)

DI<0:8>

Input data bits <0:8>, <8> will be generated if PARGEN is true

Write pulse (active LOW)

WRB

FULL, EMPTY

EQTH, GEQTH*

OUT

FIFO flags. FULL prevents write and EMPTY prevents read

EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.

GEQTH is true when the FIFO holds (LEVEL) words or more

DO<0:8>

RPE

OUT

Output data bits <0:8>

Read parity error (active HIGH)

WPE

Write parity error (active HIGH)

LGDEP <0:2>

PARODD

Configures DEPTH of the FIFO to 2 ^(LGDEP+1)

Selects odd parity generation/detect when high, even when low

Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be

possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that

indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL.

Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs.

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FULL

Write

cycle

Write inhibited

Write accepted

1 ns

3 ns

Note: –F speed grade devices are 20% slower than the standard numbers.

Figure 1-40 • Write Timing Diagram

EMPTY

Read

cycle

Read inhibited

Read accepted

1 ns

3 ns

Note: –F speed grade devices are 20% slower than the standard numbers.

Figure 1-41 • Read Timing Diagram

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Asynchronous FIFO Read

RPRDA

RDH

RDL

Cycle Start

RB = (RDB+RBLKB)

(Empty inhibits read)

RDATA

RPE

EMPTY

FULL

EQTH, GETH

, t

RDWRS

ERDH FRDH

, t

ORDH

ERDA FRDA

RPRDH

THRDH

ORDA

THRDA

RPRDA

RDL

RDH

RDCYC

Note: The plot shows the normal operation status.

Figure 1-42 • Asynchronous FIFO Read

Table 1-45 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

De scrip t io n

Min .

Ma x. Un it s

No t e s

ERDH, FRDH, Old EMPTY, FULL, EQTH, & GETH valid hold

0.5

Empty/full/thresh are invalid from the end of

hold until the new access is complete

THRDH

ERDA

time from RB ↑

New EMPTY access from RB ↑

FULL↓access from RB ↑

New DO access from RB ↓

Old DO valid from RB ↓

Read cycle time

3.0¹

7.5

FRDA

ORDA

ORDH

RDCYC

RDWRS

3.0

1.0

7.5

3.0²

WB ↑ , clearing EMPTY, setup to

RB ↓

Enabling the read operation

Inhibiting the read operation

Inactive

RDH

RB high phase

3.0

9.5

RDL

RB low phase

Active

RPRDA

RPRDH

THRDA

Notes:

New RPE access from RB ↓

Old RPE valid from RB ↓

EQTH or GETH access from RB↑

4.0

4.5

1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.

2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns – WRL), 3.0 ns.

3. –F speed grade devices are 20% slower than the standard numbers.

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Asynchronous FIFO Write

Cycle Start

WB = (WRB+WBLKB)

WDATA

WPE

(Full inhibits write)

FULL

EMPTY

EQTH, GETH

WRRDS

DWRH

WPDH

WPDA

DWRS

, t

EWRH FWRH

, t

EWRA FWRA

THWRH

THWRA

WRL

WRH

WRCYC

Note: The plot shows the normal operation status.

Figure 1-43 • Asynchronous FIFO Write

Table 1-46 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

DWRH

De scrip t io n

DI hold from WB ↑

Min .

1.5

Ma x.

Un it s

No t e s

DWRS

DI setup to WB ↑

0.5

PARGEN is inactive

PARGEN is active

DWRS

2.5

EWRH, FWRH, Old EMPTY, FULL, EQTH, & GETH valid hold

0.5

Empty/full/thresh are invalid from the end

of hold until the new access is complete

THWRH

time after WB ↑

EWRA

EMPTY ↓access from WB ↑

New FULL access from WB ↑

EQTH or GETH access from WB ↑

WPE access from DI

3.0¹

4.5

FWRA

THWRA

WPDA

WPDH

WRCYC

WRRDS

3.0

WPE is invalid while PARGEN is active

WPE hold from DI

1.0

Cycle time

7.5

RB ↑ , clearing FULL, setup to

WB ↓

3.0²

Enabling the write operation

Inhibiting the write operation

Inactive

WRH

WB high phase

WB low phase

3.0

WRL

Active

Notes:

1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns.

2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns.

3. –F speed grade devices are 20% slower than the standard numbers.

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Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

RCLK

Cycle Start

RDB

RDATA

RPE

Old Data Out

New Valid Data Out (Empty Inhibits Read)

EMPTY

FULL

EQTH, GETH

, t

RDCH

ECBH FCBH

, t

ECBA FCBA

RDCS

THCBH

OCH

RPCH

HCBA

OCA

RPCA

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-44 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

Table 1-47 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CCYC

De scrip t io n

Min .

7.5

Ma x.

Un it s

No t e s

Cycle time

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

ECBA

New EMPTY access from RCLKS ↓

FULL ↓access from RCLKS ↓

3.0¹

FCBA

ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold

1.0

3.0

Empty/full/thresh are invalid from the end

of hold until the new access is complete

THCBH

time from RCLKS ↓

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RDB hold from RCLKS ↑

7.5

OCH

RDCH

RDCS

RPCA

RPCH

HCBA

Notes:

0.5

1.0

9.5

RDB setup to RCLKS ↑

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

EQTH or GETH access from RCLKS ↓

3.0

4.5

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.

2. –F speed grade devices are 20% slower than the standard numbers.

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Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)

RCLK

Cycle Start

RDB

RDATA

RPE

Old Data Out

New Valid Data Out

New RPE Out

Old RPE Out

EMPTY

FULL

EQTH, GETH

, t

ECBH FCBH

OCA

, t

RDCH

ECBA FCBA

RDCS

THCBH

RPCH

OCH

HCBA

RPCA

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-45 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)

Table 1-48 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CCYC

De scrip t io n

Min . Ma x. Un it s

No t e s

Cycle time

7.5

3.0

CMH

Clock high phase

CML

Clock low phase

3.0

ECBA

New EMPTY access from RCLKS ↓

FULL ↓access from RCLKS ↓

3.0¹

FCBA

ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold

THCBH

1.0

Empty/full/thresh are invalid from the end of

hold until the new access is complete

time from RCLKS ↓

OCA

New DO access from RCLKS ↑

Old DO valid from RCLKS ↑

RDB hold from RCLKS ↑

2.0

OCH

0.75

RDCH

RDCS

RPCA

RPCH

HCBA

Notes:

0.5

1.0

4.0

RDB setup to RCLKS ↑

New RPE access from RCLKS ↑

Old RPE valid from RCLKS ↑

EQTH or GETH access from RCLKS ↓

1.0

4.5

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns.

2. –F speed grade devices are 20% slower than the standard numbers.

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Synchronous FIFO Write

WCLKS

Cycle Start

WRB, WBLKB

(Full Inhibits Write)

WPE

FULL

EMPTY

EQTH, GETH

, t

WRCH WBCH

ECBH FCBH

, t

ECBA FCBA

WRCS WBCS

DCS

HCBH

HCBA

WPCH

DCH

WPCA

CML

CMH

CCYC

Note: The plot shows the normal operation status.

Figure 1-46 • Synchronous FIFO Write

Table 1-49 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CCYC

CMH

De scrip t io n

Min .

7.5

Ma x. Un it s

No t e s

Cycle time

Clock high phase

3.0

CML

Clock low phase

3.0

DCH

DI hold from WCLKS ↑

DI setup to WCLKS ↑

0.5

DCS

1.0

FCBA

New FULL access from WCLKS ↓

EMPTY↓access from WCLKS ↓

3.0¹

ECBA

ECBH,

FCBH,

HCBH

Old EMPTY, FULL, EQTH, & GETH valid hold

time from WCLKS ↓

1.0

0.5

Empty/full/thresh are invalid from the end of

hold until the new access is complete

HCBA

WPCA

WPCH

EQTH or GETH access from WCLKS ↓

New WPE access from WCLKS ↑

Old WPE valid from WCLKS ↑

4.5

3.0

WPE is invalid while

PARGEN is active

WRCH, WBCH WRB & WBLKB hold from WCLKS ↑

WRCS, WBCS WRB & WBLKB setup to WCLKS ↑

Notes:

0.5

1.0

1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.

2. –F speed grade devices are 20% slower than the standard numbers.

1 -6 0

v 3 . 5

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Pro ASIC

Fla sh Fa m ily FPGAs

FIFO Reset

RESETB

WB*

Cycle Start

WCLKS, RCLKS

FULL

Cycle Start

EMPTY

EQTH, GETH

CBRSS

, t

ERSA FRSA

CBRSH

WBRSH

THRSA

RSL

WBRSS

Note: *The plot shows the normal operation status.

Figure 1-47 • FIFO Reset

Table 1-50 • T_J= 0°C to 110°C; V_DD= 2.3V to 2.7V

Sym b o l t _xxx

CBRSH

CBRSS

ERSA

De scrip t io n

WCLKS or RCLKS ↑ hold from RESETB ↑

WCLKS or RCLKS ↓setup to RESETB ↑

New EMPTY ↑ access from RESETB ↓

FULL ↓access from RESETB ↓

RESETB low phase

Min .

1.5

3.0

7.5

4.5

1.5

Ma x.

Un it s

No t e s

Synchronous mode only

FRSA

RSL

THRSA

WBRSH

WBRSS

EQTH or GETH access from RESETB ↓

WB ↓hold from RESETB ↑

Asynchronous mode only

WB ↑ setup to RESETB ↑

Note: –F speed grade devices are 20% slower than the standard numbers.

v 3 . 5

1-61

PLUS

Pro ASIC

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Asynchronous FIFO Full and Empty Transitions

The asynchronous FIFO accepts writes and reads while

not full or not empty. When the FIFO is full, all writes are

inhibited. Conversely, when the FIFO is empty, all reads

are inhibited. A problem is created if the FIFO is written

during the transition out of full to not full or read during

the transition out of empty to not empty. The exact time

The timing diagram for write is shown in Figure 1-40 on

page 1-55. The timing diagram for read is shown in

Figure 1-41 on page 1-55. For basic SRAM configurations,

see Table 1-12 on page 1-22.

Enclosed Timing Diagrams – FIFO Mode:

at which the write or read operation changes from

inhibited to accepted after the read (write) signal which

causes the transition from full or empty to not full or not

empty is indeterminate. This indeterminate period starts

1 ns after the RB (WB) transition, which deactivates full

or not empty and ends 3 ns after the RB (WB) transition

for slow cycles. For fast cycles, the indeterminate period

ends 3 ns (7.5 ns – RDL (WRL)) after the RB (WB)

transition, whichever is later (Table 1-44 on page 1-54).

•

Asynchronous FIFO Read

Asynchronous FIFO Write

Synchronous FIFO Read, Access Timed Output

Strobe (Synchronous Transparent)

•

Synchronous FIFO Read, Pipeline Mode Outputs

(Synchronous Pipelined)

•

Synchronous FIFO Write

FIFO Reset

1 -6 2

v 3 . 5

PLUS

Pro ASIC

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TMS

Te st Mo d e Se le ct

Pin Description

The TMS pin controls the use of boundary-scan circuitry.

This pin has an internal pull-up resistor.

User Pins

TCK

Te st Clo ck

I/O

Use r In p u t /Ou t p u t

Clock input pin for boundary scan (maximum 10 MHz). Actel

recommends adding a nominal 20kΩ pull-up resistor to this

pin.

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Input and output signal levels are

compatible with standard LVTTL and LVCMOS

specifications. Unused I/O pins are configured as inputs

with pull-up resistors.

TDI

Te st Da t a In

Serial input for boundary scan. A dedicated pull-up

resistor is included to pull this pin high when not being

driven.

No Co n n e ct

To maintain compatibility with other Actel ProASIC^PLUS

products, it is recommended that this pin not be

connected to the circuitry on the board.

TDO

Te st Da t a Ou t

Serial output for boundary scan. Actel recommends

adding a nominal 20kΩ pull-up resistor to this pin.

Glo b a l Pin

TRST

Te st Re se t In p u t

Low skew input pin for clock or other global signals. This

pin can be configured with an internal pull-up resistor.

When it is not connected to the global network or the

clock conditioning circuit, it can be configured and used

as a normal I/O.

Asynchronous, active-low input pin for resetting

boundary-scan circuitry. This pin has an internal pull-up

resistor.

Special Function Pins

GLMX

Glo b a l Mu lt ip le xin g Pin

RCK

Ru n n in g Clo ck

Low skew input pin for clock or other global signals. This

pin can be used in one of two special ways: (Refer to

Actel’s Using ProASIC^PLUSClock Conditioning Circuits.

When the external feedback option is selected for the

PLL block, this pin is routed as the external feedback

source to the clock conditioning circuit.

A free running clock is needed during programming if

the programmer cannot guarantee that TCK will be

uninterrupted. If not used, this pin has an internal pull-

up and can be left floating.

NPECL

Use r Ne g a t ive In p u t

3. In applications where two different signals access the

same global net (but at different times) through the

use of GLMXx and GLMXLx macros, this pin will be

fixed as one of the source pins.

Provides high speed clock or data signals to the PLL

block. If unused, leave the pin unconnected.

PPECL

Use r Po sit ive In p u t

This pin can be configured with an internal pull-up

resistor. When it is not connected to the global network

or the clock conditioning circuit, it can be configured and

used as any normal I/O. If not used, a global will be

configured as an input with pull-up.

Provides high speed clock or data signals to the PLL

block. If unused, leave the pin unconnected.

AVDD

PLL Po w e r Su p p ly

Analog V_DDshould be V_DD(core voltage) 2.5V (nominal)

and be decoupled from GND with suitable decoupling

capacitors to reduce noise. For more information, refer

to Actel’s Using ProASIC^PLUSClock Conditioning Circuits

application note. If the clock conditioning circuitry are

not used in a design, AVDD can either be left floating or

tied to 2.5 V.

Dedicated Pins

GND

Gro u n d

Common ground supply voltage.

Lo g ic Arra y Po w e r Su p p ly Pin

AGND

PLL Po w e r Gro u n d

2.5V supply voltage.

Analog GND should be 0V and be decoupled from GND

with suitable decoupling capacitors to reduce noise. For

more information, refer to Actel’s Using ProASIC^PLUS

Clock Conditioning Circuits application note. If the PLLs

or clock conditioning circuitry are not used in a design,

AGND should be tied to GND.

I/O Pa d Po w e r Su p p ly Pin

DDP

2.5V or 3.3V supply voltage.

v 3 . 5

1-63

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Pro ASIC

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Pro g ra m m in g Su p p ly Pin

finite length conductors that distribute the power to the

device. This can be accomplished by providing sufficient

bypass capacitance between the V_PPand V_PNpins and

GND (using the shortest paths possible). Without

sufficient bypass capacitance to counteract the

inductance, the V_PPand V_PNpins may incur a voltage

spike beyond the voltage that the device can withstand.

This issue applies to all programming configurations.

This pin may be connected to any voltage between GND

and 16.5V during normal operation, or it can be left

unconnected.³For information on using this pin during

programming, see the Performing Internal In-System

Programming

application note. Actel recommends floating the pin or

connecting it to V_DDP

Using

Actel’s ProASIC^PLUSDevices

The power supply voltage limits are defined in the

"Supply Voltages" section on page 1-30. The solution

prevents spikes from damaging the ProASIC^PLUSdevices.

Bypass capacitors are required for the V_PPand V_PNpads.

Use a 0.01 µF to 0.1 µF ceramic capacitor with a 25V or

Pro g ra m m in g Su p p ly Pin

This pin may be connected to any voltage between GND

and –13.8V during normal operation, or it can be left

unconnected.⁴For information on using this pin during

programming, see the Performing Internal In-System

greater

rating.

filter

low-frequency noise

Programming

Using

Actel’s ProASIC^PLUSDevices

(decoupling), use a 4.7 µF (low ESR, <1 <Ω, tantalum, 25V

or greater rating) capacitor. The capacitors should be

located as close to the device pins as possible (within

2.5cm is desirable). The smaller, high-frequency capacitor

should be placed closer to the device pins than the larger

low-frequency capacitor. The same dual capacitor circuit

should be used on both the V_PPand V_PNpins (Figure 1-48

on page 1-64).

application note. Actel recommends floating the pin or

connecting it to GND.

Recommended Design Practice

for V /V

PN PP

PLUS

ProASIC

Devices – APA450, APA600,

ProASIC

APA300

Devices – APA075, APA150,

APA750, APA1000

Bypass capacitors are required from V_PPto GND and V_PN

to GND for all ProASIC^PLUSdevices during programming.

During the erase cycle, ProASIC^PLUSdevices may have

current surges on the V_PPand V_PNpower supplies. The

only way to maintain the integrity of the power

distribution to the ProASIC^PLUSdevice during these

current surges is to counteract the inductance of the

These devices do not require bypass capacitors on the V_PP

and V_PNpins as long as the total combined distance of

the programming cable and the trace length on the

board is less than or equal to 30 inches. Note: For trace

lengths greater than 30 inches, use the bypass capacitor

recommendations in the previous section.

2.5cm

0.1µF

4.7µF

Programming

Header

Actel

ProASIC

Device

0.01µF

PLUS

Supplies

0.1µF

0.01µF

4.7µF

(See the " Recommended Design Practice for VPN/VPP" section on page 1-64)

PLUS

Figure 1-48 • ProASIC

and V_PNCapacitor Requirements

3. There is a nominal 40kΩ pull-up resistor on V_PP.

4. There is a nominal 40kΩ pull-down resistor on V_PN

1 -6 4

v 3 . 5

APA300-FFG144I [ACTEL]

相关型号：

APA300-FFG256I

APA300-FFG256X79

APA300-FFGB

APA300-FFGES

APA300-FFGG144C

APA300-FFGG256C

APA300-FFGGB

APA300-FFGGES

APA300-FFGGI

APA300-FFGGM

APA300-FFGGPP

APA300-FFGI