AX500-1BGG896PP [ACTEL]

Axcelerator Family FPGAs; 的Axcelerator系列FPGA


型号：	AX500-1BGG896PP
厂家：	Actel Corporation
描述：	Axcelerator Family FPGAs 的Axcelerator系列FPGA
文件：	总226页 (文件大小：2293K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

v2.7

Axcelerator Family FPGAs

–

Voltage-Referenced I/O Standards: GTL+, HSTL

Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

Registered I/Os

Hot-Swap Compliant I/Os (except PCI)

Programmable Slew Rate and Drive Strength on

Outputs

Leading-Edge Performance

•

350+ MHz System Performance

500+ MHz Internal Performance

High-Performance Embedded FIFOs

700 Mb/s LVDS Capable I/Os

–

Specifications

–

Programmable Delay and Weak Pull-Up/Pull-Down

Circuits on Inputs

•

Up to 2 Million Equivalent System Gates

Up to 684 I/Os

Up to 10,752 Dedicated Flip-Flops

Up to 295 kbits Embedded SRAM/FIFO

Manufactured on Advanced 0.15 μm CMOS Antifuse

Process Technology, 7 Layers of Metal

•

Embedded Memory:

–

Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4,

x9, x18, x36 Organizations Available)

Independent, Width-Configurable Read and Write Ports

Programmable Embedded FIFO Control Logic

–

•

Segmentable Clock Resources

Embedded Phase-Locked Loop:

Features

•

Single-Chip, Nonvolatile Solution

–

14-200 MHz Input Range

Frequency Synthesis Capabilities up to 1 GHz

Up to 100% Resource Utilization with 100% Pin Locking

1.5V Core Voltage for Low Power

Footprint Compatible Packaging

•

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Debug Capability

with Actel Silicon Explorer II

Flexible, Multi-Standard I/Os:

–

1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation

Bank-Selectable I/Os – 8 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V

PCI, and 3.3V PCI-X

•

Boundary-Scan Testing Compliant with IEEE Standard

1149.1 (JTAG)

FuseLock^TMSecure Programming Technology

Prevents Reverse Engineering and Design Theft

–

Differential I/O Standards: LVPECL and LVDS

Table 1-1 • Axcelerator Family Product Profile

Device

AX125

125,000

82,000

AX250

250,000

154,000

AX500

500,000

286,000

AX1000

1,000,000

612,000

AX2000

2,000,000

1,060,000

Capacity (in Equivalent System Gates)

Typical Gates

Modules

Combinatorial (C-cells)

Maximum Flip-Flops

Embedded RAM/FIFO

Number of Core RAM Blocks

Total Bits of Core RAM

Clocks (Segmentable)

Hardwired

672

1,344

1,408

2,816

2,688

5,376

6,048

12,096

10,752

21,504

55,296

73,728

165,888

294,912

18,432

Routed

PLLs

I/Os

I/O Banks

Maximum User I/Os

Maximum LVDS Channels

Total I/O Registers

Package

168

504

248

124

744

336

168

1,008

516

258

1,548

684

342

2,052

CSP

180

PQFP

208

BGA

FBGA

CQFP

729

484, 676, 896

352

256, 324

256, 484

208, 352

484, 676

208, 352

896, 1152

352

CCGA

624

November 2008

*See Actel’s website for the latest version of the datasheet.

Axcelerator Family FPGAs

Ordering Information

AX1000

896

Application

Blank =Commercial (0 to +70° C)

PP =Pre-Production

I =Industrial (-40 to +85° C)

M =Military (-55 to +125° C)

B =MIL-STD-883 Class B

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G= RoHS-Compliant Packaging

Package Type

BG Ball Grid Array (1.27mm pitch)

FG Fine Ball Grid Array (1.0mm pitch)

CS Chip Scale Package (0.8mm pitch)

PQ Plastic Quad Flat Pack (0.5mm pitch)

CQ Ceramic Quad Flat Pack (0.5mm pitch)

CG Ceramic Column Grid Array

Speed Grade

Blank Standard Speed

Approximately 15% Faster than Standard

Approximately 25% Faster than Standard

Part Number

AX125 = 125,000 Equivalent System Gates

AX250 = 250,000 Equivalent System Gates

AX500 = 500,000 Equivalent System Gates

AX1000 = 1,000,000 Equivalent System Gates

AX2000 = 2,000,000 Equivalent System Gates

Device Resources

User I/Os (Including Clock Buffers)

Package

CS180

PQ208

CQ208

FG256

FG324

CQ352

FG484

CG624

FG676

BG729

FG896

FG1152

AX125

AX250

AX500

AX1000

AX2000

–

115

138

–

115

–

138

168

–

198

248

–

198

317

–

198

317

418

516

–

198

–

418

–

336

–

586

684

–

Note: The FG256, FG324, and FG484 are footprint compatible with one another. The FG676, FG896, and FG1152 are also footprint

compatible with one another.

v2.7

Axcelerator Family FPGAs

Temperature Grade Offerings

Package

CS180

PQ208

CQ208

FG256

FG324

CQ352

FG484

CG624

FG676

BG729

FG896

FG1152

AX125

AX250

AX500

AX1000

AX2000

C, I

–

C, I, M

–

M, B

–

C, I

–

C, I, M

–

M, B

C, I, M

M, B

C, I, M

–

M, B

–

C, I, M

–

M, B

–

C, I, M

–

C, I, M

–

Notes:

1. C = Commercial

2. I = Industrial

3. M = Military

4. B = MIL-STD-883 Class B

Speed Grade and Temperature Grade Matrix

Std

–1

✓

–2

✓

–

✓

–

Notes:

5. C = Commercial

6. I = Industrial

7. M = Military

8. B = MIL-STD-883 Class B

Packaging Data

Refer to the following documents located on the Actel website for additional packaging information.

Package Mechanical Drawings

Package Thermal Characteristics and Weights

Hermatic Package Mechanical Information

Contact your local Actel representative for device availability.

v2.7

iii

Axcelerator Family FPGAs

Table of Contents

General Description

Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Low Power (LP) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Detailed Specifications

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Voltage-Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

Axcelerator Clock Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91

Package Pin Assignments

180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

729-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

324-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

v2.7

Axcelerator Family FPGAs

Table of Contents

1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83

352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88

624-Pin CCGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

v2.7

Axcelerator Family FPGAs

General Description

Axcelerator offers high performance at densities of up to

two million equivalent system gates. Based upon the

Actel AX architecture, Axcelerator has several system-

level features such as embedded SRAM (with complete

FIFO control logic), PLLs, segmentable clocks, chip-wide

highway routing, and carry logic.

page 1-2). This completely eliminates the channels of

routing and interconnect resources between logic

modules (as implemented on traditional FPGAs) and

enables the efficient sea-of-modules architecture. The

antifuses are normally open circuit and, when

programmed, form

permanent, passive, low-

impedance connection, leading to the fastest signal

propagation in the industry. In addition, the extremely

small size of these interconnect elements gives the

Axcelerator family abundant routing resources.

Device Architecture

Actel's AX architecture, derived from the highly-

successful SX-A sea-of-modules architecture, has been

designed for high performance and total logic module

utilization (Figure 1-1). Unlike in traditional FPGAs, the

entire floor of the Axcelerator device is covered with a

grid of logic modules, with virtually no chip area lost to

interconnect elements or routing.

The very nature of Actel's nonvolatile antifuse

technology provides excellent protection against design

pirating and cloning (FuseLock technology). Cloning is

impossible (even if the security fuse is left

unprogrammed) as no bitstream or programming file is

ever downloaded or stored in the device. Reverse

engineering is virtually impossible due to the difficulty of

trying to distinguish between programmed and

unprogrammed antifuses and also due to the

programming methodology of antifuse devices (see

"Security" on page 2-90).

Programmable Interconnect

Element

The Axcelerator family uses a patented metal-to-metal

antifuse programmable interconnect element that resides

between the upper two layers of metal (Figure 1-2 on

Routing

Switch

Matrix

Logic Block

Sea-of-Modules

Architecture

Traditional FPGA

Architecture

Logic

Modules

Figure 1-1 • Sea-of-Modules Comparison

v2.7

1-1

Axcelerator Family FPGAs

Figure 1-2 • Axcelerator Family Interconnect Elements

Logic Modules

Actel's Axcelerator family provides two types of logic

modules: the register cell (R-cell) and the combinatorial

cell (C-cell). The

The logic modules within the SuperCluster are arranged

so that two combinatorial modules are side-by-side,

giving a C–C–R – C–C–R pattern to the SuperCluster. This

C–C–R pattern enables efficient implementation

(minimum delay) of two-bit carry logic for improved

arithmetic performance (Figure 1-5 on page 1-3).

can implement more than 4,000 combinatorial functions

of up to five inputs (Figure 1-3 on page 1-3).

The R-cell contains a flip-flop featuring asynchronous

clear, asynchronous preset, and active-low enable control

signals (Figure 1-3 on page 1-3). The R-cell registers

feature programmable clock polarity selectable on a

flexibility (e.g., easy mapping of dual-data-rate functions

into the FPGA) while conserving valuable clock resources.

The clock source for the R-cell can be chosen from the

hardwired clocks, routed clocks, or internal logic.

The AX architecture is fully fracturable, meaning that if

one or more of the logic modules in a SuperCluster are

used by a particular signal path, the other logic modules

are still available for use by other paths.

At the chip level, SuperClusters are organized into core

tiles, which are arrayed to build up the full chip. For

example, the AX1000 is composed of a 3x3 array of nine

core tiles. Surrounding the array of core tiles are blocks

of I/O Clusters and the I/O bank ring (Table 1-1 on

page 1-3). Each core tile consists of an array of 336

SuperClusters and four SRAM blocks (176 SuperClusters

and three SRAM blocks for the AX250). The SRAM blocks

are arranged in a column on the west side of the tile

(Figure 1-6 on page 1-4).

Two C-cells, a single R-cell, and two Transmit (TX) and two

Receive (RX) routing buffers form a Cluster, while two

Clusters comprise a SuperCluster (Figure 1-4 on page 1-3).

Each SuperCluster also contains an independent Buffer (B)

module, which supports buffer insertion on high-fanout

nets by the place-and-route tool, minimizing system

delays while improving logic utilization.

1-2

v2.7

Axcelerator Family FPGAs

FCI

A[1:0]

B[1:0]

CLK

PSET

CLR

C-cell

D[3:0]

CFN

(Positive Edge Triggered)

FCO

C-Cell

R-Cell

Figure 1-3 • AX C-Cell and R-Cell

C C R

Figure 1-4 • AX SuperCluster

FCI

DCOUT

C-Cell

Carry Logic

FCO

Figure 1-5 • AX 2-bit Carry Logic

Table 1-1 • Number of Core Tiles per Device

Device

AX125

AX250

AX500

AX1000

AX2000

Number of Core Tiles

1 regular tile

4 smaller tiles

4 regular tiles

9 regular tiles

16 regular tiles

v2.7

1-3

Axcelerator Family FPGAs

SuperCluster

RAMC SC

RAM/

FIFO

RAMC SC

RAM/

FIFO

RAMC SC

RAM/

FIFO

Chip Layout

RAMC SC

Core Tile

RAM/

FIFO

RAMC SC

I/O Structure

See Figure 7

Figure 1-6 • AX Device Architecture (AX1000 shown)

as control circuitry to prevent metastability and

erroneous operation. The embedded SRAM/FIFO blocks

can be cascaded to create larger configurations.

Embedded Memory

As mentioned earlier, each core tile has either three (in a

smaller tile) or four (in the regular tile) embedded SRAM

blocks along the west side, and each variable-aspect-

ratio SRAM block is 4,608 bits in size. Available memory

configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or

4kx1 bits. The individual blocks have separate read and

write ports that can be configured with different bit

widths on each port. For example, data can be written in

by eight and read out by one.

I/O Logic

The Axcelerator family of FPGAs features a flexible I/O

structure, supporting a range of mixed voltages with its

bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V. In all,

Axcelerator FPGAs support at least 14 different I/O

standards (single-ended, differential, voltage-referenced).

The I/Os are organized into banks, with eight banks per

device (two per side). The configuration of these banks

determines the I/O standards supported (see "User I/Os"

on page 2-10 for more information). All I/O standards are

available in each bank.

In addition, every SRAM block has an embedded FIFO

control unit. The control unit allows the SRAM block to

be configured as a synchronous FIFO without using core

logic modules. The FIFO width and depth are

programmable. The FIFO also features programmable

ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL)

flags in addition to the normal EMPTY and FULL flags. In

addition to the flag logic, the embedded FIFO control

unit also contains the counters necessary for the

generation of the read and write address pointers as well

Each I/O module has an input register (InReg), an output

(Figure 1-7 on page 1-5). An I/O Cluster includes two I/O

modules, four RX modules, two TX modules, and a buffer

(B) module.

1-4

v2.7

Axcelerator Family FPGAs

I/O Module

InReg

OutReg

EnReg

RAM/

FIFO

I/O

Module

I/O

Module

I/O Cluster

RX RX

RAM/

FIFO

RAM/

FIFO

CoreTile

RAM/

FIFO

Figure 1-7 • I/O Cluster Arrangement

The next level contains the core tile routing. Over the

SuperClusters within a core tile, both vertical and

horizontal tracks run across rows or columns,

respectively. At the chip level, vertical and horizontal

tracks extend across the full length of the device, both

north-to-south and east-to-west. These tracks are

composed of highway routing that extend the entire

length of the device (segmented at core tile boundaries)

as well as segmented routing of varying lengths.

Routing

The AX hierarchical routing structure ties the logic

modules, the embedded memory blocks, and the I/O

modules together (Figure 1-8 on page 1-6). At the lowest

level, in and between SuperClusters, there are three local

routing structures: FastConnect, DirectConnect, and

CarryConnect routing. DirectConnects provide the highest

performance routing inside the SuperClusters by

connecting a C-cell to the adjacent R-cell. DirectConnects

do not require an antifuse to make the connection and

achieve a signal propagation time of less than 0.1 ns.

Global Resources

FastConnects provide high-performance, horizontal

routing inside the SuperCluster and vertical routing to

the SuperCluster immediately below it. Only one

programmable connection is used in a FastConnect path,

delivering a maximum routing delay of 0.4 ns.

Each family member has three types of global signals

available to the designer: HCLK, CLK, and GCLR/GPSET.

There are four hardwired clocks (HCLK) per device that

can directly drive the clock input of each R-cell. Each of

the four routed clocks (CLK) can drive the clock, clear,

preset, or enable pin of an R-cell or any input of a C-cell

(Figure 1-3 on page 1-3).

CarryConnects are used for routing carry logic between

adjacent SuperClusters. They connect the FCO output of

one two-bit, C-cell carry logic to the FCI input of the two-

bit, C-cell carry logic of the SuperCluster below it.

CarryConnects do not require an antifuse to make the

connection and achieve a signal propagation time of less

than 0.1 ns.

Global clear (GCLR) and global preset (GPSET) drive the

clear and preset inputs of each R-cell as well as each I/O

Each HCLK and CLK has an associated analog PLL (a total

of eight per chip). Each embedded PLL can be used for

clock delay minimization, clock delay adjustment, or

clock frequency synthesis. The PLL is capable of

v2.7

1-5

Axcelerator Family FPGAs

Figure 1-8 • AX Routing Structures

operating with input frequencies ranging from 14 MHz

to 200 MHz and can generate output frequencies

between 20 MHz and 1 GHz. The clock can be either

divided or multiplied by factors ranging from 1 to 64.

Additionally, multiply and divide settings can be used in

any combination as long as the resulting clock frequency

is between 20 MHz and 1 GHz. Adjacent PLLs can be

cascaded to create complex frequency combinations.

Design Environment

The Axcelerator family of FPGAs is fully supported by both

Actel's Libero™ Integrated Design Environment and

Designer FPGA Development software. Actel Libero IDE is

an integrated design manager that seamlessly integrates

design tools while guiding the user through the design

flow, managing all design and log files, and passing

necessary design data among tools. Additionally, Libero

IDE allows users to integrate both schematic and HDL

synthesis into a single flow and verify the entire design in

a single environment (see the Libero IDE Flow diagram

located on Actel’s website). Libero IDE includes Synplify^®

Actel Edition (AE) from Synplicity^®, ViewDraw^®AE from

Mentor Graphics^®, ModelSim^®HDL Simulator from

Mentor Graphics, WaveFormer Lite™ AE from

SynaptiCAD^®, and Designer software from Actel.

The PLL can be used to introduce either a positive or a

negative clock delay of up to 3.75 ns in 250 ps

increments. The reference clock required to drive the PLL

can be derived from three sources: external input pad

(either single-ended or differential), internal logic, or the

output of an adjacent PLL.

Low Power (LP) Mode

Actel's Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

the following:

The AX architecture was created for high-performance

designs but also includes a low power mode (activated via

the LP pin). When the low power mode is activated, I/O

banks can be disabled (inputs disabled, outputs tristated),

and PLLs can be placed in a power-down mode. All

internal register states are maintained in this mode.

Furthermore, individual I/O banks can be configured to

opt out of the LP mode, thereby giving the designer access

to critical signals while the rest of the chip is in low power

mode.

•

Timer – a world-class integrated static timing analyzer

and constraints editor which support timing-driven

place-and-route

•

NetlistViewer – a design netlist schematic viewer

ChipPlanner – a graphical floorplanner viewer and editor

SmartPower – allows the designer to quickly estimate

the power consumption of a design

The power can be further reduced by providing an

external voltage source (V_PUMP) to the device to bypass

the internal charge pump (See "Low Power Mode" on

page 2-89 for more information).

•

PinEditor – a graphical application for editing pin

assignments and I/O attributes

I/O Attribute Editor – displays all assigned and

unassigned I/O macros and their attributes in a

spreadsheet format

1-6

v2.7

Axcelerator Family FPGAs

With the Designer software, a user can lock the design

pins before layout while minimally impacting the results

of place-and-route. Additionally, Actel’s back-annotation

flow is compatible with all the major simulators and the

simulation results can be cross-probed with Silicon

Explorer II, Actel’s integrated verification and logic

analysis tool. Another tool included in the Designer

software is the SmartGen core generator, which easily

creates popular and commonly used logic functions for

implementation into your schematic or HDL design.

In-System Diagnostic and Debug

Capabilities

The Axcelerator family of FPGAs includes internal probe

circuitry, allowing the designer to dynamically observe

and analyze any signal inside the FPGA without disturbing

normal device operation. Up to four individual signals can

be brought out to dedicated probe pins (PRA/B/C/D) on

the device. The probe circuitry is accessed and controlled

via Silicon Explorer II (Figure 1-9), Actel's integrated

verification and logic analysis tool that attaches to the

serial port of a PC and communicates with the FPGA via

the JTAG port (See "Silicon Explorer II Probe Interface"

on page 2-91).

Actel's Designer software is compatible with the most

popular FPGA design entry and verification tools from

EDA vendors, such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

Summary

Actel’s Axcelerator family of FPGAs extends the

successful SX-A architecture, adding embedded RAM/

FIFOs, PLLs, and high-speed I/Os. With the support of a

suite of robust software tools, design engineers can

incorporate high gate counts and fixed pins into an

Axcelerator design yet still achieve high performance

and efficient device utilization.

Programming

Programming support is provided through Actel's Silicon

Sculptor II, a single-site programmer driven via a PC-

based GUI. In addition, BP Microsystems offers multi-site

programmers that provide qualified support for Actel

devices. Factory programming is available for high-

volume production needs.

Axcelerator FPGAs

16 Pin

Connection

TDI

TCK

TMS

TDO

Serial

Connection

Silicon Explorer II

PRA

PRB

22 Pin

Connection

CH3/PRC

CH4/PRD

Additional 14 Channels

(Logic Analyzer)

Figure 1-9 • Probe Setup

v2.7

1-7

Axcelerator Family FPGAs

Related Documents

Application Notes

Simultaneous Switching Noise and Signal Integrity

http://www.actel.com/documents/SSN_AN.pdf

Axcelerator Family PLL and Clock Management

http://www.actel.com/documents/AX_PLL_AN.pdf

Implementing DDR Transmit in Axcelerator

http://www.actel.com/documents/AX_DDR_AN.pdf

Implementation of Security in Actel Antifuse FPGAs

http://www.actel.com/documents/Antifuse_Security_AN.pdf

User’s Guides and Manuals

Antifuse Macro Library Guide

http://www.actel.com/documents/libguide_UG.pdf

SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder

http://www.actel.com/documents/genguide_ug.pdf

Silicon Sculptor II User’s Guide

http://www.actel.com/techdocs/manuals/default.asp

White Paper

Design Security in Nonvolatile Flash and Antifuse FPGAs

http://www.actel.com/documents/DesignSecurity_WP.pdf

Understanding Actel Antifuse Device Security

http://www.actel.com/documents/AntifuseSecurity_WP.pdf

Miscellaneous

Libero IDE flow diagram

http://www.actel.com/products/tools/libero/flow.html

1-8

v2.7

Axcelerator Family FPGAs

Detailed Specifications

Operating Conditions

Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent

damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device

reliability. Devices should not be operated outside the recommendations in Table 2-2.

Table 2-1 • Absolute Maximum Ratings

Symbol

V_CCA

V_CCI

V_REF

V_I

Parameter

Limits

Units

DC Core Supply Voltage

DC I/O Supply Voltage

DC I/O Reference Voltage

Input Voltage

–0.3 to 1.6

–0.3 to 3.75

–0.5 to 3.75

–60 to +150

–0.3 to 3.75

V_O

Output Voltage

T_STG

Storage Temperature

Supply Voltage for Differential I/Os

°C

V_CCDA

Note: * Should be the maximum of all V_CCI

Table 2-2 • Recommended Operating Conditions

Parameter Range

Commercial

Industrial

–40 to +85

Military

Units

Ambient Temperature (T_A)¹

1.5V Core Supply Voltage

1.5V I/O Supply Voltage

1.8V I/O Supply Voltage

2.5V I/O Supply Voltage

3.3V I/O Supply Voltage

V_CCDASupply Voltage

0 to +70

1.425 to 1.575

1.71 to 1.89

2.375 to 2.625

3.0 to 3.6

–55 to +125

1.425 to 1.575

1.71 to 1.89

2.375 to 2.625

3.0 to 3.6

°C

1.425 to 1.575

1.71 to 1.89

2.375 to 2.625

3.0 to 3.6

V_PUMPSupply Voltage

3.0 to 3.6

Notes:

1. Ambient temperature (T_A) is used for commercial and industrial grades; case temperature (T_C) is used for military grades.

2. T_Jmax = 125°C

Power-Up/Down Sequence

All Axcelerator I/Os are tristated during power-up until normal device operating conditions are reached, when I/Os

enter user mode. V_CCDAshould be powered up before (or coincidentally with) V_CCAand V_CCIto ensure the behavior of

user I/Os at system start-up. Conversely, V_CCDAshould be powered down after (or coincidentally with) V_CCAand V_CCI

Note that V_CCIand V_CCAcan be powered up in any sequence with respect to each other, provided the requirement

with respect to V_CCDAis satisfied.

v2.7

2-1

Axcelerator Family FPGAs

Calculating Power Dissipation

Table 2-3 • Standby Current

I_CCA

I_CCDA

I_CCBANK

I_CCPLL

I_CCCP

Standby Current per

I/O Bank

Standby Current,

Charge Pump

Standby

Current,

Current Differential

Standby

Current

per PLL

Bypassed

Device

Temperature

Typical at 25°C

70°C

(Core)

1.5

I/O

1.5

2.5V V_CCI3.3V V_CCI

Active

0.3

0.4

0.3

0.4

0.3

0.4

0.3

0.4

0.3

0.4

Mode

0.01

0.2

Units

AX125

0.2

0.5

0.6

0.3

0.75

0.8

1.5

0.4

0.9

0.2

85°C

125°C

0.5

AX250

AX500

AX1000

AX2000

Typical at 25°C

70°C

1.5

1.4

0.25

0.8

1.3

0.4

0.2

0.01

0.2

85°C

125°C

1.8

0.75

1.5

1.9

2.5

1.25

0.5

Typical at 25°C

70°C

1.4

0.2

0.01

0.2

85°C

125°C

180

7.5

1.75

0.5

1.5

0.2

0.5

Typical at 25°C

70°C

1.5

0.01

0.2

85°C

120

200

3.4

125°C

1.6

1.5

0.2

0.5

Typical at 25°C

70°C

0.7

1.5

0.01

0.2

160

200

500

85°C

125°C

1.5

0.5

Note: I_CCCPActive is the I_CCDAor the Internal Charge Pump current. I_CCCPBypassed mode is the External Charge Pump current I_IH(V_PUMP

pin).

Table 2-4 • Default C_LOAD/V_CCI

C_LOAD(pF)

V_CCI(V)

P_LOAD(μw/MHz)

P₁₀(μw/MHz)

P_I/O(μW/MHz)*

Single-Ended without VREF

LVTTL 24mA High Slew

LVTTL 16mA High Slew

LVTTL 12mA High Slew

LVTTL 8mA High Slew

LVTTL 24mA Low Slew

LVTTL 16mA Low Slew

LVTTL 12mA Low Slew

LVTTL 8mA Low Slew

LVCMOS – 25

3.3

2.5

1.8

381.2

218.8

113.4

262.6

220.1

160.9

125.4

164.2

145.9

133.6

113.8

143.2

68.7

643.7

601.3

542.1

506.5

545.4

527.0

514.8

494.9

361.9

182.1

LVCMOS – 18

Note: *P_I/O= P₁₀+ C_LOAD*V_CCI

2-2

v2.7

Axcelerator Family FPGAs

Table 2-4 • Default C_LOAD/V_CCI(Continued)

_LOAD(pF)

V_CCI(V)

1.5

P_LOAD(μw/MHz)

P₁₀(μw/MHz)

P_I/O(μW/MHz)*

123.6

LVCMOS - 15 (JESD8-11)

78.8

108.9

44.9

213.5

158.0

PCI

3.3

322.4

PCI-X

3.3

266.9

Single-Ended with VREF

HSTL-I

1.5

2.5

3.3

2.5

3.3

36.8

166.9

143.5

322.8

284.0

TBD

36.8

166.9

143.5

322.8

284.0

TBD

SSTL2-I

SSTL2-II

SSTL3-I

SSTL3-II

GTLP - 25

GTLP - 33

TBD

Differential

LVPECL - 33

LVDS - 25

N/A

3.3

2.5

255.1

140.4

255.1

140.4

Note: *P_I/O= P₁₀+ C_LOAD*V_CCI

Table 2-5 • Different Components Contributing to the Total Power Consumption in Axcelerator Devices

Device Specific Value (in µW/MHz)

Component

Definition

Core tile HCLK power component

AX125 AX250 AX500 AX1000 AX2000

P10

P11

0.2

4.5

0.2

4.5

0.2

130

0.2

216

0.2

R-cell power component

HCLK signal power dissipation

13.5

130

0.3

Core tile RCLK power component

0.3

1.6

1.4

216

0.3

R-cell power component

0.3

6.5

1.6

1.4

0.3

6.5

1.6

1.4

RCLK signal power dissipation

19.5

1.6

Power dissipation due to the switching activity on the R-cell

Power dissipation due to the switching activity on the C-cell

Power component associated with the input voltage

Power component associated with the output voltage

1.6

1.4

See table Per pin contribution

Power component associated with the read operation in the RAM

block

P12

P13

Power component associated with the write operation in the RAM

block

Core PLL power component

1.5

v2.7

2-3

Axcelerator Family FPGAs

P_total= P_dc+ P_ac

P_dc

P_ac

I_CCA* V_CCA

P_HCLK+ P_CLK+ P_R-cells+ P_C-cells+ P_inputs+ P_outputs+ P_memory+ P_PLL

P_HCLK= (P1 + P2 * s + P3 * sqrt[s]) * Fs

the number of R-cells clocked by this clock

the clock frequency

P_CLK= (P4 + P5 * s + P6 * sqrt[s]) * Fs

the number of R-cells clocked by this clock

the clock frequency

P_R-cells= P7 * ms * Fs

the number of R-cells switching at each Fs cycle

the clock frequency

P_C-cells= P8 * mc * Fs

the number of C-cells switching at each Fs cycle

the clock frequency

P_inputs= P9 * pi * F_pi

the number of inputs

F_pi

the average input frequency

P_outputs= P_I/O* po * F_po

C_load

V_CCI

the output load (technology dependent)

the output voltage (technology dependent)

the number of outputs

F_po

the average output frequency

P_memory= P11 * N_block* F_RCLK+ P12 * N_block* F_WCLK

N_block= the number of RAM/FIFO blocks (1 block = 4k)

F_RCLK= the read-clock frequency of the memory

F_WCLK= the write-clock frequency of the memory

P_PLL= P13 * F_CLK

F_RefCLK= the clock frequency of the clock input of the PLL

F_CLK

= the clock frequency of the first clock output of the PLL

2-4

v2.7

Axcelerator Family FPGAs

Power Estimation Example

This example employs an AX1000 shift-register design with 1,080 R-cells, one C-cell, one reset input, and one LVTTL

12mA Output, with High Slew.

This design uses one HCLK at 100 MHz.

1,080 (in a shift register - 100% of R-cells are toggling at each clock cycle)

100 MHz

1080

=> P_HCLK= (P1 + P2 * s + P3 * sqrt[s]) * Fs = 79 mW

and Fs = 100 MHz

=> P_R-cells= P7 * ms * Fs = 173 mW

1 (1 C-cell in this shift-register)

and Fs = 100 MHz

=> P_C-cells= P8 * mc * Fs = 0.14 mW

F_pi~ 0 MHz

and pi= 1 (1 reset input => this is why F_pi=0)

P_inputs= P9 * pi * F_pi= 0 mW

_po= 50 MHz

and po = 1

=> P_outputs= P_I/O* po * F_po= 27.10 mW

No RAM/FIFO in this shift-register

P_memory= 0 mW

No PLL in this shift-register

=> P_PLL= 0 mW

P_ac= P_HCLK+ P_CLK+ P_R-cells+ P_C-cells+ P_inputs+ P_outputs+ P_memory+ P_PLL= 276 mW

_dc= 7.5mA * 1.5V = 11.25 mW

P_total= P_dc+ P_ac= 11.25 mW + 276mW = 290.30 mW

v2.7

2-5

Axcelerator Family FPGAs

Thermal Characteristics

Introduction

The temperature variable in Actel’s Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the chip junction

temperature to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature.

T_J= Junction Temperature = ΔT + T_a

ΔT = θ_ja* P

EQ 2-1

EQ 2-2

Where:

T_a= Ambient Temperature

Where:

= Power

ΔT = Temperature gradient between junction

θ_ja= Junction to ambient of package. θ_janumbers

(silicon) and ambient

are located under Table 2-6 on page 2-6.

Package Thermal Characteristics

The device junction-to-case thermal characteristic is θ_jc, and the junction-to-ambient air characteristic is θ_ja. The

thermal characteristics for θ_jaare shown with two different air flow rates. θ_jcvalues are provided for reference. The

absolute maximum junction temperature is 125°C.

The maximum power dissipation allowed for commercial- and industrial-grade devices is a function of θ . A sample

calculation of the absolute maximum power dissipation allowed for an 896-pin FBGA package at commercial

temperature and still air is as follows:

Max. junction temp. (°C) – Max. ambient temp. (°C)

125°C – 70°C

Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 4. 04 W

θ_ja(°C/W) 13.6°C/W

The maximum power dissipation allowed for Military temperature and Mil-Std 883B devices is specified as a function

of θ_jc.

Table 2-6 • Package Thermal Characteristics

Package Type

Pin Count

180

θ_jc

N/A

8.0

2.2

3.0

3.2

2.4

1.8

2.0

6.5

_jaStill Air

57.8

_ja1.0m/s

51.0

23.5

10.6

22.8

22.1

17.0

13.0

10.4

8.9

_ja2.5m/s

Units

°C/W

Chip Scale Package (CSP)

Plastic Quad Flat Pack (PQFP)

Plastic Ball Grid Array (PBGA)

Fine Pitch Ball Grid Array (FBGA)

Ceramic Quad Flat Pack (CQFP)¹

Ceramic Column Grid Array (CCGA)²

Notes:

208

20.9

9.6

729

13.7

26.6

25.8

20.5

16.4

13.6

12.0

256

21.5

20.9

15.9

12.0

9.4

324

484

676

896

1152

208

7.9

19.8

16.1

8.5

18.0

14.7

352

17.9

8.9

624

1. θ for the 208-pin and 352-pin CQFP refers to the thermal resistance between the junction and the bottom of the package.

2. θ for the 624-pin CCGA refers to the thermal resistance between the junction and the top surface of the package. Thermal

resistance from junction to board (θ_jb) for CCGA 624 package is 3.4°C/W.

2-6

v2.7

Axcelerator Family FPGAs

Timing Characteristics

Axcelerator devices are manufactured in a CMOS process, therefore, device performance varies according to

temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage,

minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating

voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-7 should

be applied to all timing data contained within this datasheet.

Table 2-7 • Temperature and Voltage Timing Derating Factors

(Normalized to Worst-Case Commercial, T_J= 70°C, V_CCA= 1.425V)

Junction Temperature

V_CCA

1.4V

–55°C

0.83

0.82

0.78

0.74

0.73

–40°C

0.86

0.84

0.80

0.76

0.75

0°C

0.91

0.90

0.85

0.81

0.80

25°C

0.96

0.94

0.89

0.85

0.84

70°C

1.02

1.00

0.95

0.90

0.89

85°C

1.05

1.04

0.98

0.94

0.92

125°C

1.15

1.13

1.07

1.02

1.01

1.425V

1.5V

1.575V

1.6V

Notes:

1. The user can set the junction temperature in Designer software to be any integer value in the range of –55°C to 175°C.

2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V.

All timing numbers listed in this datasheet represent sample timing characteristics of Axcelerator devices. Actual

timing delay values are design-specific and can be derived from the Timer tool in Actel’s Designer software after place-

and-route.

v2.7

2-7

Axcelerator Family FPGAs

Timing Model

I/O Module

(Nonregistered)

Carry Chain

t_PY= 2.28 ns

I/O

Combinatorial

Cell

Combinatorial

Cell

LVPECL

FCO

I/O

t_CCY= 0.61 ns

t_PDC= 0.57 ns

I/O Module

(Registered)

I/O Module

(Nonregistered)

t_RD2= 0.53 ns

Combinatorial

Cell

_DP= 1.70 ns

Buffer

Module

Buffer

Module

t_PY= 3.03 ns

LVPECL

LVTTL

Output Drive

Strength = 4 (24mA)

High Slew Rate

t_BFPD= 0.12 ns

t_PD= 0.74 ns

_BFPD= 0.12 ns

_RD1= 0.45 ns

_RD2= 0.53 ns

_RD3= 0.56 ns

t_ICKLQ= 0.67 ns

t_SUD= 0.23 ns

Hardwired Clock

t_HCKH= 3.03 ns

_MAX(external) = 350 MHz

Combinatorial

Cell

t_RCO= 0.67 ns

_SUD= 0.23 ns

I/O Module

t_OCLKY= 0.67 ns

_SUD= 0.23 ns

F_MAX(internal) = 870 MHz

Buffer

Module

t_RD1= 0.45 ns

t_PY= 1.01 ns

GTL + 3.3V

I/O Module

(Non- registered)

t_BPFD= 0.12 ns

t_PD= 0.74 ns

t_RCO= 0.67 ns

t_SUD= 0.23 ns

LVDS

t_RCKL= 3.08 ns

F_MAX(external) = 350 MHz

F_MAX(internal) = 870 MHz

Routed Clock

t_DP= 1.84 ns

Hardwired or

Routed Clock

t_HCKL= 3.02 ns

t_RCKL= 3.08 ns

Note: Worst case timing data for the AX1000, –2 speed grade

Figure 2-1 • Worst Case Timing Data

Hardwired Clock – Using LVTTL 24mA High

Slew Clock I/O

Routed Clock – Using LVTTL 24mA High Slew

Clock I/O

External Setup

= (t_DP+ t_RD2+ t_SUD)– t_HCKL

= (1.72 + 0.53 + 0.23) – 3.02 = –0.54 ns

Clock-to-Out (Pad-to-Pad)

= (t_DP+ t_RD2+ t_SUD)– t_RCKH

= (1.72 + 0.53 + 0.23) – 3.13 = –0.65 ns

Clock-to-Out (Pad-to-Pad)

= t_HCKL+ t_RCO+ t_RD1+ t_PYs

= 3.02 + 0.67 + 0.45 + 3.03 = 7.17 ns

= t_RCKH+ t_RCO+ t_RD1+ t_PY

= 3.13 + 0.67 + 0.45 + 3.03 = 7.28 ns

2-8

v2.7

Axcelerator Family FPGAs

I/O Specifications

Pin Descriptions

Supply Pins

Axcelerator Chip

V_CCPLX

250 Ω

1.5V Supply

GND

Ground

Low supply voltage.

10µf

0.1µf

Supply Voltage

CCA

V_COMPLX

Supply voltage for array (1.5V). See "Operating

Conditions" on page 2-1 for more information.

Supply Voltage

CCIBx

Figure 2-2 • V_CCPLXand V_COMPLXPower Supply Connect

Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See

"Operating Conditions" on page 2-1 for more

information.

User-Defined Supply Pins

Supply Voltage

REF

Reference voltage for I/O banks. V_REFpins are configured

by the user from regular I/O pins; V_REFpins are not in

fixed locations. There can be one or more V_REFpins in an

I/O bank.

Supply Voltage

CCDA

Supply voltage for the I/O differential amplifier and JTAG

and probe interfaces. See "Operating Conditions" on

page 2-1 for more information. V_CCDAshould be tied to

3.3V.

Global Pins

Supply Voltage

CCPLA/B/C/D/E/F/G/H

HCLKA/B/C/D

Dedicated (Hardwired) Clocks A, B, C

and D

PLL analog power supply (1.5V) for internal PLL. There

are eight in each device. V_CCPLAsupports the PLL

associated with global resource HCLKA, V_CCPLBsupports

the PLL associated with global resource HCLKB, etc. The

PLL analog power supply pins should be connected to

1.5V whether PLL is used or not.

These pins are the clock inputs for sequential modules or

north PLLs. Input levels are compatible with all

supported I/O standards. There is a P/N pin pair for

support of differential I/O standards. Single-ended clock

I/Os can only be assigned to the P side of a paired I/O.

This input is directly wired to each R-cell and offers clock

speeds independent of the number of R-cells being

driven. When the HCLK pins are unused, it is

recommended that they are tied to ground.

Supply Voltage

COMPLA/B/C/D/E/F/G/H

Compensation reference signals for internal PLL. There

are eight in each device. V_COMPLAsupports the PLL

associated with global resource HCLKA, V_COMPLE

supports the PLL associated with global resource CLKE,

etc. (see Figure 2-2 on page 2-9 for correct external

connection to the supply). The V_COMPLXpins should be

left floating if PLL is not used.

CLKE/F/G/H

Routed Clocks E, F, G, and H

These pins are clock inputs for clock distribution

networks or south PLLs. Input levels are compatible with

all supported I/O standards. There is a P/N pin pair for

support of differential I/O standards. Single-ended clock

I/Os can only be assigned to the P side of a paired I/O.

The clock input is buffered prior to clocking the R-cells.

When the CLK pins are unused, Actel recommends that

they are tied to ground.

Supply Voltage (External Pump)

PUMP

In the low power mode, V_PUMPwill be used to access an

external charge pump (if the user desires to bypass the

internal charge pump to further reduce power). The

device starts using the external charge pump when the

voltage level on V_PUMPreaches V_IH¹. In normal device

operation, when using the internal charge pump, V_PUMP

should be tied to GND.

1. When V_PUMP= V_IH, it shuts off the internal charge pump. See "Low Power Mode" on page 2-89.

v2.7

2-9

Axcelerator Family FPGAs

JTAG/Probe Pins

User I/Os

PRA/B/C/D

Probe A/B/C/D

Introduction

The Axcelerator family features a flexible I/O structure,

supporting a range of mixed voltages (1.5V, 1.8V, 2.5V,

and 3.3V) with its bank-selectable I/Os. Table 2-8 on

page 2-11 contains the I/O standards supported by the

Axcelerator family, and Table 2-10 on page 2-11

compares the features of the different I/O standards.

The Probe pins are used to output data from any user-

defined design node within the device (controlled with

Silicon Explorer II). These independent diagnostic pins

can be used to allow real-time diagnostic output of any

signal path within the device. The pins’ probe

capabilities can be permanently disabled to protect

programmed design confidentiality. The probe pins are

of LVTTL output levels.

Each I/O provides programmable slew rates, drive

strengths, and weak pull-up and weak pull-down circuits.

I/O standards, except 3.3V PCI and 3.3V PCI-X, are

capable of hot insertion. 3.3V PCI and 3.3V PCI-X are 5V

tolerant with the aid of an external resistor.

TCK

Test Clock

Test clock input for JTAG boundary-scan testing and

diagnostic probe (Silicon Explorer II).

The input buffer has an optional user-configurable delay

element. The element can reduce or eliminate the hold

time requirement for input signals registered within the

I/O cell. The value for the delay is set on a bank-wide

basis. Note that the delay WILL be a function of process

variations as well as temperature and voltage changes.

TDI

Test Data Input

Serial input for JTAG boundary-scan testing and

diagnostic probe. TDI is equipped with an internal 10 kΩ

pull-up resistor.

Each I/O includes three registers: an input (InReg), an

output (OutReg), and an enable register (EnReg). I/Os are

organized into banks, and there are eight banks per

device — two per side (Figure 2-6 on page 2-15). Each I/O

bank has a common V_CCI, the supply voltage for its I/Os.

TDO

Test Data Output

Serial output for JTAG boundary-scan testing.

TMS

Test Mode Select

The TMS pin controls the use of the IEEE 1149.1

boundary-scan pins (TCK, TDI, TDO, TRST). TMS is

equipped with an internal 10 kΩ pull-up resistor.

For voltage-referenced I/Os, each bank also has a

common reference-voltage bus, V_REF. While V_REFmust

have a common voltage for an entire I/O bank, its

location is user-selectable. In other words, any user I/O in

TRST

Boundary Scan Reset Pin

the bank can be selected to be a V_REF

The TRST pin functions as an active-low input to

asynchronously initialize or reset the boundary scan circuit.

The TRST pin is equipped with a 10 kΩ pull-up resistor.

The location of the V_REFpin should be selected according

to the following rules:

•

Any pin that is assigned as a V_REFcan control a

maximum of eight user I/O pad locations in each

direction (16 total maximum) within the same I/O

bank.

Special Functions

Low Power Pin

•

I/O pad locations listed as no connects are counted

as part of the 16 maximum. In many cases, this

leads to fewer than eight user I/O package pins in

each direction being controlled by a V_REFpin.

The LP pin controls the low power mode of Axcelerator

devices. The device is placed in the low power mode by

connecting the LP pin to logic high. To exit the low

power mode, the LP pin must be set Low. Additionally,

the LP pin must be set Low during chip powering-up or

chip powering-down operations. See "Low Power

Mode" on page 2-89 for more details.

•

Dedicated I/O pins (GND, V_CCI...) are counted as

part of the 16.

The two user I/O pads immediately adjacent on each

side of the V_REFpin (four in total) may only be used

No Connection

as an input. The exception is when there is a V_CCI

GND pair separating the V_REFpin and the user I/O

pad location.

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

2. Do not use an external resister to pull the I/O above V_CCIfor a higher logic “1” voltage level. The desired higher logic “1”

voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above V_CCI

2-10

v2.7

Axcelerator Family FPGAs

The differential amplifier supply voltage V_CCDAshould be

connected to 3.3V.

•

Use generic I/O macros and then use Actel

Designer’s PinEditor to specify the desired I/O

standards (please note that this is not applicable

to differential standards)

A user can gain access to the various I/O standards in

three ways:

A combination of the first two methods.

•

Instantiate specific library macros that represent

the desired specific standard

Please refer to the I/O Features in Axcelerator Family

Devices application note and the Antifuse Macro Library

Guide for more details.

Table 2-8 • I/O Standards Supported by the Axcelerator Family

Input/Output Supply Input Reference Voltage

Board Termination Voltage

(V_TT)

I/O Standard

LVTTL

Voltage (V_CCI

)

(V_REF

N/A

1.0

)

3.3

2.5

1.8

1.5

3.3

2.5

1.5

3.3

2.5

3.3

N/A

1.2

LVCMOS 2.5V

LVCMOS 1.8V

LVCMOS 1.5V (JDEC8-11)

3.3V PCI/PCI-X

GTL+ 3.3V

GTL+ 2.5V^*

1.0

1.2

HSTL Class 1

SSTL3 Class 1 and II

SSTL2 Class1 and II

LVDS

0.75

1.5

0.75

1.5

1.25

N/A

1.25

N/A

LVPECL

Note: *2.5V GTL+ is not supported across the full military temperature range.

Table 2-9 • Supply Voltages

V_CCA

1.5V

V_CCI

1.5V

1.8V

2.5V

3.3V

Input Tolerance

Output Drive Level

3.3V

1.5V

1.8V

2.5V

3.3V

Table 2-10 • I/O Features Comparison

I/O Assignment

Clamp Diode

Hot Insertion

5V Tolerance

Input Buffer

Output Buffer

LVTTL

Yes

Yes¹

Yes^{1, 2}

Enabled/Disabled

3.3V PCI, 3.3V PCI-X

LVCMOS2.5V

Enabled/Disabled

Yes

LVCMOS1.8V

LVCMOS1.5V (JESD8-11)

Voltage-Referenced Input Buffer

Differential, LVDS/LVPECL, Input

Differential, LVDS/LVPECL, Output

Notes:

Enabled

Disabled

Disabled³

Enabled⁴

1. Can be implemented with an IDT bus switch.

2. Can be implemented with an external resistor.

3. The OE input of the output buffer must be deasserted permanently (handled by software).

4. The OE input of the output buffer must be asserted permanently (handled by software).

v2.7

2-11

Axcelerator Family FPGAs

recommends that users not exceed eight simultaneous

switching outputs (SSO) per each V_CCI/GND pair. To ease

this potential burden on designers, Actel has designed all

of the Axcelerator BGAs³to not exceed this limit with

the exception of the CS180, which has an I/O to V_CCI/GND

pair ratio of nine to one.

5V Tolerance

There are two schemes to achieve 5V tolerance:

1. 3.3V PCI and 3.3V PCI-X are the only I/O standards

that directly allow 5V tolerance. To implement this,

an internal clamp diode between the input pad and

the V_CCIpad is enabled so that the voltage at the

input pin is clamped as shown in EQ 2-3:

Please refer to the Simultaneous Switching Noise and

Signal Integrity application note for more information.

_input= V_CCI+ V_diode= 3.3V + 0.8V = 4.1V

EQ 2-3

I/O Banks and Compatibility

An external series resister (~100Ω) is required between

the input pin and the 5V signal source to limit the

current (Figure 2-3).

Since each I/O bank has its own user-assigned input

reference voltage (V_REF) and an input/output supply

voltage (V_CCI), only I/Os with compatible standards can

be assigned to the same bank.

Non-Actel Part

Actel FPGA

3.3V 3.3V

Table 2-11 shows the compatible I/O standards for a

common V_REF(for voltage-referenced standards).

Similarly, Table 2-12 shows compatible standards for a

PCI

common V_CCI

clamp

diode

Table 2-11 • Compatible I/O Standards for Different V_REF

Values

ext

V_REF

1.5V

Compatible Standards

SSTL 3 (Class I and II)

1.25V

1.0V

SSTL 2 (Class I and II)

Figure 2-3 • Use of an External Resistor for 5V Tolerance

GTL+ (2.5V and 3.3V Outputs)

HSTL (Class I)

0.75V

2. 5V tolerance can also be achieved with 3.3V I/O

standards (3.3V PCI, 3.3V PCI-X, and LVTTL) using a

bus-switch product (e.g. IDTQS32X2384). This will

convert the 5V signal to a 3.3V signal with minimum

delay (Figure 2-4).

Table 2-12 • Compatible I/O Standards for Different V_CCI

Values

V_CCI

3.3V

2.5V

1.8V

1.5V

Notes:

Compatible Standards

LVTTL, PCI, PCI-X, LVPECL, GTL+ 3.3V

SSTL 3 (Class I and II), LVTTL, PCI, LVPECL

LVCMOS 2.5V, GTL+ 2.5V, LVDS²

V_REF

1.0

3.3V

20X

3.3V

1.5

1.0

LVCMOS 2.5V, SSTL 2 (Classes I and II), LVDS²1.25

LVCMOS 1.8V

N/A

Figure 2-4 • Bus Switch IDTQS32X2384

LVCMOS 1.5V, HSTL Class I

0.75

Simultaneous Switching Outputs (SSO)

1. V_CCIis used for both inputs and outputs

When multiple output drivers switch simultaneously,

they induce a voltage drop in the chip/package power

distribution. This simultaneous switching momentarily

raises the ground voltage within the device relative to

the system ground. This apparent shift in the ground

potential to a non-zero value is known as simultaneous

switching noise (SSN) or more commonly, ground

bounce.

2. V_CCItolerance is 5%

Table 2-13 on page 2-13 summarizes the different

combinations of voltages and I/O standards that can be

used together in the same I/O bank. Note that two I/O

standards are compatible if:

•

Their V_CCIvalues are identical.

Their V_REFstandards are identical (if applicable).

SSN becomes more of an issue in high pin count

packages and when using high performance devices such

as the Axcelerator family. Based upon testing, Actel

3. The user should note that in Bank 8 of both AX1000-FG484 and AX500-FG484, there are local violations of this 8:1 ratio.

2-12

v2.7

Axcelerator Family FPGAs

For example, if LVTTL 3.3V (V_REF= 1.0V) is used, then the

other available (i.e. compatible) I/O standards in the

same bank are LVTTL 3.3V PCI/PCI-X, GTL+, and LVPECL.

Also note that when multiple I/O standards are used

within a bank, the voltage tolerance will be limited to

the minimum tolerance of all I/O standards used in the

bank.

Table 2-13 • Legal I/O Usage Matrix

I/O Standard

LVTTL 3.3V (V_REF=1.0V)

LVTTL 3.3V(V_REF=1.5V)

LVCMOS 2.5V (V_REF=1.0V)

LVCMOS 2.5V (V_REF=1.25V)

LVCMOS1.8V

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

LVCMOS1.5V (V_REF=1.75V) (JESD8-11)

3.3V PCI/PCI-X (V_REF=1.0V)

3.3V PCI/PCI-X (V_REF=1.5V)

GTL + (3.3V)

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

GTL + (2.5V)

✓

–

✓

–

HSTL Class I

–

SSTL2 Class I & II

–

✓

–

✓

–

✓

–

SSTL3 Class I & II

✓

–

✓

–

✓

–

✓

–

LVDS (V_REF=1.0V)

✓

–

✓

–

✓

–

LVDS (V_REF=1.25V)

LVPECL (V_REF=1.0V)

LVPECL (V_REF=1.5V)

Notes:

–

✓

–

✓

–

✓

–

✓

–

1. Note that GTL+ 2.5V is not supported across the full military temperature range.

2. A "✓" indicates whether standards can be used within a bank at the same time.

Examples:

a) LVTTL can be used with 3.3V PCI and GTL+ (3.3V), when V_REF= 1.0V (GTL+ requirement).

b) LVTTL can be used with 3.3V PCI and SSTL3 Class I and II, when V_REF= 1.5V (SSTL3 requirement).

v2.7

2-13

Axcelerator Family FPGAs

I/O CLUSTER

P PAD

EnReg

DIN YOUT

OEP

routed input track

OutREg

routed input track

output track

routed input track

output track

UOP

UIP

YOUT

DIN

I/O

slew rate

drive strength

programmable delay

InReg

DCIN

V_REF

N PAD

EnReg

DIN YOUT

routed input track

OEN

UON

routed input track

OutREg

routed input track

output track

I/O

YOUT

DIN

slew rate

drive strength

programmable delay

InReg

DCIN

output track

UIN

V_REF

Figure 2-5 • I/O Cluster Interface

fuse option in the Designer software, when checked, causes

all I/O registers to output logic High at device power-up.

I/O Clusters

Each I/O cluster incorporates two I/O modules, four RX

modules and two TX modules, and a buffer module. In

turn, each I/O module contains one Input Register

(InReg), one Output Register (OutReg), and one Enable

Using the Weak Pull-Up and Pull-Down

Circuits

Each Axcelerator I/O comes with a weak pull-up/down

circuit (on the order of 10 kΩ). I/O macros are provided

for combinations of pull up/down for LVTTL, LVCMOS

(2.5V, 1.8V, and 1.5V) standards. These macros can be

instantiated if a keeper circuit for any input buffer is

required.

Using an I/O Register

To access the I/O registers, registers must be instantiated

in the netlist and then connected to the I/Os. Usage of

each I/O register (register combining) is individually

controlled and can be selected/deselected using the

PinEditor tool in Actel's Designer software. I/O register

combining can also be controlled at the device level,

affecting all I/Os. Please note, the I/O register option is

deselected by default in any given design.⁴

Customizing the I/O

•

A five-bit programmable input delay element is

associated with each I/O. The value of this delay is

set on a bank-wide basis (Table 2-14 on page 2-15).

It is optional for each input buffer within the bank

(i.e. the user can enable or disable the delay

element for the I/O). When the input buffer drives a

In addition, Designer software provides a global option to

enable/disable the usage of registers in the I/Os. This option

is design-specific. The setting for each individual I/O

overrides this global option. Furthermore, the global set

4. Please note that register combining for multi fanout nets is not supported.

2-14

v2.7

Axcelerator Family FPGAs

activated by default to ensure a zero hold-time.

The default setting for this property can be set in

Designer. When the input buffer does not drive a

provide higher performance. Again, this can be

overridden by changing the default setting for this

property in Designer.

Using the Voltage-Referenced I/O Standards

Using these I/O standards is similar to that of single-

ended I/O standards. Their settings can be changed in

Designer.

Using DDR (Double Data Rate)

In Double Data Rate mode, new data is present on every

transition of the clock signal. Clock and data lines have

identical bandwidth and signal integrity requirements,

making it very efficient for implementing very high-

speed systems.

•

The slew-rate value for the LVTTL output buffer

can be programmed and can be set to either slow

or fast.

The drive strength value for LVTTL output buffers

can be programmed as well. There are four

different drive strength values – 8mA, 12mA,

16mA, or 24mA – that can be specified in

Designer.⁵

To implement a DDR, users need to:

1. Instantiate an input buffer (with the required I/O

standard)

2. Instantiate the DDR_REG macro (Figure 2-6)

Table 2-14 • Bank-Wide Delay Values

Bits Setting Delay (ns) Bits Setting Delay (ns)

3. Connect the output from the Input buffer to the

input of the DDR macro

0.54

0.65

0.71

0.83

0.9

2.01

2.13

2.19

2.3

PSET

2.38

2.49

2.55

2.67

2.75

2.87

2.93

3.04

3.12

3.23

3.29

3.41

CLK

1.01

1.08

1.19

1.27

1.39

1.45

1.56

1.64

1.75

1.81

1.93

CLR

Figure 2-6 • DDR Register

Macros for Specific I/O Standards

There are different macro types for any I/O standard or

feature that determine the required V_CCIand V_REF

voltages for an I/O. The generic buffer macros require

the LVTTL standard with slow slew rate and 24mA-drive

strength. LVTTL can support high slew rate but this

should only be used for critical signals.

Most of the macro symbols represent variations of the six

generic symbol types:

•

CLKBUF: Clock Buffer

Note: Delay values are approximate and will vary with process,

temperature, and voltage.

HCLKBUF: Hardwired Clock Buffer

INBUF: Input Buffer

Using the Differential I/O Standards

OUTBUF: Output Buffer

TRIBUF: Tristate Buffer

BIBUF: Bidirectional Buffer

Differential I/O macros should be instantiated in the

netlist. The settings for these I/O standards cannot be

changed inside Designer. Please note that there are no

tristated or bidirectional I/O buffers for differential

standards.

Other macros include the following:

•

Differential I/O standard macros: The LVDS and

LVPECL macros either have a pair of differential

5. These values are minimum drive strengths.

v2.7

2-15

Axcelerator Family FPGAs

inputs (e.g. INBUF_LVDS) or a pair of differential

outputs (e.g. OUTBUF_LVPECL).

unconnected without having the negative effect

on simulation of propagating unknowns.

•

Pull-up and pull-down variations of the INBUF,

BIBUF, and TRIBUF macros. These are available

only with TTL and LVCMOS thresholds. They can

be used to model the behavior of the pull-up and

pull-down resistors available in the architecture.

Whenever an input pin is left unconnected, the

output pin will either go high or low rather than

unknown. This allows users to leave inputs

•

DDR_REG macro. It can be connected to any I/O

standard input buffers (i.e. INBUF) to implement a

double data rate register. Designer software will

map it to the I/O module in the same way it maps

the other registers to the I/O module.

Table 2-15, Table 2-16 on page 2-17, and Table 2-17 on

page 2-17 list all the available macro names

differentiated by I/O standard, type, slew rate, and drive

strength.

Table 2-15 • Macros for Single-Ended I/O Standards

Standard

V_CCI

Macro Names

LVTTL

3.3V

CLKBUF, HCLKBUF

INBUF,

OUTBUF,

OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24,

OUTBUF_H_8, OUTBUF_H_12, OUTBUF_H_16, OUTBUF_H_24,

TRIBUF,

TRIBUF_S_8, TRIBUF_S_12, TRIBUF_S_16, TRIBUF_S_24,

TRIBUF_H_8, TRIBUF_H_12, TRIBUF_H_16, TRIBUF_H_24,

BIBUF,

BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24,

BIBUF_H_8, BIBUF_H_12, BIBUF_H_16, BIBUF_H_24,

3.3V PCI

3.3V

CLKBUF_PCI, HCLKBUF_PCI,

INBUF_PCI,

OUTBUF_PCI,

TRIBUF_PCI,

BIBUF_PCI

3.3V PCI-X

CLKBUF_PCI-X,

HCLKBUF_PCI-X,

INBUF_PCI-X,

OUTBUF_PCI-X,

TRIBUF_PCI-X,

BIBUF_PCI-X

LVCMOS25

2.5V

1.8V

1.5V

CLKBUF_LVCMOS25,

HCLKBUF_LVCMOS25,

INBUF_LVCMOS25,

OUTBUF_LVCMOS25,

TRIBUF_LVCMOS25,

BIBUF_LVCMOS25

LVCMOS18

CLKBUF_LVCMOS18,

HCLKBUF_LVCMOS18,

INBUF_LVCMOS18,

OUTBUF_LVCMOS18,

TRIBUF_LVCMOS18,

BIBUF_LVCMOS18

LVCMOS15 (JESD8-11)

CLKBUF_LVCMOS15,

HCLKBUF_LVCMOS15,

INBUF_LVCMOS15,

OUTBUF_LVCMOS15,

TRIBUF_LVCMOS15,

BIBUF_LVCMOS15

2-16

v2.7

Axcelerator Family FPGAs

Table 2-16 • I/O Macros for Differential I/O Standards

Standard

V_CCI

Macro Names

CLKBUF_LVPECL, HCLKBUF_LVPECL,

LVPECL

3.3V

INBUF_LVPECL, OUTBUF_LVPECL,

LVDS

2.5V

CLKBUF_LVDS, HCLKBUF_LVDS,

INBUF_LVDS, OUTBUF_LVDS,

Table 2-17 • I/O Macros for Voltage-Referenced I/O Standards

Standard

V_CCI

V_REF

Macro Names

GTL+

3.3V

1.0V

CLKBUF_GTP33, HCLKBUF_GTP33, INBUF_GTP33, OUTBUF_GTP33, TRIBUF_GTP33,

BIBUF_GTP33

GTL+

2.5V

3.3V

1.5V

1.0V

1.25V

1.5V

CLKBUF_GTP25, HCLKBUF_GTP25, INBUF_GTP25, OUTBUF_GTP25, TRIBUF_GTP25,

BIBUF_GTP25

SSTL2 Class I

SSTL2 Class II

SSTL3 Class I

SSTL3 Class II

HSTL Class I

CLKBUF_SSTL2_I,

TRIBUF_SSTL2_I, BIBUF_SSTL2_I

HCLKBUF_SSTL2_I,

INBUF_SSTL2_I,

INBUF_SSTL2_II,

INBUF_SSTL3_I,

INBUF_SSTL3_II,

OUTBUF_SSTL2_I,

OUTBUF_SSTL2_II,

OUTBUF_SSTL3_I,

OUTBUF_SSTL3_II,

CLKBUF_SSTL2_II,

TRIBUF_SSTL2_II, BIBUF_SSTL2_II

HCLKBUF_SSTL2_II,

CLKBUF_SSTL3_I,

TRIBUF_SSTL3_I, BIBUF_SSTL3_I

HCLKBUF_SSTL3_I,

1.5V

CLKBUF_SSTL3_II,

HCLKBUF_SSTL3_II,

TRIBUF_SSTL3_II, BIBUF_SSTL3_II

0.75V

CLKBUF_HSTL_I, HCLKBUF_HSTL_I, INBUF_HSTL_I, OUTBUF_HSTL_I, TRIBUF_HSTL_I,

BIBUF_HSTL_I

v2.7

2-17

Axcelerator Family FPGAs

User I/O Naming Conventions

Due to the complex and flexible nature of the Axcelerator family’s user I/Os, a naming scheme is used to show the

details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for

differential I/Os (Figure 2-7).

GND

V_CCDA

Corner1

I/O BANK 0

I/O BANK 1

Corner2

GND

_CCI7

GND

_CCI2

V_CCA

GND

V_CCA

GND

V_CCDA

GND

AX125

CCDA

V_CCI6

V_CCI3

GND

V_CCA

GND

V_CCA

GND

V_CCDA

GND

V_CCDA

Corner4

I/O BANK 5

I/O BANK 4

Corner3

Figure 2-7 • I/O Bank and Dedicated Pin Layout

IOxxXBxFx

Examples:

IO12PB1F1 is the positive pin of the thirteenth pair of the

first I/O bank (IOB NE). IO12PB1 combined

with IO12NB1 form a differential pair.

For those I/Os that can be employed

either as a user I/O or as a special

Pair number in the

bank, starting at 00,

clockwise from IOB NW

P - Positive Pin/ N- Negative Pin

Bank I/D 0 through 7,

clockwise from IOB NW

function, the following nomenclature

is used:

IOxxXBxFx/special_function_name

IOxxPB1Fx/xCLKx this pin can be configured as a clock

input or as a user I/O.

Fx refers to an

unimplemented feature

and can be ignored.

Figure 2-8 • General Naming Schemes

2-18

v2.7

Axcelerator Family FPGAs

I/O Standard Electrical Specifications

Table 2-18 • Input Capacitance

Symbol

C_IN

Parameter

Input Capacitance

Conditions

Min.

Max.

Units

V_IN=0, f=1.0 MHz

C_INCLK

Input Capacitance on Clock Pin

INBUF

PAD

Input High

V_trip

V_CCA

50%

t _DP

(Rising)

t _DP

GND

(Falling)

Figure 2-9 • Input Buffer Delays

OUT Pad

TRIBUF

To AC test loads (shown below)

V_CCA

50%

V_CCA

50%

V_OH

V_trip

50%

GND

10%

GND

V_CCI/V_TT

VTT

Out

V_trip

V_OH

V_trip

Out

V_OL

90%

V_OL

t_PY

V_TT

ENHZ

Out

GND/V_TT

)

DLH

DHL

t_ENLZ

Figure 2-10 • Output Buffer Delays

v2.7

2-19

Axcelerator Family FPGAs

I/O Module Timing Characteristics

Out

OutReg

EnReg

InReg

CLK

(Routed or

Hardwired)

Figure 2-11 • Timing Model

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_ICLKQ

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-12 • Input Register Timing Characteristics

2-20

v2.7

Axcelerator Family FPGAs

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_OCLKQ

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-13 • Output Register Timing Characteristics

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_OCLKQ

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-14 • Output Enable Register Timing Characteristics

v2.7

2-21

Axcelerator Family FPGAs

3.3V LVTTL

Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3V applications. It uses an LVTTL

input buffer and push-pull output buffer.

Table 2-19 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.4

V_OH

Min,V

2.4

I_OL

I_OH

–24

Min,V

Max,V

Min,V

Max,V

-0.3

0.8

2.0

3.6

AC Loadings

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

R=1k

Test Point

for t_pd

Test Point

for tristate

35 pF for t_pzh/t_pzl

35 pF

_phz/t_plz

5 pF for

Figure 2-15 • AC Test Loads

Table 2-20 • AC Waveforms, Measuring Points, and Capacitive Load

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

3.0

1.40

N/A

* Measuring Point = V_trip

Timing Characteristics

Table 2-21 • 3.3V LVTTL I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

LVTTL Output Drive Strength = 1 (8mA) / Low Slew Rate

t_DP

Input Buffer

1.72

14.32

0.67

1.96

16.31

0.77

2.31

19.19

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

0.67

0.77

0.90

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-22

v2.7

Axcelerator Family FPGAs

Table 2-21 • 3.3V LVTTL I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C (Continued)

'–2' Speed '–1' Speed

Min. Max. Min. Max. Min. Max. Units

'Std' Speed

Parameter

Description

LVTTL Output Drive Strength = 2 (12mA) / Low Slew Rate

t_DP

Input Buffer

1.72

12.18

0.67

1.96

13.87

0.77

2.31

16.31

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

0.67

0.77

0.90

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

LVTTL Output Drive Strength =3 (16mA) / Low Slew Rate

t_DP

Input Buffer

1.72

11.07

0.67

1.96

12.61

0.77

2.31

14.83

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

0.67

0.77

0.90

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

v2.7

2-23

Axcelerator Family FPGAs

Table 2-21 • 3.3V LVTTL I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C (Continued)

'–2' Speed '–1' Speed

Min. Max. Min. Max. Min. Max. Units

'Std' Speed

Parameter

Description

LVTTL Output Drive Strength = 4 (24mA) / Low Slew Rate

t_DP

Input Buffer

1.72

10.49

0.67

1.96

11.95

0.77

2.31

14.05

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

0.67

0.77

0.90

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

LVTTL Output Drive Strength = 1 (8mA) / High Slew Rate

t_DP

Input Buffer

1.72

4.26

0.67

1.96

4.86

0.77

2.31

5.72

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-24

v2.7

Axcelerator Family FPGAs

Table 2-21 • 3.3V LVTTL I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C (Continued)

'–2' Speed '–1' Speed

Min. Max. Min. Max. Min. Max. Units

'Std' Speed

Parameter

Description

LVTTL Output Drive Strength = 2 (12mA) / High Slew Rate

t_DP

Input Buffer

1.72

3.34

0.67

1.96

3.80

0.77

2.31

4.47

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

LVTTL Output Drive Strength =3 (16mA) / High Slew Rate

t_DP

Input Buffer

1.72

3.16

0.67

1.96

3.60

0.77

2.31

4.24

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

v2.7

2-25

Axcelerator Family FPGAs

Table 2-21 • 3.3V LVTTL I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C (Continued)

'–2' Speed '–1' Speed

Min. Max. Min. Max. Min. Max. Units

'Std' Speed

Parameter

Description

LVTTL Output Drive Strength = 4 (24mA) / High Slew Rate

t_DP

Input Buffer

1.72

3.03

0.67

1.96

3.45

0.77

2.31

4.06

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-26

v2.7

Axcelerator Family FPGAs

2.5V LVCMOS

Low-Voltage Complementary Metal-Oxide Semiconductor for 2.5V is an extension of the LVCMOS standard (JESD8-5)

used for general-purpose 2.5V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer.

Table 2-22 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.4

V_OH

Min,V

2.0

I_OL

I_OH

-12

Min,V

Max,V

Min,V

Max,V

-0.3

0.7

1.7

3.6

AC Loadings

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

R=1k

Test Point

for t_pd

Test Point

for tristate

35 pF for t_pzh/t_pzl

35 pF

_phz/t_plz

5 pF for

Figure 2-16 • AC Test Loads

Table 2-23 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

2.5

1.25

N/A

* Measuring Point = V_trip

Timing Characteristics

Table 2-24 • 2.5V LVCMOS I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 2.3V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

LVCMOS25 I/O Module Timing

t_DP

Input Buffer

1.99

3.24

0.67

2.26

3.69

0.77

2.66

4.34

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

v2.7

2-27

Axcelerator Family FPGAs

1.8V LVCMOS

Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8V is an extension of the LVCMOS standard (JESD8-5)

used for general-purpose 1.8V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer.

Table 2-25 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.2

V_OH

I_OL

8mA

I_OH

Min,V

Max,V

Min,V

Max,V

Min,V

V_CCI-0.2

-0.3

0.2V_CCI

0.7V_CCI

3.6

-8mA

AC Loadings

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

R=1k

Test Point

for t_pd

Test Point

for tristate

35 pF for t_pzh/t_pzl

35 pF

_phz/t_plz

5 pF for

Figure 2-17 • AC Test Loads

Table 2-26 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

1.8

0.5V_CCI

N/A

* Measuring Point = V_trip

Timing Characteristics

Table 2-27 • 1.8V LVCMOS I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 1.7V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max. Min. Max.

'Std' Speed

Parameter

Description

Min.

Max. Units

LVCMOS18 Output Module Timing

t_DP

Input Buffer

3.30

4.54

0.67

3.76

5.17

0.77

4.42

6.08

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-28

v2.7

Axcelerator Family FPGAs

1.5V LVCMOS (JESD8-11)

Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5V is an extension of the LVCMOS standard (JESD8-5)

used for general-purpose 1.5V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer.

Table 2-28 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.4

V_OH

I_OL

8mA

I_OH

Min,V

Max,V

Min,V

Max,V

Min,V

V_CCI-0.4

-0.5

0.35V_CCI

0.65V_CCI

3.6

-8mA

AC Loadings

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

R=1k

Test Point

for t_pd

Test Point

for tristate

35 pF for t_pzh/t_pzl

35 pF

_phz/t_plz

5 pF for

Table 2-29 • AC Test Loads

Table 2-30 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

1.5

0.5V_CCI

N/A

* Measuring Point = V_trip

Timing Characteristics

Table 2-31 • 1.5V LVCMOS I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 1.4V, T_J= 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min. Max. Min. Max. Min.

Max.

Units

LVCMOS15 (JESD8-11) I/O Module Timing

t_DP

Input Buffer

3.63

6.02

0.67

4.14

6.86

0.77

4.87

8.07

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

v2.7

2-29

Axcelerator Family FPGAs

3.3V PCI, 3.3V PCI-X

Peripheral Component Interface for 3.3V standard specifies support for both 33 MHz and 66 MHz PCI bus applications.

It uses an LVTTL input buffer and a push-pull output buffer. The input and output buffers are 5V tolerant with the aid

of external components. Axcelerator 3.3V PCI and 3.3V PCI-X buffers are compliant with the PCI Local Bus Specification

Rev. 2.1.

The PCI Compliance Specification requires the clamp diodes to be able to withstand for 11 ns, -3.5V in undershoot, and

7.1V in overshoot.

Table 2-32 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

I_OH

Min,V

-0.5

Max,V

Min,V

0.5V_CCI

Max,V

V_CCI+0.5

Max,V

Min,V

PCI

0.3V_CCI

(per PCI specification)

PCI-X

-0.5

0.35V_CCI

AC Loadings

R to V

R to GND for t_ph

for t_pl

CCI

R=25

R=1k

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

Test point for data

Test Point

for tristate

10pF

35 pF for t_pzl/t_pzh

5 pF for t_phz/t_plz

GND

Figure 2-18 • AC Test Loads

Table 2-33 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

(Per PCI Spec and PCI-X Spec)

N/A

* Measuring Point = V_trip

2-30

v2.7

Axcelerator Family FPGAs

Timing Characteristics

Table 2-34 • 3.3V PCI I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed

Min. Max. Min. Max. Min. Max. Units

'–1' Speed

'Std' Speed

Parameter

Description

3.3V PCI Output Module Timing

t_DP

Input Buffer

1.61

1.95

0.67

1.83

2.22

0.77

2.16

2.62

2.87

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.90

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.00

0.31

t_PRESET

Table 2-35 • 3.3V PCI-X I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

3.3V PCI-X Output Module Timing

t_DP

Input Buffer

1.61

2.14

0.67

1.83

2.44

0.77

2.16

2.87

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

v2.7

2-31

Axcelerator Family FPGAs

Voltage-Referenced I/O Standards

GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential amplifier input buffer

and an Open Drain output buffer. The V_CCIpin should be connected to 2.5V or 3.3V. Note that 2.5V GTL+ is not

supported across the full military temperature range.

Table 2-36 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.6

V_OH

Min,V

I_OL

I_OH

Min,V

Max,V

_REF-0.1

Min,V

Max,V

N/A

V_REF+0.1

N/A

AC Loadings

V_TT

Test Point

10 pF

Figure 2-19 • AC Test Loads

Table 2-37 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

_REF-0.2

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

V_REF+0.2

V_REF

1.0

* Measuring Point = V_trip

Timing Characteristics

Table 2-38 • 2.5V GTL+ I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 2.3V, T_J= 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

2.5V GTL+ I/O Module Timing

t_DP

Input Buffer

1.75

1.01

0.67

1.99

1.15

0.77

2.35

1.36

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-32

v2.7

Axcelerator Family FPGAs

'–1' Speed 'Std' Speed

Table 2-39 • 3.3V GTL+ I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

3.3V GTL+I/O Module Timing

t_DP

Input Buffer

1.75

1.01

0.67

1.99

1.15

0.77

2.35

1.36

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

v2.7

2-33

Axcelerator Family FPGAs

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5V bus standard (EIA/JESD8-6). The Axcelerator devices

support Class I. This requires a differential amplifier input buffer and a push-pull output buffer.

Table 2-40 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.4

V_OH

I_OL

I_OH

-8

Min,V

Max,V

Min,V

Max,V

Min,V

V_CC-0.4

-0.3

V_REF-0.1

V_REF+0.1

3.6

AC Loadings

V_TT

Test Point

20 pF

Figure 2-20 • AC Test Loads

Table 2-41 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

V_REF-0.5

V_REF+0.5

V_REF

0.75

* Measuring Point = V_trip

Timing Characteristics

Table 2-42 • 1.5V HSTL Class I I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 1.425V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

1.5V HSTL Class I I/O Module Timing

t_DP

Input Buffer

1.84

4.93

0.67

2.10

5.62

0.77

2.47

6.61

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-34

v2.7

Axcelerator Family FPGAs

SSTL2

Stub Series Terminated Logic for 2.5V is a general-purpose 2.5V memory bus standard (JESD8-9). The Axcelerator

devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output

buffer.

Class I

Table 2-43 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

7.6

I_OH

-7.6

Min,V

Max,V

_REF-0.2

Min,V

Max,V

V_REF-0.57

Min,V

-0.3

V_REF+0.2

3.6

V_REF+0.57

AC Loadings

V_TT

Test Point

30 pF

Figure 2-21 • AC Test Loads

Table 2-44 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

V_REF-0.75

V_REF+0.75

V_REF

1.25

* Measuring Point = V_trip

Timing Characteristics

Table 2-45 • 2.5V SSTL2 Class I I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 2.3V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

2.5V SSTL2 Class I I/O Module Timing

t_DP

Input Buffer

1.86

2.43

0.67

2.12

2.76

0.77

2.50

3.25

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

v2.7

2-35

Axcelerator Family FPGAs

Class II

Table 2-46 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

15.2

I_OH

Min,V

Max,V

Min,V

Max,V

V_REF-0.8

Min,V

V_REF+0.8

-0.3

V_REF-0.2

V_REF+0.2

3.6

-15.2

AC Loadings

V_TT

Test Point

30 pF

Figure 2-22 • AC Test Loads

Table 2-47 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

V_REF-0.75

V_REF+0.75

V_REF

1.25

* Measuring Point = V_trip

Timing Characteristics

Table 2-48 • 2.5V SSTL2 Class II I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 2.3V, T_J= 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

2.5V SSTL2 Class II I/O Module Timing

t_DP

Input Buffer

1.93

2.43

0.67

2.20

2.76

0.77

2.59

3.25

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-36

v2.7

Axcelerator Family FPGAs

SSTL3

Stub Series Terminated Logic for 3.3V is a general-purpose 3.3V memory bus standard (JESD8-8). The Axcelerator

devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output

buffer.

Class I

Table 2-49 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

I_OH

-8

Min,V

Max,V

_REF-0.2

Min,V

Max,V

V_REF-0.6

Min,V

V_REF+0.6

-0.3

V_REF+0.2

3.6

AC Loadings

V_TT

Test Point

30 pF

Figure 2-23 • AC Test Loads

Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

_REF-1.0

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

V_REF+1.0

V_REF

1.50

*Measuring Point = V_trip

Timing Characteristics

Table 2-51 • 3.3V SSTL3 Class I I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

3.3V SSTL3 Class I I/O Module Timing

t_DP

Input Buffer

1.82

2.21

0.67

2.07

2.52

0.77

2.44

2.96

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

v2.7

2-37

Axcelerator Family FPGAs

Class II

Table 2-52 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

I_OH

-16

Min,V

Max,V

Min,V

Max,V

V_REF-0.8

Min,V

V_REF+0.8

-0.3

V_REF-0.2

V_REF+0.2

3.6

AC Loadings

V_TT

Test Point

30 pF

Figure 2-24 • AC Test Loads

Table 2-53 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

V_REF-1.0

V_REF+1.0

V_REF

1.50

* Measuring Point = V_trip

Timing Characteristics

Table 2-54 • 3.3V SSTL3 Class II I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max.

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max. Units

3.3V SSTL3 Class II I/O Module Timing

t_DP

Input Buffer

1.88

2.21

0.67

2.14

2.52

0.77

2.53

2.96

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-38

v2.7

Axcelerator Family FPGAs

Differential Standards

(OutReg), Enable Register (EnReg), and Double Data

Rate (DDR). However, there is no support for

bidirectional I/Os or tristates with these standards.

Physical Implementation

Implementing differential I/O standards requires the

configuration of a pair of external I/O pads, resulting in a

single internal signal. To facilitate construction of the

differential pair, a single I/O Cluster contains the

resources for a pair of I/Os. Configuration of the I/O

Cluster as a differential pair is handled by Actel's

LVDS

Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a

high-speed, differential I/O standard. It requires that one

data bit is carried through two signal lines, so two pins

are needed. It also requires an external resistor

termination. The voltage swing between these two

signal lines is approximately 350 mV.

Designer software when the user instantiates

differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the

embedded Input Register (InReg), Output Register

FPGA

OUTBUF_LVDS

165Ω

ZO=50Ω

INBUF_LVDS

–

140Ω

100Ω

ZO=50Ω

Figure 2-25 • LVDS Board-Level Implementation

The LVDS circuit consists of differential driver

connected to a terminated receiver through a constant-

impedance transmission line. The receiver is a wide-

current of 3.5 mA. When this current flows through a

100 Ω termination resistor on the receiver side, a voltage

swing of 350 mV is developed across the resistor. The

direction of the current flow is controlled by the data fed

to the driver.

common-mode-range

differential

amplifier.

The

common-mode range is from 0.2V to 2.2V for a

differential input with 400 mV swing.

An external-resistor network (three resistors) is needed

to reduce the voltage swing to about 350 mV. Therefore,

four external resistors are required, three for the driver

and one for the receiver.

To implement the driver for the LVDS circuit, drivers from

two adjacent I/O cells are used to generate the

differential signals (note that the driver is not a current-

mode driver). This driver provides a nominal constant

Table 2-55 • DC Input and Output Levels

DC Parameter

Description

Min.

2.375

1.25

0.9

Typ.

2.5

Max.

2.625

1.6

Units

V_CCI

Supply Voltage

V_OH

Output High Voltage

Output Low Voltage

1.425

1.075

350

V_OL

1.25

450

V_ODIFF

V_OCM

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

250

1.125

0.2

1.25

1.375

2.2

V_ICM

1. +/- 5%

2. Differential input voltage =+/-350mV.

v2.7

2-39

Axcelerator Family FPGAs

Table 2-56 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.2-0.125

1.2+0.125

1.2

* Measuring Point = V_trip

Timing Characteristics

Table 2-57 • LVDS I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 2.3V, T_J= 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

LVDS Output Module Timing

t_DP

Input Buffer

1.84

2.36

0.67

2.10

2.69

0.77

2.47

3.16

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-40

v2.7

Axcelerator Family FPGAs

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit

is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The

voltage swing between these two signal lines is approximately 850 mV.

FPGA

100Ω

ZO=50Ω

OUTBUF_LVPECL

–

INBUF_LVPECL

187Ω

100Ω

Figure 2-26 • LVPECL Board-Level Implementation

The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the

receiver. The values for the three driver resistors are different from that of LVDS since the output voltage levels are

different. Please note that the V_OHlevels are 200 mV below the standard LVPECL levels.

Table 2-58 • DC Input and Output Levels

Min.

Typ.

Max.

DC Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

V_CCI

3.3

3.6

V_OH

1.8

0.96

1.49

0.86

0.3

2.11

1.27

1.92

1.06

1.49

0.86

0.3

2.28

1.43

2.13

1.3

2.41

1.57

V_OL

V_IH

2.72

1.49

0.86

0.3

2.72

V_IL

2.125

Differential Input Voltage

Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.6-0.3

1.6+0.3

1.6

* Measuring Point = V_trip

v2.7

2-41

Axcelerator Family FPGAs

Timing Characteristics

Table 2-60 • LVPECL I/O Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

LVPECL Output Module Timing

t_DP

Input Buffer

1.70

2.28

0.67

1.93

2.60

0.77

2.28

3.06

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O

enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.43

0.45

0.43

0.48

0.51

0.48

0.57

0.60

0.57

0.10

0.00

0.23

0.10

0.00

0.27

0.10

0.00

0.31

t_PRESET

2-42

v2.7

Axcelerator Family FPGAs

Module Specifications

C-Cell

•

A carry input and a carry output. The carry input

signal of the C-cell is the carry output from the C-

cell directly to the north.

Introduction

The C-cell is one of the two logic module types in the AX

architecture. It is the combinatorial logic resource in the

Axcelerator device. The AX architecture implements a

new combinatorial cell that is an extension of the C-cell

implemented in the SX-A family. The main enhancement

of the new C-cell is the addition of carry-chain logic.

•

Carry connect for carry-chain logic with a signal

propagation time of less than 0.1 ns.

A hardwired connection (direct connect) to the

adjacent R-cell (Register Cell) for all C-cells on the

east side of

propagation time of less than 0.1 ns.

a SuperCluster with a signal

The C-cell can be used in a carry-chain mode to construct

arithmetic functions. If carry-chain logic is not required,

it can be disabled.

This layout of the C-cell (and the C-cell Cluster) enables

the implementation of over 4,000 functions of up to five

bits. For example, two C-cells can be used together to

implement a four-input XOR function in a single cell

delay.

The C-cell features the following (Figure 2-27):

•

Eight-input MUX (data: D0-D3, select: A0, A1, B0,

B1). User signals can be routed to any one of these

inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0,

B1) can be tied to one of the four routed clocks

(CLKE/F/G/H).

The carry-chain configuration is handled automatically

for the user with Actel's extensive macro library (please

see Actel’s Antifuse Macro Library Guide for a complete

listing of available Axcelerator macros).

•

Inverter (DB input) can be used to drive a

complement signal of any of the inputs to the C-

cell.

FCI

CFN

D1 D3 B0 B1

0 1

D0 D2

FCO

Figure 2-27 • C-Cell

v2.7

2-43

Axcelerator Family FPGAs

Timing Model and Waveforms

V_CCA

50%

A, B, D, FCI

GND

50%

V_CCA

50%

Y, FCO

GND

t_PD, t_PDC

V_CCA

Y, FCO

50%

t_PD, t_PDC

50%

GND

t_PD, t_PDC

Figure 2-28 • C-Cell Timing Model and Waveforms

Timing Characteristics

Table 2-61 • C-Cell

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

C-Cell Propagation Delays

t_PD

Any input to output Y

0.74

0.57

0.95

0.61

0.08

0.84

0.64

1.09

0.69

0.09

0.99

0.76

1.28

0.82

0.11

t_PDC

t_PDB

t_CCY

t_CC

Any input to carry chain output (FCO)

Any input through DB when one input is used

Input to carry chain (FCI) to Y

Input to carry chain (FCI) to carry chain output (FCO)

2-44

v2.7

Axcelerator Family FPGAs

Carry-Chain Logic

The Axcelerator dedicated carry-chain logic offers a very

compact solution for implementing arithmetic functions

without sacrificing performance.

C-cell pair, drives the FCI input of the C-cell pair

immediately below it (Figure 1-4 on page 1-3 and

Figure 2-30 on page 2-46).

To implement the carry-chain logic, two C-cells in a

Cluster are connected together so the FCO (i.e. carry out)

for the two bits is generated in a carry look-ahead

scheme to achieve minimum propagation delay from the

FCI (i.e. carry in) into the two-bit Cluster. The two-bit

carry logic is shown in Figure 2-29.

The carry-chain logic is selected via the CFN input. When

carry logic is not required, this signal is deasserted to

save power. Again, this configuration is handled

automatically for the user through Actel's macro library.

The signal propagation delay between two C-cells in the

carry-chain sequence is 0.1 ns.

The FCI of one C-cell pair is driven by the FCO of the

C-cell pair immediately above it. Similarly, the FCO of one

DCOUT

Figure 2-29 • Axcelerator’s Two-Bit Carry Logic

v2.7

2-45

Axcelerator Family FPGAs

FCI₁

R-cell1

DCIN

C-cell2

DCOUT

C-cell1

FCO₂

FCI₃

DCOUT

DCIN

FCO₄

FCI₅

n-2

Clusters

FCI_(2n-1)

R-celln

CDIN

C-cell

(2n-1)

C-cell2n

DCOUT

FCO_2n

Note: The carry-chain sequence can end on either C-cell.

Figure 2-30 • Carry-Chain Sequencing of C-cells

Timing Characteristics

Refer to the Table 2-61 on page 2-44 for more information on carry-chain timing.

2-46

v2.7

Axcelerator Family FPGAs

R-Cell

•

Clock can be driven by any of the following (CKP

selects clock polarity):

Introduction

The R-cell, the sequential logic resource of the

Axcelerator devices, is the second logic module type in

the AX family architecture. It includes clock inputs for all

eight global resources of the Axcelerator architecture as

well as global presets and clears (Figure 2-31).

–

One of the four high performance hardwired

fast clocks (HCLKs)

–

One of the four routed clocks (CLKs)

User signals

The main features of the R-cell include the following:

Global power-on clear (GCLR) and preset (GPSET),

which drive each flip-flop on a chip-wide basis.

•

Direct connection to the adjacent logic module

through the hardwired connection DCIN. DCIN is

driven by the DCOUT of an adjacent C-cell via the

–

When the Global Set Fuse option in the

Designer software is unchecked (by default),

GCLR = 0 and GPSET =1 at device power-up.

When the option is checked, GCLR = 1 and

GPSET= 0. Both pins are pulled High when the

device is in user mode.

Direct-Connect routing resource, providing

connection with less than 0.1 ns of routing delay.

•

The R-cell can be used as a standalone flip-flop. It

can be driven by any C-cell or I/O modules through

the regular routing structure (using DIN as a

routable data input). This gives the option of

using the R-Cell as a 2:1 MUXed flip-flop as well.

•

S0, S1, PSET, and CLR can be driven by routed

clocks CLKE/F/G/H or user signals.

DIN and S1 can be driven by user signals.

•

Provision of data enable-input (S0).

As with the C-cell, the configuration of the R-cell to

perform various functions is handled automatically for

the user through Actel's extensive macro library (please

see Actel’s Antifuse Macro Library Guide for a complete

listing of available AX macros).

Independent active-low asynchronous clear (CLR).

Independent active-low asynchronous preset

(PSET). If both CLR and PSET are low, CLR has

higher priority.

DIN(user signals)

DCIN

HCLKA/B/C/D

CLKE/F/G/H

Internal Logic

Figure 2-31 • R-Cell

v2.7

2-47

Axcelerator Family FPGAs

Timing Models and Waveforms

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_RCO

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-32 • R-Cell Delays

Timing Characteristics

Table 2-62 • R-Cell

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

R-Cell Propagation Delays

t_RCO

Sequential Clock-to-Q

Asynchronous Clear-to-Q

0.67

0.23

0.26

0.00

0.77

0.27

0.30

0.00

0.90

0.31

0.35

0.00

t_CLR

t_PRESET

t_SUD

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Enable Input Set-Up

Flip-Flop Data Input Hold

t_SUE

t_HD

t_HE

Flip-Flop Enable Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Clock Pulse Width High to Low

Clock Pulse Width Low to High

t_WASYN

t_REASYN

t_HASYN

t_CPWHL

t_CPWLH

0.43

0.48

0.57

0.10

0.00

0.10

0.00

0.10

0.00

0.42

0.40

0.47

0.46

0.55

0.54

2-48

v2.7

Axcelerator Family FPGAs

Buffer Module

Introduction

An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When a fanout

constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has been added to

the AX architecture to avoid logic duplication resulting from the hard fanout constraints. The router utilizes this logic

resource to save area and reduce loading and delays on medium-to-high-fanout nets.

Timing Models and Waveforms

OUT

Figure 2-33 • Buffer Module Timing Model

V_CCA

50%

V_CCA

GND

50%

OUT

GND

t_BFPD

Figure 2-34 • Buffer Module Waveform

Timing Characteristics

Table 2-63 • Buffer Module

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Buffer Module Propagation Delays

t_BFPDAny input to output Y

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

0.12

0.14

0.16

v2.7

2-49

Axcelerator Family FPGAs

Routing Specifications

Routing Resources

The routing structure found in Axcelerator devices

enables any logic module to be connected to any other

logic module while retaining high performance. There

are multiple paths and routing resources that can be

used to route one logic module to another, both within a

SuperCluster and elsewhere on the chip.

DirectConnect

DirectConnects provide

high-speed connection

between an R-cell and its adjacent C-cell (Figure 2-35).

This connection can be made from DCOUT of the C-cell

to DCIN of the R-cell by configuring of the S1 line of the

R-cell. This provides a connection that does not require

an antifuse and has a delay of less than 0.1 ns.

There are four primary types of routing within the AX

architecture: DirectConnect, CarryConnect, FastConnect,

and Vertical and Horizontal Routing.

Figure 2-35 • DirectConnect and CarryConnect

then be routed through a single antifuse connection to

drive the inputs of logic modules either within one

SuperCluster or in the SuperCluster immediately below

it.

CarryConnect

CarryConnects are used to build carry chains for

arithmetic functions (Figure 2-35). The FCO output of the

right C-cell of a two-C-cell Cluster drives the FCI input of

the left C-cell in the two-C-cell Cluster immediately

below it. This pattern continues down both sides of each

SuperCluster column.

Vertical and Horizontal Routing

Vertical and Horizontal Tracks provide both local and

long distance routing (Figure 2-37 on page 2-51). These

tracks are composed of both short-distance, segmented

routing and across-chip routing tracks (segmented at

core tile boundaries). The short-distance, segmented

routing resources can be concatenated through antifuse

connections to build longer routing tracks.

Similar to the DirectConnects, CarryConnects can be built

without an antifuse connection. This connection has a

delay of less than 0.1 ns from the FCO of one two-C-cell

cluster to the FCI of the two-C-cell cluster immediately

below it (see the "Carry-Chain Logic" on page 2-45 for

more information).

These short-distance routing tracks can be used within

and between SuperClusters or between modules of non-

adjacent SuperClusters. They can be connected to the

Output Tracks and to any logic module input (R-cell,

C-cell, Buffer, and TX module).

FastConnect

For high-speed routing of logic signals, FastConnects can

be used to build a short distance connection using a

single antifuse (Figure 2-36 on page 2-51). FastConnects

provide a maximum delay of 0.3 ns. The outputs of each

logic module connect directly to the Output Tracks

within a SuperCluster. Signals on the Output Tracks can

The across-chip horizontal and vertical routing provides

long-distance routing resources. These resources

interface with the rest of the routing structures through

2-50

v2.7

Axcelerator Family FPGAs

the RX and TX modules (Figure 2-37). The RX module is

used to drive signals from the across-chip horizontal and

vertical routing to the Output Tracks within the

SuperCluster. The TX module is used to drive vertical and

horizontal across-chip routing from either short-distance

horizontal tracks or from Output Tracks. The TX module

can also be used to drive signals from vertical across-chip

tracks to horizontal across-chip tracks and vice versa.

Figure 2-36 • FastConnect Routing

Figure 2-37 • Horizontal and Vertical Tracks

v2.7

2-51

Axcelerator Family FPGAs

Timing Characteristics

Table 2-64 • AX125 Predicted Routing Delays

Worst-Case Commercial Conditions V_CCA= 1.425V, T_J= 70°C

'–2' Speed

'–1' Speed

Typical

'Std' Speed

Typical

Parameter

Description

Typical

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

0.11

0.35

0.38

0.43

0.48

0.55

0.64

0.79

0.88

1.49

2.32

0.12

0.39

0.40

0.43

0.48

0.55

0.62

0.72

0.89

0.99

1.69

2.63

0.15

0.46

0.47

0.51

0.57

0.64

0.73

0.85

1.05

1.17

1.99

3.10

t_FC

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

Table 2-65 • AX250 Predicted Routing Delays

Worst-Case Commercial Conditions V_CCA= 1.425V, T_J= 70°C

'–2' Speed

'–1' Speed

Typical

'Std' Speed

Typical

Parameter

Description

Typical

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

0.11

0.35

0.39

0.41

0.48

0.56

0.60

0.84

0.90

1.00

2.17

3.55

0.12

0.39

0.45

0.46

0.55

0.63

0.68

0.96

1.02

1.13

2.46

4.03

0.15

0.46

0.53

0.54

0.64

0.75

0.80

1.13

1.20

1.33

2.89

4.74

t_FC

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

2-52

v2.7

Axcelerator Family FPGAs

Table 2-66 • AX500 Predicted Routing Delays

Worst-Case Commercial Conditions V_CCA= 1.425V, T_J= 70°C

'–2' Speed

Typical

'–1' Speed

Typical

'Std' Speed

Typical

Parameter

Description

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

0.11

0.35

0.39

0.41

0.48

0.56

0.60

0.84

0.90

1.00

2.17

3.55

0.12

0.39

0.45

0.46

0.55

0.63

0.68

0.96

1.02

1.13

2.46

4.03

0.15

0.46

0.53

0.54

0.64

0.75

0.80

1.13

1.20

1.33

2.89

4.74

t_FC

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

Table 2-67 • AX1000 Predicted Routing Delays

Worst-Case Commercial Conditions V_CCA= 1.425V, T_J= 70°C

'–2' Speed

'–1' Speed

Typical

'Std' Speed

Typical

Parameter

Description

Typical

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

0.12

0.35

0.45

0.53

0.56

0.63

0.73

0.99

1.02

1.48

2.57

4.24

0.13

0.39

0.51

0.60

0.63

0.71

0.82

1.13

1.15

1.68

2.91

4.81

0.15

0.46

0.60

0.71

0.74

0.84

0.97

1.32

1.36

1.97

3.42

5.65

t_FC

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

v2.7

2-53

Axcelerator Family FPGAs

Table 2-68 • AX2000 Predicted Routing Delays

Worst-Case Commercial Conditions V_CCA= 1.425V, T_J= 70°C

'–2' Speed

Typical

'–1' Speed

Typical

'Std' Speed

Typical

Parameter

Description

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

0.12

0.35

0.50

0.59

0.70

0.76

0.98

1.48

1.65

1.73

2.58

4.24

0.13

0.39

0.56

0.67

0.80

0.87

1.11

1.68

1.87

1.96

2.92

4.81

0.15

0.46

0.66

0.79

0.94

1.02

1.31

1.97

2.20

2.31

3.44

5.65

t_FC

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

2-54

v2.7

Axcelerator Family FPGAs

Global Resources

One of the most important aspects of any FPGA

architecture is its global resources or clocks. The

Axcelerator family provides the user with flexible and

easy-to-use global resources, without the limitations

normally found in other FPGA architectures.

Hardwired Clocks

The hardwired (HCLK) is a low-skew network that can

directly drive the clock inputs of all sequential modules

(R-cells, I/O registers, and embedded RAM/FIFOs) in the

device with no antifuse in the path. All four HCLKs are

available everywhere on the chip.

The AX architecture contains two types of global

resources, the HCLK (hardwired clock) and CLK (routed

clock). Every Axcelerator device is provided with four

HCLKs and four CLKs for a total of eight clocks,

regardless of device density.

Timing Characteristics

Table 2-69 • AX125 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max.

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

3.02

3.03

3.44

3.46

4.05

4.06

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

Table 2-70 • AX250 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max.

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

2.57

2.61

2.93

2.97

3.45

3.50

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

v2.7

2-55

Axcelerator Family FPGAs

Table 2-71 • AX500 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed

Min. Max.

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

2.35

2.44

2.68

2.79

3.15

3.27

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

Table 2-72 • AX1000 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max.

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

3.02

3.03

3.44

3.46

4.05

4.06

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

Table 2-73 • AX2000 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max.

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

3.02

3.03

3.44

3.46

4.05

4.06

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

2-56

v2.7

Axcelerator Family FPGAs

Routed Clocks

The routed clock (CLK) is a low-skew network that can

drive the clock inputs of all sequential modules in the

device (logically equivalent to the HCLK), but has the

added flexibility in that it can drive the S0 (Enable), S1,

PSET, and CLR input of a register (R-cells and I/O

registers) as well as any of the inputs of any C-cell in the

device. This allows CLKs to be used not only as clocks, but

also for other global signals or high fanout nets. All four

CLKs are available everywhere on the chip.

Timing Characteristics

Table 2-74 • AX125 Routed Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Min. Max.

Parameter

Description

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

3.08

3.13

3.50

3.56

4.12

4.19

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

Table 2-75 • AX250 Routed Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Min. Max.

Parameter

Description

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

2.52

2.59

2.87

2.95

3.37

3.47

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

v2.7

2-57

Axcelerator Family FPGAs

Table 2-76 • AX500 Routed Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

2.31

2.44

2.63

2.78

3.09

3.27

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

Table 2-77 • AX1000 Routed Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

3.08

3.13

3.50

3.56

4.12

4.19

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

Table 2-78 • AX2000 Routed Array Clock Networks

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

3.08

3.13

3.50

3.56

4.12

4.19

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

2-58

v2.7

Axcelerator Family FPGAs

Global Resource Distribution

At the root of each global resource is a PLL. There are

two groups of four PLLs for every device. One group,

located at the center of the north edge (in the I/O ring)

of the chip, sources the four HCLKs. The second group,

located at the center of the south edge (again in the I/O

ring), sources the four CLKs (Figure 2-38).

Regardless of the type of global resource, HCLK or CLK,

each of the eight resources reach the ClockTileDist (CTD)

Cluster located at the center of every core tile with zero

skew. From the ClockTileDist Cluster, all four HCLKs and

four CLKs are distributed through the core tile (Figure 2-

39).

PLL

P N

PLL

P N

PLL

P N

PLL Cluster

HCLKA HCLKB HCLKC HCLKD

CLKE

CLKF

CLKG

CLKH

PLL Cluster

P N

PLL

Figure 2-38 • PLL Group

HCLK

PLL Group

CLK

ClockTileDist Cluster

PLL Group

Figure 2-39 • Example of HCLK and CLK Distributions on the AX2000

v2.7

2-59

Axcelerator Family FPGAs

The ClockTileDist Cluster contains an HCLKMux (HM)

module for each of the four HCLK trees and a CLKMux

(CM) module for each of the CLK trees. The HCLK

branches then propagate horizontally through the

middle of the core tile to HCLKColDist (HD) modules in

every SuperCluster column. The CLK branches propagate

vertically through the center of the core tile to

CLKRowDist (RD) modules in every SuperCluster row.

Together, the HCLK and CLK branches provide for a low-

skew global fanout within the core tile (Figure 2-40 and

Figure 2-41).

Figure 2-40 • CTD, CD, and HD Module Layout

Figure 2-41 • HCLK and CLK Distribution within a Core Tile

2-60

v2.7

Axcelerator Family FPGAs

The HM and CM modules can select between:

CLKINT and HCLKINT

•

The HCLK or CLK source respectively

CLKINT (HCLKINT) is used to access the CLK (HCLK)

resourceinternallyfromtheusersignals(Figure 2-43).

A local signal routed on generic routing resources

This allows each core tile to have eight clocks

independent of the other core tiles in the device.

Both HCLK and CLK are segmentable, meaning that

individual branches of the global resource can be used

independently.

Clock

Network

Logic

CLKINT

HCLKINT

Like the HM and CM modules, the HD and RD modules

can select between:

Figure 2-43 • CLKINT and HCLKINT

•

The HCLK or CLK source from the HM or CM

module respectively

PLLRCLK and PLLHCLK

•

A local signal routed on generic routing resources

PLLRCLK (PLLHCLK) is used to drive global resource

CLK (HCLK) from a PLL (Figure 2-44).

The AX architecture is capable of supporting a large

number of local clocks – 24 segments per HCLK driving

north-south and 28 segments per CLK driving east-west

per core tile.

Actel's Designer software’s place-and-route takes

advantage of the segmented clock structure found in

Axcelerator devices by turning off any unused clock

segments. This results in not only better performance but

also lower power consumption.

Clock

Network

RefCLK

PLL

CLK1

CLK2

PLLRCLK

PLLHCLK

Figure 2-44 • PLLRCLK and PLLHCLK

Global Resource Access Macros

Global resources can be driven by one of three sources:

external pad(s), an internal net, or the output of a PLL.

These connections can be made by using one of three

types of macros: CLKBUF, CLKINT, and PLLCLK.

Using Global Resources with PLLs

Each global resource has an associated PLL at its root. For

example, PLLA can drive HCLKA, PLLE can drive CLKE, etc.

(Figure 2-45 on page 2-62).

CLKBUF and HCLKBUF

In addition, each clock pin of the package can be used to

drive either its associated global resource or PLL. For

example, package pins CLKEP and CLKEN can drive either

the RefCLK input of PLLE or CLKE.

CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from

external pads. These macros can be used either

generically or with the specific I/O standard desired

(e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.)

(Figure 2-42).

There are two macros required when interfacing the

embedded PLLs with the global resources: PLLINT and PLLOUT.

PLLINT

This macro is used to drive the RefCLK input of the PLL

internally from user signals.

Clock

Network

PLLOUT

This macro is used to connect either the CLK1 or CLK2

output of a PLL to the regular routing network (Figure 2-

46 on page 2-62).

CLKBUF

HCLKBUF

Figure 2-42 • CLKBUF and HCLKBUF

Package pins CLKEP and CLKEN are associated with

CLKE; package pins HCLKAP and HCLKAN are

associated with HCLKA, etc.

Note that when CLKBUF (HCLKBUF) is used with a

single-ended I/O standard, it must be tied to the P-

pad of the CLK (HCLK) package pin. In this case, the

CLK (HCLK) N-pad can be used for user signals.

v2.7

2-61

Axcelerator Family FPGAs

Implementation Example:

Figure 2-47 shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being sourced from

non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the RefCLK input of PLLF. The CLK2

output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving the global resource CLKE. PLLF is driving both

CLKF and CLKG global resources.

HCLKAP

HCLKA

Network

RefCLK

CLK1

CLK2

PLLA

HCLKAN

PLLHCLK

Figure 2-45 • Example of HCLKA driven from a PLL with External Clock Source

PLLINT

PLLHCLK

HCLKA

Network

CLK1

CLK2

RefCLK

PLLA

Logic

PLLOUT

Figure 2-46 • Example of PLLINT and PLLOUT Usage

Non-Clock

Pins

INBUF

PLLINT

PLLRCLK

RefCLK

PLLE

CLK1

CLK2

CLKINT

PLLOUT

Logic

CLKE

PLLRCLK

CLKF

RefCLK

PLLF

CLK1

CLK2

CLKG

PLLRCLK

Figure 2-47 • Complex Clock Distribution Example

2-62

v2.7

Axcelerator Family FPGAs

Axcelerator Clock Management System

southern edge. The northern group is associated with

the four HCLK networks (e.g. PLLA can drive HCLKA),

while the southern group is associated with the four CLK

networks (e.g. PLLE can drive CLKE).

Introduction

Each member of the Axcelerator family contains eight

phase-locked loop (PLL) blocks which perform the

following functions:

Each PLL cell is connected to two I/O pads and a PLL

Cluster that interfaces with the FPGA core. Figure 2-48

illustrates a PLL block. The V_CCPLLpin should be

connected to a 1.5V power supply through a 250 Ω

resistor. Furthermore, 0.1 μF and 10 μF decoupling

capacitors should be connected across the V_CCPLLand

V_COMPPLLpins. Note: The V_COMPPLLpin should never be

grounded (Figure 2-2 on page 2-9)!

•

Programmable Delay (32 steps of 250 ps)

Clock Skew Minimization

Clock Frequency Synthesis

Each PLL has the following key features:

•

Input Frequency Range – 14 to 200 MHz

Output Frequency Range – 20 MHz to 1 GHz

Output Duty Cycle Range – 45% to 55%

The I/O pads associated with the PLL can also be

configured for regular I/O functions except when it is

used as a clock buffer. The I/O pads can be configured in

all the modes available to the regular I/O pads in the

same I/O bank. In particular, the [H]CLKxP pad can be

configured as a differential pair, single-ended, or

voltage-referenced standard. The [H]CLKxN pad can only

be used as a differential pair with [H]CLKxP.

Maximum Long-Term Jitter

(whichever is greater)

–

1% or 100ps

•

Maximum Short-Term Jitter – 50ps + 1% of Output

Frequency

Maximum Acquisition Time (lock) – 20µs

The block marked “/i Delay Match” is a fixed delay equal

to that of the i divider. The “/j Delay Match” block has

the same function as its j divider counterpart.

Physical Implementation

The eight PLL blocks are arranged in two groups of four.

One group is located in the center of the northern edge

of the chip, while the second group is centered on the

DIVJ

Lock

PowerDown

RefCLK

Delay Line

/i Delay

Match

CLK1

PLL

Delay Line

/j Delay

Match

CLK2

FBMuxSel

DelayLine

DIVJ

LowFreq

Osc

Figure 2-48 • PLL Block Diagram

v2.7

2-63

Axcelerator Family FPGAs

•

CLK2 provides the PLL output directly—without

division

Functional Description

Figure 2-48 on page 2-63 illustrates a block diagram of

the PLL. The PLL contains two dividers, i and j, that allow

frequency scaling of the clock signal:

The input and output frequency ranges are selected by

LowFreq and Osc(2:0), respectively. These functions and

their possible values are detailed in Table 2-79.

•

The i divider in the feedback path allows

The delay lines shown in Figure 2-48 on page 2-63 are

programmable. The feedback clock path can be delayed

(using the five DelayLine bits) relative to the reference

clock (or vice versa) by up to 3.75 ns in increments of

250 ps. Table 2-79 describes the usage of these bits. The

delay increments are independent of frequency, so this

results in phase changes that vary with frequency. The

delay value is highly dependent on V_CCand the speed

grade.

multiplication of the input clock by integer factors

ranging from 1 to 64, and the resultant frequency

is available at the output of the PLL block.

The j divider divides the PLL output by integer

factors ranging from 1 to 64, and the divided clock

is available at CLK1.

The two dividers together can implement any

combination of multiplication and division up to a

maximum frequency of 1 GHz on CLK1. Both the

CLK1 and CLK2 outputs have a fixed 50/50 duty

cycle.

The output frequencies of the two clocks are given

by the following formulas (f_REFis the reference

clock frequency):

•

Figure 2-49 on page 2-65 is a logical diagram of the

various control signals to the PLL and shows how the PLL

interfaces with the global and routing networks of the

FPGA. Note that not all signals are user-accessible. These

non-user-accessible signals are used by Actel's place-and-

route tool to control the configuration of the PLL. The

user gains access to these control signals either based

upon the connections built in the user's design or

through the special macros (Table 2-83 on page 2-67)

inserted into the design. For example, connecting the

macro PLLOUT to CLK2 will control the OUTSEL signal.

•

f_CLK1= f_REF* (DividerI) / (DividerJ)

EQ 2-4

EQ 2-5

f_CLK2= f_REF* (DividerI)

Table 2-79 • PLL Interface Signals

Signal Name

RefCLK

Type

Input

User Accessible Allowable Values

Function

Reference Clock for the PLL

Feedback port for the PLL

PLL power down control

PLL powered down

Yes

PowerDown

PLL active

DIVI[5:0]

DIVJ[5:0]

Input

Yes

1 to 64, in unsigned

binary notation offset

by -1

Sets value for feedback divider (multiplier)

Sets value for CLK1 divider

LowFreq

Input

Yes

Input frequency range selector

50–200 MHz

14–50 MHz

Osc[2:0]

Input

Yes

Output frequency range selector

XX0

001

400–1000 MHZ

200–400 MHZ

011

100–200 MHZ

101

50–100 MHZ

111

20–50 MHZ

DelayLine[4:0]

Input

Yes

–15 to +15

Clock Delay (positive/negative) in increments of 250 ps, with

(increments), in signed- maximum value of 3.75 ns

and-magnitude binary

representation

FBMuxSel

REFSEL

Input

Selects the source for the feedback input

Selects the source for the reference clock

Selects the source for the routed net output

OUTSEL

2-64

v2.7

Axcelerator Family FPGAs

Table 2-79 • PLL Interface Signals (Continued)

Signal Name

Type

User Accessible Allowable Values

Function

PLLSEL

Input

ROOTSEL & PLLSEL are used to select the source of the global

clock network

ROOTSEL

Lock

Input

Yes

Output

High value indicates PLL has locked

PLL clock output

CLK1

CLK2

PLL clock output

Note: If the input RefClk is taken outside its operating range, the outputs Lock, CLK1 and CLK2 are indeterminate.

ROOTSEL

REFSEL

CLKINT

CLK1 (PLLn-1)

[H]CLKINT

RefCLK

CLK1

CLK2

[H]CLK

[H]CLKxP

PLLSEL

PLL

I/O

Core net

CLK net

CLK Out

(Routed net out pin)

FBINT

[H]CLKxN

OUTSEL

FBMuxSEL

To PLLn+1

Note: Not all signals are available to the user.

Figure 2-49 • PLL Logical Interface

PLL Configurations

The following rules apply to the different PLL inputs and

outputs:

Regular, LVPECL, or LVDS IOPAD

Non-clock

Reference Clock

The RefCLK can be driven by (Figure 2-50):

INBUF

Pins

RefCLK

PLL

1. Global routed clocks (CLKE/F/G/H) or user-created

clock network

2. CLK1 output of an adjacent PLL

Any macro from the core, except HCLK nets

3. [H]CLKxP (single-ended or voltage-referenced)

4. [H]CLKxP/[H]CLKxN pair (differential modes like

LVPECL or LVDS)

RefCLK

PLL

Logic

Feedback Clock

The feedback clock can be driven by (Figure 2-51 on page

2-66):

For cascading

1. Global routed clocks (CLKE/F/G/H) or user-created

clock network

CLK1 RefCLK

PLL

2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL

cell

Figure 2-50 • Reference Clock Connections

3. An internal signal from the PLL block

v2.7

2-65

Axcelerator Family FPGAs

Table 2-81 • North PLL Connections

PLLOUT/PLLRCLK

CLK1

CLK2

HCLK1

Routed net

HCLK1

Unused

PLL

HCLK2

HCLK1

HCLK2

Routed net

HCLK2

Both HCLK1 and routed net

Unused

Any macro except HCLK macros

HCLK2

Unused

HCLK1

PLL

Unused

Routed net

Both HCLK1 and routed net

Unused

Figure 2-51 • Feedback Clock Connections

Unused

Routed net

HCLK1

CLK1 and CLK2

Routed net

Unused

Both PLL outputs, CLK1 and CLK2, can be used to drive a

global resource, an adjacent PLL RefCLK input, or a net in

the FPGA core. Not all drive combinations are possible

(Table 2-80).

Both HCLK1 and HCLK2

Both HCLK1 and routed net

Both HCLK2 and routed net

Routed net

Unused

Unusable

Table 2-80 • PLL General Connections Rules

HCLK1

CLK1

CLK2

Unused

HCLK1, HCLK2, and routed net Unusable

HCLK

CLK

Note: Designer software currently does not support all of these

connections. Only exclusive connections where one

output connects to a single net are supported at this time

(e.g.CLK1 driving HCLK1, and HCLK2 is not supported).

CLK

HCLK

Routed net output

HCLK

Routed net output

HCLK

Table 2-82 • South PLL Connections

NONE

CLK1

CLK2

NONE

HCLK

CLK1

Routed net

Unused

CLK

NONE

CLK1

NONE

CLK

CLK2

CLK1

CLK2

Routed net

Note: The PLL outputs remain Low when REFCLK is constant

(either Low or High).

CLK2

Both CLK1 and routed net

Unused

CLK2

Restrictions on CLK1 and CLK2

Unused

CLK1

•

When both are driving global resources, they must

be driving the same type of global resource (i.e.

either HCLK or CLK).

Unused

Routed net

Both CLK1 and routed net

Unused

•

Only one can drive a routed net at any given time.

Routed net

CLK1

Table 2-81 and Table 2-82 specify all the possible CLK1

and CLK2 connections for the north and south PLLs.

HCLK1 and HCLK2 are used to denote the different HCLK

networks when two are being driven at the same time by

a single PLL (Note that HCLK1 is the primary clock

resource associated with the PLL, and HCLK2 is the clock

resource associated with the adjacent PLL). Likewise,

CLK1 and CLK2 are used to denote the different CLK

networks when two are being driven at the same time by

a single PLL (Figure 2-48 on page 2-63).

Routed net

Unused

Both CLK1 and CLK2

Both CLK1 and routed net

Both CLK2 and routed net

CLK1, CLK2, and routed net

Routed net

Unused

Unusable

CLK1

Unused

Unusable

Note: Designer software currently does not support all of these

connections. Only exclusive connections where one

output connects to a single net are supported at this time

(e.g., CLK1 driving both CLK1 and CLK2 is not supported).

2-66

v2.7

Axcelerator Family FPGAs

Special PLL Macros

Table 2-83 shows the macros used to connect the RefCLK input and CLK1 and CLK2 outputs using the different routing

resources.

Table 2-83 • PLL Special Macros

Macro Name

PLLINT

Usage

Connects RefCLK to a regular routed net or a pad.

PLLRCLK

PLLHCLK

PLLOUT

Connects CLK1 or CLK2 to the CLK network.

Connects CLK1 or CLK2 to the HCLK network.

Connects CLK1 or CLK2 to a regular routed net.

Table 2-84 • Electrical Specifications

Parameter

Value

Notes

Frequency Ranges

Reference Frequency (min.)

Reference Frequency (max.)

OSC Frequency (min.)

14 MHz

200 MHz

20 MHz

1 GHz

Lowest input frequency

Highest input frequency

Lowest output frequency

Highest output frequency

OSC Frequency (max.)

Jitter

Long-Term Jitter (max.)

Percentage of period, low reference clock frequencies

High reference clock frequencies

Long-Term Jitter (max.)

100ps

Short-Term Jitter (max.)

Acquisition Time (lock) from Cold Start

Acquisition Time (max.)*

Power Consumption

Analog Supply Current (low freq.)

Analog Supply Current (high freq.)

Digital Supply Current (low freq.)

Digital Supply Current (high freq.)

Duty Cycle

50ps+1%

Percentage of output frequency

400 cycles

Period of low reference clock frequencies

High reference clock frequencies

1.5 μs

200μA

0.5μA/MHz

1μA/MHz

Current at minimum oscillator frequency

Frequency-dependent current

Current at maximum oscillator frequency, unloaded

Frequency-dependent current

Minimum Output Duty Cycle

Maximum Output Duty Cycle

45%

55%

Note: *The lock bit remains Low until RefCLK reaches the minimum input frequency.

v2.7

2-67

Axcelerator Family FPGAs

User Flow

There are two methods of including a PLL in a design:

•

The alternative method is to instantiate one of the

generic library primitives (PLL or PLLFB) into either

a schematic or HDL netlist, using inverters for

polarity control and tying all unused address and

data bits to ground.

•

The recommended method of using a PLL is to

create custom PLL blocks using Actel's macro

generator, SmartGen, that can be instantiated in a

design.

Timing Model

Lock

CLK1

t_PCLK*

CLK

CLK2

Note: t_PCLKis the delay in the clock signal

Figure 2-52 • PLL Model

2-68

v2.7

Axcelerator Family FPGAs

Sample Implementations

Frequency Synthesis

Figure 2-53 illustrates an example where the PLL is used

to multiply a 155.5 MHz external clock up to 622 MHz.

Note that the same PLL schematic could use an external

350 MHz clock, which is divided down to 155 MHz by the

FPGA internal logic.

Figure 2-54 illustrates the PLL using both dividers to

synthesize a 133 MHz output clock from a 155 MHz input

reference clock. The input frequency of 155 MHz is

multiplied by 6 and divided by 7, giving a CLK1 output

frequency of 132.86 MHz. When dividers are used, a

given ratio can be generated in multiple ways, allowing

the user to stay within the operating frequency ranges of

the PLL.

DividerJ

PowerDown

RefCLK

Lock

/i Delay

Delay Line

Match

155.5 MHz

CLK1

PLL

Delay Line

CLK2

/j Delay

Match

622 MHz

FBMuxSel

DelayLine

DividerI

LowFreq

Osc

÷4

Figure 2-53 • Using the PLL 155.5 MHz In, 622 MHz Out

DividerJ

PowerDown

RefCLK

Lock

Delay Line

/i Delay

Match

155 MHz

132.8 MHz

CLK1

155 MHz

930 MHz

PLL

155 MHz

CLK2

/j Delay

Match

Yes

FBMuxSel

DelayLine

LowFreq

Osc

DividerI

÷6

Figure 2-54 • Using the PLL 155 MHz In, 133 MHz Out

v2.7

2-69

Axcelerator Family FPGAs

Adjustable Clock Delay

Figure 2-55 illustrates using the PLL to delay the reference clock by employing one of the adjustable delay lines. In this

case, the output clock is delayed relative to the reference clock. Delaying the reference clock relative to the output

clock is accomplished by using the delay line in the feedback path.

DividerJ

PowerDown

Lock

RefCLK

/i Delay

Match

Delay Line

133 MHz

CLK1

PLL

CLK2

/j Delay

Match

133 MHz

FBMuxSel

DelayLine

DividerI

LowFreq

Osc

÷1

Figure 2-55 • Using the PLL Delaying the Reference Clock

2-70

v2.7

Axcelerator Family FPGAs

Clock Skew Minimization

Figure 2-56 indicates how feedback from the clock network can be used to create minimal skew between the distributed

clock network and the input clock. The input clock is fed to the reference clock input of the PLL. The output clock (CLK2)

feeds a routed clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then

adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two

clocks. Refer to Actel’s Axcelerator Family PLL and Clock Management application note for more information.

DividerJ

PowerDown

Lock

RefCLK

Input Clock

/i Delay

Match

Delay Line

133 MHz

CLK1

CLK2

133 MHz

PLL

/i Delay

Match

133 MHz

LowFreq

FBMuxSel DelayLine

DividerI

÷1

Osc

SET

CLR

Clock Network

Figure 2-56 • Using the PLL for Clock Deskewing

v2.7

2-71

Axcelerator Family FPGAs

Embedded Memory

The AX architecture provides extensive, high-speed

memory resources to the user. Each 4,608 bit block of

RAM contains its own embedded FIFO controller,

allowing the user to configure each block as either RAM

or FIFO.

RD [(N-1):0]

RA [K:0]

REN

To meet the needs of high performance designs, the

memory blocks operate in synchronous mode for both

read and write operations. However, the read and write

clocks are completely independent, and each may

operate up to and above 500 MHz.

RCLK

WD [(M-1):0]

WA [J:0]

WEN

No additional core logic resources are required to

cascade the address and data buses when cascading

different RAM blocks. Dedicated routing runs along each

column of RAM to facilitate cascading.

WCLK

PIPE

RW [2:0]

WW [2:0]

The AX memory block includes dedicated FIFO control

logic to generate internal addresses and external flag

logic (FULL, EMPTY, AFULL, AEMPTY). Since read and

write operations can occur asynchronously to one

another, special control circuitry is included to prevent

metastability, overflow, and underflow. A block diagram

of the memory module is illustrated in Figure 2-57.

Figure 2-57 • Axcelerator Memory Module

RAM

During RAM operation, read (RA) and write (WA)

addresses are sourced by user logic and the FIFO

controller is ignored. In FIFO mode, the internal

addresses are generated by the FIFO controller and

routed to the RAM array by internal MUXes. Enables

with programmable polarity are provided to create

upper address bits for cascading up to 16 memory blocks.

When cascading memory blocks, the bussed signals WA,

WD, WEN, RA, RD, and REN are internally linked to

eliminate external routing congestion.

Each memory block consists of 4,608 bits that can be

organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1

and are cascadable to create larger memory sizes. This

allows built-in bus width conversion (Table 2-85). Each

block has independent read and write ports which

enable simultaneous read and write operations.

Table 2-85 • Memory Block WxD Options

Data-word (in bits)

Depth

4,096

2,048

1,024

512

Address Bus

RA/WA[11:0]

RA/WA[10:0]

RA/WA[9:0]

RA/WA[8:0]

RA/WA[7:0]

RA/WA[6:0]

Data Bus

RD/WD[0]

RD/WD[1:0]

RD/WD[3:0]

RD/WD[8:0]

RD/WD[17:0]

RD/WD[35:0]

256

128

2-72

v2.7

Axcelerator Family FPGAs

The D x W different configurations are: 128 x 36,

256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. The allowable

RW and WW values are shown in Table 2-87.

Clocks

The RCLK and the WCLK have independent source

polarity selection and can be sourced by any global or

local signal.

When widths of one, two, and four are selected, the

ninth bit is unused. For example, when writing nine-bit

values and reading four-bit values, only the first four bits

and the second four bits of each nine-bit value are

addressable for read operations. The ninth bit is not

accessible. Conversely, when writing four-bit values and

reading nine-bit values, the ninth bit of a read operation

will be undefined.

RAM Configurations

The AX architecture allows the read side and write side

of RAMs to be organized independently, allowing for

bus conversion. For example, the write side can be set to

256x18 and the read side to 512x9.

Note that the RAM blocks employ little-endian byte

order for read and write operations.

Both the write width and read width for the RAM blocks

can be specified independently and changed dynamically

with the WW (write width) and RW (read width) pins.

Table 2-86 • RAM Signal Description

Signal

WCLK

Direction

Input

Description

Write clock (can be active on either edge).

WA[J:0]

Input

Write address bus.The value J is dependent on the RAM configuration and the number of cascaded

memory blocks. The valid range for J is from 6 to15.

WD[M-1:0]

Input

Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or

36.

RCLK

Input

Read clock (can be active on either edge).

RA[K:0]

Read address bus. The value K is dependent on the RAM configuration and the number of cascaded

memory blocks. The valid range for K is from 6 to 15.

RD[N-1:0]

REN

Output

Input

Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36.

Read enable. When this signal is valid on the active edge of the clock, data at location RA will be

driven onto RD.

WEN

Input

Write enable. When this signal is valid on the active edge of the clock, WD data will be written at

location WA.

RW[2:0]

WW[2:0]

Pipe

Input

Width of the read operation dataword.

Width of the write operation dataword.

Sets the pipe option to be on or off.

Table 2-87 • Allowable RW and WW Values

RW(2:0)

000

WW(2:0)

000

D x W

4k x 1

001

2k x 2

010

1k x 4

011

512 x 9

256 x 18

128 x 36

reserved

100

101

11x

v2.7

2-73

Axcelerator Family FPGAs

Modes of Operation

There are two read modes and one write mode:

higher frequency. The read-address is registered on the

read-port active-clock edge, and the read data is

registered and appears at RD after the second read clock

edge. Setting the PIPE to ON enables this mode.

•

Read Nonpipelined (synchronous – one clock edge)

Read Pipelined (synchronous – two clock edges)

Write (synchronous – one clock edge)

On the write active-clock edge, the write data are

written into the SRAM at the write address when WEN is

high. The setup time of the write address, write enables,

and write data are minimal with respect to the write

clock.

In the standard read mode, new data is driven onto the

RD bus in the clock cycle immediately following RA and

REN valid. The read address is registered on the read-

port active-clock edge and data appears at read-data

after the RAM access time. Setting the PIPE to OFF

enables this mode.

Write and read transfers are described with timing

requirements beginning in "Timing Characteristics".

The pipelined mode incurs an additional clock delay

from address to data, but enables operation at a much

Timing Characteristics

WCLK

WEN

RCLK

REN

Figure 2-58 • SRAM Model

t_WCKH

t_WCKP

t_WCKL

WCLK

t_WxxSU

t_WxxHD

WA<11:0>, WD<35:0>, WEN<4:0>

Figure 2-59 • RAM Write Timing Waveforms

2-74

v2.7

Axcelerator Family FPGAs

t_RCKH

t_RCKL

t_RCKP

RCLK

t_RxxSU

t_RxxHD

RA<11:0>, REN<4:0>

t_RCK2RD1

t_RCK2RD2

RD <35:0>

Figure 2-60 • RAM Read Timing Waveforms

Table 2-88 • One RAM Block

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max.

'Std' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

1.08

0.22

1.08

0.22

1.08

0.22

1.23

0.25

1.23

0.25

1.23

0.25

1.45

0.30

1.45

0.30

1.45

0.30

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

t_WENHD

t_WCKH

0.98

1.15

2.29

1.11

1.30

2.61

1.31

1.53

3.07

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

0.81

0.00

0.81

0.00

1.39

2.62

0.92

0.00

0.92

0.00

1.59

2.98

1.08

0.00

1.08

0.00

1.86

3.5

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

1.00

1.21

2.42

1.14

1.38

2.76

1.34

1.62

3.24

t_RCLKL

t_RCKP

v2.7

2-75

Axcelerator Family FPGAs

Table 2-89 • Two RAM Blocks Cascaded

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max. Min. Max.

'Std' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min.

Max.

Units

Write Data Setup vs. WCLK

1.39

0.22

1.39

0.22

1.39

0.22

1.59

0.25

1.59

0.25

1.59

0.25

1.86

0.3

Write Data Hold vs. WCLK

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

1.86

0.3

1.86

0.3

t_WENHD

t_WCKH

0.98

2.29

4.58

1.11

2.61

5.22

1.31

3.07

6.13

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

1.7

0.00

1.7

1.94

0.00

1.94

0.00

1.72

3.14

2.28

0.00

2.28

0.00

2.02

3.69

t_RADHD

t_RENSU

t_RENHD

0.00

1.51

2.76

t_RCK2RD1

t_RCK2RD2

t_RCLKH

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.95

2.46

4.92

1.08

2.8

1.27

3.29

6.59

t_RCLKL

t_RCKP

5.6

2-76

v2.7

Axcelerator Family FPGAs

'–1' Speed 'Std' Speed

Table 2-90 • Four RAM Blocks Cascaded

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min. Max. Min. Max. Min. Max. Units

Write Data Setup vs. WCLK

2.37

0.22

2.37

0.22

2.37

0.22

2.7

0.25

2.7

3.17

0.3

Write Data Hold vs. WCLK

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

3.17

0.3

0.25

2.7

3.17

0.3

t_WENHD

t_WCKH

0.25

0.98

3.27

6.53

1.11

3.72

7.44

1.31

4.37

8.75

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

3.08

0.00

3.08

0.00

2.49

3.36

3.51

0.00

3.51

0.00

2.83

3.82

4.13

0.00

4.13

0.00

3.33

4.5

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.95

3.85

7.7

1.08

4.39

8.78

1.27

5.16

t_RCLKL

t_RCKP

10.32

v2.7

2-77

Axcelerator Family FPGAs

Table 2-91 • Eight RAM Blocks Cascaded

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max. Min. Max.

'Std' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min.

Max.

Units

Write Data Setup vs. WCLK

5.78

0.22

5.78

0.22

5.78

0.22

6.58

0.25

6.58

0.25

6.58

0.25

7.74

0.3

Write Data Hold vs. WCLK

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

7.74

0.3

7.74

0.3

t_WENHD

t_WCKH

0.98

6.68

1.11

7.6

1.31

8.94

t_WCLK

t_WCKP

13.35

15.21

17.88

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

6.75

0.00

6.75

0.00

3.57

5.48

7.69

0.00

7.69

0.00

4.06

6.24

9.04

0.00

9.04

0.00

4.77

7.34

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.95

7.51

1.08

8.55

1.27

10.05

20.11

t_RCLKL

t_RCKP

15.02

17.11

2-78

v2.7

Axcelerator Family FPGAs

'–1' Speed 'Std' Speed

Table 2-92 • Sixteen RAM Blocks Cascaded

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min. Max. Min. Max. Min. Max. Units

Write Data Setup vs. WCLK

16.54

0.22

18.84

0.25

22.15

0.3

Write Data Hold vs. WCLK

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

16.54

0.22

18.84

0.25

22.15

0.3

16.54

0.22

18.84

0.25

22.15

0.3

t_WENHD

t_WCKH

0.98

17.44

34.87

1.11

19.86

39.73

1.31

23.35

46.7

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

18.13

0.00

20.65

0.00

24.27

0.00

t_RADHD

t_RENSU

18.13

0.00

20.65

0.00

24.27

0.00

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

12.71

13.91

14.48

15.85

17.03

18.63

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.95

18.75

37.5

1.08

21.36

42.72

1.27

25.11

50.22

t_RCLKL

t_RCKP

v2.7

2-79

Axcelerator Family FPGAs

FIFO

Every memory block has its own embedded FIFO

controller. Each FIFO block has one read port and one

write port. This embedded FIFO controller uses no

internal FPGA logic and features:

The FIFO block offers programmable almost-empty

(AEMPTY) and almost-full (AFULL) flags as well as EMPTY

and FULL flags (Figure 2-61):

•

The FULL flag is synchronous to WCLK. It allows

the FIFO to inhibit writing when full.

•

Glitch-free FIFO Flags

Gray-code address counters/pointers to prevent

metastability problems

•

The EMPTY flag is synchronous to RCLK. It allows

the FIFO to inhibit reading at the empty condition.

•

Overflow and underflow control

Gray code counters are used to prevent metastability

problems associated with flag logic. The depth of the

FIFO is dependent on the data width and the number of

memory blocks used to create the FIFO. The write

operations to the FIFO are synchronous with respect to

the WCLK, and the read operations are synchronous with

respect to the RCLK.

Both ports are configurable in various sizes from 4k x 1

to 128 x 36, similar to the RAM block size. Each port is

fully synchronous.

Read and write operations can be completely

independent. Data on the appropriate WD pins are

written to the FIFO on every active WCLK edge as long as

WEN is high. Data is read from the FIFO and output on

the appropriate RD pins on every active RCLK edge as

long as REN is asserted.

The FIFO block may be reset to the empty state.

RD [n-1:0]

WD [n-1:0]

RCLK

WCLK

RAM

RA [J:0]

WA [J:0]

REN

WEN

DEPTH[3:0]

CNT 16

FREN

FULL

AFULL

AFVAL

AEVAL

AEMPTY

EMPTY

CNT 16

FWEN

CLR

Figure 2-61 • Axcelerator RAM with Embedded FIFO Controller

2-80

v2.7

Axcelerator Family FPGAs

FIFO Flag Logic

The FIFO is user configurable into various DEPTHs and

WIDTHs. Figure 2-62 shows the FIFO address counter

details.

RAM block, whereas bits 13 and 12 will be used to specify

the RAM block.

The AFULL and AEMPTY flag threshold values are

programmable. The threshold values are AFVAL and

AEVAL, respectively. Although the trigger threshold for

each flag is defined with eight bits, the effective number

of threshold bits in the comparison depends on the

configuration. The effective number of threshold bits

corresponds to the range of active bits in the FIFO

address space (Table 2-93).

•

Bits 11 to 5 are active for all modes.

As the data word size is reduced, more least-

significant bits are added to the address.

•

As the number of cascaded blocks increases, the

number of significant bits in the address increases.

For example, if four blocks are cascaded as a 1kx16 FIFO

with each block having a 1kx4 aspect ratio, bits 11 to 2 of

the address will be used to specify locations within each

FIFO Address Counters

Mode when

Active

Counter

Bits

FIFO Address

Alignment of

Threshold bits

R/W EN[3]

R/W EN[2]

Cas 16 blks

Cas 8 blks

CNTR [15]

activate

AEVAL/AFVAL[7]

AEVAL/AFVAL[6]

CNTR [14]

activate

[15:W]

Cas 4 blks

Cas 2 blks

CNTR [13]

activate

R/W EN[1]

R/W EN[0]

AEVAL/AFVAL[5]

AEVAL/AFVAL[4]

[14:W]

[13:W]

[12:W]

CNTR [12]

activate

4kx1

AEVAL/AFVAL[3:0] ^{128x36 256x18}

512x9

1kx4

2kx2

R/W ADD[11:8]

R/W ADD[7:5]

by 36

CNTR [11:5]

always active

not compared

[11:5]

[11:4]

[11:3]

by 18

by 9

CNTR [4]

activate

R/W ADD[4]

not compared

[11:2]

CNTR [3]

activate

[11:1]

R/W ADD[3]

R/W ADD[2]

[11:0]

by 4

by 2

by 1

CNTR [2]

activate

CNTR [1]

activate

R/W ADD[1]

R/W ADD[0]

CNTR [0]

activate

Variable Active Address Space

CNTR [15:0]

>> REN [4:0], RAD [11:0]

>> WEN [4:0], WAD [11:0]

Note: Inactive counter bits are set to zero.

Figure 2-62 • FIFO Address Counters

Table 2-93 • FIFO Flag Logic

Mode

Inactive AEVAL/AFVAL bits

Inactive DIFF bits (set to 0) DIFF comparison to AFVAL/AEVAL

Non-cascade

[7:4]

[7:5]

[7:6]

[7]

[15:12]

[15:13]

[15:14]

[15]

DIFF[11:8] withAE/FVAL[3:0]

DIFF[12:8] withAE/FVAL[4:0]

DIFF[13:8] withAE/FVAL[5:0]

DIFF[14:8] withAE/FVAL[6:0]

DIFF[15:8] withAE/FVAL[7:0]

Cascade 2 blocks

Cascade 4 blocks

Cascade 8 blocks

Cascade 16 blocks

None

v2.7

2-81

Axcelerator Family FPGAs

Figure 2-63 illustrates flag generation. The Verilog codes for the flags are:

assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0;

assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0;

The number of DIFF-bits active depends on the configuration depth and width (Table 2-94).

ALMOST EMPTY and ALMOST FULL Logic

AEMPTY

AEVAL [7:0], GND [7:0] (MSB....LSB)

WCNTR

[15:0]

WCLK

RCLK

X>=Y

(16 bit)

DIFF [15:0]

RCNTR

[15:0]

AFULL

AFVAL [7:0], GND [7:0] (MSB....LSB)

Figure 2-63 • ALMOST-EMPTY and ALMOST-FULL Logic

Table 2-94 • Number of Available Configuration Bits

Number of Blocks

Block DxW

Number of AEVAL/AFVAL Bits

1x1

1x2

2x1

1x4

2x2

4x1

1x8

2x4

4x2

8x1

1x16

2x8

4x4

8x2

16x1

2-82

v2.7

Axcelerator Family FPGAs

The active-high CLR pin is used to reset the FIFO to the

empty state, which sets FULL and AFULL low, and EMPTY

and AEMPTY high.

Overflow and Underflow Control

The counter MSB keeps track of the difference between

the read address (RA) and the write address (WA). The

EMPTY flag is set when the read and write addresses are

equal. To prevent underflow, the write address is double-

sampled by the read clock prior to comparison with the

read address (part A in Figure 2-64). To prevent overflow,

the read address is double-sampled by the write clock

prior to comparison to the write address (part B in

Figure 2-64).

Assuming that the EMPTY flag is not set, new data is

read from the FIFO when REN is valid on the active edge

of the clock. Write and read transfers are described with

timing requirements in "Timing Characteristics" on

page 2-85.

Glitch Elimination

An analog filter is added to each FIFO controller to

guarantee glitch-free FIFO-flag logic.

FULL

EMPTY

RCLK

WCLK

Figure 2-64 • Overflow and Underflow Control

FIFO Configurations

Clock

Unlike the RAM, the FIFO's write width and read width

cannot be specified independently. For the FIFO, the

write and read widths must be the same. The WIDTH pins

are used to specify one of six allowable word widths, as

shown in Table 2-95.

As with RAM configuration, the RCLK and WCLK pins

have independent polarity selection

Table 2-95 • FIFO Width Configurations

WIDTH(2:0)

000

W x D

1 x 4k

The DEPTH pins allow RAM cells to be cascaded to create

larger FIFOs. The four pins allow depths of 2, 4, 8, and 16

to be specified. Table 2-85 on page 2-72 describes the

FIFO depth options for various data width and memory

blocks.

001

2 x 2k

010

4 x 1k

011

9 x 512

18 x 256

36 x 128

reserved

100

101

Interface

11x

Figure 2-65 shows

a logic block diagram of the

Axcelerator FIFO module.

RD [35:0]

FULL

DEPTH [3:0]

WIDTH [2:0]

Cascading FIFO Blocks

PIPE

FREN

FIFO blocks can be cascaded to create deeper FIFO

functions. When building larger FIFO blocks, if the word

width can be fractured in a multi-bit FIFO, the fractured

word configuration is recommended over a cascaded

configuration. For example, 256x36 can be configured as

two blocks of 256x18. This should be taken into account

when building the FIFO blocks manually. However, when

using SmartGen, the user only needs to specify the depth

and width of the necessary FIFO blocks. SmartGen

automatically configures these blocks to optimize

performance.

EMPTY

AFULL

RCLK

AEVAL [7:0]

AEMPTY

AFVAL [7:0]

WD [35:0]

FWEN

WCLK

CLR

Figure 2-65 • FIFO Block Diagram

v2.7

2-83

Axcelerator Family FPGAs

Table 2-96 • FIFO Signal Description

Signal

WCLK

FWEN

Direction

Description

Input

Write clock (active either edge).

FIFO write enable. When this signal is asserted, the WD bus data is latched into the

FIFO, and the internal write counters are incremented.

WD[N-1:0]

FULL

Input

Write data bus. The value N is dependent on the RAM configuration and can be 1,

2, 4, 9, 18, or 36.

Output

Active high signal indicating that the FIFO is FULL. When this signal is set,

additional write requests are ignored.

AFULL

AFVAL

RCLK

Output

Input

Active high signal indicating that the FIFO is AFULL.

8-bit input defining the AFULL value of the FIFO.

Read clock (active either edge).

Input

FREN

Input

FIFO read enable.

RD[N-1:0]

Output

Read data bus. The value N is dependent on the RAM configuration and can be 1,

2, 4, 9, 18, or 36.

EMPTY

Output

Empty flag indicating that the FIFO is EMPTY. When this signal is asserted,

attempts to read the FIFO will be ignored.

AEMPTY

AEVAL

PIPE

Output

Input

Active high signal indicating that the FIFO is AEMPTY.

8-bit input defining the almost-empty value of the FIFO.

Sets the pipe option on or off.

CLR

Active high clear input.

DEPTH

WIDTH

Determines the depth of the FIFO and the number of FIFOs to be cascaded.

Determines the width of the dataword / width of the FIFO, and the number of the

FIFOs to be cascaded.

2-84

v2.7

Axcelerator Family FPGAs

Timing Characteristics

AEMPTY

EMPTY

AFULL

FULL

FWEN

FREN

WCLK

RCLK

Clr

Figure 2-66 • FIFO Model

t_WCKH

t_WCKP

t_WCKL

WCLK

t_WSU

t_WHD

WD<35:0>, FWEN

t_CLR2HF

CLR

t_CK2xF

t_CLR2xF

EMPTY, AEMPTY, AFULL, FULL

Figure 2-67 • FIFO Write Timing

v2.7

2-85

Axcelerator Family FPGAs

t_RCKH

t_RCKL

t_RCKP

RCLK

FREN

t_RSUt_RHD

t_RCK2RD1

t_RCK2RD2

RD <35:0>

t_CLRHF

CLR

t_CLR2xF

t_CK2xF

EMPTY, AEMPTY, AFULL, FULL

Figure 2-68 • FIFO Read Timing

Table 2-97 • One FIFO Block

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max. Min. Max.

'Std' Speed

Parameter

Description

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

1.08

0.22

0.98

1.15

1.23

0.25

1.11

1.30

1.45

0.30

1.31

1.53

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

Minimum WCLK Period

Read Setup

2.3

2.6

3.06

3.24

0.81

0.00

1.00

1.21

0.92

0.00

1.14

1.38

1.08

0.00

1.34

1.62

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

2.42

2.76

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.08

2.02

4.62

2.24

5.31

1.39

2.62

1.23

2.3

1.45

2.7

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Non-Pipelined)

5.26

2.55

6.05

1.59

2.98

6.19

7.11

1.86

3.5

2-86

v2.7

Axcelerator Family FPGAs

'Std' Speed

Table 2-98 • Two FIFO Blocks Cascaded

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

FIFO Module Timing

t_WSU

Write Setup

1.39

0.22

0.98

2.29

1.59

0.25

1.11

2.61

1.86

0.3

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

1.31

3.07

Minimum WCLK Period

Read Setup

4.58

4.92

5.22

5.6

6.14

6.58

1.7

1.94

2.28

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

0.95

2.46

1.08

2.8

1.27

3.29

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.08

2.02

4.62

2.24

5.31

1.51

2.76

1.23

2.3

1.45

2.7

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Nonpipelined)

5.26

2.55

6.05

1.72

3.14

6.19

7.11

2.02

3.69

Table 2-99 • Four FIFO Blocks Cascaded

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max.

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

2.37

0.22

0.98

3.27

2.7

3.17

0.3

t_WHD

Write Hold

WCLK High

WCLK Low

0.25

1.11

3.72

t_WCKH

t_WCKL

t_WCKP

t_RSU

1.31

4.37

Minimum WCLK Period

Read Setup

6.54

7.7

7.44

8.78

8.74

3.08

3.51

4.13

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

0.95

3.85

1.08

4.39

1.27

5.16

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

10.32

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.08

2.02

4.62

2.24

5.31

2.49

3.36

1.23

2.3

1.45

2.7

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Nonpipelined)

5.26

2.55

6.05

2.83

3.82

6.19

7.11

3.33

4.5

v2.7

2-87

Axcelerator Family FPGAs

Table 2-100 • Eight FIFO Blocks Cascaded

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

Min. Max. Min. Max.

'Std' Speed

Parameter

Description

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

5.78

0.22

0.98

6.68

6.58

0.25

1.11

7.6

7.74

0.3

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

1.31

8.94

Minimum WCLK Period

Read Setup

13.36

15.02

15.2

17.1

17.88

20.1

6.75

7.69

9.04

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

0.95

7.51

1.08

8.55

1.27

10.05

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.08

2.02

4.62

2.24

5.31

3.57

5.48

1.23

2.3

1.45

2.7

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Nonpipelined)

5.26

2.55

6.05

4.06

6.24

6.19

7.11

4.77

7.34

Table 2-101 • Sixteen FIFO Blocks Cascaded

Worst-Case Commercial Conditions V_CCA= 1.425V, V_CCI= 3.0V, T_J= 70°C

'–2' Speed '–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

16.54

0.22

18.84

0.25

22.15

0.3

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

0.98

1.11

1.31

23.35

17.44

19.86

Minimum WCLK Period

Read Setup

34.88

37.5

39.72

42.72

46.7

18.13

20.65

24.27

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

0.95

18.75

1.08

21.36

1.27

25.11

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

50.22

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.08

2.02

1.23

2.3

1.45

2.7

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Nonpipelined)

4.62

5.26

2.55

6.05

14.48

15.85

6.19

2.24

5.31

7.11

17.03

18.63

12.71

13.91

2-88

v2.7

Axcelerator Family FPGAs

Building RAM and FIFO Modules

JTAG

RAM and FIFO modules can be generated and included

in a design in two different ways:

Axcelerator offers a JTAG interface that is compliant with

the IEEE 1149.1 standard. The user can employ the JTAG

interface for probing a design and performing any JTAG

Public Instructions as defined in the Table 2-102.

•

Using the SmartGen Core Generator where the

user defines the depth and width of the FIFO/

RAM, and then instantiates this block into the

design (please refer to Actel’s SmartGen,

FlashROM, Analog System Builder, and Flash

Memory System Builder User’s Guide for more

information).

Interface

The interface consists of four inputs: Test Mode Select

(TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller

Reset (TRST), and an output, Test Data Out (TDO). TMS,

TDI, and TRST have on-chip pull-up resistors.

•

The alternative is to instantiate the RAM/FIFO

blocks manually, using inverters for polarity

control and tying all unused data bits to ground.

Table 2-102 • JTAG Instruction Code

Instruction (IR4:IR0)

Extest

Binary Code

00000

Other Architectural Features

Preload / Sample

Intest

00001

00010

USERCODE

IDCODE

00011

Low Power Mode

00100

Although designed for high performance, the AX

architecture also allows the user to place the device into

a low power mode. Each I/O bank in an Axcelerator

device can be configured individually, when in low

power mode, to tristate all outputs, disable inputs, or

both. The low power mode is activated by asserting the

LP pin, which is grounded in normal operation.

HIGHZ

01110

CLAMP

01111

Diagnostic

Reserved

10000

All others

11111

Bypass

While in the low power mode, the device is still fully

functional and all internal logic states are preserved. This

allows a user to disable all but a few signals and operate

the part in a low-frequency, watchdog mode if desired.

Please note, if the I/O bank is not disabled, differential I/Os

belonging to the I/O bank will still consume normal

power, even when operating in the low power mode.

TRST

TRST (Test-Logic Reset) is an active-low, asynchronous

reset signal to the TAP controller. The TRST input can be

used to reset the Test Access Port (TAP) Controller to the

TRST state. The TAP Controller can be held at this state

permanently by grounding the TRST pin. To hold the

JTAG TAP controller in the TRST state, it is recommended

to connect TRST to ground via a 1 kΩ resistor.

The Axcelerator device will resume normal operation

10μs after the LP pin is pulled Low.

There is an optional internal pull-up resistor available for

the TRST input that can be set by the user at

programming. Care should be exercised when using this

option in combination with an external tie-off to

ground.

To further reduce power consumption, the internal

charge pump can be bypassed and an external power

supply voltage can be used instead. This saves the

internal charge-pump operating current, resulting in no

DC current draw. The Axcelerator family devices have a

dedicated "V_PUMP" pin that can be used to access an

external charge pump device. In normal chip operation,

when using the internal charge pump, V_PUMPshould be

tied to GND. When the voltage level on V_PUMPis set to

3.3V, the internal charge pump is turned off, and the

V_PUMPvoltage will be used as the charge pump voltage.

Adequate voltage regulation (i.e. high drive, low output

impedance, and good decoupling) should be used at

An on-chip power-on-reset (POWRST) circuit is included.

POWRST has the same function as "TRST," but it only

occurs at power-up or during recovery from a V_CCAand/

or V_CCDAvoltage drop.

TDO

TDO is normally tristated, and it is active only when the

TAP controller is in the "Shift_DR" state or "Shift_IR"

state. The least significant bit of the selected register (i.e.

IR or DR) is clocked out to TDO first by the falling edge of

TCK.

V_PUMP

In addition, any PLL in use can be powered down to

further reduce power consumption. This can be done

with the PowerDown pin driven Low. Driving this pin

High restarts the PLL with the output clock(s) being

stable once lock is restored.

TAP Controller

The TAP Controller is compliant with the IEEE Standard

1149.1. It is a state machine of 16 states that controls the

v2.7

2-89

Axcelerator Family FPGAs

Instruction Register (IR) and the Data Registers (such as

BSR, IDCODE, USRCODE, BYPASS, etc.). The TAP

Controller steps into one of the states depending on the

sequence of TMS at the rising edges of TCK.

Probing

Internal activities of the JTAG interface can be observed

via the Silicon Explorer II probes: "PRA," "PRB," "PRC,"

and "PRD."

Instruction Register (IR)

Special Fuses

Security

The IR has five bits (IR4 to IR0). At the TRST state, IR is

reset to IDCODE. Each time when IR is selected, it goes

through "select IR-Scan," "Capture-IR," "Shift-IR," all the

way through "Update-IR." When there is no test error,

the first five data bits coming out of TDO during the

"Shift-IR" will be "10111." If a test error occurs, the last

three bits will contain one to three zeroes corresponding

to negatively asserted signals: "TDO_ERRORB,"

"PROBA_ERRORB," and "PROBB_ERRORB." The error(s)

will be erased when the TAP is at the "Update-IR" or the

TRST state. When in user mode start-up sequence, if the

micro-probe has not been used, the "PROBA_ERRORB" is

used as a "Power-up done successfully" flag.

Actel antifuse FPGAs, with FuseLock technology, offer

the highest level of design security available in a

programmable logic device. Since antifuse FPGAs are

live-at power-up, there is no bitstream that can be

intercepted, and no bitstream or programming data is

ever downloaded to the device during power-up, thus

making device cloning impossible. In addition, special

security fuses are hidden throughout the fabric of the

device and may be programmed by the user to thwart

attempts to reverse engineer the device by attempting

to exploit either the programming or probing interfaces.

Both invasive and noninvasive attacks against an

Axcelerator device that access or bypass these security

fuses will destroy access to the rest of the device. (refer

to the Design Security in Nonvolatile Flash and Antifuse

FPGAs white paper).

Data Registers (DRs)

Data registers are distributed throughout the chip. They

store testing/programming vectors. The MSB of a data

to TDO. There are different types of data registers.

Descriptions of the main registers are as follow:

Look for this symbol to ensure your valuable IP is secure.

1. IDCODE:

The IDCODE is a 33-bit hard coded JTAG Silicon

Signature. It is a hardwired device ID code, which

contains the Actel identity, part number, and version

number in a specific JTAG format.

2. USERCODE:

The USERCODE is a 32-bit programmable JTAG Silicon

Signature. It is a supplementary identity code for the

user to program information to distinguish different

programmed parts. USERCODE fuses will read out as

"zeroes" when not programmed, so only the "1" bits

need to be programmed.

Figure 2-69 • FuseLock Logo

To ensure maximum security in Axcelerator devices, it is

recommended that the user program the device security

fuse (SFUS). When programmed, the Silicon Explorer II

testing probes are disabled to prevent internal probing,

and the programming interface is also disabled. All JTAG

public instructions are still accessible by the user.

3. Boundary-Scan Register (BSR):

Each I/O contains three Boundary-Scan Cells. Each cell

has a shift register bit, a latch, and two MUXes. The

boundary-scan cells are used for the Output-enable

(E), Output (O), and Input (I) registers. The bit order

of the boundary-scan cells for each of them is E-O-I.

The boundary-scan cells are then chained serially to

form the Boundary-Scan Register (BSR). The length of

the BSR is the number of I/Os in the die multiplied by

three.

For more information, refer to Actel’s Implementation of

Security in Actel Antifuse FPGAs application note.

Global Set Fuse

The Global Set Fuse determines if all R-cells and I/O

registers (InReg, OutReg, and EnReg) are either cleared

or preset by driving the GCLR and GPSET inputs of all R-

cells and I/O Registers (Figure 2-31 on page 2-47). Default

setting is to clear all registers (GCLR = 0 and GPSET =1) at

device power-up. When the GBSETFUS option is checked

during FUSE file generation, all registers are preset

(GCLR = 1 and GPSET= 0). A local CLR or PRESET will take

precedence over this setting. Both pins are pulled High

during normal device operation. For use details, see the

Libero IDE online help.

4. Bypass Register (BYR):

This is the "1-bit" register. It is used to shorten the

TDI-TDO serial chain in board-level testing to only

one bit per device not being tested. It is also selected

for all "reserved" or unused instructions.

2-90

v2.7

Axcelerator Family FPGAs

Silicon Explorer II Probe Interface

Programming

Silicon Explorer II is an integrated hardware and

software solution that, in conjunction with the Designer

tools, allows users to examine any of the internal nets

(except I/O registers) of the device while it is operating in

a prototype or a production system. The user can probe

up to four nodes at a time without changing the

placement and routing of the design and without using

any additional device resources. Highlighted nets in

Designer’s ChipPlanner can be accessed using Silicon

Explorer II in order to observe their real time values.

Device programming is supported through the Silicon

Sculptor II, a single-site, robust and compact device

programmer for the PC. Up to four Silicon Sculptor IIs can

be daisy-chained and controlled from a single PC host.

With standalone software for the PC, Silicon Sculptor II is

designed to allow concurrent programming of multiple

units from the same PC when daisy-chained.

Silicon Sculptor II programs devices independently to

achieve the fastest programming times possible. Each

fuse is verified by Silicon Sculptor II to ensure correct

programming. Furthermore, at the end of programming,

there are integrity tests that are run to ensure that

programming was completed properly. Not only does it

test programmed and nonprogrammed fuses, Silicon

Sculptor II also provides a self-test to test its own

hardware extensively.

Silicon Explorer II's noninvasive method does not alter

timing or loading effects, thus shortening the debug

cycle. In addition, Silicon Explorer II does not require

relayout or additional MUXes to bring signals out to

external pins, which is necessary when using

programmable logic devices from other suppliers. By

eliminating multiple place-and-route program cycles, the

integrity of the design is maintained throughout the

debug process.

Programming an Axcelerator device using Silicon

Sculptor II is similar to programming any other antifuse

device. The procedure is as follows:

Each member of the Axcelerator family has four external

pads: PRA, PRB, PRC, and PRD. These can be used to bring

out four probe signals from the Axcelerator device (note

that the AX125 only has two probe signals that can be

observed: PRA and PRB). Each core tile has up to two

probe signals. To disallow probing, the SFUS security fuse

in the silicon signature has to be programmed (see

"Special Fuses" on page 2-90).

1. Load the .AFM file.

2. Select the device to be programmed.

3. Begin programming.

When the design is ready to go to production, Actel

offers device volume-programming services either

through distribution partners or via our In-House

Programming Center.

Silicon Explorer II connects to the host PC using a

standard serial port connector. Connections to the circuit

board are achieved using a nine-pin D-Sub connector

(Figure 1-9 on page 1-7). Once the design has been

placed-and-routed, and the Axcelerator device has been

programmed, Silicon Explorer II can be connected and

the Explorer software can be launched.

In addition, BP Microsystems offers multi-site

programmers that provide qualified support for

Axcelerator devices.

For more details on programming the Axcelerator

devices, please refer to the Silicon Sculptor II User’s

Guide.

Silicon Explorer II comes with an additional optional PC

hosted tool that emulates an 18-channel logic analyzer.

Four channels are used to monitor four internal nodes,

and 14 channels are available to probe external signals.

The software included with the tool provides the user

with an intuitive interface that allows for easy viewing

and editing of signal waveforms.

v2.7

2-91

Axcelerator Family FPGAs

Package Pin Assignments

180-Pin CSP

A1 Ball Pad Corner

14 13 12 11 10

Figure 3-1 • 180-Pin CSP (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v2.7

3-1

Axcelerator Family FPGAs

180-Pin CSP

AX125 Function

180-Pin CSP

AX125 Function

Bank 0

Pin Number

H11

AX125 Function

Pin Number

IO32NB3F3

IO32PB3F3

IO34NB3F3

IO34PB3F3

IO36NB3F3

IO36PB3F3

IO38NB3F3

IO38PB3F3

IO40NB3F3

IO40PB3F3

IO41NB3F3

IO41PB3F3

IO59NB5F5

IO59PB5F5

IO00NB0F0

IO00PB0F0

H12

K14

Bank 6

IO02NB0F0

J14

IO60NB6F6

IO60PB6F6

IO62NB6F6

IO62PB6F6

IO64NB6F6

IO64PB6F6

IO66NB6F6

IO66PB6F6

IO68NB6F6

IO68PB6F6

IO70NB6F6

IO70PB6F6

IO71NB6F6

IO71PB6F6

IO02PB0F0

K13

IO07NB0F0/HCLKAN

IO07PB0F0/HCLKAP

IO08NB0F0/HCLKBN

IO08PB0F0/HCLKBP

Bank 1

J13

L13

L14

M13

M14

K12

IO09NB1F1/HCLKCN

IO09PB1F1/HCLKCP

IO10NB1F1/HCLKDN

IO10PB1F1/HCLKDP

IO11NB1F1

J12

A10

B10

B11

A11

B12

A12

D12

D11

Bank 4

IO42NB4F4

IO42PB4F4

P13

N13

L12

M12

P12

N12

N11

P11

M11

M10

IO11PB1F1

IO43NB4F4

IO15NB1F1

IO43PB4F4

IO15PB1F1

IO46NB4F4

Bank 7

IO17NB1F1

IO46PB4F4

IO72NB7F7

IO72PB7F7

IO74NB7F7

IO74PB7F7

IO76NB7F7

IO76PB7F7

IO78NB7F7

IO78PB7F7

IO79NB7F7

IO79PB7F7

IO83NB7F7

IO83PB7F7

IO17PB1F1

IO47NB4F4

Bank 2

IO47PB4F4

IO18NB2F2

C13

C12

C14

B14

D13

D14

F12

E12

E13

E14

F13

F14

G12

G11

IO49NB4F4/CLKEN

IO49PB4F4/CLKEP

IO50NB4F4/CLKFN

IO50PB4F4/CLKFP

IO18PB2F2

IO19NB2F2

IO19PB2F2

IO20NB2F2

Bank 5

IO20PB2F2

IO51NB5F5/CLKGN

IO51PB5F5/CLKGP

IO52NB5F5/CLKHN

IO52PB5F5/CLKHP

IO53NB5F5

IO22NB2F2

IO22PB2F2

IO24NB2F2

IO24PB2F2

Dedicated I/O

IO26NB2F2

IO53PB5F5

V_CCDA

GND

IO26PB2F2

IO55NB5F5

IO28NB2F2

IO55PB5F5

A14

IO28PB2F2

IO56NB5F5

Bank 3

IO56PB5F5

IO30NB3F3

H13

G13

IO57NB5F5

E10

IO30PB3F3

IO57PB5F5

3-2

v2.7

Axcelerator Family FPGAs

180-Pin CSP

AX125 Function

180-Pin CSP

AX125 Function

Pin Number

GND

GND/LP

PRA

V_CCPLF

V_CCPLG

V_CCPLH

V_CCDA

F10

B13

G14

H14

J10

H10

L11

K10

V_CCIB0

V_CCIB1

D10

N14

V_CCIB1

V_CCIB2

E11

F11

J11

K11

L10

P14

V_CCIB3

V_CCIB4

PRB

V_CCIB5

PRC

PRD

V_CCIB6

TCK

V_CCIB6

TDI

_CCIB7

TDO

TMS

V_CCDA

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

TRST

V_CCA

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

G10

C11

P10

C10

N10

A13

v2.7

3-3

Axcelerator Family FPGAs

729-Pin PBGA

A1 Ball Pad Corner

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Figure 3-2 • 729-Pin PBGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-4

v2.7

Axcelerator Family FPGAs

729-Pin PBGA

AX1000 Function Pin Number

Bank 0

IO00NB0F0

729-Pin PBGA

AX1000 Function

Pin Number

AX1000 Function

Pin Number

C17

C16

B18

B17

A18

A17

H16

G16

B19

A19

C19

C18

D18

D17

H17

G17

F17

IO18PB0F1

IO19NB0F1

IO37NB1F3

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO39NB1F3

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F4

IO41PB1F4

IO42NB1F4

IO42PB1F4

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

IO47PB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO53NB1F4

IO53PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

E11

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO19PB0F1

F11

IO20NB0F1

G12

H12

D11

D10

A10

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO23NB0F2

B11

IO23PB0F2

B10

IO24NB0F2

G13

H13

C12

C11

E12

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO26NB0F2

IO26PB0F2

D12

E13

IO27NB0F2

E17

IO27PB0F2

F13

B20

A20

C21

C20

H18

G18

F18

IO28NB0F2

G14

H14

A12

B12

IO28PB0F2

G10

H10

IO29NB0F2

IO29PB0F2

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

C13

D13

F14

E10

F10

G11

H11

E18

E14

D20

D19

A22

A21

B22

B21

F19

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO34NB1F3

C14

B14

D16

D15

B16

A16

E15

F15

IO34PB1F3

E19

IO35NB1F3

F20

IO35PB1F3

E20

IO36NB1F3

H15

G15

E21

C10

IO36PB1F3

D21

v2.7

3-5

Axcelerator Family FPGAs

729-Pin PBGA

AX1000 Function

729-Pin PBGA

AX1000 Function

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

Bank 2

Pin Number

K21

G27

F27

AX1000 Function

Pin Number

H19

G19

D22

C22

B23

A23

D23

C23

G21

G20

E23

E22

F22

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO81NB2F7

IO81PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO84NB2F7

IO84PB2F7

IO85NB2F8

IO85PB2F8

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

P27

N19

N20

P23

P22

K23

K22

H26

H25

K25

K24

J26

Bank 3

IO96NB3F9

IO96PB3F9

P25

P24

R26

R27

P21

P20

R24

R25

T26

T27

T24

T25

R20

R21

R23

R22

U26

U27

U24

U25

R19

P19

V26

V27

T23

T22

V24

V25

T20

T21

W26

W27

IO97NB3F9

IO97PB3F9

J25

IO98NB3F9

M20

L20

IO98PB3F9

IO99NB3F9

F21

J27

IO99PB3F9

H20

J19

H27

L23

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

IO103NB3F9

IO103PB3F9

IO104NB3F9

IO104PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

IO107PB3F10

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO110NB3F10

IO110PB3F10

IO111NB3F10

IO111PB3F10

L22

IO64NB2F6

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

IO72NB2F6

IO72PB2F6

IO73NB2F6

IO73PB2F6

IO74NB2F7

J21

H21

F24

F23

F26

F25

E26

E25

J22

L25

L24

N21

M21

K27

K26

M23

M22

M25

M24

L27

H22

G24

G23

K20

J20

L26

M27

M26

N23

N22

N25

N24

N27

N26

P26

G26

G25

J24

J23

H24

H23

L21

3-6

v2.7

Axcelerator Family FPGAs

729-Pin PBGA

AX1000 Function

Pin Number

U22

Pin Number

AB23

AC22

AC23

AD23

AD24

AF23

AE23

AC21

AB21

AC20

AB20

AD21

AD22

Y19

AX1000 Function

Pin Number

AB17

AE18

AE19

AA16

Y16

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO119NB3F11

IO119PB3F11

IO120NB3F11

IO120PB3F11

IO121NB3F11

IO121PB3F11

IO122NB3F11

IO122PB3F11

IO123NB3F11

IO123PB3F11

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO126NB3F11

IO126PB3F11

IO127NB3F11

IO127PB3F11

IO128NB3F11

IO128PB3F11

IO130PB4F12

IO131NB4F12

IO131PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO134NB4F12

IO134PB4F12

IO135NB4F12

IO135PB4F12

IO136NB4F12

IO136PB4F12

IO137NB4F12

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

IO141PB4F13

IO142NB4F13

IO142PB4F13

IO143NB4F13

IO143PB4F13

IO144NB4F13

IO144PB4F13

IO145NB4F13

IO145PB4F13

IO146NB4F13

IO146PB4F13

IO147NB4F13

IO147PB4F13

IO148NB4F13

IO148PB4F13

IO149NB4F13

IO149PB4F13

IO150NB4F13

IO150PB4F13

U23

Y26

Y27

IO151NB4F13

IO151PB4F13

U20

U21

IO152NB4F14

IO152PB4F14

AG18

AG19

AC16

AB16

AF17

W24

W25

V22

IO153NB4F14

IO153PB4F14

V23

IO154NB4F14

IO154PB4F14

Y24

AF18

Y25

IO155NB4F14

IO155PB4F14

AB15

AC15

AE16

AE17

Y15

V20

V21

IO156NB4F14

IO156PB4F14

AA26

AA27

W22

W23

AA24

AA25

W20

W21

AB26

AB27

Y22

AA19

AE21

AE22

AF21

AF22

AG22

AG23

Y18

IO157NB4F14

IO157PB4F14

AA15

AG16

AG17

AF15

IO158NB4F14

IO158PB4F14

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

AF16

AD14

AD15

AA18

AE20

AD20

AG20

AG21

AC19

AB19

AD18

AD19

AC18

AB18

Y17

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

IO163PB5F15

AE14

AE15

AC13

AD13

Y14

Y23

AB24

AB25

AA22

AA23

AC26

AC27

Y20

AA14

AE13

AF13

AF12

AG12

AD12

AE12

Y13

IO164NB5F15

IO164PB5F15

IO165NB5F15

IO165PB5F15

W19

Bank 4

AA17

AF19

AF20

AC17

IO166NB5F15

IO166PB5F15

IO129NB4F12

IO129PB4F12

IO130NB4F12

AA20

Y21

IO167NB5F15

IO167PB5F15

AB22

AA13

v2.7

3-7

Axcelerator Family FPGAs

729-Pin PBGA

AX1000 Function

IO168NB5F15

IO168PB5F15

IO169NB5F15

IO169PB5F15

IO170NB5F15

IO170PB5F15

IO171NB5F16

IO171PB5F16

IO172NB5F16

IO172PB5F16

IO173NB5F16

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO176NB5F16

IO176PB5F16

IO177NB5F16

IO177PB5F16

IO178NB5F16

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO182NB5F17

IO182PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO184PB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

Pin Number

AX1000 Function

Pin Number

AX1000 Function

Pin Number

AD11

AE11

AG11

AF11

AB11

AC11

AF10

AG10

AD10

AE10

Y12

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO189NB5F17

IO189PB5F17

IO190NB5F17

IO190PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO210NB6F19

IO210PB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO214NB6F20

IO214PB6F20

IO215NB6F20

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO218NB6F20

IO218PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO222NB6F20

IO222PB6F20

IO223NB6F20

IO223PB6F20

IO224NB6F20

AA9

AD6

AE6

AB6

AA1

AC6

AF5

AG5

AA6

AA7

AA12

AB10

AC10

AF9

AA8

Bank 6

IO193NB6F18

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO199NB6F18

IO199PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO202PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

AG9

AD9

AE9

AB5

AC5

AC2

AC3

AC4

AD4

Y11

AA11

AF8

AG8

AD8

AE8

AB3

AB4

AB9

AC9

Y10

AA4

AA5

AB1

AC1

AA10

AF7

AG7

AD7

AE7

AC7

AC8

AF6

AA3

AA2

AB2

AG6

AB7

AB8

3-8

v2.7

Axcelerator Family FPGAs

729-Pin PBGA

AX1000 Function

IO224PB6F20

Bank 7

Pin Number

AX1000 Function

Pin Number

AX1000 Function

Pin Number

AE1

AE2

AE25

AE26

AE27

AE3

AE5

AF1

IO243NB7F22

IO243PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO248PB7F23

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO251NB7F23

IO251PB7F23

IO252NB7F23

IO252PB7F23

IO253NB7F23

IO253PB7F23

IO254NB7F23

IO254PB7F23

IO255NB7F23

IO255PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

GND

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO228NB7F21

IO228PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

IO236PB7F22

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO238PB7F22

IO239NB7F22

IO239PB7F22

IO240NB7F22

IO240PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

AF2

AF25

AF26

AF27

AF3

AG1

AG2

AG25

AG26

AG27

AG3

B25

B26

B27

C25

C26

C27

Dedicated I/O

GND

E27

L11

A25

A26

A27

L12

L13

L14

L15

AC24

L16

v2.7

3-9

Axcelerator Family FPGAs

729-Pin PBGA

AX1000 Function

729-Pin PBGA

AX1000 Function

GND

Pin Number

U13

U14

U15

U16

U17

Pin Number

AB13

AG13

A11

AB12

AC12

AC25

AD16

AD17

E16

L17

M11

M12

M13

M14

M15

M16

M17

N11

N12

N13

N14

N15

N16

N17

P11

P12

P13

P14

P15

P16

P17

R11

R12

R13

R14

R15

R16

R17

T11

T12

T13

T14

T15

T16

T17

U11

U12

GND

GND/LP

V_CCPLG

V_CCPLH

V_CCDA

V_CCIB0

PRA

J14

PRB

D14

V14

AB14

PRC

PRD

E24

TCK

F12

TDI

F16

TDO

TMS

K14

P10

TRST

V_CCA

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

AA21

AD5

P18

W14

G22

K10

K11

K17

K18

L10

V_CCIB0

J10

V_CCIB0

J11

V_CCIB0

J12

L18

V_CCIB0

V_CCIB1

K12

K13

A24

B24

C24

J16

U10

U18

V10

V11

V17

V18

A13

J13

V_CCIB1

_CCIB1

V_CCIB1

J17

_CCIB1

J18

K15

K16

D25

D26

D27

B15

C15

AG14

AF14

V_CCIB1

V_CCIB2

_CCIB2

3-10

v2.7

Axcelerator Family FPGAs

729-Pin PBGA

AX1000 Function

V_CCIB2

_CCIB2

Pin Number

K19

AX1000 Function

V_CCIB7

_CCIB7

Pin Number

L19

V_CCIB2

M18

M19

N18

AD25

AD26

AD27

R18

V_CCIB7

M10

V_CCIB3

V_CCIB7

V_CCIB3

V_CCIB7

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

N10

B13

V_CCIB3

A14

V_CCIB3

T18

A15

T19

J15

V_CCIB3

U19

V19

AG15

W15

AC14

W13

D24

V_CCIB3

V_CCIB4

AE24

AF24

AG24

V15

V_CCIB4

V16

V_CCIB4

W16

W17

W18

AE4

V_CCIB4

V_CCIB5

AF4

_CCIB5

AG4

V12

V_CCIB5

_CCIB5

V13

W10

W11

W12

AD1

AD2

AD3

R10

V_CCIB5

_CCIB6

V_CCIB6

_CCIB6

T10

V_CCIB6

_CCIB6

_CCIB7

v2.7

3-11

Axcelerator Family FPGAs

256-Pin FBGA

A1 Ball Pad Corner

16 15 14 13 12 11 10

Figure 3-3 • 256-Pin FBGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-12

v2.7

Axcelerator Family FPGAs

256-Pin FBGA

AX125 Function Pin Number

Bank 0

IO01NB0F0

256-Pin FBGA

AX125 Function

Pin Number

B16

AX125 Function

Pin Number

IO21PB2F2

IO22NB2F2

IO22PB2F2

IO23NB2F2

IO23PB2F2

IO25NB2F2

IO25PB2F2

IO26NB2F2

IO26PB2F2

IO27NB2F2

IO27PB2F2

IO28NB2F2

IO28PB2F2

IO29NB2F2

IO29PB2F2

IO44PB4F4

IO45NB4F4

T15

R12

R13

P11

P12

T11

T12

T13

H13

IO01PB0F0

IO03NB0F0

G13

E16

IO45PB4F4

IO46NB4F4

IO03PB0F0

D16

IO46PB4F4

IO04NB0F0

H15

IO47PB4F4

IO04PB0F0

G15

H14

IO48NB4F4

IO06NB0F0

IO48PB4F4

IO06PB0F0

G14

G16

F16

IO49NB4F4/CLKEN

IO49PB4F4/CLKEP

IO50NB4F4/CLKFN

IO50PB4F4/CLKFP

IO07NB0F0/HCLKAN

IO07PB0F0/HCLKAP

IO08NB0F0/HCLKBN

IO08PB0F0/HCLKBP

Bank 1

R10

K15

K16

Bank 5

J16

IO51NB5F5/CLKGN

IO51PB5F5/CLKGP

IO52NB5F5/CLKHN

IO52PB5F5/CLKHP

IO54NB5F5

IO09NB1F1/HCLKCN

IO09PB1F1/HCLKCP

IO10NB1F1/HCLKDN

IO10PB1F1/HCLKDP

IO12NB1F1

C10

H16

Bank 3

B11

B10

A13

A12

B13

B12

C12

C11

A15

B14

C15

C14

D13

D12

IO30NB3F3

IO30PB3F3

IO31NB3F3

IO31PB3F3

IO33NB3F3

IO33PB3F3

IO35NB3F3

IO35PB3F3

IO36PB3F3

IO37NB3F3

IO37PB3F3

IO39NB3F3

IO39PB3F3

IO40NB3F3

IO40PB3F3

IO41NB3F3

IO41PB3F3

K13

J13

K14

J14

IO54PB5F5

IO12PB1F1

IO55NB5F5

IO13NB1F1

L15

IO55PB5F5

IO13PB1F1

L16

IO56NB5F5

IO14NB1F1

P16

N16

M16

P15

R16

N15

M15

M13

L13

IO56PB5F5

IO14PB1F1

IO57NB5F5

IO15NB1F1

IO57PB5F5

IO15PB1F1

IO58NB5F5

IO16NB1F1

IO58PB5F5

IO16PB1F1

IO59NB5F5

IO17NB1F1

IO59PB5F5

IO17PB1F1

Bank 6

Bank 2

IO60NB6F6

IO60PB6F6

IO61NB6F6

IO61PB6F6

IO63NB6F6

IO63PB6F6

IO64NB6F6

IO64PB6F6

IO18NB2F2

F13

E13

F14

E14

F15

E15

C16

M14

L14

IO18PB2F2

IO19NB2F2

Bank 4

IO19PB2F2

IO42NB4F4

IO42PB4F4

IO43NB4F4

IO43PB4F4

N12

N13

T14

R14

IO20NB2F2

IO20PB2F2

IO21NB2F2

v2.7

3-13

Axcelerator Family FPGAs

256-Pin FBGA

AX125 Function

256-Pin FBGA

AX125 Function

IO65NB6F6

IO65PB6F6

IO67NB6F6

IO67PB6F6

IO69NB6F6

IO69PB6F6

IO70NB6F6

IO70PB6F6

IO71NB6F6

IO71PB6F6

Pin Number

D15

E12

AX125 Function

Pin Number

GND

GND/LP

PRD

TCK

TDI

F11

TDO

TMS

G10

TRST

V_CCA

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_CCDA

D14

F10

H10

Bank 7

IO72NB7F7

IO72PB7F7

IO73NB7F7

IO73PB7F7

IO74NB7F7

IO74PB7F7

IO75NB7F7

IO75PB7F7

IO76NB7F7

IO77NB7F7

IO77PB7F7

IO78NB7F7

IO78PB7F7

IO79NB7F7

IO79PB7F7

IO81NB7F7

IO81PB7F7

IO82NB7F7

IO82PB7F7

IO83NB7F7

IO83PB7F7

G11

J10

H11

J11

K10

K11

L10

L11

M12

P13

P14

R15

A10

D10

P10

N11

T16

Dedicated I/O

A11

R11

V_CCDA

GND

A16

B15

PRA

C13

PRB

PRC

3-14

v2.7

Axcelerator Family FPGAs

256-Pin FBGA

AX125 Function

256-Pin FBGA

AX250 Function Pin Number

Bank 0

IO01NB0F0

Pin Number

J15

N14

AX250 Function

Pin Number

E15

V_CCDA

V_CCIB0

IO33PB2F2

IO35NB2F2

IO35PB2F2

IO36NB2F2

IO36PB2F2

IO38NB2F2

IO38PB2F2

IO39NB2F2

IO39PB2F2

IO40NB2F2

IO40PB2F2

IO43NB2F2

IO43PB2F2

IO44NB2F2

IO44PB2F2

H13

IO01PB0F0

IO03NB0F0

G13

E16

IO03PB0F0

D16

V_CCIB0

IO05NB0F0

H15

V_CCIB0

V_CCIB1

IO05PB0F0

G15

H14

E10

E11

IO07NB0F0

V_CCIB1

IO07PB0F0

G14

G16

F16

V_CCIB1

V_CCIB2

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

F12

G12

H12

J12

K12

L12

M10

M11

V_CCIB2

K15

V_CCIB2

V_CCIB3

K16

J16

V_CCIB3

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO17NB1F1

C10

H16

V_CCIB3

V_CCIB4

Bank 3

B11

B10

A13

A12

B13

B12

C12

C11

A15

B14

C15

C14

D13

D12

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO52NB3F3

IO52PB3F3

IO54NB3F3

IO54PB3F3

IO55PB3F3

IO56NB3F3

IO56PB3F3

IO58NB3F3

IO58PB3F3

IO59NB3F3

IO59PB3F3

IO61NB3F3

IO61PB3F3

K13

J13

V_CCIB4

V_CCIB5

K14

J14

IO17PB1F1

V_CCIB5

IO19NB1F1

L15

V_CCIB5

V_CCIB6

IO19PB1F1

L16

IO21NB1F1

P16

N16

M16

P15

R16

N15

M15

M13

L13

V_CCIB6

IO21PB1F1

V_CCIB6

IO23NB1F1

V_CCIB7

IO23PB1F1

IO26NB1F1

IO26PB1F1

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

IO27NB1F1

IO27PB1F1

Bank 2

D11

T10

N10

IO29NB2F2

F13

E13

F14

E14

C16

B16

F15

M14

L14

IO29PB2F2

V_COMPLF

IO30NB2F2

Bank 4

V_COMPLG

V_COMPLH

V_PUMP

IO30PB2F2

IO62NB4F4

IO62PB4F4

IO63NB4F4

IO63PB4F4

N12

N13

T14

R14

IO32NB2F2

A14

IO32PB2F2

IO33NB2F2

v2.7

3-15

Axcelerator Family FPGAs

256-Pin FBGA

AX250 Function

IO66PB4F4

Pin Number

AX250 Function

Pin Number

D15

E12

T15

R12

R13

P11

P12

T11

T12

T13

IO98NB6F6

IO98PB6F6

GND

GND/LP

PRA

IO67NB4F4

IO67PB4F4

IO100NB6F6

IO100PB6F6

IO102NB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO104NB6F6

IO104PB6F6

IO69NB4F4

F11

IO69PB4F4

IO70PB4F4

G10

IO73NB4F4

IO73PB4F4

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

R10

H10

Bank 7

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO111NB7F7

IO111PB7F7

IO112NB7F7

IO112PB7F7

IO113NB7F7

IO114NB7F7

IO114PB7F7

IO115NB7F7

IO115PB7F7

IO116NB7F7

IO116PB7F7

IO117NB7F7

IO117PB7F7

IO118NB7F7

IO118PB7F7

IO119NB7F7

IO119PB7F7

Bank 5

IO76NB5F5/CLKGN

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO79NB5F5

J10

K10

IO79PB5F5

IO81NB5F5

IO81PB5F5

IO83NB5F5

L11

IO83PB5F5

IO85NB5F5

M12

P13

IO85PB5F5

IO88NB5F5

IO88PB5F5

IO89NB5F5

R15

IO89PB5F5

Bank 6

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO94NB6F6

IO94PB6F6

IO97NB6F6

IO97PB6F6

T16

Dedicated I/O

V_CCDA

GND

PRB

PRC

A16

B15

PRD

TCK

TDI

3-16

v2.7

Axcelerator Family FPGAs

256-Pin FBGA

AX250 Function

Pin Number

AX250 Function

Pin Number

TDO

TMS

V_CCDA

V_CCIB0

TRST

R11

V_CCA

D14

F10

V_CCA

V_CCIB0

V_CCA

V_CCIB0

V_CCIB1

V_CCA

E10

E11

V_CCA

V_CCIB1

V_CCA

G11

V_CCIB1

V_CCIB2

V_CCA

F12

G12

H12

J12

K12

L12

M10

M11

V_CCA

H11

V_CCIB2

V_CCA

V_CCIB2

V_CCIB3

V_CCA

J11

V_CCA

V_CCIB3

V_CCA

K11

V_CCIB3

V_CCIB4

V_CCA

L10

V_CCIB4

V_CCA

V_CCIB4

V_CCIB5

V_CCA

V_CCIB5

V_CCA

V_CCIB5

V_CCIB6

V_CCA

P14

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_CCDA

V_CCIB6

A10

D10

P10

N11

V_CCIB7

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

A11

D11

T10

N10

C13

J15

N14

A14

v2.7

3-17

Axcelerator Family FPGAs

324-Pin FBGA

A1 Ball Pad Corner

18 17 16 15 14 13 12 11 10

Figure 3-4 • 324-Pin FBGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-18

v2.7

Axcelerator Family FPGAs

324-Pin FBGA

AX125 Function Pin Number

Bank 0

IO00NB0F0

324-Pin FBGA

AX125 Function Pin Number

Bank 2

IO18NB2F2

AX125 Function

Pin Number

P16

IO36NB3F3

IO36PB3F3

IO37NB3F3

IO37PB3F3

IO38NB3F3

IO38PB3F3

IO39NB3F3

IO39PB3F3

IO40NB3F3

IO40PB3F3

IO41NB3F3

IO41PB3F3

G14

F14

D16

D15

C18

B18

D17

C17

F17

E17

G16

F16

E18

D18

G18

F18

H17

G17

J16

N16

IO00PB0F0

IO01NB0F0

IO18PB2F2

IO19NB2F2

IO19PB2F2

IO20NB2F2

IO20PB2F2

IO21NB2F2

IO21PB2F2

IO22NB2F2

IO22PB2F2

IO23NB2F2

IO23PB2F2

IO24NB2F2

IO24PB2F2

IO25NB2F2

IO25PB2F2

IO26NB2F2

IO26PB2F2

IO27NB2F2

IO27PB2F2

IO28NB2F2

IO28PB2F2

IO29NB2F2

IO29PB2F2

R17

P17

IO01PB0F0

N14

IO02NB0F0

M14

U18

IO02PB0F0

IO03NB0F0

T18

IO03PB0F0

R16

IO04NB0F0

T17

IO04PB0F0

P13

IO05NB0F0

P14

IO05PB0F0

Bank 4

IO06NB0F0

IO42NB4F4

IO42PB4F4

T13

T14

U15

T15

U13

U14

V15

V16

V13

V14

V12

U12

V10

V11

T10

T11

IO06PB0F0

IO07NB0F0/HCLKAN

IO07PB0F0/HCLKAP

IO08NB0F0/HCLKBN

IO08PB0F0/HCLKBP

Bank 1

B10

IO43NB4F4

IO43PB4F4

IO44NB4F4

IO44PB4F4

IO45NB4F4

IO09NB1F1/HCLKCN

IO09PB1F1/HCLKCP

IO10NB1F1/HCLKDN

IO10PB1F1/HCLKDP

IO11NB1F1

D11

D10

C12

C11

A15

A14

B14

B13

A17

A16

D13

D12

C14

C13

B16

C15

E14

E13

H16

J18

IO45PB4F4

IO46NB4F4

H18

K17

J17

IO46PB4F4

IO47NB4F4

IO47PB4F4

IO11PB1F1

Bank 3

IO48NB4F4

IO12NB1F1

IO30NB3F3

IO30PB3F3

IO31NB3F3

IO31PB3F3

IO32NB3F3

IO32PB3F3

IO33NB3F3

IO33PB3F3

IO34NB3F3

IO34PB3F3

IO35NB3F3

IO35PB3F3

N18

M18

L18

IO48PB4F4

IO12PB1F1

IO49NB4F4/CLKEN

IO49PB4F4/CLKEP

IO50NB4F4/CLKFN

IO50PB4F4/CLKFP

IO13NB1F1

IO13PB1F1

K18

L16

IO14NB1F1

U10

IO14PB1F1

L17

Bank 5

IO15NB1F1

R18

P18

IO51NB5F5/CLKGN

IO51PB5F5/CLKGP

IO52NB5F5/CLKHN

IO52PB5F5/CLKHP

IO53NB5F5

IO15PB1F1

IO16NB1F1

N15

M15

M16

M17

IO16PB1F1

IO17NB1F1

IO17PB1F1

IO53PB5F5

v2.7

3-19

Axcelerator Family FPGAs

324-Pin FBGA

AX125 Function

IO54NB5F5

IO54PB5F5

IO55NB5F5

IO55PB5F5

IO56NB5F5

IO56PB5F5

IO57NB5F5

IO57PB5F5

IO58NB5F5

IO58PB5F5

IO59NB5F5

IO59PB5F5

Pin Number

AX125 Function

Pin Number

H11

IO72NB7F7

IO72PB7F7

IO73NB7F7

IO73PB7F7

IO74NB7F7

IO74PB7F7

IO75NB7F7

IO75PB7F7

IO76NB7F7

IO76PB7F7

IO77NB7F7

IO77PB7F7

IO78NB7F7

IO78PB7F7

IO79NB7F7

IO79PB7F7

IO80NB7F7

IO80PB7F7

IO81NB7F7

IO81PB7F7

IO82NB7F7

IO82PB7F7

IO83NB7F7

IO83PB7F7

GND

GND/LP

J10

J11

K10

K11

L10

L11

Bank 6

IO60NB6F6

IO60PB6F6

IO61NB6F6

IO61PB6F6

IO62NB6F6

IO62PB6F6

IO63NB6F6

IO63PB6F6

IO64NB6F6

IO64PB6F6

IO65NB6F6

IO65PB6F6

IO66NB6F6

IO66PB6F6

IO67NB6F6

IO67PB6F6

IO68NB6F6

IO68PB6F6

IO69NB6F6

IO69PB6F6

IO70NB6F6

IO70PB6F6

IO71NB6F6

IO71PB6F6

M12

N13

R14

T16

U17

Dedicated I/O

V_CCDA

GND

V18

A18

B17

A10

A11

A12

A13

C16

E16

F13

B12

F15

G12

Bank 7

H10

G15

3-20

v2.7

Axcelerator Family FPGAs

324-Pin FBGA

AX125 Function

Pin Number

G11

AX125 Function

V_CCIB1

_CCIB1

Pin Number

F11

F12

G13

H13

J13

V_CCA

H14

H15

V_CCA

V_CCIB2

V_CCA

H12

J14

J15

V_CCA

_CCIB3

K13

L13

M13

N10

N11

N12

V_CCA

J12

V_CCIB3

V_CCA

K14

K15

V_CCA

K12

V_CCIB4

V_CCA

V_CCIB4

V_CCA

L12

L14

L15

V_CCA

V_CCIB5

V_CCA

M10

M11

V_CCIB5

V_CCA

N17

V_CCA

_CCIB6

V_CCA

V_CCIB6

V_CCA

R15

_CCIB7

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_CCDA

V_CCIB0

V_CCIB7

R12

R13

B11

E11

R11

P12

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

C10

E12

U11

P11

T12

U16

V17

PRA

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

V_CCA

D14

E10

B15

P10

R10

K16

P15

E15

G10

_CCIB0

_CCIB1

F10

v2.7

3-21

Axcelerator Family FPGAs

484-Pin FBGA

A1 Ball Pad Corner

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Figure 3-5 • 484-Pin FBGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-22

v2.7

Axcelerator Family FPGAs

484-Pin FBGA

AX250 Function Pin Number

Bank 0

IO00NB0F0

484-Pin FBGA

AX250 Function

Pin Number

A14

A13

A16

A15

B16

AX250 Function

Pin Number

F21

IO18NB1F1

IO18PB1F1

IO19NB1F1

IO19PB1F1

IO20NB1F1

IO20PB1F1

IO21NB1F1

IO21PB1F1

IO22NB1F1

IO22PB1F1

IO23NB1F1

IO23PB1F1

IO24NB1F1

IO24PB1F1

IO25NB1F1

IO25PB1F1

IO26NB1F1

IO26PB1F1

IO27NB1F1

IO27PB1F1

IO36PB2F2

IO37NB2F2

IO37PB2F2

IO38NB2F2

IO38PB2F2

IO39NB2F2

IO39PB2F2

IO40NB2F2

IO40PB2F2

IO41NB2F2

IO41PB2F2

IO42NB2F2

IO42PB2F2

IO43NB2F2

IO43PB2F2

IO44NB2F2

IO44PB2F2

K19

J19

IO00PB0F0

IO01NB0F0

J20

IO01PB0F0

H20

L16

IO02NB0F0

B15

IO02PB0F0

C17

C16

F15

K16

J21

IO03NB0F0

IO03PB0F0

H21

L17

IO04NB0F0

F14

IO04PB0F0

D16

D15

E16

K17

J22

IO05NB0F0

IO05PB0F0

H22

L18

IO06NB0F0

E15

IO06PB0F0

F18

K18

L20

IO07NB0F0

F17

IO07PB0F0

D18

E17

K20

IO08NB0F0

Bank 3

IO08PB0F0

G16

G15

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO47NB3F3

IO47PB3F3

IO48NB3F3

IO48PB3F3

IO49NB3F3

IO49PB3F3

IO50NB3F3

IO50PB3F3

IO51NB3F3

IO51PB3F3

IO52NB3F3

IO52PB3F3

IO53NB3F3

IO53PB3F3

IO54NB3F3

IO54PB3F3

M19

L19

IO09NB0F0

IO09PB0F0

Bank 2

M21

L21

IO10NB0F0

B10

A10

E11

E10

D12

D11

IO28NB2F2

IO28PB2F2

IO29NB2F2

IO29PB2F2

IO30NB2F2

IO30PB2F2

IO31NB2F2

IO31PB2F2

IO32NB2F2

IO32PB2F2

IO33NB2F2

IO33PB2F2

IO34NB2F2

IO34PB2F2

IO35NB2F2

IO35PB2F2

IO36NB2F2

F19

E19

J16

IO10PB0F0

N17

M17

N18

N19

N16

M16

N20

M20

P21

N21

P18

P19

R20

P20

T21

R21

IO11NB0F0

IO11PB0F0

H16

E20

D20

J17

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

H17

G20

F20

H19

G19

E22

D22

J18

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

F13

F12

E14

E13

C13

C12

B14

B13

IO16PB1F1

IO17NB1F1

H18

G21

IO17PB1F1

v2.7

3-23

Axcelerator Family FPGAs

484-Pin FBGA

AX250 Function

IO55NB3F3

IO55PB3F3

IO56NB3F3

IO56PB3F3

IO57NB3F3

IO57PB3F3

IO58NB3F3

IO58PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

Pin Number

AX250 Function

Pin Number

AB13

AX250 Function

Pin Number

R17

P17

U20

T20

T18

R18

U19

T19

R16

P16

W20

V20

U18

V19

IO73PB4F4

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO93NB6F6

IO93PB6F6

IO94NB6F6

IO94PB6F6

IO95NB6F6

IO95PB6F6

IO96NB6F6

IO96PB6F6

IO97NB6F6

IO97PB6F6

IO98NB6F6

IO98PB6F6

IO99NB6F6

IO99PB6F6

IO100NB6F6

IO100PB6F6

IO101NB6F6

IO101PB6F6

IO102NB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO104NB6F6

IO104PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

V12

V13

W11

W12

Bank 5

IO76NB5F5/CLKGN

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

IO78PB5F5

U10

U11

V10

AA9

AA10

AB9

AB10

AA7

AA8

AB5

AB6

AA5

AA6

IO79NB5F5

IO79PB5F5

Bank 4

IO80NB5F5

IO80PB5F5

IO62NB4F4

IO62PB4F4

IO63NB4F4

IO63PB4F4

IO64NB4F4

IO64PB4F4

IO65NB4F4

IO65PB4F4

IO66NB4F4

IO66PB4F4

IO67NB4F4

IO67PB4F4

IO68NB4F4

IO68PB4F4

IO69NB4F4

IO69PB4F4

IO70NB4F4

IO70PB4F4

IO71NB4F4

IO71PB4F4

IO72NB4F4

IO72PB4F4

IO73NB4F4

T15

T16

IO81NB5F5

IO81PB5F5

W17

V17

IO82NB5F5

IO82PB5F5

V15

V16

IO83NB5F5

IO83PB5F5

Y19

W18

AB18

AB19

W15

W16

U14

IO84NB5F5

IO84PB5F5

IO85NB5F5

IO85PB5F5

IO86NB5F5

IO86PB5F5

U15

IO87NB5F5

IO87PB5F5

AA16

AA17

AB14

AB15

Y14

IO88NB5F5

IO88PB5F5

Bank 7

IO89NB5F5

IO89PB5F5

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO109NB7F7

IO109PB7F7

W14

AA14

AA15

AA13

Bank 6

IO90NB6F6

IO90PB6F6

IO91NB6F6

3-24

v2.7

Axcelerator Family FPGAs

484-Pin FBGA

AX250 Function

Pin Number

AA21

AA22

AB1

AB11

AB12

AB2

AB21

AB22

AX250 Function

Pin Number

M22

N10

N11

N12

N13

P14

IO110NB7F7

IO110PB7F7

IO111NB7F7

IO111PB7F7

IO112NB7F7

IO112PB7F7

IO113NB7F7

IO113PB7F7

IO114NB7F7

IO114PB7F7

IO115NB7F7

IO115PB7F7

IO116NB7F7

IO116PB7F7

IO117NB7F7

IO117PB7F7

IO118NB7F7

IO118PB7F7

IO119NB7F7

IO119PB7F7

IO120NB7F7

IO120PB7F7

IO121NB7F7

IO121PB7F7

IO122NB7F7

IO122PB7F7

IO123NB7F7

IO123PB7F7

GND

GND/LP

R15

U16

B21

B22

C20

V18

W19

D19

Y20

E18

G18

H15

A17

A18

A19

J14

K10

K11

K12

K13

AA11

AA12

AA18

AA19

AA4

AB16

AB17

AB4

AB7

AB8

B11

Dedicated I/O

L10

V_CCDA

GND

L11

L12

A11

A12

L13

L22

A21

A22

AA1

AA2

M10

M11

M12

M13

B12

B17

B18

B19

v2.7

3-25

Axcelerator Family FPGAs

484-Pin FBGA

AX250 Function

Pin Number

AX250 Function

Pin Number

AX250 Function

Pin Number

V_CCA

W21

W22

Y10

Y11

Y12

Y13

Y15

Y16

Y17

Y18

P10

P11

P12

P13

C10

C11

C14

C15

C18

C19

V_CCA

U17

F10

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_CCDA

D13

G13

U13

T14

W10

T10

D14

D21

E21

F22

PRA

PRB

PRC

PRD

TCK

TDI

G11

F11

T12

U12

F16

G12

G22

M18

T11

T17

K21

K22

N22

P22

R19

R22

TDO

TMS

TRST

V_CCA

V14

G17

J10

_CCIB0

J11

J12

V_CCIB0

H10

H11

T22

J13

_CCIB0

K14

V_CCIB1

A20

B20

H12

H13

H14

C21

C22

U21

U22

_CCIB1

L14

V_CCIB1

M14

V21

V22

_CCIB2

N14

3-26

v2.7

Axcelerator Family FPGAs

484-Pin FBGA

AX500 Function Pin Number

Bank 0

IO00NB0F0

AX250 Function

V_CCIB2

_CCIB2

Pin Number

J15

AX500 Function

IO20PB0F1/HCLKBP

Bank 1

Pin Number

D11

K15

L15

M15

N15

P15

Y21

Y22

AA20

AB20

R12

R13

R14

AA3

AB3

R10

R11

V_CCIB2

V_CCIB3

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO24NB1F2

IO24PB1F2

F13

F12

E14

E13

A14

A13

B14

B13

C15

A16

A15

B16

B15

D16

D15

A18

A17

F15

F14

C17

C16

E16

E15

B18

B17

B19

A19

C19

C18

F18

F17

D18

E17

E21

D21

E20

_CCIB3

V_CCIB3

IO03NB0F0

IO03PB0F0

_CCIB4

IO25NB1F2

IO25PB1F2

V_CCIB4

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO26NB1F2

IO27NB1F2

IO27PB1F2

_CCIB4

V_CCIB4

V_CCIB5

IO06NB0F0

IO06PB0F0

IO28NB1F2

IO28PB1F2

_CCIB5

V_CCIB5

IO07NB0F0

IO07PB0F0

IO29NB1F2

IO29PB1F2

_CCIB5

IO08NB0F0

IO08PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO30NB1F2

IO30PB1F2

V_CCIB6

IO31NB1F2

IO31PB1F2

_CCIB6

V_CCIB6

IO32NB1F3

IO32PB1F3

_CCIB7

B10

A10

B12

B11

C13

C12

E11

E10

D12

IO33NB1F3

IO33PB1F3

V_CCIB7

_CCIB7

IO13NB0F1

IO13PB0F1

IO34NB1F3

IO34PB1F3

IO14NB0F1

IO14PB0F1

IO35NB1F3

IO35PB1F3

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

D10

G10

E12

G14

W13

T13

V11

IO15NB0F1

IO15PB0F1

IO36NB1F3

IO36PB1F3

IO16NB0F1

IO16PB0F1

IO18NB0F1

IO18PB0F1

IO37NB1F3

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO39NB1F3

IO39PB1F3

D17

IO40NB1F3

v2.7

3-27

Axcelerator Family FPGAs

484-Pin FBGA

AX500 Function

IO40PB1F3

Pin Number

AX500 Function

Pin Number

AX500 Function

Pin Number

T18

D20

G16

G15

IO60NB2F5

IO60PB2F5

IO61NB2F5

IO61PB2F5

IO62NB2F5

IO62PB2F5

M21

L21

IO79NB3F7

IO79PB3F7

IO80NB3F7

IO80PB3F7

IO81NB3F7

IO81PB3F7

IO82NB3F7

IO82PB3F7

IO83NB3F7

IO83PB3F7

IO41NB1F3

R18

IO41PB1F3

L16

W20

V20

Bank 2

K16

M19

L19

IO42NB2F4

IO42PB2F4

IO43NB2F4

IO43PB2F4

IO44NB2F4

IO44PB2F4

IO45NB2F4

IO45PB2F4

IO46NB2F4

IO46PB2F4

IO47NB2F4

IO47PB2F4

IO48NB2F4

IO48PB2F4

IO49NB2F4

IO49PB2F4

IO50NB2F4

IO50PB2F4

IO51NB2F4

IO51PB2F4

IO52NB2F5

IO52PB2F5

IO53NB2F5

IO53PB2F5

IO54NB2F5

IO54PB2F5

IO55NB2F5

IO55PB2F5

IO56NB2F5

IO56PB2F5

IO58NB2F5

IO58PB2F5

IO59NB2F5

IO59PB2F5

F19

E19

J16

U19

T19

Bank 3

U18

H16

E22

D22

H19

G19

G22

F22

J17

IO63NB3F6

IO63PB3F6

IO64NB3F6

IO64PB3F6

IO65NB3F6

IO65PB3F6

IO66NB3F6

IO66PB3F6

IO67NB3F6

IO67PB3F6

IO68NB3F6

IO68PB3F6

IO69NB3F6

IO69PB3F6

IO70NB3F6

IO70PB3F6

IO71NB3F6

IO71PB3F6

IO72NB3F6

IO72PB3F6

IO73PB3F6

IO74NB3F7

IO74PB3F7

IO75NB3F7

IO75PB3F7

IO76NB3F7

IO76PB3F7

IO77NB3F7

IO77PB3F7

IO78NB3F7

IO78PB3F7

N16

M16

P22

N22

N20

M20

P21

N21

N18

N19

T22

R22

N17

M17

T21

R21

P18

P19

R20

P20

R19

V21

U21

V22

U22

U20

T20

R17

P17

W21

W22

V19

R16

P16

Bank 4

IO84NB4F8

IO84PB4F8

IO85NB4F8

IO85PB4F8

IO86NB4F8

IO86PB4F8

IO87NB4F8

IO87PB4F8

IO88NB4F8

IO88PB4F8

IO89NB4F8

IO89PB4F8

IO90NB4F8

IO90PB4F8

IO91NB4F8

IO91PB4F8

IO92PB4F8

IO93NB4F8

IO93PB4F8

IO94NB4F9

IO94PB4F9

IO95NB4F9

IO95PB4F9

IO96NB4F9

IO96PB4F9

IO97NB4F9

IO97PB4F9

AB18

AB19

T15

T16

H17

G20

F20

J18

AA18

AA19

W17

V17

H18

G21

F21

K19

J19

Y19

W18

U14

U15

Y17

J21

Y18

H21

J20

V15

V16

H20

J22

AB17

Y15

H22

L17

K17

K21

K22

L20

K20

L18

K18

Y16

AA16

AA17

AB14

AB15

W15

W16

AA13

AB13

3-28

v2.7

Axcelerator Family FPGAs

484-Pin FBGA

AX500 Function

484-Pin FBGA

Pin Number

AA14

AA15

Y14

AX500 Function

Pin Number

AX500 Function

Pin Number

IO98NB4F9

IO98PB4F9

IO119NB5F11

IO119PB5F11

IO120NB5F11

IO120PB5F11

IO121NB5F11

IO121PB5F11

IO122NB5F11

IO122PB5F11

IO123NB5F11

IO123PB5F11

IO124NB5F11

IO124PB5F11

IO125NB5F11

IO125PB5F11

AA4

AB4

IO139NB6F13

IO139PB6F13

IO140NB6F13

IO140PB6F13

IO141NB6F13

IO141PB6F13

IO142NB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO144NB6F13

IO144PB6F13

IO145NB6F13

IO145PB6F13

IO146NB6F13

IO146PB6F13

IO100NB4F9

IO100PB4F9

W14

IO101NB4F9

Y12

IO101PB4F9

Y13

IO102NB4F9

AA11

AA12

V12

IO102PB4F9

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

V13

W11

W12

IO105NB5F10/CLKGN

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO108NB5F10

IO108PB5F10

IO110NB5F10

IO110PB5F10

IO111NB5F10

IO111PB5F10

IO112NB5F10

IO113NB5F10

IO113PB5F10

IO114NB5F11

IO114PB5F11

IO115NB5F11

IO115PB5F11

IO116NB5F11

IO116PB5F11

IO117NB5F11

IO117PB5F11

IO118NB5F11

IO118PB5F11

U10

U11

Bank 6

IO126NB6F12

IO126PB6F12

IO127NB6F12

IO127PB6F12

IO128NB6F12

IO128PB6F12

IO129NB6F12

IO129PB6F12

IO130NB6F12

IO130PB6F12

IO131NB6F12

IO131PB6F12

IO132NB6F12

IO132PB6F12

IO133NB6F12

IO134NB6F12

IO134PB6F12

IO135NB6F12

IO135PB6F12

IO136NB6F13

IO136PB6F13

IO138NB6F13

IO138PB6F13

V10

Y10

Y11

AA9

AA10

AB9

AB10

Bank 7

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO149NB7F14

IO149PB7F14

IO150NB7F14

IO150PB7F14

IO151NB7F14

IO151PB7F14

IO152NB7F14

IO152PB7F14

IO153NB7F14

IO153PB7F14

IO154NB7F14

IO154PB7F14

IO155NB7F14

IO155PB7F14

IO156NB7F14

IO156PB7F14

IO157NB7F14

AB7

AA7

AA8

AB5

AB6

AA5

AA6

v2.7

3-29

Axcelerator Family FPGAs

484-Pin FBGA

AX500 Function

484-Pin FBGA

AX500 Function

IO157PB7F14

IO158NB7F15

IO158PB7F15

IO159NB7F15

IO159PB7F15

IO160NB7F15

IO160PB7F15

IO161NB7F15

IO161PB7F15

IO162NB7F15

IO162PB7F15

IO163NB7F15

IO163PB7F15

IO164NB7F15

IO164PB7F15

IO165NB7F15

IO165PB7F15

IO166NB7F15

IO166PB7F15

IO167NB7F15

IO167PB7F15

Pin Number

AB22

Pin Number

R15

GND

GND/LP

U16

B21

B22

C20

V18

W19

Y20

D19

E18

G18

H15

AB8

AB16

C10

C11

C14

G11

F11

T12

U12

J14

K10

K11

K12

K13

PRA

PRB

PRC

PRD

TCK

Dedicated I/O

L10

L11

L12

L13

L22

TDI

V_CCDA

GND

TDO

TMS

TRST

V_CCA

A11

A12

G17

J10

A21

A22

AA1

AA2

AA21

AA22

AB1

AB11

AB12

AB2

AB21

M10

M11

M12

M13

M22

N10

N11

N12

N13

P14

J11

J12

J13

K14

L14

M14

N14

3-30

v2.7

Axcelerator Family FPGAs

484-Pin FBGA

AX500 Function

Pin Number

AX500 Function

V_CCIB2

_CCIB2

Pin Number

J15

V_CCA

P10

P11

P12

P13

K15

L15

M15

N15

P15

Y21

Y22

AA20

AB20

R12

R13

R14

AA3

AB3

R10

R11

V_CCA

V_CCIB2

V_CCIB3

V_CCA

V_CCIB3

V_CCA

U17

F10

V_CCIB3

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_CCDA

V_CCIB4

D13

G13

U13

T14

W10

T10

D14

V_CCIB4

V_CCIB5

F16

G12

V_CCIB5

V_CCIB6

M18

T11

T17

V_CCIB6

V_CCIB7

V14

V_CCIB7

_CCIB0

V_CCIB0

H10

H11

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

D10

G10

E12

G14

W13

T13

V11

_CCIB0

V_CCIB1

A20

B20

H12

H13

H14

C21

C22

_CCIB1

V_CCIB1

_CCIB2

D17

v2.7

3-31

Axcelerator Family FPGAs

484-Pin FBGA

AX1000 Function

Bank 0

Pin Number

AX1000 Function

Pin Number

F12

AX1000 Function

Pin Number

J16

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO34NB1F3

IO34PB1F3

IO37NB1F3

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO40NB1F3

IO42NB1F4

IO42PB1F4

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO57NB1F5

IO57PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO63NB1F5

IO63PB1F5

Bank 2

IO68NB2F6

IO68PB2F6

IO70NB2F6

IO70PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO84NB2F7

IO84PB2F7

IO85NB2F8

IO85PB2F8

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

IO01NB0F0

IO01PB0F0

E14

H16

J17

E13

IO02NB0F0

IO02PB0F0

C13

C12

B14

B13

A16

A15

C15

A18

A17

B16

B15

B18

B17

B19

A19

C19

C18

F15

H17

J18

IO05NB0F0

IO05PB0F0

H18

G20

F20

IO06NB0F0

IO06PB0F0

H19

G19

L16

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

K16

L17

IO14NB0F1

IO14PB0F1

K17

G21

F21

IO15NB0F1

IO15PB0F1

G22

F22

IO16NB0F1

IO16PB0F1

J20

IO17NB0F1

IO17PB0F1

H20

L18

IO18NB0F1

IO18PB0F1

F14

K18

K19

J19

D16

D15

C17

C16

E22

IO19NB0F1

IO19PB0F1

J21

IO20NB0F1

IO20PB0F1

H21

J22

IO21NB0F1

IO21PB0F1

D22

E16

H22

K21

K22

L20

IO22NB0F2

IO22PB0F2

B10

A10

A14

A13

B12

B11

E11

E10

D12

D11

E15

E21

IO23NB0F2

IO23PB0F2

D21

G16

G15

D18

E17

K20

M21

L21

IO26NB0F2

IO26PB0F2

Bank 3

IO29NB0F2

IO29PB0F2

IO96NB3F9

IO96PB3F9

IO97NB3F9

IO97PB3F9

IO98NB3F9

IO98PB3F9

IO99NB3F9

IO99PB3F9

N16

M16

M19

L19

E20

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

D20

IO64NB2F6

IO64PB2F6

IO67NB2F6

IO67PB2F6

F18

F17

F19

E19

P22

N22

N20

M20

IO32NB1F3/HCLKCN

F13

3-32

v2.7

Axcelerator Family FPGAs

484-Pin FBGA

AX1000 Function

484-Pin FBGA

Pin Number

N17

M17

P21

AX1000 Function

Pin Number

U18

AX1000 Function

Pin Number

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO103NB3F9

IO103PB3F9

IO104NB3F9

IO104PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

IO107PB3F10

IO110NB3F10

IO110PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO121NB3F11

IO121PB3F11

IO124NB3F11

IO124PB3F11

IO127NB3F11

IO127PB3F11

IO140NB4F13

IO140PB4F13

IO171NB5F16

IO171PB5F16

IO172NB5F16

IO172PB5F16

IO173NB5F16

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO176NB5F16

IO176PB5F16

IO177NB5F16

IO177PB5F16

IO178NB5F16

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO184NB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO192NB5F17

IO192PB5F17

V19

IO142NB4F13

IO142PB4F13

W20

V20

N21

R20

IO143NB4F13

IO143PB4F13

W15

W16

AA18

AA19

U14

P20

N18

N19

T22

IO144NB4F13

IO144PB4F13

AA7

AA8

AB5

AB6

AA5

AA6

AA4

AB4

IO145NB4F13

IO145PB4F13

R22

U15

R17

IO146NB4F13

IO146PB4F13

Y15

P17

Y16

T21

IO147NB4F13

IO147PB4F13

AB18

AB19

Y14

R21

V22

U22

V21

U21

P18

IO149NB4F13

IO149PB4F13

W14

AA16

AA17

AA14

AA15

AB14

AB15

AA13

AB13

Y12

IO150NB4F13

IO150PB4F13

IO152NB4F14

IO152PB4F14

P19

R19

IO154NB4F14

IO154PB4F14

U20

T20

IO155NB4F14

IO155PB4F14

AB7

T18

R18

IO158NB4F14

IO158PB4F14

U19

T19

Y13

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

V12

R16

V13

P16

W11

W12

W21

W22

Bank 6

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO203NB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

Bank 4

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

IO163PB5F15

U10

U11

IO129PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO135NB4F12

IO135PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

AB17

Y19

W18

W17

V17

T15

V10

Y10

Y11

IO167NB5F15

IO167PB5F15

AA11

AA12

AA9

AA10

AB9

T16

Y17

Y18

V15

V16

IO169NB5F15

IO169PB5F15

IO170NB5F15

IO170PB5F15

AB10

v2.7

3-33

Axcelerator Family FPGAs

484-Pin FBGA

AX1000 Function

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO212NB6F19

IO212PB6F19

IO214NB6F20

IO214PB6F20

IO215NB6F20

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO222NB6F20

IO222PB6F20

IO223NB6F20

IO223PB6F20

IO224NB6F20

IO224PB6F20

Bank 7

Pin Number

AX1000 Function

Pin Number

AX1000 Function

Pin Number

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

IO236PB7F22

IO237NB7F22

IO237PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO243NB7F22

IO243PB7F22

IO246NB7F22

IO246PB7F22

IO250NB7F23

IO250PB7F23

IO253NB7F23

IO253PB7F23

IO254NB7F23

IO254PB7F23

IO257NB7F23

IO257PB7F23

GND

B21

B22

C20

D19

E18

G18

H15

J14

K10

K11

K12

K13

L10

L11

L12

L13

L22

Dedicated I/O

V_CCDA

GND

M10

M11

M12

M13

M22

N10

N11

N12

N13

P14

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO228NB7F21

IO228PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

A11

A12

A21

A22

AA1

AA2

AA21

AA22

AB1

AB11

AB12

AB2

AB21

AB22

R15

U16

V18

W19

3-34

v2.7

Axcelerator Family FPGAs

484-Pin FBGA

AX1000 Function

484-Pin FBGA

AX1000 Function

Pin Number

Y20

Pin Number

C10

C11

C14

D14

AX1000 Function

Pin Number

GND

V_CCDA

V_CCIB0

V_CCIB5

V_CCIB6

V_CCIB7

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

GND

GND/LP

PRA

G11

F11

T12

U12

PRB

F16

PRC

G12

PRD

TCK

M18

T11

T17

TDI

TDO

TMS

D10

G10

E12

G14

W13

T13

V11

TRST

V14

V_CCA

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_CCDA

G17

J10

J11

V_CCIB0

J12

V_CCIB0

V_CCIB1

H10

H11

J13

K14

A20

B20

H12

H13

H14

C21

C22

J15

D17

V_CCIB1

L14

V_CCIB1

V_CCIB2

M14

N14

V_CCIB2

P10

P11

P12

P13

K15

L15

V_CCIB3

M15

N15

P15

Y21

Y22

AA20

AB20

R12

R13

R14

AA3

AB3

R10

R11

V_CCIB3

U17

F10

_CCIB3

V_CCIB3

_CCIB4

D13

G13

U13

T14

W10

T10

AB16

AB8

V_CCIB4

V_CCIB5

v2.7

3-35

Axcelerator Family FPGAs

676-Pin FBGA

A1 Ball Pad Corner

7 6 2 1

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Figure 3-6 • 676-Pin FBGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-36

v2.7

Axcelerator Family FPGAs

676-Pin FBGA

AX500 Function Pin Number

Bank 0

IO00NB0F0

676-Pin FBGA

AX500 Function

Pin Number

AX500 Function

Pin Number

B23

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

A12

B12

C13

B13

IO38NB1F3

IO38PB1F3

IO39NB1F3

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F3

IO41PB1F3

A23

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

E21

E20

D23

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO23NB1F2

C15

C14

A15

B15

F15

C23

D25

C25

Bank 2

IO42NB2F4

IO42PB2F4

IO43NB2F4

IO43PB2F4

IO44NB2F4

IO44PB2F4

IO45NB2F4

IO45PB2F4

IO46NB2F4

IO46PB2F4

IO47NB2F4

IO47PB2F4

IO48NB2F4

IO48PB2F4

IO49NB2F4

IO49PB2F4

IO50NB2F4

IO50PB2F4

IO51NB2F4

IO51PB2F4

IO52NB2F5

IO52PB2F5

IO53NB2F5

IO53PB2F5

IO54NB2F5

IO54PB2F5

IO55NB2F5

IO55PB2F5

IO56NB2F5

IO56PB2F5

G24

G23

G26

F26

F25

E25

J21

IO23PB1F2

G15

B16

A16

A18

A17

D16

E16

F16

IO24NB1F2

IO24PB1F2

IO25NB1F2

IO25PB1F2

IO26NB1F2

IO26PB1F2

J22

IO27NB1F2

H25

G25

K23

J23

IO27PB1F2

G16

C18

C17

B19

B18

D19

C19

F17

F10

IO28NB1F2

IO28PB1F2

IO29NB1F2

J24

IO29PB1F2

H24

K21

K22

K25

J25

D10

E10

IO30NB1F2

IO30PB1F2

IO31NB1F2

IO31PB1F2

E17

B20

A20

B22

B21

D20

C20

D21

C21

D22

C22

F19

F11

G11

D11

E11

B10

C10

A10

IO32NB1F3

L20

L21

K26

J26

IO32PB1F3

IO33NB1F3

IO33PB1F3

IO34NB1F3

L23

L22

L24

K24

M20

M21

L26

L25

IO34PB1F3

IO35NB1F3

IO35PB1F3

F12

G12

C12

C11

IO36NB1F3

IO36PB1F3

IO37NB1F3

IO37PB1F3

E19

v2.7

3-37

Axcelerator Family FPGAs

676-Pin FBGA

AX500 Function

IO57NB2F5

IO57PB2F5

IO58NB2F5

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO60NB2F5

IO60PB2F5

IO61NB2F5

IO61PB2F5

IO62NB2F5

IO62PB2F5

Pin Number

AX500 Function

Pin Number

Y23

Pin Number

AC17

AC18

AD18

AD19

AA16

Y16

M23

M22

M26

M25

N22

N23

N24

M24

N20

N21

P25

IO76NB3F7

IO76PB3F7

IO77NB3F7

IO77PB3F7

IO78NB3F7

IO78PB3F7

IO79NB3F7

IO79PB3F7

IO80NB3F7

IO80PB3F7

IO81NB3F7

IO81PB3F7

IO82NB3F7

IO82PB3F7

IO83NB3F7

IO83PB3F7

IO95NB4F9

IO95PB4F9

W23

V21

IO96NB4F9

U21

IO96PB4F9

AB25

AA25

AC26

AB26

AC24

AB24

AB23

AA23

AA22

Y22

IO97NB4F9

IO97PB4F9

IO98NB4F9

AE17

AE18

AC16

AB16

AF17

IO98PB4F9

IO99NB4F9

IO99PB4F9

IO100NB4F9

N25

IO100PB4F9

AF18

Bank 3

IO101NB4F9

AA15

Y15

IO63NB3F6

IO63PB3F6

IO64NB3F6

IO64PB3F6

IO65NB3F6

IO65PB3F6

IO66NB3F6

IO66PB3F6

IO67NB3F6

IO67PB3F6

IO68NB3F6

IO68PB3F6

IO69NB3F6

IO69PB3F6

IO70NB3F6

IO70PB3F6

IO71NB3F6

IO71PB3F6

IO72NB3F6

IO72PB3F6

IO73NB3F6

IO73PB3F6

IO74NB3F7

IO74PB3F7

IO75NB3F7

IO75PB3F7

T26

R26

R24

P24

IO101PB4F9

AE26

AD26

IO102NB4F9

AC15

AB15

AE16

AF16

IO102PB4F9

Bank 4

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

P20

IO84NB4F8

IO84PB4F8

IO85NB4F8

IO85PB4F8

IO86NB4F8

IO86PB4F8

IO87NB4F8

IO87PB4F8

IO88NB4F8

IO88PB4F8

IO89NB4F8

IO89PB4F8

IO90NB4F8

IO90PB4F8

IO91NB4F8

IO91PB4F8

IO92NB4F8

IO92PB4F8

IO93NB4F8

IO93PB4F8

IO94NB4F9

IO94PB4F9

AB21

AA21

AE23

AE24

AC21

AC22

AF22

AF23

AD22

AD23

AC19

AC20

AE21

AE22

AA17

AA18

AD20

AD21

AF20

AF21

AE19

AE20

P21

AE14

AE15

T25

R25

T23

IO105NB5F10/CLKGN

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO108NB5F10

IO108PB5F10

IO109NB5F10

IO109PB5F10

IO110NB5F10

IO110PB5F10

IO111NB5F10

IO111PB5F10

IO112NB5F10

IO112PB5F10

IO113NB5F10

IO113PB5F10

AE12

AE13

AE11

AF11

Y12

R23

V26

U26

V25

U25

Y25

W25

W24

V24

V23

U23

T21

AA13

AC12

AB12

AC10

AC11

AF9

AF10

Y11

T20

AA12

AE9

AA26

Y26

AA24

Y24

AE10

AC9

AD9

3-38

v2.7

Axcelerator Family FPGAs

676-Pin FBGA

AX500 Function

Pin Number

AF6

AX500 Function

Pin Number

AX500 Function

Pin Number

IO114NB5F11

IO114PB5F11

IO115NB5F11

IO115PB5F11

IO116NB5F11

IO116PB5F11

IO117NB5F11

IO117PB5F11

IO118NB5F11

IO118PB5F11

IO119NB5F11

IO119PB5F11

IO120NB5F11

IO120PB5F11

IO121NB5F11

IO121PB5F11

IO122NB5F11

IO122PB5F11

IO123NB5F11

IO123PB5F11

IO124NB5F11

IO124PB5F11

IO125NB5F11

IO125PB5F11

IO133NB6F12

IO133PB6F12

IO134NB6F12

IO134PB6F12

IO135NB6F12

IO135PB6F12

IO136NB6F13

IO136PB6F13

IO137NB6F13

IO137PB6F13

IO138NB6F13

IO138PB6F13

IO139NB6F13

IO139PB6F13

IO140NB6F13

IO140PB6F13

IO141NB6F13

IO141PB6F13

IO142NB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO144NB6F13

IO144PB6F13

IO145NB6F13

IO145PB6F13

IO146NB6F13

IO146PB6F13

IO152NB7F14

IO152PB7F14

IO153NB7F14

IO153PB7F14

IO154NB7F14

IO154PB7F14

IO155NB7F14

IO155PB7F14

IO156NB7F14

IO156PB7F14

IO157NB7F14

IO157PB7F14

IO158NB7F15

IO158PB7F15

IO159NB7F15

IO159PB7F15

IO160NB7F15

IO160PB7F15

IO161NB7F15

IO161PB7F15

IO162NB7F15

IO162PB7F15

IO163NB7F15

IO163PB7F15

IO164NB7F15

IO164PB7F15

IO165NB7F15

IO165PB7F15

IO166NB7F15

IO166PB7F15

IO167NB7F15

IO167PB7F15

AF7

AA10

AB10

AE7

AE8

AD7

AD8

AC7

AC8

AD6

AE6

AE5

AF5

AF4

AE4

AC5

AC6

AD4

AD5

AB6

AB7

AE3

AF3

Bank 6

IO126NB6F12

IO126PB6F12

IO127NB6F12

IO127PB6F12

IO128NB6F12

IO128PB6F12

IO129NB6F12

IO129PB6F12

IO130NB6F12

IO130PB6F12

IO131NB6F12

IO131PB6F12

IO132NB6F12

IO132PB6F12

AB3

AC3

AA2

AB2

AC2

AD2

Bank 7

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO149NB7F14

IO149PB7F14

IO150NB7F14

IO150PB7F14

IO151NB7F14

IO151PB7F14

AA1

Dedicated I/O

GND

A13

A14

A19

A26

AA3

v2.7

3-39

Axcelerator Family FPGAs

676-Pin FBGA

AX500 Function

GND

Pin Number

AX500 Function

Pin Number

L16

AX500 Function

Pin Number

T11

AC23

AC4

AD24

AD3

AE2

AE25

AF1

AF13

AF14

AF19

AF26

AF8

GND

GND/LP

L17

T12

M10

M11

M12

M13

M14

M15

M16

M17

T13

T14

T15

T16

T17

U10

U11

U12

U13

U14

U15

U16

U17

V18

N10

N11

N12

N13

N14

N15

N16

N17

N26

B25

B26

C24

G20

W19

W26

H19

H26

P10

Y20

P11

J18

P12

P13

A11

A21

A22

A24

A25

AA11

AA19

AA20

AA4

AA5

AA6

AA7

AA8

AA9

AB1

K10

K11

K12

K13

K14

K15

K16

K17

L10

P14

P15

P16

P17

P26

R10

R11

R12

R13

R14

R15

R16

R17

T10

L11

L12

L13

L14

L15

3-40

v2.7

Axcelerator Family FPGAs

676-Pin FBGA

AX500 Function

676-Pin FBGA

Pin Number

AB11

AB17

AB18

AB19

AB20

AB8

AB9

AC1

AC13

AC14

AC25

AD1

AD11

AD16

AD25

AE1

AX500 Function

Pin Number

AX500 Function

Pin Number

PRA

E13

B14

Y14

AD14

F18

F20

F21

F22

F23

F24

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

V_CCA

AB4

AF24

G21

G22

H21

H22

H23

C26

J10

J11

AF2

J12

AF25

B11

J13

J14

B24

J15

P22

R20

R21

R22

J16

C16

J17

K18

D13

D14

D17

D18

L18

T22

T24

U22

U24

V22

M18

N18

D26

P18

W21

W22

Y21

R18

E18

E23

T18

E24

E26

U18

V10

v2.7

3-41

Axcelerator Family FPGAs

676-Pin FBGA

AX500 Function

676-Pin FBGA

AX500 Function

V_CCA

Pin Number

K20

L19

AX500 Function

Pin Number

V11

V12

V13

V14

V15

V16

V17

V_CCIB2

V_CCIB7

V_CCA

V_CCIB2

M19

N19

P19

R19

T19

U19

U20

V19

V20

W20

W14

W15

W16

W17

W18

Y17

Y18

Y19

W10

W11

W12

W13

_CCIB7

V_CCA

V_CCIB2

V_CCIB3

V_CCIB4

V_CCIB5

V_CCIB6

V_CCIB7

V_CCPLA

V_CCPLB

V_CCA

E12

V_CCA

F13

V_CCDA

V_CCIB0

V_CCIB1

V_CCPLC

V_CCPLD

V_CCPLE

E15

AB22

AB5

AD10

AD13

AD17

G14

AF15

AA14

AF12

AB13

D12

V_CCPLF

V_CCPLG

V_CCPLH

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

B17

D24

E14

G13

D15

F14

AD15

AB14

AD12

Y13

P23

G10

E22

H10

H11

H12

H13

Y10

G17

G18

G19

H14

H15

H16

H17

H18

H20

J19

V_CCIB1

V_CCIB6

V_CCIB1

V_CCIB6

V_CCIB1

V_CCIB6

V_CCIB1

V_CCIB2

V_CCIB6

V_CCIB7

J20

V_CCIB2

K19

V_CCIB7

3-42

v2.7

Axcelerator Family FPGAs

676-Pin FBGA

AX1000 Function Pin Number

Bank 0

IO00NB0F0

676-Pin FBGA

AX1000 Function

Pin Number

D11

AX1000 Function

Pin Number

D19

C19

D20

C20

B22

IO24NB0F2

IO24PB0F2

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

E11

IO00PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO16NB0F1

IO16PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO26NB0F2

C12

IO26PB0F2

C11

IO28NB0F2

F12

IO28PB0F2

G12

B21

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

A12

D21

C21

F19

B12

C13

B13

E19

B23

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO35NB1F3

C15

C14

A15

B15

B16

A16

F15

A23

D22

C22

B24

A24

E21

IO35PB1F3

IO36NB1F3

E20

IO36PB1F3

G15

F16

D23

C23

F21

IO38NB1F3

IO38PB1F3

G16

A18

A17

C18

C17

D16

E16

D18

D17

B19

B18

B20

A20

F17

IO40NB1F3

F20

IO40PB1F3

Bank 2

IO41NB1F4

IO64NB2F6

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

H21

G21

G22

F22

F24

F23

E24

E23

H23

H22

D25

C25

G24

G23

F25

E25

IO41PB1F4

IO42NB1F4

IO42PB1F4

F10

IO44NB1F4

IO44PB1F4

IO45NB1F4

A10

D10

E10

B10

C10

F11

G11

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO48NB1F4

IO48PB1F4

E17

A22

A21

E18

F18

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

v2.7

3-43

Axcelerator Family FPGAs

676-Pin FBGA

AX1000 Function

IO72NB2F6

IO72PB2F6

IO73NB2F6

IO73PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO80NB2F7

IO80PB2F7

IO81NB2F7

IO81PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO84NB2F7

IO84PB2F7

IO86NB2F8

IO86PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

Pin Number

AX1000 Function

IO95PB2F8

Bank 3

Pin Number

AA25

W22

G26

F26

E26

D26

J21

N25

IO119PB3F11

IO120NB3F11

IO120PB3F11

IO121NB3F11

IO121PB3F11

IO122NB3F11

IO122PB3F11

IO123NB3F11

IO123PB3F11

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO126NB3F11

IO126PB3F11

IO127NB3F11

IO127PB3F11

IO128NB3F11

IO128PB3F11

IO98NB3F9

IO98PB3F9

P20

P21

V22

Y23

IO99NB3F9

R24

P24

W23

J22

IO99PB3F9

AA24

Y24

J24

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

IO103NB3F9

IO103PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

IO107PB3F10

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO110NB3F10

IO110PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO118NB3F11

IO118PB3F11

IO119NB3F11

R22

P22

H24

K23

J23

AE26

AD26

Y21

T26

R26

R21

R20

T25

H25

G25

K25

J25

W21

AD25

AC25

AB23

AA23

AC24

AB24

AA22

Y22

R25

V26

U26

T23

K21

K22

K26

J26

R23

U24

T24

L24

K24

L23

L22

L20

L21

L26

L25

M23

M22

M26

M25

M20

M21

N24

M24

N22

N23

N20

N21

P25

Bank 4

U22

T22

IO129NB4F12

IO129PB4F12

IO131NB4F12

IO131PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO134NB4F12

IO134PB4F12

IO135NB4F12

IO135PB4F12

IO137NB4F12

IO137PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

AB21

AA21

AD22

AD23

AE23

AE24

AB20

AA20

AC21

AC22

AF22

AF23

AB19

AA19

AC19

AC20

AE21

AE22

AD20

V25

U25

T21

T20

V23

U23

Y25

W25

V21

U21

W24

V24

AA26

Y26

AC26

AB26

AB25

3-44

v2.7

Axcelerator Family FPGAs

676-Pin FBGA

AX1000 Function

676-Pin FBGA

AX1000 Function

Pin Number

AD21

AB17

AB18

AE19

AE20

AC17

AC18

AD18

AD19

AA17

AA18

AF20

AF21

AA16

Y16

Pin Number

AA12

AF9

AX1000 Function

Pin Number

AA6

IO141PB4F13

IO143NB4F13

IO143PB4F13

IO167PB5F15

IO168NB5F15

IO168PB5F15

IO169NB5F15

IO169PB5F15

IO171NB5F16

IO171PB5F16

IO173NB5F16

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO176NB5F16

IO176PB5F16

IO177NB5F16

IO177PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO184PB5F17

IO185NB5F17

IO185PB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO189NB5F17

IO189PB5F17

IO190NB5F17

IO190PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

AA7

AF10

AB11

AA11

AE9

Bank 6

IO144NB4F13

IO144PB4F13

IO193NB6F18

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO199NB6F18

IO199PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO202PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO211NB6F19

IO211PB6F19

AA5

AB3

AC3

IO145NB4F13

IO145PB4F13

AE10

AC10

AC11

AE7

IO146NB4F13

IO146PB4F13

AA4

AC2

AD2

IO147NB4F13

IO147PB4F13

AE8

IO148NB4F13

IO148PB4F13

AC9

AD9

AF6

IO149NB4F13

IO149PB4F13

AD1

AE1

AA2

AB2

AF7

IO151NB4F13

IO151PB4F13

AC16

AB16

AE17

AE18

AF17

AF18

AA15

Y15

AA10

AB10

AD7

AD8

AC7

AC8

AA9

AB9

IO153NB4F14

IO153PB4F14

AA3

IO154NB4F14

IO154PB4F14

AB1

AC1

IO155NB4F14

IO155PB4F14

IO157NB4F14

IO157PB4F14

AC15

AB15

AE16

AF16

AE14

AE15

AD6

AE6

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

AE5

AF5

AA8

AB8

AC5

AC6

AD4

AD5

AB6

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

IO163PB5F15

AE12

AE13

AE11

AF11

AC12

AB12

Y12

AB7

AA1

AF4

IO165NB5F15

IO165PB5F15

AE4

AA13

Y11

AE3

IO167NB5F15

AF3

v2.7

3-45

Axcelerator Family FPGAs

676-Pin FBGA

AX1000 Function

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO214NB6F20

IO214PB6F20

IO215NB6F20

IO215PB6F20

IO217NB6F20

IO217PB6F20

IO218NB6F20

IO218PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO223NB6F20

IO223PB6F20

Bank 7

Pin Number

AX1000 Function

Pin Number

A14

A19

A26

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO238PB7F22

IO240NB7F22

IO240PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO243NB7F22

IO243PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO248PB7F23

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO251NB7F23

IO251PB7F23

IO253NB7F23

IO253PB7F23

IO254NB7F23

IO254PB7F23

IO255NB7F23

IO255PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

GND

AC23

AC4

AD24

AD3

AE2

AE25

AF1

AF13

AF14

AF19

AF26

AF8

B25

B26

C24

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO229NB7F21

IO229PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

IO236PB7F22

G20

H19

H26

J18

K10

K11

K12

K13

K14

K15

K16

K17

L10

Dedicated I/O

GND

A13

L11

3-46

v2.7

Axcelerator Family FPGAs

676-Pin FBGA

AX1000 Function

Pin Number

L12

AX1000 Function

Pin Number

R15

AX1000 Function

Pin Number

GND

GND/LP

TCK

TDI

L13

R16

L14

R17

TDO

L15

T10

TMS

L16

T11

TRST

V_CCA

L17

T12

AB4

AF24

M10

M11

M12

M13

M14

M15

M16

M17

T13

T14

T15

C26

J10

T16

T17

J11

U10

U11

U12

U13

U14

U15

U16

U17

V18

J12

J13

J14

J15

N10

N11

N12

N13

N14

N15

N16

N17

N26

J16

J17

K18

L18

M18

W19

W26

N18

P10

Y20

P18

P11

P12

R18

P13

A25

AC13

AC14

AF2

P14

T18

P15

P16

U18

P17

AF25

D13

D14

E13

P26

V10

V11

V12

V13

V14

V15

R10

R11

R12

R13

R14

PRA

PRB

B14

PRC

Y14

AD14

PRD

v2.7

3-47

Axcelerator Family FPGAs

676-Pin FBGA

AX1000 Function

676-Pin FBGA

AX1000 Function

V_CCA

Pin Number

H15

H16

H17

H18

H20

J19

AX1000 Function

Pin Number

V16

V17

E12

V_CCIB1

V_CCIB6

V_CCA

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_CCDA

V_CCIB0

V_CCIB1

_CCIB6

F13

V_CCIB1

V_CCIB2

V_CCIB3

V_CCIB4

V_CCIB5

V_CCIB6

E15

G14

AF15

AA14

AF12

AB13

A11

V_CCIB7

J20

V_CCIB7

K19

K20

L19

V_CCIB7

M19

N19

P19

V_CCIB7

AB22

AB5

AD10

AD11

AD13

AD16

AD17

V_CCIB7

R19

T19

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

D12

G13

D15

F14

AD15

AB14

AD12

Y13

E22

U19

U20

V19

V20

W20

W14

W15

W16

W17

W18

Y17

Y18

Y19

W10

W11

W12

W13

B11

B17

C16

D24

E14

P23

G10

V_CCIB0

H10

H11

H12

H13

V_CCIB5

V_CCIB0

V_CCIB5

V_CCIB0

V_CCIB5

Y10

V_CCIB0

V_CCIB1

V_CCIB5

V_CCIB6

G17

G18

G19

H14

V_CCIB1

V_CCIB6

3-48

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

A1 Ball Pad Corner

30 29 28 2726 25 24 23 22 21 20 1918 17 16 1514 13 12 11 10 9 8 7 6 5 4 3 2 1

Figure 3-7 • 896-Pin FBGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v2.7

3-49

Axcelerator Family FPGAs

896-Pin FBGA

AX1000 Function

Bank 0

Pin Number

AX1000 Function

Pin Number

E11

Pin Number

B19

A19

H18

J18

IO18PB0F1

IO19NB0F1

IO37NB1F3

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO39NB1F3

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F4

IO41PB1F4

IO42NB1F4

IO42PB1F4

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

IO47PB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO53NB1F4

IO53PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

C12

C11

F12

IO19PB0F1

IO20NB0F1

IO20PB0F1

G12

D12

E12

B20

A20

C20

C19

E20

IO21NB0F1

IO21PB0F1

IO22NB0F2

H13

J13

IO22PB0F2

IO23NB0F2

A12

A11

F13

E19

IO23PB0F2

F18

IO24NB0F2

G18

A22

A21

F20

IO24PB0F2

G13

B13

IO25NB0F2

IO25PB0F2

B12

IO26NB0F2

E14

F19

IO26PB0F2

E13

D21

D20

D22

C22

A25

A24

H19

G19

C24

C23

G20

H20

F21

IO27NB0F2

B14

IO27PB0F2

A14

H14

J14

IO28NB0F2

IO28PB0F2

H10

G10

IO29NB0F2

B15

IO29PB0F2

A15

C14

D14

E15

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

E10

F10

D10

D15

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO34NB1F3

E17

E16

C17

D17

A17

B17

D18

C18

H17

J17

F11

G11

A10

E21

F22

E22

B25

B24

D24

D23

F23

H12

H11

B11

B10

D11

IO34PB1F3

IO35NB1F3

IO35PB1F3

IO36NB1F3

IO36PB1F3

E23

3-50

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

AX1000 Function

Pin Number

H21

AX1000 Function

Pin Number

L24

AX1000 Function

Pin Number

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO81NB2F7

IO81PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO84NB2F7

IO84PB2F7

IO85NB2F8

IO85PB2F8

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

R30

R22

R23

T27

R27

G21

D25

L26

K26

M25

L25

C25

F24

E24

K27

J27

Bank 3

D26

IO96NB3F9

IO96PB3F9

T29

T30

C26

M27

L27

G23

G22

B27

IO97NB3F9

U29

U30

T22

K30

K29

M23

M24

M28

L28

IO97PB3F9

IO98NB3F9

A27

IO98PB3F9

T23

F25

IO99NB3F9

U26

T26

E25

IO99PB3F9

H23

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

IO103NB3F9

IO103PB3F9

IO104NB3F9

IO104PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

IO107PB3F10

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO110NB3F10

IO110PB3F10

IO111NB3F10

IO111PB3F10

U24

T24

H22

N26

M26

N25

N24

N22

N23

M29

L29

Bank 2

V28

U28

U23

U22

V27

U27

W29

V29

Y28

W28

V25

U25

W26

V26

W24

V24

Y27

W27

V23

V22

AA29

Y29

IO64NB2F6

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

IO72NB2F6

IO72PB2F6

IO73NB2F6

IO73PB2F6

IO74NB2F7

K23

J23

J24

H24

H26

H25

G26

G25

K25

K24

F27

E27

J26

N28

N27

P29

P30

P25

P24

P28

J25

P27

H27

G27

J28

P22

P23

R26

P26

H28

G28

F28

L23

R24

R25

R29

v2.7

3-51

Axcelerator Family FPGAs

896-Pin FBGA

AX1000 Function

896-Pin FBGA

AX1000 Function

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO119NB3F11

IO119PB3F11

IO120NB3F11

IO120PB3F11

IO121NB3F11

IO121PB3F11

IO122NB3F11

IO122PB3F11

IO123NB3F11

IO123PB3F11

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO126NB3F11

IO126PB3F11

IO127NB3F11

IO127PB3F11

IO128NB3F11

IO128PB3F11

Bank 4

Pin Number

AK27

AF24

Pin Number

AB18

AK21

AJ21

Y25

W25

IO130PB4F12

IO131NB4F12

IO131PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO134NB4F12

IO134PB4F12

IO135NB4F12

IO135PB4F12

IO136NB4F12

IO136PB4F12

IO137NB4F12

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

IO141PB4F13

IO142NB4F13

IO142PB4F13

IO143NB4F13

IO143PB4F13

IO144NB4F13

IO144PB4F13

IO145NB4F13

IO145PB4F13

IO146NB4F13

IO146PB4F13

IO147NB4F13

IO147PB4F13

IO148NB4F13

IO148PB4F13

IO149NB4F13

IO149PB4F13

IO150NB4F13

IO150PB4F13

AB27

AA27

Y23

AF25

AG25

AG26

AD22

AC22

AE23

AE24

AH24

AH25

AJ25

IO151NB4F13

IO151PB4F13

AE18

AD18

AJ20

W23

IO152NB4F14

IO152PB4F14

AA26

Y26

AK20

AG19

AG20

AH19

AH20

AC17

AB17

AK19

AJ19

IO153NB4F14

IO153PB4F14

AC28

AB28

AE29

AD29

AE28

AD28

AD27

AC27

AA24

Y24

IO154NB4F14

IO154PB4F14

IO155NB4F14

IO155PB4F14

AJ26

AD21

AC21

AK24

AK25

AE21

AE22

AG23

AG24

AF22

IO156NB4F14

IO156PB4F14

IO157NB4F14

IO157PB4F14

AE17

AD17

AJ17

IO158NB4F14

IO158PB4F14

AB25

AA25

AC26

AB26

AG28

AF28

AB23

AA23

AF27

AE27

AD25

AC25

AE26

AD26

AC24

AB24

AJ18

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

AG18

AH18

AG16

AG17

AF23

AJ23

AJ24

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

IO163PB5F15

AG14

AG15

AG13

AH13

AE14

AD14

AJ12

AD19

AD20

AG21

AG22

AE19

AE20

AF20

IO164NB5F15

IO164PB5F15

AJ13

AF21

IO165NB5F15

IO165PB5F15

AB14

AC15

AK11

AK12

AB13

AC14

AC19

AC20

AH22

AH23

AC18

IO166NB5F15

IO166PB5F15

IO129NB4F12

IO129PB4F12

IO130NB4F12

AD23

AC23

AK26

IO167NB5F15

IO167PB5F15

3-52

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

AX1000 Function

896-Pin FBGA

Pin Number

AH11

AH12

AD13

AC13

AJ10

AJ11

AG11

AG12

AK9

AX1000 Function

Pin Number

AE7

AX1000 Function

Pin Number

IO168NB5F15

IO168PB5F15

IO169NB5F15

IO169PB5F15

IO170NB5F15

IO170PB5F15

IO171NB5F16

IO171PB5F16

IO172NB5F16

IO172PB5F16

IO173NB5F16

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO176NB5F16

IO176PB5F16

IO177NB5F16

IO177PB5F16

IO178NB5F16

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO182NB5F17

IO182PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO184PB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO189NB5F17

IO189PB5F17

IO190NB5F17

IO190PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO210NB6F19

IO210PB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO214NB6F20

IO214PB6F20

IO215NB6F20

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO218NB6F20

IO218PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO222NB6F20

IO222PB6F20

IO223NB6F20

IO223PB6F20

IO224NB6F20

AE8

AA4

AB4

AB3

AC3

AF6

AF7

AD8

AD9

AH6

AG6

AG5

AK10

AE12

AE13

AG9

AH5

AA2

AA1

AC8

AC9

Bank 6

AG10

AE11

AF11

AH8

IO193NB6F18

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO199NB6F18

IO199PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO202PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

AB7

AC7

AD5

AE5

AB6

AC6

AE4

AF4

AA8

AB8

AF3

AG3

AC4

AD4

AB5

AC5

AH9

AC12

AD12

AJ7

AJ8

AF9

AF10

AE9

AE10

AC11

AD11

AK6

AK7

AF8

AA7

AD3

AE3

AG8

AG7

AH7

AC10

AD10

AJ5

AA6

AA5

AJ6

v2.7

3-53

Axcelerator Family FPGAs

896-Pin FBGA

AX1000 Function

IO224PB6F20

Bank 7

Pin Number

AX1000 Function

Pin Number

AA21

AA28

AA3

IO243NB7F22

IO243PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO248PB7F23

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO251NB7F23

IO251PB7F23

IO252NB7F23

IO252PB7F23

IO253NB7F23

IO253PB7F23

IO254NB7F23

IO254PB7F23

IO255NB7F23

IO255PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

GND

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO228NB7F21

IO228PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

IO236PB7F22

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO238PB7F22

IO239NB7F22

IO239PB7F22

IO240NB7F22

IO240PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

AB2

AB22

AB29

AB9

AC1

AC30

AE25

AE6

AF26

AF5

AG27

AG4

AH10

AH15

AH16

AH21

AH28

AH3

AJ1

AJ2

AJ22

AJ29

AJ30

AJ9

AK13

AK18

AK2

Dedicated I/O

AK23

AK29

AK8

GND

A13

A18

A23

A29

B22

B29

AA10

B30

3-54

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

AX1000 Function

Pin Number

N17

N18

N19

N30

P12

P13

P14

P15

P16

P17

P18

P19

R12

R13

R14

R15

R16

R17

R18

R19

R28

AX1000 Function

Pin Number

U18

GND

GND/LP

C10

C15

C16

C21

C28

U19

V12

V13

V14

V15

D27

D28

V16

V17

V18

E26

V19

V30

W12

W13

W14

W15

W16

W17

W18

W19

Y11

H30

J22

J29

K10

K21

K28

Y20

L11

T12

T13

T14

T15

T16

T17

T18

T19

T28

L20

A16

M12

M13

M14

M15

M16

M17

M18

M19

A26

AA30

AB1

AB30

AC2

AC29

AD1

AD2

AD30

AE1

U12

U13

U14

U15

U16

U17

N12

N13

N14

N15

N16

AE15

AE16

v2.7

3-55

Axcelerator Family FPGAs

896-Pin FBGA

AX1000 Function

Pin Number

AX1000 Function

Pin Number

AX1000 Function

Pin Number

L13

AE2

AE30

AF1

V_CCA

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

V_CCPLG

E29

E30

F15

F16

F29

F30

L14

L15

AF2

L16

AF29

AF30

AG1

AG2

AG29

AG30

AH27

AH4

AJ14

AJ15

AJ16

AJ27

AJ4

L17

L18

L19

M11

M20

N11

N20

P11

G29

G30

H29

J30

P20

R11

R20

L30

M30

N29

T11

T20

AK14

AK15

AK16

AK17

AK22

AK4

AK5

B16

U11

U20

V11

V20

W11

W20

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

G14

H15

G17

J16

W30

Y30

G15

D16

AB16

AF16

PRA

PRB

PRC

PRD

TCK

TDI

B18

B21

B23

B26

TDO

TMS

TRST

V_CCA

C27

AD6

AH26

E28

D29

D30

AH17

AC16

AH14

L12

3-56

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

AX1000 Function

896-Pin FBGA

Pin Number

AD15

AD24

AD7

AF12

AF13

AF15

AF18

AF19

C13

AX1000 Function

V_CCIB2

_CCIB2

Pin Number

C29

AX1000 Function

V_CCIB5

_CCIB5

Pin Number

AJ3

V_CCPLH

V_CCDA

V_CCIB0

C30

AK3

AA9

AH1

AH2

T10

V_CCIB2

K22

V_CCIB6

L21

L22

_CCIB2

M21

V_CCIB6

V_CCIB2

M22

V_CCIB6

U10

V10

W10

N21

_CCIB2

P21

V_CCIB6

V_CCIB2

V_CCIB3

R21

V_CCIB6

D13

D19

AA22

AH29

AH30

T21

Y10

_CCIB3

V_CCIB6

V_CCIB3

V_CCIB7

E18

F26

_CCIB3

U21

_CCIB7

G16

T25

V_CCIB3

V21

V_CCIB7

L10

W21

W22

Y21

_CCIB3

_CCIB7

M10

V_CCIB3

V_CCIB7

Y22

N10

P10

V_CCIB0

J10

_CCIB4

AA16

AA17

AA18

AA19

AA20

AB19

AB20

AB21

AJ28

AK28

AA11

AA12

AA13

AA14

AA15

AB10

AB11

AB12

V_CCIB7

V_CCIB0

J11

V_CCIB4

V_CCIB7

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

R10

F14

J12

V_CCIB0

K11

K12

K13

K14

K15

A28

B28

J19

V_CCIB4

J15

V_CCIB0

V_CCIB4

F17

V_CCIB0

V_CCIB4

H16

AF17

AD16

AF14

AB15

G24

V_CCIB1

V_CCIB4

_CCIB1

_CCIB4

_CCIB5

V_CCIB1

J20

V_CCIB5

_CCIB1

J21

_CCIB5

K16

K17

K18

K19

K20

V_CCIB1

V_CCIB5

_CCIB1

_CCIB5

v2.7

3-57

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function

Bank 0

Pin Number

AX2000 Function

Pin Number

AX2000 Function

Pin Number

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO23NB0F2

IO23PB0F2

IO25NB0F2

IO25PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

IO28PB0F2

IO30NB0F2

IO30PB0F2

IO31NB0F2

IO31PB0F2

IO33NB0F2

IO33PB0F2

IO34NB0F3

IO34PB0F3

IO37NB0F3

IO37PB0F3

IO38NB0F3

IO38PB0F3

IO39NB0F3

IO39PB0F3

IO40NB0F3

IO40PB0F3

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

E15

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

D11

E11

D15

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO45NB1F4

E17

E16

C17

D17

A16

B16

H17

J17

H12

H11

A10

F12

IO45PB1F4

G12

B11

B10

D12

E12

IO47NB1F4

IO47PB1F4

IO48NB1F4

A17

B17

H18

J18

IO48PB1F4

IO49NB1F4

C12

C11

A12

A11

F13

IO49PB1F4

IO51NB1F4

F18

G18

B18

D18

C18

H19

G19

B19

A19

E20

E19

C20

C19

B20

A20

F20

F19

A22

A21

IO51PB1F4

IO52NB1F4

IO53NB1F4

G13

H13

J13

IO53PB1F4

IO55NB1F5

H10

G10

IO55PB1F5

B13

B12

E14

IO56NB1F5

IO56PB1F5

IO57NB1F5

E10

F10

F11

G11

E13

IO57PB1F5

B14

A14

H14

J14

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

B15

A15

C14

D14

IO61NB1F5

D10

IO61PB1F5

IO62NB1F5

IO62PB1F5

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

3-58

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function

896-Pin FBGA

Pin Number

D21

D20

G20

H20

B23

AX2000 Function

Pin Number

AX2000 Function

Pin Number

L24

IO63NB1F5

IO63PB1F5

IO65NB1F6

IO65PB1F6

IO66NB1F6

IO66PB1F6

IO67NB1F6

IO67PB1F6

IO68NB1F6

IO68PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO70PB1F6

IO71NB1F6

IO71PB1F6

IO73NB1F6

IO73PB1F6

IO74NB1F6

IO74PB1F6

IO75NB1F6

IO75PB1F6

IO76NB1F7

IO76PB1F7

IO78NB1F7

IO78PB1F7

IO79NB1F7

IO79PB1F7

IO80NB1F7

IO80PB1F7

IO81NB1F7

IO81PB1F7

IO82NB1F7

IO82PB1F7

IO83NB1F7

IO83PB1F7

IO84NB1F7

IO84PB1F7

IO85NB1F7

IO85PB1F7

F24

E24

D26

C26

F25

E25

IO99PB2F9

IO100NB2F9

IO100PB2F9

IO101PB2F9

IO102NB2F9

IO102PB2F9

IO103NB2F9

IO103PB2F9

IO104NB2F9

IO105NB2F9

IO105PB2F9

IO106NB2F9

IO106PB2F9

IO107NB2F10

IO107PB2F10

IO109NB2F10

IO109PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

IO118NB2F11

IO119NB2F11

IO119PB2F11

K27

J27

J30

E30

B21

D30

L26

H21

G21

D22

C22

A25

A24

F22

Bank 2

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

IO96NB2F9

IO96PB2F9

IO97NB2F9

IO97PB2F9

IO98NB2F9

IO98PB2F9

IO99NB2F9

G26

G25

K23

J23

K26

F29

M25

L25

J24

K30

K29

M23

M24

M27

L27

H24

E29

D29

F27

E27

H26

H25

G28

F28

J26

E22

F21

E21

C24

C23

D24

D23

H23

H22

B25

M28

L28

N22

N23

M29

L29

J25

B24

H27

G27

H29

G29

G30

F30

K25

K24

J28

N26

M26

M30

L30

B26

A26

F23

E23

N28

N27

N25

N24

N29

P22

D25

C25

G23

G22

B27

H28

L23

A27

P23

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

v2.7

3-59

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function

IO121NB2F11

IO121PB2F11

IO122NB2F11

IO122PB2F11

IO123NB2F11

IO123PB2F11

IO124NB2F11

IO124PB2F11

IO125NB2F11

IO125PB2F11

IO127NB2F11

IO127PB2F11

IO128NB2F11

IO128PB2F11

Bank 3

Pin Number

AX2000 Function

Pin Number

U25

Pin Number

AB25

AA25

AE30

P25

P24

P28

P27

R26

P26

P29

P30

R22

R23

R24

R25

R29

R30

IO139PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO143NB3F13

IO143PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

IO150NB3F14

IO150PB3F14

IO151NB3F14

IO152NB3F14

IO152PB3F14

IO153NB3F14

IO153PB3F14

IO154NB3F14

IO154PB3F14

IO155NB3F14

IO155PB3F14

IO156NB3F14

IO156PB3F14

IO157NB3F14

IO157PB3F14

IO158NB3F14

IO158PB3F14

IO159NB3F14

IO159PB3F14

IO160NB3F14

IO160PB3F14

IO161NB3F15

IO161PB3F15

IO162NB3F15

IO162PB3F15

IO163NB3F15

IO163PB3F15

IO164NB3F15

IO164PB3F15

IO165NB3F15

IO165PB3F15

IO166NB3F15

IO166PB3F15

IO167NB3F15

IO167PB3F15

IO168NB3F15

IO168PB3F15

IO169NB3F15

IO169PB3F15

IO170NB3F15

IO170PB3F15

V23

V22

W29

V29

AD30

AE29

W26

V26

AD29

AD27

AC27

AC26

AB26

AE28

W24

V24

W27

W28

Y28

AD28

AC24

AB24

AG28

AF28

Y27

Y30

W30

Y25

IO129NB3F12

IO129PB3F12

IO130NB3F12

IO130PB3F12

IO131NB3F12

IO131PB3F12

IO132NB3F12

IO132PB3F12

IO133NB3F12

IO133PB3F12

IO135NB3F12

IO135PB3F12

IO136NB3F12

IO136PB3F12

IO137NB3F12

IO137PB3F12

IO138NB3F12

IO138PB3F12

IO139NB3F13

T27

R27

T29

T30

T22

T23

U26

T26

U24

T24

U23

U22

U29

U30

V28

U28

V27

U27

V25

W25

AA29

Y29

AE26

AD26

AD25

AC25

AF27

AC29

AA26

Y26

AE27

Y23

AB23

AA23

W23

AB30

AA30

AB27

AA27

AC28

AB28

AA24

Y24

Bank 4

IO171NB4F16

IO171PB4F16

IO172NB4F16

IO172PB4F16

IO173NB4F16

IO173PB4F16

IO174NB4F16

IO174PB4F16

IO175NB4F16

AG29

AG30

AF24

AF25

AG25

AG26

AJ25

AF29

AF30

AJ26

AK26

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

3-60

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function

896-Pin FBGA

AX2000 Function

Pin Number

AK27

AE23

AE24

AH24

AH25

AD23

AC23

AJ27

Pin Number

AD20

AJ20

AX2000 Function

Pin Number

AC15

AK15

AJ15

IO175PB4F16

IO176NB4F16

IO176PB4F16

IO177NB4F16

IO177PB4F16

IO178NB4F16

IO178PB4F16

IO179PB4F16

IO180NB4F16

IO180PB4F16

IO181NB4F17

IO181PB4F17

IO182NB4F17

IO182PB4F17

IO183NB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO187NB4F17

IO187PB4F17

IO188NB4F17

IO188PB4F17

IO189PB4F17

IO190NB4F17

IO190PB4F17

IO191NB4F17

IO191PB4F17

IO192NB4F17

IO192PB4F17

IO195NB4F18

IO195PB4F18

IO196NB4F18

IO196PB4F18

IO197NB4F18

IO216PB5F20

IO217NB5F20

IO217PB5F20

IO218NB5F20

IO218PB5F20

IO219NB5F20

IO219PB5F20

IO222NB5F20

IO222PB5F20

IO223NB5F21

IO223PB5F21

IO225NB5F21

IO225PB5F21

IO226NB5F21

IO226PB5F21

IO227NB5F21

IO227PB5F21

IO228NB5F21

IO228PB5F21

IO229NB5F21

IO229PB5F21

IO230NB5F21

IO230PB5F21

IO232NB5F21

IO232PB5F21

IO233NB5F21

IO233PB5F21

IO234NB5F21

IO234PB5F21

IO236NB5F22

IO236PB5F22

IO237NB5F22

IO237PB5F22

IO238NB5F22

IO197PB4F18

AK20

AC19

AC20

AG19

AG20

AH19

AH20

AK19

AJ19

IO198NB4F18

AE14

AD14

AK14

AJ14

IO198PB4F18

IO199NB4F18

IO199PB4F18

IO200NB4F18

AB13

AC14

AJ12

AG23

AG24

AK24

AK25

AD22

AC22

AF22

IO200PB4F18

IO201NB4F18

IO201PB4F18

AJ13

IO202NB4F18

AC18

AB18

AE18

AD18

AJ17

AH11

AH12

AC13

AD13

AE12

AE13

AG11

AG12

AK11

AK12

AC12

AD12

AE11

AF11

AJ10

IO202PB4F18

IO206NB4F19

IO206PB4F19

AF23

IO207NB4F19

AE21

AE22

AJ23

IO207PB4F19

AJ18

IO208NB4F19

AE17

AD17

AK17

AC17

AB17

AJ16

IO208PB4F19

AJ24

IO209NB4F19

AH22

AH23

AD21

AC21

AK22

AF20

IO210NB4F19

IO210PB4F19

IO211NB4F19

IO211PB4F19

AK16

AG18

AH18

AG16

AG17

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

AF21

AJ11

AG21

AG22

AE19

AE20

AK21

AJ21

AC11

AD11

AK9

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO216NB5F20

AG14

AG15

AG13

AH13

AB14

AK10

AG9

AG10

AF9

AD19

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

v2.7

3-61

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function Pin Number

Bank 6

IO257NB6F24

896-Pin FBGA

AX2000 Function

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO240PB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

IO245NB5F23

IO245PB5F23

IO246NB5F23

IO246PB5F23

IO247NB5F23

IO247PB5F23

IO248NB5F23

IO249NB5F23

IO249PB5F23

IO250NB5F23

IO250PB5F23

IO251NB5F23

IO251PB5F23

IO252NB5F23

IO252PB5F23

IO253NB5F23

IO253PB5F23

IO254NB5F23

IO254PB5F23

IO255NB5F23

IO255PB5F23

IO256NB5F23

IO256PB5F23

Pin Number

AE2*

AF10

AH8

AH9

AC10

AD10

AE9

AE10

AJ7

IO273PB6F25

IO274NB6F25

IO274PB6F25

IO275NB6F25

IO275PB6F25

IO277NB6F25

IO277PB6F25

IO278NB6F26

IO278PB6F26

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO288NB6F26

IO288PB6F26

IO290NB6F27

IO290PB6F27

IO291NB6F27

IO291PB6F27

IO292NB6F27

IO292PB6F27

IO293NB6F27

AE4

AF4

AB7

AC7

AD5

AE5

AF1

AF2

AF3

AG3

AC4

AD4

AD3

AE3

AB6

AC6

AD1

AE1

AA8

AB8

AB5

AC5

AB3

AC3

AC2

AD2

IO257PB6F24

IO258NB6F24

IO258PB6F24

IO259NB6F24

IO259PB6F24

IO260NB6F24

IO260PB6F24

IO261NB6F24

IO261PB6F24

IO262NB6F24

IO262PB6F24

IO263NB6F24

IO263PB6F24

IO264NB6F24

IO264PB6F24

IO265NB6F24

IO265PB6F24

IO266NB6F24

IO266PB6F24

IO267NB6F25

IO267PB6F25

IO268NB6F25

IO268PB6F25

IO269NB6F25

IO269PB6F25

IO270NB6F25

IO270PB6F25

IO271NB6F25

IO271PB6F25

IO272NB6F25

IO272PB6F25

IO273NB6F25

AA5

AA2

AA1

AJ8

AK6

AK7

AF8

AG8

AD8

AD9

AG7

AH7

AK5

AJ5

AJ6

AC8

AC9

AH6

AG6

AF6

AF7

AG2

AG1

AE7

AE8

AG5

AH5

AJ4

AA7

AA4

AB4

AA6

AB1*

AK4

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

3-62

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function

Pin Number

AX2000 Function

Pin Number

AX2000 Function

Pin Number

IO293PB6F27

IO294NB6F27

IO294PB6F27

IO296NB6F27

IO296PB6F27

IO298NB6F27

IO298PB6F27

IO299NB6F27

IO299PB6F27

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

IO320PB7F29

IO321NB7F30

IO321PB7F30

IO322NB7F30

IO322PB7F30

IO323NB7F30

IO323PB7F30

IO324NB7F30

IO324PB7F30

IO326NB7F30

IO326PB7F30

IO327NB7F30

IO327PB7F30

IO328NB7F30

IO328PB7F30

IO329NB7F30

IO329PB7F30

IO330NB7F30

IO330PB7F30

IO331NB7F30

IO331PB7F30

IO332NB7F31

IO332PB7F31

IO333NB7F31

IO333PB7F31

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO336NB7F31

IO336PB7F31

IO337NB7F31

IO337PB7F31

IO338NB7F31

IO338PB7F31

IO339NB7F31

IO339PB7F31

IO340NB7F31

IO340PB7F31

IO341NB7F31

IO341PB7F31

Bank 7

IO300NB7F28

IO300PB7F28

IO302NB7F28

IO302PB7F28

IO303NB7F28

IO303PB7F28

IO304NB7F28

IO304PB7F28

IO306NB7F28

IO306PB7F28

IO307NB7F28

IO307PB7F28

IO308NB7F28

IO308PB7F28

IO309NB7F28

IO309PB7F28

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO313NB7F29

IO313PB7F29

Dedicated I/O

GND

A13

A18

G1*

K2*

A23

A29

AA10

AA21

AA28

AA3

AB2

AB22

AB29

AB9

AC1

AC30

AE25

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

v2.7

3-63

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function

GND

Pin Number

AX2000 Function

Pin Number

N19

N30

P12

P13

P14

P15

P16

P17

P18

P19

R12

R13

R14

R15

R16

R17

R18

R19

R28

AE6

AF26

AF5

GND

D27

D28

AG27

AG4

AH10

AH15

AH16

AH21

AH28

AH3

AJ1

E26

H30

J22

J29

AJ2

K10

K21

K28

AJ22

AJ29

AJ30

AJ9

L11

AK13

AK18

AK2

AK23

AK29

AK8

L20

M12

M13

M14

M15

M16

M17

M18

M19

T12

T13

T14

T15

T16

T17

T18

T19

T28

B22

B29

B30

N12

N13

N14

N15

N16

N17

N18

C10

C15

C16

C21

C28

U12

U13

U14

U15

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

3-64

v2.7

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function

896-Pin FBGA

AX2000 Function

Pin Number

U16

U17

U18

U19

Pin Number

AD6

AH26

E28

AX2000 Function

Pin Number

Y18

Y19

AD24

AD7

AE15

AE16

AF12

AF13

AF15

AF18

AF19

AH27

AH4

C13

C27

GND

GND/LP

PRA

V_CCA

V_CCDA

L12

V12

V13

V14

V15

V16

V17

V18

V19

V30

W12

W13

W14

W15

W16

W17

W18

W19

Y11

Y20

L13

L14

L15

L16

L17

L18

L19

M11

M20

N11

N20

P11

D13

D19

P20

R11

R20

E18

T11

F15

T20

F16

U11

U20

V11

V20

W11

W20

Y12

Y13

Y14

Y15

Y16

Y17

F26

G16

T25

G15

D16

AB16

AF16

PRB

_CCIB0

PRC

PRD

V_CCIB0

J10

TCK

_CCIB0

J11

TDI

J12

TDO

TMS

TRST

V_CCIB0

K11

K12

K13

_CCIB0

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

v2.7

3-65

Axcelerator Family FPGAs

896-Pin FBGA

AX2000 Function

V_CCIB4

896-Pin FBGA

AX2000 Function

Pin Number

AA18

AA19

AA20

AB19

AB20

AB21

AJ28

AK28

AA11

AA12

AA13

AA14

AA15

AB10

AB11

AB12

AJ3

AX2000 Function

V_CCIB7

Pin Number

V_CCIB0

K14

K15

A28

B28

_CCIB0

_CCIB1

_CCIB4

_CCIB7

N10

P10

V_CCIB1

V_CCIB4

V_CCIB7

V_CCPLA

R10

_CCIB1

J19

_CCIB4

G14

J20

V_CCPLB

H15

V_CCIB1

J21

V_CCIB4

V_CCPLC

G17

_CCIB1

K16

K17

K18

K19

K20

C29

C30

K22

L21

_CCIB4

_CCIB5

V_CCPLD

J16

V_CCPLE

AH17

AC16

AH14

AD15

F14

V_CCIB1

V_CCIB5

V_CCPLF

_CCIB1

_CCIB5

V_CCPLG

V_CCPLH

V_CCIB2

V_CCIB5

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

_CCIB2

_CCIB5

J15

F17

V_CCIB2

V_CCIB5

H16

_CCIB2

L22

_CCIB5

_CCIB6

AF17

AD16

AF14

AB15

G24

M21

M22

N21

P21

AK3

AA9

V_CCIB2

V_CCIB6

AH1

_CCIB2

_CCIB6

AH2

R21

T10

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

V_CCIB3

AA22

AH29

AH30

T21

V_CCIB6

U10

_CCIB3

_CCIB6

V10

W10

V_CCIB3

V_CCIB6

_CCIB3

U21

V21

W21

W22

Y21

Y22

AA16

AA17

_CCIB6

Y10

V_CCIB3

V_CCIB7

_CCIB3

_CCIB7

V_CCIB3

V_CCIB7

L10

_CCIB4

_CCIB7

M10

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

3-66

v2.7

Axcelerator Family FPGAs

1152-Pin FBGA

A1 Ball Pad Corner

34 33 32 31 3029 282726 25 2423 2221 20 1918 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Figure 3-8 • 1152-Pin FBGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v2.7

3-67

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

Bank 0

Pin Number

AX2000 Function

Pin Number

F13

AX2000 Function

Pin Number

C16

IO19NB0F1

IO19PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO23NB0F2

IO23PB0F2

IO24NB0F2

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

IO28PB0F2

IO29NB0F2

IO29PB0F2

IO30NB0F2

IO30PB0F2

IO31NB0F2

IO31PB0F2

IO32NB0F2

IO32PB0F2

IO33NB0F2

IO33PB0F2

IO34NB0F3

IO34PB0F3

IO35NB0F3

IO35PB0F3

IO36NB0F3

IO36PB0F3

IO37NB0F3

IO37PB0F3

IO38NB0F3

IO38PB0F3

IO39NB0F3

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

G13

A10

K16

IO39PB0F3

L16

H10

IO40NB0F3

D17

K14

K13

B11

B10

C12

C11

A12

A11

H14

J14

IO40PB0F3

C17

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

E16

F16

G17

F17

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO45NB1F4

G19

G18

E19

F19

C18

D18

A18

B18

K19

L19

C19

D19

K20

L20

A19

B19

H20

J20

K10

J10

D13

D12

F14

F10

G10

IO45PB1F4

IO46NB1F4

G14

E14

IO46PB1F4

IO47NB1F4

J11

K11

E13

IO47PB1F4

B13

B12

C14

C13

H15

J15

IO48NB1F4

IO48PB1F4

IO49NB1F4

K12

J12

G11

H11

G12

H12

IO49PB1F4

IO50NB1F4

IO50PB1F4

A14

B14

K15

L15

IO51NB1F4

IO51PB1F4

IO52NB1F4

B20

A20

F20

E20

B21

A21

K21

J21

IO52PB1F4

D15

D14

A15

B15

B16

A16

G16

G15

D16

IO53NB1F4

H13

J13

IO53PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

F12

F11

E11

E10

IO55PB1F5

IO56NB1F5

D21

C21

G22

IO56PB1F5

IO57NB1F5

3-68

v2.7

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

1152-Pin FBGA

Pin Number

G21

E22

AX2000 Function

Pin Number

B29

AX2000 Function

Pin Number

J32

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

IO64NB1F6

IO64PB1F6

IO65NB1F6

IO65PB1F6

IO66NB1F6

IO66PB1F6

IO67NB1F6

IO67PB1F6

IO68NB1F6

IO68PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO70PB1F6

IO71NB1F6

IO71PB1F6

IO72NB1F6

IO72PB1F6

IO73NB1F6

IO73PB1F6

IO74NB1F6

IO74PB1F6

IO75NB1F6

IO75PB1F6

IO76NB1F7

IO76PB1F7

IO77NB1F7

IO77PB1F7

IO78NB1F7

IO78PB1F7

IO79NB1F7

IO79PB1F7

IO80NB1F7

IO80PB1F7

IO81NB1F7

IO81PB1F7

IO82NB1F7

IO82PB1F7

IO83NB1F7

IO83PB1F7

IO84NB1F7

IO84PB1F7

IO85NB1F7

IO85PB1F7

IO96NB2F9

IO96PB2F9

A29

D28

C28

H25

G25

F27

H32

M27

M26

L30

E21

IO97NB2F9

D22

C22

B23

A23

H22

H21

C24

C23

F23

IO97PB2F9

IO98NB2F9

IO98PB2F9

K30

N25

N26

M29

L29

IO99NB2F9

E27

IO99PB2F9

J25

IO100NB2F9

IO100PB2F9

IO101NB2F9

IO101PB2F9

IO102NB2F9

IO102PB2F9

IO103NB2F9

IO103PB2F9

IO104NB2F9

IO104PB2F9

IO105NB2F9

IO105PB2F9

IO106NB2F9

IO106PB2F9

IO107NB2F10

IO107PB2F10

IO108NB2F10

IO108PB2F10

IO109NB2F10

IO109PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

J24

D29

C29

H26

G26

F28

L33

L32

F22

K34

K33

N28

M28

M34

L34

B24

A24

J22

E28

K22

B25

A25

K23

J23

H27

G27

Bank 2

P27

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

J28

J27

N27

M32

M31

P25

F24

M25

L25

L26

K26

G31

F31

H29

G29

K28

K27

J30

E24

C27

C26

H24

G24

H23

G23

B28

A28

E26

P26

N33

M33

P29

N29

P30

N30

R24

R25

E25

H30

L28

L27

K29

J29

P31

F26

N31

R28

F25

K25

K24

D27

D26

P28

P32

K31

J31

N32

R30

v2.7

3-69

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

IO115PB2F10

IO116NB2F10

IO116PB2F10

IO117NB2F10

IO117PB2F10

IO118NB2F11

IO118PB2F11

IO119NB2F11

IO119PB2F11

IO120NB2F11

IO120PB2F11

IO121NB2F11

IO121PB2F11

IO122NB2F11

IO122PB2F11

IO123NB2F11

IO123PB2F11

IO124NB2F11

IO124PB2F11

IO125NB2F11

IO125PB2F11

IO126NB2F11

IO126PB2F11

IO127NB2F11

IO127PB2F11

IO128NB2F11

IO128PB2F11

Bank 3

Pin Number

AX2000 Function

Pin Number

V33

Pin Number

AD32

AC32

AD29

AC29

AE30

AD30

AC26

AB26

AH33

AG33

AD27

AC27

AG32

AF32

R29

P34

P33

R27

R26

R34

R33

T24

T25

T33

T34

T27

T26

T30

T29

U28

T28

T31

T32

U24

U25

U33

U34

U26

U27

U31

U32

IO134PB3F12

IO135NB3F12

IO135PB3F12

IO136NB3F12

IO136PB3F12

IO137NB3F12

IO137PB3F12

IO138NB3F12

IO138PB3F12

IO139NB3F13

IO139PB3F13

IO140NB3F13

IO140PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO143NB3F13

IO143PB3F13

IO144NB3F13

IO144PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

IO150NB3F14

IO150PB3F14

IO151NB3F14

IO151PB3F14

IO152NB3F14

IO152PB3F14

IO153NB3F14

IO153PB3F14

IO154NB3F14

IO154PB3F14

IO155NB3F14

IO155PB3F14

IO156NB3F14

IO156PB3F14

IO157NB3F14

IO157PB3F14

IO158NB3F14

IO158PB3F14

IO159NB3F14

IO159PB3F14

IO160NB3F14

IO160PB3F14

IO161NB3F15

IO161PB3F15

IO162NB3F15

IO162PB3F15

IO163NB3F15

IO163PB3F15

IO164NB3F15

IO164PB3F15

IO165NB3F15

IO165PB3F15

IO166NB3F15

IO166PB3F15

IO167NB3F15

IO167PB3F15

IO168NB3F15

IO168PB3F15

IO169NB3F15

IO169PB3F15

IO170NB3F15

IO170PB3F15

W25

W24

W31

W32

Y30

W30

Y29

W29

Y27

W27

AA33

Y33

Y25

Y24

AG31

AF31

AA31

Y31

AF29

AA28

Y28

AE29

AE28

AD28

AG30

AF30

AA34

Y34

AA26

Y26

AE26

AD26

AJ30

AA29

AA30

AB30

AB29

AB32

AA32

AB27

AA27

AC31

AB31

AD33

AC33

AC28

AB28

AB25

AA25

AH30

AG28

AF28

IO129NB3F12

IO129PB3F12

IO130NB3F12

IO130PB3F12

IO131NB3F12

IO131PB3F12

IO132NB3F12

IO132PB3F12

IO133NB3F12

IO133PB3F12

IO134NB3F12

V29

U29

V31

V32

V24

V25

W28

V28

W26

V26

W33

AF27

AE27

AH29

AG29

AD25

AC25

Bank 4

IO171NB4F16

IO171PB4F16

IO172NB4F16

IO172PB4F16

AP29

AN29

AH26

AH27

3-70

v2.7

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

Pin Number

AJ27

Pin Number

AG22

AP23

AP24

AN22

AN23

AM23

AL23

AF21

AF22

AL22

AM22

AE21

AE22

AJ21

AX2000 Function

Pin Number

AJ20

IO173NB4F16

IO173PB4F16

IO174NB4F16

IO174PB4F16

IO175NB4F16

IO175PB4F16

IO176NB4F16

IO176PB4F16

IO177NB4F16

IO177PB4F16

IO178NB4F16

IO178PB4F16

IO179NB4F16

IO179PB4F16

IO180NB4F16

IO180PB4F16

IO181NB4F17

IO181PB4F17

IO182NB4F17

IO182PB4F17

IO183NB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO186NB4F17

IO186PB4F17

IO187NB4F17

IO187PB4F17

IO188NB4F17

IO188PB4F17

IO189NB4F17

IO189PB4F17

IO190NB4F17

IO190PB4F17

IO191NB4F17

IO191PB4F17

IO192NB4F17

IO192PB4F17

IO193NB4F18

IO193PB4F18

IO194NB4F18

IO194PB4F18

IO195NB4F18

IO195PB4F18

IO196NB4F18

IO196PB4F18

IO197NB4F18

IO197PB4F18

IO198NB4F18

IO198PB4F18

IO199NB4F18

IO199PB4F18

IO200NB4F18

IO200PB4F18

IO201NB4F18

IO201PB4F18

IO202NB4F18

IO202PB4F18

IO203NB4F19

IO203PB4F19

IO204NB4F19

IO204PB4F19

IO205NB4F19

IO205PB4F19

IO206NB4F19

IO206PB4F19

IO207NB4F19

IO207PB4F19

IO208NB4F19

IO208PB4F19

IO209NB4F19

IO209PB4F19

IO210NB4F19

IO210PB4F19

IO211NB4F19

IO211PB4F19

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

AJ28

AK20

AL27

AJ18

AL28

AJ19

AM28

AM29

AG25

AG26

AK26

AK27

AF25

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO216NB5F20

IO216PB5F20

AJ16

AJ17

AJ15

AK15

AD16

AE17

AM17

AL17

AG16

AF16

AM16

AL16

AP16

AN16

AN15

AP15

AD15

AE16

AL14

AL15

AN14

AP14

AK13

AK14

AE15

AF15

AG14

AG15

AJ13

AE25

AP28

AN28

AJ25

IO217NB5F20

IO217PB5F20

IO218NB5F20

IO218PB5F20

AJ22

AJ26

AK21

AK22

AM21

AL21

AE20

AD20

AN21

AP21

AP20

AN20

AN19

AP19

AG20

AF20

AL19

AL20

AG19

AF19

AN18

AP18

AE19

AD19

AL18

AM18

IO219NB5F20

IO219PB5F20

AM26

AM27

AF24

IO220NB5F20

IO220PB5F20

AE24

AH24

AH25

AG23

AG24

AL25

IO221NB5F20

IO221PB5F20

IO222NB5F20

IO222PB5F20

IO223NB5F21

IO223PB5F21

AL26

IO224NB5F21

IO224PB5F21

AP25

AP26

AK24

AK25

AF23

IO225NB5F21

IO225PB5F21

IO226NB5F21

IO226PB5F21

AE23

AN24

AM24

AH22

AH23

AJ23

IO227NB5F21

IO227PB5F21

IO228NB5F21

IO228PB5F21

AJ14

IO229NB5F21

IO229PB5F21

AM13

AM14

AE14

AF14

AJ24

IO230NB5F21

IO230PB5F21

AG21

v2.7

3-71

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

1152-Pin FBGA

AX2000 Function

IO231NB5F21

IO231PB5F21

IO232NB5F21

IO232PB5F21

IO233NB5F21

IO233PB5F21

IO234NB5F21

IO234PB5F21

IO235NB5F22

IO235PB5F22

IO236NB5F22

IO236PB5F22

IO237NB5F22

IO237PB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO240PB5F22

IO241NB5F22

IO241PB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

IO245NB5F23

IO245PB5F23

IO246NB5F23

IO246PB5F23

IO247NB5F23

IO247PB5F23

IO248NB5F23

IO248PB5F23

IO249NB5F23

IO249PB5F23

IO250NB5F23

Pin Number

AE11

AK8

AX2000 Function

Pin Number

AF4

AN12

AP12

AG13

AH13

AL12

AL13

AE13

AF13

AN11

AP11

AM11

AM12

AJ11

AJ12

AH11

AH12

AK10

AK11

AE12

AF12

AN10

AP10

AG11

AG12

AL9

IO250PB5F23

IO251NB5F23

IO251PB5F23

IO252NB5F23

IO252PB5F23

IO253NB5F23

IO253PB5F23

IO254NB5F23

IO254PB5F23

IO255NB5F23

IO255PB5F23

IO256NB5F23

IO256PB5F23

IO269PB6F25

IO270NB6F25

IO270PB6F25

IO271NB6F25

IO271PB6F25

IO272NB6F25

IO272PB6F25

IO273NB6F25

IO273PB6F25

IO274NB6F25

IO274PB6F25

IO275NB6F25

IO275PB6F25

IO276NB6F25

IO276PB6F25

IO277NB6F25

IO277PB6F25

IO278NB6F26

IO278PB6F26

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO283NB6F26

IO283PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO288NB6F26

IO288PB6F26

AB9

AC9

AC6

AD6

AB8

AC8

AE1

AJ8

AH8

AH9

AN6

AP6

AG9

AG10

AJ7

AE2

AA10

AB10

AB7

AC7

AD1

AD2

AC4

AC3

AA8

AA9

AB5

AB6

Y10

AK7

AL6

AM6

Bank 6

IO257NB6F24

IO257PB6F24

IO258NB6F24

IO258PB6F24

IO259NB6F24

IO259PB6F24

IO260NB6F24

IO260PB6F24

IO261NB6F24

IO261PB6F24

IO262NB6F24

IO262PB6F24

IO263NB6F24

IO263PB6F24

IO264NB6F24

IO264PB6F24

IO265NB6F24

IO265PB6F24

IO266NB6F24

IO266PB6F24

IO267NB6F25

IO267PB6F25

IO268NB6F25

IO268PB6F25

IO269NB6F25

AG6

AH6

AD9

AE9

AF7

AG7

AH3

AH4

AH5

AJ5

Y11

AB3

AB4

AE6

AF6

AL10

AM8

AM9

AH10

AJ10

AF10

AF11

AJ9

AF5

AA7

AC2

AC1

AG5

AD8

AE8

AF3

AG3

AC10

AD10

AD7

AE7

AD5

AE5

AE4

AA5

AA6

W10

W11

AA3

AA4

AK9

AN7

AP7

AL7

AL8

AE10

3-72

v2.7

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

1152-Pin FBGA

AX2000 Function

Pin Number

AA1

AA2

Pin Number

T11

T10

AX2000 Function

Pin Number

IO289NB6F27

IO289PB6F27

IO290NB6F27

IO290PB6F27

IO291NB6F27

IO291PB6F27

IO292NB6F27

IO292PB6F27

IO293NB6F27

IO293PB6F27

IO294NB6F27

IO294PB6F27

IO295NB6F27

IO295PB6F27

IO296NB6F27

IO296PB6F27

IO297NB6F27

IO297PB6F27

IO298NB6F27

IO298PB6F27

IO299NB6F27

IO299PB6F27

IO308NB7F28

IO308PB7F28

IO309NB7F28

IO309PB7F28

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO313NB7F29

IO313PB7F29

IO314NB7F29

IO314PB7F29

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO319NB7F29

IO319PB7F29

IO320NB7F29

IO320PB7F29

IO321NB7F30

IO321PB7F30

IO322NB7F30

IO322PB7F30

IO323NB7F30

IO323PB7F30

IO324NB7F30

IO324PB7F30

IO325NB7F30

IO325PB7F30

IO326NB7F30

IO326PB7F30

IO327NB7F30

IO327PB7F30

IO328NB7F30

IO328PB7F30

IO329NB7F30

IO329PB7F30

IO330NB7F30

IO330PB7F30

IO331NB7F30

IO331PB7F30

IO332NB7F31

IO332PB7F31

IO333NB7F31

IO333PB7F31

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO336NB7F31

IO336PB7F31

IO337NB7F31

IO337PB7F31

IO338NB7F31

IO338PB7F31

IO339NB7F31

IO339PB7F31

IO340NB7F31

IO340PB7F31

IO341NB7F31

IO341PB7F31

N10

M10

V10

V11

R10

R11

Bank 7

IO300NB7F28

IO300PB7F28

IO301NB7F28

IO301PB7F28

IO302NB7F28

IO302PB7F28

IO303NB7F28

IO303PB7F28

IO304NB7F28

IO304PB7F28

IO305NB7F28

IO305PB7F28

IO306NB7F28

IO306PB7F28

IO307NB7F28

IO307PB7F28

U10

U11

P10

Dedicated I/O

GND

A13

A22

A27

A31

A32

A33

v2.7

3-73

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

GND

Pin Number

AX2000 Function

Pin Number

AL1

Pin Number

AP33

AP4

AP8

GND

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AB1

AL11

AL2

AL24

AL3

AL31

AL32

AL33

AL34

AL4

B26

B31

B32

B33

B34

AB13

AB22

AB34

AC12

AC23

AC30

AC5

AM1

AM10

AM15

AM2

AM20

AM25

AM3

AM31

AM32

AM33

AM34

AM4

AN1

C10

C15

AD11

AD24

AD31

AD4

C20

C25

C31

C32

C33

C34

AE3

AE32

AF2

AN2

AF33

AG1

AN26

AN3

AG27

AG34

AG8

AN31

AN32

AN33

AN34

AN4

D11

D24

AH28

AH7

D31

D32

D33

D34

AJ29

AJ6

AN9

AP13

AP2

AK12

AK17

AK18

AK23

AK30

AK5

AP22

AP27

AP3

E12

E17

E18

E23

AP31

AP32

3-74

v2.7

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

1152-Pin FBGA

AX2000 Function

Pin Number

E30

Pin Number

R20

R21

AX2000 Function

Pin Number

W21

Y14

GND

GND/LP

F29

F30

Y15

R32

T14

Y16

Y17

G28

T15

Y18

T16

Y19

T17

Y20

H34

T18

Y21

T19

J33

T20

Y32

T21

K32

L11

L24

L31

U14

U15

U16

U17

U18

U19

U20

U21

U30

A17

A26

AB2

AB33

AC34

AD3

AD34

AE31

AE33

AE34

AF1

M12

M23

M30

N13

N22

N34

P14

P15

P16

P17

P18

P19

P20

P21

R14

R15

R16

R17

R18

R19

V14

V15

V16

V17

V18

V19

V20

V21

V30

AF34

AG2

AG4

AH1

AH2

AH31

AH32

AH34

AJ1

W14

W15

W16

W17

W18

W19

W20

AJ2

AJ3

AJ31

AJ32

AJ33

AJ34

AJ4

v2.7

3-75

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

Pin Number

AX2000 Function

Pin Number

AX2000 Function

Pin Number

T13

AL29

AM19

AM7

AN13

AN17

AN25

AN27

AN8

AP17

AP9

B17

B22

B27

V_CCA

V34

T22

V_CCA

U13

U22

V13

V22

W13

W22

Y13

Y22

AF26

AF9

W34

J17

V_CCA

PRA

V_CCA

PRB

F18

V_CCA

PRC

AD18

AH18

V_CCA

PRD

V_CCA

TCK

V_CCA

TDI

V_CCA

TDO

TMS

TRST

V_CCA

L10

V_CCDA

AG17

AG18

AH14

AH15

AH17

AH20

AH21

AK29

AK6

E15

AA13

AA22

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AF8

D10

D20

D23

D25

F32

F33

F34

E29

G32

G33

G34

H31

H33

AK28

G30

F15

F21

N14

N15

N16

N17

N18

N19

N20

N21

P13

G20

H17

H18

H28

J18

J34

V27

_CCIB0

V_CCIB0

_CCIB0

V_CCIB0

_CCIB0

R31

P22

R13

R22

L12

3-76

v2.7

Axcelerator Family FPGAs

1152-Pin FBGA

AX2000 Function

V_CCIB3

AX2000 Function

V_CCIB0

Pin Number

L13

Pin Number

AK34

V23

AX2000 Function

V_CCIB6

Pin Number

Y12

_CCIB0

L14

_CCIB3

_CCIB7

M13

M14

M15

M16

M17

A30

W23

V_CCIB0

_CCIB0

V_CCIB0

V_CCIB3

_CCIB4

V_CCIB4

Y23

V_CCIB7

_CCIB7

V_CCIB7

AC18

AC19

AC20

AC21

AC22

AD21

AD22

AD23

AL30

AM30

AN30

AP30

AC13

AC14

AC15

AC16

AC17

AD12

AD13

AD14

AL5

M11

N11

N12

P11

_CCIB0

_CCIB1

_CCIB4

_CCIB7

V_CCIB1

B30

V_CCIB4

V_CCIB7

_CCIB1

C30

V_CCIB4

_CCIB7

P12

D30

R12

L21

T12

L22

U12

J16

L23

V_CCPLA

V_CCPLB

V_CCIB1

M18

M19

M20

M21

M22

E31

V_CCIB4

K17

_CCIB1

_CCIB4

_CCIB5

V_CCPLC

J19

V_CCPLD

L18

V_CCIB1

V_CCIB5

V_CCPLE

AK19

AE18

AK16

AF17

H16

L17

_CCIB1

_CCIB2

V_CCIB5

V_CCPLF

V_CCPLG

V_CCPLH

E32

E33

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

E34

V_CCIB2

M24

N23

V_CCIB5

H19

K18

_CCIB2

_CCIB5

N24

AM5

AH19

AF18

AH16

AD17

J26

V_CCIB2

P23

V_CCIB5

AN5

_CCIB2

P24

_CCIB5

_CCIB6

AP5

R23

AA11

AA12

AB11

AB12

AC11

AK1

V_CCIB2

T23

V_CCIB6

_CCIB2

_CCIB3

U23

_CCIB6

AA23

AA24

AB23

AB24

AC24

AK31

AK32

AK33

V_CCIB3

V_CCIB6

_CCIB3

_CCIB6

AK2

V_CCIB3

_CCIB3

V_CCIB3

_CCIB3

V_CCIB6

_CCIB6

V_CCIB6

_CCIB6

AK3

AK4

V12

W12

v2.7

3-77

Axcelerator Family FPGAs

208-Pin PQFP

208

208-Pin PQFP

Figure 3-9 • 208-Pin PQFP

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-78

v2.7

Axcelerator Family FPGAs

208-Pin PQFP

AX250 Function Pin Number

Bank 0

IO02NB0F0

208-Pin PQFP

AX250 Function

Pin Number

AX250 Function

Pin Number

IO44NB2F2

IO44PB2F2

131

133

IO77PB5F5/CLKHP

IO78NB5F5

IO78PB5F5

IO86NB5F5

IO87NB5F5

IO87PB5F5

IO88NB5F5

IO88PB5F5

IO89NB5F5

IO89PB5F5

197

198

199

191

192

185

186

IO03NB0F0

IO03PB0F0

Bank 3

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO48NB3F3

IO48PB3F3

IO50NB3F3

IO50PB3F3

IO55NB3F3

IO55PB3F3

IO57NB3F3

IO57PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

180

181

174

175

170

171

165

166

161

162

159

160

Bank 6

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO93NB6F6

IO93PB6F6

IO94PB6F6

IO96NB6F6

IO96PB6F6

IO101NB6F6

IO101PB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

IO16PB1F1

IO24NB1F1

IO24PB1F1

IO26NB1F1

IO26PB1F1

IO27NB1F1

IO27PB1F1

Bank 2

Bank 4

IO29NB2F2

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

134

IO62NB4F4

IO62PB4F4

100

103

101

102

IO29PB2F2

IO30NB2F2

IO63NB4F4

IO30PB2F2

IO63PB4F4

IO31PB2F2

IO64NB4F4

IO32NB2F2

IO64PB4F4

IO32PB2F2

IO72NB4F4

IO34NB2F2

IO72PB4F4

Bank 7

IO34PB2F2

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO110NB7F7

IO110PB7F7

IO112NB7F7

IO112PB7F7

IO39NB2F2

IO39PB2F2

IO40PB2F2

IO41NB2F2

Bank 5

IO41PB2F2

IO76NB5F5/CLKGN

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO43NB2F2

IO43PB2F2

v2.7

3-79

Axcelerator Family FPGAs

208-Pin PQFP

AX250 Function

208-Pin PQFP

AX250 Function

IO117NB7F7

IO117PB7F7

IO119NB7F7

IO119PB7F7

IO121PB7F7

IO122NB7F7

IO122PB7F7

IO123NB7F7

IO123PB7F7

Pin Number

125

136

143

150

155

164

169

173

194

196

201

208

184

183

AX250 Function

Pin Number

GND

GND/LP

PRA

V_CCPLG

V_CCPLH

V_CCIB0

V_CCIB1

193

200

163

172

135

149

112

124

V_CCIB1

V_CCIB2

V_CCIB3

Dedicated I/O

V_CCIB3

V_CCIB4

V_CCDA

GND

_CCIB4

V_CCIB5

PRB

PRC

_CCIB6

PRD

V_CCIB6

V_CCIB7

105

130

157

167

182

202

104

TCK

205

204

203

206

207

TDI

_CCIB7

TDO

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

190

188

179

177

TMS

TRST

V_CCA

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

GND

156

GND

158

GND

118

142

168

195

189

187

178

176

GND

113

119

GND

3-80

v2.7

Axcelerator Family FPGAs

208-Pin PQFP

AX500 Function Pin Number

Bank 0

IO03NB0F0

208-Pin PQFP

AX500 Function

Pin Number

AX500 Function

Pin Number

IO62NB2F5

IO62PB2F5

131

133

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO119NB5F11

IO121NB5F11

IO121PB5F11

IO123NB5F11

IO123PB5F11

IO125NB5F11

IO125PB5F11

Bank 6

198

199

197

191

192

185

186

IO03PB0F0

IO04NB0F0

Bank 3

IO63NB3F6

IO63PB3F6

IO64NB3F6

IO64PB3F6

IO66NB3F6

IO66PB3F6

IO68NB3F6

IO68PB3F6

IO77NB3F7

IO77PB3F7

IO79NB3F7

IO79PB3F7

IO81NB3F7

IO81PB3F7

IO82NB3F7

IO82PB3F7

IO83NB3F7

IO83PB3F7

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO23NB1F2

180

181

174

175

170

171

165

166

161

162

159

160

IO127NB6F12

IO127PB6F12

IO128NB6F12

IO128PB6F12

IO129NB6F12

IO129PB6F12

IO130PB6F12

IO132NB6F12

IO132PB6F12

IO141NB6F13

IO141PB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO145NB6F13

IO145PB6F13

IO146NB6F13

IO146PB6F13

Bank 7

IO23PB1F2

IO37NB1F3

IO37PB1F3

IO39NB1F3

IO39PB1F3

IO41NB1F3

IO41PB1F3

Bank 2

Bank 4

IO43NB2F4

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

134

IO84PB4F8

IO85NB4F8

103

100

101

102

IO43PB2F4

IO44NB2F4

IO86NB4F8

IO44PB2F4

IO86PB4F8

IO45PB2F4

IO87NB4F8

IO46NB2F4

IO87PB4F8

IO46PB2F4

IO101NB4F9

IO48NB2F4

IO101PB4F9

IO48PB2F4

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO150NB7F14

IO150PB7F14

IO152NB7F14

IO152PB7F14

IO57NB2F5

IO57PB2F5

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO105NB5F10/CLKGN

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO61NB2F5

IO61PB2F5

v2.7

3-81

Axcelerator Family FPGAs

208-Pin PQFP

AX500 Function

208-Pin PQFP

AX500 Function

IO161NB7F15

IO161PB7F15

IO163NB7F15

IO163PB7F15

IO165PB7F15

IO166NB7F15

IO166PB7F15

IO167NB7F15

IO167PB7F15

Pin Number

125

143

136

150

155

164

169

173

194

196

201

208

184

183

AX500 Function

Pin Number

GND

GND/LP

PRA

V_CCPLG

V_CCPLH

V_CCIB0

V_CCIB1

200

193

172

163

149

135

124

112

V_CCIB1

V_CCIB2

V_CCIB3

Dedicated I/O

V_CCIB3

V_CCIB4

V_CCDA

GND

_CCIB4

V_CCIB5

PRB

PRC

_CCIB6

PRD

V_CCIB6

V_CCIB7

105

130

157

167

182

202

104

TCK

205

204

203

206

207

TDI

_CCIB7

TDO

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

190

188

179

177

TMS

TRST

V_CCA

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCPLF

GND

158

GND

118

142

156

168

195

189

187

178

176

GND

113

119

GND

3-82

v2.7

Axcelerator Family FPGAs

208-Pin CQFP

208

208-Pin PQFP

Figure 3-10 • 208-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v2.7

3-83

Axcelerator Family FPGAs

208-Pin CQFP

AX250 Function

Bank 0

208-Pin CQFP

AX250 Function

208-Pin CQFP

AX250 Function

Pin #

134

Pin #

IO43PB2F2

IO44NB2F2

IO44PB2F2

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

IO78PB5F5

IO02NB0F0

197

198

199

191

192

185

186

131

IO03NB0F0

133

IO03PB0F0

Bank 3

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO48NB3F3

IO48PB3F3

IO50NB3F3

IO50PB3F3

IO55NB3F3

IO55PB3F3

IO57NB3F3

IO57PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO86NB5F5

IO87NB5F5

IO87PB5F5

IO88NB5F5

IO88PB5F5

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

180

181

174

175

170

171

165

166

161

162

159

160

IO89NB5F5

IO89PB5F5

Bank 6

IO91NB6F6

IO91PB6F6

IO16PB1F1

IO24NB1F1

IO92NB6F6

IO92PB6F6

IO24PB1F1

IO26NB1F1

IO93NB6F6

IO93PB6F6

IO26PB1F1

IO27NB1F1

IO94PB6F6

IO27PB1F1

IO96NB6F6

IO96PB6F6

Bank 2

IO29NB2F2

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

Bank 4

IO101NB6F6

IO101PB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

Bank 7

IO29PB2F2

IO62NB4F4

IO62PB4F4

100

103

101

102

IO30NB2F2

IO30PB2F2

IO63NB4F4

IO31PB2F2

IO63PB4F4

IO32NB2F2

IO64NB4F4

IO32PB2F2

IO64PB4F4

IO34NB2F2

IO72NB4F4

IO34PB2F2

IO72PB4F4

IO39NB2F2

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

IO39PB2F2

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO110NB7F7

IO40PB2F2

IO41NB2F2

IO41PB2F2

IO43NB2F2

IO76NB5F5/CLKGN

3-84

v2.7

Axcelerator Family FPGAs

208-Pin CQFP

AX250 Function

208-Pin CQFP

AX250 Function

Pin #

194

196

201

208

184

183

AX250 Function

V_CCIB0

Pin #

200

163

172

135

149

112

124

IO110PB7F7

IO112NB7F7

IO112PB7F7

IO117NB7F7

IO117PB7F7

IO119NB7F7

IO119PB7F7

IO121PB7F7

IO122NB7F7

IO122PB7F7

IO123NB7F7

IO123PB7F7

GND

_CCIB1

_CCIB2

_CCIB3

_CCIB4

_CCIB5

_CCIB6

_CCIB7

GND

GND/LP

PRA

PRB

PRC

PRD

TCK

205

204

203

206

207

TDI

TDO

TMS

Dedicated I/O

TRST

GND

V_CCA

V_CCDA

V_CCPLA

V_CCPLB

189

187

178

176

V_CCPLC

V_CCPLD

118

142

156

168

195

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

190

188

179

177

104

113

119

125

136

143

150

155

164

169

173

105

130

157

167

182

202

193

158

_CCIB0

v2.7

3-85

Axcelerator Family FPGAs

208 CQFP

AX500 Function

Bank 0

208 CQFP

AX500 Function

IO61PB2F5

208 CQFP

AX500 Function

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO119NB5F11

IO121NB5F11

IO121PB5F11

IO123NB5F11

IO123PB5F11

IO125NB5F11

IO125PB5F11

Bank 6

Pin #

134

Pin #

IO03NB0F0

198

199

197

191

192

185

186

IO62NB2F5

131

IO03PB0F0

IO62PB2F5

133

IO04NB0F0

Bank 3

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

IO63NB3F6

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO63PB3F6

IO64NB3F6

IO64PB3F6

IO66NB3F6

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO23NB1F2

180

181

174

175

170

171

165

166

161

162

159

160

IO66PB3F6

IO68NB3F6

IO68PB3F6

IO77NB3F7

IO77PB3F7

IO127NB6F12

IO127PB6F12

IO128NB6F12

IO128PB6F12

IO129NB6F12

IO129PB6F12

IO130PB6F12

IO132NB6F12

IO132PB6F12

IO141NB6F13

IO141PB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO145NB6F13

IO145PB6F13

IO146NB6F13

IO146PB6F13

Bank 7

IO23PB1F2

IO79NB3F7

IO37NB1F3

IO79PB3F7

IO37PB1F3

IO81NB3F7

IO39NB1F3

IO81PB3F7

IO39PB1F3

IO82NB3F7

IO41NB1F3

IO82PB3F7

IO41PB1F3

IO83NB3F7

Bank 2

IO83PB3F7

IO43NB2F4

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

Bank 4

IO43PB2F4

IO84PB4F8

103

100

101

102

IO44NB2F4

IO85NB4F8

IO44PB2F4

IO86NB4F8

IO45PB2F4

IO86PB4F8

IO46NB2F4

IO87NB4F8

IO46PB2F4

IO87PB4F8

IO48NB2F4

IO101NB4F9

IO101PB4F9

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

IO48PB2F4

IO57NB2F5

IO57PB2F5

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO150NB7F14

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO61NB2F5

IO105NB5F10/CLKGN

3-86

v2.7

Axcelerator Family FPGAs

208 CQFP

AX500 Function

IO150PB7F14

IO152NB7F14

IO152PB7F14

IO161NB7F15

IO161PB7F15

IO163NB7F15

IO163PB7F15

IO165PB7F15

IO166NB7F15

IO166PB7F15

IO167NB7F15

IO167PB7F15

Dedicated I/O

V_CCDA

208 CQFP

AX500 Function

GND

Pin #

173

194

196

201

208

184

183

AX500 Function

V_CCIB0

Pin #

200

163

172

135

149

112

124

GND

_CCIB1

_CCIB2

_CCIB3

_CCIB4

_CCIB5

_CCIB6

_CCIB7

GND

GND/LP

PRA

PRB

PRC

PRD

TCK

205

204

203

206

207

TDI

TDO

TMS

TRST

GND

V_CCA

GND

V_CCA

V_CCPLA

V_CCPLB

189

187

178

176

GND

V_CCA

GND

V_CCA

V_CCPLC

GND

V_CCA

V_CCPLD

GND

V_CCA

V_CCPLE

GND

V_CCA

118

142

156

168

195

V_CCPLF

GND

V_CCA

V_CCPLG

V_CCPLH

GND

V_CCA

GND

V_CCA

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

190

188

179

177

GND

V_CCA

GND

V_CCDA

GND

104

113

119

125

136

143

150

155

164

169

GND

105

130

157

167

182

202

193

GND

158

GND

V_CCIB0

v2.7

3-87

Axcelerator Family FPGAs

352-Pin CQFP

264

263

262

261

Pin 1

Ceramic

Tie Bar

223

222

221

220

219

218

217

216

215

352-Pin CQFP

180

179

178

177

Figure 3-11 • 352-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-88

v2.7

Axcelerator Family FPGAs

352-Pin CQFP

AX250 Function

Bank 0

IO00NB0F0

352-Pin CQFP

AX250 Function

Pin #

271

AX250 Function

Pin #

220

213

214

211

212

207

208

205

206

201

202

199

200

195

196

193

194

187

188

189

190

183

184

181

182

179

180

IO25NB1F1

IO25PB1F1

IO27NB1F1

IO27PB1F1

IO46PB3F3

IO47NB3F3

IO47PB3F3

IO48NB3F3

IO48PB3F3

IO49NB3F3

IO49PB3F3

IO51NB3F3

IO51PB3F3

IO52NB3F3

IO52PB3F3

IO53NB3F3

IO53PB3F3

IO54NB3F3

IO54PB3F3

IO55NB3F3

IO55PB3F3

IO56NB3F3

IO56PB3F3

IO57NB3F3

IO57PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

341

342

343

337

338

335

336

331

332

325

326

323

324

319

320

313

314

272

IO00PB0F0

IO01NB0F0

269

270

IO02NB0F0

Bank 2

IO02PB0F0

IO29NB2F2

IO29PB2F2

IO30NB2F2

IO30PB2F2

IO31NB2F2

IO31PB2F2

IO33NB2F2

IO33PB2F2

IO34NB2F2

IO34PB2F2

IO35NB2F2

IO35PB2F2

IO36NB2F2

IO36PB2F2

IO37NB2F2

IO37PB2F2

IO38NB2F2

IO38PB2F2

IO39NB2F2

IO39PB2F2

IO41NB2F2

IO41PB2F2

IO42NB2F2

IO42PB2F2

IO43NB2F2

IO43PB2F2

IO44NB2F2

IO44PB2F2

261

262

259

260

255

256

249

250

253

254

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO04NB0F0

IO04PB0F0

IO06NB0F0

IO06PB0F0

IO08NB0F0

IO08PB0F0

IO10NB0F0

IO10PB0F0

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

305

306

299

300

289

290

295

296

287

288

283

284

277

278

281

282

275

276

IO16PB1F1

IO17NB1F1

IO17PB1F1

IO18NB1F1

Bank 4

IO18PB1F1

IO62NB4F4

IO62PB4F4

IO64NB4F4

IO64PB4F4

IO65NB4F4

IO65PB4F4

IO66NB4F4

IO66PB4F4

IO67NB4F4

172

173

166

167

170

171

164

165

160

IO20NB1F1

IO20PB1F1

IO22NB1F1

IO22PB1F1

IO23NB1F1

Bank 3

IO23PB1F1

IO45NB3F3

IO45PB3F3

IO46NB3F3

217

218

219

IO24NB1F1

IO24PB1F1

v2.7

3-89

Axcelerator Family FPGAs

352-Pin CQFP

AX250 Function

IO67PB4F4

352-Pin CQFP

AX250 Function

352-Pin CQFP

AX250 Function

Pin #

161

158

159

154

155

152

153

146

147

142

143

136

137

Pin #

IO90PB6F6

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO93NB6F6

IO93PB6F6

IO95NB6F6

IO95PB6F6

IO96NB6F6

IO96PB6F6

IO97NB6F6

IO97PB6F6

IO98NB6F6

IO98PB6F6

IO99NB6F6

IO99PB6F6

IO100NB6F6

IO100PB6F6

IO101NB6F6

IO101PB6F6

IO103NB6F6

IO103PB6F6

IO104NB6F6

IO104PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

Bank 7

IO110PB7F7

IO111NB7F7

IO111PB7F7

IO113NB7F7

IO113PB7F7

IO114NB7F7

IO114PB7F7

IO115NB7F7

IO115PB7F7

IO116NB7F7

IO116PB7F7

IO117NB7F7

IO117PB7F7

IO118NB7F7

IO118PB7F7

IO119NB7F7

IO119PB7F7

IO121NB7F7

IO121PB7F7

IO123NB7F7

IO123PB7F7

IO68NB4F4

IO68PB4F4

IO70NB4F4

IO70PB4F4

IO72NB4F4

IO72PB4F4

IO73NB4F4

IO73PB4F4

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

IO76NB5F5/CLKGN

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

128

129

122

123

112

113

118

119

110

111

106

107

100

101

104

105

IO78PB5F5

IO79NB5F5

IO79PB5F5

Dedicated I/O

IO80NB5F5

GND

IO80PB5F5

IO82NB5F5

IO82PB5F5

IO84NB5F5

IO84PB5F5

IO85NB5F5

IO85PB5F5

IO86NB5F5

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO109NB7F7

IO109PB7F7

IO110NB7F7

IO86PB5F5

IO87NB5F5

IO87PB5F5

IO89NB5F5

IO89PB5F5

Bank 6

3-90

v2.7

Axcelerator Family FPGAs

352-Pin CQFP

AX250 Function

352-Pin CQFP

AX250 Function

Pin #

334

340

345

352

AX250 Function

Pin #

209

233

251

263

279

291

329

339

GND

V_CCA

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

240

246

252

258

264

265

274

280

286

292

298

310

322

330

V_CCA

117

130

131

148

174

268

294

307

308

327

328

312

311

135

134

349

348

347

350

351

V_CCA

V_CCDA

116

132

149

178

221

266

293

309

346

321

333

344

273

285

297

227

239

245

257

185

197

203

215

144

156

168

PRA

PRB

PRC

PRD

TCK

TDI

_CCIB0

_CCIB1

_CCIB2

_CCIB3

_CCIB4

TDO

TMS

TRST

V_CCA

102

114

150

162

175

191

v2.7

3-91

Axcelerator Family FPGAs

352-Pin CQFP

AX250 Function

V_CCIB5

352-Pin CQFP

AX500 Function

Bank 0

IO00PB0F0

352-Pin CQFP

AX500 Function

Pin #

271

IO37NB1F3

IO37PB1F3

IO41NB1F3

IO41PB1F3

V_CCIB5

V_CCIB6

V_CCIB7

108

120

343

341

342

337

338

335

336

331

332

325

326

323

324

319

320

313

314

272

IO03NB0F0

IO03PB0F0

269

270

IO05NB0F0

Bank 2

IO05PB0F0

IO43NB2F4

IO43PB2F4

IO45NB2F4

IO45PB2F4

IO47NB2F4

IO47PB2F4

IO49NB2F4

IO49PB2F4

IO50NB2F4

IO50PB2F4

IO51NB2F4

IO51PB2F4

IO53NB2F5

IO53PB2F5

IO54NB2F5

IO54PB2F5

IO55NB2F5

IO55PB2F5

IO57NB2F5

IO57PB2F5

IO58NB2F5

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO61NB2F5

IO61PB2F5

IO62NB2F5

IO62PB2F5

261

262

259

260

255

256

253

254

247

248

249

250

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO07NB0F0

IO07PB0F0

IO09NB0F0

IO09PB0F0

IO15NB0F1

V_CCPLA

V_CCPLB

317

315

303

301

140

138

126

124

318

316

304

302

141

139

127

125

267

IO15PB0F1

IO17NB0F1

V_CCPLC

IO17PB0F1

V_CCPLD

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO23NB1F2

305

306

299

300

289

290

295

296

287

288

283

284

281

282

277

278

275

276

IO23PB1F2

IO24NB1F2

IO24PB1F2

IO25NB1F2

IO25PB1F2

IO27NB1F2

IO27PB1F2

IO29NB1F2

IO29PB1F2

IO31NB1F2

Bank 3

IO31PB1F2

IO63NB3F6

IO63PB3F6

IO64NB3F6

217

218

219

IO35NB1F3

IO35PB1F3

3-92

v2.7

Axcelerator Family FPGAs

352-Pin CQFP

AX500 Function

352-Pin CQFP

AX500 Function

Pin #

220

213

214

207

208

211

212

205

206

201

202

199

200

193

194

195

196

189

190

187

188

183

184

181

182

179

180

Pin #

161

158

159

154

155

146

147

152

153

142

143

136

137

AX500 Function

Pin #

IO64PB3F6

IO65NB3F6

IO65PB3F6

IO67NB3F6

IO67PB3F6

IO68NB3F6

IO68PB3F6

IO69NB3F6

IO69PB3F6

IO71NB3F6

IO71PB3F6

IO73NB3F6

IO73PB3F6

IO75NB3F7

IO75PB3F7

IO76NB3F7

IO76PB3F7

IO77NB3F7

IO77PB3F7

IO79NB3F7

IO79PB3F7

IO80NB3F7

IO80PB3F7

IO81NB3F7

IO81PB3F7

IO83NB3F7

IO83PB3F7

IO95PB4F9

IO97NB4F9

IO126PB6F12

IO127NB6F12

IO127PB6F12

IO129NB6F12

IO129PB6F12

IO131NB6F12

IO131PB6F12

IO133NB6F12

IO133PB6F12

IO134NB6F12

IO134PB6F12

IO135NB6F12

IO135PB6F12

IO137NB6F13

IO137PB6F13

IO138NB6F13

IO138PB6F13

IO139NB6F13

IO139PB6F13

IO141NB6F13

IO141PB6F13

IO142NB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO145NB6F13

IO145PB6F13

IO146NB6F13

IO146PB6F13

IO97PB4F9

IO99NB4F9

IO99PB4F9

IO100NB4F9

IO100PB4F9

IO101NB4F9

IO101PB4F9

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

IO105NB5F10/CLKGN

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO114NB5F11

IO114PB5F11

IO115NB5F11

IO115PB5F11

IO116NB5F11

IO116PB5F11

IO117NB5F11

IO117PB5F11

IO119NB5F11

IO119PB5F11

IO121NB5F11

IO121PB5F11

IO123NB5F11

IO123PB5F11

IO125NB5F11

IO125PB5F11

Bank 6

128

129

122

123

118

119

112

113

110

111

106

107

104

105

100

101

Bank 4

IO85NB4F8

IO85PB4F8

IO87NB4F8

IO87PB4F8

IO89NB4F8

IO89PB4F8

IO94NB4F9

IO94PB4F9

IO95NB4F9

172

173

170

171

166

167

164

165

160

Bank 7

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO149NB7F14

IO149PB7F14

IO151NB7F14

v2.7

3-93

Axcelerator Family FPGAs

352-Pin CQFP

AX500 Function

IO151PB7F14

IO152NB7F14

IO152PB7F14

IO153NB7F14

IO153PB7F14

IO155NB7F14

IO155PB7F14

IO157NB7F14

IO157PB7F14

IO159NB7F15

IO159PB7F15

IO160NB7F15

IO160PB7F15

IO161NB7F15

IO161PB7F15

IO163NB7F15

IO163PB7F15

IO165NB7F15

IO165PB7F15

IO167NB7F15

IO167PB7F15

Dedicated I/O

GND

352-Pin CQFP

AX500 Function

352-Pin CQFP

AX500 Function

Pin #

334

340

345

352

GND

GND/LP

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

240

246

252

258

264

265

274

280

286

292

298

310

322

330

117

130

131

148

174

268

294

307

308

327

328

312

311

135

134

349

348

347

350

351

PRA

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

V_CCA

GND

102

114

150

162

175

191

GND

3-94

v2.7

Axcelerator Family FPGAs

352-Pin CQFP

AX500 Function

352-Pin CQFP

AX500 Function

V_CCIB5

Pin #

209

233

251

263

279

291

329

339

Pin #

AX1000 Function

Bank 0

IO02NB0F0

Pin #

V_CCA

_CCIB5

_CCIB6

_CCIB7

108

120

341

342

343

337

338

331

332

335

336

325

326

323

324

319

320

313

314

V_CCA

IO02PB0F0

IO03PB0F0

V_CCA

IO04NB0F0

V_CCA

IO04PB0F0

V_CCA

IO08NB0F0

V_CCA

IO08PB0F0

V_CCDA

IO09NB0F0

IO09PB0F0

IO24NB0F2

116

132

149

178

221

266

293

309

346

321

333

344

273

285

297

227

239

245

257

185

197

203

215

144

156

168

V_CCPLA

V_CCPLB

317

315

303

301

140

138

126

124

318

316

304

302

141

139

127

125

267

IO24PB0F2

IO25NB0F2

V_CCPLC

IO25PB0F2

V_CCPLD

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

V_CCPLE

V_CCPLF

V_CCPLG

V_CCPLH

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO38NB1F3

305

306

299

300

295

296

287

288

289

290

281

282

283

284

277

278

275

276

_CCIB0

_CCIB1

_CCIB2

_CCIB3

_CCIB4

IO38PB1F3

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

v2.7

3-95

Axcelerator Family FPGAs

352-Pin CQFP

AX1000 Function

IO61NB1F5

IO61PB1F5

IO63NB1F5

IO63PB1F5

Bank 2

352-Pin CQFP

AX1000 Function

IO97PB3F9

352-Pin CQFP

AX1000 Function

IO134PB4F12

Pin #

271

Pin #

220

213

214

211

212

207

208

205

206

199

200

201

202

195

196

193

194

189

190

183

184

187

188

181

182

179

180

Pin #

161

158

159

154

155

152

153

146

147

142

143

136

137

272

IO99NB3F9

IO136NB4F12

269

IO99PB3F9

IO136PB4F12

270

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO111NB3F10

IO111PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO127NB3F11

IO127PB3F11

IO128NB3F11

IO128PB3F11

Bank 4

IO137NB4F12

IO137PB4F12

IO64NB2F6

IO64PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

Bank 3

259

260

261

262

255

256

253

254

249

250

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO138NB4F12

IO138PB4F12

IO153NB4F14

IO153PB4F14

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO167NB5F15

128

129

122

123

118

119

110

111

112

113

104

105

106

107

IO167PB5F15

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO184PB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

IO130NB4F12

IO130PB4F12

IO131NB4F12

IO131PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO134NB4F12

172

173

170

171

166

167

164

165

160

IO187NB5F17

IO187PB5F17

IO188NB5F17

100

101

IO188PB5F17

IO190NB5F17

IO190PB5F17

IO96NB3F9

IO96PB3F9

IO97NB3F9

217

218

219

IO192NB5F17

IO192PB5F17

Bank 6

3-96

v2.7

Axcelerator Family FPGAs

352-Pin CQFP

AX1000 Function

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO223NB6F20

IO223PB6F20

IO224NB6F20

IO224PB6F20

Bank 7

352-Pin CQFP

AX1000 Function

IO238PB7F22

IO240NB7F22

IO240PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

Dedicated I/O

GND

Pin #

AX1000 Function

Pin #

GND

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

240

246

252

258

264

265

274

280

286

292

298

310

322

330

GND

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO237NB7F22

IO237PB7F22

IO238NB7F22

GND

v2.7

3-97

Axcelerator Family FPGAs

352-Pin CQFP

AX1000 Function

V_CCA

352-Pin CQFP

AX1000 Function

V_CCIB5

AX1000 Function

GND

Pin #

334

340

345

352

Pin #

291

329

339

Pin #

V_CCA

_CCIB5

_CCIB6

_CCIB7

108

120

V_CCA

V_CCDA

130

131

174

268

307

308

312

311

135

134

349

348

347

350

351

V_CCDA

116

117

132

148

149

178

221

266

293

294

309

327

328

346

321

333

344

273

285

297

227

239

245

257

185

197

203

215

144

156

168

V_CCDA

PRA

V_CCDA

V_CCPLA

V_CCPLB

317

315

303

301

140

138

126

124

318

316

304

302

141

139

127

125

267

PRB

V_CCDA

PRC

V_CCDA

V_CCPLC

PRD

V_CCDA

V_CCPLD

TCK

V_CCDA

V_CCPLE

TDI

V_CCDA

V_CCPLF

TDO

V_CCDA

V_CCPLG

V_CCPLH

TMS

V_CCDA

TRST

V_CCA

V_CCDA

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

_CCIB0

_CCIB1

_CCIB2

_CCIB3

_CCIB4

102

114

150

162

175

191

209

233

251

263

279

3-98

v2.7

Axcelerator Family FPGAs

352-Pin CQFP

AX2000 Function Pin Number

Bank 0

IO01NB0F0

352-Pin CQFP

AX2000 Function Pin Number

Bank 2

IO87NB2F8

AX2000 Function

Pin Number

208

IO142PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

IO161NB3F15

IO161PB3F15

IO163NB3F15

IO163PB3F15

IO165NB3F15

IO165PB3F15

IO167NB3F15

IO167PB3F15

341

342

343

337

338

335

336

331

332

325

326

323

324

319

320

313

314

261

262

255

256

259

260

253

254

249

250

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

199

IO01PB0F0

IO02PB0F0

IO87PB2F8

IO88NB2F8

200

201

IO04NB0F0

IO88PB2F8

202

IO04PB0F0

IO89NB2F8

193

IO05NB0F0

IO89PB2F8

194

IO05PB0F0

IO91NB2F8

195

IO08NB0F0

IO91PB2F8

196

IO08PB0F0

IO99NB2F9

189

IO37NB0F3

IO99PB2F9

190

IO37PB0F3

IO100NB2F9

IO100PB2F9

IO107NB2F10

IO107PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

183

IO38NB0F3

184

IO38PB0F3

187

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

188

181

182

179

180

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO48NB1F4

305

306

299

300

295

296

283

284

289

290

287

288

275

276

281

282

277

278

269

270

271

272

Bank 4

IO181NB4F17

IO181PB4F17

172

173

170

171

166

167

164

165

160

161

158

159

154

155

152

153

146

147

142

143

136

IO182NB4F17

IO182PB4F17

IO48PB1F4

IO183NB4F17

IO183PB4F17

IO65NB1F6

IO65PB1F6

IO184NB4F17

IO184PB4F17

IO66NB1F6

IO66PB1F6

IO185NB4F17

IO185PB4F17

IO68NB1F6

Bank 3

IO68PB1F6

IO129NB3F12

IO129PB3F12

IO132NB3F12

IO132PB3F12

IO137NB3F12

IO137PB3F12

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

219

220

217

218

213

214

211

212

205

206

207

IO190NB4F17

IO190PB4F17

IO69NB1F6

IO69PB1F6

IO191NB4F17

IO191PB4F17

IO70NB1F6

IO70PB1F6

IO192NB4F17

IO192PB4F17

IO71NB1F6

IO71PB1F6

IO207NB4F19

IO207PB4F19

IO73NB1F6

IO73PB1F6

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO74NB1F6

IO74PB1F6

v2.7

3-99

Axcelerator Family FPGAs

352-Pin CQFP

AX2000 Function

IO213PB4F19/CLKFP

Bank 5

Pin Number

AX2000 Function

Pin Number

AX2000 Function

Pin Number

137

IO282PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO294NB6F27

IO294PB6F27

IO296NB6F27

IO296PB6F27

IO341PB7F31

Dedicated I/O

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO217NB5F20

IO217PB5F20

IO236NB5F22

IO236PB5F22

IO237NB5F22

IO237PB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO240PB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

Bank 6

128

129

122

123

118

119

110

111

112

113

104

105

106

107

100

101

GND

Bank 7

IO300NB7F28

IO300PB7F28

IO303NB7F28

IO303PB7F28

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

IO320PB7F29

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO338NB7F31

IO338PB7F31

IO341NB7F31

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

240

IO257PB6F24

IO258NB6F24

IO258PB6F24

IO261NB6F24

IO261PB6F24

IO262NB6F24

IO262PB6F24

IO265NB6F24

IO265PB6F24

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

3-100

v2.7

Axcelerator Family FPGAs

352-Pin CQFP

AX2000 Function

352-Pin CQFP

AX2000 Function

Pin Number

246

252

258

264

265

274

280

286

292

298

310

322

330

334

340

345

352

312

311

135

134

349

348

347

350

351

Pin Number

263

279

291

329

339

AX2000 Function

Pin Number

203

215

144

156

168

GND

PRA

V_CCA

V_CCIB3

V_CCIB4

V_CCIB5

V_CCIB6

V_CCIB7

V_CCPLA

V_CCPLB

V_CCPLC

V_CCPLD

V_CCPLE

V_CCA

V_CCDA

V_CCIB0

V_CCIB1

V_CCIB2

108

120

116

117

130

131

132

148

149

174

178

221

266

268

293

294

307

308

309

327

328

346

321

333

344

273

285

297

227

239

245

257

185

197

317

315

303

301

140

138

126

124

318

316

304

302

141

139

127

125

267

PRB

PRC

PRD

TCK

V_CCPLF

TDI

V_CCPLG

V_CCPLH

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

TDO

TMS

TRST

V_CCA

102

114

150

162

175

191

209

233

251

V_CCIB2

V_CCIB3

v2.7

3-101

Axcelerator Family FPGAs

624-Pin CCGA

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

7 6

5 4 3 2 1

Figure 3-12 • 624-Pin CCGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-102

v2.7

Axcelerator Family FPGAs

624-Pin CCGA

AX1000 Function Pin Number

Bank 0

IO00NB0F0

624-Pin CCGA

AX1000 Function

Pin Number

F11

AX1000 Function

Pin Number

A16

A15

A20

A19

B17

IO23PB0F2

IO24NB0F2

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO53NB1F4

IO53PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO58NB1F5

IO58PB1F5

IO60NB1F5

IO60PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

IO00PB0F0

IO02NB0F0

IO02PB0F0

IO04NB0F0

IO04PB0F0

IO06NB0F0

IO06PB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO23NB0F2

IO24PB0F2

IO25PB0F2

B12

H11

G11

C11

IO26NB0F2

IO26PB0F2

B16

IO27NB0F2

G17

H17

A17

C19

C18

B20

IO27PB0F2

IO28NB0F2

J13

IO28PB0F2

K13

F10

IO29NB0F2

IO29PB0F2

D10

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

G13

G12

C13

C12

B19

H20

H19

A22

A21

C21

C20

B22

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO34NB1F3

G15

G14

B14

B13

G16

H16

C17

B18

H18

H15

H13

E15

F15

B21

J18

IO34PB1F3

J19

IO35NB1F3

D18

D17

F20

IO35PB1F3

IO36NB1F3

IO36PB1F3

F19

IO37NB1F3

E17

D12

D11

B11

B10

A11

A10

H10

E11

IO38NB1F3

F17

IO38PB1F3

D20

D19

E18

IO39NB1F3

D14

C14

D16

D15

F16

IO39PB1F3

IO40NB1F3

F18

IO40PB1F3

G19

G18

IO41NB1F4

IO42NB1F4

G21

G20

Bank 2

IO64NB2F6

IO42PB1F4

M17

v2.7

3-103

Axcelerator Family FPGAs

624-Pin CCGA

AX1000 Function

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

IO72NB2F6

IO72PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO84NB2F7

IO84PB2F7

IO86NB2F8

IO86PB2F8

Pin Number

AX1000 Function

Pin Number

L24

AX1000 Function

Pin Number

R25

G22

J21

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO110NB3F10

IO110PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO120NB3F11

IO120PB3F11

IO122NB3F11

IO122PB3F11

IO124NB3F11

IO124PB3F11

IO126NB3F11

IO126PB3F11

IO128NB3F11

IO128PB3F11

K24

P25

J20

G24

F24

U25

L23

T25

K20

F23

J25

U24

G25

F25

U23

E23

L18

T24

L25

R24

K18

E24

D24

H23

G23

L19

K25

Y25

J24

W25

V23

H24

J23

V24

N24

M24

N25

M25

AA24

Y24

K19

J22

AB25

AA25

T20

H22

N23

M23

N17

N16

L22

Bank 3

IO96NB3F9

IO96PB3F9

T18

R18

N20

P24

P20

P19

P21

T22

W24

R22

P22

U19

T19

V20

U20

R23

P23

R19

R20

AB24

R21

W22

W23

V22

IO97NB3F9

IO97PB3F9

IO98NB3F9

IO98PB3F9

U22

K22

M19

M18

N19

N18

L21

Y23

IO99NB3F9

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

IO104NB3F9

IO104PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

AA23

V21

U21

Y22

Y21

L20

Bank 4

P18

P17

N22

M22

M20

M21

E25

D25

IO129NB4F12

IO129PB4F12

IO131NB4F12

IO131PB4F12

IO133NB4F12

IO133PB4F12

IO135NB4F12

IO135PB4F12

W20

Y20

V19

W19

Y18

Y19

W18

V18

3-104

v2.7

Axcelerator Family FPGAs

624-Pin CCGA

AX1000 Function

Pin Number

Y17

AX1000 Function

Pin Number

AC18

AX1000 Function

Pin Number

IO137NB4F12

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

IO141PB4F13

IO142NB4F13

IO142PB4F13

IO143NB4F13

IO143PB4F13

IO144PB4F13

IO145NB4F13

IO145PB4F13

IO146NB4F13

IO146PB4F13

IO147NB4F13

IO147PB4F13

IO148PB4F13

IO149NB4F13

IO149PB4F13

IO150NB4F13

IO150PB4F13

IO151NB4F13

IO151PB4F13

IO152NB4F14

IO152PB4F14

IO153NB4F14

IO153PB4F14

IO155NB4F14

IO155PB4F14

IO156NB4F14

IO156PB4F14

IO157NB4F14

IO157PB4F14

IO158NB4F14

IO158PB4F14

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO182NB5F17

IO182PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO189NB5F17

IO189PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

AA17

AB19

AB18

AA19

U18

AC15

Y10

AC19

W10

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

W14

W15

AC13

AD9

AD10

AE10

AE11

AD7

AD8

AB9

AE6

AC20

AC21

AD17

AD18

AD21

AD22

AB17

AC17

AE22

AE15

AE16

AD19

AD20

AD15

AD16

AE21

AD14

AC14

AE19

AE20

V17

AD13

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

IO163PB5F15

W13

Y13

AC12

AD12

V10

V11

T13

AE7

IO164NB5F15

IO164PB5F15

AE4

AE5

IO165NB5F15

IO165PB5F15

U13

V13

W11

W12

AB6

AA6

AA9

IO167NB5F15

IO167PB5F15

AD5

AD6

AC5

AC6

AB7

AC7

IO168NB5F15

IO168PB5F15

IO169NB5F15

IO169PB5F15

IO171NB5F16

IO171PB5F16

Bank 6

IO172NB5F16

IO172PB5F16

AB8

AC8

AA11

Y11

AB10

AB11

AC9

AE9

AA8

IO193NB6F18

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO199NB6F18

IO199PB6F18

W17

AB16

W16

IO173NB5F16

IO173PB5F16

AA3

Y15

IO174NB5F16

IO174PB5F16

Y16

V15

IO175NB5F16

IO175PB5F16

V16

AB14

AB15

AE14

IO177NB5F16

IO177PB5F16

IO178NB5F16

v2.7

3-105

Axcelerator Family FPGAs

624-Pin CCGA

AX1000 Function

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO210NB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO215NB6F20

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

Pin Number

AX1000 Function

Pin Number

AX1000 Function

Pin Number

IO221PB6F20

IO223NB6F20

IO223PB6F20

IO224NB6F20

IO224PB6F20

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO249NB7F23

IO249PB7F23

IO251NB7F23

IO251PB7F23

IO253NB7F23

IO253PB7F23

IO255NB7F23

IO255PB7F23

IO257NB7F23

IO257PB7F23

AA1

AB1

Bank 7

IO225NB7F21

IO225PB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO239NB7F22

IO239PB7F22

IO240NB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO243NB7F22

IO243PB7F22

N10

AA2

AB2

Dedicated I/O

GND

A18

A24

A25

AA10

AA16

AA18

AA21

AA5

AB22

AB4

AC10

AC16

AC23

AC3

3-106

v2.7

Axcelerator Family FPGAs

624-Pin CCGA

AX1000 Function

624-Pin CCGA

AX1000 Function

Pin Number

AD1

AD2

AD24

AD25

AE1

AE18

AE2

AE24

AE25

AE8

Pin Number

M12

M13

M14

M15

N11

N12

N13

N14

N15

P11

AX1000 Function

Pin Number

GND

GND/LP

GND

TCK

TDI

TDO

TMS

TRST

V_CCA

V_CCDA

AB20

F22

J17

P12

K10

K11

K15

K16

L10

P13

B24

B25

C10

C16

C23

P14

P15

R11

R12

L16

R13

R10

R16

T10

T11

T15

T16

U17

R14

D22

R15

T21

E10

T23

E16

E21

V25

A12

AA13

AA15

AA7

AC11

AD11

AE17

B15

C15

H21

H25

K21

K23

A14

AA20

AB13

AD4

AE12

F21

L11

L12

G10

F13

L13

PRA

PRB

L14

A13

AB12

AE13

L15

PRC

PRD

D13

E13

M11

v2.7

3-107

Axcelerator Family FPGAs

624-Pin CCGA

AX1000 Function

V_CCIB4

624-Pin CCGA

AX1000 Function

V_CCDA

Pin Number

T14

U15

U16

AB5

AC4

AD3

AE3

T12

U10

U11

AA4

AB3

AC1

AC2

P10

AX1000 Function

Pin Number

V14

E19

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

V_CCDA

V_CCIB4

V_CCIB5

V_CCIB6

V_CCIB7

AA12

V_CCDA

N21

V12

V_CCDA

E20

V_CCDA

W21

V_CCIB0

V_CCIB1

V_CCIB2

V_CCIB3

V_CCIB4

J10

J11

K12

A23

B23

C22

D21

J15

J16

K14

C24

C25

D23

E22

K17

L17

M10

E12

J12

V_CCPLA

V_CCPLB

M16

AA22

AB23

AC24

AC25

P16

V_CCPLC

V_CCPLD

V_CCPLE

E14

H14

Y14

U14

Y12

U12

F12

V_CCPLF

V_CCPLG

V_CCPLH

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

R17

T17

AB21

AC22

AD23

AE23

H12

F14

J14

AA14

3-108

v2.7

Axcelerator Family FPGAs

624-Pin CCGA

AX2000 Function Pin Number

Bank 0

IO00NB0F0

624-Pin CCGA

AX2000 Function

Pin Number

B11

AX2000 Function

Pin Number

D15

A22

A21

F16

IO30NB0F2

IO30PB0F2

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO65NB1F6

IO66PB1F6

IO67NB1F6

IO67PB1F6

IO68NB1F6

IO68PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO70PB1F6

IO71PB1F6

IO73NB1F6

IO74NB1F6

IO74PB1F6

IO75NB1F6

IO75PB1F6

IO76NB1F7

IO76PB1F7

IO79NB1F7

IO79PB1F7

IO80NB1F7

IO80PB1F7

IO81NB1F7

IO81PB1F7

IO82NB1F7

IO82PB1F7

IO85NB1F7

D7*

E7*

B10

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO11NB0F0

IO11PB0F0

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20PB0F1

IO23NB0F2

IO23PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

IO28PB0F2

IO31NB0F2

E11

IO31PB0F2

F11

IO33NB0F2

D12

G17

H17

B17

IO33PB0F2

D11

IO34NB0F3

A11

IO34PB0F3

A10

B16

IO37NB0F3

J13

H18

C17

B18

IO37PB0F3

K13

IO38NB0F3

H11

IO38PB0F3

G11

B12

J18

IO40PB0F3

J19

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

G13

G12

C13

B20

B19

E9*

D8*

D10

E17

C12

F17

B22

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO45NB1F4

G15

G14

B14

B13

H13

D14

C14

A16

A15

H15

E15

F15

B21

G18

G19

C19

C18

D18

D17

C21

C20

H20

H19

E18

IO47NB1F4

IO47PB1F4

IO48NB1F4

IO48PB1F4

IO49PB1F4

F10

IO51NB1F4

IO51PB1F4

C11*

B8*

H10

IO52NB1F4

A17

G16

H16

A20

A19

D16

F18

IO55NB1F5

G21

G20

F20

IO55PB1F5

IO56NB1F5

IO56PB1F5

F19

IO57NB1F5

D20*

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

v2.7

3-109

Axcelerator Family FPGAs

624-Pin CCGA

AX2000 Function

Pin Number

AX2000 Function

Pin Number

L24

AX2000 Function

Pin Number

T24

IO85PB1F7

D19*

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

IO118NB2F11

IO121NB2F11

IO121PB2F11

IO122NB2F11

IO122PB2F11

IO123NB2F11

IO123PB2F11

IO124NB2F11

IO124PB2F11

IO127NB2F11

IO127PB2F11

IO128NB2F11

IO128PB2F11

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO153NB3F14

IO153PB3F14

IO154NB3F14

IO154PB3F14

IO157NB3F14

IO157PB3F14

IO158NB3F14

IO158PB3F14

IO160PB3F14

IO161NB3F15

IO161PB3F15

IO162NB3F15

IO162PB3F15

IO163NB3F15

IO163PB3F15

IO164NB3F15

IO164PB3F15

IO166NB3F15

IO167NB3F15

IO167PB3F15

IO168NB3F15

IO168PB3F15

IO169NB3F15

IO169PB3F15

IO170NB3F15

IO170PB3F15

Bank 2

K24

R24

IO86NB2F8

IO86PB2F8

F23

E23

H23

G23

E24

D24

M17*

G22*

J22

N17

T20

M20

M21

N19

R20

IO87NB2F8

IO87PB2F8

U25

T25

IO88NB2F8

IO88PB2F8

N18

T22

J25

U19

IO89NB2F8

IO89PB2F8

N24

T19

M24

L25

Y25

IO91NB2F8

IO91PB2F8

W25

V20

H22

L18

K25

IO92NB2F8

IO92PB2F8

N22

U20

K18

G24

F24

M22

N23

AB25

AA25

W24

U24

IO96NB2F9

IO96PB2F9

M23

P18

IO97NB2F9

IO97PB2F9

J21

J20

P17

U23

IO98PB2F9

J23

N25

AA24

Y24

IO99NB2F9

IO99PB2F9

L19

M25

K19

E25

D25

K20

M19

M18

J24

Bank 3

V22

IO100NB2F9

IO100PB2F9

IO103PB2F9

IO105NB2F9

IO105PB2F9

IO106NB2F9

IO106PB2F9

IO107NB2F10

IO107PB2F10

IO109NB2F10

IO109PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO129NB3F12

IO130PB3F12

IO131NB3F12

IO133NB3F12

IO133PB3F12

IO138NB3F12

IO138PB3F12

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO142NB3F13

IO142PB3F13

IO143PB3F13

IO145NB3F13

IO145PB3F13

N20

P24

P21

P20

P19

R23

P23

R22

P22

R19

R25

P25

R21

T18

R18

U22

V23

V24

AB24

V21

U21

H24

L23*

N16*

L22

Y23

AA23

W22*

W23*

Y22

K22

G25

F25

Y21

Bank 4

L21

IO171NB4F16

IO171PB4F16

AC20*

AC21*

L20

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

3-110

v2.7

Axcelerator Family FPGAs

624-Pin CCGA

AX2000 Function

Pin Number

W20

Pin Number

AB14

AB15

AE15

AE16

W16

AX2000 Function

Pin Number

AD10

V11

AD7

AD8

IO172NB4F16

IO172PB4F16

IO173NB4F16

IO173PB4F16

IO174NB4F16

IO176NB4F16

IO176PB4F16

IO177NB4F16

IO177PB4F16

IO182NB4F17

IO182PB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO187PB4F17

IO188NB4F17

IO188PB4F17

IO189PB4F17

IO191NB4F17

IO191PB4F17

IO192PB4F17

IO195PB4F18

IO196NB4F18

IO197NB4F18

IO197PB4F18

IO198NB4F18

IO198PB4F18

IO199NB4F18

IO199PB4F18

IO200NB4F18

IO201NB4F18

IO201PB4F18

IO202NB4F18

IO202PB4F18

IO206NB4F19

IO206PB4F19

IO229PB5F21

IO230NB5F21

IO233NB5F21

IO233PB5F21

IO234NB5F21

IO234PB5F21

IO236NB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO246NB5F23

IO246PB5F23

IO247NB5F23

IO247PB5F23

IO250NB5F23

IO250PB5F23

IO251NB5F23

IO251PB5F23

IO252NB5F23

IO252PB5F23

IO253NB5F23

IO253PB5F23

IO254NB5F23

IO254PB5F23

IO256NB5F23

IO256PB5F23

Y20

AD21

AD22

AA19

Y18

IO207NB4F19

IO207PB4F19

IO208PB4F19

IO209NB4F19

AE14

V15

V10

AC9

Y19

IO210NB4F19

AB19

AB18

V19

IO210PB4F19

V16

IO211NB4F19

AD14

AC14

W14

IO211PB4F19

AE4

AE5

AB9

AA9

W19

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

AC19

AB17

AC17

AD19

AD20

AC18

Y17

W15

AC13

AD13

AD5

AD6

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO216NB5F20

W13

Y13

AC12

AD12

U13

AB8

AC8

AB7

AC7

AA8

AA17

AE22

W18

IO216PB5F20

V13

V18

IO217NB5F20

AE10

AE11

W11

W12

AA11

Y11

U18

IO217PB5F20

AE21

AB16

AD17

AD18

V17

IO218NB5F20

IO218PB5F20

IO222NB5F20

IO222PB5F20

IO223PB5F21

AE9

AC5

AC6

W17

IO225NB5F21

AE6

AE19

AE20

AC15

AD15

AD16

Y15

IO225PB5F21

AE7

IO226NB5F21

Y10

IO226PB5F21

W10

T13

AB6*

AA6*

IO227PB5F21

IO228NB5F21

AB10

AB11

AD9

Bank 6

IO228PB5F21

IO257NB6F24

IO257PB6F24

Y16

IO229NB5F21

AA3

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

v2.7

3-111

Axcelerator Family FPGAs

624-Pin CCGA

AX2000 Function

IO258NB6F24

IO258PB6F24

IO259NB6F24

IO259PB6F24

IO260NB6F24

IO260PB6F24

IO262NB6F24

IO262PB6F24

IO263NB6F24

IO263PB6F24

IO268NB6F25

IO268PB6F25

IO269PB6F25

IO272NB6F25

IO272PB6F25

IO273NB6F25

IO273PB6F25

IO274NB6F25

IO274PB6F25

IO275NB6F25

IO275PB6F25

IO277NB6F25

IO278NB6F26

IO278PB6F26

IO279PB6F26

IO280NB6F26

IO281NB6F26

IO281PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

Pin Number

AX2000 Function

Pin Number

AX2000 Function

Pin Number

AA2

AB2

V6*

W4*

IO288NB6F26

IO290NB6F27

IO291NB6F27

IO291PB6F27

IO292NB6F27

IO292PB6F27

IO293NB6F27

IO293PB6F27

IO294NB6F27

IO296NB6F27

IO296PB6F27

IO298NB6F27

IO298PB6F27

IO299NB6F27

IO299PB6F27

IO321NB7F30

IO321PB7F30

IO323NB7F30

IO323PB7F30

IO324NB7F30

IO324PB7F30

IO327NB7F30

IO327PB7F30

IO328NB7F30

IO328PB7F30

IO329NB7F30

IO329PB7F30

IO331PB7F30

IO332NB7F31

IO332PB7F31

IO333NB7F31

IO333PB7F31

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO337NB7F31

IO338NB7F31

IO338PB7F31

IO339NB7F31

IO339PB7F31

IO340NB7F31

IO340PB7F31

IO341NB7F31

IO341PB7F31

Bank 7

IO300NB7F28

IO300PB7F28

IO302NB7F28

IO304NB7F28

IO304PB7F28

IO308NB7F28

IO309NB7F28

IO309PB7F28

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO313NB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

P9*

N6*

N10

AA1

AB1

G4*

G3*

Dedicated I/O

GND

A18

A24

A25

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

3-112

v2.7

Axcelerator Family FPGAs

624-Pin CCGA

AX2000 Function

Pin Number

AX2000 Function

Pin Number

AX2000 Function

Pin Number

GND

PRA

AA10

AA16

AA18

AA21

AA5

AB22

AB4

V25

H21

H25

K21

K23

F13

PRB

A13

AB12

AE13

PRC

PRD

L11

TCK

AC10

AC16

AC23

AC3

AD1

AD2

AD24

AD25

AE1

L12

TDI

L13

TDO

L14

TMS

L15

TRST

V_CCA

V_CCDA

M11

M12

M13

M14

M15

N11

N12

N13

N14

N15

P11

P12

P13

P14

P15

R11

R12

R13

R14

R15

T21

T23

AB20

F22

J17

AE18

AE2

K10

K11

K15

K16

L10

AE24

AE25

AE8

L16

R10

R16

T10

T11

T15

T16

U17

B24

B25

C10

C16

C23

D22

E10

A12

A14

AA13

AA15

E16

E21

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

v2.7

3-113

Axcelerator Family FPGAs

624-Pin CCGA

AX2000 Function

V_CCIB2

624-Pin CCGA

AX2000 Function

V_CCDA

Pin Number

D23

E22

AX2000 Function

V_CCIB7

Pin Number

AA20

AA7

AB13

AC11

AD11

AD4

AE12

AE17

B15

C15

V_CCDA

_CCIB2

_CCIB7

V_CCDA

K17

V_CCDA

V_CCIB2

_CCIB2

V_CCIB3

L17

V_CCIB7

V_CCPLA

M10

E12

V_CCDA

M16

AA22

AB23

AC24

AC25

P16

V_CCDA

V_CCPLB

J12

V_CCDA

_CCIB3

V_CCPLC

E14

V_CCDA

V_CCPLD

H14

Y14

U14

Y12

U12

F12

V_CCDA

V_CCIB3

V_CCPLE

V_CCDA

V_CCIB3

V_CCIB4

V_CCPLF

V_CCDA

R17

V_CCPLG

V_CCPLH

V_CCDA

D13

E13

E19

F21

T17

V_CCDA

AB21

AC22

AD23

AE23

T14

V_COMPLA

V_COMPLB

V_COMPLC

V_COMPLD

V_COMPLE

V_COMPLF

V_COMPLG

V_COMPLH

V_PUMP

V_CCDA

H12

F14

V_CCDA

V_CCIB4

V_CCDA

G10

_CCIB4

J14

V_CCDA

AA14

V14

AA12

V12

E20

V_CCDA

N21

V_CCIB4

U15

U16

AB5

AC4

AD3

AE3

V_CCDA

V_CCIB4

V_CCIB5

V_CCDA

W21

V_CCIB0

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

V_CCIB0

V_CCIB5

T12

_CCIB0

J10

_CCIB5

U10

U11

AA4

AB3

AC1

AC2

P10

J11

V_CCIB0

K12

A23

B23

C22

D21

J15

V_CCIB6

_CCIB1

_CCIB6

V_CCIB1

V_CCIB6

_CCIB1

_CCIB6

V_CCIB1

J16

V_CCIB6

_CCIB1

_CCIB2

K14

C24

C25

_CCIB7

V_CCIB2

V_CCIB7

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

* Not routed on the same package layer

and to adjacent LGA pads as its differential

pair complement. Recommended to be

used as a single-ended I/O.

3-114

v2.7

Axcelerator Family FPGAs

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version

Changes in Current Version (v2.7)

Page

v2.6

RoHS-compliant information was added to the "Ordering Information".

ACTgen was changed to SmartGen because ACTgen was obsolete.

In Table 2-4, the units for the P_LOAD, P₁₀, and P_I/Owere updated from mW/MHz to mW/MHz.

N/A

2-2

2-9

v2.5

In the "Pin Descriptions"section, the HCLK and CLK descriptions were updated to include tie-off

information.

The "Global Resource Distribution" section was updated.

The " 624-Pin CCGA" table was updated.

A note was added to Table 2-2.

2-59

3-103

2-1

v2.4

v2.3

v2.2

In the "Package Thermal Characteristics", the temperature was changed from 150°C to 125°C.

Revised ordering information and timing data to reflect phase out of –3 speed grade options.

Table 2-3 was updated.

2-6

The "Packaging Data" section is new.

iii

Table 2-2 was updated.

2-1

2-9

2-10

1-3

"VCCDA Supply Voltage" was updated.

"PRA/B/C/D Probe A/B/C/D" was updated.

The "User I/Os" was updated.

v2.1

Figure 1-3 was updated.

Table 2-2 was updated.

2-1

2-2

2-3

2-7

2-8

The "Power-Up/Down Sequence" section was updated.

Table 2-4 was updated.

Table 2-5 was updated.

The "Timing Characteristics" section was added.

Table 2-7 was updated.

Figure 2-1 was updated.

The External Setup and Clock-to-Out (Pad-to-Pad) equations in the "Hardwired Clock – Using

LVTTL 24mA High Slew Clock I/O" section were updated.

The External Setup and Clock-to-Out (Pad-to-Pad) in the "Routed Clock – Using LVTTL 24mA

High Slew Clock I/O" section were updated.

2-8

The "Global Pins" section was updated.

The "User I/Os" section was updated.

Table 2-17 was updated.

2-9

2-10

2-17

2-18

2-21

Figure 2-8 was updated.

Figure 2-13 and Figure 2-14 were updated.

v2.7

4-1

Axcelerator Family FPGAs

Previous Version

Changes in Current Version (v2.7)

Page

v2.1 (continued)

The following timing parameters were renamed in I/O timing characteristic tables from 2-22 to 2-41

Table 2-21 to Table 2-59:

_IOCLKQ> t_ICLKQ

t_IOCLKY> t_OCLKQ

Timing numbers were updated from Table 2-21 to Table 2-77.

The "R-Cell" section was updated.

Figure 2-59 was updated.

2-22 to 2-58

2-47

2-74

Figure 2-60 was updated.

2-75

Figure 2-67 was updated.

2-85

Figure 2-68 was updated.

2-86

Table 2-88 to Table 2-92 were updated.

Table 2-97 to Table 2-101 were updated.

The "TRST" section was updated.

The "Global Set Fuse" section was added.

2-75 to 2-79

2-86 to 2-88

2-89

2-90

A footnote was added to "896-Pin FBGA" for the AX2000 regarding pins AB1, AE2, G1, and

K2.

3-49

Pinouts for the AX250, AX500 and AX1000 were added for "352-Pin CQFP".

Pinout for the AX1000 was added for "624-Pin CCGA".

Table 2-78 was updated.

3-88

3-102

2-58

2-89

v2.0

The "Low Power Mode" section was updated.

Table 1-1 has been updated.

Advanced v1.6

"Ordering Information" section has been updated.

The "Device Resources" section has been updated.

The "Temperature Grade Offerings" section is new.

The "Speed Grade and Temperature Grade Matrix" section has been updated.

Table 2-9 has been updated.

iii

2-11

2-1

2-2

2-3

2-5

2-6

2-7

2-9

Table 2-10 has been updated.

Table 2-1 has been updated.

Table 2-2 has been updated.

Table 2-3 has been updated.

Table 2-4 has been updated.

Table 2-5 has been updated.

The "Power Estimation Example" section has been updated.

The "Thermal Characteristics" section has been updated.

The "Package Thermal Characteristics" section has been updated.

The "Timing Characteristics" section has been updated.

The "Pin Descriptions" section has been updated.

Timing numbers have been updated from the "3.3V LVTTL" section to the "Timing 2-22 to 2-48

Characteristics" section. Many AC Loads were updated as well.

Timing characteristics for the "Hardwired Clocks" section were updated.

2-55

4-2

v2.7

Axcelerator Family FPGAs

Previous Version

Advanced v0.6

(continued)

Changes in Current Version (v2.7)

Page

2-57

Timing characteristics for the "Routed Clocks" section were updated.

Table 2-88 to Table 2-91 were updated.

2-75 to 2-78

2-86 to 2-87

2-89

Table 2-97 to Table 2-98were updated.

The "Low Power Mode" section was updated.

The "Interface" section was updated.

2-89

The "Data Registers (DRs)" section was updated.

The "Security" section was updated.

2-90

The "Silicon Explorer II Probe Interface" section was updated.

The "Programming" section was updated.

2-91

In the "208-Pin PQFP" (AX500) section, pins 2, 52, and 156 changed from V_CCDAto V_CCA

3-78

For pins 170 and 171, the I/O names refer to pair 23 instead of 24.

The following changes were made in the "676-Pin FBGA"(AX500) section:

3-36

AE2, AE25

AF2, AF25

Change from NC to GND.

Changed from GND to NC

AB4, AF24, C1, C26 Changed from V_CCDAto V_CCA

AD15

AD17

Change from V_CCDAto V_COMPLE

Changed from V_COMPLEto V_CCDA

In the "896-Pin FBGA" (AX2000) section, the AK28 changed from V_CCIB5 to V_CCIB4.

The "352-Pin CQFP" section is new.

The "624-Pin CCGA" section is new.

All I/O FIFO capability was removed.

Table 1-1 was updated.

3-49

3-88

3-102

n/a

Advanced v1.5

Figure 1-9 and was updated.

1-7

Figure 2-5 was updated.

2-14

3-22

2-2

The "Using an I/O Register" section was updated.

The AX250 and AX1000 descriptions were added to the "484-Pin FBGA"section.

Table 2-3 was updated.

Advanced v1.4

Advanced v1.3

Figure 2-1 was updated.

2-8

Figure 2-48 was updated.

2-63

2-68

3-78

Figure 2-52 was updated.

In the "208-Pin PQFP" table, pin 196 was missing, but it has been added in this version with a

function of GND.

The following pins in the "484-Pin FBGA" table for AX500 were changed:

Pin G7 is GND/LP

3-22

Pins AB8, C10, C11, C14, AB16 are NC.

The "676-Pin FBGA" table was updated.

3-36

v2.7

4-3

Axcelerator Family FPGAs

Previous Version

Changes in Current Version (v2.7)

Page

Advanced v1.2

The "Device Resources" section was updated for the CS180.

The "Programmable Interconnect Element" and Figure 1-2 was new.

The "180-Pin CSP" table is new.

1-1 and 1-2

3-1

The "208-Pin PQFP" tables for the AX500 were updated. The following pins were not defined

3-78

in the previous version:

GND 21

IO106PB5F10/CLKHP 71

GND 136

Advanced v1.1

Table 1-1 was updated.

"Ordering Information", "Device Resources" and the Product Plan table were updated.

Figure 1-3 was updated.

1-3

The "Design Environment" section was updated.

Figure 1-8 was new.

1-6

Table 2-3 was updated.

2-2

"Package Thermal Characteristics" was updated.

Figure 2-2 was updated.

2-6

2-9

Table 2-8 was updated.

2-11

2-20

2-22 to 2-49

2-55

2-86 to 2-87

3-78

3-12

3-18

Figure 2-11 was updated.

The timing characteristics tables from pages 2-22 to 2-49 were updated.

The "Global Resources" section was updated.

The timing characteristics tables from pages 2-86 to 2-87 were updated.

The "208-Pin PQFP" tables are new.

The "256-Pin FBGA" tables are new.

The "324-Pin FBGA" tables are new.

4-4

v2.7

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” The

definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a advanced datasheet (advanced or production) containing general

product information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could

require an approved export license prior to export from the United States. An export includes release of product or

disclosure of technology to a foreign national inside or outside the United States.

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

www.actel.com

Actel Corporation

Actel Europe Ltd.

Actel Japan

Actel Hong Kong

2061 Stierlin Court

Mountain View, CA

94043-4655

River Court, Meadows Business Park EXOS Ebisu Building 4F

Room 2107, China Resources Building

26 Harbour Road

Wanchai, Hong Kong

Station Approach, Blackwater

Camberley Surrey GU17 9AB

United Kingdom

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

USA

Phone +81.03.3445.7671

Fax +81.03.3445.7668

Phone +852 2185 6460

Fax +852 2185 6488

Phone 650.318.4200

Fax 650.318.4600

Phone +44 (0) 1276 609 300

Fax +44 (0) 1276 607 540

http://jp.actel.com

www.actel.com.cn

5172160-15/11.08

AX500-1BGG896PP [ACTEL]

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