EX128-FCS128I [ACTEL]
Field Programmable Gate Array, 6000 Gates, 178MHz, 384-Cell, CMOS, PBGA128, 0.8 MM PITCH, CSP-128;型号: | EX128-FCS128I |
厂家: | Actel Corporation |
描述: | Field Programmable Gate Array, 6000 Gates, 178MHz, 384-Cell, CMOS, PBGA128, 0.8 MM PITCH, CSP-128 时钟 栅 可编程逻辑 |
文件: | 总48页 (文件大小:371K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
v4.2
eX Family FPGAs
FuseLock
•
•
Live on Power-Up
No Power-Up/Down Sequence Required for Supply
Voltages
Leading Edge Performance
•
•
•
240 MHz System Performance
350 MHz Internal Performance
3.9 ns Clock-to-Out (Pad-to-Pad)
•
Configurable Weak-Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
Individual Output Slew Rate Control
2.5V, 3.3V, and 5.0V Mixed-Voltage Operation
with 5.0V Input Tolerance and 5.0V Drive Strength
Software Design Support with Actel Designer and
Libero™ Integrated Design Environment (IDE)
Tools
•
•
Specifications
•
•
•
•
•
•
3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22µm CMOS Process Technology
Up to 100% Resource Utilization with 100% Pin
Locking
Up to 132 User-Programmable I/O Pins
•
•
Deterministic Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Fuselock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Features
•
•
•
•
•
•
High-Performance, Low-Power Antifuse FPGA
•
•
LP/Sleep Mode for Additional Power Savings
Advanced Small-Footprint Packages
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
Product Profile
De vice
e X64
e X128
e X256
Capacity
3,000
2,000
6,000
4,000
12,000
8,000
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64
128
128
256
256
512
Combinatorial Cells
Maximum User I/Os
128
84
256
100
512
132
Global Clocks
Hardwired
Routed
1
2
1
2
1
2
Speed Grades
–F, Std, –P
C, I, A
–F, Std, –P
C, I, A
–F, Std, –P
C, I, A
Temperature Grades*
Package (by pin count)
TQFP
64, 100
49, 128
64, 100
49, 128
100
128, 180
CSP
Note: *Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.
Ju n e 2004
i
© 2004 Actel Corporation
e X Fa m ily FPGAs
Ordering Information
eX128
P
TQ
100
Application (Ambient Temperature Range)
Blank = Commercial (0˚C to 70˚C)
I = Industrial (-40˚C to 85˚C)
A= Automotive (-40˚C to 125˚C)
PP = Pre-production
Package Lead Count
Package Type
=
TQ Thin Quad Flat Pack (1.4mm pitch)
=
CS
Chip-Scale Package (0.8mm pitch)
Speed Grade
Blank= Standard Speed
P = Approximately 30% Faster than Standard
F = Approximately 40% Slower than Standard
Part Number
eX64 = 64 Dedicated Flip-Flops (3,000 System Gates)
eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)
eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Plastic Device Resources
Use r I/Os (In clu d in g Clo ck Bu ffe rs)
De vice
TQFP 64-Pin
TQFP 100-Pin
CSP 49-Pin
CSP 128-Pin
CSP 180-Pin
eX64
41
46
—
56
70
81
36
36
—
84
—
—
eX128
eX256
100
100
132
Note: Package Definitions:TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
Temperature Grade Offerings
De vice \Pa cka g e
eX64
TQFP 64-Pin
C, I, A
TQFP 100-Pin
C, I, A
CSP 49-Pin
C, I, A
CSP 128-Pin
C, I, A
CSP 180-Pin
C, I, A
eX128
C, I, A
C, I, A
C, I, A
C, I, A
C, I, A
eX256
C, I, A
C, I, A
C, I, A
C, I, A
C, I, A
Notes: C = Commercial
I = Industrial
A = Automotive
Speed Grade and Temperature Grade Matrix
–F
St d
✓
–P
✓
✓
C
✓
I
✓
A
✓
Notes:
P = Approximately 30% faster than Standard
–F = Approximately 40% slower than Standard
Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.
Contact your local Actel representative for device availability.
i i
v 4 . 2
e X Fa m ily FPGAs
Table of Contents
eX Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2.5V/3.3V/5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
5.0V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Package Pin Assignments
64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
v 4 .1
iii
e X Fa m ily FPGAs
eX Family FPGAs
impedance connection. Actel’s eX family provides two
types of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
General Description
The eX family of FPGAs is a low-cost solution for low-
power, high-performance designs. The inherent low
power attributes of the antifuse technology, coupled
with an additional low static power mode, make these
devices ideal for power-sensitive applications. Fabricated
with an advanced 0.22µm CMOS antifuse technology,
these devices achieve high performance with no power
penalty.
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-1). The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the eX FPGA. The clock source for the R-
cell can be chosen from either the hard-wired clock or
the routed clock.
eX Family Architecture
The C-cell implements a range of combinatorial functions
up to five inputs (Figure 1-2 on page 1-2). Inclusion of
the DB input and its associated inverter function enables
the implementation of more than 4,000 combinatorial
functions in the eX architecture in a single module.
Actel's eX family is implemented on a high-voltage twin-
well CMOS process using 0.22µm design rules. The eX
family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a
grid of logic modules with virtually no chip area lost to
interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
Two C-cells can be combined together to create a flip-
flop to imitate an R-cell via the use of the CC macro. This
is particularly useful when implementing non-timing-
critical paths and when the design engineer is running
out of R-cells. More information about the CC macro can
be found in Actel’s Maximizing Logic Utilization in eX, SX
and SX-A FPGA Devices Using CC Macros application
note.
patented
metal-to-metal
programmable
antifuse
interconnect elements. The antifuse interconnect is
made up of a combination of amorphous silicon and
dielectric material with barrier metals and has an "on"
state resistance of 25Ω with a capacitance of 1.0fF for
low-signal impedance. The antifuses are normally open
circuit and, when programmed, form a permanent low-
Routed
Data Input
S0
S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
CLR
Internal Logic
CKS
CKP
Figure 1-1 • R-Cell
v4.2
1-1
e X Fa m ily FPGAs
Module Organization
C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which contains two C-cells
and one R-cell in a C-R-C configuration.
Clusters are further organized into modules called SuperClusters for improved design efficiency and device
performance, as shown in Figure 1-3. Each SuperCluster is a two-wide grouping of Clusters.
D0
D1
Y
D2
D3
Sa
Sb
DB
B1
A1
A0 B0
Figure 1-2 • C-Cell
R-Cell
C-Cell
Routed
Data Input
D0
D1
S1
S0
PSET
CLR
Y
D2
D3
DirectConnect
Q
D
Y
Input
Sb
Sa
HCLK
CLKA,
CLKB,
DB
Internal Logic
CKS
CKP
A0 B0
A1
B1
Cluster
Cluster
SuperCluster
Figure 1-3 • Cluster Organization
1 -2
v 4 . 2
e X Fa m ily FPGAs
Routing Resources
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 1-4). This routing
architecture also dramatically reduces the number of
antifuses required to complete a circuit, ensuring the
highest possible performance.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering maximum pin-to-pin
propagation of 0.3 ns (–P speed grade).
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
fully automatic place-and-route software to minimize
signal propagation delays.
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring R-
cell in a given SuperCluster. DirectConnect uses a hard-
wired signal path requiring no programmable
interconnection to achieve its fast signal propagation
time of less than 0.1 ns (–P speed grade).
DirectConnect
• No antifuses
SuperClusters
• 0.1 ns routing delay
FastConnect
• One antifuse
• 0.5 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 1-4 • DirectConnect and FastConnect for SuperClusters
v4.2
1-3
e X Fa m ily FPGAs
The remaining two clocks (CLKA, CLKB) are global routed
clock networks that can be sourced from external pins or
from internal logic signals (via the CLKINT routed clock
buffer) within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals, the
external clock pin cannot be used for any other input
and must be tied LOW or HIGH and must not float.
Figure 1-6 describes the CLKA and CLKB circuit used in eX
devices.
Clock Resources
eX’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-Cell.
HCLK cannot be connected to combinational logic. This
provides a fast propagation path for the clock signal,
enabling
the
3.9 ns clock-to-out
(pad-to-pad)
performance of the eX devices. The hard-wired clock is
tuned to provide a clock skew of less than 0.1 ns worst
case. If not used, the HCLK pin must be tied LOW or HIGH
and must not be left floating. Figure 1-5 describes the
clock circuit used for the constant load HCLK.
Table 1-1 describes the possible connections of the
routed clock networks, CLKA and CLKB.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Design
software and the pin must be tied to GND on the board.
(See the "TRST, I/O Boundary Scan Reset Pin" on page 1-
26).
Unused clock pins must not be left floating and must be
tied to HIGH or LOW.
Constant Load
Clock Network
HCLKBUF
Figure 1-5 • eX HCLK Clock Pad
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 1-6 • eX Routed Clock Buffer
Table 1-1 • Connections of Routed Clock Netw orks, CLKA
and CLKB
Mo d u le
C-Cell
Pin s
A0, A1, B0 and B1
CLKA, CLKB, S0, S1, PSET, and CLR
EN
R-Cell
I/O-Cell
1 -4
v 4 . 2
e X Fa m ily FPGAs
Other Architectural Features
All unused I/Os are configured as tristate outputs by
Actel's Designer software, for maximum flexibility when
designing new boards or migrating existing designs.
Each I/O module has an available pull-up or pull-down
resistor of approximately 50kΩ that can configure the I/O
in a known state during power-up. Just shortly before
VCCA reaches 2.5V, the resistors are disabled and the I/Os
will be controlled by user logic.
Performance
The combination of architectural features described
above enables eX devices to operate with internal clock
frequencies exceeding 350 MHz for very fast execution
of complex logic functions. The eX family is an optimal
platform upon which the functionality previously
contained in CPLDs can be integrated. eX devices meet
the performance goals of gate arrays, and at the same
time, present significant improvements in cost and time
to market. Using timing-driven place-and-route tools,
designers can achieve highly deterministic device
performance.
Table 1-2 describes the I/O features of eX devices. For
more information on I/Os, refer to Actel eX, SX-A, and
RT54SX-S I/Os application note.
Table 1-2 • I/O Features
Fu n ct io n
De scrip t io n
User Security
Input Buffer • 5.0V TTL
Threshold
•
•
•
•
•
3.3V LVTTL
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
such that they cannot be accessed or bypassed without
destroying the rest of the device, making both invasive
and more-subtle noninvasive attacks ineffective against
Actel antifuse FPGAs.
Selection
2.5V LVCMOS2
5.0V TTL/CMOS
3.3V LVTTL
Nominal
Output Drive
2.5V LVCMOS 2
Output Buffer “Hot-Swap” Capability
•
I/O on an unpowered device does not sink
current
•
Can be used for “cold sparing”
Look for this symbol to ensure your valuable IP is secure.
Selectable on an individual I/O basis
Individually selectable low-slew option
Power-Up
Individually selectable pull ups and pull downs
during power-up (default is to power up in
tristate)
Enables deterministic power-up of device
FuseLock
VCCA and VCCI can be powered in any order
Figure 1-7 • Fuselock
For more information, refer to Actel's Implementation of
Security in Actel Antifuse FPGAs application note.
The eX family supports mixed-voltage operation and is
designed to tolerate 5.0V inputs in each case.
A detailed description of the I/O pins in eX devices can be
found in "Pin Description" on page 1-26.
I/O Modules
Each I/O on an eX device can be configured as an input,
an output, a tristate output, or a bidirectional pin. Even
without the inclusion of dedicated I/O registers, these I/
Os, in combination with array registers, can achieve
clock-to-out (pad-to-pad) timing as fast as 3.9 ns. I/O cells
in eX devices do not contain embedded latches or flip-
flops and can be inferred directly from HDL code. The
device can easily interface with any other device in the
system, which in turn enables parallel design of system
components and reduces overall design time.
v4.2
1-5
e X Fa m ily FPGAs
Hot Sw apping
Low Pow er Mode
eX I/Os are configured to be hot-swappable. During
power-up/down (or partial up/down), all I/Os are
tristated, provided VCCA ramps up within a diode drop of
VCCI. VCCA and VCCI do not have to be stable during
power-up/down, and they do not require a specific
power-up or power-down sequence in order to avoid
damage to the eX devices. In addition, all outputs can be
programmed to have a weak resistor pull-up or pull-
down for output tristate at power-up. After the eX
device is plugged into an electrically active system, the
device will not degrade the reliability of or cause
damage to the host system. The device's output pins are
driven to a high impedance state until normal chip
operating conditions are reached. Please see the
application note, Actel SX-A and RT54SX-S Devices in
Hot-Swap and Cold-Sparing Applications, which also
applies to the eX devices, for more information on hot
swapping.
The eX family has been designed with a Low Power
Mode. This feature, activated with setting the special LP
pin to HIGH for a period longer than 800 ns, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated when the device enters this mode.
Since the core of the device is turned off, the states of
the registers are lost. The device must be re-initialized
when returning to normal operating mode. I/Os can be
driven during LP mode. For details, refer to the Design
For Low Power in Actel Antifuse FPGAs application note
under the section Using the LP Mode Pin on eX Devices.
Clock pins should be driven either HIGH or LOW and
should not float; otherwise, they will draw current and
burn power. The device must be re-initialized when
exiting LP mode. To exit the LP mode, the LP pin must be
driven LOW for over 200µs to allow for the charge
pumps to power-up and device initialization can begin.
Table 1-3 illustrates the standby current of eX devices in
LP mode.
Pow er Requirements
Power consumption is extremely low for the eX family
due to the low capacitance of the antifuse interconnects.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power FPGA architecture available today.
Table 1-3 • Standby Pow er of eX Devices in LP Mode
Typical Conditions, VCCA, VCCI = 2.5V, TJ = 25° C
Pro d u ct
eX64
Lo w Po w e r St a n d b y Cu rre n t
Un it s
µA
100
111
134
eX128
eX256
µA
µA
1 -6
v 4 . 2
e X Fa m ily FPGAs
Figure 1-8 to Figure 1-11 on page 1-8 show some sample power characteristics of eX devices.
300
250
eX64
200
150
100
50
eX128
eX256
0
50
100
150
200
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7V, device tested at room temperature.
Figure 1-8 • eX Dynamic Pow er Consumption – High Frequency
80
70
60
50
40
30
20
10
0
eX64
eX128
eX256
0
10
20
30
40
50
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7V, device tested at room temperature.
Figure 1-9 • eX Dynamic Pow er Consumption – Low Frequency
v4.2
1-7
e X Fa m ily FPGAs
180
160
140
120
100
80
32-bit Decoder
8 x 8-bit Counters
SDRAM Controller
60
40
20
0
0
25
50
75
100
125
150
175
200
Frequency (MHz)
Figure 1-10 • Total Dynamic Pow er (mW)
12,000
10,000
8,000
6,000
4,000
2,000
0
5% DC
10% DC
15% DC
0
10
20
30
40
50
60
Frequency (MHz)
Figure 1-11 • System Pow er at 5% , 10% , and 15% Duty Cycle
1 -8
v 4 . 2
e X Fa m ily FPGAs
Boundary Scan Testing (BST)
Flexible Mode
All eX devices are IEEE 1149.1 compliant. eX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test
pins (TMS, TDI, TCK, TDO and TRST). The functionality of
each pin is defined by two available modes: Dedicated
and Flexible, and is described in Table 1-4. In the
dedicated test mode, TCK, TDI, and TDO are dedicated
pins and cannot be used as regular I/Os. In flexible mode
(default mode), TMS should be set HIGH through a pull-
up resistor of 10kΩ. TMS can be pulled LOW to initiate
the test sequence.
In Flexible Mode, TDI, TCK and TDO may be used as
either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are disabled in flexible
JTAG mode, and an external 10kΩ pull-resistor to VCCI is
required on the TMS pin.
To select the Flexible mode, users need to uncheck the
"Reserve JTAG" box in "Device Selection Wizard" in
Actel's Designer software. The functionality of TDI, TCK,
and TDO pins is controlled by the BST TAP controller. The
TAP controller receives two control inputs, TMS and TCK.
Upon power-up, the TAP controller enters the Test-Logic-
Reset state. In this state, TDI, TCK, and TDO function as
user I/Os. The TDI, TCK, and TDO pins are transformed
from user I/Os into BST pins when the TMS pin is LOW at
the first rising edge of TCK. The TDI, TCK, and TDO pins
return to user I/Os when TMS is held HIGH for at least
five TCK cycles.
Table 1-4 • Boundary Scan Pin Functionality
De d ica t e d Te st Mo d e
Fle xib le Mo d e
TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and
BST pins may be used as I/Os
No need for pull-up resistor for Use a pull-up resistor of 10kΩ
Table 1-5
describes
the
different
configuration
TMS and TDI
on TMS
requirements of BST pins and their functionality in
different modes.
Dedicated Test Mode
Table 1-5 • Boundary-Scan Pin Configurations and
Functions
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
De sig n e r
" Re se rve JTAG"
Se le ct io n
TAP Co n t ro lle r
St a t e
Mo d e
Dedicated (JTAG)
Flexible (User I/O)
Flexible (JTAG)
Checked
Unchecked
Unchecked
Any
To select Dedicated mode, users need to reserve the JTAG
pins in Actel's Designer software by checking the
"Reserve JTAG" box in "Device Selection Wizard"
(Figure 1-12).
Test-Logic-Reset
Any EXCEPT Test-
Logic-Reset
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan
Reset pin when the "Reserve JTAG Test Reset" option is
selected as shown in Figure 1-12. An internal pull-up
resistor is permanently enabled on the TRST pin in this
mode. It is recommended to connect this pin to GND in
normal operation to keep the JTAG state controller in
the Test-Logic-Reset state. When JTAG is being used, it
can be left floating or be driven HIGH.
When the "Reserve JTAG Test Reset" option is not
selected, this pin will function as a regular I/O. If unused
as an I/O in the design, it will be configured as a tristated
output.
Figure 1-12 • Device Selection Wizard
v4.2
1-9
e X Fa m ily FPGAs
1. Load the .AFM file
JTAG Instructions
2. Select the device to be programmed
3. Begin programming
Table 1-6 lists the supported instructions with the
corresponding IR codes for eX devices.
When the design is ready to go to production, Actel
offers device volume-programming services either
Table 1-6 • JTAG Instruction Code
In st ru ct io n s (IR4: IR0)
EXTEST
Bin a ry Co d e
00000
through
distribution
partners or via
in-house
programming from the factory.
For more details on programming eX devices, please
refer to the Programming Actel Devices application note
and the Silicon Sculptor II User's Guide.
SAMPLE / PRELOAD
INTEST
00001
00010
USERCODE
IDCODE
00011
Probing Capabilities
00100
eX devices provide internal probing capability that is
accessed with the JTAG pins. The Silicon Explorer II
Diagnostic hardware is used to control the TDI, TCK, TMS
and TDO pins to select the desired nets for debugging.
The user simply assigns the selected internal nets in the
Silicon Explorer II software to the PRA/PRB output pins
for observation. Probing functionality is activated when
the BST pins are in JTAG mode and the TRST pin is driven
HIGH or left floating. If the TRST pin is held LOW, the
TAP controller will remain in the Test-Logic-Reset state so
no probing can be performed. The Silicon Explorer II
automatically places the device into JTAG mode, but the
user must drive the TRST pin HIGH or allow the internal
pull-up resistor to pull TRST HIGH.
HIGHZ
01110
CLAMP
01111
Diagnostic
BYPASS
10000
11111
Reserved
All others
Table 1-7 lists the codes returned after executing the
IDCODE instruction for eX devices. Note that bit 0 is
always "1." Bits 11-1 are always "02F", which is Actel's
manufacturer code.
Table 1-7 • IDCODE for eX Devices
When you select the "Reserve Probe Pin" box as shown
in Figure 1-12 on page 1-9, the layout tool reserves the
PRA and PRB pins as dedicated outputs for probing. This
"reserve" option is merely a guideline. If the Layout tool
requires that the PRA and PRB pins be user I/Os to
achieve successful layout, the tool will use these pins for
user I/Os. If you assign user I/Os to the PRA and PRB pins
and select the "Reserve Probe Pin" option, Designer
Layout will override the "Reserve Probe Pin" option and
place your user I/Os on those pins.
De vice
eX64
Re visio n
Bit s 31-28
Bit s 27-12
40B2, 42B2
40B0, 42B0
40B5, 42B5
40B2, 42B2
40B0, 42B0
40B5, 42B5
0
0
0
1
1
1
8
9
eX128
eX256
eX64
9
A
B
B
eX128
eX256
To allow for probing capabilities, the security fuse must
not be programmed. Programming the security fuse will
disable the probe circuitry. Table 1-8 on page 1-11
summarizes the possible device configurations for
probing once the device leaves the "Test-Logic-Reset"
JTAG state.
Programming
Device programming is supported through Silicon
Sculptor series of programmers. In particular, Silicon
Sculptor II is a compact, robust, single-site and multi-site
device programmer for the PC.
With standalone software, Silicon Sculptor II allows
concurrent programming of multiple units from the
same PC, ensuring the fastest programming times
possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition,
integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor II also provides extensive
hardware self-testing capability.
Silicon Explorer II Probe
Silicon Explorer II is an integrated hardware and
software solution that, in conjunction with Actel’s
Designer software tools, allow users to examine any of
the internal nets of the device while it is operating in a
prototype or a production system. The user can probe
into an eX device via the PRA and PRB pins without
changing the placement and routing of the design and
without using any additional resources. Silicon Explorer
The procedure for programming an eX device using
Silicon Sculptor II is as follows:
1 -1 0
v 4 . 2
e X Fa m ily FPGAs
II's non-invasive method does not alter timing or loading
effects, thus shortening the debug cycle.
interconnection between Silicon Explorer II and the eX
device to perform in-circuit verification.
Silicon Explorer II does not require re-layout or
additional MUXes to bring signals out to an external pin,
which is necessary when using programmable logic Design Considerations
devices from other suppliers.
The TDI, TCK, TDO, PRA, and PRB pins should not be used
Silicon Explorer II samples data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
as input or bidirectional ports. Since these pins are active
during probing, critical signals input through these pins
are not available while probing. In addition, the Security
Fuse should not be programmed because doing so
disables the probe circuitry. It is recommended to use a
series 70Ω termination resistor on every probe connector
(TDI, TCK, TMS, TDO, PRA, PRB). The 70Ω series
termination is used to prevent data transmission
corruption during probing and reading back the
checksum.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 1-13 illustrates the
Table 1-8 • Device Configuration Options for Probe Capability (TRST pin reserved)
JTAG Mo d e
Dedicated
Flexible
TRST1
LOW
LOW
HIGH
HIGH
–
Se cu rit y Fu se Pro g ra m m e d
PRA, PRB2
User I/O3
TDI, TCK, TDO2
Probing Unavailable
User I/O3
No
No
No
No
Yes
User I/O3
Dedicated
Flexible
Probe Circuit Outputs
Probe Circuit Outputs
Probe Circuit Secured
Probe Circuit Inputs
Probe Circuit Inputs
Probe Circuit Secured
–
Notes:
1. If TRST pin is not reserved, the device behaves according to TRST=HIGH in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
Actel’s Designer software.
16 Pin
Connection
e X FPGAs
TDI
TCK
TMS
TDO
Se ria l
Silicon Explorer II
Co n n e ct io n
PRA
PRB
22 Pin
Connection
Additional 16 Channels
(Logic Analyzer)
Figure 1-13 • Silicon Explorer II Probe Setup
v4.2
1-11
e X Fa m ily FPGAs
Development Tool Support
The eX family of FPGAs is fully supported by both Actel's
Libero™ Integrated Design Environment and Designer
FPGA Development software. Actel Libero IDE is a design
management environment that streamlines the design
flow. Libero IDE provides an integrated design manager
that seamlessly integrates design tools while guiding the
user through the design flow, managing all design and
log files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. Libero IDE
includes Synplify® for Actel from Synplicity®, ViewDraw
for Actel from Mentor Graphics, ModelSim™ HDL
Simulator from Mentor Graphics®, WaveFormer Lite™
from SynaptiCAD™, and Designer software from Actel.
Refer to the Libero IDE flow (located on Actel’s website)
diagram for more information.
Related Documents
Datasheet
eX Automotive Family FPGAs
http://www.actel.com/documents/eXAutoDS.pdf
Application Notes
Maximizing Logic Utilization in eX, SX and SX-A FPGA
Devices Using CC Macros
http://www.actel.com/documents/MaxLogicUtil.pdf
Actel's Implementation of Security in Actel Antifuse FPGAs
http://www.actel.com/documents/
AntifuseSecurityAN.pdf
Actel eX, SX-A, and RT54SX-S I/Os
http://www.actel.com/documents/antifuseIOan.pdf
Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-
Sparing Applications
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
http://www.actel.com/documents/
HotSwapColdSparing.pdf
Design For Low Power in Actel Antifuse FPGAs
http://www.actel.com/documents/lowpower.pdf
Programming Actel Devices
timing-driven place-and-route, and
a
world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can lock his/her
design pins before layout while minimally impacting the
results of place-and-route. Additionally, the back-
annotation flow is compatible with all the major
simulators and the simulation results can be cross-probed
with Silicon Explorer II, Actel’s integrated verification
and logic analysis tool. Another tool included in the
Designer software is the ACTgen macro builder, which
easily creates popular and commonly used logic
functions for implementation into your schematic or HDL
design. Actel's Designer software is compatible with the
most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
http://www.actel.com/documents/
ProgrammingGuide.pdf
User Guides
Silicon Sculptor II User's Guide
http://www.actel.com/techdocs/manuals/
default.asp#programmers
Miscellaneous
Libero IDE flow
http://www.actel.com/products/tools/libero/flow.html
1 -1 2
v 4 . 2
e X Fa m ily FPGAs
2.5V/3.3V/5.0V Operating Conditions
Table 1-9 • Absolute Maximum Ratings*
Sym b o l
VCCI
Pa ra m e t e r
Lim it s
Un it s
V
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
–0.3 to +6.0
–0.3 to +3.0
–0.5 to +5.75
–0.5 to +VCCI
–65 to +150
VCCA
V
V
V
I
VO
Output Voltage
V
TSTG
Storage Temperature
°C
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 1-10 • Recommended Operating Conditions
Pa ra m e t e r
Co m m e rcia l
0 to +70
In d u st ria l
–40 to +85
2.3-2.7
Un it s
°C
Temperature Range*
2.5V Power Supply
2.3-2.7
V
Range (VCCA, VCCI
)
3.3V Power Supply
3.0-3.6
3.0-3.6
V
V
Range (VCCI
)
5.0V Power Supply
4.75-5.25
4.75-5.25
Range (VCCI
)
Note: *Ambient temperature (TA).
Table 1-11 • Typical eX Standby Current at 25°C
V
CCA= 2.5V
VCCA = 2.5V
VCCA = 2.5V
Pro d u ct
eX64
VCCI = 2.5V
VCCI = 3.3V
VCCI = 5.0V
397µA
696µA
698µA
497µA
795µA
796µA
700µA
1,000µA
2,000µA
eX128
eX256
v4.2
1-13
e X Fa m ily FPGAs
2.5V LVCMOS2 Electrical Specifications
Co m m e rcia l
In d u st ria l
Sym b o l Pa ra m e t e r
Min .
(IOH = -100µA) 2.1
Ma x.
Min .
Ma x.
Un it s
V
VOH
VCCI = MIN, V = VIH or V
2.1
2.0
1.7
I
IL
VCCI = MIN, V = VIH or V
(IOH = -1 mA)
(IOH = -2 mA)
(IOL= 100µA)
(IOL= 1mA)
2.0
1.7
V
I
IL
VCCI = MIN, V = VIH or V
V
I
IL
VOL
VCCI = MIN, V = VIH or V
0.2
0.4
0.7
0.7
0.2
0.4
0.7
0.7
V
I
IL
VCCI = MIN, V = VIH or V
V
I
IL
VCCI = MIN,V = VIH or V
(IOL= 2 mA)
V
I
IL
V
Input Low Voltage, VOUT ≤ VOL(max)
Input High Voltage, VOUT ≥ VOH(min)
–0.3
-0.3
V
IL
V
1.7 VCCI + 0.3 1.7
VCCI
0.3
+
V
IH
I / I
Input Leakage Current, VIN = VCCI or GND
3-State Output Leakage Current, VOUT = VCCI or GND
Input Transition Time
–10
–10
10
10
10
10
1.0
–10
–10
10
10
10
10
3.0
µA
µA
ns
IL IH
IOZ
1,2
tR, tF
CIO
I/O Capacitance
pF
3,4
ICC
Standby Current
mA
IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1. tR is the transition time from 0.7 V to 1.7V.
2. tF is the transition time from 1.7V to 0.7V.
3. ICC max Commercial –F = 5.0mA
4. ICC = ICCI + ICCA
1 -1 4
v 4 . 2
e X Fa m ily FPGAs
3.3V LVTTL Electrical Specifications
Co m m e rcia l
In d u st ria l
Sym b o l Pa ra m e t e r
Min .
Ma x.
Min .
Ma x.
Un it s
V
VOH
VOL
VCCI = MIN, V = VIH or V
(IOH = –8mA)
(IOL= 12mA)
2.4
2.4
I
IL
VCCI = MIN, V = VIH or V
0.4
0.8
0.4
0.8
V
I
IL
V
Input Low Voltage
V
IL
V
Input High Voltage
2.0
–10
–10
VCCI +0.5
10
2.0
–10
–10
VCCI +0.5
10
V
IH
I / I
Input Leakage Current, VIN = VCCI or GND
3-State Output Leakage Current, VOUT = VCCI or GND
Input Transition Time
µA
µA
ns
IL IH
IOZ
10
10
1,2
tR, tF
CIO
10
10
I/O Capacitance
10
10
pF
mA
3,4
ICC
Standby Current
1.5
10
IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1. tR is the transition time from 0.8 V to 2.0V.
2. tF is the transition time from 2.0V to 0.8V.
3.
ICC max Commercial –F=5.0mA
4. ICC = ICCI + ICCA
5.0V TTL Electrical Specifications
Co m m e rcia l
In d u st ria l
Un it
s
Sym b o l Pa ra m e t e r
Min .
Ma x.
Min .
Ma x.
VOH
VOL
VCCI = MIN, V = VIH or V
(IOH = –8mA)
(IOL= 12mA)
2.4
2.4
V
V
I
IL
VCCI = MIN, V = VIH or V
0.4
0.8
0.4
0.8
I
IL
V
Input Low Voltage
V
IL
V
Input High Voltage
2.0
–10
–10
VCCI +0.5
10
2.0
–10
–10
VCCI +0.5
10
V
IH
I / I
Input Leakage Current, VIN = VCCI or GND
3-State Output Leakage Current, VOUT = VCCI or GND
Input Transition Time
µA
µA
ns
IL IH
IOZ
10
10
1,2
tR, tF
CIO
10
10
I/O Capacitance
10
10
pF
mA
3,4
ICC
Standby Current
15
20
IV Curve Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html
Note:
1. tR is the transition time from 0.8 V to 2.0V.
2. tF is the transition time from 2.0V to 0.8V.
3. ICC max Commercial –F=20mA
4. ICC = ICCI + ICCA
v4.2
1-15
e X Fa m ily FPGAs
CEQ Values for eX Devices
Combinatorial modules (Ceqcm) 1.70pF
Pow er Dissipation
Power consumption for eX devices can be divided into
Sequential modules (Ceqsm)
Input buffers (Ceqi)
1.70pF
1.30pF
7.40pF
1.05pF
two components: static and dynamic.
Output buffers (Ceqo)
Routed array clocks (Ceqcr)
Static Pow er Component
The power due to standby current is typically a small
component of the overall power. Typical standby current
for eX devices is listed in the Table 1-11 on page 1-13. For
example, the typical static power for eX128 at 3.3V VCCI
is:
The variable and fixed capacitance of other device
components must also be taken into account when
estimating the dynamic power dissipation.
Table 1-12 shows the capacitance of the clock
components of eX devices.
ICC * VCCA = 795µA x 2.5V = 1.99mW
Table 1-12 • Capacitance of Clock Components of eX
Devices
Dynamic Pow er Component
e X64
e X128
e X256
Power dissipation in CMOS devices is usually dominated
by the dynamic power dissipation. This component is
frequency-dependent and a function of the logic and the
external I/O. Dynamic power dissipation results from
charging internal chip capacitance due to PC board
traces and load device inputs. An additional component
of the dynamic power dissipation is the totem pole
current in the CMOS transistor pairs. The net effect can
be associated with an equivalent capacitance that can be
combined with frequency and voltage to represent
dynamic power dissipation.
Dedicated array clock
variable (Ceqhv)
–
0.85pF
0.85pF
0.85pF
Dedicated array clock – fixed 18.00pF 20.00pF 25.00pF
(Ceqhf)
Routed array clock A (r1)
Routed array clock B (r2)
23.00pF 28.00pF 35.00pF
23.00pF 28.00pF 35.00pF
The estimation of the dynamic power dissipation is a
piece-wise linear summation of the power dissipation of
each component.
2
Dynamic power dissipation = CEQ * VCCA x F
where:
Dynamic power dissipation
2
CEQ = Equivalent capacitance
= VCCA * [(mc * Ceqcm * fmC)Comb Modules + (ms * Ceqsm
*
fmS)Seq Modules + (n * Ceqi * fn)Input Buffers + (0.5 * (q1 *
Ceqcr * fq1) + (r1 * fq1))RCLKA + (0.5 * (q2 * Ceqcr * fq2) +
F
= switching frequency
Equivalent capacitance is calculated by measuring ICCA at
specified frequency and voltage for each circuit
component of interest. Measurements have been made
(r2 * fq2))RCLKB + (0.5 * (s1 * Ceqhv * fs1)+(Ceqhf
*
a
2
fs1))HCLK] + VCCI * [(p * (Ceqo + CL) * fp)Output Buffers
]
where:
over a range of frequencies at a fixed value of VCC
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown
below.
.
mc
ms
n
= Number of combinatorial cells switching at
frequency fm, typically 20% of C-cells
= Number of sequential cells switching at
frequency fm, typically 20% of R-cells
= Number of input buffers switching at
frequency fn, typically number of inputs / 4
= Number of output buffers switching at
frequency fp, typically number of outputs / 4
= Number of R-cells driven by routed array
clock A
p
q1
q2
=
Number of R-cells driven by routed array
clock B
r1
r2
s1
= Fixed capacitance due to routed array clock A
= Fixed capacitance due to routed array clock B
= Number of R-cells driven by dedicated array
clock
Ceqcm
=
Equivalent capacitance of combinatorial
modules
1 -1 6
v 4 . 2
e X Fa m ily FPGAs
Ceqsm
=
Equivalent capacitance of sequential
modules
Thermal Characteristics
The temperature variable in the Designer software refers
to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature. EQ 1-1,
shown below, can be used to calculate junction
temperature.
Ceqi = Equivalent capacitance of input buffers
Ceqcr = Equivalent capacitance of routed array clocks
Ceqhv = Variable capacitance of dedicated array clock
Ceqhf = Fixed capacitance of dedicated array clock
Ceqo = Equivalent capacitance of output buffers
CL
=
Average output loading capacitance,
typically 10pF
fmc
= Average C-cell switching frequency, typically
F/10
EQ 1-1
Junction Temperature = ∆T + Ta(1)
Where:
fms = Average R-cell switching frequency, typically
F/10
fn
=
Average input buffer switching frequency,
typically F/5
Ta = Ambient Temperature
∆T = Temperature gradient between junction
(silicon) and ambient = θja * P
fp
= Average output buffer switching frequency,
typically F/5
fq1
fq2
fs1
= Frequency of routed clock A
= Frequency of routed clock B
= Frequency of dedicated array clock
P = Power
θ
= Junction to ambient of package. θ numbers are
ja
located in the "Package Thermal Characteristics" section
below.
ja
The eX, SX-A and RTSX-S Power Calculator can be used to
estimate the total power dissipation (static and dynamic)
of eX devices and can be found at
http://www.actel.com/products/rescenter/power/
calculators.asp.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two
different air flow rates. θjc is provided for reference.
The maximum junction temperature is 150°C.
The maximum power dissipation allowed for eX devices
is a function of θja. A sample calculation of the absolute
maximum power dissipation allowed for a TQFP 100-pin
package at commercial temperature and still air is as
follows:
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C
--------------------------------------------------------------------------------------------------------------------------------- ----------------------------------
Maximum Power Allowed =
=
= 2.39W
θja(°C/W)
33.5°C/W
θja
1.0 m /s
2.5 m /s
Pa cka g e Typ e
Pin Co u n t
θjc
St ill Air
42.4
200 ft/m in
500 ft/m in
Un it s
°C/W
°C/W
°C/W
°C/W
°C/W
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
Chip Scale Package (CSP)
Chip Scale Package (CSP)
Chip Scale Package (CSP)
64
100
49
12.0
14.0
36.3
27.4
59.5
44.6
47.6
34.0
25.0
54.1
40.6
43.3
33.5
72.2
128
180
54.1
57.8
v4.2
1-17
e X Fa m ily FPGAs
eX Timing Model
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
Combinatorial
Cell
t
t
= 0.3 ns
= 0.4 ns
I/O Module
I/O Module
IRD1
IRD2
t
= 0.7 ns
INYH
t
= 2.6 ns
DHL
t
= 0.7 ns
PD
t
t
t
= 0.3 ns
RD1
= 0.7 ns
RD4
= 1.2 ns
RD8
I/O Module
Register
Cell
t
= 1.9 ns
ENZL
D
Q
t
t
t
RD1
= 0.5 ns
= 0.3 ns
SUD
HD
= 0.0 ns
t
= 2.6 ns
DHL
Routed
Clock
t
= 1.3 ns
RCKH
t
= 0.6 ns
(100% Load)
RCO
I/O Module
Register
Cell
I/O Module
t
= 1.3 ns
t
= 1.9 ns
INYH
ENZL
t
= 0.3 ns
= 0.5 ns
IRD1
D
Q
t
t
t
RD1
= 0.3 ns
SUD
= 0.0 ns
HD
t
= 2.6 ns
DHL
Hard-Wired
Clock
t
t
RCO
= 1.1 ns
= 0.6 ns
HCKH
Note: Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).
Figure 1-14 • eX Timing Model
Hardw ired Clock
Routed Clock
External Setup
=
tINYH + tIRD1 + tSUD – tHCKH
0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns
External Setup
=
tINYH + tIRD2 + tSUD – tRCKH
0.7 + 0.4 + 0.5 – 1.3= 0.3 ns
=
=
Clock-to-Out (Pad-to-Pad), typical
Clock-to-Out (Pad-to-Pad), typical
=
=
t
HCKH + tRCO + tRD1 + tDHL
=
=
t
RCKH + tRCO + tRD1 + tDHL
1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
1 -1 8
v 4 . 2
e X Fa m ily FPGAs
Output Buffer Delays
E
D
PAD To AC test loads (shown below)
TRIBUFF
VCC
VCC
VCC
50% 50%
VCC
In
50%
50%
GND
1.5V
50%
50%
GND
10%
En
GND
90%
En
Out
VOH
1.5V
VOH
1.5V
1.5V
Out
VOL
Out
GND
VOL
t
t
t
t
t
ENHZ
t
DHL
DLH
ENZL
ENZH
ENLZ
Table 1-13 • Output Buffer Delays
AC Test Loads
Load 3
(Used to measure disable delays)
Load 1
(used to measure
propagation delay)
Load 2
(Used to measure enable delays)
GND
GND
VCC
VCC
To the output
under test
t
t
R to VCC for PLZ
R to VCC for PZL
35 pF
t
t
To the output
under test
To the output
under test
R to GND for PHZ
R to GND for PHZ
R = 1 kW
R = 1 kW
35 pF
5 pF
Figure 1-15 • AC Test Loads
v4.2
1-19
e X Fa m ily FPGAs
Input Buffer Delays
C-Cell Delays
S
Y
A
B
Y
PAD
INBUF
VCC
50%
50%
S, A or B
GND
VCC
50%
3V
50%
Out
GND
In
0V
1.5V 1.5V
t
t
PD
PD
V
CC
Out
VCC
Out
50%
50%
GND
t
50%
50%
GND
t
tINY
tINY
PD
PD
Table 1-14 • Input Buffer Delays
Table 1-15 • C-Cell Delays
Cell Timing Characteristics
D
Q
PRESET
CLR
CLK
(Positive edge triggered)
tHD
D
tHP
t SUD
t HPWH
,
t RPWH
CLK
,
t
HPWL tRPWL
tRCO
Q
t PRESET
tCLR
CLR
tWASYN
PRESET
Figure 1-16 • Flip-Flops
1 -2 0
v 4 . 2
e X Fa m ily FPGAs
Long Tracks
Timing Characteristics
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, no more than six
percent of nets in a fully utilized device require long
tracks. Long tracks contribute approximately 4 ns to 8.4
ns delay. This additional delay is represented statistically
in higher fanout routing delays.
Timing characteristics for eX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer utility or performing simulation with post-
layout delays.
Timing Derating
Critical Nets and Typical Nets
eX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case
processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating
temperature, and worst-case processing.
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to six percent of the nets in a design may be designated
as critical.
Temperature and Voltage Derating Factors
Table 1-16 • Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 2.3V)
Ju n ct io n Te m p e ra t u re (TJ)
25 70
VCCA
2.3
–55
0.79
0.74
0.69
–40
0.80
0.74
0.70
0
85
125
1.13
1.06
1.00
0.87
0.81
0.76
0.88
0.83
0.78
1.00
0.93
0.88
1.04
0.97
0.91
2.5
2.7
v4.2
1-21
e X Fa m ily FPGAs
eX Family Timing Characteristics
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.3V TJ = 70°C)
,
‘–P’ Sp e e d
‘St d ’ Sp e e d
‘–F’ Sp e e d
Pa ra m e t e r
De scrip t io n
Min .
Ma x.
Min .
Ma x.
Min .
Ma x.
Un it s
C-Ce ll Pro p a g a t io n De la ys1
tPD
Internal Array Module
0.7
1.0
1.4
ns
Pre d ict e d Ro u t in g De la ys2
tDC
FO=1 Routing Delay, DirectConnect
0.1
0.3
0.3
0.4
0.5
0.7
1.2
1.7
0.1
0.5
0.5
0.6
0.8
1.0
1.7
2.5
0.2
0.7
0.7
0.8
1.1
1.3
2.4
3.5
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO=1 Routing Delay, FastConnect
FO=1 Routing Delay
tRD1
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
tRD12
R-Ce ll Tim in g
tRCO
FO=12 Routing Delay
Sequential Clock-to-Q
0.6
0.6
0.7
0.9
0.8
0.9
1.3
1.2
1.3
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Hold Time
tPRESET
tSUD
0.5
0.0
1.3
0.3
0.3
0.7
0.0
1.9
0.5
0.5
1.0
0.0
2.6
0.7
0.7
tHD
tWASYN
tRECASYN
tHASYN
2.5V In p u t Mo d u le Pro p a g a t io n De la ys
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
0.6
0.8
0.9
1.1
1.3
1.5
ns
ns
3.3V In p u t Mo d u le Pro p a g a t io n De la ys
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
0.7
0.9
1.0
1.3
1.4
1.8
ns
ns
5.0V In p u t Mo d u le Pro p a g a t io n De la ys
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
0.7
0.9
1.0
1.3
1.4
1.8
ns
ns
In p u t Mo d u le Pre d ict e d Ro u t in g De la ys2
tIRD1
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.4
0.5
0.7
1.2
1.7
0.4
0.6
0.8
1.0
1.7
2.5
0.5
0.8
1.1
1.3
2.4
3.5
ns
ns
ns
ns
ns
ns
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
1 -2 2
v 4 . 2
e X Fa m ily FPGAs
Table 1-18 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 4.75V, TJ = 70°C)
‘–P’ Sp e e d ‘St d ’ Sp e e d
‘–F’ Sp e e d
Pa ra m e t e r
De scrip t io n
Min .
Ma x.
Min .
Ma x.
Min .
Ma x.
Un it s
De d ica t e d (Ha rd -Wire d ) Arra y Clo ck Ne t w o rks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.1
1.6
1.6
2.3
2.3
ns
ns
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
1.4
1.4
2.0
2.0
2.8
2.8
ns
ns
<0.1
357
<0.1
250
<0.1
178
ns
Minimum Period
2.8
4.0
5.6
ns
fHMAX
Maximum Frequency
MHz
Ro u t e d Arra y Clo ck Ne t w o rks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.1
1.0
1.2
1.2
1.3
1.3
1.6
1.4
1.7
1.7
1.9
1.9
2.2
2.0
2.4
2.4
2.6
2.6
ns
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
tRPWH
tRPWL
Min. Pulse Width HIGH
1.5
1.5
2.1
2.1
3.0
3.0
ns
ns
ns
ns
ns
Min. Pulse Width LOW
1
1
1
tRCKSW
tRCKSW
tRCKSW
Note:
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.2
0.1
0.1
0.3
0.2
0.1
0.4
0.3
0.2
1. Clock skew improves as the clock network becomes more heavily loaded.
v4.2
1-23
e X Fa m ily FPGAs
Table 1-19 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 2.3V or 3.0V, TJ = 70°C)
‘–P’ Sp e e d ‘St d ’ Sp e e d
‘–F’ Sp e e d
Pa ra m e t e r
De scrip t io n
Min .
Ma x.
Min .
Ma x.
Min .
Ma x.
Un it s
De d ica t e d (Ha rd -Wire d ) Arra y Clo ck Ne t w o rks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.1
1.6
1.6
2.3
2.3
ns
ns
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
1.4
1.4
2.0
2.0
2.8
2.8
ns
ns
<0.1
357
<0.1
250
<0.1
178
ns
Minimum Period
2.8
4.0
5.6
ns
fHMAX
Maximum Frequency
MHz
Ro u t e d Arra y Clo ck Ne t w o rks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.0
1.2
1.2
1.4
1.4
1.4
1.4
1.7
1.7
2.0
2.0
2.0
2.0
2.4
2.4
2.8
2.8
ns
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
tRPWH
tRPWL
Min. Pulse Width HIGH
1.4
1.4
2.0
2.0
2.8
2.8
ns
ns
ns
ns
ns
Min. Pulse Width LOW
1
1
1
tRCKSW
tRCKSW
tRCKSW
Note:
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.2
0.2
0.1
0.3
0.2
0.1
0.4
0.3
0.2
1. Clock skew improves as the clock network becomes more heavily loaded.
1 -2 4
v 4 . 2
e X Fa m ily FPGAs
Table 1-20 • eX Family Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.3V, TJ = 70°C)
‘–P’ Sp e e d
Min . Ma x.
‘St d ’ Sp e e d
‘–F’ Sp e e d
Min . Ma x.
Pa ra m e t e r
De scrip t io n
Min .
Ma x.
Un it s
2.5V LVCMOS Ou t p u t Mo d u le Tim in g 1 (VCCI = 2.3V)
tDLH
Data-to-Pad LOW to HIGH
3.3
3.5
4.7
5.0
6.6
7.0
ns
ns
tDHL
Data-to-Pad HIGH to LOW
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
dTLH
Data-to-Pad HIGH to LOW—Low Slew
Enable-to-Pad, Z to L
11.6
2.5
16.6
3.6
23.2
5.1
ns
ns
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
11.8
3.4
16.9
4.9
23.7
6.9
ns
ns
Enable-to-Pad, L to Z
2.1
3.0
4.2
ns
Enable-to-Pad, H to Z
2.4
5.67
0.046
0.022
0.072
7.94
0.066
0.05
0.1
ns
Delta Delay vs. Load LOW to HIGH
Delta Delay vs. Load HIGH to LOW
Delta Delay vs. Load HIGH to LOW—Low Slew
0.034
0.016
0.05
ns/pF
ns/pF
ns/pF
dTHL
dTHLS
3.3V LVTTL Ou t p u t Mo d u le Tim in g 1 (VCCI = 3.0V)
tDLH
Data-to-Pad LOW to HIGH
2.8
2.7
4.0
3.9
5.6
5.4
ns
ns
tDHL
Data-to-Pad HIGH to LOW
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
dTLH
Data-to-Pad HIGH to LOW—Low Slew
Enable-to-Pad, Z to L
9.7
13.9
3.2
19.5
4.4
ns
2.2
ns
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
9.7
13.9
4.0
19.6
5.6
ns
2.8
ns
Enable-to-Pad, L to Z
2.8
4.0
5.6
ns
Enable-to-Pad, H to Z
2.6
3.8
5.3
ns
Delta Delay vs. Load LOW to HIGH
Delta Delay vs. Load HIGH to LOW
Delta Delay vs. Load HIGH to LOW—Low Slew
0.02
0.016
0.05
0.03
0.022
0.072
0.046
0.05
0.1
ns/pF
ns/pF
ns/pF
dTHL
dTHLS
5.0V TTL Ou t p u t Mo d u le Tim in g 1 (VCCI = 4.75V)
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Data-to-Pad HIGH to LOW—Low Slew
Enable-to-Pad, Z to L
2.0
2.6
6.8
1.9
6.8
2.1
3.3
2.9
3.7
9.7
2.7
9.8
3.0
4.8
4.0
5.2
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
Note:
13.6
3.8
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
13.7
4.1
Enable-to-Pad, L to Z
6.6
1. Delays based on 35 pF loading.
v4.2
1-25
e X Fa m ily FPGAs
Pin Description
CLKA/B
Ro u t e d Clo ck A a n d B
TCK, I/O
Te st Clo ck
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL
or LVTTL specifications. The clock input is buffered prior
to clocking the R-cells. If not used, this pin must be set
LOW or HIGH on the board. It must not be left floating.
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to Table 1-4 on
page 1-9). This pin functions as an I/O when the
boundary scan state machine reaches the “logic reset”
state.
GND
Gro u n d
TDI, I/O
Te st Da t a In p u t
LOW supply voltage.
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set LOW (refer to Table 1-4 on page 1-9). This pin
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
HCLK
De d ica t e d (Ha rd w ire d )
Arra y Clo ck
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell
and offers clock speeds independent of the number of R-
cells being driven. If not used, this pin must be set LOW
or HIGH on the board. It must not be left floating.
TDO, I/O
Te st Da t a Ou t p u t
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 1-4 on page 1-9). This pin functions as an I/O when
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer is being used, TDO
will act as an output when the "checksum" command is
run. It will return to user I/O when "checksum" is
complete.
I/O
In p u t /Ou t p u t
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL or LVTTL specifications. Unused I/O pins are
automatically tristated by the Designer software.
TMS
Te st Mo d e Se le ct
LP
Lo w Po w e r Pin
The TMS pin controls the use of the IEEE 1149.1
Boundary scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set LOW, the TCK, TDI, and
TDO pins are boundary scan pins (refer to Table 1-4 on
page 1-9). Once the boundary scan pins are in test mode,
they will remain in that mode until the internal
boundary scan state machine reaches the “logic reset”
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The “logic
reset” state is reached five TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
Controls the low power mode of the eX devices. The
device is placed in the low power mode by connecting
the LP pin to logic HIGH. In low power mode, all I/Os are
tristated, all input buffers are turned OFF, and the core
of the device is turned OFF. To exit the low power mode,
the LP pin must be set LOW. The device enters the low
power mode 800 ns after the LP pin is driven to a logic
HIGH. It will resume normal operation 200µs after the LP
pin is driven to a logic LOW.
NC
No Co n n e ct io n
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
TRST, I/O
Bo u n d a ry Sca n Re se t Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the “Reserve JTAG Reset Pin” is
not selected in the Designer software.
PRA/PRB, I/O
Pro b e A/B
The Probe pin is used to output data from any user-
defined design node within the device. This diagnostic
pin can be used independently or in conjunction with the
other probe pin to allow real-time diagnostic output of
any signal path within the device. The Probe pin can be
used as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be
permanently disabled to protect programmed design
confidentiality.
V
Su p p ly Vo lt a g e
CCI
Supply voltage for I/Os.
V
Su p p ly Vo lt a g e
CCA
Supply voltage for Array.
1 -2 6
v 4 . 2
e X Fa m ily FPGAs
Package Pin Assignments
64-Pin TQFP
64
1
64-Pin
TQFP
Figure 2-1 • 64-Pin TQFP
v4.2
2-1
e X Fa m ily FPGAs
64-Pin TQFP
64-Pin TQFP
e X64
e X128
e X64
e X128
Pin Nu m b e r
Fu n ct io n
Fu n ct io n
Pin Nu m b e r
Fu n ct io n
Fu n ct io n
1
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
33
34
35
36
37
38
39
40
41
42
43
44
45*
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
I/O
GND
I/O
2
3
I/O
I/O
4
TMS
GND
VCCI
I/O
TMS
GND
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
5
6
7
I/O
I/O
8
I/O
I/O
NC
I/O
9
NC
I/O
NC
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
I/O
I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
I/O
I/O
VCCA
GND/LP
GND
I/O
VCCA
GND/ LP
GND
I/O
NC
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
PRB, I/O
VCCA
GND
I/O
PRB, I/O
VCCA
GND
I/O
I/O
I/O
CLKA
CLKB
VCCA
GND
PRA, I/O
I/O
CLKA
CLKB
VCCA
GND
PRA, I/O
I/O
HCLK
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
TDO, I/O
TCK, I/O
TCK, I/O
Note: *Please read the LP pin descriptions for restrictions on
Note: *Please read the LP pin descriptions for restrictions on
their use
their use
2 -2
v 4 . 2
e X Fa m ily FPGAs
100-Pin TQFP
100
1
100-Pin
TQFP
Figure 2-2 • 100-Pin TQFP (Top View )
v4.2
2-3
e X Fa m ily FPGAs
100-Pin TQFP
100-Pin TQFP
e X64
e X128
e X256
e X64
e X128
e X256
Pin Nu m b e r
Fu n ct io n
GND
TDI, I/O
NC
Fu n ct io n
Fu n ct io n
Pin Nu m b e r
Fu n ct io n
VCCA
GND
NC
Fu n ct io n
Fu n ct io n
1
GND
TDI, I/O
NC
GND
TDI, I/O
I/O
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
VCCA
GND
NC
VCCA
GND
NC
2
3
4
NC
NC
I/O
I/O
I/O
I/O
5
NC
NC
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
6
I/O
I/O
I/O
7
TMS
VCCI
GND
NC
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
9
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VCCI
I/O
VCCI
I/O
VCCI
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
TDO, I/O
NC
TDO, I/O
I/O
TDO, I/O
I/O
TRST, I/O
NC
TRST, I/O
I/O
TRST, I/O
I/O
GND
NC
GND
NC
GND
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
NC
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
NC
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
VCCA
VCCI
NC
VCCA
VCCI
I/O
VCCA
VCCI
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND/LP
VCCA
GND/LP
VCCA
GND/LP
PRB, I/O
PRB, I/O
PRB, I/O
Note: *Please read the LP pin descriptions for restrictions on
Note: *Please read the LP pin descriptions for restrictions on
their use
their use
2 -4
v 4 . 2
e X Fa m ily FPGAs
100-Pin TQFP
e X64
e X128
e X256
Pin Nu m b e r
Fu n ct io n
GND
I/O
Fu n ct io n
Fu n ct io n
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
I/O
GND
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
NC
I/O
NC
NC
I/O
NC
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
NC
CLKA
CLKB
NC
CLKA
CLKB
NC
VCCA
GND
PRA, I/O
I/O
VCCA
GND
PRA, I/O
I/O
VCCA
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
Note: *Please read the LP pin descriptions for restrictions on
their use
v4.2
2-5
e X Fa m ily FPGAs
49-Pin CSP
A1 Ball Pad Corner
2
3
6
1
5
7
4
A
B
C
D
E
F
G
Figure 2-3 • 49-Pin CSP (Top View )
2 -6
v 4 . 2
e X Fa m ily FPGAs
49-Pin CSP
49-Pin CSP
e X64
e X128
e X64
e X128
Pin Nu m b e r
Fu n ct io n
Fu n ct io n
Pin Nu m b e r
Fu n ct io n
Fu n ct io n
A1
A2
A3
A4
A5
A6
A7
B1
I/O
I/O
I/O
I/O
D5
D6
D7
E1
E2
E3
E4
E5
E6
E7
F1
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
TRST, I/O
VCCI
GND
I/O
TRST, I/O
VCCI
GND
I/O
I/O
I/O
TCK, I/O
I/O
TCK, I/O
I/O
B2
I/O
I/O
B3
I/O
I/O
VCCI
I/O
VCCI
I/O
B4
PRA, I/O
CLKA
I/O
PRA, I/O
CLKA
I/O
B5
F2
I/O
I/O
B6
F3
I/O
I/O
B7*
C1
C2
C3
C4
C5
C6
C7
D1
D2
D3
D4
GND/LP*
I/O
GND/LP*
I/O
F4
I/O
I/O
F5
HCLK
I/O
HCLK
I/O
TDI, I/O
VCCI
GND
CLKB
VCCA
I/O
TDI, I/O
VCCI
GND
CLKB
VCCA
I/O
F6
F7
TDO, I/O
I/O
TDO, I/O
I/O
G1
G2
G3
G4
G5
G6
G7
I/O
I/O
I/O
I/O
PRB, I/O
VCCA
I/O
PRB, I/O
VCCA
I/O
I/O
I/O
TMS
GND
GND
TMS
GND
GND
I/O
I/O
Note: *Please read the LP pin descriptions for restrictions on
their use.
Note: *Please read the LP pin descriptions for restrictions on
their use.
v4.2
2-7
e X Fa m ily FPGAs
128-Pin CSP
A1 Ball Pad Corner
2
3
4
5
6
8
12
1
7
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
Figure 2-4 • 128-Pin CSP (Top View )
2 -8
v 4 . 2
e X Fa m ily FPGAs
128-Pin CSP
128-Pin CSP
e X64
e X128
e X256
e X64
e X128
e X256
Pin Nu m b e r
A1
Fu n ct io n
Fu n ct io n
Fu n ct io n
Pin Nu m b e r
C10
C11
C12
D1
Fu n ct io n
Fu n ct io n
Fu n ct io n
I/O
I/O
TCK, I/O
VCCI
I/O
I/O
TCK, I/O
VCCI
I/O
NC
I/O
I/O
I/O
I/O
A2
TCK, I/O
VCCI
I/O
NC
A3
I/O
I/O
I/O
A4
NC
I/O
I/O
A5
I/O
I/O
I/O
D2
I/O
I/O
I/O
A6
VCCA
I/O
VCCA
I/O
VCCA
I/O
D3
I/O
I/O
I/O
A7
D4
I/O
I/O
I/O
A8
I/O
I/O
I/O
D5
I/O
I/O
I/O
A9
VCCI
I/O
VCCI
I/O
VCCI
I/O
D6
GND
I/O
GND
I/O
GND
I/O
A10
A11
A12
B1
D7
I/O
I/O
I/O
D8
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
D9
TMS
I/O
TMS
I/O
TMS
I/O
D10
D11
D12
E1
I/O
I/O
I/O
B2
I/O
I/O
I/O
B3
I/O
I/O
I/O
VCCI
NC
VCCI
I/O
VCCI
I/O
B4
I/O
I/O
I/O
B5
I/O
I/O
I/O
E2
VCCI
I/O
VCCI
I/O
VCCI
I/O
B6
PRA, I/O
CLKB
I/O
PRA, I/O
CLKB
I/O
PRA, I/O
CLKB
I/O
E3
B7
E4
GND
GND
I/O
GND
GND
I/O
GND
GND
I/O
B8
E9
B9
I/O
I/O
I/O
E10
E11*
E12
F1
B10
B11
B12
C1
I/O
I/O
I/O
GND/LP*
VCCA
NC
GND/LP*
VCCA
I/O
GND/LP*
VCCA
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
F2
NC
I/O
I/O
C2
TDI, I/O
I/O
TDI, I/O
I/O
TDI, I/O
I/O
F3
NC
I/O
I/O
C3
F4
I/O
I/O
I/O
C4
I/O
I/O
I/O
F9
GND
NC
GND
I/O
GND
I/O
C5
I/O
I/O
I/O
F10
F11
F12
G1
C6
CLKA
I/O
CLKA
I/O
CLKA
I/O
I/O
I/O
I/O
C7
I/O
I/O
I/O
C8
I/O
I/O
I/O
NC
I/O
I/O
C9
I/O
I/O
I/O
G2
TRST, I/O
TRST, I/O
TRST, I/O
Note: *Please read the LP pin descriptions for restrictions on
Note: *Please read the LP pin descriptions for restrictions on
their use.
their use.
v4.2
2-9
e X Fa m ily FPGAs
128-Pin CSP
128-Pin CSP
e X64
e X128
e X256
e X64
e X128
e X256
Pin Nu m b e r
G3
G4
G9
G10
G11
G12
H1
Fu n ct io n
Fu n ct io n
Fu n ct io n
Pin Nu m b e r
K8
Fu n ct io n
Fu n ct io n
Fu n ct io n
I/O
I/O
GND
GND
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
NC
K9
I/O
K10
K11
K12
L1
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
L2
I/O
I/O
I/O
H2
L3
NC
I/O
I/O
H3
VCCI
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
L4
I/O
I/O
I/O
H4
L5
I/O
I/O
I/O
H9
L6
I/O
I/O
I/O
H10
H11
H12
J1
VCCI
VCCA
NC
VCCI
VCCA
I/O
VCCI
VCCA
I/O
L7
I/O
I/O
I/O
L8
I/O
I/O
I/O
L9
I/O
I/O
I/O
NC
NC
VCCA
I/O
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
I/O
I/O
I/O
J2
I/O
I/O
NC
I/O
I/O
J3
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
J4
J5
I/O
I/O
I/O
J6
I/O
I/O
I/O
I/O
I/O
I/O
J7
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
J8
I/O
I/O
I/O
J9
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
J10
J11
J12
K1
VCCA
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
K2
I/O
I/O
I/O
I/O
I/O
I/O
K3
I/O
I/O
I/O
I/O
I/O
I/O
K4
I/O
I/O
I/O
Note: *Please read the LP pin descriptions for restrictions on
their use.
K5
I/O
I/O
I/O
K6
PRB, I/O
HCLK
PRB, I/O
HCLK
PRB, I/O
HCLK
K7
Note: *Please read the LP pin descriptions for restrictions on
their use.
2 -1 0
v 4 . 2
e X Fa m ily FPGAs
180-Pin CSP
A1 Ball Pad Corner
12
1
2
3
4
5
6
7
9 10
14
13
8
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 2-5 • 180-Pin CSP
v4.2
2-11
e X Fa m ily FPGAs
180-Pin CSP
180-Pin CSP
180-Pin CSP
180-Pin CSP
Pin
e X256
Pin
e X256
Pin
e X256
Pin
e X256
Nu m b e r
Fu n ct io n
Nu m b e r
Fu n ct io n
Nu m b e r
Fu n ct io n
Nu m b e r
H11
H12
H13
H14
J1
Fu n ct io n
A1
A2
I/O
C5
I/O
I/O
E9
GND
I/O
I/O
I/O
I/O
C6
E10
E11
E12
E13
E14
F1
A3
GND
NC
C7
PRA, I/O
CLKB
I/O
I/O
I/O
A4
C8
I/O
I/O
A5
NC
C9
VCCI
I/O
I/O
A6
NC
C10
C11
C12
C13
C14
D1
I/O
J2
GND
I/O
A7
NC
I/O
I/O
J3
A8
NC
GND
I/O
F2
I/O
J4
VCCI
GND
I/O
A9
NC
F3
VCCI
I/O
J5
A10
A11
A12
A13
A14
B1
NC
I/O
F4
J10
J11
J12
J13
J14
K1
NC
I/O
F5
GND
GND
I/O
VCCI
VCCA
I/O
I/O
D2
I/O
F10
F11
F12*
F13
F14
G1
I/O
D3
TDI, I/O
I/O
I/O
D4
GND/LP*
VCCA
I/O
I/O
I/O
D5
I/O
I/O
B2
I/O
D6
I/O
K2
VCCA
I/O
B3
TCK, I/O
VCCI
I/O
D7
CLKA
I/O
VCCA
I/O
K3
B4
D8
G2
K4
VCCI
I/O
B5
D9
I/O
G3
I/O
K5
B6
I/O
D10
D11
D12
D13
D14
E1
I/O
G4
I/O
K6
I/O
B7
VCCA
I/O
I/O
G5
I/O
K7
I/O
B8
I/O
G10
G11
G12
G13
G14
H1
GND
I/O
K8
GND
I/O
B9
I/O
I/O
K9
B10
B11
B12
B13
B14
C1
VCCI
I/O
I/O
I/O
K10
K11
K12
K13
K14
L1
GND
I/O
I/O
I/O
I/O
E2
I/O
VCCA
I/O
I/O
I/O
E3
I/O
I/O
I/O
E4
I/O
H2
I/O
I/O
I/O
E5
I/O
H3
TRST, I/O
I/O
I/O
C2
TMS
I/O
E6
I/O
H4
L2
I/O
C3
E7
GND
I/O
H5
GND
GND
L3
I/O
C4
I/O
E8
H10
L4
I/O
Note: *Please read the LP
pin descriptions for
restrictions on their
use.
Note: *Please read the LP
pin descriptions for
restrictions on their
use.
Note: *Please read the LP
pin descriptions for
restrictions on their
use.
Note: *Please read the LP
pin descriptions for
restrictions on their
use.
2 -1 2
v 4 . 2
e X Fa m ily FPGAs
180-Pin CSP
180-Pin CSP
Pin
e X256
Pin
e X256
Nu m b e r
Fu n ct io n
Nu m b e r
Fu n ct io n
L5
I/O
I/O
N9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
NC
NC
GND
I/O
L6
N10
N11
N12
N13
N14
P1
L7
PRB, I/O
HCLK
I/O
L8
L9
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
I/O
I/O
TDO, I/O
I/O
P2
P3
I/O
P4
I/O
P5
I/O
P6
I/O
P7
I/O
P8
I/O
P9
I/O
P10
P11
P12
P13
I/O
I/O
I/O
I/O
Note: *Please read the LP
pin descriptions for
restrictions on their
use.
I/O
I/O
VCCI
I/O
I/O
N2
GND
I/O
N3
N4
I/O
N5
I/O
N6
I/O
N7
I/O
N8
VCCA
Note: *Please read the LP
pin descriptions for
restrictions on their
use.
v4.2
2-13
e X Fa m ily FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Pre vio u s ve rsio n Ch a n g e s in cu rre n t ve rsio n (v4.2)
Pa g e
v4.1
v4.0
The "eX Timing Model" was updated.
1-18
1-12
1-17
1-i
The "Development Tool Support" section was updated.
The "Package Thermal Characteristics" section was updated.
The "Product Profile" section was updated.
v3.0
The "Ordering Information" section was updated.
The "Temperature Grade Offerings" section is new.
The "Speed Grade and Temperature Grade Matrix" section is new.
The "General Description" section was updated.
The "Clock Resources" section was updated.
1-ii
1-ii
1-ii
1-1
1-4
Table 1-1 • Connections of Routed Clock Networks, CLKA and CLKB is new.
The "User Security" section was updated.
1-4
1-5
The "I/O Modules" section was updated.
1-5
The "Hot Swapping" section was updated.
1-6
The "Power Requirements" section was updated.
The "Low Power Mode" section was updated.
1-6
1-6
The "Boundary Scan Testing (BST)" section was updated.
The "Dedicated Test Mode" section was updated.
The "Flexible Mode" section was updated.
1-9
1-9
1-9
Table 1-5 • Boundary-Scan Pin Configurations and Functions is new.
The "TRST Pin" section was updated.
1-9
1-9
The "Probing Capabilities" section is new.
1-10
1-10
1-10
1-10
1-11
1-12
1-13
1-21
1-26
1-26
1-26
1-26
The "Programming" section was updated.
The "Probing Capabilities" section was updated.
The "Silicon Explorer II Probe" section was updated.
The "Design Considerations" section was updated.
The "Development Tool Support" section was updated.
The "Absolute Maximum Ratings*" section was updated.
The "Temperature and Voltage Derating Factors" section was updated.
The "TDI, I/O Test Data Input" section was updated.
The "TDO, I/O Test Data Output" section was updated.
The "TMS Test Mode Select" section was updated.
The "TRST, I/O Boundary Scan Reset Pin" section was updated.
v 4 . 2
3-1
e X Fa m ily FPGAs
v3.0
All VSV pins were changed to VCCA. The change affected the following pins:
64-Pin TQFP –Pin 36
100-Pin TQFP –Pin 57
49-Pin CSP –Pin D5
128-Pin CSP–Pin H11 and Pin J1 for eX256
180-Pin CSP –Pins J12 and K2
v2.0.1
The "Recommended Operating Conditions" section has been changed.
The "3.3V LVTTL Electrical Specifications" section has been updated.
The "5.0V TTL Electrical Specifications" section has been updated.
The "Total Dynamic Power (mW)" section is new.
1-13
1-15
1-15
1-8
The "System Power at 5% , 10% , and 15% Duty Cycle" section is new.
The "eX Timing Model" section has been updated.
1-8
1-18
1-5
Advanced v0.4
The I/O Features table, Table 1-2 on page 1-5, was updated.
The table, "Standby Power of eX Devices in LP Mode Typical Conditions, VCCA, VCCI = 1-6
2.5V, TJ = 25× C" section, was updated.
"Typical eX Standby Current at 25°C" section is a new table.
1-13
The table in the section, "Package Thermal Characteristics" section has been updated for 1-17
the 49-Pin CSP.
The "eX Timing Model" section has been updated.
1-18
The timing numbers found in, "eX Family Timing Characteristics" section have been 1-22
updated.
The VSV pin has been added to the "Pin Description" section.
1-26
Please see the following pin tables for the VSV pin and an important footnote including the 2-1, 2-3, 2-6, 2-11
pin: "64-Pin TQFP","100-Pin TQFP" ,, ,"128-Pin CSP", and "180-Pin CSP" .
The figure, "64-Pin TQFP" section has been updated.
2-1
1-i
1-i
Advanced v0.3
Advanced v0.2
In the Product Profile, the Maximum User I/Os for eX64 was changed to 84.
In the Product Profile table, the Maximum User I/Os for eX128 was changed to 100.
The Mechanical Drawings section has been removed from the data sheet. The mechanical
drawings are now contained in a separate document, “Package Characteristics and
Mechanical Drawings,” available on the Actel web site.
A new section describing "Clock Resources"has been added.
A new table describing "I/O Features"has been added.
The "Pin Description" section has been updated and clarified.
1-4
1-5
1-26
The original Electrical Specifications table was separated into two tables (2.5V and 3.3/ Page 8 and 9
5.0V). In both tables, several different currents are specified for VOH and VOL
.
A new table listing 2.5V low power specifications and associated power graphs were added. page 9
Pin functions for eX256 TQ100 have been added to the " 100-Pin TQFP"table. 2-3
A CS49 pin drawing and pin assignment table including eX64 and eX128 pin functions have page 26
been added.
A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256 pin pages 26-27
functions have been added.
A CS180 pin drawing and pin assignment table for eX256 pin functions have been added. pages 27, 31
Advanced v.1
The following table note was added to the eX Timing Characteristics table for clarification: pages 14-15
Clock skew improves as the clock network becomes more heavily loaded.
3 -2
v 4 . 2
e X Fa m ily FPGAs
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
v 4 . 2
3-3
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
2061 Stierlin Court
Mountain View, CA
94043-4655 USA
Dunlop House, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
EXOS Ebisu Bldg. 4F
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Tokyo 150 Japan
39th Floor, One Pacific Place
88 Queensway, Admiralty
Hong Kong
Phone 650.318.4200
Fax 650.318.4600
Phone +44 (0)1276 401 450
Fax +44 (0) 1276 401 490
Phone +81.03.3445.7671
Fax +81.03.3445.7668
Phone +852.227.35712
Fax +852.227.35999
5172154-7/06.04
相关型号:
EX128-FCS128X79
Field Programmable Gate Array, 256 CLBs, 6000 Gates, 178MHz, 384-Cell, CMOS, PBGA128, 0.80 MM PITCH, PLASTIC, CSP-128
ACTEL
EX128-FCS49I
Field Programmable Gate Array, 6000 Gates, 178MHz, 384-Cell, CMOS, PBGA49, 0.8 MM PITCH, CSP-49
ACTEL
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