M1425-VQG100C_技术文档

Actel

Mask Programmed Gate Arrays

F e a t u r e s

• Available in commercial or industrial temperature ranges

• PLCC, PQFP, VQFP, and TQFP packages available

• Mask Programmed versions of Actel Field Programmable

Gate Arrays (FPGAs)

• Meets all internal worst-case FPGA performance

specifications

• Significant cost reduction for medium- to high-volume

applications

• Lower I/O capacitance than FPGA

• Lower power dissipation than FPGA

• Pin-for-pin compatible with Actel FPGAs

• PCI Local Bus Revision 2 Compliant

D e s c r i p t i o n

• Automatic translation from Actel FPGA netlist to MPGA

• Test vectors generated from customer simulation vectors

• Short lead times for prototype and production devices

The Actel Mask Programmed Gate Array (MPGA) products

are masked versions of the popular Actel FPGA families.

These semi-custom devices offer the customer a design path

that provides significant cost reduction without significant

risk or engineering effort. For medium- to high-volume

applications in which the design is fixed, the Actel FPGA used

for prototyping and initial production can be replaced by the

corresponding MPGA device.

• MPGA available for all ACT 1, ACT 2, 1200XL, ACT 3, and

3200DX devices

• Device sizes from 1,200 to 10,000 gates

• Up to 175 user I/Os

P r o d u c t F a m i l y P r o f i l e

Capacity

Available Packages

MPGA

Device

Type

Gate Array

Equivalent

Gates

PLD

Equivalent

Gates

Flip-Flops

User I/Os

(Maximum) (Maximum)

PLCC

PQFP

VQFP

TQFP

M1010

M1020

1,200

2,000

3,000

6,000

147

273

57

69

44, 68-pin

100-pin

80-pin

—

44, 68,

84-pin

M1225

M1240

M1280

2,500

4,000

8,000

6,250

10,000

20,000

382

568

998

83

104

140

84-pin

100-pin

—

100, 144-pin

176-pin

100, 160,

208-pin

—

M1415

M1425

1,500

2,500

3,750

6,250

312

435

80

100

140

167

175

126

152

176

202

250

288

84-pin

—

100-pin

100, 160-pin

160-pin

100-pin

—

M1440

4,000

10,000

15,000

25,000

1,600

706

176-pin

—

M1460

6,000

976

160, 208-pin

208-pin

M14100

M3265

10,000

6,500

1153

747

—

84-pin

—

100, 160-pin

160, 208-pin

208, 240-pin

240-pin

176-pin

—

M32100

M32140

M32200

M32300

M32400

10,000

14,000

20,000

30,000

40,000

25,000

35,000

50,000

75,000

100,000

1031

1410

1822

2804

3759

—

S e p t e m b e r 1 9 9 7

1 -3 8 9

The granular, regular structure of the Actel antifuse-based

FPGA products enables easy conversion to MPGA. Actel

provides all required engineering services to convert the

cost-reduction path becomes a key factor to ensure continued

success and profitability of the end product. Once the design

has stabilized and volumes are increasing, a choice can be

customer design from FPGA to MPGA, using proprietary made to convert the design to an MPGA. Since the MPGA

software to automatically convert the FPGA logic design into product is pin-for-pin compatible with the FPGA, no board

the MPGA device. Test vector generation is made easy by redesign is required, and the MPGA can directly replace the

software that converts the customer's third-party simulation

vectors into the final vectors used to test the device in

production.

FPGA.

A typical design process uses the FPGA device as the

prototyping and initial production product of choice and

converts to the MPGA as volumes warrant. Figure 1 shows the

design process for Actel FPGA and MPGA devices. This option

gives you the flexibility to adjust volumes as the demand for

the end product changes. Since the MPGA is a semicustom

device, all production is built to your order. If the design is

All Actel MPGA devices are pin-for-pin compatible with the

corresponding FPGA, and therefore no board redesign is

required. MPGA devices meet all worst-case timing

specifications of the FPGA devices. MPGA devices are

available for all plastic packaged devices from ACT 1, ACT 2,

1200XL, ACT 3, and 3200DX families. See the “Product Plan” already completed in the FPGA, any demand upsides can be

on page 1-260 for a detailed list of available device and

package combinations.

satisfied by temporarily switching production back to the

FPGA. Since Actel FPGAs are standard off-the-shelf devices,

additional product requirements can be met within a short

lead time.

A c t e l F P G A t o M P G A D e s i g n F l o w

Actel’s three families of FPGA devices offer a wide selection

of device sizes, package choices, performance characteristics,

and price points. The FPGA families provide the ideal

prototyping tool and are cost-effective for low- to

medium-volume applications. As volumes increase, a

The Actel FPGA devices offer the easiest and fastest way to

bring a new product to market, and the three FPGA families

offer a wide selection of low-cost, high-performance devices.

The addition of the MPGA devices offers a simple, low-risk

cost-reduction path as production volumes increase.

1 -3 9 0

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

CAE Tools

Design Entry

Simulation

Designer/Designer

Advantage System

• ACTmap FPGA Fitter

• ACTgen Macro Builder

• Auto Place and Route

• ChipEdit

Design

Start

Checklist

MPGA

back-annotation

(optional)

simulation

vectors

netlist

• Timer

• Backannotation

Actel MPGA Tools

• Simulation

• Timing Analysis

• Power Calculation

FPGA Programmers

• Activator 2

• Activator 2S

• Data I/O Unisite, 3900

Autosite

Actel MPGA

prototype

devices

Actel

FPGA

devices

Device Test

In-System Test

Prototype Approval

Final Review

Actel MPGA

production

devices

FPGA Design Flow

MPGA Design Flow

(Note: Shaded items are completed by the customer.)

Figure 1 • Actel Device Design Flow

1 -3 9 1

P r o d u c t P l a n

Availability

Application

ACT 1 Family

Commercial

Industrial

M1010 Device

44-pin Plastic Leaded Chip Carrier (PLCC)

68-pin Plastic Leaded Chip Carrier (PLCC)

80-pin Very Thin Plastic Quad Flatpack (VQFP)

100-pin Plastic Quad Flatpack (PQFP)

✔

—

✔

M1020 Device

44-pin Plastic Leaded Chip Carrier (PLCC)

68-pin Plastic Leaded Chip Carrier (PLCC)

80-pin Very Thin Plastic Quad Flatpack (VQFP)

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

✔

—

✔

ACT 2/1200XL Family

M1225 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

100-pin Thin Plastic Quad Flatpack (TQFP)

✔

—

M1240 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

144-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Plastic Quad Flatpack (TQFP)

✔

—

M1280 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Plastic Quad Flatpack (TQFP)

✔

—

ACT 3 Family

M1415 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

100-pin Very Thin Plastic Quad Flatpack (VQFP)

✔

—

Note:M1425 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

100-pin Very Thin Plastic Quad Flatpack (VQFP)

160-pin Plastic Quad Flatpack (PQFP)

✔

—

✔

M1440 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Plastic Quad Flatpack (VQFP)

160-pin Plastic Quad Flatpack (PQFP)

✔

—

✔

176-pin Thin Plastic Quad Flatpack (TQFP)

—

M1460 Device

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Plastic Quad Flatpack (TQFP)

208-pin Plastic Quad Flatpack (PQFP)

✔

—

✔

M14100 Device

208-pin Plastic Quad Flatpack (PQFP)

✔

1 -3 9 2

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

P r o d u c t P l a n (c o n t in u e d )

Availability

Application

3200DX Family

M3265 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Plastic Quad Flatpack (TQFP)

✔

M32100 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

160-pin Plastic Quad Flatpack (PQFP)

208-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Plastic Quad Flatpack (TQFP)

P

M32140 Device

84-pin Plastic Leaded Chip Carrier (PLCC)

160-pin Plastic Quad Flatpack (PQFP)

208-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Plastic Quad Flatpack (TQFP)

✔

M32200 Device

208-pin Plastic Quad Flatpack (PQFP)

240-pin Plastic Quad Flatpack (PQFP)

176-pin This Plastic Quad Flatpack (TQFP)

✔

M32300 Device

208-pin Plastic Quad Flatpack (PQFP)

240-pin Plastic Quad Flatpack (PQFP)

✔

Availability:

✔

P

—

=

Available

Planned

Not Planned

A C T 1 D e v i c e R e s o u r c e s

User I/Os

Gate Array

Equivalent

Gates

PLCC

PQFP

VQFP

80-pin

MPGA

Device Type

44-pin

68-pin

84-pin

100-pin

M1010

M1020

1200

2000

34

57

69

57

69

57

69

A C T 2 /1 2 0 0 X L D e v i c e R e s o u r c e s

User I/Os

Gate Array

Equivalent

Gates

PLCC

84-pin

PQFP

VQFP

TQFP

MPGA

Device Type

100-pin

144-pin

160-pin

208-pin

100-pin

176-pin

M1225

M1240

M1280

2500

4000

8000

72

83

—

104

—

83

—

104

140

125

140

1 -3 9 3

A C T 3 D e v i c e R e s o u r c e s

User I/Os

PQFP

Gate Array

Equivalent

Gates

PLCC

84-pin

VQFP

TQFP

MPGA

Device Type

100-pin

160-pin

208-pin

100-pin

176-pin

M1415

M1425

M1440

M1460

M14100

1500

2500

4000

6000

10000

70

—

80

—

80

83

—

100

131

—

140

151

—

167

175

3 2 0 0 D X D e v i c e R e s o u r c e s

User I/Os

PQFP

Gate Array

Equivalent

Gates

PLCC

84-pin

TQFP

MPGA

Device Type

100-pin

160-pin

208-pin

240-pin

176-pin

M3265

M32100

M32140

M32200

M32300

M32400

6500

10000

14000

20000

30000

40000

72

—

83

—

125

—

126

151

—

156

176

—

TBD

—

O r d e r i n g I n f o r m a t i o n

M14100

–

RQ

208

C

Application (Temperature Range)

C = Commercial (0 to +70°C)

I

= Industrial (–40 to +85°C)

Package Lead Count

Package Type

PL = Plastic Leaded Chip Carrier (PLCC)

PQ = Plastic Quad Flatpack (PQFP)

TQ = Thin (1.4 mm) Plastic Quad Flatpack (TQFP)

VQ = Very Thin (1.0 mm) Plastic Quad Flatpack (VQFP)

RQ = Power Plastic Quad Flatpack (RQFP)

Part Number

M1010= 1200 Gates—ACT 1

M1020= 2000 Gates—ACT 1

M1225= 2500 Gates—ACT 2/1200XL

M1240= 4000 Gates—ACT 2/1200XL

M1280= 8000 Gates—ACT 2/1200XL

M1415= 1500 Gates—ACT 3

M1425= 2500 Gates—ACT 3

M1440= 4000 Gates—ACT 3

M1460= 6000 Gates—ACT 3

M14100=10000 Gates—ACT 3

M3265= 6500 Gates—3200DX

M32100=10000 Gates—3200DX

M32140=14000 Gates—3200DX

M32200=20000 Gates—3200DX

M32300=30000 Gates—3200DX

M32400=40000 Gates—3200DX

1 -3 9 4

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

1

A b s o l u t e M a x i m u m R a t i n g s

R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s

F r e e a ir t e m p e r a t u r e r a n g e

Parameter

Commercial Industrial Units

Symbol

Parameter

Limits

Units

Temperature Range

0 to +70

–40 to +85

°C

%V

V

DC Supply Voltage

Input Voltage

–0.3 to +7.0

V

CC

Power Supply

Tolerance

±5

±10

CC

–0.3 to V +0.3

I

CC

V

Output Voltage

–0.3 to V +0.3

O

CC

I/O Source Sink

Current

I

±20

mA

IO

T

Storage Temperature

–55 to +125

°C

STG

Note:

1. Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. Exposure

to absolute maximum rated conditions for extended periods

may affect device reliability. Device should not be operated

outside the Recommended Operating Conditions.

E l e c t r i c a l S p e c i f i c a t i o n s

Commercial

Industrial

Symbol

Parameter

Test Condition

Min.

Max.

Min.

Max.

Units

1,2

V

HIGH Level Output

I

= –6 mA (CMOS)

3.7

2.4

3.7

2.4

V

OH

OL

3

= –8 mA (TTL)

1,2

V

LOW Level Output

= +6 mA (CMOS)

0.4

V

OL

3

= +8 mA (TTL)

V

HIGH Level Input

LOW Level Input

Input Leakage

TTL Inputs

2.0

–0.3

–1

V

+ 0.3

2.0

–0.3

–1

V + 0.3

CC

V

IH

IL

CC

0.8

+1

0.8

V

I

V = V or GND

+1

+10

10

µA

pF

IN

OZ

I

CC

3-state Output Leakage

V = V or GND

–10

+10

10

–10

O

CC

3

C

I/O Capacitance

IO

I

Standby Supply Current

V = V or GND,

CC(S)

I

CC

I

= 0 mA

100

500

µA

O

Notes:

1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required.

2. Tested one output at a time, V = min.

CC

3. Not tested, for information only.

1 -3 9 5

C h i p -t o -C h i p P e r f o r m a n c e

Chip #1

Chip #2

35 pF

up to 1000

clock loads

CLK

t

(GLOBAL CLOCK

TO OUTPUT PAD)

TRACE

(INPUT SETUP)

Chip-to-Chip Performance

(Worst-Case Commercial)

t

(GLOBAL CLOCK

TO OUPUT PAD)

t

Total

16.8

MHz

60

TRACE

(INPUT SETUP)

Actel MPGA

12.7

1.0

3.1

1 -3 9 6

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

P i n D e s c r i p t i o n

note between the device types. First, dedicated FPGA global

and debugging pins are general purpose MPGA I/O pins. Also,

dedicated FPGA programming voltage pins are Vcc or ground

pins on an MPGA. Refer to Table 1 for a complete

cross-reference of pin descriptions between the FPGA and

MPGA.

Package pin assignments for an FPGA design are directly

transferred to the equivalent MPGA package because all I/O

and power pins are located in identical positions. While the

conversion of package pin assignments is transparent in the

end product, there are two small functional differences to

Table 1 • FPGA-to-MPGA Pin Cross-Reference

FPGA Pin Description

MPGA Pin Description

No Change

CLK

Clock (ACT 1 only)

→

TTL Clock input for ACT 1 global clock distribution net-

work. This pin can also be used as an I/O.

If desired, TTL Clock input signals may be moved to any

MPGA I/O location.

CLKA Clock A (ACT 3, 3200DX, 1200XL, and ACT 2

only)

No Change

If desired, TTL Clock input signals may be moved to any

MPGA I/O location.

TTL Clock input for clock distribution networks. This pin

can also be used as an I/O.

CLKB Clock B (ACT 3, 3200DX, 1200XL, and ACT 2

only)

No Change

→

If desired, TTL Clock input signals may be moved to any

MPGA I/O location.

TTL Clock input for clock distribution networks. This pin

can also be used as an I/O.

DCLK Diagnostic Clock

I/O

→

TTL Clock input for diagnostic probe and device program-

ming. Function is controlled by the MODE pin.

This pin is used as an I/O only. It is not used for diagnos-

tic probe or device programming functions on an MPGA.

GND

Ground

LOW supply voltage.

HCLK Dedicated (Hard-wired) Array Clock

(ACT 3 only)

No Change

→

If desired, TTL Clock input signals may be moved to any

MPGA I/O location.

TTL Clock input for ACT 3 sequential modules. This pin

can also be used as an I/O.

I/O

Input/Output

I/O

The I/O pin functions as an input, output, three-state, or

bidirectional buffer. Unused pins are automatically driven

LOW by the Designer software.

User-deﬁned MPGA I/O pins function identically to their

FPGA counterparts. However, unused pins are NC (no

connection) pins.

IOCLK Dedicated (Hard-wired) I/O Clock

(ACT 3 only)

No Change

If desired, TTL Clock input signals may be moved to any

MPGA I/O location.

TTL Clock input for ACT 3 I/O modules. This pin can also

be used as an I/O.

IOPCL Dedicated (Hard-wired) I/O Preset/Clear

(ACT 3 only)

No Change

If desired, this input signal may be moved to any MPGA

I/O location.

TTL input for ACT 3 I/O preset or clear. This pin can also

be used as an I/O.

MODE Mode

TEST (No Connection)

The MODE pin controls the use of diagnostic pins (DCLK,

PRA, PRB, SDI). When the MODE pin is HIGH, the spe-

cial functions are active.When the MODE pin is LOW, the

pins function as I/Os.

→

This pin is reserved for parametric testing and should be

connected to ground (LOW supply voltage).

1 -3 9 7

Table 1 • FPGA-to-MPGA Pin Cross-Reference (continued)

FPGA Pin Description

MPGA Pin Description

NC No Connection

NC

No Connection

→

This pin is not connected to circuitry within the device.

PRA

Probe A

I/O

The Probe A pin is used for FPGA diagnostics. Function

is controlled by the MODE pin.

This pin is used as an I/O only. It is not used for diagnos-

tic probe or device programming functions on an MPGA.

PRB

Probe B

I/O

→

The Probe B pin is used for FPGA diagnostics. Function

is controlled by the MODE pin.

This pin is used as an I/O only. It is not used for diagnos-

tic probe or device programming functions on an MPGA.

QCLKA/B,C,D

Quadrant Clock (Input/Output)

(3200DX only)

No Change

If desired, TTL Clock input signals may be moved to any

MPGA location.

These four pins are the quadrant clock inputs. When not

used as a register control signal, these pins can function

as general purpose I/O.

SDI

Serial Data Input

I/O

→

Serial data input for diagnostic probe and device pro-

gramming. Function is controlled by the MODE pin.

This pin is used as an I/O only. It is not used for diagnos-

tic probe or device programming functions on an MPGA.

TCK

Test Clock (3200DX only)

No Change

Clock signal to shift the JTAG data into the device. This

pin functions as an I/O when the JTAG fuse is not pro-

grammed

TDI

Test Data In (3200DX only)

→

Serial data input or JTAG instructions and data. Data is

shifted in on the rising edge of TCLK. This pin functions

as an I/O when the JTAG fuse is not programmed.

TDO

Test Data Out (3200DX only)

Serial data output for JTAG instructions and test data.

This pin functions as an I/O when the JTAG fuse is not

programmed.

TMS

Test Mode Select (3200DX only)

Serial data input for JTAG test mode. Data is shifted in on

the rising edge of TCLK. This pin functions as an I/O

when the JTAG fuse is not programmed.

V

Supply Voltage

V

CC

→

HIGH supply voltage.

1 -3 9 8

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

M P G A A r c h i t e c t u r e

where

C_EQis the equivalent capacitance in picofarads (pF)

The Actel MPGA is built using a “sea-of-gates” architecture. A

solid, regularly ordered array of transistors is overlaid with a

multilevel metal interconnect. Surrounding this logic core is

an array of programmable power and I/O pads. Separate grids

provide power and ground supplies for the core logic and I/O

cells.

V is the DC supply voltage in volts (V)

CC

f is the switching frequency in megahertz (MHz)

Upon receipt of the “Design Start Checklist” and associated

materials, Actel calculates the MPGA active power

dissipation for each design based on this formula. This

calculation is immediately relayed to you so that you can

update system power specifications accordingly. Typically,

power dissipation of an Actel design is significantly lower for

the MPGA version versus the FPGA version.

The highly dense structure of Actel MPGAs provides for a

cost-effective solution while maintaining the high

performance of each particular design. This architecture

reduces die size for low cost while minimizing gate length and

shortening routing paths for excellent system performance.

The robust power supply grids provide high I/O current drive

without sacrificing high noise immunity. Since Actel FPGAs

use a similar gate array architecture, design migration is a

straightforward, simple process. Because of the advanced

technology employed by the MPGA, the internal and external

performance of each design is virtually assured to be

preserved or improved after migration. To simplify migration

further, the I/O pads are carefully arranged to allow FPGA pin

assignments to be directly transferred to the full line of

MPGA packages. For more information about the ease of

design migration from Actel FPGAs to MPGAs, see the

application note “Designing for Migration to Actel MPGAs.”

T i m i n g C h a r a c t e r i s t i c s

The timing characteristics for Actel MPGA devices are

consistent across family and device types. Typical I/O buffer,

internal logic cell, and internal routing delays are common to

all MPGA devices. The advanced technology of the devices

ensures converted designs meet or exceed FPGA

performance. Refer to the MPGA Timing Model diagram and

Timing Characteristics chart for detailed timing and delay

estimates.

T i m i n g D e r a t i n g

Timing derating factors due to temperature, voltage, and

process variations are summarized in the following tables and

graphs. Use these derating factors to determine device

performance at any particular condition within the electrical

and environmental specifications.

P o w e r D i s s i p a t i o n

The power dissipation for an Actel MPGA is composed of two

parts: static power and active power. The static power is a

product of the standby supply current (Icc) and the DC

supply voltage (Vcc). Specifications for Icc and Vcc are

located in the “Electrical Specifications” section of this data

sheet. The active power is a product of equivalent

capacitance, square of the DC supply voltage, and average

switching frequency of the circuit. It is expressed in the

formula

MPGA devices are manufactured in a CMOS process.

Therefore, device performance varies according to

temperature, voltage, and process variations. Minimum

timing parameters reflect maximum operating voltage,

minimum operating temperature, and best-case processing.

Maximum timing parameters reflect minimum operating

voltage, maximum operating temperature, and worst-case

processing.

2

Power (µW) = C_EQ• V

• f

CC

1 -3 9 9

T i m i n g D e r a t i n g F a c t o r , T e m p e r a t u r e a n d V o l t a g e

Industrial

Minimum

0.85

Maximum

1.07

(Commercial Minimum/Maximum Speciﬁcation) x

T i m i n g D e r a t i n g F a c t o r f o r D e s i g n s a t T y p i c a l T e m p e r a t u r e ( T = 2 5 °C )

J

a n d V o l t a g e ( V

= 5 . 0 V )

C C

(Commercial Maximum Speciﬁcation) x

0.86

Temperature Derating Curve

Voltage Derating Curve

1.40

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

1.30

1.20

1.10

1.00

0.90

0.80

0.70

Factor

4.5 4.75 5.0 5.25 5.5

(Volts)

-20 0 20 40 60 80

V

Junction Temperature (°C)

CC

Note: This derating factor applies to all routing and propagation delays.

1 -4 0 0

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

M P G A T i m i n g M o d e l

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

Combinatorial

Logic Module

I/O Module

t

= 0.3 ns

IRD2

t

= 2.0ns

INY

I/O Module

t

= 1.5 ns

t

= 0.2 ns

= 0.7 ns

= 1.4 ns

PD

RD1

• • •

RD4

RD8

t

= 5.5 ns

= 6.1 ns

DHL

DLH

Sequential

Logic Module

D

Q

t

= 1.5 ns

CO

t

= 1.5 ns

= 0.0 ns

SUD

t

HD

Array Clock

f

= 167 MHz

MAX

t

= t

= 5.0 ns

CKH

CKL

O u t p u t B u f f e r D e l a y s

E

D

PAD To AC test loads (shown below)

TRIBUFF

V

CC

In

GND

1.4 V

50%

En

Out

GND

En

50%

GND

50%

CC

50%

V

OH

1.4 V

90%

Out

1.4 V

10%

1.4 V

V

GND

OL

t

ENHZ

DLH

DHL

ENZL

ENLZ

ENZH

1 -4 0 1

A C T e s t L o a d s

Load 2

Load 1

(Used to measure rising/falling edges)

(Used to measure propagation delay)

V

GND

CC

To the output under test

35 pF

R to V for t /t

CC

PLZ PZL

R to GND for t

/t

PHZ PZH

R = 1 kΩ

To the output under test

35 pF

I n p u t B u f f e r D e l a y s

M o d u l e D e l a y s

S

A

B

Y

PAD

INBUF

V

CC

GND

S, A or B

50% 50%

V

CC

50%

Out

50%

In

0 V

50%

1. 4 V

1.4 V

GND

V

CC

t

PD

Out

GND

V

50%

Out

CC

GND

50%

t

PD

INY

PD

S e q u e n t i a l M o d u l e T i m i n g C h a r a c t e r i s t i c s

F lip -F lo p s

D

Q

CLK

CLR

(Positive edge triggered)

t

HD

D

t

A

WCLKA

SUD

CLK

t

WCLKA

t

CO

Q

t

CLR

t

WASYN

1 -4 0 2

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

S e q u e n t i a l T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

In p u t B u ffe r La t c h e s (3 2 0 0 DX o n ly )

PAD

DATA

IBDL

G

PAD

CLK

CLKBUF

DATA

G

t

INH

t

INSU

t

HEXT

CLK

t

SUEXT

O u t p u t B u ffe r La t c h e s (3 2 0 0 DX o n ly )

D

G

PAD

OBDLHS

D

t

OUTSU

G

t

OUTH

1 -4 0 3

D e c o d e M o d u l e T i m i n g (3 2 0 0 DX o n ly )

A

B

C

D

E

F

Y

G

V

CC

A–G, H

50%

V

CC

Y

t

PHL

t

PLH

S R A M T i m i n g C h a r a c t e r i s t i c (3 2 0 0 DX o n ly )

Read Port

Write Port

WRAD [5:0]

RDAD [5:0]

LEW

RAM Array

BLKEN

32x8 or 64x4

WEN

REN

(256 bits)

WCLK

RCLK

WD [7:0]

RD [7:0]

1 -4 0 4

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

D u a l -P o r t S R A M T i m i n g W a v e f o r m s

S R AM Wr it e O p e r a t io n (3 2 0 0 DX o n ly )

t

RCKHL

WCLK

t

ADSU

ADH

WD[7:0]

WRAD[5:0]

Valid

WENSU

WENH

BENH

WEN

t

BENSU

Valid

BLKEN

Note: Identical timing for falling-edge clock.

S R AM S y n c h r o n o u s R e a d O p e r a t io n (3 2 0 0 DX o n ly )

t

RCKHL

RCLK

REN

t

RENSU

RENH

t

ADH

ADSU

Valid

RDAD[5:0]

t

RCO

t

DOH

Old Data

New Data

RD[7:0]

Note: Identical timing for falling-edge clock

1 -4 0 5

S R AM As y n c h r o n o u s R e a d O p e r a t io n —T y p e 1 (3 2 0 0 DX o n ly )

((Read Address Controlled)

t

RENHA

t

RENSUA

(Data 2 in hold state)

REN

t

RDADV

RDAD[5:0]

ADDR1

ADDR2

t

RPD

t

DOH

Data 1

Data 2

RD[7:0]

S R AM As y n c h r o n o u s R e a d O p e r a t io n —T y p e 2 (3 2 0 0 DX o n ly )

(Write Address Controlled)

WEN

t

WENSU

WENH

WD[7:0]

WRAD[5:0]

BLKEN

Valid

t

ADH

ADSU

WCLK

t

RPD

t

DOH

Old Data

New Data

RD[7:0]

t

RENH

REN

1 -4 0 6

A c t e l M a s k P r o g r a m m e d G a t e A r r a y s

M P G A T i m i n g C h a r a c t e r i s t i c s

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V

= 4 . 7 5 V, T = 7 0 °C )

J

C C

Preliminary Information

Logic Module Propagation Delays

Parameter

Description

Min.

Max.

Units

t

Internal Array Module

Sequential Clock to Q

1.5

ns

PD

CO

CLR

Asynchronous Clear to Q

1

Predicted Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.2

0.3

0.5

0.7

1.4

ns

RD1

RD2

RD3

RD4

RD8

Logic Module Sequential Timing

t

f

Flip-Flop Data Input Setup

1.5

0.0

1.5

0.0

2.0

8.0

ns

SUD

Flip-Flop Data Input Hold

Latch Data Input Setup

HD

ns

SUD

HD

Latch Data Input Hold

ns

Asynchronous Pulse Width

Flip-Flop Clock Pulse Width

Flip-Flop Clock Input Period

Flip-Flop Clock Frequency

ns

WASYN

WCLKA

A

ns

125

2.0

MHz

MAX

I/O Module Input Propagation Delay

t

Input Data Pad to Y

ns

INY

1

Predicted Input Routing Delays

t

FO=1 Routing Delay

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

0.2

0.3

0.5

0.7

1.4

ns

IRD1

IRD2

IRD3

IRD4

IRD8

Note:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based

on actual routing delay measurements performed on the device prior to shipment.

1 -4 0 7

M P G A T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )

(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )

Preliminary Information

1

I/O Module – TTL Output Timing

Parameter

Description

Min.

Max.

Units

t

Data to Pad, High to Low

Data to Pad, Low to High

Enable to Pad, Z to High

Enable to Pad, Z to Low

Enable to Pad, High to Z

Enable to Pad, Low to Z

Delta Low to High

6.8

3.9

ns

DHL

DLH

4.5

ns

ENZH

ENZL

ENHZ

ENLZ

6.8

ns

3.8

ns

2.0

ns

d

0.05

0.09

ns/pF

TLH

THL

d

Delta High to Low

1

I/O Module – CMOS Output Timing

t

Data to Pad, High to Low

Data to Pad, Low to High

Enable to Pad, Z to High

Enable to Pad, Z to Low

Enable to Pad, High to Z

Enable to Pad, Low to Z

Delta Low to High

5.5

6.1

ns

DHL

DLH

6.7

ns

ENZH

ENZL

ENHZ

ENLZ

5.6

ns

3.8

ns

2.0

ns

d

0.09

0.07

ns/pF

TLH

THL

d

Delta High to Low

Global Clock Networks (for Fanout = 1000)

t

f

Input Low to High

Input High to Low

Min. Pulse Width High

Min. Pulse Width Low

Maximum Skew

5.0

ns

CKH

CKL

PWH

PWL

CKSW

P

2.9

ns

0.4

ns

Minimum Period

6.0

ns

Maximum Frequency

167

MHz

MAX

Note:

1. Delays based on 35pF loading.

1 -4 0 8


型号：	M1425-VQG100C
厂家：	Actel Corporation
描述：	Field Programmable Gate Array, 2500 Gates, 125MHz, CMOS, PQFP100, 1 MM HEIGHT, PLASTIC, VQFP-100 栅
文件：	总20页 (文件大小：105K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M1425-VQG100C [ACTEL]

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