M1A3P1000-1PQ144M_技术文档

v1.0

®

Military ProASIC3/EL Low-Power Flash FPGAs

with Flash*Freeze Technology

Advanced and Pro (Professional) I/Os^††

Features and Benefits

• 700 Mbps DDR, LVDS-Capable I/Os

†

Military Temperature Tested and Qualified

• Each Device Tested from –55°C to 125°C

Firm-Error Immune

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

• Not Susceptible to Neutron-Induced Configuration Loss

†

LVCMOS 2.5 V / 5.0 V Input

Low Power

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

• Dramatic Reduction in Dynamic and Static Power

• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

†

• Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry To / Exit From Low-Power Flash*Freeze

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay (A3PE3000L only)

• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the Military ProASIC®3EL

Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, One with Integrated PLL (ProASIC3) and All

with Integrated PLL (ProASIC3EL)

ƒ

Mode

• Supports Single-Voltage System Operation

H^•igh^LowCa^-Imp^pa^ec^dit^ay^{nce Switches}

• 600 k to 3 M System Gates

• Up to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

H^•igh^ReP^taeⁱⁿr^sfo^Prr^om^gra^amnc^me^{ed Design when Powered Off}

• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

• Configurable

Phase

Shift, Multiply/Divide,

Delay

Capabilities, and External Feedback

• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

systems) and 350 MHz (1.5 V systems)

• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

SRAMs and FIFOs

PCI (1.2 V systems)

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation:

®

to Secure FPGA Contents

H^•igh^Fla-P^she^Lr^of^co^krmance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

– 250 MHz: For 1.2 V Systems

– 350 MHz: For 1.5 V Systems

ARM^®Processor Support in ProASIC3/EL FPGAs

• ARM Cortex™-M1 Soft Processor Available with or without

Debug

Table 1-1 • Military ProASIC3/EL Low-Power Devices

ProASIC3/EL Devices

ARM Cortex-M1 Devices

System Gates

A3PE600L

A3P1000

A3PE3000L

1

M1A3P1000

M1A3PE3000L

600 k

13,824

108

24

1 M

24,576

144

32

3 M

75,264

504

112

1 k

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

1 k

Yes

1

2

Yes

6

Yes

6

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

18

8

4

8

Maximum User I/Os

Package Pins

270

154

620

PQFP

FBGA

PQ208

FG144

FG484

FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for ARM-enabled ProASIC3/EL devices.

†

ƒ

A3P1000 only supports 1.5 V core operation.

Flash*Freeze technology is not available for A3P1000.

†† Pro I/Os are not available on A3P1000.

August 2008

i

Military ProASIC3/EL Low-Power Flash FPGAs

1

I/Os Per Package

ProASIC3/EL

Low-Power

Devices

A3PE600L

A3P1000

A3PE3000L

ARM

Cortex-M1

Devices

M1A3P1000

M1A3PE3000L

Single-

Differential

I/O Pairs

Single-

Differential

I/O Pairs

Single-

Differential

I/O Pairs

Package

PQ208

FG144

FG484

FG896

Notes:

Ended I/O²

–

154

97

–

35

25

–

270

–

135

–

341

620

168

300

–

1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the

datasheet to ensure you are complying with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. "G" indicates RoHS-compliant packages. Refer to "Military ProASIC3/EL Ordering Information" on page iii for the

location of the "G" in the part number.

4. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-

ended user I/Os available is reduced by one.

ii

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Military ProASIC3/EL Ordering Information

_

A3P1000

1

FG

G

144

M

Application (Temperature Range)

M = Military ( 55°C to 125°C Junction Temperature)

Package Lead Count

–

Lead-Free Packaging

Blank = Standard Packaging

G= RoHS-Compliant (Green) Packaging

Package Type

=

FG

PQ

Fine Pitch Ball Grid Array (1.0 mm pitch)

Plastic Quad Flat Pack (0.5 mm pitch)

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

Part Number

Military ProASIC3/EL Devices

A3PE600L = 600,000 System Gates

A3P1000 = 1,000,000 System Gates

A3PE3000L = 3,000,000 System Gates

Military ProASIC3/EL Devices with ARM Cortex-M1

M1A3P1000 = 1,000,000 System Gates

M1A3PE3000L = 3,000,000 System Gates

v1.0

iii

Military ProASIC3/EL Low-Power Flash FPGAs

Temperature Grade Offerings

Package

A3PE600L

A3P1000

A3PE3000L

ARM Cortex-M1 Devices

M1A3P1000

M1A3PE3000L

PQ208

FG144

FG484

FG896

–

M

–

M

–

M

–

Note: M = Military temperature range: –55°C to 125°C junction temperature

Speed Grade and Temperature Grade Matrix

Temperature Grade

Std.

–1

M

✓

Note: M = Military temperature range: –55°C to 125°C junction temperature

Contact your local Actel representative for device availability:

http://www.actel.com/contact/default.aspx.

iv

v1.0

1 – Military ProASIC3/EL Device Family Overview

General Description

The military ProASIC3/EL family of Actel flash FPGAs dramatically reduces dynamic power

consumption by 40% and static power by 50%. These power savings are coupled with

performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability,

and advanced features.

Actel's proven Flash*Freeze technology enables military ProASIC3EL device users to shut off

dynamic power instantaneously and switch the device to static mode without the need to switch

off clocks or power supplies, and retaining internal states of the device. This greatly simplifies

power management. In addition, optimized software tools using power-driven layout provide

instant push-button power reduction.

Nonvolatile flash technology gives military ProASIC3/EL devices the advantage of being a secure,

low-power, single-chip solution that is live at power-up (LAPU). Military ProASIC3/EL devices offer

dramatic dynamic power savings, giving FPGA users flexibility to combine low power with high

performance.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

Military ProASIC3/EL devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM

storage as well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop

(PLL). Military ProASIC3/EL devices support devices from 600 k system gates to 3 million system

gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os.

M1 military ProASIC3/EL devices support the high-performance, 32-bit Cortex-M1 processor

developed by ARM for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully

implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between

low-power consumption and speed when implemented in an M1 military ProASIC3/EL device. The

processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can

be implemented with or without the debug block. ARM Cortex-M1 is available at no cost from

Actel for use in M1 military ProASIC3/ELFPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1 and do not support

AES decryption.

†

Flash*Freeze Technology

Military ProASIC3EL devices offer Actel's proven Flash*Freeze technology, which allows

instantaneous switching from an active state to a static state. When Flash*Freeze mode is

activated, military ProASIC3EL devices enter a static state while retaining the contents of registers

and SRAM. Power is conserved without the need for additional external components to turn off

I/Os or clocks. Flash*Freeze technology is combined with in-system programmability, which enables

users to quickly and easily upgrade and update their designs in the final stages of manufacturing

or in the field. The ability of military ProASIC3EL devices to support a 1.2 V core voltage allows for

an even greater reduction in power consumption, which enables low total system power.

When the military ProASIC3EL device enters Flash*Freeze mode, the device automatically shuts off

the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity

resumes and data is retained.

The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage

solution, make military ProASIC3EL devices suitable for low-power data transfer and manipulation

in military-temperature applications where available power may be limited (e.g., in battery-

powered equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced

cooling).

†

Flash*Freeze technology is not supported on A3P1000.

v1.0

1-1

Military ProASIC3/EL Device Family Overview

Flash Advantages

ƒ

Low Power

The military ProASIC3EL family of Actel flash-based FPGAs provides a low-power advantage, and

when coupled with high performance, enables designers to make power-smart choices using a

single-chip, reprogrammable, and live-at-power-up device.

Military ProASIC3EL devices offer 40% dynamic power and 50% static power savings by reducing

the core operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero^®

Integrated Design Environment (IDE) offers up to 30% additional power reduction. With

Flash*Freeze technology, military ProASIC3EL device is able to retain device SRAM and logic while

dynamic power is reduced to a minimum, without the need to stop clock or power supplies.

Combining these features provides a low-power, feature-rich, and high-performance solution.

Security

Nonvolatile, flash-based military ProASIC3/EL devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. Military ProASIC3/EL devices incorporate

FlashLock, which provides a unique combination of reprogrammability and design security without

external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

Military ProASIC3/EL devices utilize a 128-bit flash-based lock and a separate AES key to secure

programmed intellectual property and configuration data. In addition, all FlashROM data in

military ProASIC3/EL devices can be encrypted prior to loading, using the industry-leading AES-128

(FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of

Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. Military ProASIC3/EL

devices have a built-in AES decryption engine and a flash-based AES key that make them the most

comprehensive programmable logic device security solution available today. Military ProASIC3/EL

devices with AES-based security allow for secure, remote field updates over public networks such as

the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system

cloners, and IP thieves. The contents of a programmed device cannot be read back, although secure

design verification is possible.

Security, built into the FPGA fabric, is an inherent component of the military ProASIC3/EL family.

The flash cells are located beneath seven metal layers, and many device design and layout

techniques have been used to make invasive attacks extremely difficult. The military ProASIC3/EL

family, with FlashLock and AES security, is unique in being highly resistant to both invasive and

noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. A

military ProASIC3/EL device provides the most impenetrable security for programmable logic

designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

military ProASIC3/EL FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

Actel flash-based military ProASIC3/EL devices support Level 0 of the LAPU classification standard.

This feature helps in system component initialization, execution of critical tasks before the

processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based military ProASIC3/EL devices greatly simplifies total

system design and reduces total system cost, often eliminating the need for CPLDs and clock

generation PLLs. In addition, glitches and brownouts in system power will not corrupt the military

ProASIC3/EL device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to

be reloaded when system power is restored. This enables the reduction or complete removal of the

configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices

from the PCB design. Flash-based military ProASIC3/EL devices simplify total system design and

ƒ

A3P1000 only supports 1.5 V core operation.

1-2

v1.0

Military ProASIC3/EL Device Family Overview

reduce cost and design risk while increasing system reliability and improving system initialization

time.

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based military ProASIC3/EL devices allow all functionality to be live at

power-up; no external boot PROM is required. On-board security mechanisms prevent access to all

the programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property cannot be compromised or copied.

Secure ISP can be performed using the industry-standard AES algorithm. The military ProASIC3/EL

family device architecture mitigates the need for ASIC migration at higher volumes. This makes the

military ProASIC3/EL family a cost-effective ASIC replacement.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of military

ProASIC3/EL flash-based FPGAs. Once it is programmed, the flash cell configuration element of

military ProASIC3/EL FPGAs cannot be altered by high-energy neutrons and is therefore immune to

them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily

be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The military ProASIC3/EL family offers many benefits, including nonvolatility and

reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with 7 layers of

metal. Standard CMOS design techniques are used to implement logic and control functions. The

combination of fine granularity, enhanced flexible routing resources, and abundant flash switches

allows for very high logic utilization without compromising device routability or performance.

Logic functions within the device are interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary military ProASIC3/EL architecture provides granularity comparable to standard-cell

ASICs. The military ProASIC3/EL device consists of five distinct and programmable architectural

features (Figure 1-1 on page 1-4 and Figure 1-2):

•

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory

Extensive CCCs and PLLs

I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the military ProASIC3/EL core tile, as either a three-

input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of

the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-

architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

v1.0

1-3

Military ProASIC3/EL Device Family Overview

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of military ProASIC3/EL devices via an IEEE 1532 JTAG interface.

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

ISP AES

Decryption

User Nonvolatile

FlashROM

Charge Pumps

Bank 2

Figure 1-1 • Military ProASIC3 Device Architecture Overview with Four I/O Banks (A3P1000)

CCC

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

Pro I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Figure 1-2 • Military ProASIC3EL Device Architecture Overview (A3PE600L and A3PE3000L)

1-4

v1.0

Military ProASIC3/EL Device Family Overview

††

Flash*Freeze Technology

Military ProASIC3EL devices offer Actel's proven Flash*Freeze technology, which enables designers

to instantaneously shut off dynamic power consumption while retaining all SRAM and register

information. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit

Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept at their

original values. In addition, I/Os and global I/Os can still be driven and can be toggling without

impact on power consumption; clocks can still be driven or can be toggling without impact on

power consumption; all core registers and SRAM cells retain their states. I/Os are tristated during

Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute

configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLLs. Flash*Freeze

technology allows the user to switch to active mode on demand, thus simplifying the power

management of the device.

The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when

it is safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if

Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low-

power static and dynamic capabilities of the military ProASIC3EL device. Refer to Figure 1-3 for an

illustration of entering/exiting Flash*Freeze mode.

Actel ProASIC3EL

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-3 • Military ProASIC3EL Flash*Freeze Mode

VersaTiles

The military ProASIC3/EL core consists of VersaTiles, which have been enhanced beyond the

ProASIC^PLUS®core tiles. The military ProASIC3/EL VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-4 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

X1

Data

Y

Data

CLK

CLR

Y

X2

X3

LUT-3

Y

D-FF

CLK

D-FF

Enable

CLR

Figure 1-4 • VersaTile Configurations

†† Flash*Freeze technology is not supported for A3P1000.

v1.0

1-5

Military ProASIC3/EL Device Family Overview

User Nonvolatile FlashROM

Actel military ProASIC3/EL devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM.

The FlashROM can be used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

FlashROM is written using the standard military ProASIC3/EL IEEE 1532 JTAG programming

interface. The core can be individually programmed (erased and written), and on-chip AES

decryption can be used selectively to securely load data over public networks, as in security keys

stored in the FlashROM for a user design.

FlashROM can be programmed via the JTAG programming interface, and its contents can be read

back either through the JTAG programming interface or via direct FPGA core addressing. Note that

the FlashROM can only be programmed from the JTAG interface and cannot be programmed from

the internal logic array.

FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel military ProASIC3/EL development software solutions, Libero IDE and Designer, have

extensive support for the FlashROM. One such feature is auto-generation of sequential

programming files for applications requiring a unique serial number in each part. Another feature

allows the inclusion of static data for system version control. Data for the FlashROM can be

generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive

programming file support is also included to allow for easy programming of large numbers of parts

with differing FlashROM contents.

SRAM and FIFO

Military ProASIC3/EL devices have embedded SRAM blocks along their north and south sides. Each

variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,

512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that

can be configured with different bit widths on each port. For example, data can be sent through a

4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the

device JTAG port (ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

Military ProASIC3 devices provide designers with flexible clock conditioning circuit (CCC)

capabilities. Each member of the military ProASIC3 family contains six CCCs, located at the four

corners and the centers of the east and west sides. One CCC (center west side) has a PLL. All six CCC

blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well

as clock spine access.

Military ProASIC3EL devices also contain six CCCs; however, all six are equipped with a PLL.

1-6

v1.0

Military ProASIC3/EL Device Family Overview

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz up to 250 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz up to 250 MHz

2 programmable delay types for clock skew minimization

Clock frequency synthesis

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration.

•

Output duty cycle = 50% 1.5% or better

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used

•

Maximum acquisition time is 300 µs

Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

f_{OUT_CCC}

Global Clocking

Military ProASIC3/EL devices have extensive support for multiple clocking domains. In addition to

the CCC and PLL support described above, there is a comprehensive global clock distribution

network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The military ProASIC3/EL family of FPGAs features a flexible I/O structure, supporting a range of

voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for military

ProASIC3EL devices. Military ProASIC3/EL FPGAs support different I/O standards, including single-

ended, differential, and voltage-referenced (military ProASIC3EL). The I/Os are organized into

banks, with two, four, or eight (military ProASIC3EL only) banks per device. The configuration of

these banks determines the I/O standards supported. For military ProASIC3EL, each I/O bank is

subdivided into V_REFminibanks, which are used by voltage-referenced I/Os. V_REFminibanks contain

8 to 18 I/Os. All the I/Os in a given minibank share a common V_REFline. Therefore, if any I/O in a

given V_REFminibank is configured as a V_REFpin, the remaining I/Os in that minibank will be able to

use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

Military ProASIC3EL banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can

support up to 20 loads.

Part Number and Revision Date

Part Number 51700106-001-0

Revised August 2008

v1.0

1-7

Military ProASIC3/EL Device Family Overview

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

1-8

v1.0

2 – Military ProASIC3/EL DC and Switching

Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

absolute maximum ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

V_CC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

V

V_JTAG

V_PUMP

V_CCPLL

V_CCI

Programming voltage

Analog power supply (PLL)

DC I/O output buffer supply

voltage

for

A3PE600L

and

A3PE3000L. DC Output buffer

supply voltage for A3P1000.

VI

I/O input voltage

–0.3 V to 3.6 V (when I/O hot insertion mode is

enabled)

V

–0.3 V to (V_CCI+ 1 V) or 3.6 V, whichever voltage

is lower (when I/O hot-insertion mode is

disabled)

VMV

DC input buffer supply voltage for

A3P1000

–0.3 to 3.75

V

2

T_STG

Storage temperature

Junction temperature

–65 to +150

+150

°C

2

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-7.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

v1.0

2-1

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-2 • Recommended Operating Conditions²

Symbol

T_A

Parameter

Ambient temperature

Junction temperature

Military

–55 to 125

1.14 to 1.575

Units

°C

T_J

°C

V_CC

DC core supply voltage for

A3PE600L/A3PE3000L

V

DC core supply voltage for A3P1000¹

1.425 to 1.575

1.4 to 3.6

V

V_JTAG

JTAG DC voltage

3

V_PUMP

Programming voltage

Programming mode

Operation³

3.15 to 3.45

0 to 3.6

V_CCPLL

Analog power supply (PLL) for DC core supply voltage 1.14 to 1.575

A3PE600L/A3PE3000L

Analog power supply (PLL) for DC core supply voltage 1.425 to 1.575

A3P1000

V_CCIand VMV

1.2 V DC supply voltage⁴

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.3 V DC supply voltage

LVDS differential I/O

1.14 to 1.26

1.425 to 1.575

1.7 to 1.9

V

2.3 to 2.7

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

LVPECL differential I/O

Notes:

1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-23 on page 2-24. VMV and V_CCIshould be at the same voltage within a

given I/O bank.

2. All parameters representing voltages are measured with respect to GND unless otherwise specified.

3. V_PUMPcan be left floating during normal operation (not programming mode).

4. For A3PE600L and A3PE3000L devices only.

2-2

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

110

100

90

80

70

60

50

40

30

20

10

0

HTR

Lifetime

(yrs)

Tj (°C)

70

85

102.7

43.8

20.0

15.6

100

105

110

115

120

125

130

12.3

9.7

7.7

6.2

5.0

135

140

145

150

4.0

3.3

2.7

2.2

70 85 100 105 110 115 120 125 130 135 140 145 150

Temperature (ºC)

Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage.

Figure 2-1 • High-Temperature Data Retention (HTR)

Table 2-3 • Overshoot and Undershoot Limits

Average V_CCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle

Maximum Overshoot/

Undershoot (125°C)

V_CCIand VMV

2.7 V or less

10%

5%

0.72 V

0.82 V

0.72 V

0.81 V

0.69 V

0.79 V

N/A

3 V

10%

5%

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

N/A

1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

2. This table does not provide PCI overshoot/undershoot limits.

v1.0

2-3

Military ProASIC3/EL Low-Power Flash FPGAs

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Military)

Sophisticated power-up management circuitry is designed into every ProASIC^®3 device. These

circuits ensure easy transition from the powered-off state to the powered-up state of the device.

The many different supplies can power up in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6.

There are five regions to consider during power-up.

Military ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. V_CCand V_CCIare above the minimum specified trip points (Figure 2-2 on page 2-5 and

Figure 2-3 on page 2-6).

2. V_CCI> V_CC– 0.75 V (typical)

3. Chip is in the operating mode.

V_CCITrip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

V_CCTrip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

V_CCand V_CCIramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

•

During programming, I/Os become tristated and weakly pulled up to V_CCI.

JTAG supply, PLL power supplies, and charge pump V_PUMPsupply have no influence on I/O

behavior.

2-4

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic, at least until V_CCand V_CCPLXexceed brownout

activation levels. The V_CCactivation level is specified as 1.1 V worst-case (see Figure 2-2 and

Figure 2-3 on page 2-6 for more details).

When PLL power supply voltage and/or V_CClevels drop below the V_CCbrownout levels (0.75 V

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the Power-

Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information on clock

and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

V_CC= V_CCI+ VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

V_CC

V_CC= 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, V_IH/V_IL, V_OH/V_OL, etc.

(except differential inputs)

but slower because V_CCIis

below specification. For the

same reason, input buffers do not

meet V_IH/V_ILlevels, and output

buffers do not meet V_OH/V_OLlevels.

V_CC= 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V_CCis below specification.

I/Os are functional (except differential inputs)

but slower because V_CCI/V_CCare below

specification. For the same reason, input

buffers do not meet V_IH/V_ILlevels, and

output buffers do not meet V_OH/V_OLlevels.

Activation trip point:

V

_a= 0.85 V 0.25 V

Deactivation trip point:

_d= 0.75 V 0.25 V

Region 1: I/O buffers are OFF

V

V_CCI

Activation trip point:

Min V_CCIdatasheet specification

V_a= 0.9 V 0.3 V

Deactivation trip point:

V_d= 0.8 V 0.3 V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

Figure 2-2 • Devices Operating at 1.5 V Core – I/O State as a Function of V_CCIand V_CCVoltage Levels

v1.0

2-5

Military ProASIC3/EL Low-Power Flash FPGAs

V

= V + VT

CCI

CC

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

V

CC

V

= 1.575 V

CC

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, V_IH/V_IL, V_OH/V_OL, etc.

but slower because V_CCIis

below specification. For the

same reason, input buffers do not

meet V_IH/V_ILlevels, and output

buffers do not meet V_OH/V_OLlevels.

V

= 1.14 V

CC

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V_CCis below specification.

I/Os are functional (except differential inputs)

but slower because V_CCI/V_CCare below

specification. For the same reason, input

buffers do not meet V_IH/V_ILlevels, and

output buffers do not meet V_OH/V_OLlevels.

Activation trip point:

= 0.85 V 0.2 V

V

a

Deactivation trip point:

= 0.75 V 0.2 V

Region 1: I/O buffers are OFF

V

d

V

Activation trip point:

= 0.9 V 0.15 V

CCI

Min V datasheet specification

CCI

V

voltage at a selected I/O

a

Deactivation trip point:

= 0.8 V 0.15 V

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

V

d

Figure 2-3 • Device Operating at 1.2 V Core Voltage – I/O State as a Function of V_CCIand V_CCVoltage Levels;

Only A3PE600L and A3PE3000L Devices Operate at 1.2 V Core Voltage

2-6

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction temperature to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

T_J= Junction Temperature = ΔT + T_A

EQ 2-1

where:

T_A= Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θ_ja* P

θ_ja= Junction-to-ambient of the package. θ_janumbers are located in Table 2-4.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θ_jcand the junction-to-ambient air thermal

resistivity is θ_ja. The thermal characteristics for θ_jaare shown for two air flow rates. The

recommended maximum junction temperature is 125°C. EQ 2-2 shows a sample calculation of the

recommended maximum power dissipation allowed for a 484-pin FBGA package at military

temperature and in still air.

Max. junction temp. (°C) – Max. ambient temp. (°C)

125°C – 70°C

20.6°C/W

Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 2. 670

θ_ja(°C/W)

EQ 2-2

Table 2-4 • Package Thermal Resistivities

θ_ja

Package Type

Device

Pin Count θ_jcStill Air 200 ft./min. 500 ft./min. Units

Plastic Quad Flat Pack (PQ208)*

Fine Pitch Ball Grid Array (FBGA)

A3P1000

208

144

484

896

3.8

6.3

9.5

4.7

2.4

16.2

31.6

27.5

20.6

13.6

13.3

26.2

21.9

15.7

10.4

11.9

24.2

20.2

14.0

9.4

C/W

A3PE600L

A3PE3000L

* Embedded heatspreader

v1.0

2-7

Military ProASIC3/EL Low-Power Flash FPGAs

Temperature and Voltage Derating Factors

Table 2-5 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 125°C, V_CC= 1.14 V)

Applicable to A3PE600L and A3PE3000L Only

Junction Temperature

0°C 25°C 70°C

Array Voltage V_CC(V)

–55°C

0.86

0.83

0.79

0.77

0.75

0.72

0.70

0.67

0.64

–40°C

0.87

0.84

0.80

0.78

0.75

0.73

0.71

0.67

0.65

85°C

0.98

0.94

0.90

0.88

0.85

0.81

0.80

0.76

0.73

125°C

1.00

0.96

0.92

0.90

0.87

0.83

0.82

0.78

0.75

1.14

1.2

0.90

0.87

0.83

0.81

0.78

0.75

0.74

0.70

0.67

0.92

0.89

0.85

0.83

0.80

0.77

0.76

0.71

0.69

0.96

0.93

0.89

0.86

0.83

0.80

0.79

0.75

0.72

1.26

1.3

1.35

1.4

1.425

1.5

1.575

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 125°C, V_CC= 1.425 V)

Applicable to A3P1000 Devices Only

Junction Temperature

Array Voltage V_CC(V)

–55°C

0.81

–40°C

0.83

0°C

0.88

0.83

0.80

25°C

0.90

0.85

0.82

70°C

0.95

0.90

0.87

85°C

0.97

0.92

0.88

125°C

1.00

1.425

1.5

0.77

0.79

0.95

1.575

0.74

0.76

0.92

2-8

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Calculating Power Dissipation

Quiescent Supply Current

Table 2-7 • Quiescent Supply Current (I_DD) Characteristics When Using Flash*Freeze Mode in Military

ProASIC3/EL*

Core Voltage

1.2 V

A3PE600L

A3PE3000L

Units

mA

Typical (25°C)

2.75

1.5 V

mA

* I_DDincludes V_CC, V_PUMP, V_CCI, V_JTAG, and V_CCPLLcurrents. Values do not include I/O static contribution (P_DC6

and P_DC7).

Table 2-8 • Quiescent Supply Current (I_DD) Characteristics, Military ProASIC3/EL Sleep Mode (V_CC= 0 V)*

Core Voltage

A3PE600L

A3PE3000L

Units

V_CCI/ V_JTAG= 1.2 V (per bank)

1.2 V / 1.5 V

1.7

µA

Typical (25°C)

V_CCI/ V_JTAG= 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V

1.8

1.9

2.2

2.5

1.8

1.9

2.2

2.5

µA

V_CCI/ V_JTAG= 1.8 V (per bank)

Typical (25°C)

V_CCI/ V_JTAG= 2.5 V (per bank)

Typical (25°C)

V_CCI/ V_JTAG= 3.3 V (per bank)

Typical (25°C)

* I_DDincludes V_CC, V_PUMP, and V_CCPLLcurrents. Values do not include I/O static contribution (P_DC6and P_DC7).

Table 2-9 • Quiescent Supply Current (I_DD) Characteristics for A3PE600L and A3PE3000L Devices Only

Shutdown Mode, (V_CCand V_CCI= 0 V)*

Core Voltage

A3PE600L

A3PE3000L

Typical (25°C)

1.2 V

0 µA

* I_DDincludes V_CC, V_PUMP, V_CCI, V_JTAG, and V_CCPLLcurrents. Values do not include I/O static contribution (P_DC6

and P_DC7).

v1.0

2-9

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-10 • Quiescent Supply Current (I_DD), No Military ProASIC3/EL Flash*Freeze Mode¹

Core Voltage

A3PE600L

A3PE3000L

Units

I_CCACurrent²

Typical (25°C)

1.2 V

1.5 V

2.75

mA

I_CCIor I_JTAGCurrent^{3, 4}

V_CCI/ V_JTAG= 1.2 V (per bank)

Typical (25°C)

1.2 V / 1.5 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

V_CCI/ V_JTAG= 1.5 V (per bank)

Typical (25°C)

V_CCI/ V_JTAG= 1.8 V (per bank)

Typical (25°C)

V_CCI/ V_JTAG= 2.5 V (per bank)

Typical (25°C)

V_CCI/ V_JTAG= 3.3 V (per bank)

Typical (25°C)

Notes:

1. To calculate total device I_DD, multiply the number of banks used by I_CCIand add I_CCAcontribution.

2. Includes V_CC, V_CCPLL, and V_PUMPcurrents.

3. Per V_CCIor V_JTAGbank.

4. Values do not include I/O static contribution (P_DC6and P_DC7).

Table 2-11 • Quiescent Supply Current (I_DD) Characteristics

A3P1000

Typical (25°C)

8 mA

Maximum Military (125°C)

200 mA

* I_DDincludes V_CC, V_PUMP, V_CCI, V_JTAG, and V_CCPLLcurrents. Values do not include I/O static contribution (P_DC6

and P_DC7).

2-10

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Power per I/O Pin

Table 2-12 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Static Power P_DC6

(mW)¹

Dynamic Power P_AC9

V_CCI(V)

(µW/MHz)²

Single-Ended

3.3 V LVTTL/LVCMOS

3.3

2.5

1.8

1.5

1.2

3.3

–

16.34

24.49

4.71

3.3 V LVTTL/LVCMOS – Schmitt trigger

2.5 V LVCMOS

2.5 V LVCMOS – Schmitt trigger

6.13

1.8 V LVCMOS

1.66

1.8 V LVCMOS – Schmitt trigger

1.78

1.5 V LVCMOS (JESD8-11)

1.01

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

0.97

1.2 V LVCMOS³

0.60

1.2 V LVCMOS (JESD8-11) – Schmitt trigger³

0.53

3.3 V PCI

17.76

19.10

17.76

19.10

3.3 V PCI – Schmitt trigger

3.3 V PCI-X

3.3 V PCI-X – Schmitt trigger

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

3.3

2.90

2.13

2.81

2.57

0.17

1.38

3.21

7.07

3.62

2.97

2.55

0.85

3.30

8.08

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

2.5

3.3

2.26

5.71

0.95

1.62

LVPECL

Notes:

1. P_DC6is the static power (where applicable) measured on V_CCI

.

2. P_AC9is the total dynamic power measured on V_CCI

.

v1.0

2-11

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks for A3P1000 Only

Static Power

P_DC6(mW)²

Dynamic Power

VMV (V)

P_AC9(µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

16.69

5.12

2.13

1.45

18.11

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

1.20

1.87

LVPECL

Notes:

1. P_DC6is the static power (where applicable) measured on VMV.

2. P_AC9is the total dynamic power measured on VMV.

Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks for A3P1000 Only

Static Power

P

Dynamic Power

VMV (V)

_DC6(mW)¹

P_AC9(µW/MHz)²

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

16.72

5.14

2.13

1.48

18.13

16.72

3.3 V PCI-X

Notes:

1. P_DC6is the static power (where applicable) measured on VMV.

2. P_AC9is the total dynamic power measured on VMV.

2-12

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Static Power

P_DC7(mW)²

Dynamic Power

P

C_LOAD(pF)

V_CCI(V)

_AC10(µW/MHz)³

Single-Ended

3.3 V LVTTL/LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁴

3.3 V PCI

5

3.3

2.5

1.8

1.5

1.2

3.3

–

148.00

83.23

54.58

37.05

17.94

204.61

5

10

3.3 V PCI-X

Voltage-Referenced

3.3 V GTL

10

20

30

3.3

2.5

3.3

2.5

1.5

2.5

3.3

–

24.08

13.52

24.10

2.5 V GTL

–

3.3 V GTL+

2.5 V GTL+

HSTL (I)

–

13.54

7.08

13.88

16.69

25.91

26.02

42.21

26.22

27.22

105.56

116.60

114.87

131.76

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

–

2.5

3.3

7.70

89.62

LVPECL

19.42

168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. P_DC7is the static power (where applicable) measured on V_CCI

.

3. P_AC10is the total dynamic power measured on V_CCI

.

v1.0

2-13

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks for A3P1000 Only

Static Power P_DC7

(mW)²

Dynamic Power

P

_AC10(µW/MHz)³

C_LOAD(pF)

V_CCI(V)

Single-Ended

3.3 V LVTTL /

5

3.3

–

141.97

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

5

2.5

1.8

1.5

3.3

–

79.98

52.26

5

35.62

10

201.02

3.3 V PCI-X

Differential

LVDS

–

2.5

3.3

7.74

89.71

LVPECL

19.54

167.54

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. P_DC7is the static power (where applicable) measured on V_CCI

.

3. P_AC10is the total dynamic power measured on V_CCI

.

Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks for A3P1000 Only

Static Power P_DC7

Dynamic Power

C_LOAD(pF)

V_CCI(V)

(mW)²

P_AC10(µW/MHz)³

Single-Ended

3.3 V LVTTL /

5

3.3

–

125.97

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

5

2.5

1.8

1.5

3.3

–

70.82

36.39

5

25.34

10

184.92

3.3 V PCI-X

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. P_DC7is the static power (where applicable) measured on V_CCI

.

3. P_AC10is the total dynamic power measured on V_CCI

.

2-14

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Power Consumption of Various Internal Resources

Table 2-18 • Different Components Contributing to Dynamic Power Consumption in Devices Operating at

1.2 V V_CC

Device-Specific Dynamic Power

(µW/MHz)

Parameter

P_AC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

A3PE3000L

12.61

A3PE600L

P_AC2

2.66

P_AC3

0.56

P_AC4

Clock contribution of a VersaTile used as a sequential

module

0.07

0.05

0.19

0.11

0.45

P_AC5

P_AC6

P_AC7

First contribution of a VersaTile used as a sequential

module

Second contribution of a VersaTile used as a sequential

module

Contribution of a VersaTile used as a combinatorial

module

P_AC8

P_AC9

Average contribution of a routing net

Contribution of an I/O input pin (standard-dependent)

See Table 2-12 on page 2-11

through Table 2-14 on page 2-12.

P_AC10

P_AC11

P_AC12

P_AC13

Contribution of an I/O output pin (standard-dependent)

See Table 2-15 on page 2-13

through Table 2-17 on page 2-14.

Average contribution of a RAM block during a read

operation

25.00

30.00

1.74

Average contribution of a RAM block during a write

operation

Dynamic contribution for PLL

v1.0

2-15

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-19 • Different Components Contributing to Dynamic Power Consumption in Military ProASIC3/EL

Devices at 1.5 V V_CC

Device-Specific Dynamic Power

(µW/MHz)

Parameter

P_AC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

A3PE3000L A3PE600L

A3P1000

14.50

2.48

19.7

4.16

0.88

0.12

P_AC2

P_AC3

0.81

P_AC4

Clock contribution of a VersaTile used as a sequential

module

P_AC5

P_AC6

P_AC7

First contribution of a VersaTile used as a sequential

module

0.07

0.29

0.70

Second contribution of a VersaTile used as a sequential

module

Contribution of a VersaTile used as a combinatorial

Module

P_AC8

P_AC9

Average contribution of a routing net

Contribution of an I/O input pin (standard-dependent) See Table 2-12 on page 2-11 through

Table 2-14 on page 2-12.

P_AC10

P_AC11

P_AC12

P_AC13

Contribution of an I/O output pin (standard- See Table 2-15 on page 2-13 through

dependent)

Table 2-17 on page 2-14.

Average contribution of a RAM block during a read

operation

25.00

Average contribution of a RAM block during a write

operation

30.00

2.60

Dynamic contribution for PLL

Table 2-20 • Different Components Contributing to the Static Power Consumption in Military ProASIC3/EL

Devices

Device-Specific Dynamic Power (µW)

Parameter

P_DC1

Definition

Array static power in Active mode

Array static power in Static (Idle) mode

Array static power in Flash*Freeze mode

A3PE3000L

A3PE600L

A3P1000

See Table 2-10 on page 2-10.

See Table 2-7 on page 2-9.

P_DC2

P_DC3

P_DC4

Static PLL contribution at 1.2 V operating core voltage

(for A3PE600L and A3PE3000L only)

1.42 mW

N/A

Static PLL contribution 1.5 V operating core voltage

Bank quiescent power (V_CCI-dependent)

2.55 mW

P_DC5

P_DC6

P_DC7

See Table 2-7 on page 2-9, Table 2-8

on page 2-9, Table 2-10 on page 2-10.

I/O input pin static power (standard-dependent)

I/O output pin static power (standard-dependent)

See Table 2-12 on page 2-11. through

Table 2-14 on page 2-12.

See Table 2-15 on page 2-13 through

Table 2-17 on page 2-14.

* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Libero^®Integrated Design Environment (IDE).

2-16

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock

generated

•

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-21 on

page 2-19.

•

Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-22 on page 2-19.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-22 on page 2-19. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

P_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

STAT

P_STAT= (P_DC1or P_DC2or P_DC3) + N_BANKS* P_DC5+ N_INPUTS* P_DC6+ N_OUTPUTS* P_DC7

N_INPUTSis the number of I/O input buffers used in the design.

N

_OUTPUTSis the number of I/O output buffers used in the design.

_BANKSis the number of I/O banks powered in the design.

N

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (P_AC1+ N_SPINE*P_AC2+ N_ROW*P_AC3+ N_S-CELL* P_AC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided

in Table 2-21 on page 2-19.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in

Table 2-21 on page 2-19.

F_CLKis the global clock signal frequency.

N

_S-CELLis the number of VersaTiles used as sequential modules in the design.

_AC1, P_AC2, P_AC3, and P_AC4are device-dependent.

Sequential Cells Contribution—P

P

S-CELL

P_S-CELL= N_S-CELL* (P_AC5+ α₁/ 2 * P_AC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on

page 2-19.

F_CLKis the global clock signal frequency.

v1.0

2-17

Military ProASIC3/EL Low-Power Flash FPGAs

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* α₁/ 2 * P_AC7* F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on

page 2-19.

F_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * α₁/ 2 * P_AC8* F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on

page 2-19.

F_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* α₂/ 2 * P_AC9* F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-21 on page 2-19.

F_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* α₂/ 2 * β₁* P_AC10* F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-21 on page 2-19.

β₁is the I/O buffer enable rate—guidelines are provided in Table 2-22 on page 2-19.

F_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= P_AC11* N_BLOCKS* F_READ-CLOCK* β₂+ P_AC12* N_BLOCK* F_WRITE-CLOCK* β₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

β₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

F

β₃is the RAM enable rate for write operations—guidelines are provided in Table 2-22

on page 2-19.

PLL Contribution—P

PLL

P_PLL= P_DC4+ P_AC13*F_CLKOUT

F_CLKOUTis the output clock frequency.¹

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its

corresponding contribution (P_AC13* F_CLKOUTproduct) to the total PLL contribution.

2-18

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-21 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

α₁

α₂

10%

Table 2-22 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

β₁

β₂

β₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

v1.0

2-19

Military ProASIC3/EL Low-Power Flash FPGAs

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

LVPECL

Y

t

= 0.78 ns

t

= 0.67 ns

PD

t

= 1.54 ns

DP

I/O Module

(Non-Registered)

Combinational Cell

Y

Output Drive Strength = 12 mA

High Slew Rate

LVTTL

t

= 2.08 ns

DP

t

= 1.21 ns

PD

I/O Module

(Non-Registered)

Combinational Cell

Y

I/O Module

(Registered)

Output Drive Strength = 8 mA

High Slew Rate

LVTTL

t

= 1.84 ns

PY

t

= 2.37 ns

DP

LVPECL

t

= 0.70 ns

PD

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

Output Drive Strength = 4 mA

High Slew Rate

LVCMOS 1.5 V

t

= 0.33 ns

ICLKQ

ISUD

t

= 2.83 ns

DP

t

= 0.65 ns

= 0.36 ns

PD

Input LVTTL

Clock

I/O Module

(Registered)

Register Cell

Combinational Cell

Y

t

= 1.48 ns

PY

D

Q

D

Q

D

t

Q

LVTTL 3.3 V Output Drive

Strength = 12 mA

I/O Module

t

= 0.65 ns

PD

t

= 2.08 ns

High Slew Rate

(Non-Registered)

DP

t

= 0.76 ns

= 0.59 ns

CLKQ

SUD

= 0.81 ns

= 0.43 ns

t

= 0.76 ns

= 0.9 ns

OCLKQ

CLKQ

SUD

LVDS,

B-LVDS,

M-LVDS

t

OSUD

Input LVTTL

Clock

Input LVTTL

Clock

t

= 2.04 ns

PY

t

= 1.48 ns

t

= 1.48 ns

PY

Figure 2-4 • Timing Model

Operating Conditions: –1 Speed, Military Temperature Range (T_J= 125°C), Worst-Case

V_CC= 1.14 V (example for A3PE3000L and A3PE600L)

2-20

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t

_PY= MAX(t_PY(R), t_PY(F))

_DIN= MAX(t_DIN(R), t_DIN(F))

V_IH

V_trip

V_CC

V_IL

PAD

Y

50%

GND

t_PY

(R)

t_PY

(F)

V_CC

50%

DIN

t_DOUT

(R)

GND

t_DOUT

(F)

Figure 2-5 • Input Buffer Timing Model and Delays (example)

v1.0

2-21

Military ProASIC3/EL Low-Power Flash FPGAs

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(F)

V_CC

(R)

50%

D

0 V

V_CC

50%

DOUT

PAD

0 V

V_OH

V_trip

V_OL

t_DP

(R)

t_DP

(F)

Figure 2-6 • Output Buffer Model and Delays (example)

2-22

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

t

EOUT

D

Q

CLK

t , t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

t

CLK

D

= MAX(t

(r), t

(f))

V

I/O Interface

EOUT

V

CC

D

E

CC

50%

t

EOUT (F)

t

EOUT (R)

V

CC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

V

HZ

CCI

90% V

CCI

V

trip

V

10% V

OL

CCI

V

CC

D

E

V

CC

50%

t

EOUT (F)

EOUT (R)

V

CC

50%

EOUT

PAD

50%

t

ZHS

t

V

ZLS

OH

V

trip

V

OL

Figure 2-7 • Tristate Output Buffer Timing Model and Delays (example)

v1.0

2-23

Military ProASIC3/EL Low-Power Flash FPGAs

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Military Conditions—Software Default Settings

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

1

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

Drive

Slew

I/O Standard

Strength Rate Min, V

Max, V

3.3 V LVTTL / 12 mA

3.3 V LVCMOS

–0.3

0.8

2

3.6

12

2

High

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

12 mA

2 mA

0.7

1.7

2.7

1.9

0.7

1.7

12

–0.3 0.35 * V_CCI0.65 * V_CCI

0.45

V_CCI– 0.45 12

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI12

–0.3 0.35 * V_CCI0.65 * V_CCI

1.26

0.25 * V_CCI0.75 * V_CCI

2

3.3 V PCI

Per PCI Specification

3.3 V PCI-X

3.3 V GTL

Per PCI-X Specification

25 mA²

35 mA

33 mA

8 mA

–0.3 V_REF–0.05 V_REF+ 0.05

3.6

0.4

–

25

51

40

8

25

51

40

8

High

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

–0.3 V_REF–0.05 V_REF+ 0.05

2.7

–

–0.3

V_REF– 0.1

V_REF+ 0.1

V_REF+ 0.2

3.6

0.6

–

2.7

0.6

–

V

_REF– 0.1

1.575

2.7

0.4

V_CCI– 0.4

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA²

15 mA

18 mA

14 mA

21 mA

V_REF– 0.1

V_REF– 0.2

0.4

15

18

14

21

0.54

0.35

0.7

V_CCI–0.62 15

V_CCI–0.43 18

V

_REF– 0.2

2.7

V_REF– 0.2

3.6

V_CCI– 1.1

V_CCI– 0.9

14

21

3.6

0.5

1. Currents are measured at 125°C junction temperature.

2. Output drive strength is below JEDEC specification.

3. Output slew rate can be extracted using the IBIS Models.

2-24

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military

Conditions—Software Default Settings

Applicable to Advanced I/O Banks for A3P1000 Only

1

V_IL

Max, V

V_IH

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

Drive

Slew

I/O Standard

Strength Rate Min, V

Min, V

Max, V

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High

–0.3

0.8

2

3.6

12

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

3.3 V PCI

0.7

1.7

2.7

1.9

0.7

1.7

12

12 mA

2 mA

High

–0.3 0.35 * V_CCI0.65 * V_CCI

0.45

V_CCI–0.45 12 12

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI12 12

–0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI0.75 * V_CCI

2

Per PCI specifications

3.3 V PCI-X

Notes:

Per PCI-X specifications

1. Currents are measured at 125°C junction temperature.

2. Output slew rate can be extracted using the IBIS Models

Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military

Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks for A3P1000 Only

1

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

Drive

Slew

I/O Standard Strength Rate Min, V

Max, V

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

High

–0.3

0.8

2

3.6

12

2.5 V LVCMOS 12 mA

High

0.7

1.7

2.7

1.9

0.7

1.7

12

8

12

8

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

3.3 V PCI

8 mA

4 mA

2 mA

–0.3 0.35 * V_CCI0.65 * V_CCI

0.45

V_CCI– 0.45

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI

–0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI0.75 * V_CCI

4

2

Per PCI specifications

3.3 V PCI-X

Notes:

Per PCI-X specifications

1. Currents are measured at 125°C junction temperature.

2. Output slew rate can be extracted using the IBIS Models.

v1.0

2-25

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-26 • Summary of Maximum and Minimum DC Input Levels

Applicable to Military Conditions

Military

I_IL

µA

15

I_IH

µA

15

DC I/O Standard

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

3.3 V PCI

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Note: Military temperature range: –55°C to 125°C

2-26

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-27 • Summary of AC Memory Points*

Input Reference Voltage

(V_{REF_TYP}

Board Termination

Measuring Trip Point

(V_trip

Standard

)

Voltage (V_{TT_REF}

)

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS*

3.3 V PCI

–

1.4 V

1.2 V

0.90 V

0.75 V

0.6V

0.285 * V_{CCI (RR)}

0.615 * V_{CCI (FF))}

0.285 * V_{CCI (RR)}

0.615 * V_{CCI (FF)}

V_REF

3.3 V PCI-X

–

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

0.8 V

1.0 V

0.75 V

1.25 V

1.5 V

–

1.2 V

1.5 V

0.75 V

1.25 V

1.485 V

–

V_REF

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

V_REF

Cross point

LVPECL

–

* Applicable to A3PE600L and A3PE3000L devices operating at 1.2 V core regions only.

Table 2-28 • I/O AC Parameter Definitions

Parameter

t_DP

Parameter Definition

Data to Pad delay through the Output Buffer

t_PY

Pad to Data delay through the Input Buffer

t_DOUT

t_EOUT

t_DIN

t_HZ

Data to Output Buffer delay through the I/O interface

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Enable to Pad delay through the Output Buffer—HIGH to Z

Enable to Pad delay through the Output Buffer—Z to HIGH

Enable to Pad delay through the Output Buffer—LOW to Z

Enable to Pad delay through the Output Buffer—Z to LOW

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

v1.0

2-27

Military ProASIC3/EL Low-Power Flash FPGAs

1.2 V Core Operating Voltage

Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: T_J= 125°C, Worst Case V_CC= 1.14 V, Worst Case V_CCI

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Standard

3.3 V LVTTL /

12 mA High

5

–

0.68 2.08 0.05 1.48 2.03 0.44 2.12 1.56 2.76 3.04 4.00 3.44 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High

1.8 V LVCMOS 12 mA High

1.5 V LVCMOS 12 mA High

1.2 V LVCMOS 2mA High

5

–

0.68 2.12 0.05 1.74 2.16 0.44 2.16 1.74 2.84 2.94 4.04 3.63 ns

0.68 2.36 0.05 1.69 2.38 0.44 2.40 1.94 3.14 3.57 4.28 3.82 ns

0.68 2.71 0.05 1.86 2.59 0.44 2.76 2.24 3.34 3.68 4.64 4.12 ns

0.68 4.40 0.05 2.23 3.20 0.44 4.21 3.71 4.35 4.11 6.02 5.52 ns

3.3 V PCI

PerPCI High 10 25 0.68 2.36 0.05 2.31 3.12 0.44 2.41 1.68 2.76 3.04 4.29 3.56 ns

spec

3.3 V PCI-X

Per

PCI-X

spec

High 10 25 0.68 2.36 0.05 2.31 3.12 0.44 2.41 1.68 2.76 3.04 4.29 3.56 ns

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

25 mA High 10 25 0.68 1.75 0.05 1.98

25 mA High 10 25 0.68 1.79 0.05 1.92

35 mA High 10 25 0.68 1.73 0.05 1.98

33 mA High 10 25 0.68 1.86 0.05 1.92

8 mA High 20 25 0.68 2.68 0.05 2.34

15 mA High 20 50 0.68 2.55 0.05 2.34

15 mA High 30 25 0.68 1.79 0.05 1.77

18 mA High 30 50 0.68 1.83 0.05 1.77

14 mA High 30 25 0.68 1.94 0.05 1.69

21 mA High 30 50 0.68 1.74 0.05 1.69

–

0.44 1.72 1.75

0.44 1.82 1.79

0.44 1.76 1.73

0.44 1.89 1.77

0.44 2.73 2.65

0.44 2.59 2.29

0.44 1.82 1.56

0.44 1.86 1.49

0.44 1.98 1.55

0.44 1.77 1.41

–

3.60 3.63 ns

3.70 3.68 ns

3.65 3.61 ns

3.78 3.65 ns

4.61 4.53 ns

4.48 4.17 ns

1.82 1.56 ns

1.86 1.49 ns

1.98 1.55 ns

1.77 1.41 ns

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

24 mA High

–

0.68 1.57 0.05 2.04

0.68 1.54 0.05 1.84

–

ns

LVPECL

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on

page 2-65 for connectivity. This resistor is not required during normal operation.

2-28

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

1.5 V Core Voltage

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst Case V_CCI

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Standard

3.3 V LVTTL / 12 mA High

5

–

0.52 2.08 0.03 1.48 2.03 0.34 2.12 1.56 2.76 3.04 4.00 3.44 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High

1.8 V LVCMOS 12 mA High

1.5 V LVCMOS 12 mA High

5

–

0.52 2.12 0.03 1.74 2.16 0.34 2.16 1.74 2.84 2.94 4.04 3.63 ns

0.52 2.36 0.03 1.69 2.38 0.34 2.40 1.94 3.14 3.57 4.28 3.82 ns

0.52 2.71 0.03 1.86 2.59 0.34 2.76 2.24 3.34 3.68 4.64 4.12 ns

3.3 V PCI

PerPCI High 10 25 0.52 2.36 0.03 2.31 3.12 0.34 2.41 1.68 2.76 3.04 4.29 3.56 ns

spec

3.3 V PCI-X

Per

PCI-X

spec

High 10 25 0.52 2.36 0.03 2.31 3.12 0.34 2.41 1.68 2.76 3.04 4.29 3.56 ns

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

25 mA High 10 25 0.52 1.75 0.03 1.98

25 mA High 10 25 0.52 1.79 0.03 1.92

35 mA High 10 25 0.52 1.73 0.03 1.98

33 mA High 10 25 0.52 1.86 0.03 1.92

8 mA High 20 25 0.52 2.68 0.03 2.34

15 mA High 20 50 0.52 2.55 0.03 2.34

15 mA High 30 25 0.52 1.79 0.03 1.77

18 mA High 30 50 0.52 1.83 0.03 1.77

14 mA High 30 25 0.52 1.94 0.03 1.69

21 mA High 30 50 0.52 1.74 0.03 1.69

–

0.34 1.72 1.75

0.34 1.82 1.79

0.34 1.76 1.73

0.34 1.89 1.77

0.34 2.73 2.65

0.34 2.59 2.29

0.34 1.82 1.56

0.34 1.86 1.49

0.34 1.98 1.55

0.34 1.77 1.41

–

3.60 3.63 ns

3.70 3.68 ns

3.65 3.61 ns

3.78 3.65 ns

4.61 4.53 ns

4.48 4.17 ns

1.82 1.56 ns

1.86 1.49 ns

1.98 1.55 ns

1.77 1.41 ns

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

24 mA High

–

0.52 1.57 0.03 2.04

0.52 1.54 0.03 1.84

–

ns

LVPECL

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on

page 2-65 for connectivity. This resistor is not required during normal operation.

v1.0

2-29

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: T_J= 125°C, Worst Case V_CC= 1.425 V, Worst Case V_CCI

Applicable to Advanced I/O Banks for A3P1000 Only

I/O Standard

3.3 V LVTTL /

12 mA

High 5pF

–

0.54 2.24 0.04 0.95 0.39 2.28 1.70 3.00 3.35 4.38 3.79 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

High 5 pF

–

0.54 2.26 0.04 1.23 0.39 2.30 1.89 3.09 3.22 4.39 3.99 ns

0.54 2.49 0.04 1.14 0.39 2.54 2.12 3.46 3.82 4.63 4.21 ns

0.54 2.85 0.04 1.35 0.39 2.90 2.45 3.69 3.93 4.99 4.55 ns

Per PCI spec. High 5 pF 25 ²0.54 2.51 0.04 0.81 0.39 2.39 1.68 3.00 3.35 4.65 3.92 ns

Per PCI-X spec. High 10 pF 25 ²0.54 2.51 0.04 0.78 0.39 2.39 1.68 3.00 3.35 4.65 3.92 ns

3.3 V PCI-X

LVDS

24 mA

High

–

0.54 1.71 0.04 1.50 N/A N/A N/A N/A N/A N/A N/A ns

0.54 1.68 0.04 1.31 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on

page 2-65 for connectivity. This resistor is not required during normal operation.

2-30

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: T_J= 125°C, Worst Case V_CC= 1.425 V, Worst Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

I/O Standard

3.3 V LVTTL /

12 mA

High 5pF

–

0.54 1.90 0.04 0.94 0.39 1.94 1.47 2.61 3.01 4.03 3.56 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

8 mA

4 mA

High 5pF

–

0.54 1.94 0.04 1.21 0.39 1.97 1.62 2.64 2.91 4.07 3.71 ns

0.54 2.62 0.04 1.33 0.39 2.67 2.23 2.84 2.93 4.77 4.32 ns

Per PCI spec. High 10 pF 25 ²0.54 2.16 0.04 0.80 0.39 2.03 1.45 2.61 3.01 4.29 3.69 ns

Per PCI-X spec. High 10 pF 25 ²0.54 2.16 0.04 0.78 0.39 2.03 1.45 2.61 3.01 4.29 3.69 ns

3.3 V PCI-X

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on

page 2-65 for connectivity. This resistor is not required during normal operation.

Detailed I/O DC Characteristics

Table 2-33 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min.

Max.

Units

pF

Input capacitance

Input capacitance on the clock pin

V_IN= 0, f = 1.0 MHz

8

C_INCLK

pF

v1.0

2-31

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-34 • I/O Output Buffer Maximum Resistances¹

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

4 mA

(Ω)²

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

100

50

300

150

75

8 mA

12 mA

16 mA

24 mA

4 mA

25

17

50

11

33

2.5 V LVCMOS

1.8 V LVCMOS

100

50

200

100

50

8 mA

12 mA

16 mA

24 mA

2 mA

25

20

40

11

22

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

12 mA

16 mA

2 mA

20

22

20

22

1.5 V LVCMOS

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

2 mA

33

37

1.2 V LVCMOS

3.3 V PCI/PCI-X

TBD

25

TBD

75

Per PCI/PCI-X

specification

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

25 mA

35 mA

33 mA

8 mA

11

14

12

15

50

25

27

13

44

18

–

50

25

31

15

69

32

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA

18 mA

14 mA

21 mA

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

2-32

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-35 • I/O Output Buffer Maximum Resistances¹

Applicable to Advanced I/O Banks for A3P1000 Only

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

(Ω)²

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

100

50

300

150

75

50

25

17

50

11

33

2.5 V LVCMOS

100

50

300

150

75

50

25

17

50

11

33

1.8 V LVCMOS

100

50

200

100

50

25

20

40

1.5 V LVCMOS

200

100

67

224

112

75

33

37

33

37

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

25

75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

v1.0

2-33

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-36 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard Plus I/O Banks for A3P1000 Only

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

(Ω)²

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

100

50

300

150

75

4 mA

6 mA

8 mA

50

12 mA

16 mA

2 mA

25

75

2.5 V LVCMOS

100

50

200

100

50

4 mA

6 mA

8 mA

50

12 mA

2 mA

25

1.8 V LVCMOS

1.5 V LVCMOS

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

2 mA

200

100

25

224

112

75

4 mA

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

2-34

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-37 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

(Ω)

V_CCI

Min.

10 k

11 k

18 k

19 k

TBD

Max.

45 k

55 k

70 k

90 k

TBD

Min.

Max.

45 k

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

Notes:

10 k

12 k

17 k

19 k

TBD

74 k

110 k

140 k

TBD

1. R_{(WEAK PULL-UP-MAX)}= (V_OLspec) / I_{(WEAK PULL-UP-MIN)}

2. R_{(WEAK PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_{(WEAK PULL-UP-MIN)}

v1.0

2-35

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-38 • I/O Short Currents I_OSH/I_OSL

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive Strength

4 mA

I

_OSL(mA)*

I_OSH(mA)*

27

3.3 V LVTTL / 3.3 V LVCMOS

25

8 mA

51

54

12 mA

16 mA

24 mA

4 mA

103

132

268

16

109

127

181

18

2.5 V LVCMOS

8 mA

32

37

12 mA

16 mA

24 mA

2 mA

65

74

83

87

169

9

124

11

1.8 V LVCMOS

4 mA

17

22

6 mA

35

44

8 mA

45

51

12 mA

16 mA

2 mA

91

74

91

74

1.5 V LVCMOS

13

16

4 mA

25

33

6 mA

32

39

8 mA

66

55

12 mA

2mA

66

55

1.2 V LVCMOS

3.3 V PCI/PCIX

TBD

Per PCI/PCI-X

Specification

Per PCI Curves

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

25 mA

35 mA

33 mA

8 mA

268

169

268

169

32

181

124

181

124

39

HSTL (II)

15 mA

18 mA

14 mA

21 mA

66

55

SSTL2 (I)

83

87

SSTL2 (II)

SSTL3 (I)

169

51

124

54

SSTL3 (II)

* T_J= 100°C

103

109

2-36

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-39 • I/O Short Currents I_OSH/I_OSL

Applicable to Advanced I/O Banks for A3P1000 Only

Drive Strength

I

_OSL(mA)*

25

I_OSH(mA)*

27

3.3 V LVTTL / 3.3V LVCMOS

2mA

4mA

25

27

6mA

51

54

8mA

51

54

12mA

16mA

24mA

2mA

103

132

268

25

109

127

181

27

3.3 V LVCMOS

4mA

25

27

6mA

51

54

8mA

51

54

12mA

16mA

24mA

2mA

103

132

268

16

109

127

181

18

2.5 V LVCMOS

4mA

16

18

6mA

32

37

8mA

32

37

12mA

16mA

24mA

2mA

65

74

83

87

169

9

124

11

1.8 V LVCMOS

4mA

17

22

6mA

35

44

8mA

45

51

12mA

16mA

2mA

91

74

91

74

1.5 V LVCMOS

13

16

4mA

25

33

6mA

32

39

8mA

66

55

12mA

Per PCI/PCI-X specification

66

55

3.3 V PCI/PCI-X

103

109

* T_J= 100°C

v1.0

2-37

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-40 • I/O Short Currents I_OSH/I_OSL

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive Strength

I

_OSL(mA)*

25

I_OSH(mA)*

27

3.3 V LVTTL / 3.3V LVCMOS

2mA

4mA

25

27

6mA

51

54

8mA

51

54

12mA

103

16

109

18

16mA

2.5 V LVCMOS

2mA

4mA

16

18

6mA

32

37

8mA

32

37

12mA

65

74

1.8 V LVCMOS

1.5V LVCMOS

2mA

9

11

4mA

17

22

6mA

35

44

8mA

35

44

2mA

4mA

13

16

25

33

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

103

109

* T_J= 100°C

Table 2-41 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (typical) for Schmitt Mode Input

Buffers Applicable to A3PE600L and A3PE3000L Only

Input Buffer Configuration

Hysteresis Value (typical)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

1.2 V LVCMOS (Schmitt trigger mode)

240 mV

140 mV

80 mV

60 mV

40 mV

The length of time an I/O can withstand I_OSH/I_OSLevents depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

2-38

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-42 • Duration of Short Circuit Event before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

110°C

125°C

6 months

3 months

1 month

Table 2-43 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.)

No requirement

Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS

10 ns *

20 years (110°C)

10 years (100°C)

LVDS/B-LVDS/

No requirement

M-LVDS/LVPECL

* The maximum input rise/fall time is related to the noise induced in the input buffer trace. If the noise is low,

the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity

evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

v1.0

2-39

Military ProASIC3/EL Low-Power Flash FPGAs

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-44 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

4 mA

–0.3

0.8

2

3.6

0.4

2.4

4

8

4

8

25

51

27

54

15 15

8 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

103

132

268

109

127

181

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-45 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks for A3P1000 Only

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

25

27

15 15

4 mA

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

103

132

268

109

127

181

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

2-40

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-46 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks for A3P1000 Only

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

25

27

15 15

4 mA

6 mA

51

54

8 mA

51

54

12 mA

16 mA

Notes:

12 12

16 16

103

109

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

35 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-8 • AC Loading

Table 2-47 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C_LOAD(pF)

0

3.3

1.4

5

* Measuring point = V_trip.See Table 2-27 on page 2-27 for a complete table of trip points.

v1.0

2-41

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-48 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.80 6.03 0.05 1.74 2.39 0.52 6.14 4.84 2.66 2.42 8.35

7.06

6.00

6.35

5.40

5.82

4.95

5.71

4.85

5.72

4.87

ns

0.68 5.13 0.05 1.48 2.03 0.44 5.22 4.12 2.27 2.06 7.11

0.80 4.93 0.05 1.74 2.39 0.52 5.02 4.14 3.01 3.03 7.23

0.68 4.19 0.05 1.48 2.03 0.44 4.27 3.52 2.56 2.58 6.15

0.80 4.15 0.05 1.74 2.39 0.52 4.22 3.61 3.24 3.43 6.44

0.68 3.53 0.05 1.48 2.03 0.44 3.59 3.07 2.76 2.92 5.47

0.80 3.92 0.05 1.74 2.39 0.52 3.99 3.49 3.29 3.54 6.21

0.68 3.34 0.05 1.48 2.03 0.44 3.40 2.97 2.80 3.01 5.28

0.80 3.81 0.05 1.74 2.39 0.52 3.88 3.51 3.35 3.92 6.09

0.68 3.24 0.05 1.48 2.03 0.44 3.30 2.98 2.85 3.34 5.18

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-49 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.80 3.39 0.05 1.74 2.39 0.52 3.45 2.60 2.66 2.56 5.67

4.81

4.10

4.30

3.65

4.05

3.44

4.00

3.40

3.94

3.35

ns

0.68 2.89 0.05 1.48 2.03 0.44 2.94 2.21 2.27 2.18 4.82

0.80 2.79 0.05 1.74 2.39 0.52 2.84 2.08 3.02 3.18 5.05

0.68 2.37 0.05 1.48 2.03 0.44 2.42 1.77 2.57 2.70 4.30

0.80 2.45 0.05 1.74 2.39 0.52 2.49 1.83 3.24 3.58 4.71

0.68 2.08 0.05 1.48 2.03 0.44 2.12 1.56 2.76 3.04 4.00

0.80 2.39 0.05 1.74 2.39 0.52 2.43 1.79 3.30 3.69 4.65

0.68 2.03 0.05 1.48 2.03 0.44 2.07 1.52 2.80 3.14 3.95

0.80 2.41 0.05 1.74 2.39 0.52 2.46 1.72 3.35 4.08 4.67

0.68 2.05 0.05 1.48 2.03 0.44 2.09 1.47 2.85 3.47 3.97

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-42

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

1.5 V DC Core Voltage

Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 6.03 0.04 1.74 2.39 0.40 6.14 4.84 2.66 2.42 8.35

7.06

6.00

6.35

5.40

5.82

4.95

5.71

4.85

5.72

4.87

ns

0.52 5.13 0.03 1.48 2.03 0.34 5.22 4.12 2.27 2.06 7.11

0.61 4.93 0.04 1.74 2.39 0.40 5.02 4.14 3.01 3.03 7.23

0.52 4.19 0.03 1.48 2.03 0.34 4.27 3.52 2.56 2.58 6.15

0.61 4.15 0.04 1.74 2.39 0.40 4.22 3.61 3.24 3.43 6.44

0.52 3.53 0.03 1.48 2.03 0.34 3.59 3.07 2.76 2.92 5.47

0.61 3.92 0.04 1.74 2.39 0.40 3.99 3.49 3.29 3.54 6.21

0.52 3.34 0.03 1.48 2.03 0.34 3.40 2.97 2.80 3.01 5.28

0.61 3.81 0.04 1.74 2.39 0.40 3.88 3.51 3.35 3.92 6.09

0.52 3.24 0.03 1.48 2.03 0.34 3.30 2.98 2.85 3.34 5.18

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 3.39 0.04 1.74 2.39 0.40 3.45 2.60 2.66 2.56 5.67

4.81

4.10

4.30

3.65

4.05

3.44

4.00

3.40

3.94

3.35

ns

0.52 2.89 0.03 1.48 2.03 0.34 2.94 2.21 2.27 2.18 4.82

0.61 2.79 0.04 1.74 2.39 0.40 2.84 2.08 3.02 3.18 5.05

0.52 2.37 0.03 1.48 2.03 0.34 2.42 1.77 2.57 2.70 4.30

0.61 2.45 0.04 1.74 2.39 0.40 2.49 1.83 3.24 3.58 4.71

0.52 2.08 0.03 1.48 2.03 0.34 2.12 1.56 2.76 3.04 4.00

0.61 2.39 0.04 1.74 2.39 0.40 2.43 1.79 3.30 3.69 4.65

0.52 2.03 0.03 1.48 2.03 0.34 2.07 1.52 2.80 3.14 3.95

0.61 2.41 0.04 1.74 2.39 0.40 2.46 1.72 3.35 4.08 4.67

0.52 2.05 0.03 1.48 2.03 0.34 2.09 1.47 2.85 3.47 3.97

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-43

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

8.83

7.51

7.81

6.65

7.81

6.65

7.05

5.99

6.81

5.79

6.68

5.68

t_ZHS

7.75

6.59

7.04

5.99

7.04

5.99

6.51

5.54

6.39

5.43

6.43

5.47

Units

ns

4 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

6.25 0.05 1.12

5.32 0.04 0.95

5.25 0.05 1.12

4.47 0.04 0.95

5.25 0.05 1.12

4.47 0.04 0.95

4.50 0.05 1.12

3.83 0.04 0.95

4.27 0.05 1.12

3.63 0.04 0.95

4.14 0.05 1.12

3.53 0.04 0.95

6.37 5.29 2.91 2.70

5.42 4.50 2.47 2.30

5.35 4.58 3.28 3.34

4.55 3.90 2.79 2.85

5.35 4.58 3.28 3.34

4.55 3.90 2.79 2.85

4.59 4.05 3.53 3.76

3.90 3.45 3.00 3.20

4.35 3.93 3.58 3.86

3.70 3.34 3.05 3.29

4.22 3.97 3.65 4.27

3.59 3.38 3.10 3.63

ns

6 mA

Std.

–1

ns

8 mA

Std.

–1

ns

12 mA

16 mA

24 mA

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

6.07

5.17

5.46

4.65

5.46

4.65

5.14

4.38

5.09

4.33

5.12

4.35

t_ZHS

5.25

4.46

4.71

4.01

4.71

4.01

4.45

3.79

4.41

3.75

4.35

3.70

Units

ns

4 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

3.55 0.05 1.12

3.02 0.04 0.95

2.95 0.05 1.12

2.51 0.04 0.95

2.95 0.05 1.12

2.51 0.04 0.95

2.64 0.05 1.12

2.24 0.04 0.95

2.58 0.05 1.12

2.20 0.04 0.95

2.61 0.05 1.12

2.22 0.04 0.95

3.62 2.79 2.91 2.87

3.08 2.37 2.48 2.44

3.00 2.25 3.28 3.52

2.55 1.91 2.79 3.00

3.00 2.25 3.28 3.52

2.55 1.91 2.79 3.00

2.68 1.99 3.53 3.94

2.28 1.70 3.00 3.35

2.63 1.95 3.59 4.05

2.24 1.66 3.05 3.44

2.66 1.89 3.66 4.46

2.26 1.61 3.11 3.80

ns

6 mA

Std.

–1

ns

8 mA

Std.

–1

ns

12 mA

16 mA

24 mA

Notes:

Std.

–-1

Std.

–-1

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

2-44

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

8.20

6.98

7.19

6.11

7.19

6.11

6.47

5.51

6.47

5.51

t_ZHS

7.24

6.16

6.62

5.63

6.62

5.63

6.13

5.21

6.13

5.21

Units

ns

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

5.64 0.05 1.10

4.79 0.04 0.94

4.64 0.05 1.10

3.95 0.04 0.94

4.64 0.05 1.10

3.95 0.04 0.94

3.94 0.05 1.10

3.35 0.04 0.94

3.94 0.05 1.10

3.35 0.04 0.94

5.74 4.78 2.50 2.43

4.88 4.06 2.13 2.07

4.73 4.16 2.84 3.01

4.02 3.54 2.42 2.56

4.73 4.16 2.84 3.01

4.02 3.54 2.42 2.56

4.01 3.67 3.07 3.39

3.41 3.12 2.61 2.88

4.01 3.67 3.07 3.39

3.41 3.12 2.61 2.88

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.59

4.75

5.01

4.26

5.01

4.26

4.74

4.03

4.74

4.03

t_ZHS

4.91

4.18

4.43

3.76

4.43

3.76

4.18

3.56

4.18

3.56

Units

ns

4 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

3.07 0.05 1.10

2.61 0.04 0.94

2.51 0.05 1.10

2.13 0.04 0.94

2.51 0.05 1.10

2.13 0.04 0.94

2.24 0.05 1.10

1.90 0.04 0.94

2.24 0.05 1.10

1.90 0.04 0.94

3.13 2.46 2.50 2.57

2.66 2.09 2.13 2.19

2.55 1.97 2.84 3.16

2.17 1.67 2.41 2.69

2.55 1.97 2.84 3.16

2.17 1.67 2.41 2.69

2.28 1.72 3.07 3.54

1.94 1.47 2.61 3.01

2.28 1.72 3.07 3.54

1.94 1.47 2.61 3.01

ns

6 mA

Std.

–1

ns

8 mA

Std.

–1

ns

12 mA

16 mA

Notes:

Std.

–1

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

v1.0

2-45

Military ProASIC3/EL Low-Power Flash FPGAs

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-56 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

2.5 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

4 mA

–0.3

0.7

1.7

2.7

0.7

1.7

4

8

4

8

16

32

18

37

15 15

8 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

65

74

83

87

169

124

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-57 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks for A3P1000 Only

2.5 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

16

18

15 15

4 mA

6 mA

32

37

8 mA

32

37

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

65

74

83

87

169

124

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

2-46

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-58 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks for A3P1000 Only

2.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

16

32

65

18

37

74

15 15

12 12

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

35 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-9 • AC Loading

Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

2.5

1.2

5

* Measuring point = V_trip.See Table 2-27 on page 2-27 for a complete table of trip points.

v1.0

2-47

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-60 • 2.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 6.86 0.04 2.04 2.54 0.40 6.99 5.83 2.69 2.17 9.20

8.04

6.84

7.15

6.08

6.51

5.54

6.37

5.42

6.39

5.43

ns

0.52 5.84 0.03 1.74 2.16 0.34 5.95 4.96 2.29 1.85 7.83

0.61 5.61 0.04 2.04 2.54 0.40 5.72 4.94 3.07 2.90 7.93

0.52 4.77 0.03 1.74 2.16 0.34 4.86 4.20 2.61 2.47 6.75

0.61 4.72 0.04 2.04 2.54 0.40 4.81 4.30 3.33 3.36 7.02

0.52 4.02 0.03 1.74 2.16 0.34 4.09 3.66 2.84 2.86 5.98

0.61 4.45 0.04 2.04 2.54 0.40 4.53 4.16 3.39 3.49 6.75

0.52 3.79 0.03 1.74 2.16 0.34 3.86 3.54 2.88 2.97 5.74

0.61 4.33 0.04 2.04 2.54 0.40 4.41 4.18 3.46 3.96 6.63

0.52 3.69 0.03 1.74 2.16 0.34 3.76 3.55 2.94 3.37 5.64

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-61 • 2.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.80 3.50 0.05 2.04 2.54 0.52 3.57 3.13 2.69 2.26 5.78

5.34

4.54

4.62

3.93

4.26

3.63

4.20

3.57

4.11

3.50

ns

0.68 2.98 0.05 1.74 2.16 0.44 3.03 2.66 2.29 1.93 4.92

0.80 2.87 0.05 2.04 2.54 0.52 2.92 2.41 3.07 3.00 5.13

0.68 2.44 0.05 1.74 2.16 0.44 2.48 2.05 2.61 2.55 4.37

0.80 2.49 0.05 2.04 2.54 0.52 2.53 2.05 3.33 3.46 4.75

0.68 2.12 0.05 1.74 2.16 0.44 2.16 1.74 2.84 2.94 4.04

0.80 2.42 0.05 2.04 2.54 0.52 2.47 1.99 3.39 3.59 4.68

0.68 2.06 0.05 1.74 2.16 0.44 2.10 1.69 2.88 3.05 3.98

0.80 2.43 0.05 2.04 2.54 0.52 2.48 1.90 3.46 4.07 4.69

0.68 2.07 0.05 1.74 2.16 0.44 2.11 1.61 2.94 3.46 3.99

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-48

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

1.5 V DC Core Voltage

Table 2-62 • 2.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 6.86 0.04 2.04 2.54 0.40 6.99 5.83 2.69 2.17 9.20

8.04

6.84

7.15

6.08

6.51

5.54

6.37

5.42

6.39

5.43

ns

0.52 5.84 0.03 1.74 2.16 0.34 5.95 4.96 2.29 1.85 7.83

0.61 5.61 0.04 2.04 2.54 0.40 5.72 4.94 3.07 2.90 7.93

0.52 4.77 0.03 1.74 2.16 0.34 4.86 4.20 2.61 2.47 6.75

0.61 4.72 0.04 2.04 2.54 0.40 4.81 4.30 3.33 3.36 7.02

0.52 4.02 0.03 1.74 2.16 0.34 4.09 3.66 2.84 2.86 5.98

0.61 4.45 0.04 2.04 2.54 0.40 4.53 4.16 3.39 3.49 6.75

0.52 3.79 0.03 1.74 2.16 0.34 3.86 3.54 2.88 2.97 5.74

0.61 4.33 0.04 2.04 2.54 0.40 4.41 4.18 3.46 3.96 6.63

0.52 3.69 0.03 1.74 2.16 0.34 3.76 3.55 2.94 3.37 5.64

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-63 • 2.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 3.50 0.04 2.04 2.54 0.40 3.57 3.13 2.69 2.26 5.78

5.34

4.54

4.62

3.93

4.26

3.63

4.20

3.57

4.11

3.50

ns

0.52 2.98 0.03 1.74 2.16 0.34 3.03 2.66 2.29 1.93 4.92

0.61 2.87 0.04 2.04 2.54 0.40 2.92 2.41 3.07 3.00 5.13

0.52 2.44 0.03 1.74 2.16 0.34 2.48 2.05 2.61 2.55 4.37

0.61 2.49 0.04 2.04 2.54 0.40 2.53 2.05 3.33 3.46 4.75

0.52 2.12 0.03 1.74 2.16 0.34 2.16 1.74 2.84 2.94 4.04

0.61 2.42 0.04 2.04 2.54 0.40 2.47 1.99 3.39 3.59 4.68

0.52 2.06 0.03 1.74 2.16 0.34 2.10 1.69 2.88 3.05 3.98

0.61 2.43 0.04 2.04 2.54 0.40 2.48 1.90 3.46 4.07 4.69

0.52 2.07 0.03 1.74 2.16 0.34 2.11 1.61 2.94 3.46 3.99

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-49

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-64 • 2.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.66

8.22

8.48

7.21

8.48

7.21

7.61

6.47

7.32

6.23

7.19

6.12

t_ZHS

8.78

7.47

7.88

6.70

7.88

6.70

7.25

6.17

7.10

6.04

7.17

6.10

Units

ns

4 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

7.07 0.05 1.44

6.02 0.04 1.23

5.91 0.05 1.44

5.03 0.04 1.23

5.91 0.05 1.44

5.03 0.04 1.23

5.05 0.05 1.44

4.30 0.04 1.23

4.78 0.05 1.44

4.06 0.04 1.23

4.71 0.05 1.44

4.01 0.04 1.23

7.20 6.32 2.95 2.43

6.13 5.38 2.51 2.06

6.02 5.42 3.35 3.18

5.12 4.61 2.85 2.70

6.02 5.42 3.35 3.18

5.12 4.61 2.85 2.70

5.15 4.79 3.63 3.66

4.38 4.07 3.09 3.11

4.86 4.65 3.70 3.78

4.14 3.95 3.14 3.22

4.73 4.71 3.78 4.26

4.03 4.01 3.21 3.62

ns

6 mA

Std.

–1

ns

8 mA

Std.

–1

ns

12 mA

16 mA

24 mA

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-65 • 2.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

6.16

5.24

5.50

4.68

5.50

4.68

5.16

4.39

5.10

4.34

5.12

4.35

t_ZHS

5.80

4.94

5.05

4.30

5.05

4.30

4.69

3.99

4.62

3.93

4.54

3.87

Units

ns

4 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

3.63 0.05 1.44

3.09 0.04 1.23

2.99 0.05 1.44

2.54 0.04 1.23

2.99 0.05 1.44

2.54 0.04 1.23

2.65 0.05 1.44

2.26 0.04 1.23

2.59 0.05 1.44

2.21 0.04 1.23

2.61 0.05 1.44

2.22 0.04 1.23

3.70 3.34 2.94 2.53

3.15 2.84 2.51 2.16

3.04 2.59 3.35 3.30

2.59 2.20 2.85 2.81

3.04 2.59 3.35 3.30

2.59 2.20 2.85 2.81

2.70 2.23 3.63 3.78

2.30 1.89 3.09 3.22

2.64 2.16 3.70 3.90

2.25 1.83 3.15 3.32

2.66 2.08 3.78 4.40

2.26 1.77 3.22 3.74

ns

6 mA

Std.

–1

ns

8 mA

Std.

–1

ns

12 mA

16 mA

24 mA

Notes:

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

2-50

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-66 • 2.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.02

7.68

7.84

6.67

7.84

6.67

7.02

5.97

t_ZHS

8.17

6.95

7.38

6.28

7.38

6.28

6.81

5.79

Units

ns

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

6.45 0.05 1.43

5.48 0.04 1.21

5.28 0.05 1.43

4.50 0.04 1.21

5.28 0.05 1.43

4.50 0.04 1.21

4.48 0.05 1.43

3.81 0.04 1.21

6.56 5.71 2.48 2.19

5.58 4.86 2.11 1.86

5.38 4.92 2.85 2.88

4.58 4.19 2.42 2.45

5.38 4.92 2.85 2.88

4.58 4.19 2.42 2.45

4.56 4.35 3.11 3.31

3.88 3.70 2.65 2.82

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-67 • 2.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.69

4.84

5.08

4.32

5.08

4.32

4.78

4.07

t_ZHS

5.38

4.58

4.70

4.00

4.70

4.00

4.36

3.71

Units

ns

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

3.18 0.05 1.43

2.70 0.04 1.21

2.57 0.05 1.43

2.19 0.04 1.21

2.57 0.05 1.43

2.19 0.04 1.21

2.28 0.05 1.43

1.94 0.04 1.21

3.23 2.92 2.48 2.28

2.75 2.48 2.11 1.94

2.62 2.24 2.84 2.98

2.23 1.90 2.42 2.54

2.62 2.24 2.84 2.98

2.23 1.90 2.42 2.54

2.32 1.90 3.11 3.42

1.97 1.62 2.64 2.91

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

v1.0

2-51

Military ProASIC3/EL Low-Power Flash FPGAs

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-68 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3 0.35 * V_CCI0.65 * V_CCI

1.9

0.45 V_CCI– 0.45

2

4

6

8

2

4

6

8

9

11

22

44

51

74

15 15

4 mA

–0.3 0.35 * V_CCI0.65 * V_CCI

17

35

45

91

6 mA

8 mA

12 mA

16 mA

Notes:

0.45 V_CCI– 0.45 12 12

0.45 V_CCI– 0.45 16 16

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-69 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks for A3P1000 Only

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI1.9

0.45 V_CCI– 0.45

2

4

6

8

2

4

6

8

9

11

22

44

51

74

15 15

–0.3 0.35 * V_CCI0.65 * V_CCI1.9

17

35

45

91

–0.3 0.35 * V_CCI0.65 * V_CCI

1.9

0.45 V_CCI– 0.45 12 12

0.45 V_CCI– 0.45 16 16

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

2-52

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-70 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSH

I_IL

I_IH

Drive

Strength Min., V

Max., Max.,

Max., V

Min., V

Max., V Max., V

Min., V

mA mA mA¹mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.35 * V_CCI0.65 * V_CCI

1.9

0.45

V_CCI– 0.45

2

4

6

8

2

4

6

8

9

11

22

44

15 15

–0.3 0.35 * V_CCI0.65 * V_CCI

17

35

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

35 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-10 • AC Loading

Table 2-71 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.8

0.9

5

* Measuring point = V_trip.See Table 2-27 on page 2-27 for a complete table of trip points.

v1.0

2-53

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-72 • 1.8 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.7 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.80 9.15 0.05 1.98 2.80 0.52 9.32 7.69 2.75 1.57 11.54 9.90

ns

0.68 7.79 0.05 1.69 2.38 0.44 7.93 6.54 2.34 1.33 9.81

0.80 7.54 0.05 1.98 2.80 0.52 7.68 6.48 3.22 2.74 9.89

0.68 6.41 0.05 1.69 2.38 0.44 6.53 5.51 2.74 2.33 8.42

0.80 6.39 0.05 1.98 2.80 0.52 6.51 5.65 3.53 3.32 8.72

0.68 5.44 0.05 1.69 2.38 0.44 5.54 4.80 3.00 2.83 7.42

0.80 6.01 0.05 1.98 2.80 0.52 6.12 5.48 3.60 3.49 8.33

0.68 5.11 0.05 1.69 2.38 0.44 5.20 4.66 3.07 2.97 7.09

0.80 5.89 0.05 1.98 2.80 0.52 6.00 5.49 3.70 4.07 8.22

0.68 5.01 0.05 1.69 2.38 0.44 5.11 4.67 3.15 3.46 6.99

0.80 5.89 0.05 1.98 2.80 0.52 6.00 5.49 3.70 4.07 8.22

0.68 5.01 0.05 1.69 2.38 0.44 5.11 4.67 3.15 3.46 6.99

8.42

8.69

7.39

7.86

6.69

7.70

6.55

7.71

6.56

7.71

6.56

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-73 • 1.8 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.7 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

Std.

–1

0.80 4.14 0.05 1.98 2.80 0.52 4.21 4.05 2.75 1.62 6.43

6.27

5.33

5.22

4.44

4.71

4.00

4.61

3.92

4.49

3.82

4.49

3.82

ns

0.68 3.52 0.05 1.69 2.38 0.44 3.58 3.45 2.34 1.38 5.47

0.80 3.35 0.05 1.98 2.80 0.52 3.42 3.01 3.22 2.84 5.63

0.68 2.85 0.05 1.69 2.38 0.44 2.91 2.56 2.74 2.41 4.79

0.80 2.87 0.05 1.98 2.80 0.52 2.93 2.49 3.53 3.43 5.14

0.68 2.44 0.05 1.69 2.38 0.44 2.49 2.12 3.00 2.92 4.37

0.80 2.78 0.05 1.98 2.80 0.52 2.83 2.40 3.60 3.59 5.05

0.68 2.37 0.05 1.69 2.38 0.44 2.41 2.04 3.06 3.05 4.29

0.80 2.77 0.05 1.98 2.80 0.52 2.82 2.28 3.70 4.19 5.03

0.68 2.36 0.05 1.69 2.38 0.44 2.40 1.94 3.14 3.57 4.28

0.80 2.77 0.05 1.98 2.80 0.52 2.82 2.28 3.70 4.19 5.03

0.68 2.36 0.05 1.69 2.38 0.44 2.40 1.94 3.14 3.57 4.28

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-54

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

1.5 V DC Core Voltage

Table 2-74 • 1.8 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.61 9.15 0.04 1.98 2.80 0.40 9.32 7.69 2.75 1.57 11.54 9.90

ns

0.52 7.79 0.03 1.69 2.38 0.34 7.93 6.54 2.34 1.33 9.81

0.61 7.54 0.04 1.98 2.80 0.40 7.68 6.48 3.22 2.74 9.89

0.52 6.41 0.03 1.69 2.38 0.34 6.53 5.51 2.74 2.33 8.42

0.61 6.39 0.04 1.98 2.80 0.40 6.51 5.65 3.53 3.32 8.72

0.52 5.44 0.03 1.69 2.38 0.34 5.54 4.80 3.00 2.83 7.42

0.61 6.01 0.04 1.98 2.80 0.40 6.12 5.48 3.60 3.49 8.33

0.52 5.11 0.03 1.69 2.38 0.34 5.20 4.66 3.07 2.97 7.09

0.61 5.89 0.04 1.98 2.80 0.40 6.00 5.49 3.70 4.07 8.22

0.52 5.01 0.03 1.69 2.38 0.34 5.11 4.67 3.15 3.46 6.99

0.61 5.89 0.04 1.98 2.80 0.40 6.00 5.49 3.70 4.07 8.22

0.52 5.01 0.03 1.69 2.38 0.34 5.11 4.67 3.15 3.46 6.99

8.42

8.69

7.39

7.86

6.69

7.70

6.55

7.71

6.56

7.71

6.56

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-75 • 1.8 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

Std.

–1

0.61 4.14 0.04 1.98 2.80 0.40 4.21 4.05 2.75 1.62 6.43

6.27

5.33

5.22

4.44

4.71

4.00

4.61

3.92

4.49

3.82

4.49

3.82

ns

0.52 3.52 0.03 1.69 2.38 0.34 3.58 3.45 2.34 1.38 5.47

0.61 3.35 0.04 1.98 2.80 0.40 3.42 3.01 3.22 2.84 5.63

0.52 2.85 0.03 1.69 2.38 0.34 2.91 2.56 2.74 2.41 4.79

0.61 2.87 0.04 1.98 2.80 0.40 2.93 2.49 3.53 3.43 5.14

0.52 2.44 0.03 1.69 2.38 0.34 2.49 2.12 3.00 2.92 4.37

0.61 2.78 0.04 1.98 2.80 0.40 2.83 2.40 3.60 3.59 5.05

0.52 2.37 0.03 1.69 2.38 0.34 2.41 2.04 3.06 3.05 4.29

0.61 2.77 0.04 1.98 2.80 0.40 2.82 2.28 3.70 4.19 5.03

0.52 2.36 0.03 1.69 2.38 0.34 2.40 1.94 3.14 3.57 4.28

0.61 2.77 0.04 1.98 2.80 0.40 2.82 2.28 3.70 4.19 5.03

0.52 2.36 0.03 1.69 2.38 0.34 2.40 1.94 3.14 3.57 4.28

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-55

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-76 • 1.8 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

9.50 0.05 1.44

8.08 0.04 1.23

7.80 0.05 1.44

6.64 0.04 1.23

6.70 0.05 1.44

5.70 0.04 1.23

6.31 0.05 1.44

5.37 0.04 1.23

6.18 0.05 1.44

5.26 0.04 1.23

6.18 0.05 1.44

5.26 0.04 1.23

9.68 8.31 3.06 1.76 12.14 10.77

8.23 7.07 2.60 1.50 10.32

7.95 7.06 3.55 3.01 10.41

9.16

9.52

8.10

8.70

7.40

8.53

7.26

8.61

7.32

8.61

7.32

ns

Std.

–1

ns

6.76 6.00 3.02 2.56

6.82 6.25 3.89 3.60

5.80 5.31 3.31 3.06

6.43 6.07 3.97 3.75

5.47 5.17 3.37 3.19

6.30 6.15 4.08 4.34

5.36 5.23 3.47 3.70

6.30 6.15 4.08 4.34

5.36 5.23 3.47 3.70

8.85

9.28

7.90

8.89

7.56

8.76

7.45

8.76

7.45

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-77 • 1.8 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

6.94

5.90

5.96

5.07

5.53

4.71

5.45

4.64

5.44

4.63

5.44

4.63

t_ZHS

6.76

5.75

5.69

4.84

5.16

4.39

5.06

4.31

4.95

4.21

4.95

4.21

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

4.40 0.05 1.34

3.74 0.04 1.14

3.44 0.05 1.34

2.92 0.04 1.14

3.02 0.05 1.34

2.57 0.04 1.14

2.94 0.05 1.34

2.50 0.04 1.14

2.93 0.05 1.34

2.49 0.04 1.14

2.93 0.05 1.34

2.49 0.04 1.14

4.48 4.30 3.05 1.82

3.81 3.66 2.59 1.55

3.50 3.23 3.54 3.12

2.98 2.75 3.01 2.66

3.07 2.70 3.88 3.72

2.61 2.30 3.30 3.16

2.99 2.60 3.96 3.87

2.54 2.21 3.37 3.30

2.98 2.49 4.07 4.49

2.54 2.12 3.46 3.82

2.98 2.49 4.07 4.49

2.54 2.12 3.46 3.82

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

2-56

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-78 • 1.8 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

9.97

8.48

8.89

7.56

8.14

6.93

8.14

6.93

Units

ns

2 mA

4 mA

6 mA

8 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

8.81 0.05 1.43

7.50 0.04 1.21

7.10 0.05 1.43

6.04 0.04 1.21

6.06 0.05 1.43

5.16 0.04 1.21

6.06 0.05 1.43

5.16 0.04 1.21

8.98 7.51 2.48 1.61 11.44

7.64 6.39 2.11 1.37

7.23 6.43 2.92 2.75

6.15 5.47 2.48 2.34

6.17 5.68 3.23 3.29

5.25 4.84 2.75 2.80

6.17 5.68 3.23 3.29

5.25 4.84 2.75 2.80

9.73

9.69

8.24

8.63

7.34

8.63

7.34

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-79 • 1.8 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

6.47

5.51

5.55

4.72

5.16

4.39

5.16

4.39

t_ZHS

6.18

5.26

5.21

4.43

4.73

4.02

4.73

4.02

Units

ns

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

3.94 0.05 1.32

3.35 0.04 1.12

3.03 0.05 1.32

2.58 0.04 1.12

2.65 0.05 1.32

2.26 0.04 1.12

2.65 0.05 1.32

2.26 0.04 1.12

4.01 3.72 2.47 1.67

3.41 3.16 2.10 1.42

3.09 2.75 2.91 2.86

2.63 2.34 2.48 2.44

2.70 2.27 3.22 3.41

2.30 1.93 2.74 2.90

2.70 2.27 3.22 3.41

2.30 1.93 2.74 2.90

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

v1.0

2-57

Military ProASIC3/EL Low-Power Flash FPGAs

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-80 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI

2

4

6

8

2

4

6

8

13

25

32

66

16

33

39

55

15 15

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI12 12

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-81 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks for A3P1000 Only

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI

2

4

6

8

2

4

6

8

13

25

32

66

16

33

39

55

15 15

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI12 12

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

2-58

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-82 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks for A3P1000 Only

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI

2

4

2

4

13

25

16

33

15 15

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

35 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-11 • AC Loading

Table 2-83 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.5

0.75

5

* Measuring point = V_trip.See Table 2-27 on page 2-27 for a complete table of trip points.

v1.0

2-59

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-84 • 1.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.80 9.52 0.05 2.19 3.05 0.52 9.69 7.89 3.37 2.65 11.91 10.10

ns

0.68 8.10 0.05 1.86 2.59 0.44 8.25 6.71 2.87 2.26 10.13 8.59

0.80 8.14 0.05 2.19 3.05 0.52 8.29 6.89 3.73 3.32 10.50 9.10

Std.

–1

0.68 6.92 0.05 1.86 2.59 0.44 7.05 5.86 3.17 2.83 8.93

0.80 7.64 0.05 2.19 3.05 0.52 7.78 6.70 3.80 3.51 9.99

0.68 6.50 0.05 1.86 2.59 0.44 6.62 5.70 3.24 2.99 8.50

0.80 7.54 0.05 2.19 3.05 0.52 7.68 6.71 3.93 4.18 9.89

0.68 6.41 0.05 1.86 2.59 0.44 6.53 5.71 3.34 3.55 8.41

0.80 7.54 0.05 2.19 3.05 0.52 7.68 6.71 3.93 4.18 9.89

0.68 6.41 0.05 1.86 2.59 0.44 6.53 5.71 3.34 3.55 8.41

7.74

8.92

7.59

8.92

7.59

8.92

7.59

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-85 • 1.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.80 3.91 0.05 2.19 3.05 0.52 3.98 3.54 3.36 2.76 6.19

5.76

4.90

5.12

4.35

5.00

4.25

4.85

4.12

4.85

4.12

ns

0.68 3.32 0.05 1.86 2.59 0.44 3.38 3.01 2.86 2.35 5.27

0.80 3.33 0.05 2.19 3.05 0.52 3.39 2.90 3.71 3.44 5.61

0.68 2.83 0.05 1.86 2.59 0.44 2.89 2.47 3.16 2.93 4.77

0.80 3.22 0.05 2.19 3.05 0.52 3.28 2.78 3.80 3.63 5.49

0.68 2.74 0.05 1.86 2.59 0.44 2.79 2.37 3.23 3.09 4.67

0.80 3.18 0.05 2.19 3.05 0.52 3.24 2.63 3.92 4.33 5.46

0.68 2.71 0.05 1.86 2.59 0.44 2.76 2.24 3.34 3.68 4.64

0.80 3.18 0.05 2.19 3.05 0.52 3.24 2.63 3.92 4.33 5.46

0.68 2.71 0.05 1.86 2.59 0.44 2.76 2.24 3.34 3.68 4.64

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-60

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

1.5 V DC Core Voltage

Table 2-86 • 1.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.61 9.52 0.04 2.19 3.05 0.40 9.69 7.89 3.37 2.65 11.91 10.10

ns

0.52 8.10 0.03 1.86 2.59 0.34 8.25 6.71 2.87 2.26 10.13 8.59

0.61 8.14 0.04 2.19 3.05 0.40 8.29 6.89 3.73 3.32 10.50 9.10

Std.

–1

0.52 6.92 0.03 1.86 2.59 0.34 7.05 5.86 3.17 2.83 8.93

0.61 7.64 0.04 2.19 3.05 0.40 7.78 6.70 3.80 3.51 9.99

0.52 6.50 0.03 1.86 2.59 0.34 6.62 5.70 3.24 2.99 8.50

0.61 7.54 0.04 2.19 3.05 0.40 7.68 6.71 3.93 4.18 9.89

0.52 6.41 0.03 1.86 2.59 0.34 6.53 5.71 3.34 3.55 8.41

0.61 7.54 0.04 2.19 3.05 0.40 7.68 6.71 3.93 4.18 9.89

0.52 6.41 0.03 1.86 2.59 0.34 6.53 5.71 3.34 3.55 8.41

7.74

8.92

7.59

8.92

7.59

8.92

7.59

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-87 • 1.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.61 3.91 0.04 2.19 3.05 0.40 3.98 3.54 3.36 2.76 6.19

5.76

4.90

5.12

4.35

5.00

4.25

4.85

4.12

4.85

4.12

ns

0.52 3.32 0.03 1.86 2.59 0.34 3.38 3.01 2.86 2.35 5.27

0.61 3.33 0.04 2.19 3.05 0.40 3.39 2.90 3.71 3.44 5.61

0.52 2.83 0.03 1.86 2.59 0.34 2.89 2.47 3.16 2.93 4.77

0.61 3.22 0.04 2.19 3.05 0.40 3.28 2.78 3.80 3.63 5.49

0.52 2.74 0.03 1.86 2.59 0.34 2.79 2.37 3.23 3.09 4.67

0.61 3.18 0.04 2.19 3.05 0.40 3.24 2.63 3.92 4.33 5.46

0.52 2.71 0.03 1.86 2.59 0.34 2.76 2.24 3.34 3.68 4.64

0.61 3.18 0.04 2.19 3.05 0.40 3.24 2.63 3.92 4.33 5.46

0.52 2.71 0.03 1.86 2.59 0.34 2.76 2.24 3.34 3.68 4.64

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-61

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-88 • 1.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

9.96 8.57 3.74 2.91 12.42 11.03

8.47 7.29 3.18 2.47 10.56 9.38

8.60 7.59 4.12 3.60 11.06 10.05

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

9.78 0.05 1.44

8.32 0.04 1.23

8.44 0.05 1.44

7.18 0.04 1.23

7.95 0.05 1.44

6.77 0.04 1.23

7.84 0.05 1.44

6.67 0.04 1.23

7.84 0.05 1.44

6.67 0.04 1.23

ns

Std.

–1

ns

7.32 6.46 3.51 3.06

8.10 7.39 4.21 3.78 10.56

6.89 6.29 3.58 3.21 8.98

7.98 7.47 4.35 4.45 10.44

6.79 6.35 3.70 3.79 8.88

7.98 7.47 4.35 4.45 10.44

6.79 6.35 3.70 3.79 8.88

9.41

8.55

9.85

8.38

9.92

8.44

9.92

8.44

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-89 • 1.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

6.52

5.54

5.99

5.10

5.89

5.01

5.87

4.99

5.87

4.99

t_ZHS

6.26

5.32

5.61

4.77

5.48

4.66

5.34

4.55

5.34

4.55

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

0.63

0.54

3.98 0.05 1.58

3.39 0.04 1.35

3.47 0.05 1.58

2.95 0.04 1.35

3.37 0.05 1.58

2.87 0.04 1.35

3.35 0.05 1.58

2.85 0.04 1.35

3.35 0.05 1.58

2.85 0.04 1.35

4.06 3.80 3.73 3.04

3.45 3.23 3.17 2.59

3.53 3.15 4.11 3.74

3.01 2.68 3.50 3.18

3.43 3.02 4.20 3.92

2.92 2.57 3.57 3.33

3.41 2.88 4.34 4.62

2.90 2.45 3.69 3.93

3.41 2.88 4.34 4.62

2.90 2.45 3.69 3.93

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

2-62

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-90 • 1.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

Std.

–1

0.63

0.54

0.63

0.54

8.94 0.05 1.43

7.61 0.04 1.21

7.68 0.05 1.43

6.54 0.04 1.21

9.11 7.80 2.99 2.67 11.57 10.26

7.75 6.64 2.54 2.27

7.83 6.91 3.34 3.30 10.29

6.66 5.88 2.84 2.80 8.75

9.84

8.73

9.37

7.97

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-91 • 1.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.45

0.39

0.45

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

6.07

5.16

5.60

4.77

t_ZHS

5.68

4.83

5.08

4.32

Units

ns

2 mA

4 mA

Notes:

Std.

–1

0.63

0.54

0.63

0.54

3.55 0.05 1.56

3.02 0.04 1.33

3.09 0.05 1.56

2.62 0.04 1.33

3.61 3.22 2.98 2.80

3.07 2.74 2.54 2.39

3.14 2.62 3.34 3.44

2.67 2.23 2.84 2.93

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

v1.0

2-63

Military ProASIC3/EL Low-Power Flash FPGAs

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose

1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer.

Table 2-92 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Operating at 1.2 V Core Voltage

1.2 V

LVCMOS

1

2

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA Max., mA µA µA

2 mA

–0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI0.75 * V_CCI

2

TBD

15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-12 • AC Loading

Table 2-93 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.2

0.6

5

* Measuring point = V_trip.See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

1.2 V DC Core Voltage

Table 2-94 • 1.2 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.80 12.62 0.05 2.62 3.76 0.52 12.07 9.47 5.12 4.68 14.20 11.60

0.68 10.73 0.05 2.23 3.20 0.44 10.27 8.05 4.36 3.98 12.08 9.87

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-95 • 1.2 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only

Drive

Speed

Strength

Grade t_DOUTt_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.80

0.68

5.17 0.05 2.62 3.76 0.52

4.40 0.05 2.23 3.20 0.44

4.95 4.36 5.11 4.83 7.08

4.21 3.71 4.35 4.11 6.02

6.49

5.52

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-64

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

Table 2-96 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

Drive Strength

Per PCI specification

Notes:

V_IL

Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA¹Max, mA¹µA²µA²

Per PCI curves 15 15

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the database; Actel loadings for enable

path characterization are described in Figure 2-13.

R to V_CCIfor t_DP(F)

R to GND for t_DP(R)

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-13 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-97.

Table 2-97 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

0.285 * V_CCIfor t_DP(R)

0.615 * V_CCIfor t_DP(F)

C_LOAD(pF)

0

3.3

10

* Measuring point = V_trip.See Table 2-27 on page 2-27 for a complete table of trip points.

v1.0

2-65

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-98 • 3.3 V PCI/PCI-X

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

3.67 0.52

3.12 0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.80 2.78

0.68 2.36

0.05 2.72

0.05 2.31

2.83 1.98

2.41 1.68

3.24 3.58

2.76 3.04

5.04 4.19

4.29 3.56

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

1.5 V DC Core Voltage

Table 2-99 • 3.3 V PCI/PCI-X

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

3.67 0.40

3.12 0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.61 2.78

0.52 2.36

0.04 2.72

0.03 2.31

2.83 1.98

2.41 1.68

3.24 3.58

2.76 3.04

5.04 4.19

4.29 3.56

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-100 • 3.3 V PCI/PCI-X

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks for A3P1000 Only

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

0.45 2.81

0.39 2.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.63 2.95

0.54 2.51

0.05 0.95

0.04 0.81

1.98 3.53

1.68 3.00

3.94 5.46

3.35 4.65

4.61 0.63

3.92 0.54

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

Table 2-101 • 3.3 V PCI/PCI-X

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks for A3P1000 Only

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

0.45 2.39

0.39 2.03

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.63 2.54

0.54 2.16

0.05 0.94

0.04 0.80

1.71 3.07

1.45 2.61

3.54 5.04

3.01 4.29

4.33 0.63

3.69 0.54

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

2-66

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The V_CCIpin should be connected to 3.3 V.

Table 2-102 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL

Drive

Strength Min., V Max., V

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

–0.3 V_REF– 0.05 V_REF+ 0.05 3.6 0.4 25 25 268 181 15 15

25 mA³

–

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

GTL

25

Test Point

10 pF

Figure 2-14 • AC Loading

Table 2-103 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

10

V_REF– 0.05

V_REF+ 0.05

0.8

1.2

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-104 • 3.3 V GTL

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 3.0 V, V_REF= 0.8 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.23

3.60

t_ZHS

4.27

3.63

Units

ns

2.05

1.75

2.33

1.98

2.02

1.72

2.05

1.75

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-105 • 3.3 V GTL

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 3.0 V, V_REF= 0.8 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.23

3.60

t_ZHS

4.27

3.63

Units

ns

2.05

1.75

2.33

1.98

2.02

1.72

2.05

1.75

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-67

Military ProASIC3/EL Low-Power Flash FPGAs

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to

2.5 V.

Table 2-106 • Minimum and Maximum DC Input and Output Levels

2.5 GTL

Drive

Strength Min., V Max., V

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Min., V

Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2.7 0.4 25 25 169 124 15 15

25 mA³

–0.3 V_REF– 0.05 V_REF+ 0.05

–

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

GTL

25

Test Point

10 pF

Figure 2-15 • AC Loading

Table 2-107 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

10

V_REF– 0.05

V_REF+ 0.05

0.8

1.2

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-108 • 2.5 V GTL

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 3.0 V, V_REF= 0.8 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.35

3.70

t_ZHS

4.32

3.68

Units

ns

2.11

1.79

2.26

1.92

2.14

1.82

2.11

1.79

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-109 • 2.5 V GTL

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 3.0 V, V_REF= 0.8 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.35

3.70

t_ZHS

4.32

3.68

Units

ns

2.11

1.79

2.26

1.92

2.14

1.82

2.11

1.79

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-68

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to

3.3 V.

Table 2-110 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

3.6 0.6 35 35 268 181 15 15

35 mA

–0.3 V_REF– 0.1 V_REF+ 0.1

–

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

V_TT

GTL+

25

Test Point

10 pF

Figure 2-16 • AC Loading

Table 2-111 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

10

V_REF– 0.1

V_REF+ 0.1

1.0

1.5

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-112 • 3.3 V GTL+

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 3.0 V, V_REF= 1.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.29

3.65

t_ZHS

4.25

3.61

Units

ns

2.03

1.73

2.33

1.98

2.07

1.76

2.03

1.73

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-113 • 3.3 V GTL+

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 3.0 V, V_REF= 1.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.29

3.65

t_ZHS

4.25

3.61

Units

ns

2.03

1.73

2.33

1.98

2.07

1.76

2.03

1.73

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-69

Military ProASIC3/EL Low-Power Flash FPGAs

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to

2.5 V.

Table 2-114 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2.7 0.6 33 33 169 124 15 15

33 mA

–0.3 V_REF– 0.1 V_REF+ 0.1

–

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

V_TT

GTL+

25

Test Point

10 pF

Figure 2-17 • AC Loading

Table 2-115 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

10

V_REF– 0.1

V_REF+ 0.1

1.0

1.5

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-116 • 2.5 V GTL+

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 2.3 V, V_REF= 1.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.44

3.78

t_ZHS

4.29

3.65

Units

ns

2.18

1.86

2.26

1.92

2.22

1.89

2.08

1.77

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-117 • 2.5 V GTL+

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 2.3 V, V_REF= 1.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.44

3.78

t_ZHS

4.29

3.65

Units

ns

2.18

1.86

2.26

1.92

2.22

1.89

2.08

1.77

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-70

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

Military ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a

push-pull output buffer.

Table 2-118 • Minimum and Maximum DC Input and Output Levels

HSTL Class I

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

8 mA

–0.3 V_REF– 0.1 V_REF+ 0.1 1.575

0.4

V_CCI– 0.4

8

32

39

15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

V_TT

HSTL

Class I

50

Test Point

20 pF

Figure 2-18 • AC Loading

Table 2-119 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring Point*

Input LOW (V)

Input HIGH (V)

(V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

20

V_REF– 0.1

V_REF+ 0.1

0.75

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-120 • HSTL Class I

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 1.4 V, V_REF= 0.75 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.42

4.61

t_ZHS

5.33

4.53

Units

ns

3.15

2.68

2.75

2.34

3.21

2.73

3.11

2.65

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-121 • HSTL Class I

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 1.4 V, V_REF= 0.75 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.42

4.61

t_ZHS

5.33

4.53

Units

ns

3.15

2.68

2.75

2.34

3.21

2.73

3.11

2.65

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-71

Military ProASIC3/EL Low-Power Flash FPGAs

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

Military ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a

push-pull output buffer.

Table 2-122 • Minimum and Maximum DC Input and Output Levels

HSTL Class II

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

15 mA³

–0.3 V_REF– 0.1 V_REF+ 0.1 1.575

0.4

V_CCI– 0.4 15 15

66

55

15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

HSTL

Class II

25

Test Point

20 pF

Figure 2-19 • AC Loading

Table 2-123 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

20

V_REF– 0.1

V_REF+ 0.1

0.75

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-124 • HSTL Class II

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 1.4 V, V_REF= 0.75 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.26

4.48

t_ZHS

4.90

4.17

Units

ns

2.99

2.55

2.75

2.34

3.05

2.59

2.69

2.29

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-125 • HSTL Class II

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 1.4 V, V_REF= 0.75 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.26

4.48

t_ZHS

4.90

4.17

Units

ns

2.99

2.55

2.75

2.34

3.05

2.59

2.69

2.29

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-72

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Military ProASIC3E devices

support Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-126 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class I

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

15 mA

–0.3 V_REF– 0.2 V_REF+ 0.2

2.7

0.54 V_CCI– 0.62 15 15

83

87

15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

V_TT

SSTL2

Class I

50

Test Point

25

30 pF

Figure 2-20 • AC Loading

Table 2-127 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

30

V_REF– 0.2

V_REF+ 0.2

1.25

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-128 • SSTL2 Class I

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 2.3 V, V_REF= 1.25 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.14

1.82

t_ZHS

1.83

1.56

Units

ns

2.11

1.79

2.08

1.77

2.14

1.82

1.83

1.56

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-129 • SSTL2 Class I

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 2.3 V, V_REF= 1.25 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.14

1.82

t_ZHS

1.83

1.56

Units

ns

2.11

1.79

2.08

1.77

2.14

1.82

1.83

1.56

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-73

Military ProASIC3/EL Low-Power Flash FPGAs

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Military ProASIC3E devices

support Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-130 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class II

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

18 mA

–0.3 V_REF– 0.2 V_REF+ 0.2

2.7

0.35 V_CCI– 0.43 18 18

169

124

15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

V_TT

SSTL2

Class II

25

Test Point

25

30 pF

Figure 2-21 • AC Loading

Table 2-131 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

30

V_REF– 0.2

V_REF+ 0.2

1.25

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-132 • SSTL2 Class II

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 2.3 V, V_REF= 1.25 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.19

1.86

t_ZHS

1.75

1.49

Units

ns

2.15

1.83

2.08

1.77

2.19

1.86

1.75

1.49

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-133 • SSTL2 Class II

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 2.3 V, V_REF= 1.25 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.19

1.86

t_ZHS

1.75

1.49

Units

ns

2.15

1.83

2.08

1.77

2.19

1.86

1.75

1.49

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-74

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Military ProASIC3E devices

support Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-134 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

14 mA

–0.3 V_REF– 0.2 V_REF+ 0.2

3.6

0.7 V_CCI– 1.1 14 14

51

54

15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

V_TT

SSTL3

Class I

50

Test Point

25

30 pF

Figure 2-22 • AC Loading

Table 2-135 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

30

V_REF– 0.2

V_REF+ 0.2

1.5

1.485

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-136 • SSTL3 Class I

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 3.0 V, V_REF= 1.5 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.33

1.98

t_ZHS

1.82

1.55

Units

ns

2.28

1.94

1.99

1.69

2.33

1.98

1.82

1.55

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-137 • SSTL3 Class I

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 3.0 V, V_REF= 1.5 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.33

1.98

t_ZHS

1.82

1.55

Units

ns

2.28

1.94

1.99

1.69

2.33

1.98

1.82

1.55

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

v1.0

2-75

Military ProASIC3/EL Low-Power Flash FPGAs

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Military ProASIC3E devices

support Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-138 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

21 mA

–0.3 V_REF– 0.2 V_REF+ 0.2

3.6

0.5 V_CCI– 0.9 21 21

103

109

15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 125°C junction temperature.

V_TT

SSTL3

Class II

25

Test Point

25

30 pF

Figure 2-23 • AC Loading

Table 2-139 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input LOW (V)

Input HIGH (V)

Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

30

V_REF– 0.2

V_REF+ 0.2

1.5

1.485

* Measuring point = V_trip. See Table 2-27 on page 2-27 for a complete table of trip points.

Timing Characteristics

Table 2-140 • SSTL3 Class II

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V,

Worst-Case V_CCI= 3.0 V, V_REF= 1.5 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

t_EOUT

0.52

0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.08

1.77

t_ZHS

1.65

1.41

Units

ns

2.04

1.74

1.99

1.69

2.08

1.77

1.65

1.41

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-141 • SSTL3 Class II

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V,

Worst-Case V_CCI= 3.0 V, V_REF= 1.5 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed

Grade

Std.

–1

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.08

1.77

t_ZHS

1.65

1.41

Units

ns

2.04

1.74

1.99

1.69

2.08

1.77

1.65

1.41

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-76

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Actel Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-24. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, military ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-

LVDS) configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

165 Ω

Z₀= 50 Ω

140 Ω

Z₀= 50 Ω

INBUF_LVDS

+

–

100 Ω

N

Figure 2-24 • LVDS Circuit Diagram and Board-Level Implementation

v1.0

2-77

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-142 • Minimum and Maximum DC Input and Output Levels

DC Parameter

Description

Supply Voltage

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V

V_CCI

V_OL

V_OH

Output Low Voltage

1.075

1.425

0.91

V

Output High Voltage

1.25

0.65

0

V

4

Output Lower Current

Output High Current

I_OL

1.16

2.925

10

mA

V

4

I_OH

Input Voltage

V_I

3

Input High Leakage Current

Input Low Leakage Current

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

I_IH

µA

mV

V

3

I_IL

10

V_ODIFF

V_OCM

V_ICM

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

V_IDIFF

Notes:

mV

1.

5%

2. Differential input voltage = 350 mV.

3. Currents are measured at 125°C junction temperature.

4. I_OL/I_OHis defined by V_ODIFF/(Resistor Network).

Table 2-143 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

1.075

1.325

Cross point

* Measuring point = V_trip.See Table 2-27 on page 2-27 for a complete table of trip points.

2-78

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-144 • LVDS

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed Grade

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

Units

ns

Std.

–1

1.81

1.57

2.39

2.04

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

1.5 V DC Core Voltage

Table 2-145 • LVDS

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed Grade

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

1.81

1.57

2.39

2.04

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-146 • LVDS

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks for A3P1000 Only

Speed Grade

t_DOUT

0.63

t_DP

t_DIN

0.05

0.04

t_PY

Units

ns

Std.

–1

2.01

1.71

1.76

1.50

0.54

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

v1.0

2-79

Military ProASIC3/EL Low-Power Flash FPGAs

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations

may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers

require series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus since the driver can be located anywhere on the bus. These

configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-25. The input and output

buffer delays are available in the LVDS section in Table 2-142 on page 2-78.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:

R_S= 60 Ω and R_T= 70 Ω, given Z₀= 50 Ω (2") and Z_stub= 50 Ω (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-25 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

2-80

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-26. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVDS implementation

because the output standard specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

P

OUTBUF_LVPECL

100 Ω

Z = 50 Ω

0

INBUF_LVPECL

+

–

187 W

Z = 50 Ω

100 Ω

0

N

Figure 2-26 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-147 • Minimum and Maximum DC Input and Output Levels

DC Parameter

V_CCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

Min.

Max.

Units

V

3.0

3.3

3.6

V_OL

Output LOW Voltage

0.96

1.8

1.27

2.11

3.3

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.9

V

V_OH

Output HIGH Voltage

V

V_IL, V_IH

V_ODIFF

V_OCM

Input LOW, Input HIGH Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

0

V

0.625

1.762

1.01

300

0.97 0.625

1.98 1.762

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

V

V_ICM

2.57

1.01

300

V

V_IDIFF

mV

Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

1.64

1.94

Cross point

* Measuring point = V_trip.See Table 2-27 on page 2-27 for a complete table of trip points.

v1.0

2-81

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-149 • LVPECL

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed Grade

t_DOUT

0.80

t_DP

t_DIN

0.05

t_PY

Units

ns

Std.

–1

1.81

1.54

2.16

1.84

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

1.5 V DC Core Voltage

Table 2-150 • LVPECL

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Speed Grade

t_DOUT

0.61

t_DP

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

1.81

1.54

2.16

1.84

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-151 • LVPECL

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks for A3P1000 Only

Speed Grade

t_DOUT

0.63

t_DP

t_DIN

0.05

0.04

t_PY

Units

ns

Std.

–1

1.98

1.68

1.54

1.31

0.54

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

2-82

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

L

D

DOUT

Data_out

PRE

DFN1E1P1

F

PRE

DFN1E1P1

Y

E

Core

Array

Data

Enable

CLK

D

Q

D

Q

C

G

E

EOUT

B

H

I

A

PRE

DFN1E1P1

J

D

Q

K

Data Input I/O Register with:

Active High Enable

E

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

INBUF

CLKBUF

Postive-Edge Triggered

Figure 2-27 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

v1.0

2-83

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-152 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

G, H

L, DOUT

L, H

t_OHE

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

J, H

t_OESUE

t_OEHE

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

* See Figure 2-27 on page 2-83 for more information.

2-84

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

CLR

LL

HH

AA

DD

JJ

D

Q

CLR

DFN1E1C1

KK

E

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-28 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

v1.0

2-85

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-153 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

FF, HH

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

GG, HH

LL, DOUT

LL, HH

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

JJ, HH

t_OESUE

t_OEHE

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

* See Figure 2-28 on page 2-85 for more information.

2-86

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Input Register

t_ICKMPWHt_ICKMPWL

50%

CLK

t_IHD

t_ISUD

50%

1

0

Data

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-29 • Input Register Timing Diagram

v1.0

2-87

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

Table 2-154 • Input Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V for A3PE600L and A3PE3000L

Description

Clock-to-Q of the Input Data Register

Parameter

t_ICLKQ

–1 Std. Units

0.33 0.39 ns

0.36 0.43 ns

0.00 0.00 ns

0.51 0.60 ns

0.00 0.00 ns

0.63 0.74 ns

0.00 0.00 ns

0.31 0.36 ns

0.00 0.00 ns

0.31 0.36 ns

0.19 0.22 ns

0.31 0.36 ns

0.28 0.32 ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-155 • Input Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V for A3PE600L and A3PE3000L

Parameter

t_ICLKQ

Description

Clock-to-Q of the Input Data Register

–1 Std. Units

0.25 0.30 ns

0.28 0.33 ns

0.00 0.00 ns

0.39 0.46 ns

0.00 0.00 ns

0.48 0.56 ns

0.00 0.00 ns

0.24 0.28 ns

0.00 0.00 ns

0.24 0.28 ns

0.19 0.22 ns

0.31 0.36 ns

0.28 0.32 ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

2-88

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Table 2-156 • Input Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.425 V for A3P1000

Parameter

t_ICLKQ

Description

–1 Std. Units

0.29 0.34 ns

0.32 0.37 ns

0.00 0.00 ns

0.45 0.53 ns

0.00 0.00 ns

0.55 0.64 ns

0.00 0.00 ns

0.27 0.31 ns

0.00 0.00 ns

0.27 0.31 ns

0.25 0.30 ns

0.41 0.48 ns

0.37 0.43 ns

Clock-to-Q of the Input Data Register

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating

values.

v1.0

2-89

Military ProASIC3/EL Low-Power Flash FPGAs

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

1

0

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

t_OHE

50%

t_OSUE

t_OREMCLR

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-30 • Output Register Timing Diagram

2-90

v1.0

Military ProASIC3/EL Low-Power Flash FPGAs

Timing Characteristics

Table 2-157 • Output Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, Worst-Case V_CC= 1.14 V for A3PE600L and A3PE3000L

Description –1 Std. Units

Clock-to-Q of the Output Data Register

Parameter

t_OCLKQ

t_OSUD

0.81 0.96

0.43 0.51

0.00 0.00

0.61 0.71

0.00 0.00

1.11 1.31

0.00 0.00

0.31 0.36

0.00 0.00

0.31 0.36

0.19 0.22

0.31 0.36

0.28 0.32

ns

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

t_OCKMPWHClock Minimum Pulse Width HIGH for the Output Data Register

t_OCKMPWLClock Minimum Pulse Width LOW for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-158 • Output Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, V_CC= 1.425 V for A3PE600L and A3PE3000L

Parameter

t_OCLKQ

t_OSUD

Description

Clock-to-Q of the Output Data Register

–1 Std. Units

0.62 0.73

0.33 0.39

0.00 0.00

0.46 0.55

0.00 0.00

0.85 1.00

0.00 0.00

0.24 0.28