M1AFS250-1PQG256I_技术文档

Preliminary v1.7

®

Actel Fusion Mixed-Signal FPGAs

Family with Optional ARM Support

®

– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

Features and Benefits

Low Power Consumption

High-Performance Reprogrammable Flash

• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

• Sleep and Standby Low Power Modes

Technology

• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Nonvolatile, Retains Program when Powered Off

• Live at Power-Up (LAPU) Single-Chip Solution

• 350 MHz System Performance

In-System Programming (ISP) and Security

• Secure ISP with 128-Bit AES via JTAG

®

• FlashLock to Secure FPGA Contents

Advanced Digital I/O

Embedded Flash Memory

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

• User Flash Memory – 2 Mbits to 8 Mbits

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

• 1 kbit of Additional FlashROM

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI

LVCMOS 2.5 V / 5.0 V Input

/ 3.3 V PCI-X, and

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

– Built-In I/O Registers

Integrated A/D Converter (ADC) and Analog I/O

• Up to 12-Bit Resolution and up to 600 ksps

• Internal 2.56 V or External Reference Voltage

• ADC: Up to 30 Scalable Analog Input Channels

• High-Voltage Input Tolerance: –10.5 V to +12 V

• Current Monitor and Temperature Monitor Blocks

• Up to 10 MOSFET Gate Driver Outputs

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths

• ADC Accuracy is Better than 1%

– 700 Mbps DDR Operation

• Hot-Swappable I/Os

• Programmable Output Slew Rate, Drive Strength, and Weak

Pull-Up/Down Resistor

• Pin-Compatible Packages across the Fusion Family

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

On-Chip Clocking Support

• Programmable Embedded FIFO Control Logic

• Internal 100 MHz RC Oscillator (accurate to 1%)

• Crystal Oscillator Support (32 kHz to 20 MHz)

• Programmable Real-Time Counter (RTC)

• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated

PLLs

Soft ARM7™ Core Support in M7 and M1 Fusion Devices

• ARM Cortex™-M1 (without debug), CoreMP7Sd (with

debug) and CoreMP7S (without debug)

– Phase Shift, Multiply/Divide, and Delay Capabilities

Fusion Family

Fusion Devices

AFS090

AFS250

AFS600

AFS1500

CoreMP7 ¹

Cortex-M1 ²

M7AFS600

ARM-Enabled

Fusion Devices

M1AFS250

M1AFS600

M1AFS1500

System Gates

90,000

2,304

Yes

1

250,000

6,144

Yes

1

600,000

13,824

Yes

2

1,500,000

38,400

Yes

2

Tiles (D-flip-flops)

Secure (AES) ISP

PLLs

General

Information

Globals

18

1

18

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

FlashROM Bits

1

2

4

2 M

1 k

6

2 M

1 k

8

4 M

1 k

24

8 M

1 k

60

Memory

RAM Blocks (4,608 bits)

RAM kbits

27

5

36

108

10

270

10

Analog Quads

6

Analog Input Channels

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

15

5

18

30

6

10

Analog and I/Os

4

5

75

20

114

24

172

40

252

40

Notes:

1. Refer to the CoreMP7 datasheet for more information.

2. Refer to the Cortex-M1 product brief for more information.

October 2008

I

Actel Fusion Mixed-Signal FPGAs

Fusion Device Architecture Overview

Bank 0

Bank 1

CCC

SRAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

OSC

I/Os

CCC/PLL

VersaTile

SRAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

ISP AES

Decryption

User Nonvolatile

FlashROM

Charge Pumps

Flash Memory Blocks

ADC

Flash Memory Blocks

Analog Analog Analog Analog Analog Analog Analog

Quad Quad Quad Quad Quad Quad Quad

Analog Analog

Quad Quad

Analog

Quad

CCC

Bank 3

Figure 1-1 • Fusion Device Architecture Overview (AFS600)

Package I/Os: Single-/Double-Ended (Analog)

Fusion Devices

AFS090

AFS250

AFS600

AFS1500

CoreMP7

M7AFS600

M1AFS600

ARM-Enabled Devices

QN108

Cortex-M1

M1AFS250

M1AFS1500

37/9 (16)

QN180

60/16 (20)

65/15 (24)

93/26 (24)

114/37 (24)

PQ208

95/46 (40)

119/58 (40)

172/86 (40)

FG256

75/22 (20)

119/58 (40)

223/109 (40)

252/126 (40)

FG484

FG676

Note: All devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600).

II

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Product Ordering Codes

_

M7AFS600

1

FG

G

256

I

Application (ambient temperature range)

Blank = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

PP = Pre-Production

ES = Engineering Silicon (room temperature only)

Package Lead Count

Lead-Free Packaging Options

Blank = Standard Packaging

G = RoHS-Compliant (green) Packaging

Package Type

=

QN

PQ

FG

Quad Flat No Lead (0.5 mm pitch)

Plastic Quad Flat Pack (0.5 mm pitch)

Fine Pitch Ball Grid Array (1.0 mm pitch)

Speed Grade

F = 20% Slower than Standard

Blank = Standard

1 = 15% Faster than Standard

2 = 25% Faster than Standard

Part Number

Fusion Devices

AFS090 = 90,000 System Gates

AFS250 = 250,000 System Gates

AFS600 = 600,000 System Gates

AFS1500 = 1,500,000 System Gates

ARM-Enabled Fusion Devices

M7AFS600 = 600,000 System Gates

M1AFS250 = 250,000 System Gates

M1AFS600 = 600,000 System Gates

M1AFS1500 = 1,500,000 System Gates

Notes:

1. DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for

the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and

will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial

temperature range.

2. Quad Flat No Lead packages are only offered as RoHS compliant, QNG.

Preliminary v1.7

III

Actel Fusion Mixed-Signal FPGAs

Temperature Grade Offerings

Fusion Devices

AFS090

AFS250

AFS600

AFS1500

CoreMP7

M7AFS600

ARM-Enabled Devices

QN108

Cortex-M1

M1AFS250

M1AFS600

M1AFS1500

C, I

–

C, I

–

QN180

PQ208

C, I

–

FG256

C, I

–

C, I

FG484

FG676

–

Notes:

1. C = Commercial Temperature Range: 0°C to 70°C Ambient

2. I = Industrial Temperature Range: –40°C to 85°C Ambient

Speed Grade and Temperature Grade Matrix

–F¹

✓

–

Std.

–1

✓

–2

✓

C²

I³

✓

Notes:

1. DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided

for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added

and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial

temperature range.

2. C = Commercial Temperature Range: 0°C to 70°C Ambient

3. I = Industrial Temperature Range: –40°C to 85°C Ambient

Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).

IV

Preliminary v1.7

1 – Fusion Device Family Overview

Introduction

The Actel Fusion^®mixed-signal FPGA satisfies the demand from system architects for a device that

simplifies design and unleashes their creativity. As the world’s first mixed-signal programmable

logic family, Fusion integrates mixed-signal analog, flash memory, and FPGA fabric in a monolithic

device. Actel Fusion devices enable designers to quickly move from concept to completed design

and then deliver feature-rich systems to market. This new technology takes advantage of the

unique properties of Actel flash-based FPGAs, including a high-isolation, triple-well process and the

ability to support high-voltage transistors to meet the demanding requirements of mixed-signal

system design.

Actel Fusion mixed-signal FPGAs bring the benefits of programmable logic to many application

areas, including power management, smart battery charging, clock generation and management,

and motor control. Until now, these applications have only been implemented with costly and

space-consuming discrete analog components or mixed-signal ASIC solutions. Actel Fusion mixed-

signal FPGAs present new capabilities for system development by allowing designers to integrate a

wide range of functionality into a single device, while at the same time offering the flexibility of

upgrades late in the manufacturing process or after the device is in the field. Actel Fusion devices

provide an excellent alternative to costly and time-consuming mixed-signal ASIC designs. In

addition, when used in conjunction with the Actel or ARM-based soft MCU core, Actel Fusion

technology represents the definitive mixed-signal FPGA platform.

Flash-based Fusion devices are live at power-up. As soon as system power is applied and within

normal operating specifications, Fusion devices are working. Fusion devices have a 128-bit flash-

based lock and industry-leading AES decryption, used to secure programmed intellectual property

(IP) and configuration data. Actel Fusion devices are the most comprehensive single-chip analog

and digital programmable logic solution available today.

To support this new ground-breaking technology, Actel has developed a series of major tool

innovations to help maximize designer productivity. Implemented as extensions to the popular

Actel Libero^®Integrated Design Environment (IDE), these new tools allow designers to easily

instantiate and configure peripherals within a design, establish links between peripherals, create

or import building blocks or reference designs, and perform hardware verification. This tool suite

will also add comprehensive hardware/software debug capability as well as a suite of utilities to

simplify development of embedded soft-processor-based solutions.

General Description

The Actel Fusion family, based on the highly successful ProASIC^®3 and ProASIC3E Flash FPGA

architecture, has been designed as a high-performance, programmable, mixed-signal platform. By

combining an advanced flash FPGA core with flash memory blocks and analog peripherals, Fusion

devices dramatically simplify system design and, as a result, dramatically reduce overall system cost

and board space.

The state-of-the-art flash memory technology offers high-density integrated flash memory blocks,

enabling savings in cost, power, and board area relative to external flash solutions, while providing

increased flexibility and performance. The flash memory blocks and integrated analog peripherals

enable true mixed-mode programmable logic designs. Two examples are using an on-chip soft

processor to implement a fully functional Flash MCU and using high-speed FPGA logic to offer

system and power supervisory capabilities. Live at power-up and capable of operating from a single

3.3 V supply, the Fusion family is ideally suited for system management and control applications.

The devices in the Fusion family are categorized by FPGA core density. Each family member

contains many peripherals, including flash memory blocks, an analog-to-digital-converter (ADC),

high-drive outputs, both RC and crystal oscillators, and a real-time counter (RTC). This provides the

Preliminary v1.7

1-1

Fusion Device Family Overview

user with a high level of flexibility and integration to support a wide variety of mixed-signal

applications. The flash memory block capacity ranges from 2 Mbits to 8 Mbits. The integrated 12-

bit ADC supports up to 30 independently configurable input channels. The on-chip crystal and RC

oscillators work in conjunction with the integrated phase-locked loops (PLLs) to provide clocking

support to the FPGA array and on-chip resources. In addition to supporting typical RTC uses such as

watchdog timer, the Fusion RTC can control the on-chip voltage regulator to power down the

device (FPGA fabric, flash memory block, and ADC), enabling a low-power standby mode.

The Actel Fusion family offers revolutionary features, never before available in an FPGA. The

nonvolatile flash technology gives the Fusion solution the advantage of being a secure, low-power,

single-chip solution that is live at power-up. Fusion is reprogrammable and offers time to market

benefits at an ASIC-level unit cost. These features enable designers to create high-density systems

using existing ASIC or FPGA design flows and tools.

The family has up to 1.5 M system gates, supported with up to 270 kbits of true dual-port SRAM, up

to 8 Mbits of flash memory, 1 kbit of user FlashROM, and up to 278 user I/Os. With integrated flash

memory, the Fusion family is the ultimate soft-processor platform. The AFS600 and AFS1500 devices

both support the Actel ARM7 core (CoreMP7). The ARM-enabled versions are identified with the

M7 prefix as M7AFS600 and M7AFS1500. The AFS250, AFS600, and AFS1500 devices support the

Actel Cortex-M1 core. The Cortex-M1-enabled versions are identified with the M1 prefix as

M1AFS250, M1AFS600, and M1AFS1500.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-

based Fusion devices are live at power-up and do not need to be loaded from an external boot

PROM. On-board security mechanisms prevent access to the programming information and enable

secure remote updates of the FPGA logic. Designers can perform secure remote in-system

reprogramming to support future design iterations and field upgrades, with confidence that

valuable IP cannot be compromised or copied. Secure ISP can be performed using the industry-

standard AES algorithm with MAC data authentication on the device. The Fusion family device

architecture mitigates the need for ASIC migration at higher user volumes. This makes the Fusion

family a cost-effective ASIC replacement solution for applications in the consumer, networking and

communications, computing, and avionics markets.

Security

As the nonvolatile, flash-based Fusion family requires no boot PROM, there is no vulnerable

external bitstream. Fusion devices incorporate FlashLock, which provides a unique combination of

reprogrammability and design security without external overhead, advantages that only an FPGA

with nonvolatile flash programming can offer.

Fusion devices utilize a 128-bit flash-based key lock and a separate AES key to secure programmed

IP and configuration data. The FlashROM data in Fusion devices can also be encrypted prior to

loading. Additionally, the Flash memory blocks can be programmed during runtime using the

industry-leading AES-128 block cipher encryption standard (FIPS Publication 192). The AES standard

was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the

DES standard, which was adopted in 1977. Fusion devices have a built-in AES decryption engine

and a flash-based AES key that make Fusion devices the most comprehensive programmable logic

device security solution available today. Fusion devices with AES-based security allow for secure

remote field updates over public networks, such as the Internet, and ensure that valuable IP

remains out of the hands of system overbuilders, system cloners, and IP thieves. As an additional

security measure, the FPGA configuration data of a programmed Fusion device cannot be read

back, although secure design verification is possible. During design, the user controls and defines

both internal and external access to the flash memory blocks.

Security, built into the FPGA fabric, is an inherent component of the Fusion family. The Flash cells

are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. Fusion with FlashLock and AES security is unique

in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected,

1-2

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

making secure remote ISP possible. A Fusion device provides the most impenetrable security for

programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

Fusion FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

Flash-based Fusion devices are Level 0 live at power-up (LAPU). LAPU Fusion devices greatly simplify

total system design and reduce total system cost by eliminating the need for CPLDs. The Fusion

LAPU clocking (PLLs) replaces off-chip clocking resources. The Fusion mix of LAPU clocking and

analog resources makes these devices an excellent choice for both system supervisor and system

management functions. LAPU from a single 3.3 V source enables Fusion devices to initiate, control,

and monitor multiple voltage supplies while also providing system clocks. In addition, glitches and

brownouts in system power will not corrupt the Fusion device flash configuration. Unlike SRAM-

based FPGAs, the device will not have to be reloaded when system power is restored. This enables

reduction or complete removal of expensive voltage monitor and brownout detection devices from

the PCB design. Flash-based Fusion devices simplify total system design and reduce cost and design

risk, while increasing system reliability.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

Another source of radiation-induced firm errors is alpha particles. For an alpha to cause a soft or

firm error, its source must be in very close proximity to the affected circuit. The alpha source must

be in the package molding compound or in the die itself. While low-alpha molding compounds are

being used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors.

Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not occur in Fusion Flash-based FPGAs. Once it is

programmed, the flash cell configuration element of Fusion FPGAs cannot be altered by high-

energy neutrons and is therefore immune to errors from them.

Recoverable (or soft) errors occur in the user data SRAMs of all FPGA devices. These can easily be

mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based Fusion devices exhibit power characteristics similar to those of an ASIC, making them

an ideal choice for power-sensitive applications. With Fusion devices, there is no power-on current

surge and no high current transition, both of which occur on many FPGAs.

Fusion devices also have low dynamic power consumption and support both low power standby

mode and very low power sleep mode, offering further power savings.

Advanced Flash Technology

The Fusion family offers many benefits, including nonvolatility and reprogrammability through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows very high logic utilization

(much higher than competing SRAM technologies) without compromising device routability or

performance. Logic functions within the device are interconnected through a four-level routing

hierarchy.

Preliminary v1.7

1-3

Fusion Device Family Overview

Advanced Architecture

The proprietary Fusion architecture provides granularity comparable to standard-cell ASICs. The

Fusion device consists of several distinct and programmable architectural features, including the

following (Figure 1-1 on page 1-5):

•

Embedded memories

–

Flash memory blocks

FlashROM

SRAM and FIFO

•

Clocking resources

–

PLL and CCC

RC oscillator

Crystal oscillator

No-Glitch MUX (NGMUX)

•

Digital I/Os with advanced I/O standards

FPGA VersaTiles

Analog components

–

ADC

Analog I/Os supporting voltage, current, and temperature monitoring

1.5 V on-board voltage regulator

Real-time counter

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic lookup table (LUT) equivalent or a D-flip-flop or latch (with or without enable) by

programming the appropriate flash switch interconnections. This versatility allows efficient use of

the FPGA fabric. The VersaTile capability is unique to the Actel families of flash-based FPGAs.

VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. Flash

switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect

programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid (3.3 V) single-voltage

programming of Fusion devices via an IEEE 1532 JTAG interface.

Unprecedented Integration

Integrated Analog Blocks and Analog I/Os

Fusion devices offer robust and flexible analog mixed-signal capability in addition to the high-

performance flash FPGA fabric and flash memory block. The many built-in analog peripherals

include a configurable 32:1 input analog MUX, up to 10 independent MOSFET gate driver outputs,

and a configurable ADC. The ADC supports 8-, 10-, and 12-bit modes of operation with a

cumulative sample rate up to 600 k samples per second (ksps), differential nonlinearity (DNL) < 1.0

LSB, and Total Unadjusted Error (TUE) of 0.72 LSB in 10-bit mode. The TUE is used for

characterization of the conversion error and includes errors from all sources, such as offset and

linearity. Internal bandgap circuitry offers 1% voltage reference accuracy with the flexibility of

utilizing an external reference voltage. The ADC channel sampling sequence and sampling rate are

programmable and implemented in the FPGA logic using Designer and Libero IDE software tool

support.

Two channels of the 32-channel ADCMUX are dedicated. Channel 0 is connected internally to V_CC

and can be used to monitor core power supply. Channel 31 is connected to an internal temperature

diode which can be used to monitor device temperature. The 30 remaining channels can be

connected to external analog signals. The exact number of I/Os available for external connection

signals is device-dependent (refer to the "Fusion Family" table on page I for details).

1-4

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

With Fusion, Actel also introduces the Analog Quad I/O structure (Figure 1-1 on page 1-5). Each

quad consists of three analog inputs and one gate driver. Each quad can be configured in various

built-in circuit combinations, such as three prescaler circuits, three digital input circuits, a current

monitor circuit, or a temperature monitor circuit. Each prescaler has multiple scaling factors

programmed by FPGA signals to support a large range of analog inputs with positive or negative

polarity. When the current monitor circuit is selected, two adjacent analog inputs measure the

voltage drop across a small external sense resistor. Built-in operational amplifiers amplify small

voltage signals (2 mV sensitivity) for accurate current measurement. One analog input in each quad

can be connected to an external temperature monitor diode and achieves detection accuracy of

3ꢀC. In addition to the external temperature monitor diode(s), a Fusion device can monitor an

internal temperature diode using dedicated channel 31 of the ADCMUX.

Figure 1-1 on page 1-5 illustrates a typical use of the Analog Quad I/O structure. The Analog Quad

shown is configured to monitor and control an external power supply. The AV pad measures the

source of the power supply. The AC pad measures the voltage drop across an external sense resistor

to calculate current. The AG MOSFET gate driver pad turns the external MOSFET on and off. The AT

pad measures the load-side voltage level.

Power

Line Side

Load Side

Off-Chip

R_pullup

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Pre-

scaler

Pre-

scaler

Pre-

scaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor/Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 1-1 • Analog Quad

Embedded Memories

Flash Memory Blocks

The flash memory available in each Fusion device is composed of one to four flash blocks, each 2

Mbits in density. Each block operates independently with a dedicated flash controller and

interface. Fusion flash memory blocks combine fast access times (60 ns random access and 10 ns

access in Read-Ahead mode) with a configurable 8-, 16-, or 32-bit datapath, enabling high-speed

Preliminary v1.7

1-5

Fusion Device Family Overview

flash operation without wait states. The memory block is organized in pages and sectors. Each

page has 128 bytes, with 33 pages comprising one sector and 64 sectors per block. The flash block

can support multiple partitions. The only constraint on size is that partition boundaries must

coincide with page boundaries. The flexibility and granularity enable many use models and allow

added granularity in programming updates.

Fusion devices support two methods of external access to the flash memory blocks. The first

method is a serial interface that features a built-in JTAG-compliant port, which allows in-system

programmability during user or monitor/test modes. This serial interface supports programming of

an AES-encrypted stream. Secure data can be passed through the JTAG interface, decrypted, and

then programmed in the flash block. The second method is a soft parallel interface.

FPGA logic or an on-chip soft microprocessor can access flash memory through the parallel

interface. Since the flash parallel interface is implemented in the FPGA fabric, it can potentially be

customized to meet special user requirements. For more information, refer to the CoreCFI

Handbook. The flash memory parallel interface provides configurable byte-wide (×8), word-wide

(×16), or dual-word-wide (×32) data port options. Through the programmable flash parallel

interface, the on-chip and off-chip memories can be cascaded for wider or deeper configurations.

The flash memory has built-in security. The user can configure either the entire flash block or the

small blocks to prevent unintentional or intrusive attempts to change or destroy the storage

contents. Each on-chip flash memory block has a dedicated controller, enabling each block to

operate independently.

The flash block logic consists of the following sub-blocks:

•

Flash block – Contains all stored data. The flash block contains 64 sectors and each sector

contains 33 pages of data.

Page Buffer – Contains the contents of the current page being modified. A page contains 8

blocks of data.

Block Buffer – Contains the contents of the last block accessed. A block contains 128 data

bits.

ECC Logic – The flash memory stores error correction information with each block to

perform single-bit error correction and double-bit error detection on all data blocks.

User Nonvolatile FlashROM

In addition to the flash blocks, Actel Fusion devices have 1 kbit of user-accessible, nonvolatile

FlashROM on-chip. The FlashROM is organized as 8×128-bit pages. The FlashROM can be used in

diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard IEEE 1532 JTAG programming interface. Pages can be

individually programmed (erased and written). On-chip AES decryption can be used selectively over

public networks to securely load data such as security keys stored in the FlashROM for a user

design.

The FlashROM can be programmed (erased and written) via the JTAG programming interface, and

its contents can be read back either through the JTAG programming interface or via direct FPGA

core addressing.

The FlashPoint tool in the Actel Fusion development software solutions, Libero IDE and Designer,

has extensive support for flash memory blocks and FlashROM. One such feature is auto-generation

of sequential programming files for applications requiring a unique serial number in each part.

Another feature allows the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using the Actel Libero IDE and Designer software

1-6

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

tools. Comprehensive programming file support is also included to allow for easy programming of

large numbers of parts with differing FlashROM contents.

SRAM and FIFO

Fusion devices have embedded SRAM blocks along the north and south sides of the device. Each

variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,

512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that

can be configured with different bit widths on each port. For example, data can be written

through a 4-bit port and read as a single bitstream. The SRAM blocks can be initialized from the

flash memory blocks or via the device JTAG port (ROM emulation mode), using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal EMPTY and FULL flags. The

embedded FIFO control unit contains the counters necessary for the generation of the read and

write address pointers. The SRAM/FIFO blocks can be cascaded to create larger configurations.

Clock Resources

PLLs and Clock Conditioning Circuits (CCCs)

Fusion devices provide designers with very flexible clock conditioning capabilities. Each member of

the Fusion family contains six CCCs. In the two larger family members, two of these CCCs also

include a PLL; the smaller devices support one PLL.

The inputs of the CCC blocks are accessible from the FPGA core or from one of several inputs with

dedicated CCC block connections.

The CCC block has the following key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz to 350 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz to 350 MHz

Clock phase adjustment via programmable and fixed delays from –6.275 ns to +8.75 ns

Clock skew minimization (PLL)

Clock frequency synthesis (PLL)

On-chip analog clocking resources usable as inputs:

–

100 MHz on-chip RC oscillator

Crystal oscillator

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°

Output duty cycle = 50% 1.5%

Low output jitter. Samples of peak-to-peak period jitter when a single global network is

used:

–

70 ps at 350 MHz

90 ps at 100 MHz

180 ps at 24 MHz

Worst case < 2.5% × clock period

•

Maximum acquisition time = 150 µs

Low power consumption of 5 mW

Global Clocking

Fusion devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there are on-chip oscillators as well as a comprehensive global clock

distribution network.

The integrated RC oscillator generates a 100 MHz clock. It is used internally to provide a known

clock source to the flash memory read and write control. It can also be used as a source for the PLLs.

Preliminary v1.7

1-7

Fusion Device Family Overview

The crystal oscillator supports the following operating modes:

•

Crystal (32.768 kHz to 20 MHz)

Ceramic (500 kHz to 8 MHz)

RC (32.768 kHz to 4 MHz)

Each VersaTile input and output port has access to nine VersaNets: six main and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

MUXes. The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of

high-fanout nets.

Digital I/Os with Advanced I/O Standards

The Fusion family of FPGAs features a flexible digital I/O structure, supporting a range of voltages

(1.5 V, 1.8 V, 2.5 V, and 3.3 V). Fusion FPGAs support many different digital I/O standards, both

single-ended and differential.

The I/Os are organized into banks, with four or five banks per device. The configuration of these

banks determines the I/O standards supported. The banks along the east and west sides of the

device support the full range of I/O standards (single-ended and differential). The south bank

supports the Analog Quads (analog I/O). In the family's two smaller devices, the north bank

supports multiple single-ended digital I/O standards. In the family’s larger devices, the north bank is

divided into two banks of digital Pro I/Os, supporting a wide variety of single-ended, differential,

and voltage-referenced I/O standards.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following applications:

•

Single-Data-Rate (SDR) applications

Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communications

Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points.

VersaTiles

The Fusion core consists of VersaTiles, which are also used in the successful Actel ProASIC3 family.

The Fusion VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set and optional enable

Refer to Figure 1-2 for the VersaTile configuration arrangement.

LUT-3 Equivalent

D-Flip-Flop with Clear or Set

Enable D-Flip-Flop with Clear or Set

Data

CLK

CLR

Y

X1

X2

X3

Data

CLK

Enable

Y

D-FF

LUT-3

D-FFE

Y

CLR

Figure 1-2 • VersaTile Configurations

1-8

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Read Next Operation

The Read Next operation is a feature by which the next block relative to the block in the Block

Buffer is read from the FB Array while performing reads from the Block Buffer. The goal is to

minimize wait states during consecutive sequential Read operations.

The Read Next operation is performed in a predetermined manner because it does look-ahead

reads. The general look-ahead function is as follows:

•

Within a page, the next block fetched will be the next in linear address.

When reading the last data block of a page, it will fetch the first block of the next page.

When reading spare pages, it will read the first block of the next sector's spare page.

Reads of the last sector will wrap around to sector 0.

Reads of Auxiliary blocks will read the next linear page's Auxiliary block.

When an address on the ADDR input does not agree with the predetermined look-ahead address,

there is a time penalty for this access. The FB will be busy finishing the current look-ahead read

before it can start the next read. The worst case is a total of nine BUSY cycles before data is

delivered.

The Non-Pipe Mode and Pipe Mode waveforms for Read Next operations are illustrated in

Figure 2-39 and Figure 2-40.

CLK

REN

READNEXT

ADDR[17:0]

DATAWIDTH[1:0]

BUSY

A0

A1

A2

A3

A4

A5

S4

A6

A7

A8

A9

STATUS[1:0]

RD[31:0]

0

S0

S1

S2

S3

0

S5

S6

S7

0

S8 S9

D8 D9

D0 D1 D2 D3

D4 D5 D6 D7

Figure 2-39 • Read Next Waveform (Non-Pipe Mode, 32-bit access)

CLK

REN

READNEXT

A0

A1

A2

A3

A4

A5

A6

A7

A8

ADDR[17:0]

BUSY

S0

S1

D1

S2

D2

S3

D3

0

S4

D4

S5

D5

S6

D6

S7

0

STATUS[1:0]

RD[31:0]

0

D0

D7

Figure 2-40 • Read Next WaveForm (Pipe Mode, 32-bit access)

2-52

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Unprotect Page Operation

An Unprotect Page operation will clear the protection for a page addressed on the ADDR input. It

is initiated by setting the UNPROTECTPAGE signal on the interface along with the page address on

ADDR.

If the page is not in the Page Buffer, the Unprotect Page operation will copy the page into the Page

Buffer. The Copy Page operation occurs only if the current page in the Page Buffer is not Page Loss

Protected.

The waveform for an Unprotect Page operation is shown in Figure 2-41.

CLK

UNPROTECTPAGE

Page

ADDR[17:0]

BUSY

STATUS[1:0]

Valid

Figure 2-41 • FB Unprotected Page Waveform

The Unprotect Page operation can incur the following error conditions:

1. If the copy of the page to the Page Buffer determines that the page has a single-bit

correctable error in the data, it will report a STATUS = '01'.

2. If the address on ADDR does not match the address of the Page Buffer, PAGELOSSPROTECT is

asserted, and the Page Buffer has been modified, then STATUS = '11' and the addressed

page is not loaded into the Page Buffer.

3. If the copy of the page to the Page Buffer determines that at least one block in the page has

a double-bit uncorrectable error, STATUS = '10' and the Page Buffer will contain the

corrupted data.

Discard Page Operation

If the contents of the modified Page Buffer have to be discarded, the DISCARDPAGE signal should

be asserted. This command results in the Page Buffer being marked as unmodified.

The timing for the operation is shown in Figure 2-42. The BUSY signal will remain asserted until the

operation has completed.

CLK

DISCARDPAGE

BUSY

Figure 2-42 • FB Discard Page Waveform

Preliminary v1.7

2-53

Device Architecture

Flash Memory Block Characteristics

CLK

RESET

Active Low, Asynchronous

BUSY

Figure 2-43 • Reset Timing Diagram

Table 2-25 • Flash Memory Block Timing

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

Description

–2

–1

Std.

10.70

6.74

6.62

5.96

Units

ns

t_CLK2RD

Clock-to-Q in 5-cycle read mode of the Read Data

Clock-to-Q in 6-cycle read mode of the Read Data

Clock-to-Q in 5-cycle read mode of BUSY

Clock-to-Q in 6-cycle read mode of BUSY

Clock-to-Status in 5-cycle read mode

7.99

5.03

4.95

4.45

9.10

5.73

5.63

5.07

t_CLK2BUSY

t_CLK2STATUS

11.24 12.81 15.06

Clock-to-Status in 6-cycle read mode

4.48

1.92

0.00

2.76

0.00

1.85

0.00

3.85

0.00

2.37

0.00

2.16

0.00

3.74

0.00

3.74

0.00

2.17

0.00

3.76

0.00

2.01

0.00

5.10

2.19

0.00

3.14

0.00

2.11

0.00

4.39

0.00

2.69

0.00

2.46

0.00

4.26

0.00

4.26

0.00

2.47

0.00

4.28

0.00

2.29

0.00

6.00

2.57

0.00

3.69

0.00

2.48

0.00

5.16

0.00

3.17

0.00

2.89

0.00

5.01

0.00

5.00

0.00

2.90

0.00

5.03

0.00

2.69

0.00

t_DSUNVM

Data Input Setup time for the Control Logic

Data Input Hold time for the Control Logic

Address Input Setup time for the Control Logic

Address Input Hold time for the Control Logic

Data Width Setup time for the Control Logic

Data Width Hold time for the Control Logic

Read Enable Setup time for the Control Logic

Read Enable Hold Time for the Control Logic

Write Enable Setup time for the Control Logic

Write Enable Hold Time for the Control Logic

Program Setup time for the Control Logic

Program Hold time for the Control Logic

SparePage Setup time for the Control Logic

SparePage Hold time for the Control Logic

Auxiliary Block Setup Time for the Control Logic

Auxiliary Block Hold Time for the Control Logic

ReadNext Setup Time for the Control Logic

ReadNext Hold Time for the Control Logic

Erase Page Setup Time for the Control Logic

Erase Page Hold Time for the Control Logic

Unprotect Page Setup Time for the Control Logic

Unprotect Page Hold Time for the Control Logic

t_DHNVM

t_ASUNVM

t_AHNVM

t_SUDWNVM

t_HDDWNVM

t_SURENNVM

t_HDRENNVM

t_SUWENNVM

t_HDWENNVM

t_SUPROGNVM

t_HDPROGNVM

t_SUSPAREPAGE

t_HDSPAREPAGE

t_SUAUXBLK

t_HDAUXBLK

t_SURDNEXT

t_HDRDNEXT

t_SUERASEPG

t_HDERASEPG

t_{SUUNPROTECTPG}

t_{HDUNPROTECTPG}

2-54

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-25 • Flash Memory Block Timing (continued)

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

Description

–2

–1

Std.

2.52

0.00

2.19

0.00

2.27

0.00

3.33

0.00

2.52

0.00

1.16

0.00

1.25

0.00

Units

ns

t_SUDISCARDPG

t_HDDISCARDPG

t_SUOVERWRPRO

t_HDOVERWRPRO

t_SUPGLOSSPRO

t_HDPGLOSSPRO

t_SUPGSTAT

Discard Page Setup Time for the Control Logic

Discard Page Hold Time for the Control Logic

Overwrite Protect Setup Time for the Control Logic

Overwrite Protect Hold Time for the Control Logic

Page Loss Protect Setup Time for the Control Logic

Page Loss Protect Hold Time for the Control Logic

Page Status Setup Time for the Control Logic

Page Status Hold Time for the Control Logic

Over Write Page Setup Time for the Control Logic

Over Write Page Hold Time for the Control Logic

Lock Request Setup Time for the Control Logic

Lock Request Hold Time for the Control Logic

Reset Recovery Time

1.88

0.00

1.64

0.00

1.69

0.00

2.49

0.00

1.88

0.00

0.87

0.00

0.94

0.00

2.14

0.00

1.86

0.00

1.93

0.00

2.83

0.00

2.14

0.00

0.99

0.00

1.07

0.00

t_HDPGSTAT

t_SUOVERWRPG

t_HDOVERWRPG

t_{SULOCKREQUEST}

t_{HDLOCKREQUEST}

t_RECARNVM

t_REMARNVM

Reset Removal Time

t_MPWARNVM

Asynchronous Reset Minimum Pulse Width for the 10.00 12.50 12.50

Control Logic

t_MPWCLKNVM

t_FMAXCLKNVM

Clock Minimum Pulse Width for the Control Logic

Maximum Frequency for Clock for the Control Logic

4.00

5.00

ns

100.00 80.00 80.00

MHz

Preliminary v1.7

2-55

Device Architecture

FlashROM

Fusion devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the FPGA

core fabric. The FlashROM is arranged in eight banks of 128 bits during programming. The 128 bits

in each bank are addressable as 16 bytes during the read-back of the FlashROM from the FPGA core

(Figure 2-44).

The FlashROM can only be programmed via the IEEE 1532 JTAG port. It cannot be programmed

directly from the FPGA core. When programming, each of the eight 128-bit banks can be selectively

reprogrammed. The FlashROM can only be reprogrammed on a bank boundary. Programming

involves an automatic, on-chip bank erase prior to reprogramming the bank. The FlashROM

supports a synchronous read and can be read on byte boundaries. The upper three bits of the

FlashROM address from the FPGA core define the bank that is being accessed. The lower four bits

of the FlashROM address from the FPGA core define which of the 16 bytes in the bank is being

accessed.

The maximum FlashROM access clock is 20 MHz. Figure 2-45 shows the timing behavior of the

FlashROM access cycle—the address has to be set up on the rising edge of the clock for DOUT to be

valid on the next falling edge of the clock.

If the address is unchanged for two cycles:

•

D0 becomes invalid 10 ns after the second rising edge of the clock.

D0 becomes valid again 10 ns after the second falling edge.

If the address unchanged for three cycles:

•

D0 becomes invalid 10 ns after the second rising edge of the clock.

D0 becomes valid again 10 ns after the second falling edge.

D0 becomes invalid 10 ns after the third rising edge of the clock.

D0 becomes valid again 10 ns after the third falling edge.

Byte Number in Bank

4 LSB of ADDR (READ)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Figure 2-44 • FlashROM Architecture

2-56

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

FlashROM Characteristics

t_SU

t_HOLD

Address

A0

A1

t_CK2Q

D0

t_CK2Q

D1

t_CK2Q

D0

Figure 2-45 • FlashROM Timing Diagram

Table 2-26 • FlashROM Access Time

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_SU

Description

Address Setup Time

Address Hold Time

Clock to Out

–2

–1

Std.

0.71

Units

0.53

0.61

ns

t_HOLD

t_CK2Q

F_MAX

0.00

21.42

15.00

24.40

15.00

28.68

15.00

ns

Maximum Clock frequency

MHz

Preliminary v1.7

2-57

Device Architecture

SRAM and FIFO

All Fusion devices have SRAM blocks along the north side of the device. Additionally, AFS600 and

AFS1500 devices have an SRAM block on the south side of the device. To meet the needs of high-

performance designs, the memory blocks operate strictly in synchronous mode for both read and

write operations. The read and write clocks are completely independent, and each may operate at

any desired frequency less than or equal to 350 MHz. The following configurations are available:

•

4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—two read, two write or one read, one write)

512×9, 256×18 (two-port RAM—one read and one write)

Sync write, sync pipelined/nonpipelined read

The Fusion SRAM memory block includes dedicated FIFO control logic to generate internal

addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY).

During RAM operation, addresses are sourced by the user logic, and the FIFO controller is ignored.

In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM

array by internal MUXes. Refer to Figure 2-46 for more information about the implementation of

the embedded FIFO controller.

The Fusion architecture enables the read and write sizes of RAMs to be organized independently,

allowing for bus conversion. This is done with the WW (write width) and RW (read width) pins. The

different D×W configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1. For example, the write size

can be set to 256×18 and the read size to 512×9.

Both the write and read widths for the RAM blocks can be specified independently with the WW

(write width) and RW (read width) pins. The different D×W configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1.

Refer to the allowable RW and WW values supported for each of the RAM macro types in

Table 2-27 on page 2-61.

When a width of one, two, or four is selected, the ninth bit is unused. For example, when writing 9-

bit values and reading 4-bit values, only the first four bits and the second four bits of each 9-bit

value are addressable for read operations. The ninth bit is not accessible.

2-58

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Conversely, when writing 4-bit values and reading 9-bit values, the ninth bit of a read operation

will be undefined. The RAM blocks employ little-endian byte order for read and write operations.

RD

RD[17:0]

WD[17:0]

RCLK

WD

RCLK

WCLK

RAM

RADD[J:0]

WADD[J:0]

REN

WEN

FREN

FWEN

CNT 12

E

RBLK

REN

=

FULL

ESTOP

AFVAL

AFULL

AEVAL

AEMPTY

EMPTY

CNT 12

E

SUB 12

WBLK

WEN

=

FSTOP

Reset

Figure 2-46 • Fusion RAM Block with Embedded FIFO Controller

Preliminary v1.7

2-59

Device Architecture

RAM4K9 Description

RAM4K9

ADDRA11 DOUTA8

DOUTA7

ADDRA10

DOUTA0

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11 DOUTB8

ADDRB10 DOUTB7

ADDRB0

DOUTB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RESET

Figure 2-47 • RAM4K9

2-60

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

The following signals are used to configure the RAM4K9 memory element:

WIDTHA and WIDTHB

These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 2-27).

Table 2-27 • Allowable Aspect Ratio Settings for WIDTHA[1:0]

WIDTHA1, WIDTHA0

WIDTHB1, WIDTHB0

D×W

4k×1

2k×2

1k×4

512×9

00

01

10

11

00

01

10

11

Note: The aspect ratio settings are constant and cannot be changed on the fly.

BLKA and BLKB

These signals are active low and will enable the respective ports when asserted. When a BLKx signal

is deasserted, the corresponding port’s outputs hold the previous value.

WENA and WENB

These signals switch the RAM between read and write mode for the respective ports. A LOW on

these signals indicates a write operation, and a HIGH indicates a read.

CLKA and CLKB

These are the clock signals for the synchronous read and write operations. These can be driven

independently or with the same driver.

PIPEA and PIPEB

These signals are used to specify pipelined read on the output. A LOW on PIPEA or PIPEB indicates

a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. A

HIGH indicates a pipelined, read and data appears on the corresponding output in the next clock

cycle.

WMODEA and WMODEB

These signals are used to configure the behavior of the output when the RAM is in write mode. A

LOW on these signals makes the output retain data from the previous read. A HIGH indicates pass-

through behavior, wherein the data being written will appear immediately on the output. This

signal is overridden when the RAM is being read.

RESET

This active low signal resets the output to zero, disables reads and writes from the SRAM block, and

clears the data hold registers when asserted. It does not reset the contents of the memory.

ADDRA and ADDRB

These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4 k

is specified, the unused high-order bits must be grounded (Table 2-28).

Table 2-28 • Address Pins Unused/Used for Various Supported Bus Widths

ADDRx

D×W

4k×1

2k×2

1k×4

512×9

Unused

None

[11]

Used

[11:0]

[10:0]

[9:0]

[11:10]

[11:9]

[8:0]

Note: The "x" in ADDRx implies A or B.

Preliminary v1.7

2-61

Device Architecture

DINA and DINB

These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all

configurations. When a data width less than nine is specified, unused high-order signals must be

grounded (Table 2-29).

DOUTA and DOUTB

These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with

DINA and DINB, high-order bits may not be used (Table 2-29). The output data on unused pins is

undefined.

Table 2-29 • Unused/Used Input and Output Data Pins for Various Supported Bus Widths

DINx/DOUTx

D×W

4k×1

2k×2

1k×4

512×9

Unused

[8:1]

Used

[0]

[8:2]

[1:0]

[3:0]

[8:0]

[8:4]

None

Note: The "x" in DINx and DOUTx implies A or B.

2-62

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

RAM512X18 Description

RAM512X18

RADDR8

RADDR7

RD17

RD16

RADDR0

RD0

RW1

RW0

PIPE

REN

RCLK

WADDR8

WADDR7

WADDR0

WD17

WD16

WD0

WW1

WW0

WEN

WCLK

RESET

Figure 2-48 • RAM512X18

Preliminary v1.7

2-63

Device Architecture

RAM512X18 exhibits slightly different behavior from RAM4K9, as it has dedicated read and write

ports.

WW and RW

These signals enable the RAM to be configured in one of the two allowable aspect ratios

(Table 2-30).

Table 2-30 • Aspect Ratio Settings for WW[1:0]

WW[1:0]

01

RW[1:0]

01

D×W

512×9

10

256×18

Reserved

00, 11

WD and RD

These are the input and output data signals, and they are 18 bits wide. When a 512×9 aspect ratio

is used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read,

then RD[17:9] are undefined.

WADDR and RADDR

These are read and write addresses, and they are nine bits wide. When the 256×18 aspect ratio is

used for write or read, WADDR[8] or RADDR[8] are unused and must be grounded.

WCLK and RCLK

These signals are the write and read clocks, respectively. They are both active high.

WEN and REN

These signals are the write and read enables, respectively. They are both active low by default.

These signals can be configured as active high.

RESET

This active low signal resets the output to zero, disables reads and/or writes from the SRAM block,

and clears the data hold registers when asserted. It does not reset the contents of the memory.

PIPE

This signal is used to specify pipelined read on the output. A LOW on PIPE indicates a nonpipelined

read, and the data appears on the output in the same clock cycle. A HIGH indicates a pipelined

read, and data appears on the output in the next clock cycle.

Clocking

The dual-port SRAM blocks are only clocked on the rising edge. SmartGen allows falling-edge-

triggered clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are

clocked on either edge (rising or falling). For dual-port SRAM, each port can be clocked on either

edge or by separate clocks, by port.

Fusion devices support inversion (bubble pushing) throughout the FPGA architecture, including the

clock input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic

or in the HDL code will be automatically accounted for during design compile without incurring

additional delay in the clock path.

The two-port SRAM can be clocked on the rising edge or falling edge of WCLK and RCLK.

If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion

management (bubble pushing) is automatically used within the Fusion development tools,

without performance penalty.

2-64

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Modes of Operation

There are two read modes and one write mode:

•

Read Nonpipelined (synchronous—1 clock edge): In the standard read mode, new data is

driven onto the RD bus in the same clock cycle following RA and REN valid. The read address

is registered on the read port clock active edge, and data appears at RD after the RAM

access time. Setting PIPE to OFF enables this mode.

Read Pipelined (synchronous—2 clock edges): The pipelined mode incurs an additional clock

delay from the address to the data but enables operation at a much higher frequency. The

read address is registered on the read port active clock edge, and the read data is registered

and appears at RD after the second read clock edge. Setting PIPE to ON enables this mode.

Write (synchronous—1 clock edge): On the write clock active edge, the write data is written

into the SRAM at the write address when WEN is HIGH. The setup times of the write address,

write enables, and write data are minimal with respect to the write clock. Write and read

transfers are described with timing requirements in the "SRAM Characteristics" section on

page 2-66 and the "FIFO Characteristics" section on page 2-77.

RAM Initialization

Each SRAM block can be individually initialized on power-up by means of the JTAG port using the

UJTAG mechanism (refer to the "JTAG IEEE 1532" section on page 2-224 and the Fusion SRAM/FIFO

Blocks application note). The shift register for a target block can be selected and loaded with the

proper bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single

operation.

Preliminary v1.7

2-65

Device Architecture

SRAM Characteristics

Timing Waveforms

t_CYC

t_CKH

t_CKL

CLK

t_ASt_AH

A₀

A₁

A₂

ADD

BLK_B

WEN_B

DO

t_BKS

t_BKH

t_ENS

t_ENH

t_CKQ1

D_n

D₀

D₁

D₂

t_DOH1

Figure 2-49 • RAM Read for Flow-Through Output

t_CYC

t_CKH

t_CKL

CLK

t_ASt_AH

A₀

A₁

A₂

ADD

BLK_B

WEN_B

DO

t_BKS

t_BKH

t_ENS

t_ENH

t_CKQ2

D_n

D₀

D₁

t_DOH2

Figure 2-50 • RAM Read for Pipelined Output

2-66

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

t_CYC

t_CKH

t_CKL

CLK

t_AS

t_AH

A₀

A₁

A₂

ADD

BLK_B

WEN_B

DI

t_BKS

t_BKH

t_ENS

t_ENH

t_DS

t_DH

DI₁

DI₀

D_n

D₂

DO

Figure 2-51 • RAM Write, Output Retained (WMODE = 0)

t_CYC

t_CKH

t_CKL

CLK

ADD

t_ASt_AH

A₀

A₁

A₂

t_BKS

t_BKH

BLK_B

WEN_B

DI

t_ENS

t_DS

t_DH

DI₁

D₀

DI₂

DO

DI₀

D_n

DI₁

(flow-through)

DO

DI₀

D_n

DI₁

(Pipelined)

Figure 2-52 • RAM Write, Output as Write Data (WMODE = 1)

Preliminary v1.7

2-67

Device Architecture

CLK1

ADD1

DI1

t_ASt_AH

A₀

A₂

D₂

A₃

D₃

t_DSt_DH

D₀

t_WRO

CLK2

t_ASt_AH

A₁

A₀

A₄

ADD2

DO2

t_CKQ1

D_n

D₀

D₁

(flow-through)

t_CKQ2

DO2

(Pipelined)

D_n

D₀

Figure 2-53 • One Port Write / Other Port Read Same

CLK1

t_AS

t_AH

A₀

A₃

D₃

ADD1

DI1

A₁

D₂

t_DS

t_DH

D₁

t_CCKH

CLK2

WEN_B1

WEN_B2

t_AS

t_AH

A₀

A₄

A₀

D₀

ADD2

DI2

D₄

t_CKQ1

DO2

(pass-through)

D₀

D_n

t_CKQ2

DO2

(pipelined)

D₀

D_n

Figure 2-54 • Write Access After Write onto Same Address

2-68

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

CLK1

ADD1

t_AS

t_AH

A₀

A₃

D₃

A₂

D₂

t_DS

t_DH

DI1

D₀

t_WRO

CLK2

WEN_B1

WEN_B2

ADD2

t_AS

t_AH

A₁

A₄

A₀

t_CKQ1

DO2

(pass-through)

D_n

D₀

D₁

D₀

t_CKQ2

DO2

(pipelined)

D_n

Figure 2-55 • Read Access After Write onto Same Address

Preliminary v1.7

2-69

Device Architecture

CLK1

t_AS

t_AH

A₀

ADD1

WEN_B1

DO1

A₁

t_CKQ1

D_n

D₁

D₀

t_CKQ2

(pass-through)

DO1

(pipelined)

D₀

D_n

t_CCKH

CLK2

t_AS

t_AH

A₁

A₀

D₁

A₃

D₃

ADD2

DI2

D₂

WEN_B2

Figure 2-56 • Write Access After Read onto Same Address

t_CYC

t_CKH

t_CKL

CLK

RESET_B

DO

t_RSTBQ

D_m

D_n

Figure 2-57 • RAM Reset

2-70

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Timing Characteristics

Table 2-31 • RAM4K9

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_AS

Description

–2

–1

Std. Units

Address Setup time

0.25

0.00

0.14

0.10

0.23

0.02

0.18

0.00

1.79

2.36

0.89

0.28 0.33

0.00 0.00

0.16 0.19

0.11 0.13

0.27 0.31

0.02 0.02

0.21 0.25

0.00 0.00

2.03 2.39

2.68 3.15

1.02 1.20

ns

t_AH

Address Hold time

t_ENS

REN_B,WEN_B Setup time

t_ENH

t_BKS

t_BKH

t_DS

REN_B, WEN_B Hold time

BLK_B Setup time

BLK_B Hold time

Input data (DI) Setup time

t_DH

Input data (DI) Hold time

t_CKQ1

Clock High to New Data Valid on DO (output retained, WMODE = 0)

Clock High to New Data Valid on DO (flow-through, WMODE = 1)

Clock High to New Data Valid on DO (pipelined)

t_CKQ2

t_WRO

Address collision clk-to-clk delay for reliable read access after write TBD

on same address

TBD

t_CCKH

Address collision clk-to-clk delay for reliable write access after TBD

write/read on same address

TBD

ns

t_RSTBQ

RESET_B Low to Data Out Low on DO (flow-through)

RESET_B Low to Data Out Low on DO (pipelined)

RESET_B Removal

0.92

0.29

1.50

0.21

3.23

310

1.05 1.23

0.33 0.38

1.71 2.01

0.24 0.29

3.68 4.32

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle time

F_MAX

Maximum Clock Frequency

272

231 MHz

Note: For the derating values at specific junction temperature and voltage-supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-71

Device Architecture

Table 2-32 • RAM512X18

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_AS

Description

–2

–1

Std. Units

Address Setup time

0.25

0.00

0.09

0.06

0.18

0.00

0.28 0.33

0.00 0.00

0.10 0.12

0.07 0.08

0.21 0.25

0.00 0.00

2.46 2.89

1.02 1.20

TBD TBD

ns

t_AH

Address Hold time

t_ENS

REN_B,WEN_B Setup time

REN_B, WEN_B Hold time

Input data (DI) Setup time

Input data (DI) Hold time

t_ENH

t_DS

t_DH

t_CKQ1

t_CKQ2

t_WRO

Clock High to New Data Valid on DO (output retained, WMODE = 0) 2.16

Clock High to New Data Valid on DO (pipelined) 0.90

Address collision clk-to-clk delay for reliable read access after write TBD

on same address

t_CCKH

Address collision clk-to-clk delay for reliable write access after TBD

write/read on same address

TBD TBD

ns

t_RSTBQ

RESET_B Low to Data Out Low on DO (flow-through)

RESET_B Low to Data Out Low on DO (pipelined)

RESET_B Removal

0.92

0.29

1.50

0.21

3.23

310

1.05 1.23

0.33 0.38

1.71 2.01

0.24 0.29

3.68 4.32

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle time

F_MAX

Maximum Clock Frequency

272

231 MHz

Note: For the derating values at specific junction temperature and voltage-supply levels, refer to Table 3-7 on

page 3-9.

2-72

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

FIFO4K18 Description

FIFO4K18

RD17

RD16

RW2

RW1

RW0

WW2

WW1

WW0

RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AEMPTY

AEVAL11

AEVAL10

AEVAL0

AFVAL11

AFVAL10

AFVAL0

REN

RBLK

RCLK

WD17

WD16

WD0

WEN

WBLK

WCLK

RPIPE

RESET

Figure 2-58 • FIFO4KX18

Preliminary v1.7

2-73

Device Architecture

The following signals are used to configure the FIFO4K18 memory element:

WW and RW

These signals enable the FIFO to be configured in one of the five allowable aspect ratios

(Table 2-33).

Table 2-33 • Aspect Ratio Settings for WW[2:0]

WW2, WW1, WW0

RW2, RW1, RW0

D×W

4k×1

000

001

2k×2

010

1k×4

011

512×9

256×18

Reserved

100

101, 110, 111

WBLK and RBLK

These signals are active low and will enable the respective ports when LOW. When the RBLK signal

is HIGH, the corresponding port’s outputs hold the previous value.

WEN and REN

Read and write enables. WEN is active low and REN is active high by default. These signals can be

configured as active high or low.

WCLK and RCLK

These are the clock signals for the synchronous read and write operations. These can be driven

independently or with the same driver.

RPIPE

This signal is used to specify pipelined read on the output. A LOW on RPIPE indicates a

nonpipelined read, and the data appears on the output in the same clock cycle. A HIGH indicates a

pipelined read, and data appears on the output in the next clock cycle.

RESET

This active low signal resets the output to zero when asserted. It resets the FIFO counters. It also

sets all the RD pins LOW, the FULL and AFULL pins LOW, and the EMPTY and AEMPTY pins HIGH

(Table 2-34).

Table 2-34 • Input Data Signal Usage for Different Aspect Ratios

D×W

WD/RD Unused

WD[17:1], RD[17:1]

WD[17:2], RD[17:2]

WD[17:4], RD[17:4]

WD[17:9], RD[17:9]

–

4k×1

2k×2

1k×4

512×9

256×18

WD

This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a

data width less than 18 is specified, unused higher-order signals must be grounded (Table 2-34).

RD

This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the

WD bus, high-order bits become unusable if the data width is less than 18. The output data on

unused pins is undefined (Table 2-34).

2-74

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

ESTOP, FSTOP

ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the

EMPTY flag goes HIGH). A HIGH on this signal inhibits the counting.

FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the

FULL flag goes HIGH). A HIGH on this signal inhibits the counting.

For more information on these signals, refer to the "ESTOP and FSTOP Usage" section on

page 2-76.

FULL, EMPTY

When the FIFO is full and no more data can be written, the FULL flag asserts HIGH. The FULL flag is

synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to

prevent overflows. Since the write address is compared to a resynchronized (and thus time-

delayed) version of the read address, the FULL flag will remain asserted until two WCLK active

edges after a read operation eliminates the full condition.

When the FIFO is empty and no more data can be read, the EMPTY flag asserts HIGH. The EMPTY

flag is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition

and to prevent underflows. Since the read address is compared to a resynchronized (and thus time-

delayed) version of the write address, the EMPTY flag will remain asserted until two RCLK active

edges after a write operation removes the empty condition.

For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on

page 2-76.

AFULL, AEMPTY

These are programmable flags and will be asserted on the threshold specified by AFVAL and

AEVAL, respectively.

When the number of words stored in the FIFO reaches the amount specified by AEVAL while

reading, the AEMPTY output will go HIGH. Likewise, when the number of words stored in the FIFO

reaches the amount specified by AFVAL while writing, the AFULL output will go HIGH.

Preliminary v1.7

2-75

Device Architecture

AFVAL, AEVAL

The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold

values, respectively. They are 12-bit signals. For more information on these signals, refer to

"FIFO Flag Usage Considerations" section.

ESTOP and FSTOP Usage

The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty

(i.e., the EMPTY flag goes HIGH). Likewise, the FSTOP pin is used to stop the write counter from

counting any further once the FIFO is full (i.e., the FULL flag goes HIGH).

The FIFO counters in the Fusion device start the count at 0, reach the maximum depth for the

configuration (e.g., 511 for a 512×9 configuration), and then restart at 0. An example application

for the ESTOP, where the read counter keeps counting, would be writing to the FIFO once and

reading the same content over and over without doing another write.

FIFO Flag Usage Considerations

The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values,

respectively. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR)

counters. WADDR is incremented every time a write operation is performed, and RADDR is

incremented every time a read operation is performed. Whenever the difference between WADDR

and RADDR is greater than or equal to AFVAL, the AFULL output is asserted. Likewise, whenever

the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is

asserted. To handle different read and write aspect ratios, AFVAL and AEVAL are expressed in terms

of total data bits instead of total data words. When users specify AFVAL and AEVAL in terms of

read or write words, the SmartGen tool translates them into bit addresses and configures these

signals automatically. SmartGen configures the AFULL flag to assert when the write address

exceeds the read address by at least a predefined value. In a 2k×8 FIFO, for example, a value of

1,500 for AFVAL means that the AFULL flag will be asserted after a write when the difference

between the write address and the read address reaches 1,500 (there have been at least 1500 more

writes than reads). It will stay asserted until the difference between the write and read addresses

drops below 1,500.

The AEMPTY flag is asserted when the difference between the write address and the read address

is less than a predefined value. In the example above, a value of 200 for AEVAL means that the

AEMPTY flag will be asserted when a read causes the difference between the write address and the

read address to drop to 200. It will stay asserted until that difference rises above 200. Note that the

FIFO can be configured with different read and write widths; in this case, the AFVAL setting is

based on the number of write data entries and the AEVAL setting is based on the number of read

data entries. For aspect ratios of 512×9 and 256×18, only 4,096 bits can be addressed by the 12 bits

of AFVAL and AEVAL. The number of words must be multiplied by 8 and 16, instead of 9 and 18.

The SmartGen tool automatically uses the proper values. To avoid halfwords being written or read,

which could happen if different read and write aspect ratios are specified, the FIFO will assert FULL

or EMPTY as soon as at least a minimum of one word cannot be written or read. For example, if a

two-bit word is written and a four-bit word is being read, the FIFO will remain in the empty state

when the first word is written. This occurs even if the FIFO is not completely empty, because in this

case, a complete word cannot be read. The same is applicable in the full state. If a four-bit word is

written and a two-bit word is read, the FIFO is full and one word is read. The FULL flag will remain

asserted because a complete word cannot be written at this point.

2-76

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

FIFO Characteristics

Timing Waveforms

RCLK/

WCLK

t_MPWRSTB

t_RSTCK

RESET_B

t_RSTFG

EF

AEF

FF

t_RSTAF

t_RSTFG

t_RSTAF

AFF

WA/RA

(Address Counter)

MATCH (A₀)

Figure 2-59 • FIFO Reset

t_CYC

RCLK

EF

t_RCKEF

t_CKAF

AEF

WA/RA

(Address Counter)

NO MATCH

Dist = AEF_TH

MATCH (EMPTY)

Figure 2-60 • FIFO EMPTY Flag and AEMPTY Flag Assertion

Preliminary v1.7

2-77

Device Architecture

t_CYC

WCLK

t_WCKFF

FF

t_CKAF

AFF

WA/RA

NO MATCH

Dist = AFF_TH

MATCH (FULL)

(Address Counter)

Figure 2-61 • FIFO FULL and AFULL Flag Assertion

WCLK

MATCH

(EMPTY)

WA/RA

NO MATCH

Dist = AEF_TH + 1

(Address Counter)

1st rising

2nd rising

edge

after 1st

write

edge

after 1st

write

RCLK

EF

t

RCKEF

t

CKAF

AEF

Figure 2-62 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

RCLK

WA/RA

(Address Counter) MATCH (FULL)

NO MATCH

Dist = AFF_TH - 1

1st Rising

Edge

After 1st

Read

Edge

After 2nd

Read

WCLK

FF

t_WCKF

t_CKAF

AFF

Figure 2-63 • FIFO FULL Flag and AFULL Flag Deassertion

2-78

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Timing Characteristics

Table 2-35 • FIFO

Worst Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

Parameter

t_ENS

Description

–2

–1

Std.

1.79

0.00

0.26

0.00

0.25

0.00

2.90

1.26

2.30

2.18

8.29

2.27

8.20

1.23

0.38

2.01

0.29

4.32

231

Units

ns

REN_B, WEN_B Setup time

1.34

0.00

0.19

0.00

0.18

0.00

2.17

0.94

1.72

1.63

6.19

1.69

6.13

0.92

0.29

1.50

0.21

3.23

310

1.52

0.00

0.22

0.00

0.21

0.00

2.47

1.07

1.96

1.86

7.05

1.93

6.98

1.05

0.33

1.71

0.24

3.68

272

t_ENH

REN_B, WEN_B Hold time

t_BKS

BLK_B Setup time

t_BKH

BLK_B Hold time

t_DS

Input data (DI) Setup time

t_DH

Input data (DI) Hold time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on DO (flow-through)

Clock High to New Data Valid on DO (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

Clock High to Almost Empty/Full Flag Valid

RESET_B Low to Empty/Full Flag Valid

RESET_B Low to Almost-Empty/Full Flag Valid

RESET_B Low to Data out Low on DO (flow-through)

RESET_B Low to Data out Low on DO (pipelined)

RESET_B Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET_B Recovery

RESET_B Minimum Pulse Width

Clock Cycle time

F_MAX

Maximum Frequency for FIFO

Note: For specific junction temperature and voltage-supply levels, refer to Table 3-7 on page 3-9 for derating

values.

Preliminary v1.7

2-79

Device Architecture

Analog Block

With the Fusion family, Actel has introduced the world's first mixed-mode FPGA solution.

Supporting a robust analog peripheral mix, Fusion devices will support a wide variety of

applications. It is this Analog Block that separates Fusion from all other FPGA solutions on the

market today.

By combining both flash and high-speed CMOS processes in a single chip, these devices offer the

best of both worlds. The high-performance CMOS is used for building RAM resources. These high-

performance structures support device operation up to 350 MHz. Additionally, the advanced Actel

0.13 µm flash process incorporates high-voltage transistors and a high-isolation, triple-well process.

Both of these are suited for the flash-based programmable logic and nonvolatile memory

structures.

High-voltage transistors support the integration of analog technology in several ways. They aid in

noise immunity so that the analog portions of the chip can be better isolated from the digital

portions, increasing analog accuracy. Because they support high voltages, Actel flash FPGAs can be

connected directly to high-voltage input signals, eliminating the need for external resistor divider

networks, reducing component count, and increasing accuracy. By supporting higher internal

voltages, the Actel advanced flash process enables high dynamic range on analog circuitry,

increasing precision and signal–noise ratio. Actel flash FPGAs also drive high-voltage outputs,

eliminating the need for external level shifters and drivers.

The unique triple-well process enables the integration of high-performance analog features with

increased noise immunity and better isolation. By increasing the efficiency of analog design, the

triple-well process also enables a smaller overall design size, reducing die size and cost.

The Analog Block consists of the Analog Quad I/O structure, RTC (for details refer to the "Real-Time

Counter System" section on page 2-34), ADC, and ACM. All of these elements are combined in the

single Analog Block macro, with which the user implements this functionality (Figure 2-64).

The Analog Block needs to be reset/reinitialized after the core powers up or the device is

programmed. An external reset/initialize signal, which can come from the internal voltage

regulator when it powers up, must be applied.

2-80

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

VAREF

GNDREF

AV0

AC0

AT0

DAVOUT0

DACOUT0

DATOUT0

AV9

AC9

AT9

DAVOUT9

DACOUT9

DATOUT9

ATRETURN01

AG0

AG1

ATRETURN9

DENAV0

DENAC0

DENAT0

AG9

DENAV0

DENAC0

DENAT0

CMSTB0

CSMTB9

GDON0

GDON9

TMSTB0

TMSTB9

MODE[3:0]

TVC[7:0]

STC[7:0]

BUSY

CALIBRATE

DATAVALID

SAMPLE

CHNUMBER[4:0]

TMSTINT

RESULT[11:0]

RTCMATCH

RTCXTLMODE

RTCXTLSEL

ADCSTART

VAREFSEL

PWRDWN

ADCRESET

RTCPSMMATCH

RTCCLK

SYSCLK

ACMWEN

ACMRESET

ACMWDATA

ACMADDR

ACMCLK

ACMRDATA[7:0]

AB

Figure 2-64 • Analog Block Macro

Preliminary v1.7

2-81

Device Architecture

Table 2-36 describes each pin in the Analog Block. Each function within the Analog Block will be

explained in detail in the following sections.

Table 2-36 • Analog Block Pin Description

Number

of Bits

Location of

Details

Signal Name

VAREF

Direction

Function

1

4

1

8

1

Input/Output Voltage reference for ADC

ADC

GNDREF

Input

External ground reference

ADC operating mode

External system clock

Clock divide control

MODE[3:0]

SYSCLK

TVC[7:0]

ADC

STC[7:0]

Sample time control

ADCSTART

PWRDWN

ADCRESET

Start of conversion

Comparator power-down if 1

ADC resets and disables Analog

Quad – active high

BUSY

1

Output

Input

1 – Running conversion

1 – Power-up calibration

1 – Valid conversion result

Conversion result

ADC

CALIBRATE

DATAVALID

RESULT[11:0]

TMSTBINT

SAMPLE

1

12

1

Internal temp. monitor strobe

1

Output

1 – An analog signal is actively being

sampled (stays high during signal

acquisition only)

0

– No analog signal is being

sampled

VAREFSEL

1

5

Input

0 = Output

reference (2.56 V) to VAREF

internal

voltage

ADC

1 = Input external voltage reference

from VAREF and GNDREF

CHNUMBER[4:0]

Analog input channel select

Input

multiplexer

ACMCLK

1

Input

Output

Input

ACM clock

ACM

ACMWEN

ACM write enable – active high

ACM reset – active low

ACM write data

ACMRESET

1

ACMWDATA[7:0]

ACMRDATA[7:0]

ACMADDR[7:0]

CMSTB0 to CMSTB9

8

ACM read data

8

ACM address

10

Current monitor strobe – 1 per quad, Analog Quad

active high

GDON0 to GDON9

TMSTB0 to TMSTB9

10

Input

Control to power MOS – 1 per quad Analog Quad

Temperature monitor strobe – 1 per Analog Quad

quad; active high

2-82

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-36 • Analog Block Pin Description (continued)

Number

of Bits

Location of

Details

Signal Name

Direction

Function

DAVOUT0, DACOUT0, DATOUT0

to

30

Output

Digital outputs – 3 per quad

Analog Quad

DAVOUT9, DACOUT9, DATOUT9

DENAV0, DENAC0, DENAT0 to

DENAV9, DENAC9, DENAT9

30

Input

Digital input enables – 3 per quad

Analog Quad 0

Analog Quad

AV0

1

Input

Analog Quad

AC0

AG0

Output

Input

AT0

ATRETURN01

Input

Temperature monitor return shared Analog Quad

by Analog Quads 0 and 1

AV1

1

Input

Analog Quad 1

Analog Quad

AC1

AG1

Output

Input

AT1

AV2

Input

Analog Quad 2

AC2

AG2

Output

Input

AT2

ATRETURN23

Input

Temperature monitor return shared Analog Quad

by Analog Quads 2 and 3

AV3

1

Input

Analog Quad 3

Analog Quad

AC3

AG3

Output

Input

AT3

AV4

Input

Analog Quad 4

AC4

AG4

Output

Input

AT4

ATRETURN45

Input

Temperature monitor return shared Analog Quad

by Analog Quads 4 and 5

AV5

AC5

AG5

AT5

AV6

AC6

AG6

AT6

1

Input

Analog Quad 5

Analog Quad

Output

Input

Analog Quad 6

Input

Output

Input

Preliminary v1.7

2-83

Device Architecture

Table 2-36 • Analog Block Pin Description (continued)

Number

of Bits

Location of

Details

Signal Name

Direction

Function

ATRETURN67

1

Input

Temperature monitor return shared Analog Quad

by Analog Quads 6 and 7

AV7

1

Input

Analog Quad 7

Analog Quad

AC7

AG7

Output

Input

AT7

AV8

Analog Quad 8

AC8

AG8

Output

Input

AT8

ATRETURN89

Temperature monitor return shared Analog Quad

by Analog Quads 8 and 9

AV9

1

2

1

Input

Analog Quad 9

Analog Quad

RTC

AC9

AG9

Output

Input

AT9

RTCMATCH

RTCPSMMATCH

RTCXTLMODE[1:0]

RTCXTLSEL

RTCCLK

Output

Input

MATCH

MATCH connected to VRPSM

Drives XTLOSC RTCMODE[1:0] pins

Drives XTLOSC MODESEL pin

RTC clock input

RTC

Analog Quad

With the Fusion family, Actel introduces the Analog Quad, shown in Figure 2-65 on page 2-85, as

the basic analog I/O structure. The Analog Quad is a four-channel system used to precondition a set

of analog signals before sending it to the ADC for conversion into a digital signal. To maximize the

usefulness of the Analog Quad, the analog input signals can also be configured as LVTTL digital

input signals. The Analog Quad is divided into four sections.

The first section is called the Voltage Monitor Block, and its input pin is named AV. It contains a

two-channel analog multiplexer that allows an incoming analog signal to be routed directly to the

ADC or allows the signal to be routed to a prescaler circuit before being sent to the ADC. The

prescaler can be configured to accept analog signals between –12 V and 0 or between 0 and +12 V.

The prescaler circuit scales the voltage applied to the ADC input pad such that it is compatible with

the ADC input voltage range. The AV pin can also be used as a digital input pin.

The second section of the Analog Quad is called the Current Monitor Block. Its input pin is named

AC. The Current Monitor Block contains all the same functions as the Voltage Monitor Block with

one addition, which is a current monitoring function. A small external current sensing resistor

(typically less than 1 Ω) is connected between the AV and AC pins and is in series with a power

source. The Current Monitor Block contains a current monitor circuit that converts the current

through the external resistor to a voltage that can then be read using the ADC.

The third part of the Analog Quad is called the Gate Driver Block, and its output pin is named AG.

This section is used to drive an external FET. There are two modes available: a High Current Drive

mode and a Current Source Control mode. Both negative and positive voltage polarities are

available, and in the current source control mode, four different current levels are available.

2-84

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

The fourth section of the Analog Quad is called the Temperature Monitor Block, and its input pin

name is AT. This block is similar to the Voltage Monitor Block, except that it has an additional

function: it can be used to monitor the temperature of an external diode-connected transistor. It

has a modified prescaler and is limited to positive voltages only.

The Analog Quad can be configured during design time by Actel Libero IDE; however, the ACM can

be used to change the parameters of any of these I/Os during runtime. This type of change is

referred to as a context switch. The Analog Quad is a modular structure that is replicated to

generate the analog I/O resources. Each Fusion device supports between 5 and 10 Analog Quads.

The analog pads are numbered to clearly identify both the type of pad (voltage, current, gate

driver, or temperature pad) and its corresponding Analog Quad (AV0, AC0, AG0, AT0, AV1, …, AC9,

AG9, and AT9). There are three types of input pads (AVx, ACx, and ATx) and one type of analog

output pad (AGx). Since there can be up to 10 Analog Quads on a device, there can be a maximum

of 30 analog input pads and 10 analog output pads.

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor/Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-65 • Analog Quad

Preliminary v1.7

2-85

Device Architecture

Voltage Monitor

The Fusion Analog Quad offers a robust set of voltage-monitoring capabilities unique in the FPGA

industry. The Analog Quad comprises three analog input pads— Analog Voltage (AV), Analog

Current (AC), and Analog Temperature (AT)—and a single gate driver output pad, Analog Gate

(AG). There are many common characteristics among the analog input pads. Each analog input can

be configured to connect directly to the input MUX of the ADC. When configured in this manner

(Figure 2-66), there will be no prescaling of the input signal. Care must be taken in this mode not

to drive the ADC into saturation by applying an input voltage greater than the reference voltage.

The internal reference voltage of the ADC is 2.56 V. Optionally, an external reference can be

supplied by the user. The external reference can be a maximum of 3.3 V DC.

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-66 • Analog Quad Direct Connect

2-86

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

The Analog Quad offers a wide variety of prescaling options to enable the ADC to resolve the input

signals. Figure 2-67 shows the path through the Analog Quad for a signal that is to be prescaled

prior to conversion. The ADC internal reference voltage and the prescaler factors were selected to

make both prescaling and postscaling of the signals easy binary calculations (refer to Table 2-54 on

page 2-128 for details). When an analog input pad is configured with a prescaler, there will be a

1 MΩ resistor to ground. This occurs even when the device is in power-down mode. In low power

standby or sleep mode (V_CCis OFF, V_CC33Ais ON, V_CCIis ON) or when the resource is not used,

analog inputs are pulled down to ground through a 1 MΩ resistor. The gate driver output is

floating (or tristated), and there is no extra current on V_CC33A

.

These scaling factors hold true whether the particular pad is configured to accept a positive or

negative voltage. Note that whereas the AV and AC pads support the same prescaling factors, the

AT pad supports a reduced set of prescaling factors and supports positive voltages only.

Typical scaling factors are given in Table 2-54 on page 2-128, and the gain error (which contributes

to the minimum and maximum) is in Table 2-46 on page 2-115.

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-67 • Analog Quad Prescaler Input Configuration

Preliminary v1.7

2-87

Device Architecture

Terminology

BW – Bandwidth

BW is a range of frequencies that a Channel can handle.

Channel

A channel is define as an analog input configured as one of the Prescaler range shown in

Table 2-54 on page 2-128. The channel includes the Prescaler circuit and the ADC.

Channel Gain

Channel Gain is a measured of the deviation of the actual slope from the ideal slope. The slope is

measured from the 20% and 80% point.

Gain_actual

Gain = -----------------------

Gain_ideal

EQ 2-1

Channel Gain Error

Channel Gain Error is a deviation from the ideal slope of the transfer function. The Prescaler Gain

Error is expressed as the percent difference between the actual and ideal, as shown in EQ 2-2.

Error_Gain= (1-Gain) × 100%

EQ 2-2

Channel Input Offset Error

Channel Offset error is measured as the input voltage that causes the transition from zero to a

count of one. An Ideal Prescaler will have offset equal to ½ of LSB voltage. Offset error is a positive

or negative when the first transition point is higher or lower than ideal. Offset error is expressed in

LSB or input voltage.

Total Channel Error

Total Channel Error is defined as the total error measured compared to the ideal value. Total

Channel Error is the sum of gain error and offset error combined. Figure 2-68 shows how Total

Channel Error is measured.

Total Channel Error is defined as the difference between the actual ADC output and ideal ADC

output. In the example shown in Figure 2-68, the Total Channel Error would be a negative number.

Channel Gain

Actual Output

Ideal Output

Total Channel Error

Channel Input

Offset Error

Input Voltage to Prescaler

Figure 2-68 • Total Channel Error Example

2-88

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Direct Digital Input

The AV, AC, and AT pads can also be configured as high-voltage digital inputs (Figure 2-69). As

these pads are 12 V–tolerant, the digital input can also be up to 12 V. However, the frequency at

which these pads can operate is limited to 10 MHz.

To enable one of these analog input pads to operate as a digital input, its corresponding Digital

Input Enable (DENAxy) pin on the Analog Block must be pulled HIGH, where x is either V, C, or T

(for AV, AC, or AT pads, respectively) and y is in the range 0 to 9, corresponding to the appropriate

Analog Quad.

When the pad is configured as a digital input, the signal will come out of the Analog Block macro

on the appropriate DAxOUTy pin, where x represents the pad type (V for AV pad, C for AC pad, or

T for AT pad) and y represents the appropriate Analog Quad number. Example: If the AT pad in

Analog Quad 5 is configured as a digital input, it will come out on the DATOUT5 pin of the Analog

Block macro.

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-69 • Analog Quad Direct Digital Input Configuration

Preliminary v1.7

2-89

Device Architecture

Current Monitor

The Fusion Analog Quad is an excellent element for voltage- and current-monitoring applications.

In addition to supporting the same functionality offered by the AV pad, the AC pad can be

configured to monitor current across an external sense resistor (Figure 2-70). To support this

current monitor function, a differential amplifier with 10x gain passes the amplified voltage drop

between the AV and AC pads to the ADC. The amplifier enables the user to use very small resistor

values, thereby limiting any impact on the circuit. This function of the AC pad does not limit AV

pad operation. The AV pad can still be configured for use as a direct voltage input or scaled

through the AV prescaler independently of it’s use as an input to the AC pad’s differential

amplifier.

Power

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-70 • Analog Quad Current Monitor Configuration

2-90

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

To initiate a current measurement, the appropriate Current Monitor Strobe (CMSTB) signal on the

AB macro must be asserted low for at least t_CMSLOin order to discharge the previous measurement.

Then CMSTB must be asserted high for at least t_CMSETprior to asserting the ADCSTART signal. The

CMSTB must remain high until after the SAMPLE signal is de-asserted by the AB macro. Note that

the minimum sample time cannot be less than t_CMSHI. Figure 2-71 shows the timing diagram of

CMSTB in relationship with the ADC control signals.

t_CMSHI

CMSTBx

t

CMSLO

CMSET

V

ADCSTART can be asserted

ADC

after this point to start ADC

sampling.

ADCSTART

Figure 2-71 • Timing Diagram for Current Monitor Strobe

Figure 2-72 illustrates positive current monitor operation. The differential voltage between AV and

AC goes into the 10× amplifier and is then converted by the ADC. For example, a current of 1.5 A is

drawn from a 10 V supply and is measured by the voltage drop across a 0.050 Ω sense resistor, The

voltage drop is amplified by ten times by the amplifier and then measured by the ADC. The 1.5 A

current creates a differential voltage across the sense resistor of 75 mV. This becomes 750 mV after

amplification. Thus, the ADC measures a current of 1.5 A as 750 mV. Using an ADC with 8-bit

resolution and VAREF of 2.56 V, the ADC result is decimal 75. EQ 2-3 shows how to compute the

current from the ADC result.

I = (ADC × V_AREF) ⁄ (10 × 2^N× R_sense

)

EQ 2-3

where

I is the current flowing through the sense resistor

ADC is the result from the ADC

VAREF is the Reference voltage

N is the number of bits

Rsense is the resistance of the sense resistor

Preliminary v1.7

2-91

Device Architecture

I

R

0-12 V

SENSE

AVx

ACx

CMSTBx

to Analog MUX

(refer Table 2-36

for MUX channel

number)

V

ADC

10 X

Current Monitor

Figure 2-72 • Positive Current Monitor

Care must be taken when choosing the right resistor for current measurement application. Note

that because of the 10× amplification, the maximum measurable difference between the AV and

AC pads is V_AREF/ 10. A larger AV-to-AC voltage drop will result in ADC saturation; that is, the

digital code put out by the ADC will stay fixed at the full scale value. Therefore, the user must

select the external sense resistor appropriately. Table 2-37 shows recommended resistor values for

different current measurement ranges. When choosing resistor values for a system, there is a trade-

off between measurement accuracy and power consumption. Choosing a large resistor will increase

the voltage drop and hence increase accuracy of the measurement; however the larger voltage

drop dissipates more power (P = I²× R).

The Current Monitor is a unipolar system, meaning that the differential voltage swing must be

from 0 V to V_AREF/10. Therefore, the Current Monitor only supports differential voltage where

|V_AV-V_AC| is greater than 0 V. This results in the requirement that the potential of the AV pad must

be larger than the potential of the AC pad. This is straightforward for positive voltage systems. For

a negative voltage system, it means that the AV pad must be "more negative" than the AC pad.

This is shown in Figure 2-73.

In this case, both the AV pad and the AC pad are configured for negative operations and the

output of the differential amplifier still falls between 0 V and V_AREFas required.

2-92

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-37 • Recommended Resistor for Different Current Range Measurement

Current Range

> 5 mA – 10 mA

> 10 mA – 20 mA

> 20 mA – 50 mA

> 50 mA – 100 mA

> 100 mA – 200 mA

> 200 mA – 500 mA

> 500 mA – 1 A

> 1 A – 2 A

Recommended Minimum Resistor Value (Ohms)

10 – 20

5 – 10

2.5 – 5

1 – 2

0.5 – 1

0.3 – 0.5

0.1 – 0.2

0.05 – 0.1

0.025 – 0.05

0.0125 – 0.025

0.00625 – 0.02

> 2 A – 4 A

> 4 A – 8 A

> 8 A – 12 A

I

R_SENSE

0 to

–10.5 V

AVx

ACx

CMSTBx

to Analog MUX

V_ADC

10 X

(refer Table 2-36

for MUX channel

number)

Current Monitor

Figure 2-73 • Negative Current Monitor

Terminology

Accuracy

The accuracy of Fusion Current Monitor is 2 mV minimum plus 5% of the differential voltage at

the input. The input accuracy can be translated to error at the ADC output by using EQ 2-4. The

10 V/V gain is the gain of the Current Monitor Circuit, as described in the "Current Monitor"

section on page 2-90. For 8-bit mode, N = 8, V_AREF= 2.56 V, zero differential voltage between AV

and AC, the Error (E_ADC) is equal to 2 LSBs.

2^N

V_AREF

--------------

E_ADC= (2mV + 0.05 V_AV– V_AC) × (10V) ⁄ V ×

EQ 2-4

where

N is the number of bits

V_AREFis the Reference voltage

V_AVis the voltage at AV pad

V_ACis the voltage at AC pad

Preliminary v1.7

2-93

Device Architecture

Gate Driver

The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin (Figure 2-74).

Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current

sink or source and requires an external pull-up or pull-down resistor. The AG supports 4 selectable

gate drive levels: 1 µA, 3 µA, 10 µA, and 30 µA (Figure 2-75 on page 2-95). The AG also supports a

High Current Drive mode in which it can sink 20 mA; in this mode the switching rate is

approximately 1.3 MHz with 100 ns turn-on time and 600 ns turn-off time. Modeled on an open-

drain-style output, it does not output a voltage level without an appropriate pull-up or pull-down

resistor. If 1 V is forced on the drain, the current sinking/sourcing will exceed the ability of the

transistor, and the device could be damaged.

The AG pad is turned on via the corresponding GDONx pin in the Analog Block macro, where x is

the number of the corresponding Analog Quad for the AG pad to be enabled (GDON0 to GDON9).

Power

Line Side

Load Side

Off-Chip

R_pullup

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-74 • Gate Driver

The gate-to-source voltage (V_gs) of the external MOSFET is limited to the programmable drive

current times the external pull-up or pull-down resistor value (EQ 2-5).

V_gs≤ I_g× (R_pullupor R_pulldown

)

EQ 2-5

The rate at which the gate voltage of the external MOSFET slews is determined by the current, I_g,

sourced or sunk by the AG pin and the gate-to-source capacitance, C_GS, of the external MOSFET. As

an approximation, the slew rate is given by EQ 2-6.

dv/dt = I_g/ C_GS

EQ 2-6

2-94

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

C_GSis not a fixed capacitance but, depending on the circuitry connected to its drain terminal, can

vary significantly during the course of a turn-on or turn-off transient. Thus, EQ 2-6 on page 2-94

can only be used for a first-order estimate of the switching speed of the external MOSFET.

1 µA

3 µA

10 µA

30 µA

AG

High

Current

1 µA

3 µA

10 µA

30 µA

Figure 2-75 • Gate Driver Example

Preliminary v1.7

2-95

Device Architecture

Temperature Monitor

The final pin in the Analog Quad is the Analog Temperature (AT) pin. The AT pin is used to

implement an accurate temperature monitor in conjunction with an external diode-connected

bipolar transistor (Figure 2-76). For improved temperature measurement accuracy, it is important

to use the ATRTN pin for the return path of the current sourced by the AT pin. Each ATRTN pin is

shared between two adjacent Analog Quads. Additionally, if not used for temperature monitoring,

the AT pin can provide functionality similar to that of the AV pad. However, in this mode only

positive voltages can be applied to the AT pin, and only two prescaler factors are available (16 V

and 4 V ranges—refer to Table 2-54 on page 2-128).

Discrete

Bipolar

Transistor

Off-Chip

ATRTN

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-76 • Temperature Monitor Quad

Fusion uses a remote diode as a temperature sensor. The Fusion Temperature Monitor uses a

differential input; the AT pin and ATRTN (AT Return) pin are the differential inputs to the

2-96

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Temperature Monitor. There is one Temperature Monitor in each Quad. A simplified block diagram

is shown in Figure 2-77.

VDD33A

10 µA

ATx

100 µA

TMSTBx

+

–

to Analog MUX

(refer Table 2-36

for MUX Channel

Number)

+

V_ADC

∆V

–

12.5 X

ATRTNxy

Figure 2-77 • Block Diagram for Temperature Monitor Circuit

The Fusion approach to measuring temperature is forcing two different currents through the diode

with a ratio of 10:1. The switch that controls the different currents is controlled by the Temperature

Monitor Strobe signal, TMSTB. Setting TMSTB to '1' will initiate a Temperature reading. The TMSTB

should remain '1' until the ADC finishes sampling the voltage from the Temperature Monitor. The

minimum sample time for the Temperature Monitor cannot be less than the minimum strobe high

time minus the setup time. Figure 2-78 shows the timing diagram.

t_TMSHI

TMSTBx

t_TMSLO

t_TMSSET

V_ADC

ADC should start

sampling at this point

ADCSTART

Figure 2-78 • Timing Diagram for the Temperature Monitor Strobe Signal

The diode’s voltage is measured at each current level and the temperature is calculated based on

EQ 2-7.

I_TMSLO

kT

q

⎛

⎞

⎠

----- ---------------

_TMSLO– V_TMSHI= n ln

V

⎝

I_TMSHI

EQ 2-7

Preliminary v1.7

2-97

Device Architecture

where

I_TMSLOis the current when the Temperature Strobe is Low, typically 100 µA

I_TMSHIis the current when the Temperature Strobe is High, typically 10 µA

V_TMSLOis diode voltage while Temperature Strobe is Low

V_TMSHIis diode voltage while Temperature Strobe is High

n is the non-ideality factor of the diode-connected transistor. It is typically 1.004 for the Actel-

recommended transistor type 2N3904.

K = 1.3806 x 10^-23J/K is the Boltzman constant

Q = 1.602 x 10^-19C is the charge of a proton

When I_TMSLO/ I_TMSHI= 10, the equation can be simplified as shown in EQ 2-8.

ΔV = V_TMSLO– V_TMSHI= 1.986 × 10^–4nT

EQ 2-8

In the Fusion TMB, the ideality factor n for 2N3904 is 1.004 and ΔV is amplified 12.5 times by an

internal amplifier; hence the voltage before entering the ADC is as given in EQ 2-9.

V_ADC= ΔV × 12.5 = 2.5 mV ⁄ (K × T)

EQ 2-9

This means the temperature to voltage relationship is 2.5 mV per degree Kelvin. The unique design

of Fusion has made the Temperature Monitor System simple for the user. When the 10-bit mode

ADC is used, each LSB represents 1 degree Kelvin, as shown in EQ 2-10. That is, e. 25°C is equal to

293°K and is represented by decimal 293 counts from the ADC.

2¹⁰

2.56 V

----------------

1K = 2.5 mV ×

= 1 LSB

EQ 2-10

If 8-bit mode is used for the ADC resolution, each LSB represents 4 degrees Kelvin; however, the

resolution remains as 1 degree Kelvin per LSB, even for 12-bit mode, due to the Temperature

Monitor design. An example of the temperature data format for 10-bit mode is shown in

Table 2-38.

Table 2-38 • Temperature Data Format

Digital Output

Temperature

–40°C

–20°C

0°C

Temperature (K)

(ADC 10-bit mode)

00 1110 1001

00 1111 1101

01 0001 0001

01 0001 0010

01 0001 1011

01 0010 1010

01 0100 0011

01 0110 0110

233

253

273

274

283

298

323

358

1°C

10 °C

25°C

50 °C

85 °C

2-98

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Terminology

Resolution

Resolution defines the smallest temperature change Fusion Temperature Monitor can resolve. For

ADC configured as 8-bit mode, each LSB represents 4°C, and 1°C per LSB for 10-bit mode. With 12-

bit mode, the Temperature Monitor can still only resolve 1°C due to Temperature Monitor design.

Offset

The Fusion Temperature Monitor has a systematic offset of +5°C, excluding error due board

resistance and ideality factor of the external diode, between the operation range of –40°C to

+85°C. For instance, 25°C will be read by the Temperature Monitor as 30°C plus error. The user can

remove any offset error through hardware or software during the calibration routine.

Preliminary v1.7

2-99

Device Architecture

Analog-to-Digital Converter Block

At the heart of the Fusion analog system is a programmable Successive Approximation Register

(SAR) ADC. The ADC can support 8-, 10-, or 12-bit modes of operation. In 12-bit mode, the ADC can

resolve 500 ksps. All results are MSB-justified in the ADC. The input to the ADC is a large 32:1

analog input multiplexer. A simplified block diagram of the Analog Quads, analog input

multiplexer, and ADC is shown in Figure 2-79. The ADC offers multiple self-calibrating modes to

ensure consistent high performance both at power-up and during runtime.

V_CC(1.5 V)

0

1

Pads

AV0

AC0

AG0

AT0

Analog

Quad 0

These are hardwired

connections within

Analog Quad.

ATRETURN01

AV1

AC1

AG1

AT1

Analog

Quad 1

AV2

AC2

AG2

AT2

Analog

Quad 2

ATRETURN23

AV3

AC3

AG3

AT3

Analog

Quad 3

AV4

AC4

AG4

AT4

Analog

Quad 4

12

Analog MUX

(32 to 1)

ATRETURN45

ADC

AV5

AC5

AG5

AT5

AV6

AC6

AG6

AT6

Analog

Quad 5

Digital Output to FPGA

Analog

Quad 6

ATRETURN67

AV7

AC7

AG7

AT7

Analog

Quad 7

AV8

AC8

AG8

AT8

Analog

Quad 8

ATRETURN89

AV9

AC9

AG9

AT9

Analog

Quad 9

31

Temperature

Monitor

CHNUMBER[4:0]

Internal Diode

Figure 2-79 • ADC Block Diagram

2-100

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

ADC Input Multiplexer

At the input to the Fusion ADC is a 32:1 multiplexer. Of the 32 input channels, up to 30 are user

definable. Two of these channels are hardwired internally. Channel 31 connects to an internal

temperature diode so the temperature of the Fusion device itself can be monitored. Channel 0 is

wired to the FPGA’s 1.5 V V_CCsupply, enabling the Fusion device to monitor its own power supply.

Doing this internally makes it unnecessary to use an analog I/O to support these functions. The

balance of the MUX inputs are connected to Analog Quads (see the "Analog Quad" section on

page 2-84). Table 2-39 defines which Analog Quad inputs are associated with which specific analog

MUX channels. The number of Analog Quads present is device-dependent; refer to the family list in

the "Fusion Family" table on page I of this datasheet for the number of quads per device.

Regardless of the number of quads populated in a device, the internal connections to both V_CCand

the internal temperature diode remain on Channels 0 and 31, respectively. To sample the internal

temperature monitor, it must be strobed (similar to the AT pads). The TMSTBINT pin on the Analog

Block macro is the control for strobing the internal temperature measurement diode.

To determine which channel is selected for conversion, there is a five-pin interface on the Analog

Block, CHNUMBER[4:0], defined in Table 2-40 on page 2-102. Table 2-39 shows the correlation

between the analog MUX input channels and the analog input pins.

Table 2-39 • Analog MUX Channels

Analog MUX Channel

Signal

Vcc_analog

AV0

AC0

Analog Quad Number

0

1

Analog Quad 0

2

3

AT0

4

AV1

AC1

Analog Quad 1

Analog Quad 2

Analog Quad 3

Analog Quad 4

Analog Quad 5

Analog Quad 6

5

6

AT1

7

AV2

AC2

8

9

AT2

10

11

12

13

14

15

16

17

18

19

20

21

AV3

AC3

AT3

AV4

AC4

AT4

AV5

AC5

AT5

AV6

AC6

AT6

Preliminary v1.7

2-101

Device Architecture

Table 2-39 • Analog MUX Channels (continued)

Analog MUX Channel

Signal

AV7

AC7

AT7

Analog Quad Number

22

23

24

25

26

27

28

29

30

31

Analog Quad 7

AV8

AC8

AT8

Analog Quad 8

Analog Quad 9

AV9

AC9

AT9

Internal temperature

monitor

Table 2-40 • Channel Selection

Channel Number

CHNUMBER[4:0]

0

1

2

3

00000

00001

00010

00011

.

30

31

11110

11111

2-102

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

ADC Description

The Actel Fusion ADC is a 12-bit SAR ADC. It offers a wide variety of features for different use

models. Figure 2-80 shows a block diagram of the Fusion ADC.

•

Configurable resolution: 8-bit, 10-bit, and 12-bit mode

DNL: 0.6 LSB for 10-bit mode

INL: 0.4 LSB for 10-bit mode

No missing code

Internal VAREF = 2.56 V

Maximum Sample Rate = 600 ksps

Power-up calibration and dynamic calibration after every sample to compensate for

temperature drift over time

CALIBRATE

SAMPLE

BUSY

DATAVALID

VAREF

Analog

STATUS

MUX

32

12

Signals from

Analog Quads

SAR ADC

RESULT

CHNUMBER

SYSCLK

STC

MODE

TVC

ADCCLK

Figure 2-80 • ADC Simplified Block Diagram

ADC Configuration Description

The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after

conversion, and dynamic calibration. This is controlled by MODE[3:0], as defined in Table 2-41.

Table 2-41 • Mode Bits Function

Name

Bits

Function

MODE

3

0 – Internal calibration after every conversion; two ADCCLK cycles are used

after the conversion.

1 – No calibration after every conversion

MODE

2

0 – Power-down after conversion

1 – No Power-down after conversion

1:0

00 – 10-bit

01 – 12-bit

10 – 8-bit

11 – Unused

Preliminary v1.7

2-103

Device Architecture

The speed of the ADC depends on its internal clock, ADCCLK, which is not accessible to users. The

ADCCLK is derived from SYSCLK. Input signal TVC[7:0], Time Divider Control, determines the speed

of the ADCCLK in relationship to SYSCLK, based on EQ 2-11.

t_ADCCLK= 4 × (1 + TVC) × t_SYSCLK

EQ 2-11

TVC: Time Divider Control (0–255)

t

_ADCCLKis the period of ADCCLK, and must be between 0.5 MHz and 10 MHz

_SYSCLKis the period of SYSCLK

t

Table 2-42 • TVC Bits Function

Name

Bits

Function

TVC

[7:0]

SYSCLK divider control

The frequency of ADCCLK, f_ADCCLK, must be within 0.5 Hz to 10 MHz.

The inputs to the ADC are synchronized to SYSCLK. A conversion is initiated by asserting the

ADCSTART signal on a rising edge of SYSCLK. Figure 2-82 on page 2-108 and Figure 2-83 on

page 2-108 show the timing diagram for the ADC.

A conversion is performed in three phases. In the first phase, the analog input voltage is sampled

on the input capacitor. This phase is called sample phase. During the sample phase, the output

signals BUSY and SAMPLE change from '0' to '1', indicating the ADC is busy and sampling the

analog signal. The sample time can be controlled by input signals STC[7:0]. The sample time can be

calculated by EQ 2-12. When controlling the sample time for the ADC along with the use of

Prescaler or Current Monitor or Temperature Monitor, the minimum sample time for each must be

obeyed. Refer to the corresponding section and Table 2-43 for further information.

t_sample= (2 + STC) × t_ADCCLK

EQ 2-12

STC: Sample Time Control value (0–255)

t_SAMPLEis the sample time

Table 2-43 • STC Bits Function

Name

Bits

Function

STC

[7:0]

Sample time control

Sample time is computed based on the period of ADCCLK.

The second phase is called the distribution phase. During distribution phase, the ADC computes the

equivalent digital value from the value stored in the input capacitor. In this phase, the output

signal SAMPLE goes back to '0', indicating the sample is completed; but the BUSY signal remains

'1', indicating the ADC is still busy for distribution. The distribution time depends strictly on the

number of bits. If the ADC is configured as a 10-bit ADC, then 10 ADCCLK cycles are needed. EQ 2-

13 describes the distribution time.

t_distrib= N × t_ADCCLK

EQ 2-13

N: Number of bits

The last phase is the post-calibration phase. This is an optional phase. The post-calibration phase

takes two ADCCLK cycles. The output BUSY signal will remain '1' until the post-calibration phase is

completed. If the post-calibration phase is skipped, then the BUSY signal goes to '0' after

distribution phase. As soon as BUSY signal goes to '0', the DATAVALID signal goes to '1', indicating

the digital result is available on the RESULT output signals. DATAVAILD will remain '1' until the next

ADCSTART is asserted. Actel recommends enabling post-calibration to compensate for drift and

temperature-dependent effects. This ensures that the ADC remains consistent over time and with

2-104

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

temperature. The post-calibration phase is enabled by bit 3 of the Mode register. EQ 2-14 describes

the post-calibration time.

t_post-cal= MODE[3] × (2 × t_ADCCLK

)

EQ 2-14

MODE[3]: Bit 3 of the Mode register, described in Table 2-41 on page 2-103.

The calculation for the conversion time for the ADC is summarized in EQ 2-15.

t_conv= t_{sync_read}+ t_sample+ t_distrib+ t_post-cal+ t_{sync_write}

EQ 2-15

t

_conv: conversion time

_{sync_read}: maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the

t

worst case is a period of SYSCLK, t_SYSCLK

.

t

_sample: Sample time

_distrib: Distribution time

_post-cal: Post-calibration time

_{sync_write}: Maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the

worst case is a period of SYSCLK, t_SYSCLK

.

Example

This example shows how to choose the correct settings to achieve the fastest sample time in 10-bit

mode for a system that runs at 66 MHz.

The period of SYSCLK: t_SYSCLK= 1/66 MHz = 0.015 µs

Choosing TVC between 1 and 33 will meet the maximum and minimum period for the ADCCLK

requirement. A higher TVC leads to a higher ADCCLK period.

The minimum TVC is chosen so that t_distriband t_post-calcan be run faster. The period of ADCCLK

with a TVC of 1 can be computed by EQ .

t_ADCCLK= 4 × (1 + TVC) × t_SYSCLK= 4 × (1 + 1) × 0.015 µs = 0.12 µs

From Table 2-47 on page 2-118, minimum conversion for 10-bit mode is 1.8 µs. To compute STC, the

calculation will first compute the post-calibration time, second the distribution time, and finally the

STC setting.

Since Actel recommends post-calibration for temperature drift over time, post-calibration shall be

enabled and the post-calibration time, t_post-cal, can be computed by EQ 2-16. The post-calibration

time is 0.24 µs.

t_post-cal= 2 × t_ADCCLK= 0.24 µs

EQ 2-16

The distribution time, t_distrib, is equal to 1.2 µs and can be computed using EQ 2-17.

t_distrib= N × t_ADCCLK= 10 × 0.12 = 1.2 µs

EQ 2-17

The STC value can now be computed through EQ 2-18. The sample time is equal to 0.32 µs. By

rearranging EQ 2-12 on page 2-104 with a t_sampleof 0.35 µs, the STC can be computed.

t_sample= t_conv– t_post-cal– t_distrib– t_{sync_read}– t_{sync_write}

= 1.8 µs – 0.24 µs – 1.2 µs – 0.15 µs – 0.15 µs = 0.32 µs

t_sample

STC = ------------------- – 2 = ------------------ – 2 = 2.85

t_ADCCLK0.12 µs

0.35 µs

EQ 2-18

Preliminary v1.7

2-105

Device Architecture

And so, STC will be rounded up to 3 to ensure the minimum conversion time is met. The sample

time, t_sample, with an STC of 3, is now equal to 0.36 µs.

The total sample time, using EQ 2-19, can now be summated.

= t_{sync_read}+ t_sample+ t_distrib+ t_post-cal+ t_{sync_write}= 0.015 µs + 0.36 µs + 1.2 µs + 0.24 µs + 0.015 µs = 1.8

EQ 2-19

The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is listed

as follows:

TVC[7:0]

STC[7:0]

= 1

= 3

= 0x01

= 0x03

MODE[3:0] = b'0100 = 0x4*

*Note that no power-down after every conversion is chosen in this case; however, if the application

is power-sensitive, the MODE[2] can be set to '0', as described above, and it will not affect any

performance.

Integrated Voltage Reference

The Fusion device has an integrated on-chip 2.56 V reference voltage for the ADC. The value of this

reference voltage was chosen to make the prescaling and postscaling factors for the prescaler

blocks change in a binary fashion. However, if desired, an external reference voltage of up to 3.3 V

can be connected between the VAREF and GNDREF pins. The VAREFSEL control pin is used to select

the reference voltage.

Table 2-44 • VAREF Bit Function

Name

Bit

Function

VAREF

0

Reference voltage selection

0 – Internal voltage reference selected. VAREF pin outputs 2.56 V.

1 – Input external voltage reference from VAREF and GNDREF

ADC Operation Description

The ADC can be powered down independently of the FPGA core, as an additional control or for

power-saving considerations, via the PWRDWN pin of the Analog Block. The PWRDWN pin controls

only the comparators in the ADC.

Once the ADC has powered up and been released from reset, ADCRESET, the ADC will initiate a

calibration routine designed to provide optimal ADC performance. The Fusion ADC offers a robust

calibration scheme to reduce integrated offset and linearity errors. The offset and linearity errors

of the main capacitor array are compensated for with an 8-bit calibration capacitor array. The

offset/linearity error calibration is carried out in two ways. First, a power-up calibration is carried

out when the ADC comes out of reset. This is initiated by the CALIBRATE output of the Analog

Block macro and is a fixed number of ADC_CLK cycles (3,840 cycles), as shown in Figure 2-81 on

page 2-107. In this mode, the linearity and offset errors of the capacitors are calibrated.

To further compensate for drift and temperature-dependent effects, every conversion is followed

by post-calibration of either the offset or a bit of the main capacitor array. The post-calibration

ensures that, over time and with temperature, the ADC remains consistent.

After both calibration and the setting of the appropriate configurations, as explained above, the

ADC is ready for operation. Setting the ADCSTART signal high for one clock period will initiate the

sample and conversion of the analog signal on the channel as configured by CHNUMBER[4:0]. The

status signals SAMPLE and BUSY will show when the ADC is sampling and converting (Figure 2-83

on page 2-108). Both SAMPLE and BUSY will initially go high. After the ADC has sampled and held

the analog signal, SAMPLE will go low. After the entire operation has completed and the analog

signal is converted, BUSY will go low and DATAVALID will go high. This indicates that the digital

result is available on the RESULT[11:0] pins.

2-106

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

DATAVALID will remain high until a subsequent ADC_START is issued. The DATAVALID goes low on

the rising edge of SYSCLK as shown in Figure 2-82 on page 2-108. The RESULT signals will be kept

constant until the ADC finishes the subsequent sample. The next sampled RESULT will be available

when DATAVALID goes high again. It is ideal to read the RESULT when DATAVALID is '1'. The

RESULT is latched and remains unchanged until the next DATAVLAID rising edge.

Intra-Conversion

Performing a conversion during power-up, calibration is possible but should be avoided, since the

performance is not guaranteed, as shown in Table 2-46 on page 2-115. This is described as intra-

conversion.

Injected Conversion

A conversion can be interrupted by another conversion. Before the current conversion is finished, a

second conversion can be started by issuing a pulse on signal ADCSTART. When a second conversion

is issued before the current conversion is completed, the current conversion would be dropped and

the ADC would start the second conversion on the rising edge of the SYSCLK. This is known as

injected conversion. Since the ADC is synchronous, the minimum time to issue a second conversion

is two clock cycles of SYSCLK after the previous one.

Timing Diagram

t_CAL= 3,840 t_ADCCLK

*

SYSCLK

t_RECCLR

t_REMCLR

ADCRESET

t_SUTVCt_HDTVC

TVC[7:0]

t_CK2QCAL

CALIBRATE

Note: *Refer to EQ 2-11 on page 2-104 for the calculation on the period of ADCCLK, t_ADCCLK

.

Figure 2-81 • Power-Up Calibration Status Signal Timing Diagram

Preliminary v1.7

2-107

Device Architecture

t_MINSYSCLK

t_MPWSYSCLK

SYSCLK

t_SUADCSTARTt_HDADCSTART

ADCSTART

t_SUMODEt_HDMODE

MODE[3:0]

TVC[7:0]

t_SUTVCt_HDTVC

t_SUSTCt_HDSTC

STC[7:0]

VAREF

t_SUVAREFSELt_HDVAREFSEL

t_SUCHNUMt_HDCHNUM

CHNUMBER[7:0]

Figure 2-82 • Input Setup Time

3

t_SAMPLE

1

t_DATA2START

SYSCLK

t_SUADCSTARTt_HDADCSTART

ADCSTART

BUSY

t_CK2QBUSY

t_CK2QSAMPLE

SAMPLE

2

t_CONV

t_CK2QVAL

DATAVALID

ADC_RESULT[11:0]

t_CLK2RESULT

1^stSample Result

2^ndSample Result

Notes:

1. Refer to EQ 2-12 on page 2-104 for the calculation on the sample time, t_SAMPLE

2. See EQ 2-19 on page 2-106 for calculation on the conversion time, t_CONV

.

3. Minimum time to issue an ADCSTART after DATAVALID is 1 SYSCLK period

Figure 2-83 • Standard Conversion Status Signal Timing Diagram

2-108

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

ADC Interface Timing

Table 2-45 • ADC Interface Timing

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Description

Mode Pin Setup Time

Parameter

t_SUMODE

–2

0.56

0.26

0.68

0.32

1.58

1.27

0.00

0.67

0.90

0.00

0.75

0.43

1.33

0.63

3.12

0.22

2.53

2.06

2.15

2.41

2.17

2.25

0.00

0.63

4.00

100.00

–1

0.64

0.29

0.77

0.36

1.79

1.45

0.00

0.76

1.03

0.00

0.85

0.49

1.51

0.71

3.55

0.25

2.89

2.35

2.45

2.74

2.48

2.56

0.00

0.72

4.00

100.00

Std.

0.75

0.34

0.90

0.43

2.11

1.71

0.00

0.89

1.21

0.00

1.00

0.57

1.78

0.84

4.17

0.30

3.39

2.76

2.88

3.22

2.91

3.01

0.00

0.84

4.00

100.00

Units

ns

MHz

t_HDMODE

Mode Pin Hold Time

t_SUTVC

Clock Divide Control (TVC) Setup Time

Clock Divide Control (TVC) Hold Time

Sample Time Control (STC) Setup Time

Sample Time Control (STC) Hold Time

Voltage Reference Select (VAREFSEL) Setup Time

Voltage Reference Select (VAREFSEL) Hold Time

Channel Select (CHNUMBER) Setup Time

Channel Select (CHNUMBER) Hold Time

Start of Conversion (ADCSTART) Setup Time

Start of Conversion (ADCSTART) Hold Time

Busy Clock-to-Q

t_HDTVC

t_SUSTC

t_HDSTC

t_SUVAREFSEL

t_HDVAREFSEL

t_SUCHNUM

t_HDCHNUM

t_SUADCSTART

t_HDADCSTART

t_CK2QBUSY

t_CK2QCAL

Power-Up Calibration Clock-to-Q

Valid Conversion Result Clock-to-Q

Sample Clock-to-Q

t_CK2QVAL

t_CK2QSAMPLE

t_CK2QRESULT

t_CLR2QBUSY

t_CLR2QCAL

t_CLR2QVAL

t_CLR2QSAMPLE

t_CLR2QRESULT

t_RECCLR

Conversion Result Clock-to-Q

Busy Clear-to-Q

Power-Up Calibration Clear-to-Q

Valid Conversion Result Clear-to-Q

Sample Clear-to-Q

Conversion result Clear-to-Q

Recovery Time of Clear

t_REMCLR

Removal Time of Clear

t_MPWSYSCLK

t_FMAXSYSCLK

Clock Minimum Pulse Width for the ADC

Clock Maximum Frequency for the ADC

Preliminary v1.7

2-109

Device Architecture

Terminology

Conversion Time

Conversion time is the interval between the release of the hold state (imposed by the input

circuitry of a track-and-hold) and the instant at which the voltage on the sampling capacitor settles

to within one LSB of a new input value.

DNL – Differential Non-Linearity

For an ideal ADC, the analog-input levels that trigger any two successive output codes should differ

by one LSB (DNL = 0). Any deviation from one LSB in defined as DNL (Figure 2-84).

Ideal Output

Actual Output

Error = –0.5 LSB

Error = +1 LSB

Input Voltage to Prescaler

Figure 2-84 • Differential Non-Linearity (DNL)

ENOB – Effective Number of Bits

ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling

rate. An ideal ADC’s error consists only of quantization of noise. As the input frequency increases,

the overall noise (particularly in the distortion components) also increases, thereby reducing the

ENOB and SINAD (also see “Signal-to-Noise and Distortion Ratio (SINAD)”.) ENOB for a full-scale,

sinusoidal input waveform is computed using EQ 2-20.

SINAD – 1.76

ENOB = ----------------------------------

6.02

EQ 2-20

FS Error – Full-Scale Error

Full-scale error is the difference between the actual value that triggers that transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error.

2-110

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Gain Error

The gain error of an ADC indicates how well the slope of an actual transfer function matches the

slope of the ideal transfer function. Gain error is usually expressed in LSB or as a percent of full-

scale (%FSR). Gain error is the full-scale error minus the offset error (Figure 2-85).

Gain = 2 LSB

1...11

Ideal Output

Actual Output

0...00

Input Voltage to Prescaler

Figure 2-85 • Gain Error

Gain Error Drift

Gain-error drift is the variation in gain error due to a change in ambient temperature, typically

expressed in ppm/°C.

Preliminary v1.7

2-111

Device Architecture

INL – Integral Non-Linearity

INL is the deviation of an actual transfer function from a straight line. After nullifying offset and

gain errors, the straight line is either a best-fit straight line or a line drawn between the end points

of the transfer function (Figure 2-86).

INL = +0.5 LSB

Ideal Output

Actual Output

INL = +1 LSB

Input Voltage to Prescaler

Figure 2-86 • Integral Non-Linearity (INL)

LSB – Least Significant Bit

In a binary number, the LSB is the least weighted bit in the group. Typically, the LSB is the furthest

right bit. For an ADC, the weight of an LSB equals the full-scale voltage range of the converter

divided by 2^N, where N is the converter’s resolution. For a 10-bit ADC with a unipolar full-scale

voltage of 2.56 V, 1 LSB = (2.56 V / 2¹⁰) = 2.5 mV.

No Missing Codes

An ADC has no missing codes if it produces all possible digital codes in response to a ramp signal

applied to the analog input.

Offset Error

Offset error indicates how well the actual transfer function matches the ideal transfer function at a

single point. For an ideal ADC, the first transition occurs at 0.5 LSB above zero. The offset voltage is

measured by applying an analog input such that the ADC outputs all zeroes and increases until the

first transition occurs (Figure 2-87).

2-112

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Ideal Output

Actual Output

0...01

0...00

Offset Error = 1.5 LSB

Input Voltage to Prescaler

Figure 2-87 • Offset Error

Resolution

ADC resolution is the number of bits used to represent an analog input signal. To more accurately

replicate the analog signal, resolution needs to be increased.

Sampling Rate

Sampling rate or sample frequency, specified in samples per second (sps), is the rate at which an

ADC acquires (samples) the analog input.

SNR – Signal-to-Noise Ratio

SNR is the ratio of the amplitude of the desired signal to the amplitude of the noise signals at a

given point in time. For a waveform perfectly reconstructed from digital samples, the theoretical

maximum SNR (EQ 2-21) is the ratio of the full-scale analog input (RMS value) to the RMS

quantization error (residual error). The ideal, theoretical minimum ADC noise is caused by

quantization error only and results directly from the ADC’s resolution (N bits):

SNR_dB[MAX]= 6.02_dB× N + 1.76_dB

EQ 2-21

SINAD – Signal-to-Noise and Distortion

SINAD is the ratio of the rms amplitude to the mean value of the root-sum-square of the all other

spectral components, including harmonics, but excluding DC. SINAD is a good indication of the

overall dynamic performance of an ADC because it includes all components which make up noise

and distortion.

Total Harmonic Distortion

THD measures the distortion content of a signal, and is specified in decibels relative to the carrier

(dBc). THD is the ratio of the RMS sum of the selected harmonics of the input signal to the

fundamental itself. Only harmonics within the Nyquist limit are included in the measurement.

TUE – Total Unadjusted Error

Preliminary v1.7

2-113

Device Architecture

TUE is a comprehensive specification that includes linearity errors, gain error, and offset error. It is

the worst-case deviation from the ideal device performance. TUE is a static specification

(Figure 2-88).

TUE = 0.5 LSB

IDEAL OUTPUT

Input Voltage to Prescaler

Figure 2-88 • Total Unadjusted Error (TUE)

2-114

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Analog System Characteristics

Table 2-46 • Analog Channel Specifications

All Values at Industrial Operating Conditions (unless noted otherwise)

Typical: V_CC33A= 3.3 V, V_CC= 1.5 V, and T_A= 25°C

Parameter

Description

Condition

Minimum Typical Maximum Units

Voltage Monitor using Analog Pads AV, AC and AT (using prescaler)

V_INAP

Input Voltage

Refer to Table 3-2 on page 3-3.

Uncalibrated Gain

and Offset Errors

Refer

page 2-120.

to

Table 2-48

on

Calibrated Gain

and Offset Errors

Refer to

page 2-121.

Table 2-49

Bandwidth

100

10

kHz

µs

Input Resistance

Scaling Factor

Refer to Table 3-3 on page 3-4.

Prescaler modes (Table 2-54 on

page 2-128).

Sampling Time

Current Monitor using Analog Pads AV and AC1 (potential on the AV pad must be greater than the AC pad)

1

V_RSM

Maximum

VAREF / 10 mV

Differential Input

Resolution

See Accuracy specification

Common Mode

Range

Refer to Table 3-2 on page 3-3 for

maximum voltage limits.

–10.5 to

+12

V

CMRR

Common Mode

Rejection Ratio

DC – 1 kHz

60

dB

1 kHz – 10 kHz

>10 kHz

50

30

dB

µs

t_CMSHI

Strobe

High time

ADC

conv.

time

200

t_CMSLO

t_CMSSET

Low time

5

µs

Setting time

0.02

Accuracy

Input differential voltage > 50 mV

–2 – (0.05 × mV

(AV – AC)

to

2 + (0.05 ×

(AV – AC))

Notes:

1. V_RSMis the maximum voltage drop across the current sense resistor.

2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad.

There is no reliability concern on digital inputs as long as V_INDdoes not exceed these limits.

3. V_INDis limited to V_CC33A+ 0.2 to allow reaching 10 MHz input frequency.

4. Measurement is done by forcing a temperature on an external diode, with the Fusion device at room

temperature.

5. The temperature offset is a fixed positive value.

6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be

used, based on voltage on the pad.

Preliminary v1.7

2-115

Device Architecture

Table 2-46 • Analog Channel Specifications (continued)

All Values at Industrial Operating Conditions (unless noted otherwise)

Typical: V_CC33A= 3.3 V, V_CC= 1.5 V, and T_A= 25°C

Parameter

Description

Condition

Minimum Typical Maximum Units

Temperature Monitor Using Analog Pad AT

External

Temperature

Monitor⁴

(using

external

diode

Resolution

8-bit ADC

10-bit ADC

12-bit ADC

4

1

5

3

°C

ꢀC

°C

Offset ⁵

Accuracy

2N3904)

External Sensor

Source Current

High level

10

µA

Low level

8-bit ADC

10-bit ADC

12-bit ADC

100

4

µA

°C

ꢀC

°C

µs

Internal

Temperature

Monitor

Resolution

1

Offset ⁵

5

Accuracy

3

t_TMSHI

t_TMSLO

t_TMSSET

Temperature

Monitor Strobe

High time

Low time

10

5

105

Setting time

5

Analog Input as a Digital Input

2, 3

V_IND

Input Voltage

Hysteresis

Refer to Table 3-2 on page 3-3.

V_HYSDIN

V_IHDIN

V_ILDIN

0.3

1.2

0.9

V

Input HIGH

Input LOW

V

V_MPWDIN

Minimum Pulse

Width

50

ns

F_DIN

Maximum Frequency

10

MHz

µA

I_STBDIN

Input Leakage

Current

2

I_DYNDIN

t_INDIN

Dynamic Current

Input Delay

20

10

µA

ns

Notes:

1. V_RSMis the maximum voltage drop across the current sense resistor.

2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad.

There is no reliability concern on digital inputs as long as V_INDdoes not exceed these limits.

3. V_INDis limited to V_CC33A+ 0.2 to allow reaching 10 MHz input frequency.

4. Measurement is done by forcing a temperature on an external diode, with the Fusion device at room

temperature.

5. The temperature offset is a fixed positive value.

6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be

used, based on voltage on the pad.

2-116

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-46 • Analog Channel Specifications (continued)

All Values at Industrial Operating Conditions (unless noted otherwise)

Typical: V_CC33A= 3.3 V, V_CC= 1.5 V, and T_A= 25°C

Parameter

Description

Condition

Minimum Typical Maximum Units

Gate Driver Output Using Analog Pad AG

V_G

I_G

Voltage Range

Output Current Drive High Current Mode⁶at 1.0 V

Refer to Table 3-2 on page 3-3.

20

mA

µA

nA

Low Current Mode – 1 µA

1

3

Low Current Mode – 3 µA

Low Current Mode – 10 µA

10

30

100

Low Current Mode – 30 µA

I_OFFG

F_G

Maximum

Current

Off

High Current Mode 1 kΩ resistive load

1.3

3

MHz

kHz

(maximum at 1.0 V

switching

rate)

Low Current Mode – 3,000 kΩ resistive load

1 µA

Low Current Mode – 1,000 kΩ resistive load

3 µA

7

Low Current Mode – 300 kΩ resistive load

10 µA

25

78

Low Current Mode – 105 kΩ resistive load

30 µA

Notes:

1. V_RSMis the maximum voltage drop across the current sense resistor.

2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad.

There is no reliability concern on digital inputs as long as V_INDdoes not exceed these limits.

3. V_INDis limited to V_CC33A+ 0.2 to allow reaching 10 MHz input frequency.

4. Measurement is done by forcing a temperature on an external diode, with the Fusion device at room

temperature.

5. The temperature offset is a fixed positive value.

6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be

used, based on voltage on the pad.

Preliminary v1.7

2-117

Device Architecture

Table 2-47 • ADC Characteristics in Direct Input Mode

All Values at Industrial Operating Conditions (unless noted otherwise)

Typical: V_CC33A= 3.3 V, V_CC= 1.5 V, and T_A= 25°C

Parameter

Description Condition

Minimum

Typical

Maximum

Units

All Analog Inputs

V_INADC

Input Voltage (direct to Refer to Table 3-2 on

ADC)

page 3-3.

C_INADC

Input Capacitance

Channel not selected

7

8

pF

Channel selected but

not sampling

Channel selected and

sampling

18

pF

Z_INADC

VAREF

Input Impedance

Reference Voltage

8-bit mode

10-bit mode

12-bit mode

2

kΩ

V

2

Internal

Accuracy at 25°C

reference

2.537

2.527

2.56

2.583

Temperature Drift of

Internal Reference

65

ppm/°

C

External reference

V_CC33A

0.05

+

V

DC Accuracy (using external reference)^{1, 2}

TUE

Total Unadjusted Error

8-bit mode

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

0.29

0.72

1.80

0.20

0.32

1.71

0.20

0.60

2.40

0.01

0.05

0.20

0.0004

0.002

0.007

2.0

LSB

%FSR

INL

Integral Non-Linearity

0.25

0.43

1.80

0.24

0.65

2.48

0.17

0.20

0.40

0.003

0.011

0.044

DNL

Differential

Linearity

(no missing codes)

Non- 8-bit mode

10-bit mode

12-bit mode

8-bit mode

Offset Error

Gain Error

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

Gain Error (with internal All modes

reference)

Notes:

1. Accuracy of the external reference is 2.56 V 4.6 mV.

2. Data is based on characterization.

3. The sample rate is time-shared among active analog inputs.

2-118

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-47 • ADC Characteristics in Direct Input Mode (continued)

All Values at Industrial Operating Conditions (unless noted otherwise)

Typical: V_CC33A= 3.3 V, V_CC= 1.5 V, and T_A= 25°C

Parameter

Dynamic Accuracy (using external reference, 100 kHz Sine Wave Input, 2.38 V_P-P, 500 ksps,

_ADCCLK= 10 MHz)^{1, 2}

Description

Condition

Minimum

Typical

Maximum

Units

f

SNR

Signal-to-Noise Ratio

8-bit mode

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

48.0

58.0

62.9

47.6

57.4

62.0

49.5

60.0

64.5

49.5

59.8

64.2

–74.4

–78.3

–77.9

7.9

dB

SINAD

THD

Signal-to-Noise and

Distortion

dB

Total Harmonic

Distortion

–63.0

–64.4

dBc

bits

ENOB

Effective Number of Bits 8-bit mode

10-bit mode

7.6

9.2

9.6

12-bit mode

10.0

10.4

Conversion ²

Conversion Time

8-bit mode

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

1.7

1.8

2.0

µs

Sample Rate²

600

550

500

ksps

Notes:

1. Accuracy of the external reference is 2.56 V 4.6 mV.

2. Data is based on characterization.

3. The sample rate is time-shared among active analog inputs.

Preliminary v1.7

2-119

Device Architecture

Table 2-48 • Uncalibrated Analog Channel Accuracy*

Worst-Case Industrial Conditions, T_A= 85°C

Total Channel

Error (LSB)

Channel Input Offset

Error (LSB)

Channel Input Offset

Error (mV)

Channel Gain Error

(%FSR)

Analog Prescaler Neg.

Pad Range (V) Max. Med. Max. Max Med. Max.

Pos. Neg

Pos.

Neg.

Max.

Pos.

Max. Min. Typ. Max.

Med.

Positive Range

ADC in 10-Bit Mode

AV, AC

16

8

–22

–40

–45

–70

–25

–41

–53

–89

–3

–2

–5

12

17

24

33

5

–11

–16

–33

–11

–12

–20

–40

–4

–2

–5

14

21

36

66

26

38

40

88

4

–169

–87

–63

–66

–11

–6

–32

–40

–43

–39

–3

224

166

144

131

26

3

2

3

5

7

1

0

–3

–4

–3

–4

–5

–1

4

–9

–11

–20

–3

0

2

–19

–7

0

1

–1

0

0.5

0.25

0.125

16

4

–12

–14

–29

9

8

–7

–4

19

24

15

–14

–28

0

–5

–3

10

–5

–4

11

0

AT

–64

–44

5

64

0

–10

2

–11

–2

11

–8

44

0

Negative Range

ADC in 10-Bit Mode

AV, AC

16

8

–35

–65

–86

–10

–19

–28

9

–24

–34

–64

–6

9

–383

–268

–254

–230

–39

–96

–99

–96

–83

–8

148

75

76

78

15

9

5

–1

–2

–3

–4

–5

–6

–5

12

21

37

8

–12

–24

9

4

19

39

15

18

40

56

5

–6

2

–136 –53

–98 –35

–115 –42

6

–7

1

–39

–54

–72

–8

10

14

16

–10

–11

–12

–14

0.5

0.25

0.125

–121 –46

–149 –49

–188 –67

7

–14

–16

–27

–7

19

38

–18

–4

10

7

–112 –27

–14

–3

Note: *Channel Accuracy includes prescaler and ADC accuracies. For 12-bit mode, multiply the LSB count by 4.

For 8-bit mode, divide the LSB count by 4. Gain remains the same.

2-120

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-49 • Calibrated Analog Channel Accuracy ^1,2,3

Worst-Case Industrial Conditions, T_A= 85°C

Condition

Total Channel Error (LSB)

Analog Pad

Prescaler Range (V)

Input Voltage⁴(V)

Negative Max.

Median

Positive Max.

Positive Range

ADC in 10-Bit Mode

AV, AC

16

8

0.300 to 12.0

0.250 to 8.00

0.200 to 4.00

0.150 to 2.00

0.050 to 1.00

0.300 to 16.0

0.100 to 4.00

–6

–7

–6

–5

–7

1

6

7

6

5

7

0

4

–1

2

0

1

–1

AT

16

4

0

–1

Negative Range

ADC in 10-Bit Mode

AV, AC

16

8

–0.400 to –10.5

–0.350 to –8.00

–0.300 to –4.00

–0.250 to –2.00

–0.050 to –1.00

–7

1

9

7

–1

–2

–1

4

–7

9

2

–7

7

1

–16

20

Notes:

1. Channel Accuracy includes prescaler and ADC accuracies. For 12-bit mode, multiply the LSB count by 4. For

8-bit mode, divide the LSB count by 4. Overall accuracy remains the same.

2. Requires enabling Analog Calibration in the Actel tool flow.

3. Calibrated with two-point calibration methodology, using 20% and 80% full-scale points.

4. The lower limit of the input voltage is determined by the prescaler input offset.

Preliminary v1.7

2-121

Device Architecture

Table 2-50 • Analog Channel Accuracy: Monitoring Standard Positive Voltages

Typical Conditions, T_A= 25°C

Direct ADC^2,3

(%FSR)

Calibrated Typical Error per Positive Prescaler Setting¹(%FSR)

InputVoltage

(V)

16 V (12 V)

(AV/AC)

8 V

4 V

2 V

1 V

16 V (AT)

(AV/AC) 4 V (AT) (AV/AC) (AV/AC) (AV/AC) VAREF = 2.56 V

15

1

2

3

4

5

7

9

14

12

1

2

4

5

6

9

5

1

3.3

2.5

1.8

1.5

1.2

0.9

Notes:

1

2

4

1

2

3

1

2

3

1

1. Requires enabling Analog Calibration in the Actel tool flow.

2. Direct ADC mode using an external VAREF of 2.56V 4.6mV, without Analog Calibration macro.

3. For input greater than 2.56 V, the ADC output will saturate. A higher VAREF or prescaler usage is

recommended.

Examples

Calculating Accuracy for an Uncalibrated Analog Channel

Formula

For a given prescaler range,

Output Voltage = (Channel Output Offset in V) + (Input Voltage x Channel Gain)

where

Channel Output offset in V = Channel Output offset in LSBs x Equivalent voltage per LSB

Channel Gain Factor = 1+ (% Channel Gain / 100)

Example

Input Voltage = 5 V

Chosen Prescaler range = 8 V range

Refer to Table 2-48 on page 2-120.

Max. Output Voltage = (Max Positive output offset) + (Input Voltage x Max Gain Factor)

Max. Positive output offset = (8 LSB) x (8mV per LSB in 10-bit mode)

Max. Positive output offset = 64 mV

Max. Gain = 1 + (2/100)

Max. Gain = 1.02

Max. Output Voltage = (64 mV) + (5 V x 1.02)

Max. Output Voltage = 5.164 V

Similarly,

2-122

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Min. Output Voltage = (Min. Negative output offset) + (Input Voltage x Min. Gain)

= (–136 mV) + (5 V x 0.98) = 4.764 V

Calculating Accuracy for a Calibrated Analog Channel

Formula

For a given prescaler range,

Output Voltage = Channel TUE in V + Input Voltage

where

Channel TUE in V = Channel TUE in LSBs x Equivalent voltage per LSB

Example

Input Voltage = 5 V

Chosen Prescaler range = 8 V range

Refer to Table 2-49 on page 2-121.

Max. Output Voltage = Max. Channel TUE in V + Input Voltage

Max. Channel TUE in V = (6 LSB) × (8 mV per LSB in 10-bit mode) = 48 mV

Max. Output Voltage = 48 mV + 5 V = 5.048 V

Similarly,

Min Output Voltage = Min Channel TUE in V + Input Voltage = (-48 mV) + 5 V = 4.952 V

Calculating LSBs from a Given Error Budget

Formula

For a given prescaler range,

LSB count = (Input Voltage × Required % error) / (Equivalent voltage per LSB)

Example

Input Voltage = 5 V

Required error margin= 1%

Refer to Table 2-49 on page 2-121.

Equivalent voltage per LSB = 16 mV for a 16V prescaler, with ADC in 10-bit mode

LSB Count = (5.0 V × 1%) / (0.016)

LSB Count = 3.125

Equivalent voltage per LSB = 8 mV for an 8 V prescaler, with ADC in 10-bit mode

LSB Count = (5.0 V × 1%) / (0.008)

LSB Count = 6.25

The 8 V prescaler satisfies the calculated LSB count accuracy requirement (see Table 2-49 on

page 2-121).

Preliminary v1.7

2-123

Device Architecture

Analog Configuration MUX

The ACM is the interface between the FPGA, the Analog Block configurations, and the real-time

counter. Actel Libero IDE will generate IP that will load and configure the Analog Block via the

ACM. However, users are not limited to using the Libero IDE IP. This section provides a detailed

description of the ACM's register map, truth tables for proper configuration of the Analog Block

and RTC, as well as timing waveforms so users can access and control the ACM directly from their

designs.

The Analog Block contains four 8-bit latches per Analog Quad that are initialized through the

ACM. These latches act as configuration bits for Analog Quads. The ACM block runs from the core

voltage supply (1.5 V).

Access to the ACM is achieved via 8-bit address and data busses with enables. The pin list is

provided in Table 2-36 on page 2-82. The ACM clock speed is limited to a maximum of 10 MHz,

more than sufficient to handle the low-bandwidth requirements of configuring the Analog Block

and the RTC (sub-block of the Analog Block).

Table 2-51 decodes the ACM address space and maps it to the corresponding Analog Quad and

configuration byte for that quad.

Table 2-51 • ACM Address Decode Table for Analog Quad

ACMADDR [7:0] in

Decimal

Associated

Peripheral

Name

–

Description

–

0

1

2

3

4

5

Analog Quad

AQ0

AQ1

Byte 0

Byte 1

Byte 2

Byte 3

Byte 0

.

36

37

38

39

40

41

AQ8

AQ9

Byte 3

Byte 0

Analog Quad

Byte 1

Byte 2

Byte 3

Undefined

.

63

64

65

66

67

68

72

Undefined

Counter bits 7:0

RTC

COUNTER0

COUNTER1

COUNTER2

COUNTER3

COUNTER4

MATCHREG0

Counter bits 15:8

Counter bits 23:16

Counter bits 31:24

Counter bits 39:32

Match register bits 7:0

2-124

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-51 • ACM Address Decode Table for Analog Quad (continued)

ACMADDR [7:0] in

Decimal

Associated

Peripheral

Name

Description

73

MATCHREG1

MATCHREG2

MATCHREG3

MATCHREG4

MATCHBITS0

MATCHBITS1

MATCHBITS2

MATCHBITS3

MATCHBITS4

CTRL_STAT

Match register bits 15:8

Match register bits 23:16

Match register bits 31:24

Match register bits 39:32

Individual match bits 7:0

Individual match bits 15:8

Individual match bits 23:16

Individual match bits 31:24

Individual match bits 39:32

RTC

74

75

76

80

81

82

83

84

88

Control (write) / Status (read)

register bits 7:0

89

TEST_REG

Test register(s)

RTC

Note: ACMADDR bytes 1 to 40 pertain to the Analog Quads; bytes 64 to 89 pertain to the RTC.

1

ACM Characteristics

ACMCLK

t_SUEACM

t_HEACM

ACMWEN

ACMWDATA

ACMADDRESS

t_SUDACM

t_HDACM

D0

D1

A1

t_SUAACM

t_HAACM

A0

Figure 2-89 • ACM Write Waveform

t_MPWCLKACM

ACMCLK

ACMADDRESS

ACMRDATA

A0

A1

t_CLKQACM

RD0

RD1

Figure 2-90 • ACM Read Waveform

1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the

rc_osc, byte_en, and aq_wen signals have no impact.

Preliminary v1.7

2-125

Device Architecture

Timing Characteristics

Table 2-52 • Analog Configuration Multiplexer (ACM) Timing

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_CLKQACM

t_SUDACM

t_HDACM

Description

Clock-to-Q of the ACM

–2

–1

Std.

26.42

5.88

0.00

6.33

0.00

5.27

0.00

10.00

Units

ns

19.73

4.39

0.00

4.73

0.00

3.93

0.00

22.48

5.00

0.00

5.38

0.00

4.48

0.00

10.00

Data Setup time for the ACM

Data Hold time for the ACM

Address Setup time for the ACM

Address Hold time for the ACM

Enable Setup time for the ACM

Enable Hold time for the ACM

ns

t_SUAACM

t_HAACM

t_SUEACM

t_HEACM

ns

t_MPWARACM

Asynchronous Reset Minimum Pulse Width for the 10.00

ACM

ns

t_REMARACM

t_RECARACM

t_MPWCLKACM

t_FMAXCLKACM

Asynchronous Reset Removal time for the ACM

Asynchronous Reset Recovery time for the ACM

Clock Minimum Pulse Width for the ACM

lock Maximum Frequency for the ACM

12.98

45.00

10.00

14.79

45.00

10.00

17.38

45.00

10.00

ns

MHz

2-126

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Analog Quad ACM Description

Table 2-53 maps out the ACM space associated with configuration of the Analog Quads within the

Analog Block. Table 2-53 shows the byte assignment within each quad and the function of each bit

within each byte. Subsequent tables will explain each bit setting and how it corresponds to a

particular configuration. After 3.3 V and 1.5 V are applied to Fusion, Analog Quad configuration

registers are loaded with default settings until the initialization and configuration state machine

changes them to user-defined settings.

Table 2-53 • Analog Quad ACM Byte Assignment

Byte

Bit

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

Signal (Bx)

B0[0]

B0[1]

B0[2]

B0[3]

B0[4]

B0[5]

B0[6]

B0[7]

B1[0]

B1[1]

B1[2]

B1[3]

B1[4]

B1[5]

B1[6]

B1[7]

B2[0]

Function

Default Setting

Byte 0

(AV)

Scaling factor control – prescaler Highest voltage range

Analog MUX select

Prescaler

Off

Current monitor switch

Direct analog input switch

Selects V-pad polarity

Prescaler op amp mode

Off

Positive

Power-down

Byte 1

(AC)

Scaling factor control – prescaler Highest voltage range

Analog MUX select

Prescaler

Direct analog input switch

Selects C-pad polarity

Off

Positive

Power-down

Prescaler op amp mode

Byte 2

(AG)

Internal

monitor

chip

temperature Off

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

B2[1]

B2[2]

B2[3]

B2[4]

B2[5]

B2[6]

B2[7]

B3[0]

B3[1]

B3[2]

B3[3]

B3[4]

B3[5]

B3[6]

B3[7]

Spare

–

Current drive control

Lowest current

Spare

–

Spare

–

Selects G-pad polarity

Selects low/high drive

Positive

Low drive

Byte 3

(AT)

Scaling factor control – prescaler Highest voltage range

Analog MUX select

Prescaler

Direct analog input switch

Off

–

Prescaler op amp mode

Power-down

Preliminary v1.7

2-127

Device Architecture

Table 2-54 details the settings available to control the prescaler values of the AV, AC, and AT pins.

Note that the AT pin has a reduced number of available prescaler values.

Table 2-54 • Prescaler Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)

Scaling Factor, LSB for an 8-Bit LSB for a 10-Bit LSB for a 12-Bit

Control Lines

Bx[2:0]

Pad to ADC

Input

Conversion²

(mV)

Conversion²

(mV)

Conversion²

(mV)

Full-Scale

Voltage

Range

Name

000 ¹

0.15625

0.3125

0.625

1.25

64

32

16

8

16

8

4

2

16.368 V

8.184 V

16 V

8 V

001

010 ¹

011

4

1

4.092 V

4 V

2

0.5

2.046 V

2 V

100

2.5

4

1

0.25

0.125

0.0625

0.03125

1.023 V

1 V

101

5.0

2

0.5

0.25

0.125

0.5115 V

0.25575 V

0.127875 V

0.5 V

0.25 V

0.125 V

110

10.0

1

111

20.0

0.5

Notes:

1. These are the only valid ranges for the Temperature Monitor Block Prescaler.

2. LSB voltage equivalences assume VAREF = 2.56 V.

Table 2-55 details the settings available to control the MUX within each of the AV, AC, and AT

circuits. This MUX determines whether the signal routed to the ADC is the direct analog input,

prescaled signal, or output of either the Current Monitor Block or the Temperature Monitor Block.

Table 2-55 • Analog Multiplexer Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)

Control Lines Bx[4]

Control Lines Bx[3]

ADC Connected To

0

1

0

1

0

1

Prescaler

Direct input

Current amplifier temperature monitor

Not valid

Table 2-56 details the settings available to control the Direct Analog Input switch for the AV, AC,

and AT pins.

Table 2-56 • Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)

Control Lines Bx[5]

Direct Input Switch

0

1

Off

On

Table 2-57 details the settings available to control the polarity of the signals coming to the AV, AC,

and AT pins. Note that the only valid setting for the AT pin is logic 0 to support positive voltages.

Table 2-57 • Voltage Polarity Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)*

Control Lines Bx[6]

Input Signal Polarity

Positive

0

1

Negative

Note: *The B3[6] signal for the AT pad should be kept at logic 0 to accept only positive voltages.

2-128

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-58 details the settings available to either power down or enable the prescaler associated

with the analog inputs AV, AC, and AT.

Table 2-58 • Prescaler Op Amp Power-Down Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)

Control Lines Bx[7]

Prescaler Op Amp

Power-down

0

1

Operational

Table 2-59 details the settings available to enable the Current Monitor Block associated with the AC

pin.

Table 2-59 • Current Monitor Input Switch Control Truth Table—AV (x = 0)

Control Lines B0[4]

Current Monitor Input Switch

0

1

Off

On

Table 2-60 details the settings available to configure the drive strength of the gate drive when not

in high-drive mode.

Table 2-60 • Low-Drive Gate Driver Current Truth Table (AG)

Control Lines B2[3]

Control Lines B2[2]

Current (µA)

0

1

0

1

0

1

3

10

30

Table 2-61 details the settings available to set the polarity of the gate driver (either p-channel- or

n-channel-type devices).

Table 2-61 • Gate Driver Polarity Truth Table (AG)

Control Lines B2[6]

Gate Driver Polarity

Positive

0

1

Negative

Table 2-62 details the settings available to turn on the Gate Driver and set whether high-drive

mode is on or off.

Table 2-62 • Gate Driver Control Truth Table (AG)

Control Lines B2[7]

GDON

Gate Driver

Off

0

1

0

1

0

1

Low drive on

Off

High drive on

Table 2-63 details the settings available to turn on and off the chip internal temperature monitor.

Table 2-63 • Internal Temperature Monitor Control Truth Table

Control Lines B2[0]

PDTMB

Chip Internal Temperature Monitor

0

1

0

1

Off

On

Preliminary v1.7

2-129

Device Architecture

User I/Os

Introduction

Fusion devices feature a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V,

2.5 V, and 3.3 V) through a bank-selectable voltage. Table 2-65, Table 2-66, Table 2-67, and

Table 2-68 on page 2-133 show the voltages and the compatible I/O standards. I/Os provide

programmable slew rates, drive strengths, weak pull-up, and weak pull-down circuits. 3.3 V PCI and

3.3 V PCI-X are 5 V–tolerant. See the "5 V Input Tolerance" section on page 2-143 for possible

implementations of 5 V tolerance.

All I/Os are in a known state during power-up, and any power-up sequence is allowed without

current impact. Refer to the "I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)" section on page 3-5 for more information. In low power standby or

sleep mode (V_CCis OFF, V_CC33Ais ON, V_CCIis ON) or when the resource is not used, digital inputs are

tristated, digital outputs are tristated, and digital bibufs (input/output) are tristated.

I/O Tile

The Fusion I/O tile provides a flexible, programmable structure for implementing a large number of

I/O standards. In addition, the registers available in the I/O tile in selected I/O banks can be used to

support high-performance register inputs and outputs, with register enable if desired (Figure 2-91

on page 2-131). The registers can also be used to support the JESD-79C DDR standard within the I/O

structure (see the "Double Data Rate (DDR) Support" section on page 2-137 for more information).

As depicted in Figure 2-92 on page 2-136, all I/O registers share one CLR port. The output register

and output enable register share one CLK port. Refer to the "I/O Registers" section on page 2-136

for more information.

I/O Banks and I/O Standards Compatibility

The digital I/Os are grouped into I/O voltage banks. There are three digital I/O banks on the AFS090

and AFS250 devices and four digital I/O banks on the AFS600 and AFS1500 devices. Figure 2-105 on

page 2-158 and Figure 2-106 on page 2-158 show the bank configuration by device. The north side

of the I/O in the AFS600 and AFS1500 devices comprises two banks of Actel Pro I/Os. The Actel Pro

I/Os support a wide number of voltage-referenced I/O standards in addition to the multitude of

single-ended and differential I/O standards common throughout all Actel digital I/Os. Each I/O

voltage bank has dedicated I/O supply and ground voltages (V_CCI/GNDQ for input buffers and

V_CCI/GND for output buffers). Because of these dedicated supplies, only I/Os with compatible

standards can be assigned to the same I/O voltage bank. Table 2-66 and Table 2-67 on page 2-132

show the required voltage compatibility values for each of these voltages.

For more information about I/O and global assignments to I/O banks, refer to the specific pin table

of the device in the "Package Pin Assignments" section on page 4-1 and the "User I/O Naming

Convention" section on page 2-157.

Each Pro I/O bank is divided into minibanks. Any user I/O in a V_REFminibank (a minibank is the

region of scope of a V_REFpin) can be configured as a V_REFpin (Figure 2-91 on page 2-131). Only one

V_REFpin is needed to control the entire V_REFminibank. The location and scope of the V_REF

minibanks can be determined by the I/O name. For details, see the "User I/O Naming Convention"

section on page 2-157.

Table 2-67 on page 2-132 shows the I/O standards supported by Fusion devices and the

corresponding voltage levels.

I/O standards are compatible if the following are true:

•

Their V_CCIvalues are identical.

If both of the standards need a V_REF, their V_REFvalues must be identical (Pro I/O only).

2-130

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

CCC

Bank 0

Bank 1

Up to five V_REF

minibanks within

an I/O bank

Common V_REF

signal for all I/Os

in V_REFminibanks

V_REFsignal scope is

between 8 and 18 I/Os.

If needed, the V_REFfor a given

minibank can be provided by

any I/O within the minibank.

I/O Pad

Figure 2-91 • Fusion Pro I/O Bank Detail Showing V_REFMinibanks (north side of AFS600 and AFS1500)

Table 2-64 • I/O Standards Supported by Bank Type

Differential I/O

Hot-

I/O Bank

Single-Ended I/O Standards

Standards

Voltage-Referenced

Swap

Standard I/O LVTTL/LVCMOS 3.3 V, LVCMOS –

2.5 V / 1.8 V / 1.5 V, LVCMOS

2.5/5.0 V

–

Yes

Advanced I/O LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL and LVDS

2.5 V / 1.8 V / 1.5 V, LVCMOS

–

2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X

Pro I/O

LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL and LVDS GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, Yes

2.5 V / 1.8 V / 1.5 V, LVCMOS

2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X

HSTL Class I and II, SSTL2 Class I and

II, SSTL3 Class I and II

Preliminary v1.7

2-131

Device Architecture

Table 2-65 • I/O Bank Support by Device

I/O Bank

AFS090

AFS250

AFS600

AFS1500

Standard I/O

Advanced I/O

Pro I/O

N

E, W

–

N

E, W

–

E, W

N

–

E, W

N

Analog Quad

S

Note: E = East side of the device

W = West side of the device

N = North side of the device

S = South side of the device

Table 2-66 • Fusion V_CCIVoltages and Compatible Standards

_CCI(typical) Compatible Standards

LVTTL/LVCMOS 3.3, PCI 3.3, SSTL3 (Class I and II),* GTL+ 3.3, GTL 3.3,* LVPECL

V

3.3 V

2.5 V

1.8 V

1.5 V

LVCMOS 2.5, LVCMOS 2.5/5.0, SSTL2 (Class I and II),* GTL+ 2.5,* GTL 2.5,* LVDS, BLVDS, M-LVDS

LVCMOS 1.8

LVCMOS 1.5, HSTL (Class I),* HSTL (Class II)*

Note: *I/O standard supported by Pro I/O banks.

Table 2-67 • Fusion V_REFVoltages and Compatible Standards*

V_REF(typical)

Compatible Standards

1.5 V

1.25 V

1.0 V

0.8 V

0.75 V

SSTL3 (Class I and II)

SSTL2 (Class I and II)

GTL+ 2.5, GTL+ 3.3

GTL 2.5, GTL 3.3

HSTL (Class I), HSTL (Class II)

Note: *I/O standards supported by Pro I/O banks.

2-132

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-68 • Fusion Standard and Advanced I/O Features

3.3 V

2.5 V

–

0.80 V

1.00 V

1.50 V

–

0.80 V

1.00 V

1.25 V

–

1.8 V

1.5 V

–

0.75 V

Note: White box: Allowable I/O standard combinations

Gray box: Illegal I/O standard combinations

Preliminary v1.7

2-133

Device Architecture

Features Supported on Pro I/Os

Table 2-69 lists all features supported by transmitter/receiver for single-ended and differential

I/Os.

Table 2-69 • Fusion Pro I/O Features

Feature

Single-ended and voltage- • Hot insertion in every mode except PCI or 5 V input tolerant (these modes

Description

referenced transmitter

features

use clamp diodes and do not allow hot insertion)

Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.

Weak pull-up and pull-down

•

Two slew rates

Skew between output buffer enable/disable time: 2 ns delay (rising edge)

and 0 ns delay (falling edge); see "Selectable Skew between Output Buffer

Enable/Disable Time" on page 2-148 for more information

•

Five drive strengths

5 V–tolerant receiver ("5 V Input Tolerance" section on page 2-143)

LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs ("5 V Output

Tolerance" section on page 2-146)

•

High performance (Table 2-73 on page 2-141)

Single-ended receiver features • Schmitt trigger option

•

ESD protection

Programmable delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns

with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)

•

High performance (Table 2-73 on page 2-141)

Separate ground planes, GND/GNDQ, for input buffers only to avoid

output-induced noise in the input circuitry

Voltage-referenced

differential receiver features

•

Programmable Delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns

with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)

•

High performance (Table 2-73 on page 2-141)

Separate ground planes, GND/GNDQ, for input buffers only to avoid

output-induced noise in the input circuitry

CMOS-style

M-LVDS, or LVPECL

transmitter

LVDS,

BLVDS, • Two I/Os and external resistors are used to provide a CMOS-style LVDS,

BLVDS, M-LVDS, or LVPECL transmitter solution.

•

Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.

Weak pull-up and pull-down

Fast slew rate

LVDS/LVPECL differential

receiver features

ESD protection

High performance (Table 2-73 on page 2-141)

Programmable delay: 0.625 ns with '000' setting, 6.575 ns with '111'

setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)

•

Separate input buffer ground and power planes to avoid output-induced

noise in the input circuitry

2-134

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-70 • Maximum I/O Frequency for Single-Ended, Voltage-Referenced, and Differential I/Os;

All I/O Bank Types (maximum drive strength and high slew selected)

Specification

Performance Up To

200 MHz

250 MHz

200 MHz

130 MHz

200 MHz

300 MHz

350 MHz

300 MHz

LVTTL/LVCMOS 3.3 V

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI

PCI-X

HSTL-I

HSTL-II

SSTL2-I

SSTL2-II

SSTL3-I

SSTL3-II

GTL+ 3.3 V

GTL+ 2.5 V

GTL 3.3 V

GTL 2.5 V

LVDS

LVPECL

Preliminary v1.7

2-135

Device Architecture

I/O Registers

Each I/O module contains several input, output, and enable registers. Refer to Figure 2-92 for a

simplified representation of the I/O block.

The number of input registers is selected by a set of switches (not shown in Figure 2-92) between

registers to implement single or differential data transmission to and from the FPGA core. The

Designer software sets these switches for the user.

A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used.

Input register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The

I/O register combining must satisfy some rules.

1

I/O / Q0

2

Input

Reg

Input

Reg

Y

Pull-Up/Down

Resistor Control

CLR/PRE

To FPGA Core

3

I/O / Q1

Input

Reg

PAD

ICE

CLR/PRE

I/O / ICLK

Signal Drive Strength

and Slew-Rate Control

E = Enable Pin

A

4

I/O / D0

Output

Reg

OCE

ICE

From FPGA Core

CLR/PRE

5

I/O / D1 / ICE

Output

Reg

CLR/PRE

I/O / OCLK

I/O / OE

6

Output

Enable

Reg

OCE

CLR/PRE

I/O / CLR or I/O / PRE / OCE

Note: Fusion I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section

on page 2-137 for more information).

Figure 2-92 • I/O Block Logical Representation

2-136

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Double Data Rate (DDR) Support

Fusion Pro I/Os support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on

every transition of the clock signal. Clock and data lines have identical bandwidths and signal

integrity requirements, making it very efficient for implementing very high-speed systems.

DDR interfaces can be implemented using HSTL, SSTL, LVDS, and LVPECL I/O standards. In addition,

high-speed DDR interfaces can be implemented using LVDS I/O.

Input Support for DDR

The basic structure to support a DDR input is shown in Figure 2-93. Three input registers are used to

capture incoming data, which is presented to the core on each rising edge of the I/O register clock.

Each I/O tile on Fusion devices supports DDR inputs.

Output Support for DDR

The basic DDR output structure is shown in Figure 2-94 on page 2-138. New data is presented to

the output every half clock cycle. Note: DDR macros and I/O registers do not require additional

routing. The combiner automatically recognizes the DDR macro and pushes its registers to the I/O

register area at the edge of the chip. The routing delay from the I/O registers to the I/O buffers is

already taken into account in the DDR macro.

Refer to the Actel application note Using DDR for Fusion Devices for more information.

Input DDR

A

D

Out_QF

(to core)

Data

INBUF

FF1

E

B

C

Out_QR

(to core)

CLK

CLR

CLKBUF

INBUF

FF2

DDR_IN

Figure 2-93 • DDR Input Register Support in Fusion Devices

Preliminary v1.7

2-137

Device Architecture

A

Data_F

(from core)

FF1

FF2

Out

B

C

D

0

1

CLK

E

CLKBUF

OUTBUF

Data_R

(from core)

B

C

CLR

INBUF

DDR_OUT

Figure 2-94 • DDR Output Support in Fusion Devices

2-138

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Hot-Swap Support

Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card

in (or from) a powered-up system. The levels of hot-swap support and examples of related

applications are described in Table 2-71. The I/Os also need to be configured in hot insertion mode

if hot plugging compliance is required.

Table 2-71 • Levels of Hot-Swap Support

Device

Example of

Hot

Power

Card

Circuitry

Application with

Swapping

Level

Applied

Ground

Connected Cards that Contain Compliance of

Description to Device Bus State Connection to Bus Pins

Fusion Devices

1

2

3

Cold-swap

No

Yes

–

System and card

with Actel FPGA chip can but do not

are powered down, have to be set to

Compliant I/Os

then card gets

hot insertion

plugged into system, mode.

then power supplies

are turned on for

system but not for

FPGA on card.

Hot-swap

while reset

Held in

Must be

–

In PCI hot plug

specification, reset can but do not

Compliant I/Os

reset state made and

maintained

for 1 ms

control circuitry

isolates the card

busses until the card mode.

supplies are at their

nominal operating

have to be set to

hot insertion

before,

during, and

after

insertion/

removal

levels and stable.

Hot-swap

while bus

idle

Held idle Same as Level Must

(no

ongoing

I/O

Board bus shared

with card bus is

Compliant with

cards with two

2

remain

glitch-free "frozen," and there levels of

during is no toggling staging. I/Os

processes

during

insertion/re

moval)

power-up activity on bus. It is have to be set to

or power- critical that the logic hot insertion

down

states set on the bus mode.

signal do not get

disturbed during

card

insertion/removal.

4

Hot-swap

on an active

bus

Yes

Bus may

have active 2

I/O

Same as Level Same as

Level 3

There is activity on Compliant with

the system bus, and cards with two

it is critical that the levels of

processes

ongoing,

but device

being

logic states set on

the bus signal do not have to be set to

get disturbed during hot insertion

staging. I/Os

card

mode.

inserted or

removed

must be

idle.

insertion/removal.

Preliminary v1.7

2-139

Device Architecture

For Fusion devices requiring Level 3 and/or Level 4 compliance, the board drivers connected to

Fusion I/Os need to have 10 kΩ (or lower) output drive resistance at hot insertion, and 1 kΩ (or

lower) output drive resistance at hot removal. This is the resistance of the transmitter sending a

signal to the Fusion I/O, and no additional resistance is needed on the board. If that cannot be

assured, three levels of staging can be used to meet Level 3 and/or Level 4 compliance. Cards with

two levels of staging should have the following sequence:

1. Grounds

2. Powers, I/Os, other pins

Cold-Sparing Support

Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically

connected to the system that is in operation. This means that all input buffers of the subsystem

must present very high input impedance with no power applied so as not to disturb the operating

portion of the system.

Pro I/O banks and standard I/O banks fully support cold-sparing.

For Pro I/O banks, standards such as PCI that require I/O clamp diodes, can also achieve cold-sparing

compliance, since clamp diodes get disconnected internally when the supplies are at 0 V.

For Advanced I/O banks, since the I/O clamp diode is always active, cold-sparing can be

accomplished either by employing a bus switch to isolate the device I/Os from the rest of the system

or by driving each advanced I/O pin to 0 V.

If Standard I/O banks are used in applications requiring cold-sparing, a discharge path from the

power supply to ground should be provided. This can be done with a discharge resistor or a

switched resistor. This is necessary because the standard I/O buffers do not have built-in I/O clamp

diodes.

If a resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a

given power supply on the board (this decoupling capacitor is in parallel with the resistor). The RC

time constant should ensure full discharge of supplies before cold-sparing functionality is required.

The resistor is necessary to ensure that the power pins are discharged to ground every time there is

an interruption of power to the device.

I/O cold-sparing may add additional current if the pin is configured with either a pull-up or pull

down resistor and driven in the opposite direction. A small static current is induced on each IO pin

when the pin is driven to a voltage opposite to the weak pull resistor. The current is equal to the

voltage drop across the input pin divided by the pull resistor. Please refer to Table 2-92 on

page 2-169, Table 2-93 on page 2-169, and Table 2-94 on page 2-171 for the specific pull resistor

value for the corresponding I/O standard.

For example, assuming an LVTTL 3.3 V input pin is configured with a weak Pull-up resistor, a current

will flow through the pull-up resistor if the input pin is driven low. For an LVTTL 3.3 V, pull-up

resistor is ~45 kΩ and the resulting current is equal to 3.3 V / 45 kΩ = 73 µA for the I/O pin. This is

true also when a weak pull-down is chosen and the input pin is driven high. Avoiding this current

can be done by driving the input low when a weak pull-down resistor is used, and driving it high

when a weak pull-up resistor is used.

In Active and Static modes, this current draw can occur in the following cases:

•

Input buffers with pull-up, driven low

Input buffers with pull-down, driven high

Bidirectional buffers with pull-up, driven low

Bidirectional buffers with pull-down, driven high

Output buffers with pull-up, driven low

Output buffers with pull-down, driven high

Tristate buffers with pull-up, driven low

Tristate buffers with pull-down, driven high

2-140

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Electrostatic Discharge (ESD) Protection

Fusion devices are tested per JEDEC Standard JESD22-A114-B.

Fusion devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all

device pads against damage from ESD as well as from excessive voltage transients.

Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its

negative (N) side connected to V_CCI. The second diode has its P side connected to GND and its N side

connected to the pad. During operation, these diodes are normally biased in the Off state, except

when transient voltage is significantly above V_CCIor below GND levels.

By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 2-72 on

page 2-141 and Table 2-73 on page 2-141 for more information about I/O standards and the clamp

diode.

The second diode is always connected to the pad, regardless of the I/O configuration selected.

Table 2-72 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance Capabilities

Clamp Diode

Hot Insertion

5 V Input Tolerance¹

Standard Advanced Standard Advanced Standard Advanced

Input

Buffer

Output

Buffer

I/O Assignment

3.3 V LVTTL/LVCMOS

3.3 V PCI, 3.3 V PCI-X

LVCMOS 2.5 V

I/O

No

N/A

No

N/A

I/O

Yes

I/O

Yes

N/A

Yes

N/A

I/O

No

I/O

Yes¹

N/A

Yes¹

No

I/O

Yes¹

Yes²

No

Enabled/Disabled

LVCMOS 2.5 V / 5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

No

Differential,

N/A

No

LVDS/BLVDS/M-LVDS/

LVPECL ³

Notes:

1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.

2. Can be implemented with an external resistor and an internal clamp diode.

3. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers.

Table 2-73 • Fusion Pro I/O – Hot-Swap and 5 V Input Tolerance Capabilities

Clamp

Diode

Hot

5 V Input

I/O Assignment

Insertion Tolerance Input Buffer Output Buffer

3.3 V LVTTL/LVCMOS

3.3 V PCI, 3.3 V PCI-X

LVCMOS 2.5 V ³

No

Yes

No

Yes

No

Yes

No

Yes¹

No

Enabled/Disabled

Yes

No

LVCMOS 2.5 V / 5.0 V ³

Yes²

LVCMOS 1.8 V

Yes

No

LVCMOS 1.5 V

No

Voltage-Referenced Input Buffer

No

Preliminary v1.7

2-141

Device Architecture

Table 2-73 • Fusion Pro I/O – Hot-Swap and 5 V Input Tolerance Capabilities

Clamp

Diode

Hot

5 V Input

I/O Assignment

Insertion Tolerance Input Buffer Output Buffer

Differential, LVDS/BLVDS/M-LVDS/LVPECL⁴

No

Yes No Enabled/Disabled

Notes:

1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.

2. Can be implemented with an external resistor and an internal clamp diode.

3. In the SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User's Guide, select

the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5

V I/O standard.

4. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers.

2-142

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

5 V Input Tolerance

I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V / 5 V, and

LVCMOS 2.5 V configurations are used (see Table 2-74 on page 2-146 for more details). There are

four recommended solutions (see Figure 2-95 to Figure 2-98 on page 2-146 for details of board and

macro setups) to achieve 5 V receiver tolerance. All the solutions meet a common requirement of

limiting the voltage at the input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is

3.6 V, and any voltage above 3.6 V may cause long-term gate oxide failures.

Solution 1

The board-level design needs to ensure that the reflected waveform at the pad does not exceed

the limits provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.

This scheme will also work for a 3.3 V PCI / PCI-X configuration, but the internal diode should not

be used for clamping, and the voltage must be limited by the two external resistors, as explained

below. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V =

4 V.

The following are some examples of possible resistor values (based on a simplified simulation

model with no line effects and 10 Ω transmitter output resistance, where Rtx_out_high = (V_CCI

–

V_OH) / I_OH, Rtx_out_low = V_OL/ I_OL).

Example 1 (high speed, high current):

Rtx_out_high = Rtx_out_low = 10 Ω

R1 = 36 Ω ( 5%), P(r1)min = 0.069 Ω

R2 = 82 Ω ( 5%), P(r2)min = 0.158 Ω

Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 + 10) = 45.04 mA

t_RISE= t_FALL= 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin)

t_RISE= t_FALL= 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin)

Example 2 (low–medium speed, medium current):

Rtx_out_high = Rtx_out_low = 10 Ω

R1 = 220 Ω ( 5%), P(r1)min = 0.018 Ω

R2 = 390 Ω ( 5%), P(r2)min = 0.032 Ω

Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 + 10) = 9.17 mA

t

_RISE= t_FALL= 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin)

_RISE= t_FALL= 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin)

t

Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the

voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This

range of Vin_dc(rx) must be assured for any combination of transmitter supply (5 V 0.5 V),

transmitter output resistance, and board resistor tolerances.

Preliminary v1.7

2-143

Device Architecture

Temporary overshoots are allowed according to Table 3-4 on page 3-4.

Solution 1

Fusion I/O Input

On-Chip

Off-Chip

5.5 V

3.3 V

Rext1

Rext2

Requires two board resistors,

LVCMOS 3.3 V I/Os

Figure 2-95 • Solution 1

Solution 2

The board-level design must ensure that the reflected waveform at the pad does not exceed limits

provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.

This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be

used for clamping, and the voltage must be limited by the external resistors and Zener, as shown in

Figure 2-96. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7

V = 4 V.

Solution 2

Fusion I/O Input

Off-Chip On-Chip

3.3 V

5.5 V

Rext1

Zener

3.3 V

Requires one board resistor, one

Zener 3.3 V diode, LVCMOS 3.3 V I/Os

Figure 2-96 • Solution 2

2-144

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Solution 3

The board-level design must ensure that the reflected waveform at the pad does not exceed limits

provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.

This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be

used for clamping, and the voltage must be limited by the bus switch, as shown in Figure 2-97.

Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

Solution 3

Fusion I/O Input

Off-Chip

Bus

On-Chip

3.3 V

Switch

IDTQS32X23

5.5 V

Requires a bus switch on the board,

LVTTL/LVCMOS 3.3 V I/Os.

Figure 2-97 • Solution 3

Preliminary v1.7

2-145

Device Architecture

Solution 4

Fusion I/O Input

Off-Chip

5.5 V

On-Chip

2.5 V On-Chip

2.5 V

Clamp

Diode

Rext1

Requires one board resistor.

Available for LVCMOS 2.5 V / 5.0 V.

Figure 2-98 • Solution 4

Table 2-74 • Comparison Table for 5 V–Compliant Receiver Scheme

Scheme

Board Components

Two resistors

Speed

Current Limitations

1

2

3

4

Low to high¹Limited by transmitter's drive strength

Resistor and Zener 3.3 V

Bus switch

Minimum resistor value²

R = 47 Ω at T_J= 70°C

R = 150 Ω at T_J= 85°C

R = 420 Ω at T_J= 100°C

Medium

High

Limited by transmitter's drive strength

N/A

Medium

Maximum diode current at 100% duty cycle, signal

constantly at '1'

52.7 mA at T_J=70°C / 10-year lifetime

16.5 mA at T_J= 85°C / 10-year lifetime

5.9 mA at T_J= 100°C / 10-year lifetime

For duty cycles other than 100%, the currents can be

increased by a factor = 1 / (duty cycle).

Example: 20% duty cycle at 70°C

Maximum current = (1 / 0.2) * 52.7 mA = 5 * 52.7 mA =

263.5 mA

Notes:

1. Speed and current consumption increase as the board resistance values decrease.

2. Resistor values ensure I/O diode long-term reliability.

5 V Output Tolerance

Fusion I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is

also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor would pull the I/O

pad voltage beyond the 3.6 V absolute maximum value and consequently cause damage to the I/O.

When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, Fusion I/Os can directly drive signals into 5 V TTL

receivers. In fact, V_OL= 0.4 V and V_OH= 2.4 V in both 3.3 V LVTTL and 3.3 V LVCMOS modes exceed

2-146

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

the V_IL= 0.8 V and V_IH= 2 V level requirements of 5 V TTL receivers. Therefore, level '1' and level '0'

will be recognized correctly by 5 V TTL receivers.

Simultaneously Switching Outputs and PCB Layout

•

Simultaneously switching outputs (SSOs) can produce signal integrity problems on adjacent

signals that are not part of the SSO bus. Both inductive and capacitive coupling parasitics of

bond wires inside packages and of traces on PCBs will transfer noise from SSO busses onto

signals adjacent to those busses. Additionally, SSOs can produce ground bounce noise and

V_CCIdip noise. These two noise types are caused by rapidly changing currents through GND

and V_CCIpackage pin inductances during switching activities:

•

Ground bounce noise voltage = L(GND) * di/dt

V_CCIdip noise voltage = L(V_CCI) * di/dt

Any group of four or more input pins switching on the same clock edge is considered an SSO bus.

The shielding should be done both on the board and inside the package unless otherwise

described.

In-package shielding can be achieved in several ways; the required shielding will vary depending

on whether pins next to SSO bus are LVTTL/LVCMOS inputs, LVTTL/LVCMOS outputs, or

GTL/SSTL/HSTL/LVDS/LVPECL inputs and outputs. Board traces in the vicinity of the SSO bus have to

be adequately shielded from mutual coupling and inductive noise that can be generated by the

SSO bus. Also, noise generated by the SSO bus needs to be reduced inside the package.

PCBs perform an important function in feeding stable supply voltages to the IC and, at the same

time, maintaining signal integrity between devices.

Key issues that need to considered are as follows:

•

Power and ground plane design and decoupling network design

Transmission line reflections and terminations

Preliminary v1.7

2-147

Device Architecture

Selectable Skew between Output Buffer Enable/Disable Time

The configurable skew block is used to delay the output buffer assertion (enable) without affecting

deassertion (disable) time.

Output Enable

ENABLE (IN)

(from FPGA core)

ENABLE (OUT)

MUX

Skew Circuit

I/O Output

Buffers

Skew Select

Figure 2-99 • Block Diagram of Output Enable Path

ENABLE (IN)

ENABLE (OUT)

Less than

0.1 ns

Less than

0.1 ns

Figure 2-100 • Timing Diagram (option1: bypasses skew circuit)

ENABLE (IN)

ENABLE (OUT)

1.2 ns

(typical)

Less than

0.1 ns

Figure 2-101 • Timing Diagram (option 2: enables skew circuit)

At the system level, the skew circuit can be used in applications where transmission activities on

bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing

margin that can prevent bus contention and subsequent data loss or transmitter overstress due to

transmitter-to-transmitter current shorts. Figure 2-102 presents an example of the skew circuit

2-148

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

implementation in a bidirectional communication system. Figure 2-103 shows how bus contention

is created, and Figure 2-104 on page 2-150 shows how it can be avoided with the skew circuit.

Transmitter

ENABLE/

DISABLE

Transmitter 1: Fusion I/O

Transmitter 2: Generic I/O

Routing

Skew or

Routing

EN(b1)

EN(b2)

EN(r1)

ENABLE(t2)

Bypass

Skew

Delay (t1)

Delay (t2)

ENABLE(t1)

Bidirectional Data Bus

Figure 2-102 • Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using Fusion

Devices

EN (b1)

EN (b2)

ENABLE (r1)

ENABLE (t1)

Transmitter 1: OFF

ENABLE (t2)

Transmitter 1: OFF

Transmitter 1: ON

Transmitter 2: ON

Transmitter 2: OFF

Bus

Contention

Figure 2-103 • Timing Diagram (bypasses skew circuit)

Preliminary v1.7

2-149

Device Architecture

EN (b1)

EN (b2)

ENABLE (t1)

Transmitter 1: OFF

ENABLE (t2)

Transmitter 1: OFF

Transmitter 1: ON

Transmitter 2: ON

Transmitter 2: OFF

Result: No Bus Contention

Figure 2-104 • Timing Diagram (with skew circuit selected)

Weak Pull-Up and Weak Pull-Down Resistors

Fusion devices support optional weak pull-up and pull-down resistors for each I/O pin. When the

I/O is pulled up, it is connected to the V_CCIof its corresponding I/O bank. When it is pulled down, it

is connected to GND. Refer to Table 2-94 on page 2-171 for more information.

Slew Rate Control and Drive Strength

Fusion devices support output slew rate control: high and low. The high slew rate option is

recommended to minimize the propagation delay. This high-speed option may introduce noise into

the system if appropriate signal integrity measures are not adopted. Selecting a low slew rate

reduces this kind of noise but adds some delays in the system. Low slew rate is recommended when

bus transients are expected. Drive strength should also be selected according to the design

requirements and noise immunity of the system.

The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V,

LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O

standards have a high output slew rate by default.

For Fusion slew rate and drive strength specifications, refer to the appropriate I/O bank table:

•

Fusion Standard I/O (Table 2-75 on page 2-151)

Fusion Advanced I/O (Table 2-76 on page 2-151)

Fusion Pro I/O (Table 2-77 on page 2-151)

Table 2-79 on page 2-153 lists the default values for the above selectable I/O attributes as well as

those that are preset for each I/O standard.

2-150

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Refer to Table 2-75, Table 2-76, and Table 2-77 on page 2-151 for SLEW and OUT_DRIVE settings.

Table 2-78 on page 2-152 lists the I/O default attributes. Table 2-79 on page 2-153 lists the voltages

for the supported I/O standards.

Table 2-75 • Fusion Standard I/O Standards—OUT_DRIVE Settings

OUT_DRIVE (mA)

I/O Standards

2

✓

–

4

✓

–

6

✓

–

8

✓

–

Slew

LVTTL/LVCMOS 3.3 V

High

Low

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V

–

Table 2-76 • Fusion Advanced I/O Standards—SLEW and OUT_DRIVE Settings

OUT_DRIVE (mA)

I/O Standards

2

4

6

✓

–

8

✓

–

12

✓

–

16

✓

–

Slew

High

LVTTL/LVCMOS 3.3 V

Low

✓

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V

High

Low

–

Table 2-77 • Fusion Pro I/O Standards—SLEW and OUT_DRIVE Settings

OUT_DRIVE (mA)

I/O Standards

2

4

6

8

12

✓

16

✓

–

24

✓

–

Slew

High

LVTTL/LVCMOS 3.3 V

Low

✓

LVCMOS 2.5 V

High

LVCMOS 2.5 V/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

–

Preliminary v1.7

2-151

Device Architecture

Table 2-78 • Fusion Pro I/O Default Attributes

SLEW

OUT_DRIVE

I/O Standards

(output only)

LVTTL/LVCMOS Refer to the following

Refer to the following

tables for more

information:

Off None 35 pF

–

Off

0

Off

3.3 V

tables for more

information:

LVCMOS 2.5 V

Off None 35 pF

–

Off

0

Off

Table 2-75 on page 2-151 Table 2-75 on page 2-151

Table 2-76 on page 2-151 Table 2-76 on page 2-151

Table 2-77 on page 2-151 Table 2-77 on page 2-151

LVCMOS

2.5/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI (3.3 V)

Off None 35 pF

Off None 10 pF

Off None 20 pF

Off None 30 pF

–

Off

0

Off

PCI-X (3.3 V)

GTL+ (3.3 V)

GTL+ (2.5 V)

GTL (3.3 V)

GTL (2.5 V)

HSTL Class I

HSTL Class II

SSTL2

Class I and II

SSTL3

Class I and II

Off None 30 pF

–

Off

0

Off

LVDS, BLVDS,

M-LVDS

Off None

0 pF

LVPECL

2-152

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-79 • Fusion Pro I/O Supported Standards and Corresponding V_REFand V_TTVoltages

Input/Output Supply Input Reference Voltage Board Termination Voltage

I/O Standard

Voltage (V_{CCI_TYP}

)

(V_{REF_TYP}

)

(V_{TT_TYP})

LVTTL/LVCMOS 3.3 V

LVCMOS 2.5 V

3.30 V

–

2.50 V

LVCMOS 2.5 V / 5.0 V

Input

2.50 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI 3.3 V

1.80 V

1.50 V

3.30 V

2.50 V

3.30 V

2.50 V

1.50 V

3.30 V

2.50 V

3.30 V

–

PCI-X 3.3 V

GTL+ 3.3 V

–

1.00 V

0.80 V

0.75 V

1.50 V

1.25 V

–

1.50 V

1.20 V

0.75 V

1.50 V

1.25 V

–

GTL+ 2.5 V

GTL 3.3 V

GTL 2.5 V

HSTL Class I

HSTL Class II

SSTL3 Class I

SSTL3 Class II

SSTL2 Class I

SSTL2 Class II

LVDS, BLVDS, M-LVDS

LVPECL

–

Preliminary v1.7

2-153

Device Architecture

I/O Software Support

In the Fusion development software, default settings have been defined for the various I/O

standards supported. Changes can be made to the default settings via the use of attributes;

however, not all I/O attributes are applicable for all I/O standards. Table 2-80 and Table 2-81 list the

valid I/O attributes that can be manipulated by the user for each I/O standard.

Single-ended I/O standards in Fusion support up to five different drive strengths.

Table 2-80 • Fusion Standard and Advanced I/O Attributes vs. I/O Standard Applications

SLEW

(output OUT_DRIVE (all macros

only) (output only) with OE)* RES_PULL (output only) COMBINE_REGISTER

SKEW

OUT_LOAD

I/O Standards

LVTTL/LVCMOS 3.3 V

✓

LVCMOS 2.5 V

LVCMOS 2.5/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI (3.3 V)

PCI-X (3.3 V)

✓

LVDS, BLVDS, M-LVDS

LVPECL

Note: *This does not apply to the north I/O bank on AFS090 and AFS250 devices.

Table 2-81 • Fusion Pro I/O Attributes vs. I/O Standard Applications

I/O Standards

LVTTL/LVCMOS 3.3 V

LVCMOS 2.5 V

LVCMOS 2.5/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI (3.3 V)

✓

3

✓

PCI-X (3.3 V)

3

✓

GTL+ (3.3 V)

3

✓

2-154

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-81 • Fusion Pro I/O Attributes vs. I/O Standard Applications (continued)

I/O Standards

GTL+ (2.5 V)

✓

GTL (3.3 V)

GTL (2.5 V)

HSTL Class I

HSTL Class II

SSTL2 Class I and II

SSTL3 Class I and II

LVDS, BLVDS, M-LVDS

LVPECL

Table 2-82 lists the default values for the above selectable I/O attributes as well as those that are

preset for each I/O standard. See Table 2-75, Table 2-76, and Table 2-77 on page 2-151 for SLEW and

OUT_DRIVE settings.

Preliminary v1.7

2-155

Device Architecture

Table 2-82 • I/O Default Attributes

I/O Standards

LVTTL/LVCMOS 3.3 V

LVCMOS 2.5 V

LVCMOS 2.5/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI (3.3 V)

SLEW (output only)

OUT_DRIVE (output only)

Refer to the following

tables for more

information:

Refer to the following

tables for more

information:

Off None

35 pF

10 pF

–

Table 2-75 on page 2-151 Table 2-75 on page 2-151

Table 2-76 on page 2-151 Table 2-76 on page 2-151

Table 2-77 on page 2-151 Table 2-77 on page 2-151

PCI-X (3.3 V)

LVDS, BLVDS, M-LVDS

LVPECL

–

2-156

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

User I/O Naming Convention

Due to the comprehensive and flexible nature of Fusion device user I/Os, a naming scheme is used

to show the details of the I/O (Figure 2-105 on page 2-158 and Figure 2-106 on page 2-158). The

name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential

I/Os.

I/O Nomenclature = Gmn/IOuxwByVz

Gmn is only used for I/Os that also have CCC access—i.e., global pins.

G

= Global

m

= Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C

(east middle), D (southeast corner), E (southwest corner), and F (west middle).

n

u

x

= Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0,

C1, or C2. Figure 2-22 on page 2-28 shows the three input pins per clock source MUX at CCC location m.

= I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise

direction.

= P (Positive) or N (Negative) for differential pairs, or R (Regular – single-ended) for the I/Os that support

single-ended and voltage-referenced I/O standards only. U (Positive-LVDS only) or V (Negative-LVDS

only) restrict the I/O differential pair from being selected as an LVPECL pair.

w

= D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are

bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the

pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not

bonded out. For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal.

Diagonal adjacency does not meet the requirements for a true differential pair.

B

y

= Bank

= Bank number (0–3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a

clockwise direction.

V

z

= Reference voltage

= Minibank number

Preliminary v1.7

2-157

Device Architecture

Standard I/O Bank

CCC

"A"

CCC

"B"

Bank 0

Bank 3

Bank 1

AFS090

AFS250

CCC/PLL

"F"

CCC

"C"

Bank 3

Bank 1

CCC

"E"

CCC

"D"

Bank 2 (analog)

Analog Quads

Figure 2-105 • Naming Conventions of Fusion Devices with Three Digital I/O Banks

Pro I/O Bank

CCC

"A"

CCC

"B"

Bank 0

Bank 1

Bank 4

Bank 2

AFS600

AFS1500

CCC/PLL

"F"

CCC/PLL

"C"

Bank 4

Bank 2

CCC

"E"

CCC

"D"

Bank 3 (analog)

Analog Quads

Figure 2-106 • Naming Conventions of Fusion Devices with Four I/O Banks

2-158

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

LVPECL (Pro IO banks)

t_PD= 0.56 ns

t_PD= 0.49 ns

t_Dp= 1.60 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

LVTTL/LVCMOS 3.3 V (Pro I/O banks)

Output drive strength = 12 mA

High slew rate

t_DP= 2.74 ns

t_PD= 0.87 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

I/O Module

(Registered)

LVTTL/LVCMOS 3.3 V (Pro I/O banks)

Output drive strength = 24 mA

_DP= 2.39 ns

High slew rate

t

_PY= 1.22 ns

t_PD= 0.51 ns

LVPECL

(Pro IO Banks)

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

LVCMOS 1.5 V (Pro IO banks)

Output drive strength = 12 mA

_DP= 3.30 ns

High slew

t_ICLKQ= 0.24 ns

t_ISUD= 0.26 ns

t

t_PD= 0.47 ns

Input LVTTL/LVCMOS

3.3 V (Pro IO banks)

I/O Module

(Registered)

Register Cell

Combinational Cell

Y

t

_PY= 0.90 ns

I/O Module

D

Q

D

Q

D

Q

GTL+ 3.3 V

_DP= 1.53 ns

t_PD= 0.47 ns

t

(Non-Registered)

t

_CLKQ= 0.55 ns

_SUD= 0.43 ns

t_CLKQ= 0.55 ns

t_SUD= 0.43 ns

t_OCLKQ= 0.59 ns

_OSUD= 0.31 ns

LVDS,

BLVDS,

M-LVDS (Pro IO Banks)

t

Input LVTTL/LVCMOS

3.3 V (Pro IO banks)

IInput LVTTL/LVCMOS

3.3 V (Pro IO banks)

t_PY= 1.36 ns

t_PY= 0.90 ns

Figure 2-107 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (T_J= 70°C), Worst-Case V_CC

1.425 V

=

Preliminary v1.7

2-159

Device Architecture

t_PY

t_DIN

t_PYS

D

Q

PAD

DIN

Y

CLK

To Array

I/O interface

t_PY= MAX(t_PY(R), t_PY(F))

_PYs= MAX(t_PYS(R), t_PYS(F))

t_DIN= MAX(t_DIN(R), t_DIN(F))

t

V_IH

V_trip

V_CC

V_IL

PAD

Y

50%

GND

t_PY

(R)

t_PY

(F)

t_PYS

(R)

t_PYS

(F)

V_CC

50%

DIN

GND

t_DOUT

(R)

t_DOUT

(F)

Figure 2-108 • Input Buffer Timing Model and Delays (example)

2-160

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t

t_DOUT

(F)

V_CC

(R)

50%

V_CC

D

0 V

50%

V_OH

DOUT

PAD

0 V

V_trip

V_OL

t_DP

(R)

t_DP

(F)

Figure 2-109 • Output Buffer Model and Delays (example)

Preliminary v1.7

2-161

Device Architecture

t_EOUT

D Q

CLK

t_ZL, t_ZH, t_HZ, t_LZ, t_ZLS, t_ZHS

E

EOUT

D Q

CLK

PAD

DOUT

D

t_EOUT= MAX(t_EOUT(R). t_EOUT(F))

V_CC

I/O Interface

D

E

V_CC

50%

t_{EOUT (F)}

t_{EOUT (R)}

V_CC

50%

t_LZ

50%

ZH

50%

EOUT

PAD

t

ZL

V_CCI

V_trip

HZ

90% V_CCI

V_trip

V_OL

10% V_CCI

V_CC

D

V_CC

50%

V_CC

50%

E

t_{EOUT (F)}

t_{EOUT (R)}

50%

t_ZHS

EOUT

PAD

50%

V_OH

t_ZLS

V_trip

V_OL

Figure 2-110 • Tristate Output Buffer Timing Model and Delays (example)

2-162

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software Settings

Table 2-83 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions

Applicable to Pro I/Os

V_IL

Strength Rate Min., V Max., V

V_IH

Min., V

V_OL

V_OH

Min., V

2.4

I_OLI_OH

mA mA

12 12

Drive

Slew

I/O Standard

Max., V Max., V

3.3 V LVTTL / 12 mA

3.3 V LVCMOS

High –0.3

0.8

2

3.6

0.4

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

High –0.3

0.7

1.7

3.6

0.7

1.7

12 12

High –0.3 0.35 * V_CCI0.65*V_CCI

High –0.3 0.30 V_CCI0.7*V_CCI

0.45

V_CCI– 0.45 12 12

0.25 * V_CCI0.75 * V_CCI12 12

Per PCI Specification

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

Per PCI-X Specification

25 mA²High –0.3 V_REF– 0.05 V_REF+ 0.05

3.6

0.4

–

25 25

51 51

40 40

–

35 mA

33 mA

8 mA

High –0.3

V

_REF– 0.1 V_REF+ 0.1

0.6

–

0.6

–

0.4

V_CCI– 0.4

8

HSTL (II)

15 mA²High –0.3

V_REF– 0.1 V_REF+ 0.1

0.4

15 15

SSTL2 (I)

15 mA

18 mA

14 mA

21 mA

High –0.3

V

_REF– 0.2 V_REF+ 0.2

0.54

0.35

0.7

V_CCI– 0.6 15 15

V_CCI– 0.43 18 18

V_CCI– 1.1 14 14

V_CCI– 0.9 21 21

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

0.5

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output drive strength is below JEDEC specification.

3. Output slew rate can be extracted by the IBIS models.

Table 2-84 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions

Applicable to Advanced I/Os

Drive

Strength Rate

Slew

V_IL

V_IH

Min., V

V_OL

V_OH

Min., V

2.4

I_OLI_OH

mA mA

I/O Standard

Min., V Max., V

Max., V Max., V

3.3 V LVTTL / 12 mA High

3.3 V LVCMOS

–0.3

0.8

2

3.6

0.4

12

2.5 V LVCMOS 12 mA High

1.8 V LVCMOS 12 mA High

1.5 V LVCMOS 12 mA High

3.3 V PCI

–0.3

0.7

1.7

3.6

0.7

1.7

12

–0.3 0.35 * V_CCI0.65 * V_CCI

–0.3 0.30 * V_CCI0.7 * V_CCI

0.45

V_CCI– 0.45 12

0.25 * V_CCI0.75 * V_CCI12

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output drive strength is below JEDEC specification.

Preliminary v1.7

2-163

Device Architecture

Table 2-85 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions

Applicable to Standard I/Os

V_IL

Strength Rate Min., V Max., V

V_IH

V_OL

V_OH

Min., V

2.4

I_OLI_OH

mA mA

Drive

Slew

I/O Standard

Min., V Max., V Max., V

3.3 V LVTTL /

3.3 V LVCMOS

8 mA

High

–0.3

0.8

2

3.6

0.4

8

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

Notes:

8 mA

4 mA

2 mA

High

–0.3

0.7

1.7

3.6

0.7

1.7

8

4

2

8

4

2

–0.3 0.35 * V_CCI0.65 * V_CCI

–0.3 0.30 * V_CCI0.7 * V_CCI

0.45

V_CCI– 0.45

0.25 * V_CCI0.75 * V_CCI

1. Currents are measured at 85°C junction temperature.

2. Output drive strength is below JEDEC specification.

Table 2-86 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial

Conditions

Applicable to All I/O Bank Types

Commercial¹

Industrial²

I_IL

µA

10

I_IH

µA

10

I_IL

µA

15

I_IH

µA

15

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. Commercial range (0°C < T_A< 70°C)

2. Industrial range (–40°C < T_A< 85°C)

2-164

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-87 • Summary of AC Measuring Points

Applicable to All I/O Bank Types

Input Reference Voltage Board Termination Voltage

Measuring Trip Point

(V_trip

Standard

(V_{REF_TYP}

)

(V_{TT_REF}

)

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

–

1.4 V

1.2 V

0.90 V

0.75 V

0.285 * V_CCI(RR)

0.615 * V_CCI(FF))

3.3 V PCI-X

–

0.285 * V_CCI(RR)

0.615 * V_CCI(FF)

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

0.8 V

1.0 V

0.75 V

1.25 V

1.5 V

–

1.2 V

V_REF

1.5 V

V_REF

1.5 V

V_REF

0.75 V

1.25 V

V_REF

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

V_REF

1.485 V

V_REF

1.485 V

V_REF

–

Cross point

LVPECL

–

Table 2-88 • I/O AC Parameter Definitions

Parameter

Definition

Data to Pad delay through the Output Buffer

t_DP

t_PY

Pad to Data delay through the Input Buffer with Schmitt trigger disabled

Data to Output Buffer delay through the I/O interface

t_DOUT

t_EOUT

t_DIN

t_PYS

t_HZ

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Pad to Data delay through the Input Buffer with Schmitt trigger enabled

Enable to Pad delay through the Output Buffer—HIGH to Z

Enable to Pad delay through the Output Buffer—Z to HIGH

Enable to Pad delay through the Output Buffer—LOW to Z

Enable to Pad delay through the Output Buffer—Z to LOW

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

Preliminary v1.7

2-165

Device Architecture

Table 2-89 • Summary of I/O Timing Characteristics – Software Default Settings

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os

I/O Standard

3.3 V LVTTL/

3.3 V LVCMOS

12 mA High 35

–

0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns

2.5 V LVCMOS 12 mA High 35

1.8 V LVCMOS 12 mA High 35

1.5 V LVCMOS 12 mA High 35

0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns

0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns

0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns

0.49 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.45 2.70 3.80 3.16 ns

–

2

3.3 V PCI

Per High 10

2

PCI

spec

2

3.3 V PCI-X

Per High 10 25 0.49 2.09 0.03 0.77 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16 ns

PCI-X

spec

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

25 mA High 10 25 0.49 1.55 0.03 2.19

25 mA High 10 25 0.49 1.59 0.03 1.83

35 mA High 10 25 0.49 1.53 0.03 1.19

33 mA High 10 25 0.49 1.65 0.03 1.13

8 mA High 20 50 0.49 2.37 0.03 1.59

15 mA High 20 25 0.49 2.26 0.03 1.59

17 mA High 30 50 0.49 1.59 0.03 1.00

21 mA High 30 25 0.49 1.62 0.03 1.00

16 mA High 30 50 0.49 1.72 0.03 0.93

24 mA High 30 25 0.49 1.54 0.03 0.93

–

0.32 1.52 1.55 0.00 0.00 3.19 3.22 ns

0.32 1.61 1.59 0.00 0.00 3.28 3.26 ns

0.32 1.56 1.53 0.00 0.00 3.23 3.20 ns

0.32 1.68 1.57 0.00 0.00 3.35 3.24 ns

0.32 2.42 2.35 0.00 0.00 4.09 4.02 ns

0.32 2.30 2.03 0.00 0.00 3.97 3.70 ns

0.32 1.62 1.38 0.00 0.00 3.29 3.05 ns

0.32 1.65 1.32 0.00 0.00 3.32 2.99 ns

0.32 1.75 1.37 0.00 0.00 3.42 3.04 ns

0.32 1.57 1.25 0.00 0.00 3.24 2.92 ns

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

24 mA High

–

0.49 1.57 0.03 1.36

0.49 1.60 0.03 1.22

–

ns

LVPECL

–

Notes:

1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-115 on

page 2-191 for connectivity. This resistor is not required during normal operation.

2-166

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-90 • Summary of I/O Timing Characteristics – Software Default Settings

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/Os

I/O Standard

3.3 V LVTTL/ 12 mA High 35 pF

3.3 V LVCMOS

–

0.49 2.64 0.03 0.90 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns

2.5 V LVCMOS

12 mA High 35 pF

12 mA High 3 5pF

–

0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns

0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns

1.8 V

LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA High 35 pF

–

0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns

Per PCI High 10 pF 25²0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

spec

3.3 V PCI-X

PerPCI-X High 10 pF 25²0.49 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

spec

LVDS

24 mA High

–

0.49 1.37 0.03 1.20 N/A N/A N/A N/A N/A N/A N/A ns

0.49 1.34 0.03 1.05 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL

Notes:

1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-115 on

page 2-191 for connectivity. This resistor is not required during normal operation.

Preliminary v1.7

2-167

Device Architecture

Table 2-91 • Summary of I/O Timing Characteristics – Software Default Settings

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/Os

I/O Standard

3.3 V LVTTL/

8 mA High

35 pF

–

0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01

ns

3.3 V LVCMOS

2.5 V LVCMOS 8 mA High

1.8 V LVCMOS 4 mA High

1.5 V LVCMOS 2 mA High

Notes:

35pF

–

0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91

0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85

0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83

ns

1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-115 on

page 2-191 for connectivity. This resistor is not required during normal operation.

2-168

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Detailed I/O DC Characteristics

Table 2-92 • Input Capacitance

Symbol

C_IN

Definition

Input capacitance

Conditions

Min.

Max.

Units

pF

V_IN= 0, f = 1.0 MHz

8

C_INCLK

Input capacitance on the clock pin V_IN= 0, f = 1.0 MHz

pF

Table 2-93 • I/O Output Buffer Maximum Resistances¹

R_PULL-DOWN

(ohms)²

R_PULL-UP

Standard

Drive Strength

(ohms)³

Applicable to Pro I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

8 mA

100

50

300

150

75

50

33

200

100

50

40

22

225

112

56

22

224

112

75

37

75

–

12 mA

16 mA

24 mA

4 mA

25

17

11

2.5 V LVCMOS

1.8 V LVCMOS

100

50

8 mA

12 mA

16 mA

24 mA

2 mA

25

20

11

200

100

50

4 mA

6 mA

8 mA

50

12 mA

16 mA

2 mA

20

1.5 V LVCMOS

200

100

67

4 mA

6 mA

8 mA

33

12 mA

Per PCI/PCI-X specification

25 mA

35 mA

33

3.3 V PCI/PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

Notes:

25

11

14

–

12

–

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CC, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/techdocs/models/ibis.html.

2. R_{(PULL-DOWN-MAX)}= V_OLspec/ I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

Preliminary v1.7

2-169

Device Architecture

Table 2-93 • I/O Output Buffer Maximum Resistances¹(continued)

R_PULL-DOWN

(ohms)²

R_PULL-UP

(ohms)³

Standard

Drive Strength

33 mA

2.5 V GTL+

15

50

25

27

13

44

18

–

HSTL (I)

8 mA

50

25

31

15

69

32

HSTL (II)

15 mA

SSTL2 (I)

17 mA

SSTL2 (II)

21 mA

SSTL3 (I)

16 mA

SSTL3 (II)

24 mA

Applicable to Advanced I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

100

50

300

150

75

50

25

17

50

11

33

2.5 V LVCMOS

100

50

200

100

50

25

20

40

11

22

1.8 V LVCMOS

200

100

50

225

112

56

50

56

20

22

20

22

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CC, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/techdocs/models/ibis.html.

2. R_{(PULL-DOWN-MAX)}= V_OLspec/ I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

2-170

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-93 • I/O Output Buffer Maximum Resistances¹(continued)

R_PULL-DOWN

(ohms)²

R_PULL-UP

(ohms)³

Standard

Drive Strength

1.5 V LVCMOS

2 mA

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

33

37

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

25

75

Applicable to Standard I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

100

50

300

150

200

100

225

112

224

50

2.5 V LVCMOS

1.8 V LVCMOS

100

50

200

100

200

1.5 V LVCMOS

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CC, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/techdocs/models/ibis.html.

2. R_{(PULL-DOWN-MAX)}= V_OLspec/ I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

Table 2-94 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

(ohms)

R_{(WEAK PULL-DOWN)}

(ohms)

V_CCI

Min.

10 k

11 k

18 k

19 k

Max.

45 k

55 k

70 k

90 k

Min.

Max.

45 k

3.3 V

2.5 V

1.8 V

1.5 V

Notes:

10 k

12 k

17 k

19 k

74 k

110 k

140 k

1. R_{(WEAK PULL-DOWN-MAX)}= V_OLspec/ I_{WEAK PULL-DOWN-MIN}

2. R_{(WEAK PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_{WEAK PULL-UP-MIN}

Preliminary v1.7

2-171

Device Architecture

Table 2-95 • I/O Short Currents I_OSH/I_OSL

Drive Strength

I_OSH(mA)*

I_OSL(mA)*

Applicable to Pro I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

8 mA

25

51

103

132

268

16

32

65

83

169

9

27

54

12 mA

16 mA

24 mA

4 mA

109

127

181

18

2.5 V LVCMOS

1.8 V LVCMOS

8 mA

37

12 mA

16 mA

24 mA

2 mA

74

87

124

11

4 mA

17

35

45

91

13

25

32

66

22

6 mA

44

8 mA

51

12 mA

16 mA

2 mA

74

1.5 V LVCMOS

16

4 mA

33

6 mA

39

8 mA

55

12 mA

55

Applicable to Advanced I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

25

27

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

2 mA

103

132

268

25

109

127

181

27

3.3 V LVCMOS

4 mA

25

27

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

103

132

268

109

127

181

Note: *T_J= 100°C

2-172

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-95 • I/O Short Currents I_OSH/I_{OSL (continued)}

Drive Strength

2 mA

I_OSH(mA)*

I_OSL(mA)*

18

2.5 V LVCMOS

16

32

65

83

169

9

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

18

37

74

87

124

11

1.8 V LVCMOS

17

35

45

91

13

25

32

66

103

22

44

51

74

1.5 V LVCMOS

3.3 V PCI/PCI-X

16

33

39

55

Per PCI/PCI-X

specification

109

Applicable to Standard I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

25

51

16

32

9

27

54

18

37

11

22

16

2.5 V LVCMOS

1.8 V LVCMOS

17

13

1.5 V LVCMOS

Note: *T_J= 100°C

The length of time an I/O can withstand I_OSH/I_OSLevents depends on the junction temperature. The

reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Preliminary v1.7

2-173

Device Architecture

Table 2-96 • Short Current Event Duration before Failure

Temperature

–40°C

0°C

Time before Failure

>20 years

5 years

25°C

70°C

85°C

2 years

100°C

110°C

6 months

3 months

Table 2-97 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration

Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

240 mV

140 mV

80 mV

60 mV

Table 2-98 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.)

Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS (Schmitt trigger

disabled)

No requirement

10 ns*

20 years (110°C)

LVTTL/LVCMOS (Schmitt trigger

enabled)

No requirement

No requirement, but input 20 years (110°C)

noise voltage cannot exceed

Schmitt hysteresis

HSTL/SSTL/GTL

No requirement

10 ns*

10 years (100°C)

LVDS/BLVDS/M-LVDS/LVPECL

Note: *The maximum input rise/fall time is related only to the noise induced into the input buffer trace. If the

noise is low, the rise time and fall time of input buffers, when Schmitt trigger is disabled, can be increased

beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the

board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure there is

no excessive noise coupling into input signals.

2-174

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard

is supported as part of the 3.3 V LVTTL support.

Table 2-99 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_IL

I_IH

Max.,

mA¹

Max.,

mA¹

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Applicable to Pro I/O Banks

µA²µA²

4 mA

–0.3

0.8

2

3.6

0.4

2.4

4

8

4

8

27

54

25

51

10 10

8 mA

12 mA

16 mA

24 mA

12 12

16 16

24 24

109

127

181

103

132

268

Applicable to Advanced I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

27

25

10 10

54

51

54

51

12 12

16 16

24 24

109

127

181

103

132

268

Applicable to Standard I/O Banks

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

27

54

25

51

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Data Path

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-111 • AC Loading

Table 2-100 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

0

Input HIGH (V)

3.3

Measuring Point* (V)

1.4

V

_REF(typ.) (V)

–

C_LOAD(pF)

35

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Preliminary v1.7

2-175

Device Architecture

Timing Characteristics

Table 2-101 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29

ns

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.36 0.04 1.02 1.33 0.36 9.54 7.70 2.29 2.08 11.44 9.60

8.22 0.03 0.90 1.17 0.32 8.37 6.76 2.01 1.82 10.04 8.43

7.86 0.04 1.20 1.57 0.43 8.01 6.44 3.04 3.06 10.24 8.68

6.69 0.04 1.02 1.33 0.36 6.81 5.48 2.58 2.61 8.71 7.38

5.87 0.03 0.90 1.17 0.32 5.98 4.81 2.27 2.29 7.65 6.48

6.03 0.04 1.20 1.57 0.43 6.14 5.02 3.28 3.47 8.37 7.26

5.13 0.04 1.02 1.33 0.36 5.22 4.27 2.79 2.95 7.12 6.17

4.50 0.03 0.90 1.17 0.32 4.58 3.75 2.45 2.59 6.25 5.42

5.62 0.04 1.20 1.57 0.43 5.72 4.72 3.32 3.58 7.96 6.96

4.78 0.04 1.02 1.33 0.36 4.87 4.02 2.83 3.04 6.77 5.92

4.20 0.03 0.90 1.17 0.32 4.27 3.53 2.48 2.67 5.94 5.20

5.24 0.04 1.20 1.57 0.43 5.34 4.69 3.39 3.96 7.58 6.93

4.46 0.04 1.02 1.33 0.36 4.54 3.99 2.88 3.37 6.44 5.89

3.92 0.03 0.90 1.17 0.32 3.99 3.50 2.53 2.96 5.66 5.17

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-102 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

7.88 0.04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94

6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73 7.60

5.89 0.03 0.90 1.17 0.32 6.00 5.01 2.01 1.93 7.67 6.67

5.08 0.04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41 6.38

4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30 5.43

3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.28 2.40 5.53 4.76

3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97 5.11

3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34

2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81

3.46 0.04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76 4.84

2.95 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90 4.12

2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30 3.62

3.21 0.04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50 4.39

2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68 3.74

2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11 3.28

ns

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-176

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-103 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66 10.26 0.04

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

0.43 10.45 8.90

2.64

2.25

1.98

2.98

2.54

2.23

3.21

2.73

2.39

3.26

2.77

2.43

3.32

2.82

2.48

2.46 12.68 11.13

2.09 10.79 9.47

ns

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.72

7.66

7.27

6.19

5.43

5.58

4.75

4.17

5.21

4.43

3.89

4.85

4.13

3.62

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

8.89

7.80

7.41

6.30

5.53

5.68

4.84

4.24

5.30

4.51

3.96

4.94

4.20

3.69

7.57

6.64

6.28

5.35

4.69

4.87

4.14

3.64

4.56

3.88

3.41

4.54

3.87

3.39

–2

1.83

3.04

2.59

2.27

3.42

2.91

2.55

3.51

2.99

2.62

3.88

3.30

2.90

9.47

9.65

8.20

7.20

7.92

6.74

5.91

7.54

6.41

5.63

7.18

6.10

5.36

8.31

8.52

7.25

6.36

7.11

6.05

5.31

6.80

5.79

5.08

6.78

5.77

5.06

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-104 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

7.66

6.51

5.72

4.91

4.17

3.66

3.53

3.00

2.64

3.33

2.83

2.49

3.08

2.62

2.30

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

7.80

6.63

5.82

5.00

4.25

3.73

3.60

3.06

2.69

3.39

2.89

2.53

3.13

2.66

2.34

6.59

5.60

4.92

4.07

3.46

3.04

2.82

2.40

2.11

2.56

2.18

1.91

2.12

1.80

1.58

2.65

2.25

1.98

2.99

2.54

2.23

3.21

2.73

2.40

3.26

2.77

2.44

3.32

2.83

2.48

2.61 10.03 8.82

ns

2.22

1.95

3.20

2.73

2.39

3.58

3.05

2.68

3.68

3.13

2.75

4.06

3.45

3.03

8.54

7.49

7.23

6.15

5.40

5.83

4.96

4.36

5.63

4.79

4.20

5.37

4.57

4.01

7.51

6.59

6.31

5.36

4.71

5.06

4.30

3.78

4.80

4.08

3.58

4.35

3.70

3.25

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-177

Device Architecture

Table 2-105 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/Os

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

9.46

8.05

7.07

9.46

8.05

7.07

6.57

5.59

4.91

6.57

5.59

4.91

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

9.64

8.20

7.20

9.64

8.20

7.20

6.69

5.69

5.00

6.69

5.69

5.00

8.54

7.27

6.38

8.54

7.27

6.38

5.98

5.09

4.47

5.98

5.09

4.47

2.07

1.76

1.55

2.07

1.76

1.55

2.40

2.04

1.79

2.40

2.04

1.79

2.04

1.73

1.52

2.04

1.73

1.52

2.57

2.19

1.92

2.57

2.19

1.92

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-106 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

Std.

–1

7.07

6.01

5.28

7.07

6.01

5.28

4.41

3.75

3.29

4.41

3.75

3.29

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

7.20

6.12

5.37

7.20

6.12

5.37

4.49

3.82

3.36

4.49

3.82

3.36

6.23

5.30

4.65

6.23

5.30

4.65

3.75

3.19

2.80

3.75

3.19

2.80

2.07

1.76

1.55

2.07

1.76

1.55

2.39

2.04

1.79

2.39

2.04

1.79

2.15

1.83

1.60

2.15

1.83

1.60

2.69

2.29

2.01

2.69

2.29

2.01

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-178

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-107 • Minimum and Maximum DC Input and Output Levels

2.5 V LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_IL

I_IH

Drive

Strength

Max., Max.,

Min., V Max., V Min., V Max., V Max., V Min., V mA mA

mA¹

mA¹µA²µA²

Applicable to Pro I/O Banks

4 mA

–0.3

0.7

1.7

3.6

0.7

1.7

4

8

4

8

18

37

16

32

10 10

8 mA

12 mA

16 mA

24 mA

12 12

16 16

24 24

74

65

87

83

124

169

Applicable to Advanced I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

–0.3

0.7

1.7

3.6

0.7

1.7

2

4

6

8

2

4

6

8

18

16

10 10

37

32

37

32

12 12

16 16

24 24

74

65

87

83

124

169

Applicable to Standard I/O Banks

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.7

1.7

3.6

0.7

1.7

2

4

6

8

2

4

6

8

18

37

16

32

10 10

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Data Path

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-112 • AC Loading

Table 2-108 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V)

C_LOAD(pF)

35

0

2.5

1.2

–

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Preliminary v1.7

2-179

Device Architecture

Timing Characteristics

Table 2-109 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.60 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85

0.51 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78

ns

–2

0.45

0.60

0.51

0.45

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34

8.73 0.04 1.51 1.66 0.43 8.89 8.01 3.10 2.93 11.13 10.25

7.43 0.04 1.29 1.41 0.36 7.57 6.82 2.64 2.49 9.47 8.72

6.52 0.03 1.13 1.24 0.32 6.64 5.98 2.32 2.19 8.31 7.65

6.77 0.04 1.51 1.66 0.43 6.90 6.11 3.37 3.39 9.14 8.34

5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10

5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23

6.31 0.04 1.51 1.66 0.43 6.42 5.73 3.42 3.52 8.66 7.96

5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77

4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95

5.93 0.04 1.51 1.66 0.43 6.04 5.70 3.49 4.00 8.28 7.94

5.05 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75

4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.99 6.18 5.93

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-110 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.60 8.82 0.04 1.51 1.66 0.43 8.13 8.82 2.72 2.29 10.37 11.05

0.51 7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40

0.45 6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25

0.60 5.27 0.04 1.51 1.66 0.43 5.27 5.27 3.10 3.03 7.50 7.51

0.51 4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 6.38

0.45 3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61

0.66 3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73

0.56 3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15 4.87

0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28

0.66 3.53 0.04 1.51 1.66 0.43 3.59 3.12 3.42 3.62 5.83 5.35

0.56 3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55

0.49 2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00

0.66 3.26 0.04 1.51 1.66 0.43 3.32 2.48 3.49 4.11 5.56 4.72

0.56 2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01

0.49 2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52

ns

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-180

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-111 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66 11.40 0.04

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

0.43 11.22 11.40 2.68

2.20 13.45 13.63

1.88 11.44 11.60

1.65 10.05 10.18

2.89 10.34 10.05

ns

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.69

8.51

7.96

6.77

5.94

6.18

5.26

4.61

6.18

5.26

4.61

6.18

5.26

4.61

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

9.54

8.38

8.11

6.90

6.05

6.29

5.35

4.70

6.29

5.35

4.70

6.29

5.35

4.70

9.69

8.51

7.81

6.65

5.84

5.92

5.03

4.42

5.92

5.03

4.42

5.92

5.03

4.42

2.28

2.00

3.05

2.59

2.28

3.30

2.81

2.47

3.30

2.81

2.47

3.30

2.81

2.47

–2

8 mA

Std.

–1

2.46

2.16

3.32

2.83

2.48

3.32

2.83

2.48

3.32

2.83

2.48

8.80

7.72

8.53

7.26

6.37

8.53

7.26

6.37

8.53

7.26

6.37

8.55

7.50

8.15

6.94

6.09

8.15

6.94

6.09

8.15

6.94

6.09

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-112 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.66

7.37

6.47

5.17

4.39

3.86

3.56

3.03

2.66

3.35

2.85

2.50

3.56

3.03

2.66

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

7.83

6.66

5.85

5.04

4.28

3.76

3.63

3.08

2.71

3.41

2.90

2.55

3.63

3.08

2.71

8.66

7.37

6.47

5.17

4.39

3.86

3.43

2.92

2.56

3.06

2.60

2.29

3.43

2.92

2.56

2.68

2.28

2.00

3.05

2.59

2.28

3.30

2.81

2.47

3.36

2.86

2.51

3.30

2.81

2.47

2.30 10.07 10.90

ns

1.96

1.72

3.00

2.55

2.24

3.44

2.92

2.57

3.55

3.02

2.65

3.44

2.92

2.57

8.56

7.52

7.27

6.19

5.43

5.86

4.99

4.38

5.65

4.81

4.22

5.86

4.99

4.38

9.27

8.14

7.40

6.30

5.53

5.67

4.82

4.23

5.30

4.51

3.96

5.67

4.82

4.23

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-181

Device Architecture

Table 2-113 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

4 mA

6 mA

8 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

11.00

9.35

8.21

11.00

9.35

8.21

7.50

6.38

5.60

7.50

6.38

5.60

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

10.37

8.83

7.75

10.37

8.83

7.75

7.36

6.26

5.49

7.36

6.26

5.49

11.00

9.35

8.21

11.00

9.35

8.21

7.50

6.38

5.60

7.50

6.38

5.60

2.03

1.73

1.52

2.03

1.73

1.52

2.39

2.03

1.78

2.39

2.03

1.78

1.83

1.56

1.37

1.83

1.56

1.37

2.46

2.10

1.84

2.46

2.10

1.84

ns

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-114 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

Std.

–1

8.20

6.98

6.13

8.20

6.98

6.13

4.77

4.05

3.56

4.77

4.05

3.56

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

7.24

6.16

5.41

7.24

6.16

5.41

4.55

3.87

3.40

4.55

3.87

3.40

8.20

6.98

6.13

8.20

6.98

6.13

4.77

4.05

3.56

4.77

4.05

3.56

2.03

1.73

1.52

2.03

1.73

1.52

2.38

2.03

1.78

2.38

2.03

1.78

1.91

1.62

1.43

1.91

1.62

1.43

2.55

2.17

1.91

2.55

2.17

1.91

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-182

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

1.8 V LVCMOS

Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and push-pull output buffer.

Table 2-115 • Minimum and Maximum DC Input and Output Levels

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSH

I_ILI_IH

Drive

Strength Min., V

Max., Max.,

Max., V

Min., V

Max., V Max., V Min., V mA mA mA¹

mA¹µA²µA²

Applicable to Pro I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

–0.3

0.35 * V_CCI0.65 * V_CCI

3.6

0.45

V_CCI– 0.45

2

4

6

8

2

4

6

8

11

22

44

51

74

9

10 10

17

35

45

91

V_CCI– 0.45 12 12

V_CCI– 0.45 16 16

Applicable to Advanced I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

–0.3

0.35 * V_CCI0.65 * V_CCI

3.6

0.45

V_CCI– 0.45

2

4

6

8

2

4

6

8

11

22

44

51

74

9

10 10

17

35

45

91

V_CCI– 0.45 12 12

V_CCI– 0.45 16 16

Applicable to Standard I/O Banks

2 mA

4 mA

Notes:

–0.3

0.35 * V_CCI0.65 * V_CCI

3.6

0.45

V_CCI– 0.45

2

4

2

4

11

22

9

10 10

17

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Data Path

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-113 • AC Loading

Table 2-116 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Measuring Point* (V)

V

_REF(typ.) (V)

C_LOAD(pF)

35

0

1.8

0.9

–

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Preliminary v1.7

2-183

Device Architecture

Timing Characteristics

Table 2-117 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

16 mA

Std.

–1

0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07

0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37

0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50

0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99

0.56 9.69 0.04 1.23 1.62 0.36 9.87 9.15 2.77 2.36 11.77 11.05

0.49 8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70

0.66 8.97 0.04 1.45 1.91 0.43 9.14 8.10 3.57 3.36 11.37 10.33

0.56 7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79

0.49 6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72

0.66 8.35 0.04 1.45 1.91 0.43 8.50 7.59 3.64 3.52 10.74 9.82

0.56 7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35

0.49 6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33

0.66 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80

0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33

0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32

ns

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-118 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

16 mA

Std.

–1

0.66 12.10 0.04 1.45 1.91 0.43 9.59 12.10 2.78 1.64 11.83 14.34

0.56 10.30 0.04 1.23 1.62 0.36 8.16 10.30 2.37 1.39 10.06 12.20

ns

–2

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.04 0.03 1.08 1.42 0.32 7.16 9.04 2.08 1.22 8.83 10.71

7.05 0.04 1.45 1.91 0.43 6.20 7.05 3.25 2.86 8.44 9.29

6.00 0.04 1.23 1.62 0.36 5.28 6.00 2.76 2.44 7.18 7.90

5.27 0.03 1.08 1.42 0.32 4.63 5.27 2.43 2.14 6.30 6.94

4.52 0.04 1.45 1.91 0.43 4.47 4.52 3.57 3.47 6.70 6.76

3.85 0.04 1.23 1.62 0.36 3.80 3.85 3.04 2.95 5.70 5.75

3.38 0.03 1.08 1.42 0.32 3.33 3.38 2.66 2.59 5.00 5.05

4.12 0.04 1.45 1.91 0.43 4.20 3.99 3.63 3.62 6.43 6.23

3.51 0.04 1.23 1.62 0.36 3.57 3.40 3.09 3.08 5.47 5.30

3.08 0.03 1.08 1.42 0.32 3.14 2.98 2.71 2.71 4.81 4.65

3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32

3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53

2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-184

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-119 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/Os

Drive

Speed

Strength

Grade t_DOUTt_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

16 mA

Std.

–1

0.66 15.53 0.04

0.56 13.21 0.04

0.49 11.60 0.03

0.66 10.48 0.04

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

0.43 14.11 15.53 2.78

0.36 12.01 13.21 2.36

0.32 10.54 11.60 2.07

0.43 10.41 10.48 3.23

1.60 16.35 17.77

1.36 13.91 15.11

1.19 12.21 13.27

2.73 12.65 12.71

2.33 10.76 10.81

ns

–2

Std.

–1

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.91 0.04

7.82 0.03

8.05 0.04

6.85 0.04

6.01 0.03

7.50 0.04

6.38 0.04

5.60 0.03

7.29 0.04

6.20 0.04

5.45 0.03

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

8.86

7.77

8.20

6.97

6.12

7.64

6.50

5.71

7.23

6.15

5.40

8.91

7.82

7.84

6.67

5.86

7.30

6.21

5.45

7.29

6.20

5.45

2.75

2.41

3.54

3.01

2.64

3.61

3.07

2.69

3.71

3.15

2.77

–2

2.04

9.44

9.49

Std.

–1

3.27 10.43 10.08

2.78

2.44

3.41

2.90

2.55

3.95

3.36

2.95

8.88

7.79

9.88

8.40

7.38

9.47

8.06

7.07

8.57

7.53

9.53

8.11

7.12

9.53

8.11

7.12

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-120 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/Os

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

16 mA

Std.

–1

0.66 11.86 0.04 1.22 0.43 9.14 11.86 2.77

0.56 10.09 0.04 1.04 0.36 7.77 10.09 2.36

1.66 11.37 14.10

ns

1.41

1.24

2.84

2.41

2.12

3.38

2.88

2.53

3.52

3.00

2.63

4.08

3.47

3.05

9.67 11.99

8.49 10.53

–2

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.86

6.91

5.88

5.16

4.45

3.78

3.32

3.92

3.34

2.93

3.53

3.01

2.64

0.03 0.91 0.32 6.82

0.04 1.22 0.43 5.86

0.04 1.04 0.36 4.99

0.03 0.91 0.32 4.38

0.04 1.22 0.43 4.18

0.04 1.04 0.36 3.56

0.03 0.91 0.32 3.12

0.04 1.22 0.43 3.93

0.04 1.04 0.36 3.34

0.03 0.91 0.32 2.93

0.04 1.22 0.43 3.60

0.04 1.04 0.36 3.06

0.03 0.91 0.32 2.69

8.86

6.91

5.88

5.16

4.45

3.78

3.32

3.92

3.34

2.93

3.04

2.59

2.27

2.07

3.22

2.74

2.41

3.53

3.00

2.64

3.60

3.06

2.69

3.70

3.15

2.76

Std.

–1

8.10

6.89

6.05

6.42

5.46

4.79

6.16

5.24

4.60

5.84

4.96

4.36

9.15

7.78

6.83

6.68

5.69

4.99

6.16

5.24

4.60

5.28

4.49

3.94

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-185

Device Architecture

Table 2-121 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard I/Os

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

15.01

12.77

11.21

10.10

8.59

1.20

1.02

0.90

1.20

1.02

0.90

13.15

11.19

9.82

9.55

8.13

7.13

15.01

12.77

11.21

10.10

8.59

1.99

1.70

1.49

2.41

2.05

1.80

1.99

1.70

1.49

2.37

2.02

1.77

ns

–2

ns

4 mA

Std.

–1

ns

–2

7.54

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-122 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

11.21

9.54

8.37

6.34

5.40

4.74

0.04

0.03

0.04

0.03

1.20

1.02

0.90

1.20

1.02

0.90

0.43

0.36

0.32

0.43

0.36

0.32

8.53

7.26

6.37

5.38

4.58

4.02

11.21

9.54

8.37

6.34

5.40

4.74

1.99

1.69

1.49

2.41

2.05

1.80

1.21

1.03

0.90

2.48

2.11

1.85

ns

–2

ns

4 mA

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-186

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and push-pull output buffer.

Table 2-123 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

Max., Max.,

Min., V mA mA mA¹mA¹µA²µA²

I_OSHI_ILI_IH

Drive

Strength

Min., V

Max., V

Min., V Max., V

Max., V

Applicable to Pro I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

–0.3

0.30 * V_CCI0.7 * V_CCI

3.6

0.25 * V_CCI0.75 * V_CCI

2

4

6

8

2

4

6

8

16

33

39

55

13

25

32

66

10 10

0.30 * V_CCI0.7 * V_CCI

0.25 * V_CCI0.75 * V_CCI12 12

Applicable to Pro I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

–0.3

0.30 * V_CCI0.7 * V_CCI

3.6

0.25 * V_CCI0.75 * V_CCI

2

4

6

8

2

4

6

8

16

33

39

55

13

25

32

66

10 10

0.25 * V_CCI0.75 * V_CCI12 12

Applicable to Pro I/O Banks

2 mA

–0.3

0.30 * V_CCI0.7 * V_CCI

3.6

0.25 * V_CCI0.75 * V_CCI

2

16

13

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Data Path

35 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-114 • AC Loading

Table 2-124 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V)

C_LOAD(pF)

35

0

1.5

0.75

–

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Preliminary v1.7

2-187

Device Architecture

Timing Characteristics

Table 2-125 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

2 mA

4 mA

8 mA

12 mA

Std.

–1

0.66 14.11 0.04 1.70 2.14 0.43 14.37 13.14 3.40 2.68 16.61 15.37

0.56 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08

0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48

0.66 11.23 0.04 1.70 2.14 0.43 11.44 9.87 3.77 3.36 13.68 12.10

ns

–2

Std.

–1

0.56

0.49

9.55 0.04 1.44 1.82 0.36 9.73 8.39 3.21 2.86 11.63 10.29

8.39 0.03 1.27 1.60 0.32 8.54 7.37 2.81 2.51 10.21 9.04

–2

Std.

–1

0.66 10.45 0.04 1.70 2.14 0.43 10.65 9.24 3.84 3.55 12.88 11.48

0.56

0.49

8.89 0.04 1.44 1.82 0.36 9.06 7.86 3.27 3.02 10.96 9.76

7.81 0.03 1.27 1.60 0.32 7.95 6.90 2.87 2.65 9.62 8.57

–2

Std.

–1

0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47

0.56

0.49

8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75

7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-126 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

2 mA

4 mA

8 mA

12 mA

Std.

–1

0.66 8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77

0.56 7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08 9.16

0.49 6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09 8.04

0.66 5.41 0.04 1.70 2.14 0.43 5.22 5.41 3.75 3.48 7.45 7.65

0.56 4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34 6.50

0.49 4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56 5.71

0.66 4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13 6.98

0.56 4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06 5.94

0.49 3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32 5.21

0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86

0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98

0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37

ns

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-188

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-127 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

Std.

–1

0.66 12.78 0.04

0.56 10.87 0.04

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

0.43 12.81 12.78 3.40

0.36 10.90 10.87 2.89

2.64 15.05 15.02

2.25 12.80 12.78

1.97 11.24 11.22

3.27 12.43 11.78

2.78 10.57 10.02

ns

–2

0.49

9.55

0.03

0.32

9.57

9.55

2.54

3.75

3.19

2.80

3.83

3.26

2.86

3.95

3.36

2.95

Std.

–1

0.66 10.01 0.04

0.43 10.19 9.55

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.51

7.47

9.33

7.94

6.97

8.91

7.58

6.65

0.04

0.03

0.04

0.03

0.04

0.03

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

8.67

7.61

9.51

8.09

7.10

9.07

7.72

6.78

8.12

7.13

8.89

7.56

6.64

8.89

7.57

6.64

–2

2.44

9.28

8.80

Std.

–1

3.43 11.74 11.13

2.92

2.56

9.99

8.77

9.47

8.31

–2

Std.

–1

4.05 11.31 11.13

3.44

3.02

9.62

8.45

9.47

8.31

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-128 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.36

7.11

6.24

5.31

4.52

3.97

4.67

3.97

3.49

4.08

3.47

3.05

1.44

1.22

1.07

1.44

1.22

1.07

1.44

1.22

1.07

1.44

1.22

1.07

6.82

5.80

5.10

4.85

4.13

3.62

4.55

3.87

3.40

4.15

3.53

3.10

8.36

7.11

6.24

5.31

4.52

3.97

4.67

3.97

3.49

3.58

3.04

2.67

3.39

2.88

2.53

3.74

3.18

2.79

3.82

3.25

2.85

3.94

3.36

2.95

2.77

2.35

2.06

3.40

2.89

2.54

3.56

3.03

2.66

4.20

3.58

3.14

9.06 10.60

ns

7.71

6.76

7.09

6.03

5.29

6.78

5.77

5.07

6.39

5.44

4.77

9.02

7.91

7.55

6.42

5.64

6.90

5.87

5.16

5.81

4.95

4.34

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-189

Device Architecture

Table 2-129 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard I/Os

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

12.33

10.49

9.21

1.42

1.21

1.06

11.79

10.03

8.81

12.33

10.49

9.21

2.45

2.08

1.83

2.32

1.98

1.73

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-130 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

Std.

–1

7.65

6.50

5.71

1.42

1.21

1.06

6.31

5.37

4.71

7.65

6.50

5.71

2.45

2.08

1.83

2.45

2.08

1.83

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-190

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

3.3 V PCI, 3.3 V PCI-X

The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz

PCI Bus applications.

Table 2-131 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

V_IL

V_IH

V_OL

V_OH

I_OL

I_OH

mA

I_OSL

Max., Max.,

mA¹mA¹µA²µA²

10 10

I_OSH

I_IL

I_IH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA

Per PCI

Per PCI curves

specification

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-115.

R to V_CCIfor t_DP(F)

R to GND for t_DP(R)

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 25

Test Point

Data Path

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-115 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the data path; Actel loading for tristate

is described in Table 2-132.

Table 2-132 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V_REF(typ.) (V)

C_LOAD(pF)

0

3.3

0.285 * V_CCIfor t_DP(R)

0.615 * V_CCIfor t_DP(F)

–

10

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Preliminary v1.7

2-191

Device Architecture

Timing Characteristics

Table 2-133 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

t_PY

t_PYS

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.09

4.33

3.80

t_ZHSUnits

Std.

–1

2.81

2.39

2.09

0.04 1.05 1.67

0.04 0.89 1.42

0.03 0.78 1.25

2.86

2.43

2.13

2.00

1.70

1.49

3.28

2.79

2.45

3.61

3.07

2.70

4.23

3.60

3.16

ns

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-134 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/Os

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

t_PY

t_PYS

t_EOUT

2.73

2.32

2.04

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.19

3.56

3.13

t_ZHSUnits

2.68

2.28

2.00

0.04 0.86 0.43

0.04 0.73 0.36

0.03 0.65 0.32

1.95

1.66

1.46

3.21

2.73

2.40

3.58

3.05

2.68

4.97

4.22

3.71

0.66

0.56

0.49

ns

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-192

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Voltage Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to 3.3 V.

Table 2-135 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSH

I_ILI_IH

Drive

Strength

Max., Max.,

Min., V

Max., V

Min., V

Max., V Max., V Min., V mA mA mA¹

3.6 0.4 25 25 181

mA¹µA²µA²

25 mA³

–0.3

V_REF– 0.05 V_REF+ 0.05

–

268

10 10

Note:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

GTL

25

Test Point

10 pF

Figure 2-116 • AC Loading

Table 2-136 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

V_REF– 0.05

V_REF+ 0.05

0.8

1.2

10

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-137 • 3.3 V GTL

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V,

_REF= 0.8 V

V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.27

3.63

3.19

t_ZHSUnits

Std.

–1

2.08

1.77

1.55

2.93

2.50

2.19

2.04

1.73

1.52

2.08

1.77

1.55

4.31

3.67

3.22

ns

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-193

Device Architecture

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to 2.5 V.

Table 2-138 • Minimum and Maximum DC Input and Output Levels

2.5 GTL

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_IL

I_IH

Drive

Strength

Min.,

V

Max., Max.,

Max., V

Min., V

Max., V Max., V Min., V mA mA mA¹mA¹µA²µA²

3.6 0.4 25 25 124 169 10 10

25 mA³

–0.3 V_REF– 0.05 V_REF+ 0.05

–

1.

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

GTL

25

Test Point

10 pF

Figure 2-117 • AC Loading

Table 2-139 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

1.2

C_LOAD(pF)

V_REF– 0.05

V_REF+ 0.05

0.8

10

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-140 • 2.5 V GTL

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V,

_REF= 0.8 V

V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.40

3.74

3.28

t_ZHS

4.36

3.71

3.26

Units

ns

Std.

–1

2.13

1.81

1.59

2.46

2.09

1.83

2.16

1.84

1.61

2.13

1.81

1.59

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-194

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to 3.3 V.

Table 2-141 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSHI_IL

I_IH

Max.

,

Drive

Strength

m

A

m

A

Max.,

mA¹

Min., V

Max., V

Min., V

Max., V Max., V Min., V

3.6 0.6

mA¹µA²µA²

35 mA

–0.3

V_REF– 0.1 V_REF+ 0.1

–

35 35

181

268 10

10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

GTL+

25

Test Point

10 pF

Figure 2-118 • AC Loading

Table 2-142 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

_REF– 0.1

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

V

V_REF+ 0.1

1.0

1.5

10

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-143 • 3.3 V GTL+

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V,

V_REF= 1.0 V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.33

3.68

3.23

t_ZHS

4.29

3.65

3.20

Units

ns

Std.

–1

2.06

1.75

1.53

1.59

1.35

1.19

2.09

1.78

1.56

2.06

1.75

1.53

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-195

Device Architecture

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to 2.5 V.

Table 2-144 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+

V_IL

V_IH

V_OL

V_OH

I_OL

I_OH

I_OSL

I_OSH

I_IL

I_IH

Drive

Strength

Max., Max., Min.,

Max.,

mA¹

Max.,

Min., V Max., V

Min., V

V

mA

mA¹µA²µA²

33 mA

–0.3 V_REF– 0.1 V_REF+ 0.1 3.6

0.6

–

33

124

169

10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

GTL+

25

Test Point

10 pF

Figure 2-119 • AC Loading

Table 2-145 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

V_REF– 0.1

V_REF+ 0.1

1.0

1.5

10

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-146 • 2.5 V GTL+

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V,

V_REF= 1.0 V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.48

3.81

3.35

t_ZHS

4.34

3.69

4.34

Units

ns

Std.

–1

2.21

1.88

1.65

1.51

1.29

1.13

2.25

1.91

1.68

2.10

1.79

1.57

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-196

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-147 • Minimum and Maximum DC Input and Output Levels

HSTL Class I

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSLI_OSHI_IL

Max.

I_IH

Drive

Strength

Max.,

,

Min., V Max., V

Min., V Max., V Max., V

3.6 0.4

Min., V mA mA mA¹mA¹µA²µA²

8 mA

–0.3

V_REF– 0.1 V_REF+ 0.1

V_CCI– 0.4

8

39

32

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

HSTL

Class I

50

Test Point

20 pF

Figure 2-120 • AC Loading

Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

V_REF– 0.1 V_REF+ 0.1

Measuring Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V) C_LOAD(pF)

0.75

20

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-149 • HSTL Class I

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V,

V_REF= 0.75 V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.47

4.66

4.09

t_ZHS

5.38

4.58

4.02

Units

ns

Std.

–1

3.18

2.70

2.37

2.12

1.81

1.59

3.24

2.75

2.42

3.14

2.67

2.35

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-197

Device Architecture

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-150 • Minimum and Maximum DC Input and Output Levels

HSTL Class II

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSHI_ILI_IH

Drive

Strength

Max., Max., µA µA

2

Min., V Max., V

Min., V Max., V Max., V Min., V mA mA mA¹

3.6 0.4 V_CCI– 0.4 15 15 55

mA¹

15 mA³

–0.3

V_REF– 0.1 V_REF+ 0.1

66

10 10

Note:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

V_TT

HSTL

Class II

25

Test Point

20 pF

Figure 2-121 • AC Loading

Table 2-151 • AC Waveforms, Measuring Points, and Capacitive Loads

V_REF(typ.)

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

(V)

V_TT(typ.) (V)

C_LOAD(pF)

V_REF– 0.1

V_REF+ 0.1

0.75

20

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-152 • HSTL Class II

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V,

_REF= 0.75 V

V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.32

4.52

3.97

t_ZHS

4.95

4.21

3.70

Units

ns

Std.

–1

3.02

2.57

2.26

2.12

1.81

1.59

3.08

2.62

2.30

2.71

2.31

2.03

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-198

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class

I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-153 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class I

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSLI_OSHI_IL

Max., Max.,

I_IH

Drive

Strength

Min., V Max., V

Min., V Max., V Max., V

3.6 0.54

Min., V

mA mA mA¹mA¹µA²µA²

15 mA

–0.3

V_REF– 0.2 V_REF+ 0.2

V_CCI– 0.62 15 15

87

83

10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

SSTL2

Class I

50

Test Point

25

30 pF

Figure 2-122 • AC Loading

Table 2-154 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

V_REF– 0.2

V_REF+ 0.2

1.25

30

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-155 • SSTL 2 Class I

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V,

V_REF= 1.25 V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.40

3.74

3.29

t_ZHS

4.08

3.47

3.05

Units

ns

Std.

–1

2.13

1.81

1.59

1.33

1.14

1.00

2.17

1.84

1.62

1.85

1.57

1.38

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-199

Device Architecture

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class

II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-156 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class II

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSH

I_IL

I_IH

Drive

Strength

Max.,

V

Max., Max.,

Min., V Max., V

Min., V mA mA mA¹mA¹µA²µA²

18 mA

–0.3

V_REF– 0.2 V_REF+ 0.2

3.6

0.35 V_CCI– 0.43 18 18 124

169

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

SSTL2

Class II

25

Test Point

25

30 pF

Figure 2-123 • AC Loading

Table 2-157 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

V_REF– 0.2

V_REF+ 0.2

1.25

30

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-158 • SSTL 2 Class II

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V,

V_REF= 1.25 V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.44

3.78

3.32

t_ZHS

4.01

3.41

2.99

Units

ns

Std.

–1

2.17

1.84

1.62

1.33

1.14

1.00

2.21

1.88

1.65

1.77

1.51

1.32

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-200

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class

I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-159 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I

V_IL

V_IH

V_OL

V_OH

I_OLI_OHI_OSL

I_OSH

I_IL

I_IH

Drive

Strength

Min.,

V

Max.,

V

Max., Max.,

Max., V

Min., V

Max., V

Min., V

mA mA mA¹mA¹µA²µA²

14 14 54 51 10 10

14 mA

–0.3 V_REF– 0.2 V_REF+ 0.2 3.6

0.7

V_CCI– 1.1

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

SSTL3

Class I

50

Test Point

25

30 pF

Figure 2-124 • AC Loading

Table 2-160 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V) V_TT(typ.) (V) C_LOAD(pF)

1.5 1.485 30

V_REF– 0.2

V_REF+ 0.2

1.5

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-161 • SSTL3 Class I

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V,

V_REF= 1.5 V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.59

3.90

3.42

t_ZHS

4.07

3.46

3.04

Units

ns

Std.

–1

2.31

1.96

1.72

1.25

1.06

0.93

2.35

2.00

1.75

1.84

1.56

1.37

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Preliminary v1.7

2-201

Device Architecture

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class

II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-162 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_IL

I_IH

Drive

Strength

Max., Max.

Max., Max.,

Min., V Max., V

Min., V

V

, V

Min., V

mA mA mA¹mA¹µA²µA²

21 mA

–0.3

V_REF– 0.2 V_REF+ 0.2 3.6

0.5

V_CCI– 0.9 21 21

109 103 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

V_TT

SSTL3

Class II

25

Test Point

25

30 pF

Figure 2-125 • AC Loading

Table 2-163 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V_REF(typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

V_REF– 0.2

V_REF+ 0.2

1.5

1.485

30

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-164 • SSTL3- Class II

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V,

V_REF= 1.5 V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.34

3.69

3.24

t_ZHS

3.91

3.32

2.92

Units

ns

Std.

–1

2.07

1.76

1.54

1.25

1.06

0.93

2.10

1.79

1.57

1.67

1.42

1.25

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-202

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Differential I/O Characteristics

Configuration of the I/O modules as a differential pair is handled by the Actel Designer

software when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with these standards.

LVDS

Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-126. The building blocks of the LVDS transmitter–receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

165 Ω

ZO = 50 Ω

140 Ω

ZO = 50 Ω

INBUF_LVDS

+

–

100 Ω

N

Figure 2-126 • LVDS Circuit Diagram and Board-Level Implementation

Table 2-165 • Minimum and Maximum DC Input and Output Levels

DC Parameter

Description

Supply Voltage

Min.

2.375

0.9

Typ.

2.5

Max.

Units

V

V_CCI

V_OL

V_OH

2.625

1.25

1.6

Output LOW Voltage

Input HIGH Voltage

1.075

1.425

0.91

V

1.25

0.65

0

V

3

I_OL

Input LOW Voltage

1.16

2.925

10

mA

V

3

I_OH

Output HIGH Voltage

Input Voltage

V_I

4

I_IL

Input LOW Voltage

μA

mV

V

4

I_IH

Output HIGH Voltage

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

10

V_ODIFF

V_OCM

V_ICM

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

V_IDIFF

mV

Notes:

1. 5%

2. Differential input voltage = 350 mV

Preliminary v1.7

2-203

Device Architecture

Table 2-166 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V

_REF(typ.) (V)

1.075

1.325

Cross point

–

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-167 • LVDS

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Pro I/Os

Speed Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

2.10

1.79

1.57

1.82

1.55

1.36

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

BLVDS/M-LVDS

Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations can

contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by BLVDS and M-LVDS to accommodate the loading. The driver

requires series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus, since the driver can be located anywhere on the bus. These

configurations can be implemented using TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-127. The input and output

buffer delays are available in the LVDS section in Table 2-168.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case industrial operating conditions at the farthest receiver:

R_S= 60 Ω and R_T= 70 Ω, given Z₀= 50 Ω (2") and Z_stub= 50 Ω (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-127 • BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

2-204

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-128. The building blocks of the LVPECL transmitter–receiver are one transmitter macro,

one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver

end. The values for the three driver resistors are different from those used in the LVDS

implementation because the output standard specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

OUTBUF_LVPECL

P

100 Ω

ZO = 50 Ω

187 W

ZO = 50 Ω

INBUF_LVPECL

+

–

100 Ω

N

Figure 2-128 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-168 • Minimum and Maximum DC Input and Output Levels

DC Parameter

V_CCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

Min.

Max.

Units

V

3.0

3.3

3.6

V_OL

Output LOW Voltage

0.96

1.8

1.27

2.11

3.3

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.9

V

V_OH

Output HIGH Voltage

V

V_IL, V_IH

V_ODIFF

V_OCM

Input LOW, Input HIGH Voltages

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

0

V

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

V

V_ICM

V

V_IDIFF

mV

Table 2-169 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

V_REF(typ.) (V)

1.64

1.94

Cross point

–

Note: *Measuring point = V_trip. See Table 2-87 on page 2-165 for a complete table of trip points.

Timing Characteristics

Table 2-170 • LVPECL

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Pro I/Os

Speed Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

Units

Std.

–1

2.14

1.82

1.60

1.63

1.39

1.22

ns

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-205

Device Architecture

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

Preset

L

X

D

DOUT

X

Data_out

PRE

DFN1E1P1

F

PRE

Y

Core

Array

E

X

Data

Enable

CLK

X

C

D

Q

X

D

Q

DFN1E1P1

G

X

E

X

E

X

B

EOUT

H

I

X

A

PRE

D

J

X

Q

DFN1E1P1

E

K

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive Edge Triggered

CLKBUF

INBUF

Figure 2-129 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

2-206

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-171 • Parameter Definitions and Measuring Nodes

Parameter

Measuring Nodes

(from, to)*

Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L,DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

I, H

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

I, H

A, E

C, A

B, A

D, E

D, A

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Note: *See Figure 2-129 on page 2-206 for more information.

Preliminary v1.7

2-207

Device Architecture

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

DOUT

FF

Data_out

Y

Core

Array

D

Q

D

Q

Data

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

CLR

LL

HH

AA

DD

JJ

D

Q

CLR

DFN1E1C1

KK

E

CLR

Data Input I/O Register with

Active High Enable

Active High Clear

Positive Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive Edge Triggered

INBUF

CLKBUF

Figure 2-130 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

2-208

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 2-172 • Parameter Definitions and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

FF, HH

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

GG, HH

LL, DOUT

LL, HH

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

JJ, HH

t_OESUE

KK, HH

II, EOUT

II, HH

t_OEHE

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Note: *See Figure 2-130 on page 2-208 for more information.

Preliminary v1.7

2-209

Device Architecture

Input Register

t_ICKMPWHt_ICKMPWL

50%

t_ISUD

50%

1

CLK

t_IHD

50%

0

Data

t_IREMPRE

t_IRECPRE

Enable

Preset

50%

t_IWPRE

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-131 • Input Register Timing Diagram

Timing Characteristics

Table 2-173 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_ICLKQ

Description

–2

–1

Std. Units

Clock-to-Q of the Input Data Register

0.24 0.27 0.32

0.26 0.30 0.35

0.00 0.00 0.00

0.37 0.42 0.50

0.00 0.00 0.00

0.45 0.52 0.61

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

Enable Hold Time for the Input Data Register

t_IHE

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30

Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

0.36 0.41 0.48

0.32 0.37 0.43

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-210

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

1

0

Data_out

nable

Preset

50%

t_OREMPRE

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_OWCLR

t_ORECCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-132 • Output Register Timing Diagram

Timing Characteristics Output Enable Register

Table 2-174 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_OCLKQ

t_OSUD

Description

–2

–1

Std. Units

Clock-to-Q of the Output Data Register

0.59 0.67 0.79

0.31 0.36 0.42

0.00 0.00 0.00

0.44 0.50 0.59

0.00 0.00 0.00

0.80 0.91 1.07

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

ns

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

t_OHE

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

Asynchronous Clear Minimum Pulse Width for the Output Data 0.22 0.25 0.30

Register

t_OWPRE

Asynchronous Preset Minimum Pulse Width for the Output Data 0.22 0.25 0.30

Register

ns

t_OCKMPWHClock Minimum Pulse Width HIGH for the Output Data Register

0.36 0.41 0.48

Preliminary v1.7

2-211

Device Architecture

Table 2-174 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Description

t_OCKMPWLClock Minimum Pulse Width LOW for the Output Data Register

Parameter

–2

–1

Std. Units

ns

0.32 0.37 0.43

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

t_OECKMPWHt_OECKMPWL

50%

1

CLK

t_OESUDt_OEHD

50%

0

D_Enable

Enable

Preset

50%

t_OEREMPRE

50%

t_OEWPRE

50%

t_OERECPRE

50%

t_OESUEOEHE

t

t_OEREMCLR

50%

t_OEWCLRt_OERECCLR

50%

Clear

EOUT

t_OEPRE2Q

50%

t_OECLR2Q

50%

t_OECLKQ

Figure 2-133 • Output Enable Register Timing Diagram

2-212

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Timing Characteristics

Table 2-175 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_OECLKQ

t_OESUD

Description

–2

–1

Std. Units

Clock-to-Q of the Output Enable Register

0.44 0.51 0.59

0.31 0.36 0.42

0.00 0.00 0.00

0.44 0.50 0.58

0.00 0.00 0.00

0.67 0.76 0.89

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

ns

Data Setup Time for the Output Enable Register

t_OEHD

Data Hold Time for the Output Enable Register

t_OESUE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

t_OEHE

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLR

t_OERECCLR

t_OEREMPRE

t_OERECPRE

t_OEWCLR

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Asynchronous Clear Minimum Pulse Width for the Output Enable 0.22 0.25 0.30

Register

t_OEWPRE

Asynchronous Preset Minimum Pulse Width for the Output Enable 0.22 0.25 0.30

Register

ns

t_OECKMPWHClock Minimum Pulse Width HIGH for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width LOW for the Output Enable Register

0.36 0.41 0.48

0.32 0.37 0.43

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-213

Device Architecture

DDR Module Specifications

Input DDR Module

Input DDR

A

D

Out_QF

(to core)

Data

INBUF

FF1

E

B

C

Out_QR

(to core)

CLK

CLKBUF

FF2

CLR

INBUF

DDR_IN

Figure 2-134 • Input DDR Timing Model

Table 2-176 • Parameter Definitions

Parameter Name

Parameter Definition

Clock-to-Out Out_QR

Measuring Nodes (from, to)

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

B, D

B, E

A, B

C, D

C, E

C, B

Clock-to-Out Out_QF

Data Setup Time of DDR Input

Data Hold Time of DDR Input

Clear-to-Out Out_QR

Clear-to-Out Out_QF

Clear Removal

t_DDRIHD

t_DDRICLR2Q1

t_DDRICLR2Q2

t_DDRIREMCLR

t_DDRIRECCLR

Clear Recovery

2-214

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

CLK

t

DDRISUD

DDRIHD

Data

CLR

1

2

3

4

5

6

7

8

9

t

DDRIRECCLR

t

DDRIREMCLR

t

DDRICLKQ1

t

DDRICLR2Q1

Out_QF

Out_QR

6

7

2

4

t

DDRICLKQ2

DDRICLR2Q2

3

5

Figure 2-135 • Input DDR Timing Diagram

Timing Characteristics

Table 2-177 • Input DDR Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Description

–2

–1

Std.

0.52

0.37

0.38

0.00

0.76

0.62

0.00

0.30

0.48

0.43

Units

Clock-to-Out Out_QR for Input DDR

0.39

0.27

0.28

0.00

0.57

0.46

0.00

0.22

0.36

0.32

0.44

0.31

0.32

0.00

0.65

0.53

0.00

0.25

0.41

0.37

ns

Clock-to-Out Out_QF for Input DDR

Data Setup for Input DDR

ns

t_DDRIHD

Data Hold for Input DDR

ns

t_DDRICLR2Q1

t_DDRICLR2Q2

t_DDRIREMCLR

t_DDRIRECCLR

t_DDRIWCLR

Asynchronous Clear-to-Out Out_QR for Input DDR

Asynchronous Clear-to-Out Out_QF for Input DDR

Asynchronous Clear Removal Time for Input DDR

Asynchronous Clear Recovery Time for Input DDR

Asynchronous Clear Minimum Pulse Width for Input DDR

ns

t_DDRICKMPWHClock Minimum Pulse Width HIGH for Input DDR

t_DDRICKMPWLClock Minimum Pulse Width LOW for Input DDR

ns

F_DDRIMAX

Maximum Frequency for Input DDR

MHz

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-215

Device Architecture

Output DDR

A

Data_F

(from core)

X

FF1

FF2

Out

B

C

D

0

1

X

CLK

E

CLKBUF

X

OUTBUF

Data_R

(from core)

B

C

X

CLR

INBUF

DDR_OUT

Figure 2-136 • Output DDR Timing Model

Table 2-178 • Parameter Definitions

Parameter Name

t_DDROCLKQ

Parameter Definition

Clock-to-Out

Measuring Nodes (From, To)

B, E

C, E

C, B

A, B

D, B

A, B

D, B

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROSUD1

Asynchronous Clear-to-Out

Clear Removal

Clear Recovery

Data Setup Data_F

Data Setup Data_R

Data Hold Data_F

Data Hold Data_R

t_DDROSUD2

t_DDROHD1

t_DDROHD2

2-216

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

CLK

t_DDROHD2

t_DDROSUD2

3

4

9

5

Data_F

1

2

t_DDROHD1

t_DDROSUD1

Data_R 6

CLR

7

8

10

11

t_DDRORECCLR

t_DDROREMCLR

t_DDROCLKQ

t_DDROCLR2Q

Out

7

2

8

3

9

4

10

Figure 2-137 • Output DDR Timing Diagram

Timing Characteristics

Table 2-179 • Output DDR Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_DDROCLKQ

t_DDROSUD1

t_DDROSUD2

t_DDROHD1

Description

–2

–1

Std. Units

Clock-to-Out of DDR for Output DDR

0.70

0.38

0.00

0.80

0.00

0.22

0.36

0.32

0.80

0.43

0.00

0.91

0.00

0.25

0.41

0.37

0.94

0.51

0.00

1.07

0.00

0.30

0.48

0.43

ns

Data_F Data Setup for Output DDR

Data_R Data Setup for Output DDR

ns

Data_F Data Hold for Output DDR

ns

t_DDROHD2

Data_R Data Hold for Output DDR

ns

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROWCLR1

t_DDROCKMPWH

t_DDROCKMPWL

F_DDOMAX

Asynchronous Clear-to-Out for Output DDR

Asynchronous Clear Removal Time for Output DDR

Asynchronous Clear Recovery Time for Output DDR

Asynchronous Clear Minimum Pulse Width for Output DDR

Clock Minimum Pulse Width HIGH for the Output DDR

Clock Minimum Pulse Width LOW for the Output DDR

Maximum Frequency for the Output DDR

ns

MHz

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Preliminary v1.7

2-217

Device Architecture

Pin Descriptions

Supply Pins

GND

Ground

Ground supply voltage to the core, I/O outputs, and I/O logic.

GNDQ Ground (quiet)

Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is

decoupled from the simultaneous switching noise originated from the output buffer ground

domain. This minimizes the noise transfer within the package and improves input signal integrity.

GNDQ needs to always be connected on the board to GND. Note: In FG256, FG484, and FG676

packages, GNDQ and GND pins are connected within the package and are labeled as GND pins in

the respective package pin assignment tables.

ADCGNDREF

Analog Reference Ground

Analog ground reference used by the ADC. This pad should be connected to a quiet analog

ground.

GNDA

Ground (analog)

Quiet ground supply voltage to the Analog Block of Fusion devices. The use of a separate analog

ground helps isolate the analog functionality of the Fusion device from any digital switching noise.

A 0.2 V maximum differential voltage between GND and GNDA/GNDQ should apply to system

implementation.

GNDAQ

Ground (analog quiet)

Quiet ground supply voltage to the analog I/O of Fusion devices. The use of a separate analog

ground helps isolate the analog functionality of the Fusion device from any digital switching noise.

A 0.2 V maximum differential voltage between GND and GNDA/GNDQ should apply to system

implementation. Note: In FG256, FG484, and FG676 packages, GNDAQ and GNDA pins are

connected within the package and are labeled as GNDA pins in the respective package pin

assignment tables.

GNDNVM

Ground supply used by the Fusion device's flash memory block module(s).

GNDOSC Oscillator Ground

Ground supply for both integrated RC oscillator and crystal oscillator circuit.

Analog Power Supply (1.5 V)

A 1.5 V analog power supply input should be used to provide this input.

Analog Power Supply (3.3 V)

3.3 V clean analog power supply input for use by the 3.3 V portion of the analog circuitry.

Negative 3.3 V Output

Flash Memory Ground

V

CC15A

V

CC33A

V

CC33N

This is the –3.3 V output from the voltage converter. A 2.2 µF capacitor must be connected from

this pin to ground.

V

Analog Power Supply (3.3 V)

3.3 V clean analog power supply input for use by the analog charge pump. To avoid high current

draw, V_CC33PMPshould be powered up before or simultaneously with V_CC33A

Flash Memory Block Power Supply (1.5 V)

1.5 V power supply input used by the Fusion device's flash memory block module(s). To avoid high

CC33PMP

.

V

CCNVM

current draw, V_CCshould be powered up before or simultaneously with V_CCNVM

.

2-218

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

V

Oscillator Power Supply (3.3 V)

Power supply for both integrated RC oscillator and crystal oscillator circuit.

Core Supply Voltage

CCOSC

V

CC

Supply voltage to the FPGA core, nominally 1.5 V. V_CCis also required for powering the JTAG state

machine, in addition to V_JTAG. Even when a Fusion device is in bypass mode in a JTAG chain of

interconnected devices, both V_CCand V_JTAGmust remain powered to allow JTAG signals to pass

through the Fusion device.

V

Bx

I/O Supply Voltage

CCI

Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are

either four (AFS090 and AFS250) or five (AFS600 and AFS1500) I/O banks on the Fusion devices plus

a dedicated V_JTAGbank.

Each bank can have a separate V_CCIconnection. All I/Os in a bank will run off the same V_CCIBx

supply. V_CCIcan be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their

corresponding V_CCIpins tied to GND.

V

PLL Supply Voltage

CCPLA/B

Supply voltage to analog PLL, nominally 1.5 V, where A and B refer to the PLL. AFS090 and AFS250

each have a single PLL. The AFS600 and AFS1500 devices each have two PLLs. Actel recommends

tying V_CCPLXto V_CCand using proper filtering circuits to decouple V_CCnoise from PLL.

If unused, V_CCPLA/Bshould be tied to GND.

V

Ground for West and East PLL

COMPLA/B

V_COMPLAis the ground of the west PLL (CCC location F) and V_COMPLBis the ground of the east PLL

(CCC location C).

V

JTAG Supply Voltage

JTAG

Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives

greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG

interface is neither used nor planned to be used, the V_JTAGpin together with the TRST pin could be

tied to GND. It should be noted that V_CCis required to be powered for JTAG operation; V_JTAGalone

is insufficient. If a Fusion device is in a JTAG chain of interconnected boards and it is desired to

power down the board containing the Fusion device, this may be done provided both V_JTAGand

V_CCto the Fusion part remain powered; otherwise, JTAG signals will not be able to transition the

Fusion device, even in bypass mode.

V

Programming Supply Voltage

PUMP

Fusion devices support single-voltage ISP programming of the configuration flash and FlashROM.

For programming, V_PUMPshould be in the 3.3 V +/-5% range. During normal device operation,

V_PUMPcan be left floating or can be tied to any voltage between 0 V and 3.6 V.

When the V_PUMPpin is tied to ground, it shuts off the charge pump circuitry, resulting in no sources

of oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in

parallel across V_PUMPand GND, and positioned as close to the FPGA pins as possible.

User-Defined Supply Pins

V

I/O Voltage Reference

REF

Reference voltage for I/O minibanks. Both AFS600 and AFS1500 (north bank only) support Actel Pro

I/O. These I/O banks support voltage reference standard I/O. The V_REFpins are configured by the

user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated as the voltage

reference I/O. Only certain I/O standards require a voltage reference—HSTL (I) and (II), SSTL2 (I) and

(II), SSTL3 (I) and (II), and GTL/GTL+. One V_REFpin can support the number of I/Os available in its

minibank.

Preliminary v1.7

2-219

Device Architecture

VAREF

Analog Reference Voltage

The Fusion device can be configured to generate a 2.56 V internal reference voltage that can be

used by the ADC. While using the internal reference, the reference voltage is output on the VAREF

pin for use as a system reference. If a different reference voltage is required, it can be supplied by

an external source and applied to this pin. The valid range of values that can be supplied to the

ADC is 1.0 V to 3.3 V. When VAREF is internally generated by the Fusion device, a bypass capacitor

must be connected from this pin to ground. The value of the bypass capacitor should be between

3.3 µF and 22 µF, which is based on the needs of the individual designs. The choice of the capacitor

value has an impact on the settling time it takes the VAREF signal to reach the required

specification of 2.56 V to initiate valid conversions by the ADC. If the lower capacitor value is

chosen, the settling time required for VAREF to achieve 2.56 V will be shorter than when selecting

the larger capacitor value. The above range of capacitor values supports the accuracy specification

of the ADC, which is detailed in the datasheet. Designers choosing the smaller capacitor value will

not obtain as much margin in the accuracy as that achieved with a larger capacitor value.

Depending on the capacitor value selected in the Analog System Builder, a tool in Libero IDE, an

automatic delay circuit will be generated using logic tiles available within the FPGA to ensure that

VAREF has achieved the 2.56 V value. Actel recommends customers use 10 µF as the value of the

bypass capacitor. Designers choosing to use an external VAREF need to ensure that a stable and

clean VAREF source is supplied to the VAREF pin before initiating conversions by the ADC.

Designers should also make sure that the ADCRESET signal is deasserted before initiating valid

conversions.²

User Pins

I/O

User Input/Output

The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal

levels are compatible with the I/O standard selected. Unused I/O pins are configured as inputs with

pull-up resistors.

During programming, I/Os become tristated and weakly pulled up to V_CCI. With the V_CCIand V_CC

supplies continuously powered up, when the device transitions from programming to operating

mode, the I/Os get instantly configured to the desired user configuration.

Axy

Analog Input/Output

Analog I/O pin, where x is the analog pad type (C = current pad, G = Gate driver pad,

T = Temperature pad, V = Voltage pad) and y is the Analog Quad number (0 to 9). There is a

minimum 1 MΩ to ground on AV, AC, and AT. This pin can be left floating when it is unused.

ATRTNx

Temperature Monitor Return

AT returns are the returns for the temperature sensors. The cathode terminal of the external diodes

should be connected to these pins. There is one analog return pin for every two Analog Quads. The

x in the ATRTNx designator indicates the quad pairing (x = 0 for AQ1 and AQ2, x = 1 for AQ2 and

AQ3, ..., x = 4 for AQ8 and AQ9). The signals that drive these pins are called out as ATRETUNxy in

the software (where x and y refer to the quads that share the return signal). ATRTN is internally

connected to ground. It can be left floating when it is unused.

GL

Globals

GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to

the global network (spines). Additionally, the global I/Os can be used as Pro I/Os since they have

identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more

detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits" section on

page 2-24.

Refer to the "User I/O Naming Convention" section on page 2-157 for a description of naming of

global pins.

2. The ADC is functional with an external reference down to 1V, however to meet the performance

parameters highlighted in the datasheet refer to the VAREF specification in Table 3-2 on page 3-3.

2-220

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

JTAG Pins

Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). V_CCmust also be powered for the JTAG state machine to

operate, even if the device is in bypass mode; V_JTAGalone is insufficient. Both V_JTAGand V_CCto the

Fusion part must be supplied to allow JTAG signals to transition the Fusion device.

Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply

selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor

planned to be used, the V_JTAGpin together with the TRST pin could be tied to GND.

TCK

Test Clock

Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal

pull-up/-down resistor. If JTAG is not used, Actel recommends tying off TCK to GND or V_JTAG

through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an

undesired state.

Note that to operate at all V_JTAGvoltages, 500 Ω to 1 kΩ will satisfy the requirements. Refer to

Table 2-180 for more information.

Table 2-180 • Recommended Tie-Off Values for the TCK and TRST Pins

V_JTAG

Tie-Off Resistance^{2, 3}

V_JTAGat 3.3 V

200 Ω to 1 kΩ

V_JTAGat 2.5 V

200 Ω to 1 kΩ

V_JTAGat 1.8 V

V_JTAGat 1.5 V

Notes:

500 Ω to 1 kΩ

1. Equivalent parallel resistance if more than one device is on JTAG chain.

2. The TCK pin can be pulled up/down.

3. The TRST pin can only be pulled down.

TDI

Test Data Input

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up

resistor on the TDI pin.

TDO

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

TMS Test Mode Select

Test Data Output

The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an

internal weak pull-up resistor on the TMS pin.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary

scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an

external pull-down resistor could be included to ensure the TAP is held in reset mode. The resistor

values must be chosen from Table 2-180 and must satisfy the parallel resistance value requirement.

The values in Table 2-180 correspond to the resistor recommended when a single device is used and

to the equivalent parallel resistor when multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entering an undesired JTAG state. In

such cases, Actel recommends tying off TRST to GND through a resistor placed close to the FPGA

pin.

Note that to operate at all V_JTAGvoltages, 500 Ω to 1 kΩ will satisfy the requirements.

Preliminary v1.7

2-221

Device Architecture

Special Function Pins

NC

No Connect

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or

can be left floating with no effect on the operation of the device.

DC

This pin should not be connected to any signals on the PCB. These pins should be left unconnected.

NCAP Negative Capacitor

Don't Connect

Negative Capacitor is where the negative terminal of the charge pump capacitor is connected. A

capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP.

PCAP

Positive Capacitor

Positive Capacitor is where the positive terminal of the charge pump capacitor is connected. A

capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP.

PUB

Push Button

Push button is the connection for the external momentary switch used to turn on the 1.5 V voltage

regulator and can be floating if not used.

PTBASE

Pass Transistor Base

Pass Transistor Base is the control signal of the voltage regulator. This pin should be connected to

the base of the external pass transistor used with the 1.5 V internal voltage regulator and can be

floating if not used.

PTEM

Pass Transistor Emitter

Pass Transistor Emitter is the feedback input of the voltage regulator.

This pin should be connected to the emitter of the external pass transistor used with the 1.5 V

internal voltage regulator and can be floating if not used.

XTAL1

Crystal Oscillator Circuit Input

Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network,

or external clock input. When using an external crystal or ceramic oscillator, external capacitors are

also recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value).

If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected.

XTAL2

Crystal Oscillator Circuit Input

Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network,

or external clock input. When using an external crystal or ceramic oscillator, external capacitors are

also recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value).

If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected.

Software Tools and Programming

Overview of Tools Flow

The Fusion family of FPGAs is fully supported by both Actel Libero IDE and Designer FPGA

development software. Actel Libero IDE is an integrated design manager that seamlessly integrates

design tools while guiding the user through the design flow, managing all design and log files, and

passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both

schematic and HDL synthesis into a single flow and verify the entire design in a single environment

(see the Libero IDE flow diagram located on the Actel website). Libero IDE includes Synplify^®AE

from Synplicity,^®ViewDraw^®AE from Mentor Graphics,^®ModelSim^®HDL Simulator from Mentor

Graphics, WaveFormer Lite™ AE from SynaptiCAD,^®PALACE™ AE Physical Synthesis from Magma

Design Automation,™ and Designer software from Actel.

2-222

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend

support tools for FPGA development. The Designer software includes the following:

•

SmartTime – a world-class integrated static timing analyzer and constraints editor that

supports timing-driven place-and-route

•

NetlistViewer – a design netlist schematic viewer

ChipPlanner – a graphical floorplanning viewer and editor

SmartPower – a sophisticated power analysis environment that gives designers the ability to

quickly determine the power consumption of an FPGA or its components

•

PinEditor – a graphical application for editing pin assignments and I/O attributes

I/O Attribute Editor – displays all assigned and unassigned I/O macros and their attributes in

a spreadsheet format

With the Designer software, a user can lock the design pins before layout while minimally

impacting the results of place-and-route. Additionally, the Actel back-annotation flow is

compatible with all major simulators. Included in the Designer software is SmartGen core

generator, which easily creates commonly used logic functions for implementation into your

Fusion-based schematic or HDL design.

Actel Designer software is compatible with the most popular FPGA design entry and verification

tools from EDA vendors, such as Cadence,^®Magma,^®Mentor Graphics, Synopsys, and Synplicity.

The Designer software is available for both the Windows^®and UNIX operating systems.

CoreMP7 and Cortex-M1 Software Tools

CoreConsole is the Intellectual Property Deployment Platform (IDP) that assists the developer in

programming the soft ARM core onto M7 (CoreMP7) and M1 (Cortex-M1) Fusion devices.

CoreConsole provides the seamless environment to work with the Libero IDE and Designer FPGA

development software tools concurrently.

Security

Fusion devices have a built-in 128-bit AES decryption core. The decryption core facilitates secure, in-

system programming of the FPGA core array fabric and the FlashROM. The FlashROM and the FPGA

core fabric can be programmed independently from each other, allowing the FlashROM to be

updated without the need for change to the FPGA core fabric. The AES master key is stored in on-

chip nonvolatile memory (flash). The AES master key can be preloaded into parts in a secure

programming environment (such as the Actel in-house programming center), and then "blank"

parts can be shipped to an untrusted programming or manufacturing center for final

personalization with an AES-encrypted bitstream. Late stage product changes or personalization

can be implemented easily and securely by simply sending a STAPL file with AES-encrypted data.

Secure remote field updates over public networks (such as the Internet) are possible by sending and

programming a STAPL file with AES-encrypted data. For more information, refer to the Fusion

Security application note.

128-Bit AES Decryption

The 128-bit AES standard (FIPS-192) block cipher is the National Institute of Standards and

Technology (NIST) replacement for DES (Data Encryption Standard FIPS46-2). AES has been

designed to protect sensitive government information well into the 21st century. It replaces the

aging DES, which NIST adopted in 1977 as a Federal Information Processing Standard used by

federal agencies to protect sensitive, unclassified information. The 128-bit AES standard has

3.4 × 10³⁸possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion

years to crack 128-bit AES cipher text using exhaustive techniques. Keys are stored (securely) in

Fusion devices in nonvolatile flash memory. All programming files sent to the device can be

authenticated by the part prior to programming to ensure that bad programming data is not

loaded into the part that may possibly damage it. All programming verification is performed on-

chip, ensuring that the contents of Fusion devices remain secure.

Preliminary v1.7

2-223

Device Architecture

AES decryption can also be used on the 1,024-bit FlashROM to allow for secure remote updates of

the FlashROM contents. This allows for easy, secure support for subscription model products. See

the application note Fusion Security for more details.

AES for Flash Memory

AES decryption can also be used on the flash memory blocks. This allows for the secure update of

the flash memory blocks. During runtime, the encrypted data can be clocked in via the JTAG

interface. The data can be passed through the internal AES decryption engine, and the decrypted

data can then be stored in the flash memory block.

Programming

Programming can be performed using various programming tools, such as Silicon Sculptor II (BP

Micro Systems) or FlashPro3 (Actel).

The user can generate STP programming files from the Designer software and can use these files to

program a device.

Fusion devices can be programmed in-system. During programming, V_CCOSCis needed in order to

power the internal 100 MHz oscillator. This oscillator is used as a source for the 20 MHz oscillator

that is used to drive the charge pump for programming.

ISP

Fusion devices support IEEE 1532 ISP via JTAG and require a single V_PUMPvoltage of 3.3 V during

programming. In addition, programming via a microcontroller in a target system can be achieved.

Refer to the standard or the In-System Programming (ISP) of Actel's Low-Power Flash Devices Using

FlashPro3 document for more details.

JTAG IEEE 1532

Programming with IEEE 1532

Fusion devices support the JTAG-based IEEE1532 standard for ISP. As part of this support, when a

Fusion device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by

keeping the global IO_EN signal deactivated, which also has the effect of disabling the input

buffers. Consequently, the SAMPLE instruction will have no effect while the Fusion device is in this

unprogrammed state—different behavior from that of the ProASIC^PLUS®device family. This is done

because SAMPLE is defined in the IEEE1532 specification as a noninvasive instruction. If the input

buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be

a noninvasive instruction. Refer to the standard or the In-System Programming (ISP) of Actel's Low-

Power Flash Devices Using FlashPro3 document for more details.

Boundary Scan

Fusion devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture

and the set of mechanisms for boundary scan testing. The basic Fusion boundary scan logic circuit is

composed of the test access port (TAP) controller, test data registers, and instruction register

(Figure 2-138 on page 2-226). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST,

SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-182 on page 2-226).

Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input),

TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS,

TDI, and TRST are equipped with pull-up resistors to ensure proper operation when no input data is

supplied to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins"

section on page 2-221 for pull-up/-down recommendations for TDO and TCK pins. The TAP

controller is a 4-bit state machine (16 states) that operates as shown in Figure 2-138 on page 2-226.

The 1s and 0s represent the values that must be present on TMS at a rising edge of TCK for the

2-224

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

given state transition to occur. IR and DR indicate that the instruction register or the data register is

operating in that state.

Table 2-181 • TRST and TCK Pull-Down Recommendations

V_JTAG

Tie-Off Resistance*

200 Ω to 1 kΩ

500 Ω to 1 kΩ

V_JTAGat 3.3 V

V_JTAGat 2.5 V

V_JTAGat 1.8 V

V_JTAGat 1.5 V

Note: *Equivalent parallel resistance if more than one device is on JTAG chain.

The TAP controller receives two control inputs (TMS and TCK) and generates control and clock

signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-

Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must

remain HIGH for five TCK cycles. The TRST pin can also be used to asynchronously place the TAP

controller in the Test-Logic-Reset state.

Fusion devices support three types of test data registers: bypass, device identification, and

boundary scan. The bypass register is selected when no other register needs to be accessed in a

device. This speeds up test data transfer to other devices in a test data path. The 32-bit device

identification register is a shift register with four fields (LSB, ID number, part number, and version).

The boundary scan register observes and controls the state of each I/O pin. Each I/O cell has three

boundary scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin.

The serial pins are used to serially connect all the boundary scan register cells in a device into a

boundary scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel

ports are connected to the internal core logic I/O tile and the input, output, and control ports of an

I/O buffer to capture and load data into the register to control or observe the logic state of each

I/O.

Preliminary v1.7

2-225

Device Architecture

I/O

Test Data

Registers

Bypass Register

Instruction

Register

TAP

Controller

Device

Logic

I/O

Figure 2-138 • Boundary Scan Chain in Fusion

Table 2-182 • Boundary Scan Opcodes

Hex Opcode

EXTEST

00

07

0E

01

0F

05

FF

HIGHZ

USERCODE

SAMPLE/PRELOAD

IDCODE

CLAMP

BYPASS

2-226

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

IEEE 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays

to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/Os"

section on page 2-130 for more details.

Timing Characteristics

Table 2-183 • JTAG 1532

Commercial-Case Conditions: T_J= 70°C, V_CC= 1.425 V

Parameter

t_DISU

Description

Test Data Input Setup Time

Test Data Input Hold Time

Test Mode Select Setup Time

Test Mode Select Hold Time

Clock to Q (data out)

–2

–1

Std.

0.67

1.33

0.67

1.33

8.00

26.67

19.00

0.00

0.27

TBD

Units

ns

0.50

1.00

0.50

1.00

6.00

20.00

25.00

0.00

0.20

TBD

0.57

1.13

0.57

1.13

6.80

22.67

22.00

0.00

0.23

TBD

t_DIHD

ns

t_TMSSU

ns

t_TMDHD

t_TCK2Q

ns

t_RSTB2Q

F_TCKMAX

t_TRSTREM

t_TRSTREC

t_TRSTMPW

Reset to Q (data out)

ns

TCK Maximum Frequency

ResetB Removal Time

MHz

ns

ResetB Recovery Time

ns

ResetB Minimum Pulse

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to

Table 3-7 on page 3-9.

Preliminary v1.7

2-227

Device Architecture

Part Number and Revision Date

Part Number 51700092-014-0

Revised October 2008

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version

Changes in Current Version (Preliminary v1.7)

Page

Advance v1.6

(August 2008)

The version number category was changed from Advance to Preliminary, which

means the datasheet contains information based on simulation and/or initial

characterization. The information is believed to be correct, but changes are

possible.

N/A

The following updates were made to Table 2-38 •Temperature Data Format:

2-98

Temperature

Digital Output

213

283

358

00 1111 1101

01 0001 1011

01 0110 0110 – only the digital output was updated.

Temperature 358 remains in the temperature column.

In Advance v1.2, the "V_AREFAnalog Reference Voltage" pin description was

significantly updated but the change was not noted in the change table.

2-220

Advance v1.5

(July 2008)

The references to the Peripherals User’s Guide in the "No-Glitch MUX

(NGMUX)" section and "Voltage Regulator Power Supply Monitor (VRPSM)"

section were changed to Fusion Handbook.

2-32,

2-40

Advance v1.4

(July 2008)

The title of the datasheet changed from Actel Programmable System Chips to

Actel Fusion Mixed-Signal FPGAs. In addition, all instances of programmable

system chip were changed to mixed-signal FPGA.

N/A

Advance v1.2

(June 2008)

The "ADC Description" section was significantly updated. Please review

carefully.

2-103

2-54

Advance v1.1

(May 2008)

Table 2-25 · Flash Memory Block Timing was significantly updated.

The "V_AREFAnalog Reference Voltage" pin description section was significantly

update. Please review it carefully.

2-220

Table 2-45 · ADC Interface Timingwas significantly updated.

2-109

2-128

Table 2-56 · Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x =

1), and AT (x = 3) was significantly updated.

The following sentence was deleted from the "Voltage Monitor" section:

The Analog Quad inputs are tolerant up to 12 V + 10%.

2-86

Advance v1.0

(January 2008)

The following text was incorrect and therefore deleted:

2-204

VCC33A

Analog Power Filter

Analog power pin for the analog power supply low-pass filter. An external 100

pF capacitor should be connected between this pin and ground.

There is still a description of V_CC33Aon page 2-218.

Advance v0.9

(October 2007)

All Timing Characteristics tables were updated. For the Differential I/O

Standards, the Standard I/O support tables are new.

N/A

Table 2-3 · Array Coordinates was updated to change the max x and y values

Table 2-13 · Fusion CCC/PLL Specification was updated.

2-9

2-31

2-228

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Previous Version

Changes in Current Version (Preliminary v1.7)

Page

Advance v0.9

(continued)

A note was added to Table 2-16 · RTC ACM Memory Map.

2-36

A reference to the Peripheral’s User’s Guide was added to the "Voltage

Regulator Power Supply Monitor (VRPSM)" section.

2-40

2-54

2-57

2-82

2-86

In Table 2-25 · Flash Memory Block Timing, the commercial conditions were

updated.

In Table 2-26 · FlashROM Access Time, the commercial conditions were missing

and have been added below the title of the table.

In Table 2-36 · Analog Block Pin Description, the function description was

updated for the ADCRESET.

In the "Voltage Monitor" section, the following sentence originally had 10%

and it was changed to +10%.

The Analog Quad inputs are tolerant up to 12 V + 10%.

In addition, this statement was deleted from the datasheet:

Each I/O will draw power when connected to power (3 mA at 3 V).

The "Terminology" section is new.

2-88

2-90

The "Current Monitor" section was significantly updated. Figure 2-71 · Timing

Diagram for Current Monitor Strobe to Figure 2-73 · Negative Current Monitor

and Table 2-37 · Recommended Resistor for Different Current Range

Measurement are new.

The "ADC Description" section was updated to add the "Terminology" section.

2-93

2-94

In the "Gate Driver" section, 25 mA was changed to 20 mA and 1.5 MHz was

changed to 1.3 MHz. In addition, the following sentence was deleted:

The maximum AG pad switching frequency is 1.25 MHz.

The "Temperature Monitor" section was updated to rewrite most of the text

and add Figure 2-77, Figure 2-78, and Figure 2-38 · Temperature Data Format.

2-96

2-98

In Table 2-38 · Temperature Data Format, the temperature K column was

changed for 85°C from 538 to 358.

In Table 2-45 · ADC Interface Timing, "Typical-Case" was changed to "Worst- 2-109

Case."

The "ADC Interface Timing" section is new.

2-109

2-115

2-218

2-219

2-218

Table 2-46 · Analog Channel Specifications was updated.

The "V_CC15AAnalog Power Supply (1.5 V)" section was updated.

The "V_CCPLA/BPLL Supply Voltage" section is new.

In "V_CCNVMFlash Memory Block Power Supply (1.5 V)" section, supply was

changed to supply input.

The "V_CCPLA/BPLL Supply Voltage" pin description was updated to include the 2-219

following statement:

Actel recommends tying V_CCPLXto V_CCand using proper filtering circuits to

decouple V_CCnoise from PLL.

The "V_COMPLA/BGround for West and East PLL" section was updated.

2-219

2-118

In Table 2-47 · ADC Characteristics in Direct Input Mode, the commercial

conditions were updated and note 2 is new.

The V_CC33ACAPsignal name was changed to "XTAL1 Crystal Oscillator Circuit 2-222

Input".

Preliminary v1.7

2-229

Device Architecture

Previous Version

Changes in Current Version (Preliminary v1.7)

Page

Advance v0.9

(continued)

Table 2-48 · Uncalibrated Analog Channel Accuracy*is new.

2-120

Table 2-49 · Calibrated Analog Channel Accuracy ^1,2,3, is new.

2-121

2-122

Table 2-50 · Analog Channel Accuracy: Monitoring Standard Positive Voltages is

new.

In Table 2-57 · Voltage Polarity Control Truth Table—AV (x = 0), AC (x = 1), and 2-128

AT (x = 3)*, the following I/O Bank names were changed:

Hot-Swap changed to Standard

LVDS changed to Advanced

In Table 2-58 · Prescaler Op Amp Power-Down Truth Table—AV (x = 0), AC (x =

1), and AT (x = 3), the following I/O Bank names were changed:

2-129

Hot-Swap changed to Standard

LVDS changed to Advanced

In the title of Table 2-64 · I/O Standards Supported by Bank Type, LVDS I/O was

changed to Advanced I/O.

2-131

2-133

The title was changed from "Fusion Standard, LVDS, and Standard plus Hot-

Swap I/O" to Table 2-68 · Fusion Standard and Advanced I/O Features. In

addition, the table headings were all updated. The heading used to be

Standard and LVDS I/O and was changed to Advanced I/O. Standard Hot-Swap

was changed to just Standard.

Advance v0.9

(continued)

This sentence was deleted from the "Slew Rate Control and Drive Strength"

section:

2-150

The Standard hot-swap I/Os do not support slew rate control. In addition, these

references were changed:

• From: Fusion hot-swap I/O (Table 2-69 on page 2-122) To: Fusion Standard I/O

• From: Fusion LVDS I/O (Table 2-70 on page 2-122) To: Fusion Advanced I/O

The "Cold-Sparing Support" section was significantly updated.

2-140

2-151

In the title of Table 2-75 · Fusion Standard I/O Standards—OUT_DRIVE Settings,

Hot-Swap was changed to Standard.

In the title of Table 2-76 · Fusion Advanced I/O Standards—SLEW and 2-151

OUT_DRIVE Settings, LVDS was changed to Advanced.

In the title of Table 2-80 · Fusion Standard and Advanced I/O Attributes vs. I/O

Standard Applications, LVDS was changed to Advanced.

2-154

In Figure 2-105 · Naming Conventions of Fusion Devices with Three Digital I/O

Banks and Figure 2-106 · Naming Conventions of Fusion Devices with Four I/O

Banks the following names were changed:

2-158

Hot-Swap changed to Standard

LVDS changed to Advanced

The Figure 2-107 · Timing Model was updated.

2-159

2-164

In the notes for Table 2-86 · Summary of Maximum and Minimum DC Input

Levels Applicable to Commercial and Industrial Conditions, T_Jwas changed to

T_A.

Advance v0.7

(January 2007)

Figure 2-16 · Fusion Clocking Options and the "RC Oscillator" section were

updated to change GND_OSC and VCC_OSC to GNDOSC and VCCOSC.

2-20,

2-21

Figure 2-19 · Fusion CCC Options: Global Buffers with the PLL Macro was

updated to change the positions of OADIVRST and OADIVHALF, and a note was

added.

2-25

2-230

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Previous Version

Changes in Current Version (Preliminary v1.7)

Page

Advance v0.7

(continued)

The "Crystal Oscillator" section was updated to include information about

controlling and enabling/disabling the crystal oscillator.

2-22

2-23

2-39

Table 2-11 · Electrical Characteristics of the Crystal Oscillator was updated to

change the typical value of I_DYNXTALfor 0.032–0.2 MHz to 0.19.

The "1.5 V Voltage Regulator" section was updated to add "or floating" in the

paragraph stating that an external pull-down is required on TRST to power

down the VR.

The "1.5 V Voltage Regulator" section was updated to include information on

powering down with the VR.

2-39

2-32

This sentence was updated in the "No-Glitch MUX (NGMUX)" section to delete

GLA:

The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs

(i.e., internal signal or GLC).

In Table 2-14 · NGMUX Configuration and Selection Table, 10 and 11 were

deleted.

2-32

2-37

2-50

2-51

The method to enable sleep mode was updated for bit 0 in Table 2-17 · RTC

Control/Status Register.

S2 was changed to D2 in Figure 2-38 · Read Waveform (Pipe Mode, 32-bit

access) for RD[31:0] was updated.

The definitions for bits 2 and 3 were updated in Table 2-24 · Page Status Bit

Definition.

Figure 2-45 · FlashROM Timing Diagram was updated.

Table 2-26 · FlashROM Access Time is new.

2-57

Figure 2-54 · Write Access After Write onto Same Address, Figure 2-55 · Read

Access After Write onto Same Address, and Figure 2-56 · Write Access After

Read onto Same Address are new.

2-68–

2-70

Table 2-31 · RAM4K9 and Table 2-32 · RAM512X18 were updated.

2-71,

2-72

The VAREF and SAMPLE functions were updated in Table 2-36 · Analog Block

Pin Description.

2-82

2-91

2-94

The title of Figure 2-71 · Timing Diagram for Current Monitor Strobe was

updated to add the word "positive."

The "Gate Driver" section was updated to give information about the

switching rate in High Current Drive mode.

The "ADC Description" section was updated to include information about the 2-103

SAMPLE and BUSY signals and the maximum frequencies for SYSCLK and

ADCCLK. EQ 2-12 was updated to add parentheses around the entire

expression in the denominator.

Table 2-46 · Analog Channel Specifications and Table 2-47 · ADC Characteristics 2-115,

in Direct Input Mode were updated.

2-118

The note was removed from Table 2-55 · Analog Multiplexer Truth Table—AV (x 2-128

= 0), AC (x = 1), and AT (x = 3).

Table 2-63 · Internal Temperature Monitor Control Truth Table is new.

2-129

2-140

The "Cold-Sparing Support" section was updated to add information about

cases where current draw can occur.

Figure 2-98 · Solution 4 was updated.

2-146

Preliminary v1.7

2-231

Device Architecture

Previous Version

Changes in Current Version (Preliminary v1.7)

Page

Advance v0.7

(continued)

Table 2-75 · Fusion Standard I/O Standards—OUT_DRIVE Settings was updated.

2-151

The "GNDA Ground (analog)" section and "GNDAQ Ground (analog quiet)"

section were updated to add information about maximum differential voltage.

2-218

2-220

2-219

N/A

The "V_AREFAnalog Reference Voltage" section and "VPUMP Programming

Supply Voltage" section were updated.

The "V_CCPLA/BPLL Supply Voltage" section was updated to include information

about the east and west PLLs.

The V_COMPLFpin description was deleted.

The "Axy Analog Input/Output" section was updated with information about 2-220

grounding and floating the pin.

The voltage range in the "VPUMP Programming Supply Voltage" section was

updated. The parenthetical reference to "pulled up" was removed from the

statement, "V_PUMPcan be left floating or can be tied (pulled up) to any

voltage between 0 V and 3.6 V."

2-219

The "ATRTNx Temperature Monitor Return" section was updated with

information about grounding and floating the pin.

2-220

2-219

The following text was deleted from the "V_REFI/O Voltage Reference" section:

(all digital I/O).

The "NCAP Negative Capacitor" section and "PCAP Positive Capacitor" section 2-222

were updated to include information about the type of capacitor that is

required to connect the two.

1 µF was changed to 100 pF in the "XTAL1 Crystal Oscillator Circuit Input".

The "Programming" section was updated to include information about V_CCOSC

2-222

2-224

2-30

.

Advance v0.5

(June 2006)

The second paragraph of the "PLL Macro" section was updated to include

information about POWERDOWN.

The description for bit 0 was updated in Table 2-17 · RTC Control/Status

Register.

2-37

3.9 was changed to 7.8 in the "Crystal Oscillator (Xtal Osc)" section.

All function descriptions in Table 2-18 · Signals for VRPSM Macro.

2-38.

2-40

2-42

In Table 2-19 · Flash Memory Block Pin Names, the RD[31:0] description was

updated.

The "RESET" section was updated.

Table 2-35 · FIFO was updated.

2-61

2-64

2-79

2-82

The VAREF function description was updated in Table 2-36 · Analog Block Pin

Description.

The "Voltage Monitor" section was updated to include information about low

power mode and sleep mode.

2-86

The text in the "Current Monitor" section was changed from 2 mV to 1 mV.

2-90

2-94

The "Gate Driver" section was updated to include information about forcing 1

V on the drain.

The "Analog-to-Digital Converter Block" section was updated with the

following statement:

2-100

"All results are MSB justified in the ADC."

2-232

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Previous Version

Changes in Current Version (Preliminary v1.7)

Page

Advance v0.5

(continued)

The information about the ADCSTART signal was updated in the "ADC

Description" section.

2-103

Table 2-46 · Analog Channel Specifications was updated.

2-115

2-118

2-124

2-127

Table 2-47 · ADC Characteristics in Direct Input Mode was updated.

Table 2-51 · ACM Address Decode Table for Analog Quad was updated.

In Table 2-53 · Analog Quad ACM Byte Assignment, the Function and Default

Setting for Bit 6 in Byte 3 was updated.

The "Introduction" section was updated to include information about digital 2-130

inputs, outputs, and bibufs.

In Table 2-69 · Fusion Pro I/O Features, the programmable delay descriptions

were updated for the following features:

2-134

Single-ended receiver

Voltage-referenced differential receiver

LVDS/LVPECL differential receiver features

The "User I/O Naming Convention" section was updated to include "V" and "z"

descriptions

2-157

The "V_CC33PMPAnalog Power Supply (3.3 V)" section was updated to include 2-218

information about avoiding high current draw.

The "V_CCNVMFlash Memory Block Power Supply (1.5 V)" section was updated to 2-218

include information about avoiding high current draw.

The "VMVx I/O Supply Voltage (quiet)" section was updated to include this

statement: VMV and V_CCImust be connected to the same power supply and

V_CCIpins within a given I/O bank.

2-185

The "PUB Push Button" section was updated to include information about

leaving the pin floating if it is not used.

2-222

2-40

The "PTBASE Pass Transistor Base" section was updated to include information

about leaving the pin floating if it is not used.

The "PTEM Pass Transistor Emitter" section was updated to include information

about leaving the pin floating if it is not used.

Advance v0.4

(April 2006)

The "Voltage Regulator Power Supply Monitor (VRPSM)" section was updated.

Advance v0.2

(April 2006)

Figure 2-45 · FlashROM Timing Diagram was updated.

2-57

The "FlashROM" section was updated.

"RESET" section was updated.

2-56

2-61

2-64

2-34

2-42

2-44

"RESET" section was updated.

Figure 2-27 · Real-Time Counter System was updated.

Table 2-19 · Flash Memory Block Pin Names was updated.

Figure 2-32 · Flash Memory Block Diagram was updated to include AUX block

information.

Figure 2-33 · Flash Memory Block Organization was updated to include AUX

block information.

2-45

The note in the "Program Operation" section was updated.

Figure 2-75 · Gate Driver Example was updated.

2-47

2-95

Preliminary v1.7

2-233

Device Architecture

Previous Version

Changes in Current Version (Preliminary v1.7)

Page

Advance v0.2

(continued)

The "Analog Quad ACM Description" section was updated.

2-127

Information about the maximum pad input frequency was added to the "Gate

Driver" section.

2-94

Figure 2-64 · Analog Block Macro was updated.

The "Analog Quad" section was updated.

The "Voltage Monitor" section was updated.

The "Direct Digital Input" section was updated.

The "Current Monitor" section was updated.

2-81

2-84

2-86

2-89

2-90

2-94

Information about the maximum pad input frequency was added to the "Gate

Driver" section.

The "Temperature Monitor" section was updated.

EQ 2-12 is new.

2-96

2-104

2-103

2-20

The "ADC Description" section was updated.

Figure 2-16 · Fusion Clocking Options was updated.

Table 2-46 · Analog Channel Specifications was updated.

2-115

The notes in Table 2-72 · Fusion Standard and Advanced I/O – Hot-Swap and 5 V 2-141

Input Tolerance Capabilities were updated.

The "Simultaneously Switching Outputs and PCB Layout" section is new.

2-147

2-154

LVPECL and LVDS were updated in Table 2-80 · Fusion Standard and Advanced

I/O Attributes vs. I/O Standard Applications.

LVPECL and LVDS were updated in Table 2-81 · Fusion Pro I/O Attributes vs. I/O

Standard Applications.

2-154

The "Timing Model" was updated.

2-159

N/A

All voltage-referenced Minimum and Maximum DC Input and Output Level

tables were updated.

All Timing Characteristic tables were updated

N/A

Table 2-83 · Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions was updated.

2-163

Table 2-79 • Summary of I/O Timing Characteristics – Software Default Settings

was updated.

2-134

Table 2-93 · I/O Output Buffer Maximum Resistances¹was updated.

2-169

2-204

The "BLVDS/M-LVDS" section is new. BLVDS and M-LVDS are two new I/O

standards included in the datasheet.

The "CoreMP7 and Cortex-M1 Software Tools" section is new.

2-223

2-163

Table 2-83 · Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions was updated.

Table 2-79 • Summary of I/O Timing Characteristics – Software Default Settings

was updated.

2-134

Table 2-93 · I/O Output Buffer Maximum Resistances¹was updated.

2-169

2-204

The "BLVDS/M-LVDS" section is new. BLVDS and M-LVDS are two new I/O

standards included in the datasheet.

2-234

Preliminary v1.7

3 – DC and Power Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 3-1 may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Devices should not be operated outside the recommended operating ranges specified in Table 3-2

on page 3-3.

Table 3-1 • Absolute Maximum Ratings

Symbol

V_CC

Parameter

DC core supply voltage

Commercial

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

Industrial

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

Units

V

V_JTAG

V_PUMP

V_CCPLL

V_CCI

JTAG DC voltage

Programming voltage

Analog power supply (PLL)

DC I/O output buffer supply voltage

I/O input voltage¹

VI

–0.3 V to 3.6 V (when I/O hot insertion mode

is enabled)

–0.3 V to (V_CCI+ 1 V) or 3.6 V, whichever

voltage is lower

(when I/O hot-insertion mode is disabled)

V_CC33A

VAREF

V_CC15A

+3.3 V power supply

–0.3 to 3.75²

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

–11.0 to 12.6

–0.3 to 3.75²

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

–11.0 to 12.4

V

Voltage reference for ADC

Digital power supply for the analog system

V_CCNVMEmbedded flash power supply

V_CCOSC

AV, AC

Oscillator power supply

Unpowered,

unconfigured

ADC

reset

asserted

or

Analog input (+16 V to +2 V prescaler range)

–0.4 to 12.6

–0.4 to 3.75

–0.4 to 12.4

–0.4 to 3.75

V

Analog input (+1 V to +0.125 V prescaler

range)

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4.

2. Analog data not valid beyond 3.65 V.

3. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended

operating limits refer to Table 3-2 on page 3-3.

Preliminary v1.7

3-1

DC and Power Characteristics

Table 3-1 • Absolute Maximum Ratings (continued)

Symbol

Parameter

Commercial

–11.0 to 0.4

–3.75 to 0.4

Industrial

–11.0 to 0.4

–3.75 to 0.4

Units

Analog input (–16 V to –2 V prescaler range)

V

Analog input (–1 V to –0.125 V prescaler

range)

Analog input (direct input to ADC)

Digital input

–0.4 to 3.75

–0.4 to 12.6

–11.0 to 12.6

–0.4 to 3.75

–0.4 to 12.4

–11.0 to 12.4

V

AG

Unpowered,

unconfigured

ADC

reset

asserted

or

Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA)

–0.4 to 12.6

–11.0 to 0.4

–0.4 to 12.4

–11.0 to 0.4

V

Low Current Mode (–1 µA, –3 µA, –10 µA, –30

µA)

High Current Mode³

–11.0 to 12.6

–0.4 to 16.5

–11.0 to 12.4

–0.4 to 16.0

V

AT

Unpowered,

unconfigured

ADC

reset

asserted

or

Analog input (+16 V, 4 V prescaler range)

Analog input (direct input to ADC)

Digital input

–0.4 to 16.5

–0.4 to 3.75

–0.4 to 16.5

–0.4 to 16.0

–0.4 to 3.75

–0.4 to 16.0

V

3

T_STG

Storage temperature

–65 to +150

+125

°C

T_j³

Junction temperature

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4.

2. Analog data not valid beyond 3.65 V.

3. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended

operating limits refer to Table 3-2 on page 3-3.

3-2

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 3-2 • Recommended Operating Conditions

Symbol

T_A,T_J

Parameter

Ambient and junction temperature

1.5 V DC core supply voltage

JTAG DC voltage

Commercial

0 to +70

Industrial

–40 to +85

Units

°C

V

V_CC

1.425 to 1.575

1.4 to 3.6

1.425 to 1.575

1.4 to 3.6

V_JTAG

V_PUMP

Programming voltage

Programming mode

Operation³

3.15 to 3.45

0 to 3.6

3.15 to 3.45

0 to 3.6

V_CCPLL

V_CCI

Analog power supply (PLL)

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.3 V DC supply voltage

LVDS differential I/O

1.425 to 1.575

1.7 to 1.9

1.425 to 1.575

1.7 to 1.9

2.3 to 2.7

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

LVPECL differential I/O

+3.3 V power supply

V_CC33A

VAREF

2.97 to 3.63

2.527 to 2.593

1.425 to 1.575

2.97 to 3.63

–10.5 to 12.0

–0.3 to 12.0

–0.3 to 3.6

2.97 to 3.63

2.527 to 2.593

1.425 to 1.575

2.97 to 3.63

–10.5 to 12.0

–0.3 to 12.0

–0.3 to 3.6

Voltage reference for ADC

6

V_CC15A

Digital power supply for the analog system

Embedded flash power supply

V_CCNVM

V_CCOSC

AV, AC⁴

Oscillator power supply

Unpowered, ADC reset asserted or unconfigured

Analog input (+16 V to +2 V prescaler range)

Analog input (+1 V to + 0.125 V prescaler range)

Analog input (–16 V to –2 V prescaler range)

Analog input (–1 V to –0.125 V prescaler range)

Analog input (direct input to ADC)

Digital input

–10.5 to 0.3

–3.6 to 0.3

–10.5 to 0.3

–3.6 to 0.3

–0.3 to 3.6

–0.3 to 12.0

–10.5 to 12.0

–0.3 to 12.0

–10.5 to 0.3

–10.5 to 12.0

–0.3 to 16.0

–0.3 to 3.6

–0.3 to 12.0

–10.5 to 12.0

–0.3 to 12.0

–10.5 to 0.3

–10.5 to 12.0

–0.3 to 15.5

–0.3 to 3.6

AG⁴

Unpowered, ADC reset asserted or unconfigured

Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA)

Low Current Mode (–1 µA, –3 µA, –10 µA, –30 µA)

High Current Mode⁵

AT⁴

Unpowered, ADC reset asserted or unconfigured

Analog input (+16 V, +4 V prescaler range)

Analog input (direct input to ADC)

Digital input

–0.3 to 16.0

–0.3 to 15.5

V

Notes:

1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-81 on page 2-154.

2. All parameters representing voltages are measured with respect to GND unless otherwise specified.

3. V_PUMPcan be left floating during normal operation (not programming mode).

4. The input voltage may overshoot by up to 500 mV above the Recommended Maximum (150 mV in Direct

mode), provided the duration of the overshoot is less than 50% of the operating lifetime of the device.

5. The AG pad should also conform to the limits as specified inTable 2-45 on page 2-109.

6. Violating the V_CC15Arecommended voltage supply during an embedded flash program cycle can corrupt

the page being programmed.

Preliminary v1.7

3-3

DC and Power Characteristics

Table 3-3 • Input Resistance of Analog Pads

Pads

Pad Configuration

Prescaler Range

+16 V to +2 V

+1 V to +0.125 V

+16 V to +2 V

+1 V to +0.125 V

–16 V to –2 V

–1 V to –0.125 V

+16 V to +2 V

–16 V to –2 V

+16 V, +4 V

Input Resistance to Ground

1 MΩ (typical)

> 10 MΩ

AV, AC

Analog Input (direct input to ADC)

Analog Input (positive prescaler)

Analog Input (negative prescaler)

1 MΩ (typical)

> 10 MΩ

1 MΩ (typical)

> 10 MΩ

Digital input

1 MΩ (typical)

> 10 MΩ

Current monitor

AT

Analog Input (direct input to ADC)

Analog Input (positive prescaler)

Digital input

+16 V, +4 V

Temperature monitor

+16 V, +4 V

Table 3-4 • Overshoot and Undershoot Limits ¹

Average V_CCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle²

Maximum Overshoot/

Undershoot²

V_CCI

2.7 V or less

10%

5%

1.4 V

1.49 V

1.1 V

3.0 V

3.3 V

3.6 V

Notes:

10%

5%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

10%

5%

10%

5%

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one cycle out of six clock cycle. If the overshoot/undershoot occurs at one out of

two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3-4

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 3-5 • FPGA Programming, Storage, and Operating Limits

Storage Temperature (°C)

Product

Grade

Grade Programming

Cycles

Element

Retention

20 years²

5 years²

20 years

5 years

Minimum

Maximum

Commercial

Industrial

Notes:

FPGA/FlashROM

Embedded Flash

500

1 k

0

85

15 k

500

1 k

0

FPGA/FlashROM

Embedded Flash

–40

15 k

1. This is a stress rating only. Functional operation at any condition other than those indicated is not implied.

2. If the embedded flash has been programmed less than 1 k times, every time it is programmed, the data will

hold for 20 years. If the embedded flash has been programmed more than 1 k times but less than 15 k

times, every time it is programmed, the data will hold for 5 years.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every Fusion device. These circuits

ensure easy transition from the powered off state to the powered up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In

addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 3-1 on page 3-6.

There are five regions to consider during power-up.

Fusion I/Os are activated only if ALL of the following three conditions are met:

1. V_CCand V_CCIare above the minimum specified trip points (Figure 3-1).

2. V_CCI> V_CC– 0.75 V (typical).

3. Chip is in the operating mode.

V_CCITrip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

V_CCTrip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

V_CCand V_CCIramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

•

During programming, I/Os become tristated and weakly pulled up to V_CCI.

JTAG supply, PLL power supplies, and charge pump V_PUMPsupply have no influence on I/O

behavior.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

Preliminary v1.7

3-5

DC and Power Characteristics

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until V_CCand V_CCPLXexceed brownout

activation levels. The V_CCactivation level is specified as 1.1 V worst-case (see Figure 3-1 on page 3-6

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the Power-

Up/Down of Fusion FPGAs application note for information on clock and lock recovery.

V

= V + VT

CCI

CC

Where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

V

CC

V

= 1.575 V

CC

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

(except differential inputs)

but slower because V is

below specification. For the

I/Os meet the entire datasheet

and timer specifications for

CCI

speed, V /V , V , etc.

/V

same reason, input buffers do not

IH IL OH OL

meet V /V levels, and output

IH IL

buffers do not meet V /V levels.

OH OL

V

= 1.425 V

CC

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but slower because V /V are below

CCI CC

specification. For the same reason, input

but I/Os are slower because

buffers do not meet V /V levels, and

IH IL

the V is below specification

CC

output buffers do not meet V /V levels.

OH OL

Activation trip point:

= 0.85 V 0.25 V

V

a

Deactivation trip point:

= 0.75 V 0.25 V

Region 1: I/O buffers are OFF

V

d

V

Activation trip point:

= 0.9 V 0.3 V

CCI

Min V datasheet specification

CCI

V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

a

Deactivation trip point:

= 0.8 V 0.3 V

V

d

Figure 3-1 • I/O State as a Function of V_CCIand V_CCVoltage Levels

3-6

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient, case, or board temperatures. This is an important distinction because dynamic and

static power consumption will cause the chip's junction temperature to be higher than the

ambient, case, or board temperatures. EQ 3-1 through EQ 3-3 give the relationship between

thermal resistance, temperature gradient, and power.

T_J– θ_A

θ_JA= ----------------

P

EQ 3-1

T_J– T_B

θ_JB= ----------------

P

EQ 3-2

T_J– T_C

θ_JC= ----------------

P

EQ 3-3

where

θ_JA= Junction-to-air thermal resistance

θ_JB= Junction-to-board thermal resistance

θ_JC= Junction-to-case thermal resistance

T_J

= Junction temperature

T_A= Ambient temperature

T_B= Board temperature (measured 1.0 mm away from

the package edge)

T_C= Case temperature

P

= Total power dissipated by the device

Table 3-6 • Package Thermal Resistance

θ_JA

1.0 m/s

TBD

33.9

30.0

25.2

19.6

18.2

16.8

TBD

Product

Still Air

TBD

37.7

33.7

28.9

23.3

21.8

21.6

TBD

2.5 m/s

TBD

32.2

28.3

23.5

18.0

16.7

15.2

TBD

θ_JC

TBD

11.5

9.3

θ_JB

Units

°C/W

AFS090-QN108

AFS090-QN180

AFS250-QN180

AFS250-PQ208

AFS600-PQ208

AFS090-FG256

AFS250-FG256

AFS600-FG256

AFS1500-FG256

AFS600-FG484

AFS1500-FG484

AFS1500-FG676

TBD

29.7

24.8

19.9

14.2

16.8

14.9

TBD

6.8

4.3

7.7

5.6

TBD

Preliminary v1.7

3-7

DC and Power Characteristics

Theta-JA

Junction-to-ambient thermal resistance (θ_JA) is determined under standard conditions specified by

JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used

with caution but is useful for comparing the thermal performance of one package to another.

A sample calculation showing the maximum power dissipation allowed for the AFS600-FG484

package under forced convection of 1.0 m/s and 75°C ambient temperature is as follows:

T

_J(MAX)– T_A(MAX)

Maximum Power Allowed = ------------------------------------------

θ_JA

EQ 3-4

where

θ_JA= 19.00°C/W (taken from Table 3-6 on page 3-7).

T_A= 75.00°C

110.00°C – 75.00°C

Maximum Power Allowed = --------------------------------------------------- = 1.84 W

19.00°C/W

The power consumption of a device can be calculated using the Actel power calculator. The

device's power consumption must be lower than the calculated maximum power dissipation by the

package. If the power consumption is higher than the device's maximum allowable power

dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must be

increased.

Theta-JB

Junction-to-board thermal resistance (θ_JB) measures the ability of the package to dissipate heat

from the surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal

resistance from junction to board uses an isothermal ring cold plate zone concept. The ring cold

plate is simply a means to generate an isothermal boundary condition at the perimeter. The cold

plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm away from the

package edge.

Theta-JC

Junction-to-case thermal resistance (θ_JC) measures the ability of a device to dissipate heat from the

surface of the chip to the top or bottom surface of the package. It is applicable for packages used

with external heat sinks. Constant temperature is applied to the surface in consideration and acts

as a boundary condition. This only applies to situations where all or nearly all of the heat is

dissipated through the surface in consideration.

Calculation for Heat Sink

For example, in a design implemented in an AFS600-FG484 package with 2.5 m/s airflow, the power

consumption value using the power calculator is 3.00 W. The user-dependent T_aand T_jare given as

follows:

T_J

=

110.00°C

70.00°C

T_A

From the datasheet:

θ_JA

θ_JC

=

17.00°C/W

8.28°C/W

T_J– T_A

P = ---------------- = ---------------------------------- = 2.35 W

θ_JA17.00 W

110°C – 70°C

EQ 3-5

3-8

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

The 2.35 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the

airflow where the device is mounted should be increased. The design's total junction-to-air thermal

resistance requirement can be estimated by EQ 3-6:

T_J– T_A

θ_ja(total)= ---------------- = ---------------------------------- = 13.33°C/W

3.00 W

110°C – 70°C

P

EQ 3-6

EQ 3-7

Determining the heat sink's thermal performance proceeds as follows:

θ_JA(TOTAL)= θ_JC+ θ_CS+ θ_SA

where

θ_JA

=

0.37°C/W

Thermal resistance of the interface material

between the case and the heat sink, usually

provided by the thermal interface manufacturer

θ_SA

=

Thermal resistance of the heat sink in °C/W

θ_SA= θ_JA(TOTAL)– θ_JC– θ_CS

EQ 3-8

θ_SA= 13.33°C/W – 8.28°C/W – 0.37°C/W = 5.01°C/W

A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of

heat sinks is a function of airflow. The heat sink performance can be significantly improved with

increased airflow.

Carefully estimating thermal resistance is important in the long-term reliability of an Actel FPGA.

Design engineers should always correlate the power consumption of the device with the maximum

allowable power dissipation of the package selected for that device.

Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard

(JESD-51) and assumptions made in building the model. It may not be realized in actual application

and therefore should be used with a degree of caution. Junction-to-case thermal resistance

assumes that all power is dissipated through the case.

Temperature and Voltage Derating Factors

Table 3-7 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 70°C, V_CC= 1.425 V)

Array

Junction Temperature (°C)

Voltage V_CC

(V)

–40°C

0.88

0.83

0.80

0°C

0.93

0.88

0.85

25°C

0.95

0.90

0.87

70°C

1.00

0.95

0.91

85°C

1.02

0.96

0.93

110°C

1.05

0.99

0.96

1.425

1.500

1.575

Preliminary v1.7

3-9

DC and Power Characteristics

Calculating Power Dissipation

Quiescent Supply Current

1

Table 3-8 • Quiescent Supply Current Characteristics (I_DDQ

)

Parameter

Conditions and Modes

AFS090

15 mA

10 mA

2 mA

AFS250

30 mA

20 mA

3 mA

AFS600

45 mA

30 mA

5 mA

AFS1500

TBD

I_DC1

Maximum in operating mode (85°C) ²

Maximum in operating mode (70°C) ²

Typical in operating mode (25°C) ²

Typical in standby mode (25°C) ^3,5

Typical in sleep mode (25°C) ^4,5

TBD

I_DC2

200 µA

10 µA

200 µA

10 µA

200 µA

10 µA

TBD

I_DC3

TBD

Notes:

1. –F speed grade devices may experience higher Quiescent Supply current of up to five times the standard

I_DD, and higher I/O leakage.

2. I_DC1includes V_CC, V_PUMP, and V_CCI, currents. Values do not include I/O static contribution, which is shown in

Table 3-9 on page 3-11 and Table 3-10 on page 3-13.

3. I_DC2represents the current from the V_CC33Aand V_CCIsupplies when the RTC (and the 32 kHz crystal

oscillator) is ON, the FPGA is OFF, and the voltage regulator is OFF.

4. I_DC3represents the current from the V_CC33Aand V_CCIsupplies when the RTC (and the crystal oscillator), the

FPGA, and the voltage regulator are OFF.

5. V_CCIsupply is ON, since the east and west I/O banks are not cold-sparable. Values do not include I/O static

contribution, which is shown in Table 3-9 on page 3-11 and Table 3-10 on page 3-13.

3-10

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Power per I/O Pin

Table 3-9 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings

Static Power

Dynamic Power

P_AC9(µW/MHz)²

V_CCI(V)

P_DC7(mW)¹

Applicable to Pro I/O Banks

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVTTL/LVCMOS – Schmitt trigger

2.5 V LVCMOS

3.3

2.5

1.8

1.5

3.3

–

17.39

25.51

5.76

2.5 V LVCMOS – Schmitt trigger

1.8 V LVCMOS

7.16

2.72

1.8 V LVCMOS – Schmitt trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

3.3 V PCI

2.80

2.08

2.00

18.82

20.12

18.82

20.12

3.3 V PCI – Schmitt trigger

3.3 V PCI-X

3.3 V PCI-X – Schmitt trigger

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

3.3

2.90

2.13

2.81

2.57

0.17

1.38

3.21

8.23

4.78

4.14

3.71

2.03

4.48

9.26

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

2.5

3.3

2.26

5.71

1.50

2.17

LVPECL

Notes:

1. P_DC7is the static power (where applicable) measured on V_CCI

.

2. P_AC9is the total dynamic power measured on V_CCand V_CCI

.

Preliminary v1.7

3-11

DC and Power Characteristics

Table 3-9 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings (continued)

Static Power

P_DC7(mW)¹

Dynamic Power

V_CCI(V)

P_AC9(µW/MHz)²

Applicable to Advanced I/O Banks

Single-Ended

3.3 V LVTTL/LVCMOS

2.5 V LVCMOS

3.3

2.5

1.8

1.5

3.3

–

16.69

5.12

1.8 V LVCMOS

2.13

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

1.45

18.11

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

1.20

1.87

LVPECL

Applicable to Standard I/O Banks

3.3 V LVTTL/LVCMOS

2.5 V LVCMOS

3.3

2.5

1.8

1.5

–

16.79

5.19

2.18

1.52

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

Notes:

1. P_DC7is the static power (where applicable) measured on V_CCI

.

2. P_AC9is the total dynamic power measured on V_CCand V_CCI

.

3-12

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Table 3-10 • Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings¹

Static Power

P_DC8(mW)²

Dynamic Power

P_AC10(µW/MHz)³

C_LOAD(pF)

V_CCI(V)

Applicable to Pro I/O Banks

Single-Ended

3.3 V LVTTL/LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

35

10

3.3

2.5

1.8

1.5

3.3

–

474.70

270.73

151.78

104.55

204.61

3.3 V PCI-X

Voltage-Referenced

3.3 V GTL

10

20

30

3.3

2.5

3.3

2.5

1.5

2.5

3.3

–

24.08

13.52

24.10

13.54

26.22

27.22

105.56

116.60

114.87

131.76

2.5 V GTL

–

3.3 V GTL+

–

2.5 V GTL+

–

HSTL (I)

7.08

13.88

16.69

25.91

26.02

42.21

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

–

2.5

3.3

7.70

89.62

LVPECL

19.42

168.02

Applicable to Advanced I/O Banks

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

35

10

3.3

2.5

1.8

1.5

3.3

–

468.67

267.48

149.46

103.12

201.02

3.3 V PCI-X

Notes:

1. Dynamic power consumption is given for standard load and software-default drive strength and output

slew.

2. P_DC8is the static power (where applicable) measured on V_CCI

.

3. P_AC10is the total dynamic power measured on V_CCand V_CCI

.

Preliminary v1.7

3-13

DC and Power Characteristics

Table 3-10 • Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings¹(continued)

Static Power

P_DC8(mW)²

Dynamic Power

P_AC10(µW/MHz)³

C_LOAD(pF)

V_CCI(V)

Differential

LVDS

–

2.5

3.3

7.74

88.92

LVPECL

19.54

166.52

Applicable to Standard I/O Banks

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

35

3.3

2.5

1.8

1.5

–

431.08

247.36

128.46

89.46

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

Notes:

1. Dynamic power consumption is given for standard load and software-default drive strength and output

slew.

2. P_DC8is the static power (where applicable) measured on V_CCI

.

3. P_AC10is the total dynamic power measured on V_CCand V_CCI

.

3-14

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Dynamic Power Consumption of Various Internal Resources

Table 3-11 • Different Components Contributing to the Dynamic Power Consumption in Fusion Devices

Device-Specific

Power Supply

Dynamic Contributions

Parameter

Definition

Name Setting AFS1500 AFS600 AFS250 AFS090

Units

P_AC1

Clock contribution of a Global

Rib

V_CC

1.5 V

14.5

2.5

12.8

1.9

11

µW/MHz

P_AC2

P_AC3

P_AC4

P_AC5

P_AC6

Clock contribution of a Global

Spine

1.6

0.8

µW/MHz

Clock contribution of a VersaTile

row

0.81

Clock contribution of a VersaTile

used as a sequential module

0.11

0.07

0.29

First contribution of a VersaTile

used as a sequential module

Second

contribution

of

a

VersaTile used as a sequential

module

P_AC7

Contribution of a VersaTile used

as a combinatorial module

V_CC

1.5 V

0.29

0.70

µW/MHz

P_AC8

Average contribution of

routing net

a

P_AC9

Contribution of an I/O input pin VMV/

(standard dependent) V_CC

See Table 3-9 on page 3-11

P_AC10

P_AC11

P_AC12

Contribution of an I/O output V_CCI

/

See Table 3-10 on page 3-13

pin (standard dependent)

V_CC

Average contribution of a RAM

block during a read operation

V_CC

1.5 V

25

30

µW/MHz

Average contribution of a RAM

block during a write operation

P_AC13

P_AC15

Dynamic Contribution for PLL

V_CC

1.5 V

2.6

µW/MHz

Contribution of NVM block

during a read operation (F <

33MHz)

358

P_AC16

1st contribution of NVM block

during a read operation (F >

33MHz)

V_CC

1.5 V

12.88

4.8

mW

P_AC17

2nd contribution of NVM block

during a read operation (F >

33MHz)

V_CC

µW/MHz

P_AC18

P_AC19

P_AC20

Crystal Oscillator contribution

RC Oscillator contribution

V_CC33A

V_CC

3.3 V

1.5 V

0.63

3.3

3

mW

Analog Block dynamic power

contribution of ADC

Preliminary v1.7

3-15

DC and Power Characteristics

Static Power Consumption of Various Internal Resources

Table 3-12 • Different Components Contributing to the Static Power Consumption in Fusion Devices

Device-Specific Static Contributions

Parameter

Definition

Power Supply AFS1500 AFS600 AFS250 AFS090 Units

P_DC1

Core static power contribution in

operating mode

V_CC

1.5 V

3.3 V

TBD

7.5

4.50

3.00

mW

P_DC2

P_DC3

Device static power contribution V_CC33A

in standby mode

0.66

0.03

Device static power contribution V_CC33A

in sleep mode

P_DC4

P_DC5

NVM static power contribution

V_CC

1.5 V

3.3 V

1.19

8.25

mW

Analog Block static power V_CC33A

contribution of ADC

P_DC6

P_DC7

Analog Block static power V_CC33A

contribution per Quad

3.3 V

3.3

mW

Static contribution per input pin

standard dependent

contribution

VMV/

V_CC

See Table 3-9 on page 3-11

See Table 3-10 on page 3-13

2.55

–

P_DC8

Static contribution per input pin

standard dependent

contribution

VMV/

V_CC

–

P_DC9

Static contribution for PLL

V_CC

1.5 V

mW

3-16

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE

software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock

generated

•

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

The number of NVM blocks used in the design

The number of Analog Quads used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-13 on

page 3-21.

•

Enable rates of output buffers—guidelines are provided for typical applications in

Table 3-14 on page 3-21.

Read rate and write rate to the RAM—guidelines are provided for typical applications in

Table 3-14 on page 3-21.

Read rate to the NVM blocks

The calculation should be repeated for each clock domain defined in the design.

Methodology

Total Power Consumption—P

TOTAL

Operating Mode, Standby Mode, and Sleep Mode

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

P_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

STAT

Operating Mode

P_STAT= P_DC1+ (N_NVM-BLOCKS* P_DC4) + P_DC5+ (N_QUADS* P_DC6) + (N_INPUTS* P_DC7) + (N_OUTPUTS* P_DC8) +

(N_PLLS* P_DC9

)

N_NVM-BLOCKSis the number of NVM blocks available in the device.

N

_QUADSis the number of Analog Quads used in the design.

_INPUTSis the number of I/O input buffers used in the design.

N

N_OUTPUTSis the number of I/O output buffers used in the design.

_PLLSis the number of PLLs available in the device.

N

Standby Mode

P_STAT= P_DC2

Sleep Mode

P_STAT= P_DC3

Total Dynamic Power Consumption—P

DYN

Operating Mode

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL+ P_NVM+ P_XTL-OSC

_RC-OSC+ P_AB

+

P

Preliminary v1.7

3-17

DC and Power Characteristics

Standby Mode

P_DYN= P_XTL-OSC

Sleep Mode

P_DYN= 0 W

Global Clock Dynamic Contribution—P

CLOCK

Operating Mode

P_CLOCK= (P_AC1+ N_SPINE* P_AC2+ N_ROW* PAC3 + N_S-CELL* P_AC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in

Table 3-13 on page 3-21.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in

Table 3-13 on page 3-21.

F_CLKis the global clock signal frequency.

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

Standby Mode and Sleep Mode

P_CLOCK= 0 W

Sequential Cells Dynamic Contribution—P

S-CELL

Operating Mode

P_S-CELL= N_S-CELL* (P_AC5+ (α₁/ 2) * P_AC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a multi-

tile sequential cell is used, it should be accounted for as 1.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on

page 3-21.

F_CLKis the global clock signal frequency.

Standby Mode and Sleep Mode

P_S-CELL= 0 W

Combinatorial Cells Dynamic Contribution—P

C-CELL

Operating Mode

P_C-CELL= N_C-CELL* (α₁/ 2) * P_AC7* F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on

page 3-21.

F_CLKis the global clock signal frequency.

Standby Mode and Sleep Mode

P_C-CELL= 0 W

Routing Net Dynamic Contribution—P_NET

Operating Mode

P_NET= (N_S-CELL+ N_C-CELL) * (α₁/ 2) * P_AC8* F_CLK

N_S-CELLis the number VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on

page 3-21.

F_CLKis the global clock signal frequency.

3-18

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Standby Mode and Sleep Mode

P_NET= 0 W

I/O Input Buffer Dynamic Contribution—P

INPUTS

Operating Mode

P_INPUTS= N_INPUTS* (α₂/ 2) * P_AC9* F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-21.

_CLKis the global clock signal frequency.

F

Standby Mode and Sleep Mode

P_INPUTS= 0 W

I/O Output Buffer Dynamic Contribution—P

OUTPUTS

Operating Mode

P_OUTPUTS= N_OUTPUTS* (α₂/ 2) * β₁* P_AC10* F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-21.

β₁is the I/O buffer enable rate—guidelines are provided in Table 3-14 on page 3-21.

F_CLKis the global clock signal frequency.

Standby Mode and Sleep Mode

P_OUTPUTS= 0 W

RAM Dynamic Contribution—P

MEMORY

Operating Mode

P_MEMORY= (N_BLOCKS* P_AC11* β₂* F_READ-CLOCK) + (N_BLOCKS* P_AC12* β₃* F_WRITE-CLOCK

)

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

β₂is the RAM enable rate for read operations—guidelines are provided in Table 3-14 on

page 3-21.

β₃the RAM enable rate for write operations—guidelines are provided in Table 3-14 on

page 3-21.

F_WRITE-CLOCKis the memory write clock frequency.

Standby Mode and Sleep Mode

P_MEMORY= 0 W

PLL/CCC Dynamic Contribution—P

PLL

Operating Mode

P_PLL= P_AC13* F_CLKOUT

F_CLKINis the input clock frequency.

_CLKOUTis the output clock frequency.¹

F

Standby Mode and Sleep Mode

P_PLL= 0 W

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock

signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more

than one output clock, include each output clock in the formula output clock by adding its

corresponding contribution (P_AC14* F_CLKOUTproduct) to the total PLL contribution.

Preliminary v1.7

3-19

DC and Power Characteristics

Nonvolatile Memory Dynamic Contribution—P

NVM

Operating Mode

The NVM dynamic power consumption is a piecewise linear function of frequency.

P_NVM= N_NVM-BLOCKS* β₄* P_AC15* F_READ-NVMwhen F_READ-NVM≤ 33 MHz,

P_NVM= N_NVM-BLOCKS* β₄*(P_AC16+ P_AC17* F_READ-NVM)when F_READ-NVM> 33 MHz

N_NVM-BLOCKSis the number of NVM blocks used in the design (2 in AFS600).

β₄is the NVM enable rate for read operations. Default is 0 (NVM mainly in idle state).

F

_READ-NVMis the NVM read clock frequency.

Standby Mode and Sleep Mode

P_NVM= 0 W

Crystal Oscillator Dynamic Contribution—P

XTL-OSC

Operating Mode

P_XTL-OSC= P_AC18

Standby Mode

P_XTL-OSC= P_AC18

Sleep Mode

P_XTL-OSC= 0 W

RC Oscillator Dynamic Contribution—P

RC-OSC

Operating Mode

P_RC-OSC= P_AC19

Standby Mode and Sleep Mode

P_RC-OSC= 0 W

Analog System Dynamic Contribution—P

AB

Operating Mode

P_AB= P_AC20

Standby Mode and Sleep Mode

P_AB= 0 W

3-20

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that the net switches at half the clock frequency.

Below are some examples:

•

The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of

the clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1 = 50%

Bit 2 = 25%

…

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When non-tristate output buffers are used, the enable rate should be 100%.

Table 3-13 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

α₁

α₂

10%

Table 3-14 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

12.5%

0%

β₁

β₂

β₃

β₄

RAM enable rate for read operations

RAM enable rate for write operations

NVM enable rate for read operations

Preliminary v1.7

3-21

DC and Power Characteristics

Example of Power Calculation

This example considers a shift register with 5,000 storage tiles, including a counter and memory

that stores analog information. The shift register is clocked at 50 MHz and stores and reads

information from a RAM.

The device used is a commercial AFS600 device operating in typical conditions.

The calculation below uses the power calculation methodology previously presented and shows

how to determine the dynamic and static power consumption of resources used in the application.

Also included in the example is the calculation of power consumption in operating, standby, and

sleep modes to illustrate the benefit of power-saving modes.

Global Clock Contribution—P

CLOCK

F_CLK= 50 MHz

Number of sequential VersaTiles: N_S-CELL= 5,000

Estimated number of Spines: N_SPINES= 5

Estimated number of Rows: N_ROW= 313

Operating Mode

P_CLOCK= (P_AC1+ N_SPINE* P_AC2+ N_ROW* PAC3 + N_S-CELL* P_AC4) * F_CLK

P_CLOCK= (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50

P_CLOCK= 41.28 mW

Standby Mode and Sleep Mode

P_CLOCK= 0 W

Logic—Sequential Cells, Combinational Cells, and Routing Net Contributions—P

,

S-CELL

P

, and P

C-CELL

NET

F_CLK= 50 MHz

Number of sequential VersaTiles: N_S-CELL= 5,000

Number of combinatorial VersaTiles: N_C-CELL= 6,000

Estimated toggle rate of VersaTile outputs: α₁= 0.1 (10%)

Operating Mode

P_S-CELL= N_S-CELL* (P_AC5+ (α₁/ 2) * P_AC6) * F_CLK

P_S-CELL= 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50

P_S-CELL= 21.13 mW

P

_C-CELL= N_C-CELL* (α₁/ 2) * P_AC7* F_CLK

P_C-CELL= 6,000 * (0.1 / 2) * 0.00029 * 50

P_C-CELL= 4.35 mW

P

_NET= (N_S-CELL+ N_C-CELL) * (α₁/ 2) * P_AC8* F_CLK

P_NET= (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50

P_NET= 19.25 mW

P

_LOGIC= P_S-CELL+ P_C-CELL+ P_NET

P_LOGIC= 21.13 mW + 4.35 mW + 19.25 mW

P_LOGIC= 44.73 mW

Standby Mode and Sleep Mode

3-22

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

P_S-CELL= 0 W

P_C-CELL= 0 W

P_NET= 0 W

P_LOGIC= 0 W

I/O Input and Output Buffer Contribution—P

I/O

This example uses LVTTL 3.3 V I/O cells. The output buffers are 12 mA–capable, configured with

high output slew and driving a 35 pF output load.

F

_CLK= 50 MHz

Number of input pins used: N_INPUTS= 30

Number of output pins used: N_OUTPUTS= 40

^{Estimated I/O buffer toggle rate:}α₂= 0.1 (10%)

^{Estimated IO buffer enable rate:}β₁= 1 (100%)

Operating Mode

P_INPUTS= N_INPUTS* (α₂/ 2) * P_AC9* F_CLK

P_INPUTS= 30 * (0.1 / 2) * 0.01739 * 50

P_INPUTS= 1.30 mW

P

_OUTPUTS= N_OUTPUTS* (α₂/ 2) * β₁* P_AC10* F_CLK

P_OUTPUTS= 40 * (0.1 / 2) * 1 * 0.4747 * 50

P_OUTPUTS= 47.47 mW

P_I/O= P_INPUTS+ P_OUTPUTS

P_I/O= 1.30 mW + 47.47 mW

P_I/O= 48.77 mW

Standby Mode and Sleep Mode

P_INPUTS= 0 W

P_OUTPUTS= 0 W

P_I/O= 0 W

RAM Contribution—P

MEMORY

Frequency of Read Clock: F_READ-CLOCK= 10 MHz

Frequency of Write Clock: F_WRITE-CLOCK= 10 MHz

Number of RAM blocks: N_BLOCKS= 20

^{Estimated RAM Read Enable Rate:}β₂= 0.125 (12.5%)

^{Estimated RAM Write Enable Rate:}β₃= 0.125 (12.5%)

Operating Mode

P_MEMORY= (N_BLOCKS* P_AC11* β₂* F_READ-CLOCK) + (N_BLOCKS* P_AC12* β₃* F_WRITE-CLOCK

)

P_MEMORY= (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10)

P_MEMORY= 1.38 mW

Standby Mode and Sleep Mode

P_MEMORY= 0 W

PLL/CCC Contribution—P

PLL

PLL is not used in this application.

Preliminary v1.7

3-23

DC and Power Characteristics

P_PLL= 0 W

Nonvolatile Memory—P

NVM

Nonvolatile memory is not used in this application.

P_NVM= 0 W

Crystal Oscillator—P

XTL-OSC

The application utilizes standby mode. The crystal oscillator is assumed to be active.

Operating Mode

P_XTL-OSC= P_AC18

P_XTL-OSC= 0.63 mW

Standby Mode

P_XTL-OSC= P_AC18

P_XTL-OSC= 0.63 mW

Sleep Mode

P_XTL-OSC= 0 W

RC Oscillator—P

RC-OSC

Operating Mode

P_RC-OSC= P_AC19

P_RC-OSC= 3.30 mW

Standby Mode and Sleep Mode

P_RC-OSC= 0 W

Analog System—P

AB

Number of Quads used: N_QUADS= 4

Operating Mode

P_AB= P_AC20

P_AB= 3.00 mW

Standby Mode and Sleep Mode

P_AB= 0 W

Total Dynamic Power Consumption—P

DYN

Operating Mode

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL+ P_NVM+ P_XTL-OSC+ P_RC-

_OSC+ P_AB

P_DYN= 41.28 mW + 21.1 mW + 4.35 mW + 19.25 mW + 1.30 mW + 47.47 mW + 1.38 mW + 0 + 0 +

0.63 mW + 3.30 mW + 3.00 mW

P_DYN= 143.06 mW

Standby Mode

P_DYN= P_XTL-OSC

P_DYN= 0.63 mW

Sleep Mode

P_DYN= 0 W

3-24

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Total Static Power Consumption—P

STAT

Number of Quads used: N_QUADS= 4

Number of NVM blocks available (AFS600): N_NVM-BLOCKS= 2

Number of input pins used: N_INPUTS= 30

Number of output pins used: N_OUTPUTS= 40

Operating Mode

P_STAT= P_DC1+ (N_NVM-BLOCKS* P_DC4) + P_DC5+ (N_QUADS* P_DC6) + (N_INPUTS* P_DC7) + (N_OUTPUTS* P_DC8

)

P_STAT= 7.50 mW + (2 * 1.19 mW) + 8.25 mW + (4 * 3.30 mW) + (30 * 0.00) + (40 * 0.00)

P_STAT= 31.33 mW

Standby Mode

P_STAT= P_DC2

P_STAT= 0.03 mW

Sleep Mode

P_STAT= P_DC3

P_STAT= 0.03 mW

Total Power Consumption—P

TOTAL

In operating mode, the total power consumption of the device is 174.39 mW:

P_TOTAL= P_STAT+ P_DYN

P_TOTAL= 143.06 mW + 31.33 mW

P_TOTAL= 174.39 mW

In standby mode, the total power consumption of the device is limited to 0.66 mW:

P_TOTAL= P_STAT+ P_DYN

P_TOTAL= 0.03 mW + 0.63 mW

P_TOTAL= 0.66 mW

In sleep mode, the total power consumption of the device drops as low as 0.03 mW:

P_TOTAL= P_STAT+ P_DYN

P_TOTAL= 0.03 mW

Preliminary v1.7

3-25

DC and Power Characteristics

Power Consumption

Table 3-15 • Power Consumption

Parameter

Description

Condition

Min.

Typical

Max.

Units

Crystal Oscillator

I_STBXTAL

Standby Current of Crystal

Oscillator

10

µA

I_DYNXTAL

Operating Current

RC

0.6

0.19

0.6

mA

0.032–0.2

0.2–2.0

2.0–20.0

0.6

RC Oscillator

I_DYNRC

1

mA

ACM

Operating Current (fixed

clock)

200

30

µA/MHz

µA

Operating Current (user

clock)

NVM System

NVM

Array

Operating

Idle

795

µA

Power

Read

See

operation

Table 3-12 on

page 3-16.

Table 3-12 on

page 3-16.

Erase

Write

900

20

µA

P_NVMCTRL

NVM Controller Operating

Power

µW/MHz

3-26

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Part Number and Revision Date

Part Number 51700092-015-0

Revised October 2008

List of Changes

The following table lists critical changes that were made in the current version of the

document.

Previous Version Changes in Current Version (Preliminary v1.7)

Page

Advance v1.6

(August 2008)

The version number category was changed from Advance to Preliminary, which

N/A

means the datasheet contains information based on simulation and/or initial

characterization. The information is believed to be correct, but changes are

possible.

Advance v1.4

(July 2008)

The title of the datasheet changed from Actel Programmable System Chips to

Actel Fusion Mixed-Signal FPGAs. In addition, all instances of programmable

system chip were changed to mixed-signal FPGA.

N/A

Advance v1.3

(July 2008)

In Table 3-8 · Quiescent Supply Current Characteristics (IDDQ)1, footnote

3-10

references were updated for I_DC2and I_DC3

.

Footnote 3 and 4 were updated and footnote 5 is new.

Advance v1.1

Advance v0.9

Table 3-6 · Package Thermal Resistance was significantly updated

3-7

Table 3-11 · Different Components Contributing to the Dynamic Power

Consumption in Fusion Devices was significantly updated.

3-15

Table 3-13 · Toggle Rate Guidelines Recommended for Power Calculation was

significantly updated.

3-21

3-1

In Table 3-1 · Absolute Maximum Ratings, the AT for the Unpowered, ADC reset

asserted or unconfigured parameter, –11 was changed to –0.4.

The units column of Table 3-2 · Recommended Operating Conditions was

incomplete in the previous version. V was added to all the rows. In addition, AT

for the Unpowered, ADC reset asserted or unconfigured parameter, –10.5 was

3-3

changed to –0.3. Note 6 was updated to include V_CC15A

.

In the title of Table 3-3 · Input Resistance of Analog Pads, Impedance was

changed to Resistance.

3-4

3-5

In Table 3-5 · FPGA Programming, Storage, and Operating Limits, note 2 is new.

"Program" was removed from the table heading in the Retention column.

The "PLL Behavior at Brownout Condition" section is new.

3-6

3-9

Table 3-7 · Temperature and Voltage Derating Factors for Timing Delays was

updated.

In the Table 3-9 · Summary of I/O Input Buffer Power (per pin)—Default I/O

Software Settings, the HSTL (I) for the Static Power PDC7 (mW) was changed

from 0.1 to 0.17.

3-11

The Table 3-11 · Different Components Contributing to the Dynamic Power

Consumption in Fusion Devices was updated.

3-15

3-16

3-19

The Table 3-12 · Different Components Contributing to the Static Power

Consumption in Fusion Devices was updated.

In the "PLL/CCC Dynamic Contribution—P_PLL" section, P_AC14was deleted.

Preliminary v1.7

3-27

DC and Power Characteristics

Previous Version Changes in Current Version (Preliminary v1.7)

Page

Advance v0.8

(June 2007)

In Table 3-6 · Package Thermal Resistance, the data for the following

device/packages were updated:

3-7

AFS090-FG256

AFS250-FG256

AFS600-FG256

AFS1500-FG256

AFS600-FG484

AFS1500-FG484

AFS1500-FG676

Advance v0.7

(January 2007)

The VMV pins have now been tied internally with the V_CCIpins.

N/A

The V_COMPLFpin description was deleted.

Table 3-1 · Absolute Maximum Ratings, Table 3-2 · Recommended Operating 3-1 to

Conditions, and Table 3-3 · Input Resistance of Analog Pads were updated.

3-4

Table 3-5 · FPGA Programming, Storage, and Operating Limits was updated.

3-5

P_AC13and P_AC14were updated in Table 3-11 · Different Components

Contributing to the Dynamic Power Consumption in Fusion Devices.

3-15

The Operating Mode for the "PLL/CCC Dynamic Contribution—P_PLL" section was

updated.

3-19

3-26

3-4

Table 3-15 · Power Consumption was updated to change the typical value of

I_DYNXTALfor 0.032–0.2 MHz to 0.19.

Advance v0.5

(June 2006)

Table 3-3 · Input Resistance of Analog Pads is new.

Advance v0.4

(April 2006)

The low power modes of operation were updated and clarified.

N/A

Advance v0.2

(April 2006)

Table 3-8 · Quiescent Supply Current Characteristics (IDDQ)1 was updated.

3-10

3-15

Table 3-11 · Different Components Contributing to the Dynamic Power

Consumption in Fusion Devices was updated.

Table 3-11 · Different Components Contributing to the Dynamic Power

Consumption in Fusion Devices was updated.

The "Example of Power Calculation" was updated.

3-22

3-26

The Analog System information was deleted from Table 3-15 · Power

Consumption.

3-28

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status datasheet may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

Preliminary v1.7

3-29

Actel Fusion^®Mixed-Signal FPGAs Packaging

4 – Package Pin Assignments

108-Pin QFN

A44

B41

A56

B52

Pin A1 Mark

A43

B40

A1

B1

B13

A14

B27

A29

B26

A28

B14

A15

Note: The die attach paddle center of the package is tied to ground (GND).

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

Preliminary v1.7

4-1

Package Pin Assignments

108-Pin QFN

Pin Number

A1

AFS090 Function

Pin Number

AFS090 Function

GND

Pin Number

AFS090 Function

NC

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

B1

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

AC2

ATRTN1

A2

GNDQ

GCB1/IO35PDB1V0

GCB2/IO33PDB1V0

GBA2/IO31PDB1V0

NC

A3

GAA2/IO52PDB3V0

AG3

A4

GND

AV3

A5

GFA1/IO47PDB3V0

V_CC33A

A6

GEB1/IO45PDB3V0

GBA1/IO30RSB0V0

GBB1/IO28RSB0V0

GND

VAREF

A7

VCCOSC

PUB

A8

XTAL2

V_CC33A

A9

GEA1/IO44PPB3V0

V_CC

PTBASE

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

GEA0/IO44NPB3V0

GBC1/IO26RSB0V0

IO21RSB0V0

IO19RSB0V0

IO09RSB0V0

GAC0/IO04RSB0V0

V_CCNVM

GEB2/IO42PDB3V0

V_CC

V_CCNVM

V_CC15A

PCAP

TDI

TDO

V_JTAG

NC

V_CCIB0

GDC0/IO38NDB1V0

V_CCIB1

GNDA

AV0

GND

GAB0/IO02RSB0V0

GAA0/IO00RSB0V0

V_COMPLA

GCB0/IO35NDB1V0

GCC2/IO33NDB1V0

GBB2/IO31NDB1V0

AG0

ATRTN0

AT1

B2

V_CCIB3

V_CCIB1

AC1

B3

GAB2/IO52NDB3V0

GNDQ

AV2

B4

V_CCIB3

GBA0/IO29RSB0V0

AG2

B5

GFA0/IO47NDB3V0

GEB0/IO45NDB3V0

XTAL1

V_CCIB0

AT2

B6

GBB0/IO27RSB0V0

GBC0/IO25RSB0V0

IO20RSB0V0

AT3

B7

AC3

B8

GNDOSC

GEC2/IO43PSB3V0

GEA2/IO42NDB3V0

V_CC

GNDAQ

ADCGNDREF

NC

B9

IO10RSB0V0

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

GAC1/IO05RSB0V0

GAB1/IO03RSB0V0

V_CC

GNDA

PTEM

GNDNVM

NCAP

GAA1/IO01RSB0V0

V_CCPLA

GNDNVM

V_PUMP

V_CC33PMP

V_CC33N

TCK

GNDAQ

TMS

AC0

TRST

AT0

GDB1/IO39PSB1V0

GDC1/IO38PDB1V0

AG1

AV1

4-2

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

180-Pin QFN

A64

B60

C56

A49

B46

C43

Pin A1 Mark

D1

D4

A48

B45

A1

B1

C1

C42

C29

B31

C14

B15

A16

A33

D3

D2

Optional Corner

Pad (4X)

C15

B16

A17

C28

B30

A32

Note: The die attach paddle center of the package is tied to ground (GND).

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

Preliminary v1.7

4-3

Package Pin Assignments

180-Pin QFN

Pin Number AFS090 Function

180-Pin QFN

AFS250 Function

GNDQ

Pin Number AFS090 Function

AFS250 Function

A1

A2

GNDQ

V_CCIB3

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

B1

V_PUMP

TDI

V_PUMP

TDI

V_CCIB3

A3

GAB2/IO52NDB3V0

GFA2/IO51NDB3V0

GFC2/IO50NDB3V0

V_CCIB3

IO74NDB3V0

IO71NDB3V0

IO69NPB3V0

V_CCIB3

TDO

V_JTAG

A4

V_JTAG

A5

GDB1/IO39PPB1V0 GDA1/IO54PPB1V0

GDC1/IO38PDB1V0 GDB1/IO53PDB1V0

A6

A7

GFA1/IO47PPB3V0 GFB1/IO67PPB3V0

V_CC

A8

GEB0/IO45NDB3V0

XTAL1

NC

GCB0/IO35NPB1V0 GCB0/IO48NPB1V0

GCC1/IO34PDB1V0 GCC1/IO47PDB1V0

A9

XTAL1

GNDOSC

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

GNDOSC

V_CCIB1

GEC2/IO43PPB3V0 GEA1/IO61PPB3V0

GBC2/IO32PPB1V0 GBB2/IO41PPB1V0

IO43NPB3V0

NC

GEA0/IO61NPB3V0

V_CCIB3

GNDNVM

PCAP

V_CCIB1

NC

V_CCIB1

NC

GNDNVM

PCAP

V_CC33PMP

NC

GBA0/IO29RSB0V0 GBB1/IO37RSB0V0

V_CCIB0 V_CCIB0

GBB0/IO27RSB0V0 GBC0/IO34RSB0V0

V_CC33PMP

NC

GBC1/IO26RSB0V0

IO24RSB0V0

IO21RSB0V0

V_CCIB0

IO33RSB0V0

IO29RSB0V0

IO26RSB0V0

V_CCIB0

AV0

AG0

ATRTN0

AG1

ATRTN0

AG1

IO15RSB0V0

IO10RSB0V0

IO07RSB0V0

GAC0/IO04RSB0V0

IO21RSB0V0

IO13RSB0V0

IO10RSB0V0

IO06RSB0V0

AC1

AV2

AT2

AT3

GAB1/IO03RSB0V0 GAC1/IO05RSB0V0

V_CCV_CC

GAA1/IO01RSB0V0 GAB0/IO02RSB0V0

AC3

AV4

AC4

NC

AT4

V_COMPLA

NC

AG5

B2

GAA2/IO52PDB3V0 GAC2/IO74PDB3V0

GAC2/IO51PDB3V0 GFA2/IO71PDB3V0

GFB2/IO50PDB3V0 GFB2/IO70PSB3V0

NC

AV5

B3

ADCGNDREF

V_CC33A

GNDA

PTBASE

V_CCNVM

ADCGNDREF

V_CC33A

GNDA

PTBASE

V_CCNVM

B4

B5

V_CC

B6

GFC0/IO49NDB3V0 GFC0/IO68NDB3V0

B7

GEB1/IO45PDB3V0

V_CCOSC

NC

B8

V_CCOSC

4-4

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

180-Pin QFN

Pin Number AFS090 Function

GCB2/IO33PSB1V0 GBC2/IO42PSB1V0

V_CCV_CC

GBA2/IO31PDB1V0 GBA2/IO40PDB1V0

GNDQ GNDQ

Pin Number AFS090 Function

AFS250 Function

B9

XTAL2

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

C1

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

GEA0/IO44NDB3V0 GFA0/IO66NDB3V0

GEB2/IO42PDB3V0

V_CC

IO60NDB3V0

V_CC

GBA1/IO30RSB0V0 GBA0/IO38RSB0V0

GBB1/IO28RSB0V0 GBC1/IO35RSB0V0

V_CCNVM

V_CC15A

NCAP

VCC33N

GNDAQ

AC0

V_CCNVM

V_CC15A

NCAP

VCC33N

GNDAQ

AC0

V_CC

GBC0/IO25RSB0V0

IO23RSB0V0

IO20RSB0V0

V_CC

IO31RSB0V0

IO28RSB0V0

IO25RSB0V0

V_CC

AT0

IO11RSB0V0

IO08RSB0V0

GAC1/IO05RSB0V0

V_CCIB0

IO14RSB0V0

IO11RSB0V0

IO08RSB0V0

V_CCIB0

AT1

AV1

AC2

ATRTN1

AG3

ATRTN1

AG3

GAB0/IO02RSB0V0 GAC0/IO04RSB0V0

GAA0/IO00RSB0V0 GAA1/IO01RSB0V0

AV3

V_CCPLA

NC

V_CCPLA

NC

AG4

ATRTN2

NC

ATRTN2

AC5

C2

NC

V_CCIB3

C3

GND

NC

GND

V_CC33A

VAREF

PUB

V_CC33A

VAREF

PUB

C4

GFC2/IO69PPB3V0

C5

GFC1/IO49PDB3V0 GFC1/IO68PDB3V0

GFA0/IO47NPB3V0 GFB0/IO67NPB3V0

C6

PTEM

GNDNVM

V_CC

PTEM

GNDNVM

V_CC

C7

V_CCIB3

GND

NC

C8

GND

C9

GEA1/IO44PDB3V0 GFA1/IO66PDB3V0

GEA2/IO42NDB3V0 GEC2/IO60PDB3V0

V_CC

C10

C11

C12

C13

C14

C15

C16

C17

C18

TCK

NC

GEA2/IO58PSB3V0

TMS

NC

GND

NC

TRST

GND

NC

GDB2/IO41PSB1V0 GDA2/IO55PSB1V0

GDC0/IO38NDB1V0 GDB0/IO53NDB1V0

NC

V_CCIB1

GNDA

NC

GNDA

NC

GCA1/IO36PDB1V0 GCA1/IO49PDB1V0

GCC0/IO34NDB1V0 GCC0/IO47NDB1V0

NC

Preliminary v1.7

4-5

Package Pin Assignments

180-Pin QFN

Pin Number AFS090 Function

180-Pin QFN

AFS250 Function

Pin Number AFS090 Function

AFS250 Function

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

C51

C52

C53

C54

NC

C55

C56

D1

NC

GAA0/IO00RSB0V0

NC

AG2

NC

AG2

NC

D2

NC

D3

NC

D4

NC

AT5

GNDAQ

NC

GNDAQ

NC

GND

NC

GND

NC

GND

GDB0/IO39NPB1V0 GDA0/IO54NPB1V0

GDA1/IO37NSB1V0 GDC0/IO52NSB1V0

GCA0/IO36NDB1V0 GCA0/IO49NDB1V0

GCB1/IO35PPB1V0 GCB1/IO48PPB1V0

GND

IO41NPB1V0

IO40NDB1V0

NC

GCA2/IO32NPB1V0

GBB2/IO31NDB1V0

NC

GBA1/IO39RSB0V0

GBB0/IO36RSB0V0

GND

NC

GND

NC

IO30RSB0V0

IO27RSB0V0

GND

IO22RSB0V0

GND

IO13RSB0V0

IO09RSB0V0

IO06RSB0V0

GND

IO16RSB0V0

IO12RSB0V0

IO09RSB0V0

GND

NC

GAB1/IO03RSB0V0

4-6

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

208-Pin PQFP

208

1

208-Pin PQFP

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

Preliminary v1.7

4-7

Package Pin Assignments

208-Pin PQFP

Pin Number AFS250 Function

208-Pin PQFP

AFS600 Function

V_CCPLA

Pin Number AFS250 Function

AFS600 Function

1

V_CCPLA

V_COMPLA

GNDQ

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

GEC2/IO60PDB3V0 GEB1/IO62PDB4V0

2

V_COMPLA

IO60NDB3V0

GND

GEB0/IO62NDB4V0

GEA1/IO61PDB4V0

GEA0/IO61NDB4V0

3

GAA2/IO85PDB4V0

IO85NDB4V0

4

V_CCIB3

5

GAA2/IO76PDB3V0 GAB2/IO84PDB4V0

IO76NDB3V0 IO84NDB4V0

GAB2/IO75PDB3V0 GAC2/IO83PDB4V0

GEB2/IO59PDB3V0 GEC2/IO60PDB4V0

6

IO59NDB3V0

IO60NDB4V0

V_CCIB4

GNDQ

V_CC

7

GEA2/IO58PDB3V0

IO58NDB3V0

V_CC

8

IO75NDB3V0

NC

IO83NDB4V0

IO77PDB4V0

IO77NDB4V0

IO76PDB4V0

IO76NDB4V0

V_CC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

NC

V_CC

V_CCNVM

GNDNVM

GND

V_CCNVM

GNDNVM

GND

V_CCIB3

IO72PDB3V0

IO72NDB3V0

GND

V_CC15A

PCAP

NCAP

V_CC33PMP

VCC33N

GNDA

GNDAQ

NC

V_CC15A

PCAP

NCAP

V_CC33PMP

VCC33N

GNDA

GNDAQ

AV0

V_CCIB4

GFA2/IO71PDB3V0 GFA2/IO75PDB4V0

IO71NDB3V0 IO75NDB4V0

GFB2/IO70PDB3V0 GFC2/IO73PDB4V0

IO70NDB3V0

GFC2/IO69PDB3V0

IO69NDB3V0

V_CC

IO73NDB4V0

V_CCOSC

XTAL1

XTAL2

NC

AC0

GND

GNDOSC

NC

AG0

V_CCIB3

GFC1/IO72PDB4V0

NC

AT0

GFC1/IO68PDB3V0 GFC0/IO72NDB4V0

GFC0/IO68NDB3V0 GFB1/IO71PDB4V0

GFB1/IO67PDB3V0 GFB0/IO71NDB4V0

GFB0/IO67NDB3V0 GFA1/IO70PDB4V0

NC

ATRTN0

AT1

NC

AG1

NC

AC1

V_CCOSC

XTAL1

GFA0/IO70NDB4V0

IO69PDB4V0

IO69NDB4V0

V_CC

NC

AV1

AV0

AV2

XTAL2

AC0

AC2

GNDOSC

AG0

AG2

GEB1/IO62PDB3V0

GEB0/IO62NDB3V0

GND

AT0

AT2

V_CCIB4

ATRTN0

AT1

ATRTN1

AT3

GEA1/IO61PDB3V0 GEC1/IO63PDB4V0

GEA0/IO61NDB3V0 GEC0/IO63NDB4V0

AG1

AG3

4-8

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

208-Pin PQFP

Pin Number AFS250 Function

AFS600 Function

AC3

AFS600 Function

PTEM

72

73

AC1

AV1

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

PTEM

PTBASE

GNDNVM

V_CCNVM

V_CC

AV3

PTBASE

74

AV2

AV4

GNDNVM

V_CCNVM

75

AC2

AC4

76

AG2

AT2

AG4

V_CC

77

AT4

V_CC

78

ATRTN1

AT3

ATRTN2

AT5

V_PUMP

79

GNDQ

NC

80

AG3

AC3

AG5

V_CCIB1

TCK

81

AC5

TCK

TDI

82

AV3

AV5

TDI

TMS

83

AV4

AV6

TMS

TDO

84

AC4

AC6

TDO

TRST

85

AG4

AT4

AG6

TRST

V_JTAG

86

AT6

V_JTAG

IO57NDB2V0

GDC2/IO57PDB2V0

IO56NDB2V0

GDB2/IO56PDB2V0

IO55NDB2V0

GDA2/IO55PDB2V0

87

ATRTN2

AT5

ATRTN3

AT7

IO57NDB1V0

GDC2/IO57PDB1V0

IO56NDB1V0

GDB2/IO56PDB1V0

V_CCIB1

88

89

AG5

AC5

AG7

90

AC7

91

AV5

AV7

92

NC

AV8

GND

GDA0/IO54NDB2V

0

93

NC

AC8

128

129

130

131

132

133

134

135

136

137

138

139

140

141

IO55NDB1V0

GDA1/IO54PDB2V0

94

NC

AG8

GDA2/IO55PDB1V0

GDA0/IO54NDB1V0

GDA1/IO54PDB1V0

V_CCIB2

GND

V_CC

95

NC

AT8

96

NC

ATRTN4

AT9

97

NC

GDB0/IO53NDB1V0 GCA0/IO45NDB2V0

GDB1/IO53PDB1V0 GCA1/IO45PDB2V0

GDC0/IO52NDB1V0 GCB0/IO44NDB2V0

GDC1/IO52PDB1V0 GCB1/IO44PDB2V0

98

NC

AG9

99

NC

AC9

100

101

102

103

104

105

106

107

NC

AV9

GNDAQ

V_CC33A

ADCGNDREF

VAREF

PUB

GNDAQ

V_CC33A

ADCGNDREF

VAREF

PUB

IO51NSB1V0

V_CCIB1

GCC0/IO43NDB2V0

GCC1/IO43PDB2V0

IO42NDB2V0

GND

V_CC

IO42PDB2V0

IO50NDB1V0

IO50PDB1V0

IO41NDB2V0

V_CC33A

GNDA

V_CC33A

GNDA

GCC2/IO41PDB2V0

Preliminary v1.7

4-9

Package Pin Assignments

208-Pin PQFP

Pin Number AFS250 Function

208-Pin PQFP

AFS600 Function

V_CCIB2

Pin Number AFS250 Function

AFS600 Function

IO14NSB0V1

IO12PDB0V1

IO12NDB0V1

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

GCA0/IO49NDB1V0

GCA1/IO49PDB1V0

GCB0/IO48NDB1V0

GCB1/IO48PDB1V0

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

IO24RSB0V0

IO23RSB0V0

IO22RSB0V0

IO21RSB0V0

IO20RSB0V0

IO19RSB0V0

IO18RSB0V0

IO17RSB0V0

IO16RSB0V0

IO15RSB0V0

V_CCIB0

GND

V_CC

IO40NDB2V0

V_CCIB0

GCC0/IO47NDB1V0 GCB2/IO40PDB2V0

GND

V_CC

GCC1/IO47PDB1V0

IO42NDB1V0

GBC2/IO42PDB1V0

V_CCIB1

IO39NDB2V0

GCA2/IO39PDB2V0

IO31NDB2V0

GBB2/IO31PDB2V0

IO30NDB2V0

GBA2/IO30PDB2V0

V_CCIB2

IO10PPB0V1

IO09PPB0V1

IO10NPB0V1

IO09NPB0V1

IO08PPB0V1

IO07PPB0V1

IO08NPB0V1

IO07NPB0V1

IO06PPB0V0

IO05PPB0V0

IO06NPB0V0

IO04PPB0V0

IO05NPB0V0

IO04NPB0V0

GAC1/IO03PDB0V0

GAC0/IO03NDB0V0

V_CCIB0

GND

V_CC

IO41NDB1V0

GBB2/IO41PDB1V0

IO40NDB1V0

GBA2/IO40PDB1V0

GBA1/IO39RSB0V0

GBA0/IO38RSB0V0

GND

GNDQ

V_CC

V_COMPLB

IO14RSB0V0

IO13RSB0V0

IO12RSB0V0

IO11RSB0V0

IO10RSB0V0

IO09RSB0V0

IO08RSB0V0

IO07RSB0V0

IO06RSB0V0

GAC1/IO05RSB0V0

V_CCIB0

V_CCPLB

V_CCIB1

GNDQ

GBB1/IO37RSB0V0 GBB1/IO27PPB1V1

GBB0/IO36RSB0V0 GBA1/IO28PPB1V1

GBC1/IO35RSB0V0 GBB0/IO27NPB1V1

V_CCIB0

GND

GBA0/IO28NPB1V1

_CCIB1

V

V_CC

GND

V_CC

GBC0/IO34RSB0V0

IO33RSB0V0

IO32RSB0V0

IO31RSB0V0

IO30RSB0V0

IO29RSB0V0

IO28RSB0V0

IO27RSB0V0

IO26RSB0V0

IO25RSB0V0

V_CCIB0

GND

GBC1/IO26PDB1V1

GBC0/IO26NDB1V1

IO24PPB1V1

IO23PPB1V1

IO24NPB1V1

IO23NPB1V1

IO22PPB1V0

IO21PPB1V0

IO22NPB1V0

IO21NPB1V0

IO20PSB1V0

IO19PSB1V0

GND

V_CC

GAB1/IO02PDB0V0

GAC0/IO04RSB0V0 GAB0/IO02NDB0V0

GAB1/IO03RSB0V0 GAA1/IO01PDB0V0

GAB0/IO02RSB0V0 GAA0/IO01NDB0V

0

207

208

GAA1/IO01RSB0V0

GAA0/IO00RSB0V0

GNDQ

V_CCIB0

GND

V_CC

4-10

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

256-Pin FBGA

A1 Ball Pad Corner

1

7

6

4

5

3

2

16 15 14 13 12 11 10 9

8

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

Preliminary v1.7

4-11

Package Pin Assignments

256-Pin FBGA

AFS250 Function

GND

Pin Number

AFS090 Function

AFS600 Function

GND

AFS1500 Function

GND

A1

A2

GND

V_CCIB0

A3

A4

GAB0/IO02RSB0V0

GAB1/IO03RSB0V0

GND

GAA0/IO00RSB0V0

GAA1/IO01RSB0V0

GND

GAA0/IO01NDB0V0

GAA1/IO01PDB0V0

GND

GAA0/IO01NDB0V0

GAA1/IO01PDB0V0

GND

A5

A6

IO07RSB0V0

IO10RSB0V0

IO11RSB0V0

IO16RSB0V0

IO17RSB0V0

IO18RSB0V0

GND

IO11RSB0V0

IO14RSB0V0

IO15RSB0V0

IO24RSB0V0

IO25RSB0V0

IO26RSB0V0

GND

IO10PDB0V1

IO12PDB0V1

IO12NDB0V1

IO22NDB1V0

IO22PDB1V0

IO24NDB1V1

GND

IO07PDB0V1

IO13PDB0V2

IO13NDB0V2

IO24NDB1V0

IO24PDB1V0

IO29NDB1V1

GND

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

B1

GBC0/IO25RSB0V0

GBA0/IO29RSB0V0

GBA0/IO38RSB0V0

IO32RSB0V0

V_CCIB0

GBA0/IO28NDB1V1

IO29NDB1V1

V_CCIB1

GBA0/IO42NDB1V2

IO43NDB1V2

V_CCIB1

V_CCIB0

GND

V_COMPLA

GND

V_COMPLA

B2

V_CCPLA

B3

GAA0/IO00RSB0V0

GAA1/IO01RSB0V0

NC

IO07RSB0V0

IO06RSB0V0

GAB1/IO03RSB0V0

IO10RSB0V0

V_CCIB0

IO00NDB0V0

IO00PDB0V0

GAB1/IO02PPB0V0

IO10NDB0V1

V_CCIB0

IO00NDB0V0

IO00PDB0V0

GAB1/IO02PPB0V0

IO07NDB0V1

V_CCIB0

B4

B5

B6

IO06RSB0V0

B7

V_CCIB0

B8

IO12RSB0V0

IO13RSB0V0

IO16RSB0V0

IO17RSB0V0

V_CCIB0

IO18NDB1V0

IO18PDB1V0

V_CCIB1

IO22NDB1V0

IO22PDB1V0

V_CCIB1

B9

B10

B11

B12

B13

B14

B15

B16

C1

V_CCIB0

IO19RSB0V0

GBB0/IO27RSB0V0

GBC1/IO26RSB0V0

GBA1/IO30RSB0V0

NC

IO27RSB0V0

GBC0/IO34RSB0V0

GBA1/IO39RSB0V0

IO33RSB0V0

NC

IO24PDB1V1

GBC0/IO26NPB1V1

GBA1/IO28PDB1V1

IO29PDB1V1

V_CCPLB

IO29PDB1V1

GBC0/IO40NPB1V2

GBA1/IO42PDB1V2

IO43PDB1V2

V_CCPLB

NC

V_COMPLB

V_CCIB3

V_CCIB4

C2

GND

C3

V

_CCIB3

NC

V_CCIB3

V_CCIB4

C4

NC

V_CCIB0

C5

V_CCIB0

C6

GAC1/IO05RSB0V0

GAC1/IO03PDB0V0

4-12

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

256-Pin FBGA

AFS250 Function

IO12RSB0V0

IO22RSB0V0

IO23RSB0V0

IO30RSB0V0

IO31RSB0V0

V_CCIB0

Pin Number

C7

AFS090 Function

IO09RSB0V0

IO14RSB0V0

IO15RSB0V0

IO22RSB0V0

IO20RSB0V0

AFS600 Function

AFS1500 Function

IO09NDB0V1

IO23PDB1V0

IO23NDB1V0

IO31NDB1V1

IO31PDB1V1

V_CCIB1

IO06NDB0V0

IO16PDB1V0

IO16NDB1V0

IO25NDB1V1

IO25PDB1V1

V_CCIB1

C8

C9

C10

C11

C12

C13

C14

C15

C16

D1

V_CCIB0

GBB1/IO28RSB0V0

V_CCIB1

GBC1/IO35RSB0V0

V_CCIB1

GBC1/IO26PPB1V1

V_CCIB2

GBC1/IO40PPB1V2

V_CCIB2

GND

V_CCIB1

V_CCIB2

GFC2/IO50NPB3V0

GFA2/IO51NDB3V0

GAC2/IO51PDB3V0

GAA2/IO52PDB3V0

GAB2/IO52NDB3V0

GAC0/IO04RSB0V0

IO08RSB0V0

IO75NDB3V0

GAB2/IO75PDB3V0

IO76NDB3V0

GAA2/IO76PDB3V0

GAB0/IO02RSB0V0

GAC0/IO04RSB0V0

IO13RSB0V0

IO20RSB0V0

IO21RSB0V0

IO28RSB0V0

GBB0/IO36RSB0V0

NC

IO84NDB4V0

GAB2/IO84PDB4V0

IO85NDB4V0

GAA2/IO85PDB4V0

GAB0/IO02NPB0V0

GAC0/IO03NDB0V0

IO06PDB0V0

IO14NDB0V1

IO14PDB0V1

IO23PDB1V1

GBB0/IO27NDB1V1

IO124NDB4V0

GAB2/IO124PDB4V0

IO125NDB4V0

GAA2/IO125PDB4V0

GAB0/IO02NPB0V0

GAC0/IO03NDB0V0

IO09PDB0V1

IO15NDB0V2

IO15PDB0V2

IO37PDB1V2

GBB0/IO41NDB1V2

V_CCIB1

D2

D3

D4

D5

D6

D7

D8

NC

D9

NC

D10

D11

D12

D13

D14

D15

D16

E1

IO21RSB0V0

IO23RSB0V0

NC

V_CCIB1

GBA2/IO31PDB1V0

GBB2/IO31NDB1V0

GBC2/IO32PDB1V0

GCA2/IO32NDB1V0

GND

GBA2/IO40PDB1V0

IO40NDB1V0

GBB2/IO41PDB1V0

IO41NDB1V0

GND

GBA2/IO30PDB2V0

IO30NDB2V0

GBB2/IO31PDB2V0

IO31NDB2V0

GND

GBA2/IO44PDB2V0

IO44NDB2V0

GBB2/IO45PDB2V0

IO45NDB2V0

GND

E2

GFB0/IO48NPB3V0

GFB2/IO50PPB3V0

IO73NDB3V0

IO73PDB3V0

V_CCIB3

IO81NDB4V0

IO81PDB4V0

V_CCIB4

IO118NDB4V0

IO118PDB4V0

V_CCIB4

E3

E4

V_CCIB3

E5

NC

IO74NPB3V0

IO08RSB0V0

GND

IO83NPB4V0

IO04NPB0V0

GND

IO123NPB4V0

IO05NPB0V1

GND

E6

NC

E7

GND

NC

E8

IO18RSB0V0

NC

IO08PDB0V1

IO20NDB1V0

GND

IO11PDB0V1

IO27NDB1V1

GND

E9

NC

E10

E11

E12

GND

IO24RSB0V0

NC

GBB1/IO37RSB0V0

IO50PPB1V0

GBB1/IO27PDB1V1

IO33PSB2V0

GBB1/IO41PDB1V2

IO48PSB2V0

Preliminary v1.7

4-13

Package Pin Assignments

256-Pin FBGA

AFS250 Function

V_CCIB1

Pin Number

AFS090 Function

AFS600 Function

V_CCIB2

AFS1500 Function

V_CCIB2

E13

V_CCIB1

E14

E15

E16

F1

GCC2/IO33NDB1V0

IO42NDB1V0

GBC2/IO42PDB1V0

GND

IO32NDB2V0

GBC2/IO32PDB2V0

GND

IO46NDB2V0

GBC2/IO46PDB2V0

GND

GCB2/IO33PDB1V0

GND

NC

IO79NDB4V0

IO79PDB4V0

IO76NDB4V0

IO76PDB4V0

IO82PSB4V0

GAC2/IO83PPB4V0

IO04PPB0V0

IO08NDB0V1

IO20PDB1V0

IO23NDB1V1

IO36NDB2V0

IO36PDB2V0

IO39NDB2V0

GCA2/IO39PDB2V0

GCB2/IO40PDB2V0

IO40NDB2V0

IO74NPB4V0

V_CCIB4

IO111NDB4V0

IO111PDB4V0

IO112NDB4V0

IO112PDB4V0

IO120PSB4V0

GAC2/IO123PPB4V0

IO05PPB0V1

IO11NDB0V1

IO27PDB1V1

IO37NDB1V2

IO50NDB2V0

IO50PDB2V0

IO59NDB2V0

GCA2/IO59PDB2V0

GCB2/IO60PDB2V0

IO60NDB2V0

IO109NPB4V0

V_CCIB4

F2

NC

F3

GFB1/IO48PPB3V0

IO72NDB3V0

IO72PDB3V0

NC

F4

GFC0/IO49NDB3V0

F5

NC

F6

GFC1/IO49PDB3V0

GAC2/IO74PPB3V0

IO09RSB0V0

IO19RSB0V0

NC

F7

NC

F8

NC

F9

NC

F10

F11

F12

F13

F14

F15

F16

G1

NC

IO29RSB0V0

IO43NDB1V0

IO43PDB1V0

IO44NDB1V0

GCA2/IO44PDB1V0

GCB2/IO45PDB1V0

IO45NDB1V0

IO70NPB3V0

V_CCIB3

NC

GCC1/IO34PDB1V0

GCC0/IO34NDB1V0

GEC0/IO46NPB3V0

G2

V_CCIB3

G3

GEC1/IO46PPB3V0

GFA1/IO47PDB3V0

GND

GFB2/IO70PPB3V0

GFA2/IO71PDB3V0

GND

GFB2/IO74PPB4V0

GFA2/IO75PDB4V0

GND

GFB2/IO109PPB4V0

GFA2/IO110PDB4V0

GND

G4

G5

G6

GFA0/IO47NDB3V0

GND

IO71NDB3V0

GND

IO75NDB4V0

GND

IO110NDB4V0

GND

G7

G8

V_CC

G9

GND

G10

G11

G12

G13

G14

G15

G16

H1

V_CC

GDA1/IO37NDB1V0

GND

GCC0/IO47NDB1V0

GND

GCC0/IO43NDB2V0

GND

GCC0/IO62NDB2V0

GND

IO37PDB1V0

GCB0/IO35NPB1V0

GCC1/IO47PDB1V0

IO46NPB1V0

V_CCIB1

GCC1/IO43PDB2V0

IO41NPB2V0

V_CCIB2

GCC1/IO62PDB2V0

IO61NPB2V0

V_CCIB2

V

_CCIB1

GCB1/IO35PPB1V0

GEB1/IO45PDB3V0

GEB0/IO45NDB3V0

GCC2/IO46PPB1V0

GFC2/IO69PDB3V0

IO69NDB3V0

GCC2/IO41PPB2V0

GFC2/IO73PDB4V0

IO73NDB4V0

GCC2/IO61PPB2V0

GFC2/IO108PDB4V0

IO108NDB4V0

H2

4-14

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

256-Pin FBGA

AFS250 Function

XTAL2

Pin Number

H3

AFS090 Function

AFS600 Function

AFS1500 Function

XTAL2

XTAL1

H4

XTAL1

H5

GNDOSC

H6

V_CCOSC

H7

V_CC

H8

GND

H9

V_CC

GND

V_CC

H10

H11

H12

H13

H14

H15

H16

J1

GND

GDC0/IO38NDB1V0

GDC1/IO38PDB1V0

GDB1/IO39PDB1V0

GDB0/IO39NDB1V0

GCA0/IO36NDB1V0

GCA1/IO36PDB1V0

GEA0/IO44NDB3V0

GEA1/IO44PDB3V0

IO43NDB3V0

GEC2/IO43PDB3V0

NC

IO51NDB1V0

IO51PDB1V0

GCA1/IO49PDB1V0

GCA0/IO49NDB1V0

GCB0/IO48NDB1V0

GCB1/IO48PDB1V0

GFA0/IO66NDB3V0

GFA1/IO66PDB3V0

GFB0/IO67NDB3V0

GFB1/IO67PDB3V0

GFC0/IO68NDB3V0

GFC1/IO68PDB3V0

GND

IO47NDB2V0

IO47PDB2V0

GCA1/IO45PDB2V0

GCA0/IO45NDB2V0

GCB0/IO44NDB2V0

GCB1/IO44PDB2V0

GFA0/IO70NDB4V0

GFA1/IO70PDB4V0

GFB0/IO71NDB4V0

GFB1/IO71PDB4V0

GFC0/IO72NDB4V0

GFC1/IO72PDB4V0

GND

IO69NDB2V0

IO69PDB2V0

GCA1/IO64PDB2V0

GCA0/IO64NDB2V0

GCB0/IO63NDB2V0

GCB1/IO63PDB2V0

GFA0/IO105NDB4V0

GFA1/IO105PDB4V0

GFB0/IO106NDB4V0

GFB1/IO106PDB4V0

GFC0/IO107NDB4V0

GFC1/IO107PDB4V0

GND

J2

J3

J4

J5

J6

NC

J7

GND

J8

V_CC

J9

GND

J10

J11

J12

J13

J14

J15

J16

K1

V_CC

GDC2/IO41NPB1V0

NC

IO56NPB1V0

GDB0/IO53NPB1V0

GDA1/IO54PDB1V0

GDC1/IO52PPB1V0

IO50NPB1V0

GDC0/IO52NPB1V0

IO65NPB3V0

V_CCIB3

IO56NPB2V0

GDB0/IO53NPB2V0

GDA1/IO54PDB2V0

GDC1/IO52PPB2V0

IO51NSB2V0

GDC0/IO52NPB2V0

IO67NPB4V0

V_CCIB4

IO83NPB2V0

GDB0/IO80NPB2V0

GDA1/IO81PDB2V0

GDC1/IO79PPB2V0

IO77NSB2V0

GDC0/IO79NPB2V0

IO92NPB4V0

V_CCIB4

NC

GDA0/IO40PDB1V0

NC

GDA2/IO40NDB1V0

NC

K2

V

_CCIB3

K3

NC

IO65PPB3V0

IO64PDB3V0

GND

IO67PPB4V0

IO65PDB4V0

GND

IO92PPB4V0

IO96PDB4V0

GND

K4

NC

K5

GND

NC

K6

IO64NDB3V0

V_CC

IO65NDB4V0

V_CC

IO96NDB4V0

V_CC

K7

V_CC

K8

GND

Preliminary v1.7

4-15

Package Pin Assignments

256-Pin FBGA

AFS250 Function

V_CC

Pin Number

K9

AFS090 Function

AFS600 Function

V_CC

AFS1500 Function

V_CC

GND

NC

K10

K11

K12

K13

K14

K15

K16

L1

GND

GDC2/IO57PPB1V0

GND

GDC2/IO57PPB2V0

GND

GDC2/IO84PPB2V0

GND

NC

GDA0/IO54NDB1V0

GDA2/IO55PPB1V0

V_CCIB1

GDA0/IO54NDB2V0

GDA2/IO55PPB2V0

V_CCIB2

GDA0/IO81NDB2V0

GDA2/IO82PPB2V0

V_CCIB2

NC

V

_CCIB1

NC

GDB1/IO53PPB1V0

GEC1/IO63PDB3V0

GEC0/IO63NDB3V0

GEB1/IO62PDB3V0

GEB0/IO62NDB3V0

IO60NDB3V0

GEC2/IO60PDB3V0

GNDA

GDB1/IO53PPB2V0

GEC1/IO63PDB4V0

GEC0/IO63NDB4V0

GEB1/IO62PDB4V0

GEB0/IO62NDB4V0

IO60NDB4V0

GEC2/IO60PDB4V0

GNDA

GDB1/IO80PPB2V0

GEC1/IO90PDB4V0

GEC0/IO90NDB4V0

GEB1/IO89PDB4V0

GEB0/IO89NDB4V0

IO87NDB4V0

GEC2/IO87PDB4V0

GNDA

L2

L3

L4

L5

L6

L7

GNDA

AC0

L8

AC0

AC2

L9

AV2

AV4

L10

L11

L12

L13

L14

AC3

AC5

PTEM

TDO

V_JTAG

NC

PTEM

TDO

V_JTAG

IO57NPB1V0

GDB2/IO56PPB1V0

IO55NPB1V0

GND

IO57NPB2V0

GDB2/IO56PPB2V0

IO55NPB2V0

GND

IO84NPB2V0

GDB2/IO83PPB2V0

IO82NPB2V0

GND

L15

L16

M1

GDB2/IO41PPB1V0

NC

GND

NC

M2

GEA1/IO61PDB3V0

GEA0/IO61NDB3V0

V_CCIB3

GEA1/IO61PDB4V0

GEA0/IO61NDB4V0

V_CCIB4

GEA1/IO88PDB4V0

GEA0/IO88NDB4V0

V_CCIB4

M3

NC

M4

V_CCIB3

M5

NC

IO58NPB3V0

NC

IO58NPB4V0

AV0

IO85NPB4V0

AV0

M6

NC

M7

NC

AC1

M8

AG1

AC2

AG1

AG3

M9

AC2

AC4

M10

M11

M12

M13

M14

AC4

AC6

NC

AG5

AG7

V_PUMP

V_CCIB1

TMS

V_PUMP

V_CCIB1

V_CCIB2

TMS

4-16

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

256-Pin FBGA

Pin Number

M15

M16

N1

AFS090 Function

AFS250 Function

AFS600 Function

AFS1500 Function

TRST

GND

TRST

GND

GEB2/IO42PDB3V0

GEB2/IO59PDB3V0

IO59NDB3V0

GEA2/IO58PPB3V0

V_CC33PMP

V_CC15A

NC

GEB2/IO59PDB4V0

IO59NDB4V0

GEA2/IO58PPB4V0

V_CC33PMP

V_CC15A

AG0

GEB2/IO86PDB4V0

IO86NDB4V0

GEA2/IO85PPB4V0

V_CC33PMP

V_CC15A

AG0

N2

GEA2/IO42NDB3V0

NC

N3

N4

V_CC33PMP

V_CC15A

NC

N5

N6

N7

AC1

AC3

N8

AG3

AG5

N9

AV3

AV5

N10

N11

N12

N13

N14

N15

N16

P1

AG4

AG6

NC

AC8

GNDA

V_CC33A

V_CCNVM

TCK

GNDA

V_CC33A

V_CCNVM

TCK

GNDA

V_CC33A

V_CCNVM

TCK

GNDA

V_CC33A

V_CCNVM

TCK

TDI

V_CCNVM

GNDNVM

GNDA

NC

V_CCNVM

GNDNVM

GNDA

NC

V_CCNVM

GNDNVM

GNDA

AC0

V_CCNVM

GNDNVM

GNDA

AC0

P2

P3

P4

P5

NC

AG1

P6

NC

AV1

P7

AG0

AG2

P8

AG2

AG4

P9

GNDA

NC

GNDA

AC5

GNDA

AC7

GNDA

AC7

P10

P11

P12

P13

P14

P15

P16

R1

NC

AV8

NC

AG8

NC

AV9

ADCGNDREF

PTBASE

GNDNVM

ADCGNDREF

PTBASE

GNDNVM

V_CCIB3

PCAP

ADCGNDREF

PTBASE

GNDNVM

V_CCIB4

PCAP

ADCGNDREF

PTBASE

GNDNVM

V_CCIB4

PCAP

V_CCIB3

R2

PCAP

NC

R3

NC

AT1

R4

NC

AT0

Preliminary v1.7

4-17

Package Pin Assignments

256-Pin FBGA

Pin Number

R5

AFS090 Function

AFS250 Function

AV0

AFS600 Function

AV2

AFS1500 Function

AV2

AV0

AT0

AV1

AT3

AV4

NC

R6

AT0

AT2

R7

AV1

AV3

R8

AT3

AT5

R9

AV4

AV6

R10

R11

R12

R13

R14

R15

R16

T1

AT5

AT7

NC

AV5

AV7

NC

AT9

NC

AG9

NC

AC9

PUB

V_CCIB1

GND

V_CCIB2

GND

V_CCIB2

GND

NCAP

VCC33N

NC

T2

NCAP

VCC33N

NC

NCAP

VCC33N

ATRTN0

AT3

NCAP

VCC33N

ATRTN0

AT3

T3

T4

T5

AT1

T6

ATRTN0

AT2

ATRTN0

AT2

ATRTN1

AT4

ATRTN1

AT4

T7

T8

ATRTN1

AT4

ATRTN1

AT4

ATRTN2

AT6

ATRTN2

AT6

T9

T10

T11

T12

T13

T14

T15

T16

ATRTN2

NC

ATRTN2

NC

ATRTN3

AT8

ATRTN3

AT8

NC

ATRTN4

GNDA

V_CC33A

VAREF

GND

ATRTN4

GNDA

V_CC33A

VAREF

GND

GNDA

V_CC33A

VAREF

GND

GNDA

V_CC33A

VAREF

GND

4-18

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

484-Pin FBGA

A1 Ball Pad Corner

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

Preliminary v1.7

4-19

Package Pin Assignments

484-Pin FBGA

Pin Number AFS600 Function

484-Pin FBGA

AFS1500 Function

Pin Number AFS600 Function

AFS1500 Function

AG8

A1

A2

GND

V_CC

GND

NC

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AB1

AG8

GNDA

AG9

GNDA

AG9

A3

GAA1/IO01PDB0V0 GAA1/IO01PDB0V0

GAB0/IO02NDB0V0 GAB0/IO02NDB0V0

GAB1/IO02PDB0V0 GAB1/IO02PDB0V0

A4

VAREF

V_CCIB2

PTEM

GND

A5

V_CCIB2

A6

IO07NDB0V1

IO07PDB0V1

IO10PDB0V1

IO14NDB0V1

IO14PDB0V1

IO17PDB1V0

IO18PDB1V0

IO19NDB1V0

IO19PDB1V0

IO24NDB1V1

IO24PDB1V1

IO07NDB0V1

IO07PDB0V1

IO09PDB0V1

IO13NDB0V2

IO13PDB0V2

IO24PDB1V0

IO26PDB1V0

IO27NDB1V1

IO27PDB1V1

IO35NDB1V2

IO35PDB1V2

PTEM

GND

V_CC

A7

A8

NC

A9

GND

V_CC

GND

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AB2

NC

AB3

NC

IO94NSB4V0

GND

AB4

GND

VCC33N

AT0

AB5

VCC33N

AT0

AB6

AB7

ATRTN0

AT1

ATRTN0

AT1

AB8

GBC0/IO26NDB1V1 GBC0/IO40NDB1V2

GBA0/IO28NDB1V1 GBA0/IO42NDB1V2

AB9

AT2

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

B1

ATRTN1

AT3

ATRTN1

AT3

IO29NDB1V1

IO29PDB1V1

V_CC

IO43NDB1V2

IO43PDB1V2

NC

AT6

ATRTN3

AT7

ATRTN3

AT7

GND

V_CC

NC

AT8

GND

ATRTN4

AT9

ATRTN4

AT9

V_CCIB4

PCAP

V_CCIB4

PCAP

AG0

V_CC33A

GND

NC

V_CC33A

GND

AG0

IO76NPB2V0

NC

GNDA

AG1

GNDA

AG1

V_CC

GND

V_CC

GND

AG2

NC

GNDA

AG3

GNDA

AG3

B2

GND

B3

GAA0/IO01NDB0V0 GAA0/IO01NDB0V0

AG6

B4

GND

GNDA

AG7

GNDA

AG7

B5

IO05NDB0V0

IO05PDB0V0

IO04NDB0V0

IO04PDB0V0

B6

4-20

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

484-Pin FBGA

Pin Number AFS600 Function

AFS1500 Function

GND

AFS1500 Function

B7

B8

GND

C21

C22

D1

NC

IO48PSB2V0

IO10NDB0V1

IO13PDB0V1

GND

IO09NDB0V1

IO11PDB0V1

GND

GBB2/IO31PDB2V0 GBB2/IO45PDB2V0

B9

IO82NDB4V0

GND

IO121NDB4V0

GND

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

C1

D2

IO17NDB1V0

IO18NDB1V0

GND

IO24NDB1V0

IO26NDB1V0

GND

D3

IO83NDB4V0

IO123NDB4V0

D4

GAC2/IO83PDB4V0 GAC2/IO123PDB4V

0

D5

GAA2/IO85PDB4V0 GAA2/IO125PDB4V

0

IO21NDB1V0

IO21PDB1V0

GND

IO31NDB1V1

IO31PDB1V1

GND

D6

D7

GAC0/IO03NDB0V0 GAC0/IO03NDB0V0

GAC1/IO03PDB0V0 GAC1/IO03PDB0V0

GBC1/IO26PDB1V1 GBC1/IO40PDB1V2

GBA1/IO28PDB1V1 GBA1/IO42PDB1V2

D8

IO09NDB0V1

IO09PDB0V1

IO11NDB0V1

IO16NDB1V0

IO16PDB1V0

NC

IO10NDB0V1

IO10PDB0V1

IO14NDB0V2

IO23NDB1V0

IO23PDB1V0

IO32NPB1V1

IO34NDB1V1

IO34PDB1V1

IO37PDB1V2

D9

GND

V_CCPLB

GND

V_CCPLB

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

E1

GND

V_CC

NC

IO82PDB4V0

NC

IO121PDB4V0

IO122PSB4V0

IO00NDB0V0

IO00PDB0V0

V_CCIB0

IO23NDB1V1

IO23PDB1V1

IO25PDB1V1

C2

C3

IO00NDB0V0

IO00PDB0V0

V_CCIB0

C4

GBB1/IO27PDB1V1 GBB1/IO41PDB1V2

C5

V_CCIB2

NC

V_CCIB2

IO47PPB2V0

IO44NDB2V0

GND

C6

IO06NDB0V0

IO06PDB0V0

V_CCIB0

IO05NDB0V1

IO05PDB0V1

V_CCIB0

C7

IO30NDB2V0

GND

C8

C9

IO13NDB0V1

IO11PDB0V1

V_CCIB0

IO11NDB0V1

IO14PDB0V2

V_CCIB0

IO31NDB2V0

IO81NDB4V0

IO81PDB4V0

V_CCIB4

IO45NDB2V0

IO120NDB4V0

IO120PDB4V0

V_CCIB4

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

E2

V

_CCIB1

V_CCIB1

E3

IO20NDB1V0

IO20PDB1V0

V_CCIB1

IO29NDB1V1

IO29PDB1V1

V_CCIB1

E4

GAB2/IO84PDB4V0 GAB2/IO124PDB4V

0

E5

E6

IO85NDB4V0

GND

IO125NDB4V0

GND

IO25NDB1V1

IO37NDB1V2

E7

V_CCIB0

NC

V_CCIB0

GBB0/IO27NDB1V1 GBB0/IO41NDB1V2

E8

IO08NDB0V1

IO08PDB0V1

GND

V_CCIB1

E9

NC

V_COMPLB

E10

GND

GBA2/IO30PDB2V0 GBA2/IO44PDB2V0

Preliminary v1.7

4-21

Package Pin Assignments

484-Pin FBGA

Pin Number AFS600 Function

484-Pin FBGA

AFS1500 Function

IO22NDB1V0

IO22PDB1V0

GND

Pin Number AFS600 Function

AFS1500 Function

IO116NDB4V0

IO116PDB4V0

V_CCIB4

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

F1

IO15NDB1V0

IO15PDB1V0

GND

G3

G4

IO78NDB4V0

IO78PDB4V0

V_CCIB4

G5

NC

IO32PPB1V1

IO36NPB1V2

V_CCIB1

G6

NC

IO117PDB4V0

V_CCIB4

NC

G7

V_CCIB4

V_CCIB1

GND

G8

GND

IO04NDB0V0

IO04PDB0V0

IO12NDB0V1

IO12PDB0V1

NC

GND

G9

IO06NDB0V1

IO06PDB0V1

IO16NDB0V2

IO16PDB0V2

IO28NDB1V1

IO28PDB1V1

GND

NC

IO47NPB2V0

IO49PDB2V0

V_CCIB2

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

H1

IO33PDB2V0

V

_CCIB2

IO32NDB2V0

IO46NDB2V0

GBC2/IO32PDB2V0 GBC2/IO46PDB2V0

NC

IO80NDB4V0

IO80PDB4V0

NC

IO118NDB4V0

IO118PDB4V0

IO119NSB4V0

IO124NDB4V0

GND

F2

NC

IO38PPB1V2

IO53PDB2V0

V_CCIB2

F3

NC

F4

IO84NDB4V0

GND

V_CCIB2

F5

IO36PDB2V0

IO36NDB2V0

GND

IO52PDB2V0

IO52NDB2V0

GND

F6

V_COMPLA

V_CCPLA

V_COMPLA

F7

V_CCPLA

F8

V_CCIB0

IO35NDB2V0

IO77NDB4V0

IO76PDB4V0

V_CCIB4

IO51NDB2V0

IO115NDB4V0

IO113PDB4V0

V_CCIB4

F9

IO08NDB0V1

IO08PDB0V1

V_CCIB0

IO12NDB0V1

IO12PDB0V1

V_CCIB0

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

G1

H2

H3

V_CCIB1

H4

IO79NDB4V0

IO79PDB4V0

NC

IO114NDB4V0

IO114PDB4V0

IO117NDB4V0

GND

IO22NDB1V0

IO22PDB1V0

V_CCIB1

IO30NDB1V1

IO30PDB1V1

V_CCIB1

H5

H6

H7

GND

NC

IO36PPB1V2

IO38NPB1V2

GND

H8

V_CC

NC

H9

V_CCIB0

GND

H10

H11

H12

H13

H14

H15

H16

GND

IO33NDB2V0

IO34PDB2V0

IO34NDB2V0

IO35PDB2V0

IO77PDB4V0

GND

IO49NDB2V0

IO50PDB2V0

IO50NDB2V0

IO51PDB2V0

IO115PDB4V0

GND

V_CCIB0

V_CCIB1

GND

V_CCIB1

GND

G2

GND

4-22

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

484-Pin FBGA

Pin Number AFS600 Function

AFS1500 Function

IO53NDB2V0

AFS1500 Function

GND

H17

H18

H19

H20

H21

H22

J1

NC

K8

K9

GND

V_CC

IO38PDB2V0

IO57PDB2V0

V_CC

GCA2/IO39PDB2V0 GCA2/IO59PDB2V0

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

L1

GND

V_CCIB2

V_CC

IO37NDB2V0

IO37PDB2V0

NC

IO54NDB2V0

IO54PDB2V0

IO112PPB4V0

IO113NDB4V0

GND

V_CC

GND

J2

IO76NDB4V0

GND

J3

GFB2/IO74PDB4V0 GFB2/IO109PDB4V0

IO40NDB2V0

NC

IO60NDB2V0

IO58PDB2V0

GND

J4

GFA2/IO75PDB4V0 GFA2/IO110PDB4V

0

GND

J5

J6

NC

IO112NPB4V0

IO104PDB4V0

IO111PDB4V0

V_CCIB4

GND

NC

IO68NPB2V0

IO61NDB2V0

GND

IO41NDB2V0

GND

J7

NC

J8

V_CCIB4

GND

V_CC

IO42NDB2V0

IO73NDB4V0

V_CCOSC

V_CCIB4

XTAL2

IO56NDB2V0

IO108NDB4V0

V_CCOSC

J9

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

K1

K2

K3

K4

K5

K6

K7

V_CC

L2

GND

V_CC

GND

L3

V_CCIB4

V_CC

L4

XTAL2

GND

V_CC

GND

L5

GFC1/IO72PDB4V0 GFC1/IO107PDB4V0

V_CCIB4 V_CCIB4

GFB1/IO71PDB4V0 GFB1/IO106PDB4V0

V_CC

L6

V_CCIB2

L7

GCB2/IO40PDB2V0 GCB2/IO60PDB2V0

L8

V_CCIB4

GND

V_CCIB4

GND

NC

IO58NDB2V0

IO57NDB2V0

IO59NDB2V0

L9

IO38NDB2V0

IO39NDB2V0

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

V_CC

GND

GCC2/IO41PDB2V0 GCC2/IO61PDB2V0

V_CC

NC

IO55PSB2V0

IO56PDB2V0

GND

IO42PDB2V0

V_CC

GFC2/IO73PDB4V0 GFC2/IO108PDB4V0

V_CCIB2

IO48PDB2V0

V_CCIB2

IO70PDB2V0

V_CCIB2

IO69PDB2V0

GND

IO74NDB4V0

IO75NDB4V0

GND

IO109NDB4V0

IO110NDB4V0

GND

V

_CCIB2

IO46PDB2V0

GCA1/IO45PDB2V0 GCA1/IO64PDB2V0

V_CCIB2 V_CCIB2

NC

IO104NDB4V0

IO111NDB4V0

NC

GCC0/IO43NDB2V0 GCC0/IO62NDB2V0

Preliminary v1.7

4-23

Package Pin Assignments

484-Pin FBGA

Pin Number AFS600 Function

484-Pin FBGA

AFS1500 Function

GCC1/IO43PDB2V0 GCC1/IO62PDB2V0

Pin Number AFS600 Function

AFS1500 Function

L22

M1

M2

M3

M4

M5

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

P1

V_CC

GND

V_CC

GND

V_CC

NC

IO103PDB4V0

XTAL1

V

_CCIB4

V_CCIB4

GND

GNDOSC

GDB2/IO56PDB2V0 GDB2/IO83PDB2V0

GFC0/IO72NDB4V0 GFC0/IO107NDB4V

0

NC

IO78PDB2V0

GND

M6

M7

V_CCIB4

IO47NDB2V0

IO47PDB2V0

GND

IO72NDB2V0

IO72PDB2V0

GND

GFB0/IO71NDB4V0 GFB0/IO106NDB4V

0

M8

M9

V_CCIB4

V_CC

V_CCIB4

V_CC

IO49PDB2V0

IO71PDB2V0

GFA1/IO70PDB4V0 GFA1/IO105PDB4V

0

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

N1

GND

V_CC

P2

GFA0/IO70NDB4V0 GFA0/IO105NDB4V

0

GND

V_CC

P3

P4

IO68NDB4V0

IO65PDB4V0

IO65NDB4V0

NC

IO101NDB4V0

IO96PDB4V0

IO96NDB4V0

IO99NDB4V0

IO97NDB4V0

V_CCIB4

GND

V_CCIB2

IO48NDB2V0

V_CCIB2

IO46NDB2V0

V_CCIB2

IO70NDB2V0

V_CCIB2

IO69NDB2V0

P5

P6

P7

NC

P8

V_CCIB4

V_CC

GCA0/IO45NDB2V0 GCA0/IO64NDB2V0

V_CCIB2 V_CCIB2

P9

V_CC

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

R1

GND

GCB0/IO44NDB2V0 GCB0/IO63NDB2V0

GCB1/IO44PDB2V0 GCB1/IO63PDB2V0

V_CC

GND

NC

GND

IO68PDB4V0

NC

IO103NDB4V0

GND

V_CC

N2

GND

N3

IO101PDB4V0

IO100NPB4V0

GND

V

_CCIB2

V_CCIB2

N4

IO56NDB2V0

NC

IO83NDB2V0

IO78NDB2V0

N5

GND

NC

N6

IO99PDB4V0

IO97PDB4V0

GND

GDA1/IO54PDB2V0 GDA1/IO81PDB2V0

GDB1/IO53PDB2V0 GDB1/IO80PDB2V0

N7

NC

N8

GND

V_CC

IO51NDB2V0

IO51PDB2V0

IO49NDB2V0

IO69PDB4V0

IO73NDB2V0

IO73PDB2V0

IO71NDB2V0

IO102PDB4V0

N9

GND

N10

N11

V_CC

GND

4-24

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

484-Pin FBGA

Pin Number AFS600 Function

AFS1500 Function

IO102NDB4V0

V_CCIB4

AFS1500 Function

IO77PPB2V0

IO74PDB2V0

V_CCIB2

R2

R3

IO69NDB4V0

_CCIB4

T16

T17

T18

T19

T20

T21

T22

U1

NC

V

R4

IO64PDB4V0

IO64NDB4V0

NC

IO91PDB4V0

IO91NDB4V0

IO92PDB4V0

GND

V_CCIB2

R5

IO55NDB2V0

IO82NDB2V0

R6

GDA2/IO55PDB2V0 GDA2/IO82PDB2V0

GND GND

GDC1/IO52PDB2V0 GDC1/IO79PDB2V0

R7

GND

R8

GND

R9

V_CC33A

GNDA

V_CC33A

GNDA

V_CC33A

GNDA

V_CC

V_CC33A

IO67PDB4V0

IO67NDB4V0

IO98PDB4V0

IO98NDB4V0

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

T1

GNDA

U2

V_CC33A

U3

GEC1/IO63PDB4V0 GEC1/IO90PDB4V0

GEC0/IO63NDB4V0 GEC0/IO90NDB4V0

GNDA

U4

V_CC33A

U5

GND

V_CCNVM

V_CCIB4

V_CC15A

GNDA

AC4

GND

V_CCNVM

V_CCIB4

V_CC15A

GNDA

AC4

GNDA

U6

V_CC

U7

GND

U8

NC

IO74NDB2V0

U9

GDA0/IO54NDB2V0 GDA0/IO81NDB2V0

GDB0/IO53NDB2V0 GDB0/IO80NDB2V0

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

V1

V_CC33A

GNDA

AG5

V_CC33A

GNDA

AG5

V_CCIB2

IO50NDB2V0

IO50PDB2V0

NC

V_CCIB2

IO75NDB2V0

IO75PDB2V0

IO100PPB4V0

GND

GNDA

PUB

GNDA

PUB

T2

GND

V_CCIB2

TDI

V_CCIB2

TDI

T3

IO66PDB4V0

IO66NDB4V0

V_CCIB4

NC

IO95PDB4V0

IO95NDB4V0

V_CCIB4

T4

GND

T5

IO57NDB2V0

IO84NDB2V0

T6

IO92NDB4V0

GNDNVM

GNDA

GDC2/IO57PDB2V0 GDC2/IO84PDB2V0

NC IO77NPB2V0

T7

GNDNVM

GNDA

NC

T8

GDC0/IO52NDB2V0 GDC0/IO79NDB2V0

GEB1/IO62PDB4V0 GEB1/IO89PDB4V0

GEB0/IO62NDB4V0 GEB0/IO89NDB4V0

T9

NC

T10

T11

T12

T13

T14

T15

AV4

V2

NC

V3

V_CCIB4

AV5

V4

GEA1/IO61PDB4V0 GEA1/IO88PDB4V0

GEA0/IO61NDB4V0 GEA0/IO88NDB4V0

AC5

V5

NC

V6

GND

GNDA

V7

V_CC33PMP

Preliminary v1.7

4-25

Package Pin Assignments

484-Pin FBGA

Pin Number AFS600 Function

484-Pin FBGA

AFS1500 Function

NC

Pin Number AFS600 Function

AFS1500 Function

V8

V9

NC

V_CC33A

AG4

W22

Y1

NC

IO76PPB2V0

V_CC33A

AG4

GEC2/IO60PDB4V0 GEC2/IO87PDB4V0

IO60NDB4V0 IO87NDB4V0

GEA2/IO58PDB4V0 GEA2/IO85PDB4V0

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

W1

Y2

AT4

Y3

ATRTN2

AT5

ATRTN2

AT5

Y4

IO58NDB4V0

NCAP

IO85NDB4V0

NCAP

Y5

V_CC33A

NC

V_CC33A

NC

Y6

AC0

Y7

V_CC33A

AC1

V_CC33A

AC1

V_CC33A

GND

TMS

V_CC33A

GND

Y8

Y9

AC2

TMS

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

V_CC33A

AC3

V_CC33A

AC3

V_JTAG

V_CCIB2

TRST

TDO

V_JTAG

V_CCIB2

TRST

AC6

V_CC33A

AC7

V_CC33A

AC7

TDO

NC

IO93PDB4V0

GND

AC8

W2

GND

NC

V_CC33A

AC9

V_CC33A

AC9

W3

IO93NDB4V0

W4

GEB2/IO59PDB4V0 GEB2/IO86PDB4V0

ADCGNDREF

PTBASE

GNDNVM

V_CCNVM

V_PUMP

ADCGNDREF

PTBASE

GNDNVM

V_CCNVM

V_PUMP

W5

IO59NDB4V0

AV0

IO86NDB4V0

AV0

W6

W7

GNDA

AV1

GNDA

AV1

W8

W9

AV2

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

GNDA

AV3

GNDA

AV3

AV6

GNDA

AV7

GNDA

AV7

AV8

GNDA

AV9

GNDA

AV9

V_CCIB2

NC

V_CCIB2

IO68PPB2V0

TCK

GND

4-26

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

676-Pin FBGA

A1 Ball Pad Corner

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7 6

5

4

3

2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

Preliminary v1.7

4-27

Package Pin Assignments

676-Pin FBGA

Pin Number AFS1500 Function

676-Pin FBGA

Pin Number AFS1500 Function

A1

A2

NC

GND

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

AV2

GNDA

AB21

AB22

AB23

AB24

AB25

AB26

AC1

PTBASE

GNDNVM

V_CCNVM

V_PUMP

NC

A3

NC

AV3

A4

NC

AV6

A5

GND

GNDA

A6

NC

AV7

GND

NC

A7

NC

AV8

A8

GND

GNDA

AC2

NC

A9

IO17NDB0V2

IO17PDB0V2

GND

AV9

AC3

NC

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

V_CCIB2

IO68PPB2V0

TCK

AC4

GND

V_CCIB4

PCAP

AG0

AC5

IO18NDB0V2

IO18PDB0V2

IO20NDB0V2

IO20PDB0V2

GND

AC6

GND

AC7

IO76PPB2V0

V_CCIB2

NC

AC8

AC9

GNDA

AG1

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

IO21PDB0V2

IO21NDB0V2

GND

AG2

AB2

NC

GNDA

AG3

AB3

GEC2/IO87PDB4V0

IO87NDB4V0

GEA2/IO85PDB4V0

IO85NDB4V0

NCAP

IO39NDB1V2

IO39PDB1V2

GND

AB4

AG6

AB5

GNDA

AG7

AB6

NC

AB7

AG8

NC

AB8

AC0

GNDA

AG9

GND

AB9

V_CC33A

AC1

NC

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

VAREF

V_CCIB2

PTEM

GND

NC

AC2

V_CCIB4

V_CC33A

AC3

IO93PDB4V0

GND

AC6

IO93NDB4V0

GEB2/IO86PDB4V0

IO86NDB4V0

AV0

V_CC33A

AC7

NC

AC8

NC

V_CC33A

AC9

AD2

NC

GNDA

AD3

GND

NC

AV1

ADCGNDREF

AD4

4-28

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

676-Pin FBGA

Pin Number AFS1500 Function

AD5

AD6

IO94NPB4V0

GND

VCC33N

AT0

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

GNDA

NC

AF25

AF26

B1

GND

NC

AD7

NC

GND

AD8

GNDA

NC

B2

GND

NC

AD9

ATRTN0

AT1

B3

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

NC

B4

NC

AT2

NC

B5

NC

ATRTN1

AT3

NC

B6

V_CCIB0

NC

B7

NC

AT6

NC

B8

NC

ATRTN3

AT7

GND

NC

B9

V_CCIB0

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

IO15NDB0V2

IO15PDB0V2

V_CCIB0

AT8

ATRTN4

AT9

AF2

GND

NC

AF3

IO19NDB0V2

IO19PDB0V2

V_CCIB1

V_CC33A

GND

IO76NPB2V0

NC

AF4

NC

AF5

NC

AF6

NC

IO25NDB1V0

IO25PDB1V0

V_CCIB1

AF7

NC

GND

NC

AF8

NC

AF9

V_CC33A

NC

IO33NDB1V1

IO33PDB1V1

V_CCIB1

NC

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

GND

NC

AE2

V_CC33A

NC

AE3

NC

AE4

NC

AE5

NC

V_CC33A

NC

GND

AE6

NC

GND

AE7

NC

AE8

NC

V_CC33A

NC

C2

NC

AE9

GNDA

NC

C3

GND

AE10

AE11

AE12

AE13

AE14

NC

C4

NC

C5

GAA1/IO01PDB0V0

GAB0/IO02NDB0V0

GAB1/IO02PDB0V0

IO07NDB0V1

GNDA

NC

C6

NC

C7

NC

C8

Preliminary v1.7

4-29

Package Pin Assignments

676-Pin FBGA

Pin Number AFS1500 Function

676-Pin FBGA

Pin Number AFS1500 Function

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

IO07PDB0V1

IO09PDB0V1

IO13NDB0V2

IO13PDB0V2

IO24PDB1V0

IO26PDB1V0

IO27NDB1V1

IO27PDB1V1

IO35NDB1V2

IO35PDB1V2

GBC0/IO40NDB1V2

GBA0/IO42NDB1V2

IO43NDB1V2

IO43PDB1V2

NC

D19

D20

D21

D22

D23

D24

D25

D26

E1

GBC1/IO40PDB1V2

GBA1/IO42PDB1V2

GND

F3

F4

IO121NDB4V0

GND

F5

IO123NDB4V0

GAC2/IO123PDB4V0

GAA2/IO125PDB4V0

GAC0/IO03NDB0V0

GAC1/IO03PDB0V0

IO10NDB0V1

IO10PDB0V1

IO14NDB0V2

IO23NDB1V0

IO23PDB1V0

IO32NPB1V1

IO34NDB1V1

IO34PDB1V1

IO37PDB1V2

GBB1/IO41PDB1V2

V_CCIB2

V_CCPLB

F6

GND

F7

NC

F8

NC

F9

NC

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

G1

GND

E2

IO122NPB4V0

IO121PDB4V0

IO122PPB4V0

IO00NDB0V0

IO00PDB0V0

V_CCIB0

E3

E4

E5

E6

E7

GND

E8

IO05NDB0V1

IO05PDB0V1

V_CCIB0

NC

E9

NC

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

NC

IO11NDB0V1

IO14PDB0V2

V_CCIB0

IO47PPB2V0

IO44NDB2V0

GND

D2

NC

D3

NC

D4

GND

V

_CCIB1

IO45NDB2V0

V_CCIB2

D5

GAA0/IO01NDB0V0

GND

IO29NDB1V1

IO29PDB1V1

V_CCIB1

D6

NC

D7

IO04NDB0V0

IO04PDB0V0

GND

NC

D8

IO37NDB1V2

GBB0/IO41NDB1V2

V_CCIB1

G2

IO119PPB4V0

IO120NDB4V0

IO120PDB4V0

V_CCIB4

D9

G3

D10

D11

D12

D13

D14

D15

D16

D17

D18

IO09NDB0V1

IO11PDB0V1

GND

G4

V_COMPLB

G5

GBA2/IO44PDB2V0

IO48PPB2V0

GBB2/IO45PDB2V0

NC

G6

GAB2/IO124PDB4V0

IO125NDB4V0

GND

IO24NDB1V0

IO26NDB1V0

GND

G7

G8

G9

V_CCIB0

IO31NDB1V1

IO31PDB1V1

GND

G10

G11

G12

IO08NDB0V1

IO08PDB0V1

GND

NC

F2

V_CCIB4

4-30

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

676-Pin FBGA

Pin Number AFS1500 Function

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

H1

IO22NDB1V0

IO22PDB1V0

GND

H23

H24

H25

H26

J1

IO50NDB2V0

IO51PDB2V0

NC

K7

K8

IO114PDB4V0

IO117NDB4V0

GND

K9

IO32PPB1V1

IO36NPB1V2

V_CCIB1

GND

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

L1

V_CC

NC

V_CCIB0

J2

V_CCIB4

GND

J3

IO115PDB4V0

GND

V_CCIB0

IO47NPB2V0

IO49PDB2V0

J4

V_CCIB1

GND

J5

IO116NDB4V0

IO116PDB4V0

V_CCIB4

V_CCIB2

J6

V_CCIB1

IO46NDB2V0

GBC2/IO46PDB2V0

IO48NPB2V0

NC

J7

GND

J8

IO117PDB4V0

V_CCIB4

J9

IO53NDB2V0

IO57PDB2V0

GCA2/IO59PDB2V0

V_CCIB2

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

K1

GND

IO06NDB0V1

IO06PDB0V1

IO16NDB0V2

IO16PDB0V2

IO28NDB1V1

IO28PDB1V1

GND

H2

NC

H3

IO118NDB4V0

IO118PDB4V0

IO119NPB4V0

IO124NDB4V0

GND

IO54NDB2V0

IO54PDB2V0

NC

H4

H5

H6

NC

H7

GND

H8

V_COMPLA

IO38PPB1V2

IO53PDB2V0

V_CCIB2

L2

NC

H9

V_CCPLA

L3

IO112PPB4V0

IO113NDB4V0

GFB2/IO109PDB4V0

GFA2/IO110PDB4V0

IO112NPB4V0

IO104PDB4V0

IO111PDB4V0

V_CCIB4

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

V_CCIB0

L4

IO12NDB0V1

IO12PDB0V1

V_CCIB0

IO52PDB2V0

IO52NDB2V0

GND

L5

L6

L7

V_CCIB1

IO51NDB2V0

V_CCIB2

L8

IO30NDB1V1

IO30PDB1V1

V_CCIB1

L9

NC

L10

L11

L12

L13

L14

L15

L16

NC

GND

IO36PPB1V2

IO38NPB1V2

GND

K2

NC

V_CC

K3

IO115NDB4V0

IO113PDB4V0

V_CCIB4

GND

K4

V_CC

IO49NDB2V0

IO50PDB2V0

K5

GND

K6

IO114NDB4V0

V_CC

Preliminary v1.7

4-31

Package Pin Assignments

676-Pin FBGA

Pin Number AFS1500 Function

676-Pin FBGA

Pin Number AFS1500 Function

L17

L18

V_CCIB2

GCB2/IO60PDB2V0

IO58NDB2V0

IO57NDB2V0

IO59NDB2V0

GCC2/IO61PDB2V0

IO55PPB2V0

IO56PDB2V0

IO55NPB2V0

GND

N1

N2

NC

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

R1

V_CC

GND

V_CC

L19

N3

IO108NDB4V0

V_CCOSC

L20

N4

GND

V_CC

L21

N5

V_CCIB4

L22

N6

XTAL2

GND

L23

N7

GFC1/IO107PDB4V0

V_CCIB4

V

_CCIB2

IO70NDB2V0

V_CCIB2

L24

N8

L25

N9

GFB1/IO106PDB4V0

L26

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

P1

V

_CCIB4

IO69NDB2V0

GCA0/IO64NDB2V0

V_CCIB2

M1

NC

GND

V_CC

M2

V_CCIB4

M3

GFC2/IO108PDB4V0

GND

GCB0/IO63NDB2V0

GCB1/IO63PDB2V0

IO66NDB2V0

IO67PDB2V0

NC

M4

V_CC

M5

IO109NDB4V0

IO110NDB4V0

GND

M6

V_CC

M7

V_CCIB2

M8

IO104NDB4V0

IO111NDB4V0

GND

IO70PDB2V0

V_CCIB2

R2

V_CCIB4

M9

R3

IO103NDB4V0

GND

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

IO69PDB2V0

GCA1/IO64PDB2V0

V_CCIB2

R4

V_CC

R5

IO101PDB4V0

IO100NPB4V0

GND

R6

V_CC

GCC0/IO62NDB2V0

GCC1/IO62PDB2V0

IO66PDB2V0

IO65NDB2V0

NC

R7

GND

R8

IO99PDB4V0

IO97PDB4V0

GND

V_CC

R9

GND

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

GND

IO60NDB2V0

IO58PDB2V0

GND

P2

NC

V_CC

P3

IO103PDB4V0

XTAL1

GND

P4

V_CC

IO68NPB2V0

IO61NDB2V0

GND

P5

V_CCIB4

GND

P6

GNDOSC

V_CC

P7

GFC0/IO107NDB4V0

V_CCIB4

GND

IO56NDB2V0

V_CCIB2

P8

GDB2/IO83PDB2V0

IO78PDB2V0

GND

P9

GFB0/IO106NDB4V0

V_CCIB4

IO65PDB2V0

P10

4-32

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

676-Pin FBGA

Pin Number AFS1500 Function

R21

R22

R23

R24

R25

R26

T1

IO72NDB2V0

IO72PDB2V0

GND

U5

U6

V_CCIB4

IO91PDB4V0

IO91NDB4V0

IO92PDB4V0

GND

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

W1

AC5

NC

U7

GNDA

IO71PDB2V0

U8

IO77PPB2V0

IO74PDB2V0

V_CCIB2

U9

IO67NDB2V0

GND

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

V1

GND

V_CC33A

IO82NDB2V0

GDA2/IO82PDB2V0

GND

T2

NC

GNDA

T3

GFA1/IO105PDB4V0

GFA0/IO105NDB4V0

IO101NDB4V0

IO96PDB4V0

IO96NDB4V0

IO99NDB4V0

IO97NDB4V0

V_CCIB4

V_CC33A

T4

GNDA

GDC1/IO79PDB2V0

V_CCIB2

T5

V_CC33A

T6

GNDA

NC

T7

V_CC

GND

T8

GND

W2

IO94PPB4V0

IO98PDB4V0

IO98NDB4V0

GEC1/IO90PDB4V0

GEC0/IO90NDB4V0

GND

T9

IO74NDB2V0

GDA0/IO81NDB2V0

GDB0/IO80NDB2V0

V_CCIB2

W3

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

U1

W4

V_CC

W5

GND

W6

V_CC

IO75NDB2V0

IO75PDB2V0

NC

W7

GND

W8

V_CCNVM

V_CC

W9

VCCIB4

GND

NC

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

V_CC15A

V_CCIB2

NC

GNDA

IO83NDB2V0

IO78NDB2V0

GDA1/IO81PDB2V0

GDB1/IO80PDB2V0

IO73NDB2V0

IO73PDB2V0

IO71NDB2V0

NC

V2

V_CCIB4

AC4

V3

IO100PPB4V0

GND

V_CC33A

V4

GNDA

V5

IO95PDB4V0

IO95NDB4V0

V_CCIB4

AG5

V6

GNDA

V7

PUB

V8

IO92NDB4V0

GNDNVM

GNDA

V_CCIB2

V9

TDI

GND

V10

V11

V12

V13

V14

GND

NC

IO84NDB2V0

GDC2/IO84PDB2V0

IO77NPB2V0

GDC0/IO79NDB2V0

U2

NC

AV4

U3

IO102PDB4V0

IO102NDB4V0

NC

U4

AV5

Preliminary v1.7

4-33

Package Pin Assignments

676-Pin FBGA

Pin Number AFS1500 Function

W25

W26

Y1

NC

GND

NC

Y2

NC

Y3

GEB1/IO89PDB4V0

GEB0/IO89NDB4V0

Y4

Y5

V_CCIB4

Y6

GEA1/IO88PDB4V0

Y7

GEA0/IO88NDB4V0

GND

Y8

Y9

V_CC33PMP

NC

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

V_CC33A

AG4

AT4

ATRTN2

AT5

V_CC33A

NC

V_CC33A

GND

TMS

V_JTAG

VCCIB2

TRST

TDO

NC

4-34

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Part Number and Revision Date

Part Number 51700092-016-0

Revised October 2008

List of Changes

The following table lists critical changes that were made in the current version of the chapter.

Previous Version Changes in Current Version (Preliminary v1.7)

Page

Advance v1.6

(August 2008)

The version number category was changed from Advance to Preliminary, which

N/A

means the datasheet contains information based on simulation and/or initial

characterization. The information is believed to be correct, but changes are

possible.

Advance v1.4

(July 2008)

The title of the datasheet changed from Actel Programmable System Chips to

Actel Fusion Mixed-Signal FPGAs. In addition, all instances of programmable

system chip were changed to mixed-signal FPGA.

Advance v1.1

(May 2008)

The "108-Pin QFN"figure was updated. D1 to D4 are new and the figure was

changed to bottom view. The note below the figure is new.

4-1

4-3

4-8

The "180-Pin QFN"figure was updated. D1 to D4 are new and the figure was

changed to bottom view. The note below the figure is new.

Advance v0.9

October 2007

This change table states that in the "208-Pin PQFP" table listed under the

Advance v0.8 changes, the AFS090 device had a pin change. That is incorrect. Pin

102 was updated for AFS250 and AFS600. The function name changed from

V_CC33ACAPto V_CC33A

.

Advance v0.8

(June 2007)

In the "108-Pin QFN" table, the function changed from V_CC33ACAPto V_CC33Afor

the following pin:

4-2

4-4

B25

In the "180-Pin QFN" table, the function changed from V_CC33ACAPto V_CC33Afor

the following pins:

AFS090: B29

AFS250: B29

In the "208-Pin PQFP" table, the function changed from V_CC33ACAPto V_CC33Afor

the following pins:

4-8

AFS090: 102

AFS250: 102

In the "256-Pin FBGA" table, the function changed from V_CC33ACAPto V_CC33Afor

the following pins:

4-12

AFS090: T14

AFS250: T14

AFS600: T14

AFS1500: T14

In the "484-Pin FBGA" table, the function changed from V_CC33ACAPto V_CC33Afor

the following pins:

4-20

4-28

AFS600: AB18

AFS1500: AB18

In the "676-Pin FBGA" table, the function changed from V_CC33ACAPto V_CC33Afor

the following pins:

AFS1500: AD20

Preliminary v1.7

4-35

Package Pin Assignments

Previous Version Changes in Current Version (Preliminary v1.7)

Page

Advance v0.7

(January 2007)

The VMV pins have now been tied internally with the V_CCIpins.

N/A

The AFS090"108-Pin QFN" table was updated.

4-2

4-8

The AFS090 and AFS250 devices were updated in the "108-Pin QFN" table.

The AFS250 device was updated in the "208-Pin PQFP" table.

The AFS600 device was updated in the "208-Pin PQFP" table.

Advance v0.7

(continued)

The AFS090, AFS250, AFS600, and AFS1500 devices were updated in the "256-Pin

FBGA" table.

4-12

The AFS600 and AFS1500 devices were updated in the "484-Pin FBGA" table.

The AFS600 device was updated in the "676-Pin FBGA" table.

4-20

4-28

4-8

Advance v0.5

(June 2006)

The heading was incorrect in the "208-Pin PQFP" table. It should be AFS250 and

not AFS090.

Advance v0.4

(April 2006)

The "256-Pin FBGA" table for the AFS1500 is new.

4-12

4-2

Advance v0.2

(April 2006)

The "108-Pin QFN" table for the AFS090 device is new.

The "180-Pin QFN" table for the AFS090 device is new.

The "208-Pin PQFP" table for the AFS090 device is new.

The "256-Pin FBGA" table for the AFS090 device is new.

The "256-Pin FBGA" table for the AFS250 device is new.

4-4

4-8

4-12

4-36

Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Datasheet Categories


型号：	M1AFS250-1PQG256I
厂家：	Actel Corporation
描述：	Actel Fusion Mixed-Signal FPGAs Actel的Fusion混合信号FPGA
文件：	总318页 (文件大小：10555K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M1AFS250-1PQG256I [ACTEL]

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