M1AGL1000V5-VQ144_技术文档

v1.3

®

IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

Advanced I/O

Features and Benefits

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

Low Power

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze

Mode

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

1

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X , and

1

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• I/O Registers on Input, Output, and Enable Paths

‡

• Hot-Swappable and Cold-Sparing I/Os

1

• Programmable Output Slew Rate and Drive Strength

High Capacity

• Weak Pull-Up/-Down

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

Clock Conditioning Circuit (CCC) and PLL¹

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Six CCC Blocks, One with an Integrated PLL

• Configurable

Phase

Shift, Multiply/Divide,

Delay

Capabilities, and External Feedback

• Retains Programmed Design When Powered Off

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

In-System Programming (ISP) and Security

Embedded Memory

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• 1 kbit of FlashROM User Nonvolatile Memory

1

®

Standard (AES) Decryption (except ARM -enabled IGLOO

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

1

devices) via JTAG (IEEE 1532–compliant)

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

1

®

H^•igh^Fla-P^she^Lr^of^co^krmance Routing Hierarchy

to Secure FPGA Contents

A^•RM^TruP^er^Do^uc^ae^l-s^Ps^oo^rtr^SS^RAu^Mpp^(eo^xr^ct^epi^tn^×I¹G⁸⁾LOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

• Segmented, Hierarchical Routing and Clock Structure

IGLOO Product Family

IGLOO Devices

AGL015

AGL030

AGL060 AGL125

AGL250

AGL400

AGL600

AGL1000

ARM-Enabled IGLOO Devices

System Gates

M1AGL250 M1AGL400 M1AGL600 M1AGL1000

15 k

128

384

5

30 k

256

768

5

60 k

512

1,536

10

125 k

1,024

3,072

16

250 k

2,048

6,144

24

400 k

–

600 k

–

1 M

–

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

9,216

32

13,824

36

24,576

53

–

18

36

54

108

24

144

32

–

4

8

12

FlashROM Bits

1 k

–

1 k

–

1 k

Yes

1

1 k

Yes

1

1 k

Yes

1

1 k

Yes

1

1 k

Yes

1

1 k

Yes

1

Secure (AES) ISP

2

Integrated PLL in CCCs

–

3

VersaNet Globals

6

18

I/O Banks

2

4

Maximum User I/Os

49

81

96

133

143

194

235

300

Package Pins

UC/CS

4

4,5

UC81/CS81

CS121

CS196

CS281

QFN

QN68

QN48, QN68, QN132

QN132

QN132 QN132

VQFP

FBGA

VQ100

FG144

VQ100

FG144

5

FG144

FG144,

FG256,

FG484

FG144,

FG256,

FG484

FG144,

FG256,

FG484

Notes:

1. AES is not available for ARM-enabled IGLOO devices.

2. AGL060 in CS121 does not support the PLL.

3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

4. The M1AGL250 device does not support this package.

5. Device/package support TBD

6. For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze

Technology handbook.

1 AGL015 and AGL030 devices do not support this feature.

‡ Supported only by AGL015 and AGL030 devices.

December 2008

I

IGLOO Low-Power Flash FPGAs

1

I/Os Per Package

IGLOO Devices

AGL015 AGL030 AGL060 AGL125

AGL250

AGL400

AGL600

AGL1000

ARM-Enabled

IGLOO Devices

M1AGL250 ³

I/O Type

M1AGL400 M1AGL600 M1AGL1000

Package

QN48

QN68

UC81

–

49

–

34

49

66

–

CS81

–

CS121

VQ100

QN132

CS196

FG144

FG256

CS281

FG484

Notes:

–

96

71

80

–

77

81

–

71

84

133

97

–

68

87 ⁷

143

97

–

13

19 ⁷

35

24

–

143

97

178

–

35

25

38

–

96 ⁷

97

177

215

235

25

43

53

60

97

177

215

300

25

44

53

74

–

194

38

1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO Low-Power Flash FPGAs

handbook to ensure compliance with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. The M1AGL250 device does not support QN132 or CS196 packages. Refer to the IGLOO Low-Power Flash FPGAs

handbook for position assignments of the 15 LVPECL pairs.

4. FG256 and FG484 are footprint-compatible packages.

5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of

single-ended user I/Os available is reduced by one.

6. "G" indicates RoHS-compliant packages. Refer to "IGLOO Ordering Information" on page III for the location of the

"G" in the part number.

7. Device/package support TBD.

IGLOO FPGAs Package Sizes Dimensions

Package

UC81 CS81 CS121 QN68 QN132 CS196

CS281

FG144

VQ100

FG256

FG484

Length

×

Width 4 × 4 5 × 5

6 × 6

8 × 8

10 × 10 13 × 13 14 × 14 17 × 17 23 × 23

(mm\mm)

Nominal Area

(mm²)

16

25

36

64

100

169

196

289

529

Pitch (mm)

0.4

0.5

0.4

0.5

1.0

0.5

1.0

Height (mm)

0.80

0.99

0.90

0.75

1.20

1.05

1.45

1.00

1.60

2.23

II

v1.3

IGLOO Low-Power Flash FPGAs

IGLOO Ordering Information

_

AGL1000

V2

FG

G

144

I

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (–40°C to +85°C Ambient Temperature)

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G= RoHS-Compliant Packaging

Package Type

=

UC

CS

QN

VQ

FG

Micro Chip Scale Package (0.4 mm pitch)

Chip Scale Package (0.4 mm and 0.5 mm pitches)

Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch)

Very Thin Quad Flat Pack (0.5 mm pitch)

Fine Pitch Ball Grid Array (1.0 mm pitch)

Speed Grade

F = 20% Slower than Standard*

Blank = Standard

Supply Voltage

2 = 1.2 V to 1.5 V

5 = 1.5 V only

Part Number

IGLOO Devices

AGL015 = 15,000 System Gates

AGL030 = 30,000 System Gates

AGL060 = 60,000 System Gates

AGL125 = 125,000 System Gates

AGL250 = 250,000 System Gates

AGL400 = 400,000 System Gates

AGL600 = 600,000 System Gates

AGL1000 = 1,000,000 System Gates

IGLOO Devices with Cortex-M1

M1AGL250= 250,000 System Gates

M1AGL400= 400,000 System Gates

M1AGL600= 600,000 System Gates

M1AGL1000= 1,000,000 System Gates

Notes:

1. Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.

2. The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only

supported in the commercial temperature range.

v1.3

III

IGLOO Low-Power Flash FPGAs

Temperature Grade Offerings

AGL015

AGL030

AGL060

AGL125

AGL250

AGL400

AGL600

AGL1000

Package

QN48

QN68

UC81

M1AGL250 ⁴M1AGL400 M1AGL600 M1AGL1000

–

C, I

–

C, I

–

C, I

–

CS81

–

CS121

VQ100

QN132

CS196

FG144

FG256

CS281

FG484

Notes:

–

C, I

C, I ³

–

C, I

–

C, I

–

C, I

–

3

–

C, I

–

C, I

–

C, I

–

C, I ³

C, I

–

C, I

1. C = Commercial temperature range: 0°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

3. Device/package support TBD.

4. The M1AGL250 device does not support FG256 or QN132 packages.

Speed Grade and Temperature Grade Matrix

Temperature Grade

–F ¹

Std.

✓

C ²

✓

3

I

–

✓

Notes:

1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in

the commercial temperature range.

2. C = Commercial temperature range: 0°C to 70°C ambient temperature.

3. I = Industrial temperature range: –40°C to 85°C ambient temperature.

References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with

M1 (Cortex-M1).

Contact your local Actel representative for device availability:

http://www.actel.com/contact/default.aspx.

AGL015 and AGL030

The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.

IV

v1.3

1 – IGLOO Device Family Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low-

power mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze

technology simplifies power management through I/O and clock management with rapid recovery

to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW)

while the IGLOO device is completely functional in the system. This allows the IGLOO device to

control system power management based on external inputs (e.g., scanning for keyboard stimulus)

while consuming minimal power.

Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power,

single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-

market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and

AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates,

supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption

and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction

set, has a configurable nested interrupt controller, and can be implemented with or without the

debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support

AES decryption.

Flash*Freeze Technology

The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit

ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off

I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction

in power consumption, thus achieving the lowest total system power.

When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices

the best fit for portable electronics.

v1.3

1-1

IGLOO Device Family Overview

Flash Advantages

Low Power

Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them

an ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

IGLOO devices also have low dynamic power consumption to further maximize power savings;

power is even further reduced by the use of a 1.2 V core voltage.

Low dynamic power consumption, combined with low static power consumption and Flash*Freeze

technology, gives the IGLOO device the lowest total system power offered by any FPGA.

Security

The nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a

unique combination of reprogrammability and design security without external overhead,

advantages that only an FPGA with nonvolatile flash programming can offer.

IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in IGLOO devices can

be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. AES was adopted by the National Institute of Standards and Technology

(NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES decryption

engine and a flash-based AES key that make them the most comprehensive programmable logic

device security solution available today. IGLOO devices with AES-based security allow for secure,

remote field updates over public networks such as the Internet, and ensure that valuable IP

remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a

programmed IGLOO device cannot be read back, although secure design verification is possible.

Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES

security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable

IP is protected and secure, making remote ISP possible. An IGLOO device provides the most

impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

IGLOO FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based IGLOO devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based IGLOO devices greatly simplifies total system design

and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In

addition, glitches and brownouts in system power will not corrupt the IGLOO device's flash

configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system

power is restored. This enables the reduction or complete removal of the configuration PROM,

expensive voltage monitor, brownout detection, and clock generator devices from the PCB design.

Flash-based IGLOO devices simplify total system design and reduce cost and design risk while

increasing system reliability and improving system initialization time.

IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost

instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike

SRAM-based FPGAs the device does not need to reload configuration and design state from

1-2

v1.3

IGLOO Low-Power Flash FPGAs

external memory components; instead it retains all necessary information to resume operation

immediately.

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property cannot be compromised or copied.

Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO family device

architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO

family a cost-effective ASIC replacement solution, especially for applications in the consumer,

networking/communications, computing, and avionics markets.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of IGLOO flash-

based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO FPGAs cannot

be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors

occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error

detection and correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic

utilization without compromising device routability or performance. Logic functions within the

device are interconnected through a four-level routing hierarchy.

IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all

modes of operation.

Advanced Architecture

The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The

IGLOO device consists of five distinct and programmable architectural features (Figure 1-1 on

page 1-4 and Figure 1-2 on page 1-4):

•

Flash*Freeze technology

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory^†

Extensive CCCs and PLLs^†

Advanced I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the IGLOO core tile as either a three-input lookup

table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric.

The VersaTile capability is unique to the Actel ProASIC^®family of third-generation-architecture

flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash

switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect

programming. Maximum core utilization is possible for virtually any design.

†

The AGL015 and AGL030 do not support PLL or SRAM.

v1.3

1-3

IGLOO Device Family Overview

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of IGLOO devices via an IEEE 1532 JTAG interface.

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block*

I/Os

VersaTile

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Bank 1

* Not supported by AGL015 and AGL030 devices

Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks (AGL015, AGL030, AGL060, and

AGL125)

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

(AGL600 and AGL1000)

Bank 2

Figure 1-2 • IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and

AGL1000)

1-4

v1.3

IGLOO Low-Power Flash FPGAs

Flash*Freeze Technology

The IGLOO device has an ultra-low power static mode, called Flash*Freeze mode, which retains all

SRAM and register information and can still quickly return to normal operation. Flash*Freeze

technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating

the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and

global I/Os can still be driven and can be toggling without impact on power consumption, clocks

can still be driven or can be toggling without impact on power consumption, and the device retains

all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode

or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No

power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as

5 µW in this mode.

Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the

power management of the device.

The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to

decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a

regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the

inherent low power static (as low as 12 µW) and dynamic capabilities of the IGLOO device. Refer to

Figure 1-3 for an illustration of entering/exiting Flash*Freeze mode.

Actel IGLOOe

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-3 • IGLOO Flash*Freeze Mode

VersaTiles

The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASIC^PLUS®core

tiles. The IGLOO VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-4 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

X1

Data

Y

Data

CLK

CLR

Y

X2

X3

LUT-3

Y

D-FF

CLK

D-FF

Enable

CLR

Figure 1-4 • VersaTile Configurations

v1.3

1-5

IGLOO Device Family Overview

User Nonvolatile FlashROM

Actel IGLOO devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM

can be used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard IGLOO IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks (except in the AGL015 and AGL030 devices),

as in security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel IGLOO development software solutions, Libero^®Integrated Design Environment (IDE)

and Designer, have extensive support for the FlashROM. One such feature is auto-generation of

sequential programming files for applications requiring a unique serial number in each part.

Another feature allows the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

IGLOO devices (except the AGL015 and AGL030 devices) have embedded SRAM blocks along their

north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory

configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have

independent read and write ports that can be configured with different bit widths on each port.

For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded

SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG

macro (except in the AGL015 and AGL030 devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

IGLOO devices provide designers with very flexible clock conditioning circuit (CCC) capabilities.

Each member of the IGLOO family contains six CCCs. One CCC (center west side) has a PLL. The

AGL015 and AGL030 do not have a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One

CCC (center west side) has a PLL.

1-6

v1.3

IGLOO Low-Power Flash FPGAs

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz up to 250 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz up to 250 MHz

2 programmable delay types for clock skew minimization

Clock frequency synthesis (for PLL only)

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration (for PLL only).

•

Output duty cycle = 50% 1.5% or better (for PLL only)

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used (for PLL only)

•

Maximum acquisition time is 300 µs (for PLL only)

Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL

only)

•

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

f_{OUT_CCC}(for PLL only)

Global Clocking

IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,

1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOO FPGAs support many different I/O standards—single-ended

and differential.

The I/Os are organized into banks, with two or four banks per device. The configuration of these

banks determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-Data-Rate applications

Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications

IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS

and M-LVDS can support up to 20 loads.

v1.3

1-7

IGLOO Device Family Overview

Part Number and Revision Date

Part Number 51700095-001-6

Revised December 2008

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version

Changes in Current Version (v1.3)

QN48 and QN68 were added to the AGL030 for the following tables:

"IGLOO Product Family"

Page

v1.2

(October 2008)

N/A

"IGLOO Ordering Information"

"Temperature Grade Offerings"

QN132 is fully supported by AGL125 so footnote 3 was removed.

v1.1

(July 2008)

This document was updated to include AGL400 device information. The following

sections were updated:

N/A

"IGLOO Product Family"

"IGLOO Ordering Information"

"Temperature Grade Offerings"

"IGLOO Product Family"

Figure 1-2 · IGLOO Device Architecture Overview with Four I/O Banks (AGL250,

AGL600, AGL400, and AGL1000)

v1.0

(March 2008)

As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core

voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to

1.5 V.

N/A

51700095-001-3 This document was divided into two sections and given a version number, starting

(March 2008)

at v1.0. The first section of the document includes features, benefits, ordering

information, and temperature and speed grade offerings. The second section is a

device family overview.

51700095-001-2 The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage"

(February 2008) to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 µW)" was removed

from "Low-Power Active FPGA Operation."

I

1.2_V was added to the list of core and I/O voltages in the "Advanced I/O" and

"I/Os with Advanced I/O Standards" sections.

I, 1-7

I

The "Embedded Memory" section was updated to remove the footnote reference

from the section heading and place it instead after "4,608-Bit" and "True Dual-Port

SRAM (except ×18)."

1-8

v1.3

IGLOO Low-Power Flash FPGAs

Previous Version

Changes in Current Version (v1.3)

Page

51700095-001-1 This document was updated to include AGL015 device information. QN68 is a new

N/A

(January 2008)

package that was added because it is offered in the AGL015. The following

sections were updated:

"Features and Benefits"

"IGLOO Ordering Information"

"Temperature Grade Offerings"

"IGLOO Product Family"

"IGLOO FPGAs Package Sizes Dimensions"

"AGL015 and AGL030" note

"IGLOO Device Family Overview"

The "Temperature Grade Offerings" table was updated to include M1AGL600.

IV

III

In the "IGLOO Ordering Information" table, the QN package measurements were

updated to include both 0.4 mm and 0.5 mm.

In the "General Description" section, the number of I/Os was updated from 288 to

300.

1-5

51700095-001-0 The "Low Power" section was updated to change the description of low-power I, 1-1, 1-5

(January 2008)

active FPGA operation to "from 12 µW" from "from 25 µW." The same update

was made in the "General Description" section and the "Flash*Freeze

Technology" section.

Advance v0.7

(November

2007)

This document was previously in datasheet Advance v0.7. As a result of moving to

the handbook format, Actel has restarted the version numbers. The new version

number is 51700095-001-0.

N/A

Advance v0.6

(November

2007)

Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the i, ii, iv

Temperature Grade Offerings table were updated to reflect the following: CS196

is now supported for AGL250; device/package support for QN132 is to be

determined for AGL250; the CS281 package was added for AGL600 and AGL1000.

Table 2 • IGLOO FPGAs Package Sizes Dimensions is new, and package sizes were

removed from the "I/Os Per Package1" table.

ii

The "I/Os Per Package1"table was updated to reflect 77 instead of 79 single-

ended I/Os for the VG100 package for AGL030.

ii

Advance v0.6

(November

2007)

A note was added to "IGLOO Ordering Information" regarding marking

information.

iii

Advance v0.5

(September

2007)

Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the "IGLOO i, ii, iii, iv

Ordering Information", and the Temperature Grade Offerings table were

updated to add the UC81 package.

Advance v0.4

(September

2007)

Table 1 • IGLOO Product Family was updated for AGL030 in the Package Pins

section to change CS181 to CS81.

i

Advance v0.3

(August 2007)

Cortex-M1 device information was added to Table 1 • IGLOO Product Family, the i, ii, iii, iv

"I/Os Per Package1" table, "IGLOO Ordering Information", and Temperature

Grade Offerings.

The number of single-ended I/Os for the CS81 package for AGL030 was updated

to 66 in the "I/Os Per Package1" table.

ii

Advance v0.2

(July 2007)

In Table 1 • IGLOO Product Family, the CS81 package was added for AGL030. The

CS196 was replaced by the CS121 for AGL060. Table note 3 was moved to the

specific packages to which it applies for AGL060: QN132 and FG144.

i

The CS81 and CS121 packages were added to the "I/Os Per Package1" table. The

number of single-ended I/Os was removed for the CS196 package in AGL060.

Table note 6 was moved to the specific packages to which it applies for AGL060:

QN132 and FG144.

ii

v1.3

1-9

IGLOO Device Family Overview

Previous Version

Changes in Current Version (v1.3)

Page

The CS81 and CS121 packages were added to the Temperature Grade Offerings

table. The temperature grade offerings were removed for the CS196 package in

AGL060. Table note 3 was moved to the specific packages to which it applies for

AGL060: QN132 and FG144.

iv

Advance v0.1

The words "ambient temperature" were added to the temperature range in the

"IGLOO Ordering Information", Temperature Grade Offerings, and "Speed Grade

and Temperature Grade Matrix" sections.

iii, iv

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

1-10

v1.3

2 – IGLOO DC and Switching Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

V_CC

Parameter

Limits

Units

DC core supply voltage

JTAG DC voltage

–0.3 to 1.65

V

V_JTAG

V_PUMP

V_CCPLL

–0.3 to 3.75

Programming voltage

Analog power supply (PLL)

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

V_CCIand VMV ³DC I/O buffer supply voltage

VI

I/O input voltage

–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (V_CCI+ 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

2

T_STG

Storage Temperature

Junction Temperature

–65 to +150

+125

°C

2

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention, maximum limits refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

3. VMV pins must be connected to the corresponding V_CCIpins. See Pin Descriptions for further information.

Advance v0.5

2-1

IGLOO DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ⁴

Symbol

Parameter

Commercial

0 to +70 ⁶

0 to + 85

Industrial

–40 to +85 ⁷

–40 to +100

Units

°C

T_A

T_J

Ambient Temperature

Junction Temperature ⁸

°C

3

V_CC

1.5 V DC core supply voltage¹

1.425 to 1.575 1.425 to 1.575

V

1.2 V–1.5 V wide range core

voltage ²

1.14 to 1.575

V

V_JTAG

JTAG DC voltage

1.4 to 3.6

3.15 to 3.45

0 to 3.45

1.4 to 3.6

3.15 to 3.45

0 to 3.45

V

V_PUMP

Programming voltage

Programming Mode

Operation ⁵

1.5 V DC core supply voltage¹

9

V_CCPLL

Analog power supply (PLL)

1.4 to 1.6

1.2 V–1.5 V wide range core 1.14 to 1.575

1.14 to 1.575

voltage²

V_CCIand 1.2 V DC core supply voltage²

1.14 to 1.26

V

VMV ¹⁰

1.5 V DC supply voltage

1.425 to 1.575 1.425 to 1.575

1.8 V DC supply voltage

2.5 V DC supply voltage

1.7 to 1.9

2.3 to 2.7

2.7 to 3.6

1.7 to 1.9

2.3 to 2.7

2.7 to 3.6

3.3 V wide range DC supply

voltage ¹¹

3.3 V DC supply voltage

LVDS differential I/O

3.0 to 3.6

V

2.375 to 2.625 2.375 to 2.625

3.0 to 3.6 3.0 to 3.6

LVPECL differential I/O

Notes:

1. For IGLOO^®V5 devices

2. For IGLOO V2 devices only, operating at V_CCI≥ V_CC

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-24 on page 2-23. V_CCIshould be at the same voltage within a given I/O

bank.

4. All parameters representing voltages are measured with respect to GND unless otherwise specified.

5. V_PUMPcan be left floating during operation (not programming mode).

6. Maximum T_J= 85 °C.

7. Maximum T_J= 100 °C.

8. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

9. V_CCPLLpins should be tied to V_CCpins. See Pin Descriptions for further information.

10. VMV pins must be connected to the corresponding V_CCIpins. See Pin Descriptions for further information.

11. 3.3 V wide range is compliant to the JDEC8a specification and supports 3.0 V V_CCIoperation.

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature¹

Program Retention

Maximum Storage

Maximum Operating Junction

Temperature T_J(°C) ²

Product Grade Programming Cycles (biased/unbiased) Temperature T_STG(°C) ²

Commercial

Industrial

Notes:

500

20 years

110

100

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

2-2

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-4 • Overshoot and Undershoot Limits ¹

Average V_CCI–GND Overshoot or

Undershoot Duration

Maximum Overshoot/

Undershoot²

V_CCI

as a Percentage of Clock Cycle²

2.7 V or less

10%

5%

1.4 V

1.49 V

1.1 V

3 V

10%

5%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every IGLOO device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In

addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

IGLOO I/Os are activated only if ALL of the following three conditions are met:

1. V_CCand V_CCIare above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. V_CCI> V_CC– 0.75 V (typical)

3. Chip is in the operating mode.

V_CCITrip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V

Ramping down (V5 Devices): 0.5 V < trip_point_down < 1.1 V

Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V

V_CCTrip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V

Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V

Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V

V_CCand V_CCIramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

•

During programming, I/Os become tristated and weakly pulled up to V_CCI.

JTAG supply, PLL power supplies, and charge pump V_PUMPsupply have no influence on I/O

behavior.

Advance v0.5

2-3

IGLOO DC and Switching Characteristics

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until V_CCand V_CCPLXexceed brownout

activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the V_CCbrownout levels (0.75 V

0.25 V for V5 devices, and 0.75 V 0.2 V for V2 devices), the PLL output lock signal goes low and/or

the output clock is lost. Refer to the Brownout Voltage section in the Power-Up/-Down Behavior of

Low-Power Flash Devices chapter of the ProASIC^®3 and ProASIC3E handbooks for information on

clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

To make sure the transition from input buffers to output buffers is clean, ensure that there is no

path longer than 100 ns from input buffer to output buffer in your design.

V_CC= V_CCI+ VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

V_CC

V_CC= 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, V_IH/V_IL, V_OH/V_OL, etc.

(except differential inputs)

but slower because V_CCIis

below specification. For the

same reason, input buffers do not

meet V_IH/V_ILlevels, and output

buffers do not meet V_OH/V_OLlevels.

V_CC= 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V_CCis below specification.

I/Os are functional (except differential inputs)

but slower because V_CCI/V_CCare below

specification. For the same reason, input

buffers do not meet V_IH/V_ILlevels, and

output buffers do not meet V_OH/V_OLlevels.

Activation trip point:

V_a= 0.85 V 0.25 V

Deactivation trip point:

Region 1: I/O buffers are OFF

V_d= 0.75 V 0.25 V

V_CCI

Activation trip point:

Min V_CCIdatasheet specification

V_a= 0.9 V 0.3 V

Deactivation trip point:

V_d= 0.8 V 0.3 V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

Figure 2-1 • V5 Devices – I/O State as a Function of V_CCIand V_CCVoltage Levels

2-4

Advance v0.5

IGLOO DC and Switching Characteristics

V

= V + VT

CCI

CC

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

V

CC

V

= 1.575 V

CC

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, V_IH/V_IL, V_OH/V_OL, etc.

but slower because V_CCIis

below specification. For the

same reason, input buffers do not

meet V_IH/V_ILlevels, and output

buffers do not meet V_OH/V_OLlevels.

V

= 1.14 V

CC

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the V_CCis below specification.

I/Os are functional (except differential inputs)

but slower because V_CCI/V_CCare below

specification. For the same reason, input

buffers do not meet V_IH/V_ILlevels, and

output buffers do not meet V_OH/V_OLlevels.

Activation trip point:

= 0.85 V 0.2 V

V

a

Deactivation trip point:

= 0.75 V 0.2 V

Region 1: I/O buffers are OFF

V

d

V

Activation trip point:

= 0.9 V 0.15 V

CCI

Min V datasheet specification

CCI

V

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

a

Deactivation trip point:

= 0.8 V 0.15 V

V

d

Figure 2-2 • V2 Devices – I/O State as a Function of V_CCIand V_CCVoltage Levels

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

T_J= Junction Temperature = ∆T + T_A

EQ 2-1

where:

T_A= Ambient Temperature

∆T = Temperature gradient between junction (silicon) and ambient ∆T = θ_ja* P

θ

_ja= Junction-to-ambient of the package. θ_janumbers are located in Table 2-5 on page 2-6.

P = Power dissipation

Advance v0.5

2-5

IGLOO DC and Switching Characteristics

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θ_jcand the junction-to-ambient air thermal

resistivity is θ_ja. The thermal characteristics for θ_jaare shown for two air flow rates. The absolute

maximum junction temperature is 110°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and

in still air.

Max. junction temp. (° C) – Max. ambient temp. (° C)

100° C – 70° C

Maximum Power Allowed = ---------------------------------------------------------------------------------------------------------------------------------------- = -------------------------------------- = 1. 463 W

θ_ja(° C/W)

20.5°C/W

EQ 2-2

Table 2-5 • Package Thermal Resistivities

θ_ja

Count

200 ft./

min.

500 ft./

min.

Package Type

Device

AGL015

θ_jc

TBD

0.4

Still Air

TBD

21.4

21.2

21.1

21.0

35.3

57.8

26.9

26.6

20.5

13.6

55.2

31.6

38.6

28.1

23.3

Units

C/W

Quad Flat No Lead

68

TBD

16.8

16.6

16.5

16.4

29.4

47.6

22.9

22.8

17.0

10.4

49.4

26.2

34.7

24.4

19.0

TBD

15.3

15.0

14.9

14.8

27.1

43.3

21.5

15.9

9.4

AGL030

132

100

196

144

256

484

896

144

256

484

AGL060

0.3

AGL125

0.2

AGL250

0.1

Very Thin Quad Flat Pack (VQFP)

Chip Scale Package (CSP)

All devices

See note*

AGL060

10.0

Fine Pitch Ball Grid Array (FBGA)

3.8

3.2

2.4

18.6

6.3

47.2

24.2

33.0

22.7

16.7

AGL1000

AGL250

12.0

6.6

AGL1000

8.0

* This information applies to all IGLOO devices except those listed below. Detailed device/package thermal

information for all IGLOO devices will be available in future revisions of the datasheet.

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T_J= 70°C,

V_CC= 1.425 V)

For IGLOO V2 or V5 devices, 1.5 V DC Core Supply Voltage

Junction Temperature (°C)

Array Voltage

V_CC(V)

1.425

1.5

–40°C

0.95

0.88

0.82

0°C

0.96

0.89

0.84

25°C

0.98

0.91

0.85

70°C

1.00

0.93

0.87

85°C

1.01

0.93

0.88

110°C

1.02

0.94

0.89

1.575

2-6

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T_J= 70°C,

V_CC= 1.14 V)

For IGLOO V2, 1.2 V DC Core Supply Voltage

Junction Temperature (°C)

Array Voltage

V_CC(V)

1.14

1.2

–40°C

0.97

0.86

0.79

0°C

0.98

0.87

0.80

25°C

0.99

0.89

0.81

70°C

1.00

0.89

0.82

85°C

1.01

0.90

0.83

110°C

1.01

0.91

0.83

1.26

Calculating Power Dissipation

Quiescent Supply Current

Quiescent supply current (I_DD) calculation depends on multiple factors, including operating

voltages (V_CC, V_CCI, and V_JTAG), operating temperature, system clock frequency, and power modes

usage. Actel recommends using the PowerCalculator and SmartPower software estimation tools to

evaluate the projected static and active power based on the user design, power mode usage,

operating voltage, and temperature.

Table 2-8 • Quiescent Supply Current (I_DD) Characteristics, IGLOO Flash*Freeze Mode*

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

Typical

(25°C)

1.2 V

1.5 V

4

6

8

13

18

20

34

27

51

30

72

44

µA

6

10

127

* I_DDincludes V_CC, V_PUMP, V_CCI, V_JTAG, and V_CCPLLcurrents. Values do not include I/O static contribution (P_DC6and

P_DC7).

Table 2-9 • Quiescent Supply Current (I_DD) Characteristics, IGLOO Sleep Mode (V_CC= 0 V)*

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

V_CCI/V_JTAG= 1.2 V (per 1.2 V

bank) Typical (25°C)

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

µA

V_CCI/V_JTAG= 1.5 V (per 1.2 V /

bank) Typical (25°C)

1.5 V

V_CCI/ V_JTAG= 1.8 V 1.2 V /

(per

bank)

Typical 1.5 V

(25°C)

V_CCI/ V_JTAG= 2.5 V 1.2 V /

2.2

2.5

2.2

2.5

2.2

2.5

2.2

2.5

2.2

2.5

2.2

2.5

2.2

2.5

2.2

2.5

µA

(per

bank)

Typical 1.5 V

(25°C)

V_CCI/ V_JTAG= 3.3 V 1.2 V /

(per

bank)

Typical 1.5 V

(25°C)

* I_DDincludes V_CC, V_PUMP, and V_CCPLLcurrents. Values do not include I/O static contribution (P_DC6and P_DC7).

Table 2-10 • Quiescent Supply Current (I_DD) Characteristics, IGLOO Shutdown Mode (V_CC, V_CCI= 0 V)*

Core Voltage

AGL015

AGL030

Units

Typical (25°C)

1.2 V / 1.5 V

0

µA

* I_DDincludes V_CC, V_PUMP, V_CCI, V_JTAG, and V_CCPLLcurrents. Values do not include I/O static contribution (P_DC6

and P_DC7).

Advance v0.5

2-7

IGLOO DC and Switching Characteristics

Table 2-11 • Quiescent Supply Current (I_DD), No IGLOO Flash*Freeze Mode¹

Core

Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units

I_CCACurrent²

Typical (25°C)

1.2 V

1.5 V

5

6

10

20

13

28

18

44

25

66

28

82

42

µA

14

16

137

I

_CCIor I_JTAGCurrent^{3, 4}

V_CCI/V_JTAG1.2

(per bank) Typical

(25°C)

=

V

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

V_CCI/ V_JTAG= 1.5 V 1.2 V /

(per bank) Typical 1.5 V

(25°C)

V_CCI/V_JTAG= 1.8 V 1.2 V /

(per bank) Typical 1.5 V

(25°C)

V_CCI/V_JTAG= 2.5 V 1.2 V /

(per bank) Typical 1.5 V

(25°C)

V_CCI/V_JTAG= 3.3 V 1.2 V /

(per bank) Typical 1.5 V

(25°C)

Notes:

1. To calculate total device I_DD, multiply the number of banks used by I_CCIand add I_CCAcontribution.

2. Includes V_CC, V_PUMPand V_CCPLLcurrents.

3. Per V_CCIor V_JTAGbank

4. Values do not include I/O static contribution (P_DC6and P_DC7).

2-8

Advance v0.5

IGLOO DC and Switching Characteristics

Power per I/O Pin

Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Advanced I/O Banks

Static Power

P_DC6(mW)¹

Dynamic Power

V_CCI(V)

P_AC9(µW/MHz)²

Single-Ended

3.3 V LVTTL /

3.3

–

16.27

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS³

3.3 V PCI

2.5

1.8

1.5

1.2

3.3

–

4.65

1.61

0.96

0.58

17.67

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

0.89

1.63

LVPECL

Notes:

1. P_DC6is the static power (where applicable) measured on V_CCI

.

2. P_AC9is the total dynamic power measured on V_CCI

3. Applicable for IGLOO V2 devices only

.

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

Static Power

P_DC6(mW)¹

Dynamic Power

V_CCI(V)

P_AC9(µW/MHz)²

Single-Ended

3.3 V LVTTL /

3.3

–

16.41

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS³

3.3 V PCI

2.5

1.8

1.5

1.2

3.3

–

4.75

1.66

1.00

0.61

17.78

3.3 V PCI-X

Notes:

1. P_DC6is the static power (where applicable) measured on V_CCI

.

2. P_AC9is the total dynamic power measured on V_CCI

3. Applicable for IGLOO V2 devices only.

.

Advance v0.5

2-9

IGLOO DC and Switching Characteristics

Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to Standard I/O Banks

Static Power

P_DC6(mW)¹

Dynamic Power

P

_AC9(µW/MHz)²

V_CCI(V)

Single-Ended

3.3 V LVTTL /

3.3

–

17.24

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS³

Notes:

2.5

1.8

1.5

1.2

–

5.64

2.63

1.97

0.57

1. P_DC6is the static power (where applicable) measured on V_CCI

.

2. P_AC9is the total dynamic power measured on V_CCI

3. Applicable for IGLOO V2 devices only.

.

Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Advanced I/O Banks

Static Power

P_DC7(mW)²

Dynamic Power

P_AC10(µW/MHz)³

C_LOAD(pF)

V_CCI(V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁴

3.3 V PCI

5

3.3

2.5

1.8

1.5

1.2

3.3

–

136.95

76.84

49.31

33.36

16.24

194.05

5

10

–

3.3 V PCI-X

Differential

LVDS

–

2.5

3.3

7.74

78.72

LVPECL

19.54

143.99

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. P_DC7is the static power (where applicable) measured on V_CCI

.

3. P_AC10is the total dynamic power measured on V_CCI

.

4. Applicable for IGLOO V2 devices only.

2-10

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Standard Plus I/O Banks

Static Power

P_DC7(mW)²

Dynamic Power

P_AC10(µW/MHz)³

C_LOAD(pF)

V_CCI(V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁴

3.3 V PCI

5

3.3

2.5

1.8

1.5

1.2

3.3

–

122.16

68.37

34.53

23.66

14.90

181.06

5

10

3.3 V PCI-X

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. P_DC7is the static power (where applicable) measured on V_CCI

.

3. P_AC10is the total dynamic power measured on V_CCI

.

4. Applicable for IGLOO V2 devices only.

Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to Standard I/O Banks

Static Power

P_DC7(mW)²

Dynamic Power

C_LOAD(pF)

V_CCI(V)

P_AC10(µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

5

3.3

2.5

1.8

1.5

1.2

–

104.38

59.86

31.26

21.96

13.49

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁴

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. P_DC7is the static power (where applicable) measured on V_CCI

.

3. P_AC10is the total dynamic power measured on V_CCI

.

4. Applicable for IGLOO V2 devices only.

Advance v0.5

2-11

IGLOO DC and Switching Characteristics

Power Consumption of Various Internal Resources

Table 2-18 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices

For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Device Specific Dynamic Power

(µW/MHz)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

P_AC1

Clock contribution of a

Global Rib

14.48

12.77

11.03

9.3

P_AC2

P_AC3

P_AC4

Clock contribution of a

Global Spine

2.48

1.85

1.58

0.81

0.41

Clock contribution of a

VersaTile row

0.81

Clock contribution of a

VersaTile used as a

sequential module

0.11

0.057

0.207

0.17

0.7

P_AC5

P_AC6

P_AC7

First contribution of a

VersaTile used as a

sequential module

Second contribution of

a VersaTile used as a

sequential module

Contribution of a

VersaTile used as a

combinatorial module

P_AC8

P_AC9

Average contribution

of a routing net

Contribution of an I/O

input pin (standard-

dependent)

See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.

P_AC10

P_AC11

P_AC12

P_AC13

Contribution of an I/O

output pin (standard-

dependent)

See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.

Average contribution

of a RAM block during

a read operation

25.00

30.00

2.70

Average contribution

of a RAM block during

a write operation

Dynamic PLL

contribution

* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Actel Libero^®Integrated Design Environment (IDE).

2-12

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-19 • Different Components Contributing to the Static Power Consumption in IGLOO Devices

For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Device-Specific Static Power (mW)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

P_DC1

Array static power in

Active mode

See Table 2-11 on page 2-8.

P_DC2

P_DC3

Array static power in

Static (Idle) mode

See Table 2-10 on page 2-7.

See Table 2-8 on page 2-7.

Array static power in

Flash*Freeze mode

P_DC4

P_DC5

Static PLL contribution

1.84

Bank quiescent power

(V_CCI-dependent)

See Table 2-11 on page 2-8.

P_DC6

I/O input pin static

power (standard-

dependent)

See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.

See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.

P_DC7

I/O output pin static

power (standard-

dependent)

* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Actel Libero^®Integrated Design Environment (IDE).

Advance v0.5

2-13

IGLOO DC and Switching Characteristics

Table 2-20 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices

For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage

Device Specific Dynamic Power

(µW/MHz)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

P_AC1

Clock contribution of a

Global Rib

9.28

8.19

7.07

5.96

P_AC2

P_AC3

P_AC4

Clock contribution of a

Global Spine

1.59

1.19

1.01

0.52

0.26

Clock contribution of a

VersaTile row

0.52

Clock contribution of a

VersaTile used as a

sequential module

0.07

0.045

0.186

0.11

P_AC5

P_AC6

P_AC7

First contribution of a

VersaTile used as a

sequential module

Second contribution of

a VersaTile used as a

sequential module

Contribution of a

VersaTile used as a

combinatorial module

P_AC8

P_AC9

Average contribution

of a routing net

0.45

Contribution of an I/O

input pin (standard-

dependent)

See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.

P_AC10

P_AC11

P_AC12

P_AC13

Contribution of an I/O

output pin (standard-

dependent)

See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.

Average contribution

of a RAM block during

a read operation

25.00

30.00

2.10

Average contribution

of a RAM block during

a write operation

Dynamic PLL

contribution

* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Libero IDE.

2-14

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-21 • Different Components Contributing to the Static Power Consumption in IGLOO Device

For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage

Device Specific Static Power (mW)

Parameter

Definition

AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015

P_DC1

Array static power in

Active mode

See Table 2-11 on page 2-8.

P_DC2

P_DC3

Array static power in

Static (Idle) mode

See Table 2-10 on page 2-7.

See Table 2-8 on page 2-7.

Array static power in

Flash*Freeze mode

P_DC4

P_DC5

Static PLL contribution

0.90

Bank quiescent power

(V_CCI-Dependent)

See Table 2-11 on page 2-8.

P_DC6

I/O input pin static

power (standard-

dependent)

See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.

See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.

P_DC7

I/O output pin static

power (standard-

dependent)

* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet

calculator or SmartPower tool in Actel Libero^®Integrated Design Environment (IDE).

Advance v0.5

2-15

IGLOO DC and Switching Characteristics

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock

generated

•

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-22 on

page 2-18.

•

Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-23 on page 2-18.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-23 on page 2-18. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

P

STAT

P_STAT= (P_DC1or P_DC2or P_DC3) + N_BANKS* P_DC5+ N_INPUTS* P_DC6+ N_OUTPUTS* P_DC7

N_INPUTSis the number of I/O input buffers used in the design.

N

_OUTPUTSis the number of I/O output buffers used in the design.

_BANKSis the number of I/O banks powered in the design.

N

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (P_AC1+ N_SPINE* P_AC2+ N_ROW* P_AC3+ N_S-CELL* P_AC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided

in Table 2-22 on page 2-18.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in

Table 2-22 on page 2-18.

F_CLKis the global clock signal frequency.

N

_S-CELLis the number of VersaTiles used as sequential modules in the design.

_AC1, P_AC2, P_AC3, and P_AC4are device-dependent.

Sequential Cells Contribution—P

P

S-CELL

P_S-CELL= N_S-CELL* (P_AC5+ α₁/ 2 * P_AC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on

page 2-18.

F_CLKis the global clock signal frequency.

2-16

Advance v0.5

IGLOO DC and Switching Characteristics

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* α₁/ 2 * P_AC7* F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on

page 2-18.

F_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * α₁/ 2 * P_AC8* F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on

page 2-18.

F_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* α₂/ 2 * P_AC9* F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-22 on page 2-18.

F

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* α₂/ 2 * β₁* P_AC10* F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-22 on page 2-18.

β₁is the I/O buffer enable rate—guidelines are provided in Table 2-23 on page 2-18.

F

_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= P_AC11* N_BLOCKS* F_READ-CLOCK* β₂+ P_AC12* N_BLOCK* F_WRITE-CLOCK* β₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

β₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

F

β₃is the RAM enable rate for write operations—guidelines are provided in Table 2-23

on page 2-18.

PLL Contribution—P

PLL

P_PLL= P_DC4+ P_AC13*F_CLKOUT

F_CLKOUTis the output clock frequency.¹

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its

corresponding contribution (P_AC13* F_CLKOUTproduct) to the total PLL contribution.

Advance v0.5

2-17

IGLOO DC and Switching Characteristics

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-22 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

α₁

α₂

10%

Table 2-23 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

β₁

β₂

β₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

2-18

Advance v0.5

IGLOO DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

Combinational Cell

Y

LVPECL (Applicable to

Advanced I/O Banks Only)L

t

= 1.22 ns

t

= 1.20 ns

PD

t

= 1.72 ns

DP

I/O Module

(Non-Registered)

Combinational Cell

Y

Output drive strength = 12 mA

High slew rate

LVTTL

t

= 3.05 ns (Advanced I/O Banks)

DP

t

= 1.80 ns

PD

I/O Module

(Non-Registered)

Combinational Cell

Y

I/O Module

(Registered)

Output drive strength = 8 mA

LVTTL

t

= 1.20 ns

High slew rate

= 4.12 ns (Advanced I/O Banks)

PY

t

DP

LVPECL

(Applicable

to Advanced

I/O Banks only)

t

= 1.49 ns

PD

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

Output drive strength = 4 mA

High slew rate

LVCMOS 1.5 V

t

= 0.43 ns

ICLKQ

ISUD

t

= 4.42 ns (Advanced I/O Banks)

DP

t

= 0.86 ns

= 0.47 ns

PD

Input LVTTL

Clock

I/O Module

(Registered)

Register Cell

Combinational Cell

Y

t

= 0.87 ns (Advanced I/O Banks)

PY

D

Q

D

Q

D

t

Q

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

I/O Module

t

= 0.92 ns

PD

t

= 3.05 ns

(Non-Registered)

DP

(Advanced I/O Banks)

t

= 0.90 ns

= 0.82 ns

CLKQ

= 1.02 ns

= 0.52 ns

t

= 0.90 ns

= 0.82 ns

OCLKQ

CLKQ

LVDS,

BLVDS,

M-LVDS

SUD

t

OSUD

SUD

Input LVTTL

Clock

Input LVTTL

Clock

(Applicable for

Advanced I/O

Banks only)

t

= 1.35 ns

PY

t

= 0.87 ns

t

= 0.87 ns

PY

(Advanced I/O Banks)

Figure 2-3 • Timing Model

Operating Conditions: Std. Speed, Commercial Temperature Range (T_J= 70°C), Worst-Case

V_CC= 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices

Advance v0.5

2-19

IGLOO DC and Switching Characteristics

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t_PY= MAX(t_PY(R), t_PY(F))

t_DIN= MAX(t_DIN(R), t_DIN(F))

V_IH

V_trip

V_CC

V_IL

PAD

Y

50%

GND

t_PY

(R)

t_PY

(F)

V_CC

50%

DIN

GND

t_DOUT

(R)

t_DOUT

(F)

Figure 2-4 • Input Buffer Timing Model and Delays (example)

2-20

Advance v0.5

IGLOO DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(F)

V_CC

(R)

50%

D

0 V

V_CC

50%

DOUT

PAD

0 V

V_OH

V_trip

V_OL

t_DP

(R)

t_DP

(F)

Figure 2-5 • Output Buffer Model and Delays (example)

Advance v0.5

2-21

IGLOO DC and Switching Characteristics

t

EOUT

D

Q

CLK

t , t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

t

CLK

D

= MAX(t

(r), t

(f))

V

I/O Interface

EOUT

V

CC

D

E

CC

50%

t

EOUT (F)

t

EOUT (R)

V

CC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

V

HZ

CCI

90% V

CCI

V

trip

V

10% V

OL

CCI

V

CC

D

E

V

CC

50%

t

EOUT (F)

EOUT (R)

V

CC

50%

EOUT

PAD

50%

t

ZHS

t

V

ZLS

OH

V

trip

V

OL

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

2-22

Advance v0.5

IGLOO DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Advanced I/O Banks

1

V_IL

Strength Rate Min., V Max., V

V_IH

Min., V

V_OL

V_OH

Min., V

2.4

I_OLI_OH

Drive

Slew

I/O Standard

Max., V Max., V

mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High

–0.3

0.8

0.7

2

3.6

0.4

12

3.3 V LVCMOS

Wide Range

Any²

High

2

3.6

0.2

V_CCI– 0.2 0.1 0.1

2.5 V LVCMOS

1.8 V LVCMOS

12 mA High

1.7

2.7

1.9

0.7

1.7

12

–0.3 0.35 * V_CCI0.65 * V_CCI

0.45

V_CCI

–

0.45

1.5 V LVCMOS

1.2 V LVCMOS³

12 mA High

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI

–0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI

0.75 *

V_CCI

12

2

12

2

2 mA

High

0.75 *

V_CCI

3.3 V PCI

3.3 V PCI-X

Notes:

Per PCI specifications

Per PCI-X specifications

1. Currents are measured at 85°C junction temperature.

2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification.

3. Applicable to V2 Devices only.

Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard Plus I/O Banks

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

mA mA

Drive

Slew

I/O Standard

Strength Rate Min., V

Max, V

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3

0.8

0.7

2

3.6

12

3.3 V LVCMOS

Wide Range

Any²

High

–0.3

2

3.6

0.2

V_CCI– 0.2 0.1 0.1

2.5 V LVCMOS

1.8 V LVCMOS

12 mA High –0.3

1.7

2.7

1.9

0.7

1.7

12

8

12

8

8 mA

4 mA

2 mA

High –0.3 0.35 * V_CCI0.65 * V_CCI

0.45

V_CCI–

0.45

1.5 V LVCMOS

1.2 V LVCMOS³

High –0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI

High –0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI

0.75 *

V_CCI

4

2

4

2

0.75 *

V_CCI

3.3 V PCI

3.3 V PCI-X

Notes:

Per PCI specifications

Per PCI-X specifications

1. Currents are measured at 85°C junction temperature.

2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification.

3. Applicable to V2 Devices only.

Advance v0.5

2-23

IGLOO DC and Switching Characteristics

Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions—Software Default Settings

Applicable to Standard I/O Banks

1

V_IL

Max, V

V_IH

Min, V

V_OL

Max, V

0.4

V_OH

Min, V

2.4

I_OLI_OH

Drive

Slew

I/O Standard

Strength Rate Min, V

Max, V

mA mA

3.3 V LVTTL /

3.3 V LVCMOS

8 mA

Any²

High

–0.3

0.8

0.7

2

3.6

8

3.3 V LVCMOS

Wide Range

2

3.6

0.2

V_CCI– 0.2 0.1 0.1

2.5 V LVCMOS

1.8 V LVCMOS

8 mA

4 mA

High

1.7

2.7

1.9

0.7

1.7

8

4

8

4

–0.3 0.35 * V_CCI0.65 * V_CCI

0.45

V_CCI

–

0.45

1.5 V LVCMOS

1.2 V LVCMOS³

Notes:

2 mA

1 mA

High

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI

–0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI

0.75 *

V_CCI

2

1

2

1

0.75 *

V_CCI

1. Currents are measured at 85°C junction temperature.

2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a

specification.

3. Applicable to V2 Devices only.

Table 2-27 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

Commercial¹

Industrial²

I_IL

µA

10

I_IH

µA

10

I_IL

µA

15

I_IH

µA

15

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS³

3.3 V PCI

3.3 V PCI-X

Notes:

1. Commercial range (0°C < T_A< 70°C)

2. Industrial range (–40°C < T_A< 85°C)

3. Applicable to V2 Devices only.

2-24

Advance v0.5

IGLOO DC and Switching Characteristics

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-28 • Summary of AC Measuring Points

Standard

Measuring Trip Point (V_trip

)

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

3.3 V PCI

1.4 V

1.2 V

0.90 V

0.75 V

0.60 V

0.285 * V_CCI(RR)

0.615 * V_CCI(FF)

0.285 * V_CCI(RR)

0.615 * V_CCI(FF)

3.3 V PCI-X

Table 2-29 • I/O AC Parameter Definitions

Parameter

Parameter Definition

Data to Pad delay through the Output Buffer

Pad to Data delay through the Input Buffer

t_DP

t_PY

t_DOUT

t_EOUT

t_DIN

t_HZ

Data to Output Buffer delay through the I/O interface

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Enable to Pad delay through the Output Buffer—HIGH to Z

Enable to Pad delay through the Output Buffer—Z to HIGH

Enable to Pad delay through the Output Buffer—LOW to Z

Enable to Pad delay through the Output Buffer—Z to LOW

Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Advance v0.5

2-25

IGLOO DC and Switching Characteristics

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

3.3 V LVTTL /

12 mA High 5 pF

–

0.97 2.09 0.19 0.85 0.66 2.13 1.67 2.67 3.04 5.66 5.20 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 5 pF

1.8 V LVCMOS 12 mA High 5 pF

1.5 V LVCMOS 12 mA High 5 pF

–

0.97 2.09 0.19 1.07 0.66 2.13 1.82 2.73 2.93 5.66 5.35 ns

0.97 2.24 0.19 1.01 0.66 2.28 1.99 3.02 3.39 5.81 5.52 ns

0.97 2.50 0.19 1.17 0.66 2.55 2.26 3.20 3.48 6.08 5.79 ns

3.3 V PCI

Per PCI High 10pF 25 ²0.97 2.32 0.19 0.73 0.66 2.36 1.77 2.67 3.04 5.89 5.30 ns

spec

3.3 V PCI-X

Per PCI-X High 10pF 25 ²0.97 2.32 0.19 0.70 0.66 2.36 1.77 2.67 3.04 5.89 5.30 ns

spec

LVDS

24 mA High

–

0.97 1.67 0.19 1.31

0.97 1.67 0.19 1.16

–

ns

LVPECL

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-62 for connectivity. This resistor is not required during normal operation.

2-26

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

12 mA High 5 pF

–

0.97 1.75 0.19 0.85 0.66 1.78 1.39 2.36 2.79 5.31 4.92 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 5 pF

1.8 V LVCMOS 8 mA High 5 pF

1.5 V LVCMOS 4 mA High 5 pF

–

0.97 1.75 0.19 1.08 0.66 1.78 1.51 2.38 2.69 5.32 5.04 ns

0.97 1.97 0.19 1.01 0.66 2.01 1.76 2.46 2.66 5.54 5.29 ns

0.97 2.25 0.19 1.17 0.66 2.29 1.99 2.53 2.68 5.82 5.52 ns

3.3 V PCI

Per PCI High 10pF 25 ²0.97 1.96 0.19 0.73 0.66 2.00 1.50 2.36 2.79 5.53 5.03 ns

spec

3.3 V PCI-X

Per

PCI-X

spec

High 10pF 25 ²0.97 1.96 0.19 0.70 0.66 2.00 1.50 2.36 2.79 5.53 5.03 ns

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-62 for connectivity. This resistor is not required during normal operation.

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

3.3 V LVTTL /

8 mA High

5 pF

–

0.97 1.85 0.19 0.83 0.66 1.88 1.45 1.96 2.26 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

Notes:

8 mA High

4 mA High

2 mA High

5 pF

–

0.97 1.88 0.19 1.04 0.66 1.92 1.62 1.95 2.14 ns

0.97 2.18 0.19 0.98 0.66 2.22 1.93 1.96 2.06 ns

0.97 2.51 0.19 1.13 0.66 2.56 2.20 1.99 2.03 ns

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-62 for connectivity. This resistor is not required during normal operation.

Advance v0.5

2-27

IGLOO DC and Switching Characteristics

Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

3.3 V LVTTL /

12 mA High 5 pF

–

1.55 2.66 0.26 0.98 1.10 2.71 2.18 3.23 3.92 8.52 7.99 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 5 pF

1.8 V LVCMOS 12 mA High 5 pF

1.5 V LVCMOS 12 mA High 5 pF

–

1.55 2.63 0.26 1.20 1.10 2.68 2.30 3.28 3.77 8.48 8.10 ns

1.55 2.71 0.26 1.11 1.10 2.76 2.44 3.56 4.17 8.57 8.24 ns

1.55 2.95 0.26 1.27 1.10 3.00 2.70 3.74 4.21 8.81 8.51 ns

1.55 3.61 0.26 1.58 1.10 3.45 3.33 3.94 3.66 9.05 8.93 ns

1.2 V LVCMOS

3.3 V PCI

2 mA

High 5 p

Per PCI High 10pF 25²1.55 2.90 0.26 0.86 1.10 2.95 2.29 3.23 3.92 8.76 8.10 ns

spec

3.3 V PCI-X

Per PCI-X High 10pF 25²1.55 2.90 0.25 0.86 1.10 2.95 2.29 3.23 3.92 8.76 8.10 ns

spec

LVDS

24 mA High

–

1.55 2.19 0.25 1.52

1.55 2.24 0.25 1.37

–

ns

LVPECL

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-62 for connectivity. This resistor is not required during normal operation.

2-28

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

12 mA High 5 pF

–

1.55 2.30 0.26 0.97 1.10 2.34 1.87 2.91 3.62 8.15 7.67 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 5 pF

–

1.55 2.28 0.26 1.20 1.10 2.32 1.95 2.92 3.50 8.13 7.75 ns

1.55 2.42 0.26 1.11 1.10 2.47 2.16 2.98 3.38 8.28 7.97 ns

1.55 2.67 0.26 1.27 1.10 2.72 2.39 3.05 3.36 8.53 8.20 ns

1.55 3.23 0.26 1.58 1.10 3.09 2.76 3.30 3.49 8.69 8.36 ns

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

3.3 V PCI

8 mA High 5 pF

4 mA High 5 pF

2 mA High 5 pF

Per PCI High 10pF 25 ²1.55 2.52 0.26 0.85 1.10 2.57 1.98 2.91 3.62 8.37 7.78 ns

spec

3.3 V PCI-X

Per PCI-X High 10pF 25 ²1.55 2.52 0.25 0.85 1.10 2.57 1.98 2.91 3.62 8.37 7.78 ns

spec

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-62 for connectivity. This resistor is not required during normal operation.

Table 2-35 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard I/O Banks

3.3 V LVTTL /

8 mA High

5 pF

–

1.55 2.37 0.26 0.94 1.10 2.42 1.92 2.39 2.94 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

Notes:

8 mA High

4 mA High

2 mA High

1 mA High

5 pF

–

1.55 2.38 0.26 1.15 1.10 2.42 2.05 2.37 2.79 ns

1.55 2.60 0.26 1.08 1.10 2.64 2.33 2.37 2.61 ns

1.55 2.91 0.26 1.22 1.10 2.96 2.60 2.39 2.54 ns

1.55 3.60 0.26 1.52 1.10 3.45 3.04 2.52 2.50 ns

1. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on

page 2-62 for connectivity. This resistor is not required during normal operation.

Advance v0.5

2-29

IGLOO DC and Switching Characteristics

Detailed I/O DC Characteristics

Table 2-36 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min.

Max.

Units

pF

Input capacitance

V_IN= 0, f = 1.0 MHz

8

C_INCLK

Input capacitance on the clock pin

pF

Table 2-37 • I/O Output Buffer Maximum Resistances¹

Applicable to Advanced I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

(Ω)²

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

100

50

300

150

75

4 mA

6 mA

8 mA

50

12 mA

16 mA

24 mA

2 mA

25

17

50

11

33

2.5 V LVCMOS

100

50

300

150

75

4 mA

6 mA

8 mA

50

12 mA

16 mA

24 mA

2 mA

25

17

50

11

33

1.8 V LVCMOS

100

50

200

100

50

4 mA

6 mA

8 mA

50

12 mA

16 mA

2 mA

25

20

40

1.5 V LVCMOS

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

2 mA

33

37

1.2 V LVCMOS

3.3 V PCI/PCI-X

TBD

25

TBD

75

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

2-30

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-38 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard Plus I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

(Ω)²

100

50

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

300

150

75

4 mA

6 mA

8 mA

50

12 mA

16 mA

2 mA

25

75

2.5 V LVCMOS

100

50

200

100

50

4 mA

6 mA

8 mA

50

12 mA

2 mA

25

1.8 V LVCMOS

1.5 V LVCMOS

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

2 mA

200

100

TBD

25

224

112

TBD

75

4 mA

1.2 V LVCMOS

3.3 V PCI/PCI-X

2 mA

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

Advance v0.5

2-31

IGLOO DC and Switching Characteristics

Table 2-39 • I/O Output Buffer Maximum Resistances¹

Applicable to Standard I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

(Ω)²

(Ω)³

3.3 V LVTTL / 3.3 V LVCMOS

100

50

300

150

200

100

225

112

224

TBD

4 mA

6 mA

8 mA

50

2.5 V LVCMOS

2 mA

100

50

4 mA

6 mA

8 mA

50

1.8 V LVCMOS

2 mA

200

100

200

TBD

4 mA

1.5 V LVCMOS

1.2 V LVCMOS

Notes:

2 mA

1 mA

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on V_CCI, drive strength selection, temperature, and process. For board design considerations

and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at

http://www.actel.com/download/ibis/default.aspx.

2. R_{(PULL-DOWN-MAX)}= (V_OLspec) / I_OLspec

3. R_{(PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_OHspec

Table 2-40 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

(Ω)

V_CCI

Min.

10 k

11 k

18 k

19 k

TBD

Max.

45 k

55 k

70 k

90 k

TBD

Min.

Max.

45 k

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

Notes:

10 k

12 k

17 k

19 k

TBD

74 k

110 k

140 k

TBD

1. R_{(WEAK PULL-UP-MAX)}= (V_OLspec) / I_{(WEAK PULL-UP-MIN)}

2. R_{(WEAK PULL-UP-MAX)}= (V_CCImax– V_OHspec) / I_{(WEAK PULL-UP-MIN)}

2-32

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-41 • I/O Short Currents I_OSH/I_OSL

Applicable to Advanced I/O Banks

Drive Strength

I

_OSL(mA)*

I_OSH(mA)*

27

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

2 mA

25

27

51

54

51

54

103

132

268

16

109

127

181

18

2.5 V LVCMOS

16

18

32

37

32

37

65

74

83

87

169

9

124

11

1.8 V LVCMOS

17

22

35

44

45

51

91

74

91

74

1.5 V LVCMOS

13

16

25

33

32

39

66

55

66

55

1.2 V LVCMOS

3.3 V PCI/PCI-X

TBD

103

TBD

109

Per PCI/PCI-X

specification

* T_J= 100°C

Advance v0.5

2-33

IGLOO DC and Switching Characteristics

Table 2-42 • I/O Short Currents I_OSH/I_OSL

Applicable to Standard Plus I/O Banks

Drive Strength

2 mA

I

_OSL(mA)*

25

I_OSH(mA)*

27

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

25

27

6 mA

51

54

8 mA

51

54

12 mA

16 mA

2 mA

103

16

109

18

2.5 V LVCMOS

4 mA

16

18

6 mA

32

37

8 mA

32

37

12 mA

2 mA

65

74

1.8 V LVCMOS

1.5 V LVCMOS

9

11

4 mA

17

22

6 mA

35

44

8 mA

35

44

2 mA

13

16

4 mA

25

33

1.2 V LVCMOS

3.3 V PCI/PCI-X

2 mA

TBD

103

TBD

109

Per PCI/PCI-X

specification

* T_J= 100°C

Table 2-43 • I/O Short Currents I_OSH/I_OSL

Applicable to Standard I/O Banks

Drive Strength

I_OSL(mA)*

I_OSH(mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

1 mA

25

51

16

32

9

27

54

18

37

11

22

16

TBD

1.8 V LVCMOS

17

13

TBD

1.5 V LVCMOS

1.2 V LVCMOS

* T_J= 100°C

2-34

Advance v0.5

IGLOO DC and Switching Characteristics

The length of time an I/O can withstand I_OSH/I_OSLevents depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-44 • Duration of Short Circuit Event before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

110°C

6 months

3 months

Table 2-45 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Rise/Fall Time

(min.)

Input Rise/Fall Time

(max.)

Input Buffer

Reliability

LVTTL/LVCMOS

No requirement

10 ns *

20 years (110°C)

10 years (100°C)

LVDS/B-LVDS/M-LVDS/

LVPECL

* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the

board noise. Actel recommends signal integrity evaluation/characterization of the system to

ensure that there is no excessive noise coupling into input signals.

Advance v0.5

2-35

IGLOO DC and Switching Characteristics

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS

3.3 V software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a

specification.

Table 2-46 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

25

27

10 10

4 mA

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

103

132

268

109

127

181

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

2

25

27

10 10

4

6

51

54

8

51

54

12 12

16 16

103

109

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-36

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

V_IL

V_IH

V_OL

V_OHI_OLI_OH

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

25

51

27

54

10 10

4

6

8

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-49 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

Applicable to Advanced, Standard Plus, and Standard I/O Banks

3.3 V LVCMOS Wide

Range

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_IL

I_IH

Drive

Strength

Min., V

Max., V

Min., V

Max., V

Min., V mA mA µA²µA²

V_CCI– 0.2 0.1 0.1 10 10

All²

–0.3

0.8

2

3.6

0.2

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a

specification.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/t_ZH/t_ZHS

Test Point

5 pF

Enable Path

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-7 • AC Loading

Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C_LOAD(pF)

0

3.3

1.4

5

* Measuring point = V_trip.See Table 2-28 on page 2-25 for a complete table of trip points.

Advance v0.5

2-37

IGLOO DC and Switching Characteristics

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

0.97 4.46 0.19 0.85 0.66 4.55 3.88 2.24 2.19 8.08 7.41

ns

6 mA

0.97 3.74 0.19 0.85 0.66 3.81 3.36 2.49 2.63 7.34 6.89

0.97 3.23 0.19 0.85 0.66 3.29 2.97 2.66 2.91 6.82 6.50

0.97 3.08 0.19 0.85 0.66 3.13 2.88 2.70 2.99 6.66 6.41

0.97 3.00 0.19 0.85 0.66 3.05 2.90 2.74 3.27 6.58 6.43

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive Strength

4 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

Std.

0.97 2.73 0.19 0.85 0.66 2.78 2.21 2.25 2.31 6.31 5.74

0.97 2.31 0.19 0.85 0.66 2.36 1.84 2.50 2.76 5.89 5.37

0.97 2.09 0.19 0.85 0.66 2.13 1.67 2.67 3.04 5.66 5.20

0.97 2.05 0.19 0.85 0.66 2.09 1.63 2.70 3.12 5.62 5.16

0.97 2.07 0.19 0.85 0.66 2.11 1.59 2.75 3.41 5.64 5.12

ns

6 mA

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

0.97 3.94 0.19 0.85 0.66 4.01 3.45 1.98 2.02 7.54 6.98

ns

0.97 3.24 0.19 0.85 0.66 3.30 2.98 2.20 2.42 6.83 6.51

0.97 2.76 0.19 0.85 0.66 2.81 2.62 2.36 2.68 6.35 6.15

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-38

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus Banks

Drive Strength

4 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

Std.

0.97 2.32 0.19 0.85 0.66 2.36 1.89 1.98 2.13 5.89 5.42

0.97 1.94 0.19 0.85 0.66 1.98 1.56 2.20 2.53 5.51 5.09

0.97 1.75 0.19 0.85 0.66 1.78 1.39 2.36 2.79 5.31 4.92

ns

6 mA

8 mA

12 mA

16 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

3.80 0.19 0.83

3.15 0.19 0.83

3.87 3.40 1.74 1.78

3.20 2.93 1.96 2.17

4 mA

Std.

ns

6 mA

Std.

ns

8 mA

Std.

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2.19 0.19 0.83

1.85 0.19 0.83

2.23 1.79 1.74 1.87

1.88 1.45 1.96 2.26

4 mA

Std.

ns

6 mA

Std.

ns

8 mA

Std.

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Advance v0.5

2-39

IGLOO DC and Switching Characteristics

Applies to 1.2 V DC Core Voltage

Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

1.55 5.11 0.26 0.98 1.10 5.21 4.47 2.80 3.01 11.01 10.28

ns

6 mA

1.55 4.37 0.26 0.98 1.10 4.45 3.93 3.05 3.46 10.26 9.74

1.55 3.84 0.26 0.98 1.10 3.91 3.53 3.23 3.75 9.72 9.34

1.55 3.68 0.26 0.98 1.10 3.75 3.44 3.27 3.83 9.56 9.25

1.55 3.60 0.26 0.98 1.10 3.67 3.46 3.31 4.12 9.48 9.27

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

1.55 3.32 0.26 0.98 1.10 3.38 2.75 2.80 3.16 9.19 8.56

ns

6 mA

1.55 2.90 0.26 0.98 1.10 2.95 2.37 3.06 3.62 8.76 8.18

1.55 2.66 0.26 0.98 1.10 2.71 2.18 3.23 3.92 8.52 7.99

1.55 2.62 0.26 0.98 1.10 2.67 2.15 3.27 3.99 8.48 7.95

1.55 2.64 0.26 0.98 1.10 2.69 2.10 3.32 4.29 8.50 7.91

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

1.55 4.55 0.26 0.97 1.10 4.64 3.98 2.52 2.81 10.44 9.79

ns

1.55 3.83 0.26 0.97 1.10 3.90 3.50 2.75 3.22 9.71 9.31

1.55 3.34 0.26 0.97 1.10 3.40 3.13 2.92 3.49 9.21 8.94

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2-40

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

1.55 2.88 0.26 0.97 1.10 2.93 2.38 2.52 2.94 8.74 8.19

ns

6 mA

1.55 2.49 0.26 0.97 1.10 2.54 2.04 2.75 3.36 8.35 7.85

1.55 2.30 0.26 0.97 1.10 2.34 1.87 2.91 3.62 8.15 7.67

8 mA

12 mA

16 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

4.38 0.26 0.94

3.71 0.26 0.94

4.46 3.91 2.16 2.43

3.78 3.43 2.39 2.83

4 mA

Std.

ns

6 mA

Std.

ns

8 mA

Std.

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-62 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2.73 0.26 0.94

2.37 0.26 0.94

2.78 2.26 2.16 2.54

2.42 1.92 2.39 2.94

4 mA

Std.

ns

6 mA

Std.

ns

8 mA

Std.

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Advance v0.5

2-41

IGLOO DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-63 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

2.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_IL

I_IH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

16

18

10 10

4 mA

6 mA

32

37

8 mA

32

37

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

65

74

83

87

169

124

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-64 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

2.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_IL

I_IH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

16

32

65

18

37

74

10 10

12 12

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-42

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-65 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

2.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_IL

I_IH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

16

32

18

37

10 10

4

6

8

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-8 • AC Loading

Table 2-66 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C_LOAD(pF)

0

2.5

1.2

5

* Measuring point = V_trip.See Table 2-28 on page 2-25 for a complete table of trip points.

Advance v0.5

2-43

IGLOO DC and Switching Characteristics

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-67 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

0.97 4.96 0.19 1.07 0.66 5.05 4.58 2.26 1.99 8.58 8.11

ns

6 mA

0.97 4.15 0.19 1.07 0.66 4.23 3.93 2.54 2.51 7.76 7.46

0.97 3.57 0.19 1.07 0.66 3.64 3.46 2.73 2.83 7.17 6.99

0.97 3.39 0.19 1.07 0.66 3.45 3.35 2.77 2.92 6.98 6.88

0.97 3.37 0.19 1.07 0.66 3.37 3.37 2.83 3.25 6.90 6.90

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-68 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

0.97 2.77 0.19 1.07 0.66 2.82 2.59 2.26 2.08 6.35 6.12

ns

6 mA

0.97 2.34 0.19 1.07 0.66 2.38 2.07 2.54 2.60 5.91 5.60

0.97 2.09 0.19 1.07 0.66 2.13 1.82 2.73 2.93 5.66 5.35

0.97 2.04 0.19 1.07 0.66 2.08 1.77 2.77 3.01 5.61 5.31

0.97 2.05 0.19 1.07 0.66 2.09 1.71 2.83 3.35 5.62 5.24

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-69 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

6 mA

8 mA

12 mA

Std.

0.97 4.42 0.19 1.08 0.66 4.50 4.09 1.96 1.85 8.03 7.62

ns

0.97 3.62 0.19 1.08 0.66 3.69 3.51 2.21 2.31 7.22 7.04

0.97 3.08 0.19 1.08 0.66 3.14 3.08 2.39 2.61 6.67 6.61

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-44

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-70 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus Banks

Drive Strength

4 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

Std.

0.97 2.36 0.19 1.08 0.66 2.40 2.21 1.96 1.92 5.93 5.74

0.97 1.97 0.19 1.08 0.66 2.00 1.74 2.21 2.39 5.53 5.27

0.97 1.75 0.19 1.08 0.66 1.78 1.51 2.38 2.69 5.32 5.04

ns

6 mA

8 mA

12 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-71 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

4.27 0.19 1.04

3.54 0.19 1.04

4.35 4.06 1.71 1.62

3.60 3.47 1.95 2.07

4 mA

Std.

ns

6 mA

Std.

ns

8 mA

Std.

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-72 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2.24 0.19 1.04

1.88 0.19 1.04

2.28 2.08 1.71 1.68

1.92 1.62 1.95 2.14

4 mA

Std.

ns

6 mA

Std.

ns

8 mA

Std.

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Advance v0.5

2-45

IGLOO DC and Switching Characteristics

Applies to 1.2 V Core Voltage

Table 2-73 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

1.55 5.58 0.26 1.20 1.10 5.68 5.14 2.80 2.78 11.49 10.95

ns

6 mA

1.55 4.75 0.26 1.20 1.10 4.84 4.47 3.09 3.31 10.65 10.28

1.55 4.15 0.26 1.20 1.10 4.23 3.99 3.28 3.65 10.04 9.80

1.55 3.97 0.26 1.20 1.10 4.04 3.88 3.33 3.74 9.85 9.69

1.55 3.90 0.26 1.20 1.10 3.96 3.90 3.38 4.07 9.77 9.71

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-74 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

1.55 3.32 0.26 1.20 1.10 3.38 3.09 2.80 2.89 9.19 8.90

ns

6 mA

1.55 2.88 0.26 1.20 1.10 2.93 2.56 3.09 3.43 8.74 8.37

1.55 2.63 0.26 1.20 1.10 2.68 2.30 3.28 3.77 8.48 8.10

1.55 2.58 0.26 1.20 1.10 2.63 2.25 3.33 3.86 8.44 8.06

1.55 2.59 0.26 1.20 1.10 2.64 2.19 3.39 4.21 8.45 8.00

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-75 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

6 mA

8 mA

12 mA

Std.

1.55 5.01 0.26 1.20 1.10 5.11 4.60 2.49 2.60 10.92 10.41

ns

1.55 4.20 0.26 1.20 1.10 4.28 4.00 2.74 3.08 10.08 9.81

1.55 3.64 0.26 1.20 1.10 3.71 3.56 2.92 3.39 9.52 9.36

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2-46

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-76 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

1.55 2.90 0.26 1.20 1.10 2.95 2.66 2.48 2.70 8.76 8.47

ns

1.55 2.50 0.26 1.20 1.10 2.54 2.18 2.74 3.19 8.35 7.99

1.55 2.28 0.26 1.20 1.10 2.32 1.95 2.92 3.50 8.13 7.75

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-77 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

4.84 0.26 1.15

4.08 0.26 1.15

4.93 4.56 2.12 2.22

4.16 3.96 2.37 2.69

4 mA

Std.

ns

6 mA

Std.

ns

8 mA

Std.

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-78 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2.75 0.26 1.15

2.38 0.26 1.15

2.80 2.53 2.12 2.31

2.42 2.05 2.37 2.79

4 mA

Std.

ns

6 mA

Std.

ns

8 mA

Std.

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Advance v0.5

2-47

IGLOO DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-79 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI

1.9

0.45

V_CCI– 0.45

2

4

2

4

9

11

22

44

51

74

10 10

–0.3 0.35 * V_CCI0.65 * V_CCI

17

35

45

91

6

8

V_CCI– 0.45 12 12

V_CCI– 0.45 16 16

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-80 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI

1.9

0.45

V_CCI– 0.45

2

4

2

4

9

11

22

44

10 10

–0.3 0.35 * V_CCI0.65 * V_CCI

17

35

6

8

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-48

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-81 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.8 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI

1.9

0.45 V_CCI– 0.45

2

4

2

4

9

11

22

10 10

17

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-9 • AC Loading

Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.8

0.9

5

* Measuring point = V_trip.See Table 2-28 on page 2-25 for a complete table of trip points.

Advance v0.5

2-49

IGLOO DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-83 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

0.97 6.38 0.19 1.01 0.66 6.49 5.92 2.33 1.56 10.03 9.45

0.97 5.35 0.19 1.01 0.66 5.45 5.04 2.67 2.38 8.98 8.57

0.97 4.62 0.19 1.01 0.66 4.70 4.43 2.90 2.78 8.23 7.96

0.97 4.37 0.19 1.01 0.66 4.45 4.30 2.95 2.89 7.98 7.83

0.97 4.31 0.19 1.01 0.66 4.37 4.31 3.03 3.29 7.90 7.84

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-84 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

Std.

0.97 3.24 0.19 1.01 0.66 3.20 3.24 2.33 1.61 6.73 6.78

ns

0.97 2.62 0.19 1.01 0.66 2.67 2.50 2.66 2.46 6.20 6.04

0.97 2.31 0.19 1.01 0.66 2.35 2.14 2.89 2.87 5.88 5.67

0.97 2.25 0.19 1.01 0.66 2.29 2.07 2.95 2.98 5.82 5.60

0.97 2.24 0.19 1.01 0.66 2.28 1.99 3.02 3.39 5.81 5.52

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-85 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Std.

0.97 5.78 0.19 1.01 0.66 5.89 5.31 1.95 1.46 9.42 8.84

0.97 4.75 0.19 1.01 0.66 4.84 4.53 2.25 2.21 8.37 8.06

0.97 4.07 0.19 1.01 0.66 4.14 3.97 2.46 2.57 7.67 7.50

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-50

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-86 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

0.97 2.75 0.19 1.01 0.66 2.79 2.75 1.94 1.51 6.32 6.28

ns

0.97 2.25 0.19 1.01 0.66 2.29 2.09 2.24 2.29 5.82 5.62

0.97 1.97 0.19 1.01 0.66 2.01 1.76 2.46 2.66 5.54 5.29

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-87 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

0.97

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

5.63 0.19 0.98 0.66

4.69 0.19 0.98 0.66

5.73

4.78

5.29 1.68 1.24

4.51 1.97 1.98

4 mA

Std.

0.97

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-88 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

0.97

t_DP

t_DIN

t_PY

t_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2.62 0.19 0.98

2.18 0.19 0.98

2.67 2.59 1.67 1.29

2.22 1.93 1.96 2.06

4 mA

Std.

0.97

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Advance v0.5

2-51

IGLOO DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-89 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

1.55 6.96 0.26 1.11 1.10 7.09 6.49 2.85 2.27 12.89 12.29

1.55 5.90 0.26 1.11 1.10 6.01 5.57 3.20 3.12 11.82 11.38

1.55 5.15 0.26 1.11 1.10 5.24 4.95 3.44 3.54 11.05 10.76

1.55 4.89 0.26 1.11 1.10 4.98 4.81 3.49 3.65 10.79 10.62

1.55 4.83 0.26 1.11 1.10 4.90 4.83 3.57 4.06 10.71 10.64

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-90 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.7 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

Std.

1.55 3.73 0.26 1.11 1.10 3.71 3.73 2.85 2.32 9.52 9.54

ns

1.55 3.11 0.26 1.11 1.10 3.16 2.97 3.19 3.21 8.97 8.78

1.55 2.78 0.26 1.11 1.10 2.84 2.60 3.43 3.63 8.64 8.40

1.55 2.72 0.26 1.11 1.10 2.77 2.52 3.49 3.74 8.58 8.33

1.55 2.71 0.26 1.11 1.10 2.76 2.44 3.56 4.17 8.57 8.24

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-91 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Std.

1.55 6.31 0.26 1.11 1.10 6.43 5.81 2.46 2.14 12.24 11.62

1.55 5.26 0.26 1.11 1.10 5.35 5.01 2.77 2.91 11.16 10.82

1.55 4.55 0.26 1.11 1.10 4.64 4.44 2.98 3.29 10.45 10.25

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2-52

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-92 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

Notes:

Std.

1.55 3.21 0.26 1.11 1.10 3.26 3.18 2.45 2.18 9.07 8.99

ns

1.55 2.71 0.26 1.11 1.10 2.76 2.50 2.76 2.99 8.56 8.31

1.55 2.42 0.26 1.11 1.10 2.47 2.16 2.98 3.38 8.28 7.97

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-93 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

1.55

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

6.13 0.26 1.08 1.10

5.16 0.26 1.08 1.10

6.24

5.26

5.79 2.07 1.77

4.99 2.37 2.53

4 mA

Std.

1.55

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-94 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.7 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

Std.

t_DOUT

1.55

t_DP

t_DIN

t_PY

t_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

3.05 0.26 1.08

2.60 0.26 1.08

3.11 3.01 2.07 1.81

2.64 2.33 2.37 2.61

4 mA

Std.

1.55

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Advance v0.5

2-53

IGLOO DC and Switching Characteristics

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-95 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

m

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V

A mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI

2

4

2

4

13

25

32

66

16

33

39

55

10 10

6

8

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI12 12

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-96 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

2 mA

4 mA

Notes:

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI

2

4

2

4

13

25

16

33

10 10

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-97 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.5 V

LVCMOS

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA¹Max., mA¹µA²µA²

13 16 10 10

2 mA

–0.3 0.35 * V_CCI0.65 * V_CCI1.575 0.25 * V_CCI0.75 * V_CCI

2

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

2-54

Advance v0.5

IGLOO DC and Switching Characteristics

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-10 • AC Loading

Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.5

0.75

5

* Measuring point = V_trip.See Table 2-28 on page 2-25 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-99 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

0.97 6.62 0.19 1.17 0.66 6.74 6.05 2.79 2.31 10.28 9.58

0.97 5.74 0.19 1.17 0.66 5.85 5.33 3.06 2.78 9.38 8.86

0.97 5.43 0.19 1.17 0.66 5.53 5.18 3.12 2.90 9.06 8.71

0.97 5.35 0.19 1.17 0.66 5.45 5.19 3.21 3.36 8.98 8.72

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-100 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

Std.

0.97 2.97 0.19 1.17 0.66 3.03 2.89 2.78 2.40 6.56 6.43

0.97 2.60 0.19 1.17 0.66 2.64 2.44 3.05 2.88 6.18 5.97

0.97 3.63 0.19 1.17 0.66 3.62 3.63 3.06 3.00 7.15 7.16

0.97 2.50 0.19 1.17 0.66 2.55 2.26 3.20 3.48 6.08 5.79

ns

4 mA

6 mA

8 mA

12 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Advance v0.5

2-55

IGLOO DC and Switching Characteristics

Table 2-101 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

Std.

0.97 5.93 0.19 1.17 0.66 6.04 5.46 2.30 2.15 9.57 8.99

ns

0.97 5.11 0.19 1.17 0.66 5.20 4.79 2.54 2.58 8.73 8.32

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-102 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Plus Banks

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

Std.

0.97 2.58 0.19 1.17 0.66 2.63 2.40 2.29 2.24 6.16 5.94

0.97 2.25 0.19 1.17 0.66 2.29 1.99 2.53 2.68 5.82 5.52

ns

4 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-103 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Banks

Drive Strength

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

Std.

0.97

5.88 0.19 1.13

0.66

5.99 5.45 1.99 1.93

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-104 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

Std.

0.97

2.51 0.19 1.13

0.66

2.56 2.20 1.99 2.03

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

1.2 V DC Core Voltage

2-56

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-105 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

1.55 7.16 0.26 1.27 1.10 7.29 6.60 3.32 3.01 13.10 12.41

1.55 6.26 0.26 1.27 1.10 6.37 5.86 3.59 3.49 12.18 11.67

1.55 5.93 0.26 1.27 1.10 6.04 5.70 3.65 3.62 11.85 11.51

1.55 5.85 0.26 1.27 1.10 5.96 5.72 3.75 4.10 11.77 11.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-106 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

1.55 3.43 0.26 1.27 1.10 3.49 3.36 3.31 3.10 9.30 9.16

ns

1.55 3.04 0.26 1.27 1.10 3.10 2.89 3.58 3.59 8.91 8.70

1.55 4.11 0.26 1.27 1.10 4.10 4.11 3.59 3.72 9.91 9.92

1.55 2.95 0.26 1.27 1.10 3.00 2.70 3.74 4.21 8.81 8.51

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-107 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

Std.

1.55 6.42 0.26 1.27 1.10 6.54 5.95 2.81 2.81 12.35 11.76

ns

1.55 5.58 0.26 1.27 1.10 5.68 5.27 3.06 3.25 11.49 11.08

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-108 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Plus Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZLt_ZHt_LZt_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

Notes:

Std.

1.55 3.01 0.26 1.27 1.10 3.07 2.81 2.80 2.90 8.88 8.62

ns

1.55 2.67 0.26 1.27 1.10 2.72 2.39 3.05 3.36 8.53 8.20

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Advance v0.5

2-57

IGLOO DC and Switching Characteristics

Table 2-109 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Banks

Drive Strength

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

2 mA

Std.

1.55

6.35 0.26 1.22

1.10

6.46 5.93 2.39 2.45

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-110 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.4 V

Applicable to Standard Banks

Drive Strength

2 mA

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

Std.

1.55

2.91 0.26 1.22

1.10

2.96 2.60 2.39 2.54

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2-58

Advance v0.5

IGLOO DC and Switching Characteristics

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose

1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer.

Table 2-111 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.2 V

LVCMOS

1

2

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA Max., mA µA µA

TBD TBD 10 10

2 mA

–0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI0.75 * V_CCI

2

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-112 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

1.2 V

LVCMOS

1

2

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA Max., mA µA µA

TBD TBD 10 10

2 mA

–0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI0.75 * V_CCI

2

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-113 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard I/O Banks

1.2 V

LVCMOS

1

2

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive

Strength Min., V Max., V

Min., V Max., V Max., V

Min., V mA mA Max., mA Max., mA µA µA

1 mA

–0.3 0.35 * V_CCI0.65 * V_CCI1.26 0.25 * V_CCI0.75 * V_CCI

1

TBD

10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 1 k

Test Point

Enable Path

Test Point

Datapath

5 pF

35 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-11 • AC Loading

Advance v0.5

2-59

IGLOO DC and Switching Characteristics

Table 2-114 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.2

0.6

5

* Measuring point = V_trip.See Table 2-28 on page 2-25 for a complete table of trip points.

Timing Characteristics

1.2 V DC Core Voltage

Table 2-115 • 1.2 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 1.4 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLS

t_ZHSUnits

ns

2 mA Std. 0.97 6.62 0.19 1.17 0.66 6.74 6.05 2.79 2.31 10.28 9.58

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-116 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.14 V

Applicable to Advanced I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

8.93 ns

2 mA

Std.

1.55 3.61 0.26 1.58 1.10 3.45 3.33 3.94 3.66 9.05

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-117 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.14 V

Applicable to Standard Plus I/O Banks

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLS

t_ZHSUnits

ns

2 mA Std. 1.55 7.60 0.26 1.58 1.10 7.27 6.52 3.31 3.36 12.86 12.12

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-118 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.14 V

Applicable to Standard Plus I/O Banks

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

ns

Std. 1.55 3.23 0.26 1.58 1.10 3.09 2.76 3.30 3.49 8.69 8.36

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-119 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.14 V

Applicable to Standard Banks

Drive Strength

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

1 mA

Std.

1.55

8.58 0.26 1.52

1.10

8.21 7.36 2.52 2.40

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2-60

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-120 • 1.2 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 1.14 V

Applicable to Standard Banks

Drive Strength

1 mA

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

Std.

1.55

3.60 0.26 1.52

1.10

3.45 3.04 2.52 2.50

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Advance v0.5

2-61

IGLOO DC and Switching Characteristics

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

Table 2-121 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced and Standard Plus I/Os

3.3 V PCI/PCI-X

V_IL

V_IH

V_OL

V_OH

I_OLI_OH

I_OSH

I_OSL

I_ILI_IH

Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA¹Max, mA¹µA²µA²

Per PCI

Per PCI curves

10 10

specification

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-12.

R to V_CCIfor t_DP(F)

R to GND for t_DP(R)

R to V_CCIfor t_LZ/t_ZL/t_ZLS

R to GND for t_HZ/t_ZH/t_ZHS

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/t_ZHS/t_ZL/t_ZLS

5 pF for t_HZ/t_LZ

Figure 2-12 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-122.

Table 2-122 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

0.285 * V_CCIfor t_DP(R)

0.615 * V_CCIfor t_DP(F)

C_LOAD(pF)

0

3.3

10

* Measuring point = V_trip.See Table 2-28 on page 2-25 for a complete table of trip points.

2-62

Advance v0.5

IGLOO DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-123 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

Std.

0.97

2.32 0.19 0.70

0.66

2.36 1.77 2.67 3.04 5.89 5.30

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-124 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

Std.

0.97

1.96 0.19 0.70

0.66

2.00 1.50 2.36 2.79 5.53 5.03

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

1.2 V DC Core Voltage

Table 2-125 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.90 0.25 0.86

1.10

2.95 2.29 3.23 3.92 8.76 8.10

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Table 2-126 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.52 0.25 0.85

1.10

2.57 1.98 2.91 3.62 8.37 7.78

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Advance v0.5

2-63

IGLOO DC and Switching Characteristics

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Actel Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-13. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, IGLOO also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

165 Ω

Z₀= 50 Ω

140 Ω

Z₀= 50 Ω

INBUF_LVDS

+

–

100 Ω

N

Figure 2-13 • LVDS Circuit Diagram and Board-Level Implementation

2-64

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-127 • Minimum and Maximum DC Input and Output Levels

DC Parameter

Description

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V

V_CCI

V_OL

V_OH

Supply Voltage

Output LOW Voltage

1.075

1.425

0.91

V

Output HIGH Voltage

1.25

0.65

0

V

4

I_OL

Output Lower Current

1.16

2.925

10

mA

V

4

I_OH

Output HIGH Current

V_I

Input Voltage

3

I_IH

Input HIGH Leakage Current

Input LOW Leakage Current

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

µA

mV

V

3

I_IL

10

V_ODIFF

V_OCM

V_ICM

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

V_IDIFF

Notes:

mV

1.

5%

2. Differential input voltage = 350 mV.

3. Currents are measured at 85°C junction temperature.

4. I_OL/I_OHis defined by V_ODIFF/(resistor network).

Table 2-128 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

1.075

1.325

Cross point

* Measuring point = V_trip.See Table 2-28 on page 2-25 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-129 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

ns

Std.

0.97

1.67

0.19

1.31

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7

on page 2-7 for derating values.

1.2 V DC Core Voltage

Table 2-130 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 2.3 V

Applicable to Standard Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

1.55

2.19

0.25

1.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7

on page 2-7 for derating values.

Advance v0.5

2-65

IGLOO DC and Switching Characteristics

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations

may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers

require series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus since the driver can be located anywhere on the bus. These

configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-14. The input and output

buffer delays are available in the LVDS section in Table 2-129 on page 2-65 and Table 2-130 on

page 2-65.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:

R_S= 60 Ω and R_T= 70 Ω, given Z₀= 50 Ω (2") and Z_stub= 50 Ω (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-14 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-15. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVDS implementation

because the output standard specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

P

OUTBUF_LVPECL

100 Ω

Z₀= 50 Ω

187 W

Z₀= 50 Ω

INBUF_LVPECL

+

–

100 Ω

N

Figure 2-15 • LVPECL Circuit Diagram and Board-Level Implementation

2-66

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-131 • Minimum and Maximum DC Input and Output Levels

DC Parameter

V_CCI

Description

Supply Voltage

Min. Max. Min. Max. Min. Max. Units

3.0

3.3

3.6

V

V_OL

Output LOW Voltage

0.96

1.8

0

1.27

2.11

3.3

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.9

V_OH

Output HIGH Voltage

V

V_IL, V_IH

V_ODIFF

V_OCM

Input LOW, Input HIGH Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

V

0.625 0.97 0.625 0.97 0.625 0.97

1.762 1.98 1.762 1.98 1.762 1.98

V

V_ICM

1.01

300

2.57

1.01

300

2.57

1.01

300

2.57

V

V_IDIFF

mV

Table 2-132 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

1.64

1.94

Cross point

* Measuring point = V_trip.See Table 2-28 on page 2-87 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-133 • LVPECL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

0.97

1.67

0.19

1.16

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

1.2 V DC Core Voltage

Table 2-134 • LVPECL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V, Worst-Case V_CCI= 3.0 V

Applicable to Standard Banks

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

1.55

2.24

0.25

1.37

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Advance v0.5

2-67

IGLOO DC and Switching Characteristics

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

L

D

DOUT

Data_out

PRE

DFN1E1P1

F

PRE

DFN1E1P1

Y

E

Core

Array

Data

Enable

CLK

D

Q

D

Q

C

G

E

EOUT

B

H

I

A

PRE

DFN1E1P1

J

D

Q

K

Data Input I/O Register with:

Active High Enable

E

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

CLKBUF

INBUF

Postive-Edge Triggered

Figure 2-16 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

2-68

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-135 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

t_OHD

F, H

t_OSUE

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

L, DOUT

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

I, EOUT

I, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

* See Figure 2-16 on page 2-68 for more information.

Advance v0.5

2-69

IGLOO DC and Switching Characteristics

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

CLR

LL

HH

AA

DD

JJ

D

Q

CLR

DFN1E1C1

KK

E

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-17 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

2-70

Advance v0.5

IGLOO DC and Switching Characteristics

Table 2-136 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

t_OHD

FF, HH

t_OSUE

GG, HH

LL, DOUT

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

JJ, HH

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

* See Figure 2-17 on page 2-70 for more information.

Advance v0.5

2-71

IGLOO DC and Switching Characteristics

Input Register

t_ICKMPWHt_ICKMPWL

50%

CLK

t_IHD

t_ISUD

50%

1

0

Data

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-18 • Input Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-137 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_ICLKQ

Description

Std. Units

Clock-to-Q of the Input Data Register

0.42

0.47

0.00

0.67

0.00

0.79

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

Enable Hold Time for the Input Data Register

t_IHE

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

2-72

Advance v0.5

IGLOO DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-138 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V

Description

Clock-to-Q of the Input Data Register

Parameter

t_ICLKQ

Std. Units

0.68

0.97

0.00

1.02

0.00

1.19

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

Output Register

t

OCKMPWH OCKMPWL

50%

CLK

t

OSUD OHD

50%

1

0

Data_out

t

OREMPRE

Enable

Preset

50%

t

ORECPRE

OWPRE

t

OHE

50%

t

OSUE

t

OREMCLR

t

ORECCLR

OWCLR

50%

Clear

t

OPRE2Q

50%

DOUT

t

OCLR2Q

t

OCLKQ

Figure 2-19 • Output Register Timing Diagram

Advance v0.5

2-73

IGLOO DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-139 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Description

Clock-to-Q of the Output Data Register

Parameter

t_OCLKQ

Std. Units

1.00

0.51

0.00

0.70

0.00

1.34

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

t_OCKMPWH

t_OCKMPWL

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width HIGH for the Output Data Register

Clock Minimum Pulse Width LOW for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

1.2 V DC Core Voltage

Table 2-140 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V

Parameter

t_OCLKQ

Description

Clock-to-Q of the Output Data Register

Std. Units

1.52

1.15

0.00

1.11

0.00

1.96

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

t_OCKMPWH

t_OCKMPWL

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width HIGH for the Output Data Register

Clock Minimum Pulse Width LOW for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating

values.

2-74

Advance v0.5

IGLOO DC and Switching Characteristics

Output Enable Register

t_OECKMPWHt_OECKMPWL

50%

CLK

t_OESUDt_OEHD

50%

0

1

D_Enable

50%

Enable

Preset

t_OEWPRE

50%

t_OEREMPRE

50%

t_OERECPRE

50%

t_{OESUE OEHE}

t

t_OEREMCLR

t_OEWCLRt_OERECCLR

50%

Clear

EOUT

t_OECLR2Q

t_OEPRE2Q

50%

t_OECLKQ

50%

Figure 2-20 • Output Enable Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-141 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.425 V

Parameter

t_OECLKQ

t_OESUD

Description

Std. Units

Clock-to-Q of the Output Enable Register

0.75

0.51

0.00

0.73

0.00

1.13

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

Data Setup Time for the Output Enable Register

t_OEHD

Data Hold Time for the Output Enable Register

t_OESUE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

t_OEHE

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLR

t_OERECCLR

t_OEREMPRE

t_OERECPRE

t_OEWCLR

t_OEWPRE

Asynchronous Clear Minimum Pulse Width for the Output Enable Register

Asynchronous Preset Minimum Pulse Width for the Output Enable Register

t_OECKMPWHClock Minimum Pulse Width HIGH for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width LOW for the Output Enable Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Advance v0.5

2-75

IGLOO DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-142 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case V_CC= 1.14 V

Description

Clock-to-Q of the Output Enable Register

Parameter

t_OECLKQ

t_OESUD

Std. Units

1.10

1.15

0.00

1.22

0.00

1.65