M7AFS1500-FGG256 [ACTEL]
Field Programmable Gate Array, 350MHz, 38400-Cell, CMOS, PBGA256;型号: | M7AFS1500-FGG256 |
厂家: | Actel Corporation |
描述: | Field Programmable Gate Array, 350MHz, 38400-Cell, CMOS, PBGA256 栅 |
文件: | 总248页 (文件大小:1809K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Advanced v0.7
®
Fusion Family of Mixed-Signal Flash FPGAs
®
with Optional Soft ARM Support
–
Frequency: Input (1.5–350 MHz), Output (0.75–350 MHz)
Features and Benefits
High Performance Reprogrammable
Flash Technology
Low Power Consumption
•
•
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low Power Modes
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program When Powered-Off
Live at Power-Up (LAPU) Single-Chip Solution
350 MHz System Performance
In-System Programming (ISP) and Security
•
•
Secure ISP with 128-Bit AES Via JTAG
®
FlashLock to Secure FPGA Contents
Advanced Digital I/O
Embedded Flash Memory
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /
1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V
Input
•
User Flash Memory – 2 Mbits to 8 Mbits
–
–
Configurable 8-, 16-, or 32-Bit Datapath
10 ns Access in Read-Ahead Mode
•
1 kbit of Additional FlashROM
Integrated A/D Converter (ADC) and Analog I/O
•
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
•
•
•
•
•
•
Up to 12 bit resolution and Up to 600 ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High Voltage Input Tolerance 12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
–
–
Built-In I/O Registers
700 Mbps DDR Operation
•
•
Hot-Swappable I/Os
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
•
Pin-Compatible Packages Across the Fusion Family
–
–
P- and N-Channel Power MOSFET support
Programmable 1, 3, 10, 30 µA and 25 mA Drive Strengths
SRAMs and FIFOs
•
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (x1, x2, x4, x9,
and x18 organizations available)
On-Chip Clocking Support
•
•
•
•
Internal 100 MHz RC Oscillator (accurate to 1%)
Crystal Oscillator Support (32 kHz to 20 MHz)
Programmable Real-Time Counter (RTC)
•
•
True Dual-Port SRAM (except x18)
Programmable Embedded FIFO Control Logic
Soft ARM7™ Core Support in M7 Fusion Devices
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs
•
CoreMP7Sd (with debug) and CoreMP7S (without debug)
–
Phase Shift, Multiply/Divide, and Delay Capabilities
Table 1 • Fusion Family
Fusion Devices
AFS090
AFS250
AFS600
AFS1500
ARM-Enabled Fusion Devices
System Gates
M7AFS600
M7AFS1500
90,000
2,304
250,000
6,144
600,000
13,824
7,500
5,237
Yes
1,500,000
38,400
32,000
29,878
Yes
Tiles (D-Flip-Flops)
Usable Tiles with CoreMP7S
1
General
Information
1
Usable Tiles with CoreMP7Sd
Secure (AES) ISP
PLLs
Yes
1
Yes
1
2
2
Globals
18
1
18
1
18
18
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
FlashROM Bits
2
4
2 M
1 k
6
2 M
1 k
8
4 M
1 k
8 M
1 k
Memory
RAM Blocks (4,608 bits)
RAM kbits
24
60
27
5
36
6
108
10
270
10
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
15
5
18
6
30
30
10
10
Analog and I/Os
4
4
5
5
2
Maximum Digital I/Os
75
20
114
24
172
40
252
40
Analog I/Os
Notes:
1. Refer to the CoreMP7 datasheet for more information.
2. Some debug tools require 10 digital I/Os for external connection.
October 2007
i
© 2007 Actel Corporation
See the Actel website for the latest version of the datasheet.
Fusion Family of Mixed-Signal Flash FPGAs
Bank 0
Bank 1
CCC
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
OSC
I/Os
CCC/PLL
VersaTile
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
ISP AES
Decryption
User Nonvolatile
Charge Pumps
FlashROM
Flash Memory Blocks
ADC
Flash Memory Blocks
Analog Analog Analog Analog Analog Analog Analog
Quad Quad Quad Quad Quad Quad Quad
Analog Analog
Quad Quad
Analog
Quad
CCC
Bank 3
Figure 1 • Fusion Device Architecture Overview (AFS600)
Package I/Os: Single/Double-Ended (Analog)
Fusion Devices
AFS090
AFS250
AFS600
AFS1500
ARM-Enabled Devices
M7AFS600
M7AFS1500
QN108
QN180
PQ208
FG256
FG484
FG676
37/9 (16)
60/16 (20)
65/15 (24)
93/26 (24)
114/37 (24)
95/46 (40)
119/58 (40)
172/86 (40)
75/22 (20)
119/58 (40)
223/109 (40)
252/126 (40)
Note: All devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600).
ii
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Product Ordering Codes
_
M7AFS600
1
FG
G
256
I
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚C)
I = Industrial (–40 to +85˚C)
PP = Pre-Production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Lead-Free Packaging Options
Blank = Standard Packaging
G = RoHS-Compliant (Green) Packaging
Package Type
=
=
=
QN
PQ
FG
Quad Flat No Lead (0.5 mm pitch)
Plastic Quad Flat Pack (0.5 mm pitch)
Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
Fusion Devices
AFS090 = 90,000 System Gates
AFS250 = 250,000 System Gates
AFS600 = 600,000 System Gates
AFS1500 = 1,500,000 System Gates
ARM-Enabled Fusion Devices
M7AFS600 = 600,000 System Gates
M7AFS1500 = 1,500,000 System Gates
Note: DC and switching characteristics for –F speed grade targets based only on simulation. The characteristics provided for –F speed
grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future
revisions of this document. The –F speed grade is only supported in commercial temperature range.
Advanced v0.7
iii
Fusion Family of Mixed-Signal Flash FPGAs
Temperature Grade Offerings
Fusion Devices
ARM-Enabled Devices
QN108
AFS090
AFS250
AFS600
AFS1500
M7AFS600
M7AFS1500
C, I
C, I
–
–
C, I
C, I
C, I
–
–
–
–
–
QN180
PQ208
C, I
C, I
C, I
–
–
FG256
C, I
–
C, I
C, I
C, I
FG484
FG676
–
–
Notes:
1. C = Commercial Temperature Range: 0°C to 70°C Ambient
2. I = Industrial Temperature Range: –40°C to 85°C Ambient
Speed Grade and Temperature Grade Matrix
–F1
Std.
✓
–1
✓
–2
✓
C2
✓
I3
–
✓
✓
✓
Notes:
1. DC and switching characteristics for –F speed grade targets based only on simulation. The characteristics provided for –F speed grade
are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions
of this document. The –F speed grade is only supported in commercial temperature range.
2. C = Commercial Temperature Range: 0°C to 70°C Ambient
3. I = Industrial Temperature Range: –40°C to 85°C Ambient
Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).
iv
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table of Contents
Introduction and Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Unprecedented Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Device Architecture
Fusion Stack Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Real-Time Counter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
Analog Configuration MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
User I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-168
Software Tools and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-171
DC and Power Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Package Pin Assignments
108-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
180-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Advanced v0.7
v
Fusion Family of Mixed-Signal Flash FPGAs
Introduction and Overview
Introduction
The Actel Fusion™ Programmable System Chip (PSC)
satisfies the demand from system architects for a device
that simplifies design and unleashes their creativity. As
the world’s first mixed-signal FPGA family, Fusion
integrates mixed-signal analog, Flash memory, and FPGA
fabric in a monolithic PSC. Actel Fusion devices enable
designers to quickly move from concept to completed
design, and then deliver feature-rich systems to market.
This new technology takes advantage of the unique
properties of Actel Flash-based FPGAs, including a high-
isolation, triple-well process, and the ability to support
high-voltage transistors to meet the demanding
requirements of mixed-signal system design.
also add a comprehensive hardware/software debug
capability as well as a suite of utilities to simplify
development of embedded soft processor-based
solutions.
General Description
The Actel Fusion family, based on the highly successful
ProASIC®3 and ProASIC3E Flash FPGA architecture, has
been designed as a high-performance, programmable,
mixed-signal platform. By combining an advanced Flash
FPGA core with Flash memory blocks and analog
peripherals, Fusion devices dramatically simplify system
design, and as a result, dramatically reduce overall
system cost and board space.
Actel Fusion PSCs bring the benefits of programmable
logic to many application areas, including power
management, smart battery charging, clock generation
and management, and motor control. Until now, these
applications have only been implemented with costly
and space-consuming discrete analog components or
mixed-signal ASIC solutions. Actel Fusion PSCs present
new capabilities for system development by allowing
designers to integrate a wide range of functionality into
a single device, while at the same time offering the
flexibility of upgrades late in the manufacturing process
or after the device is in the field. Actel Fusion devices
provide an excellent alternative to costly and time-
consuming mixed-signal ASIC designs. In addition, when
used in conjunction with the Actel 8051-based or ARM-
based soft MCU core, the Actel Fusion technology
represents the definitive PSC platform.
The state-of-the-art Flash memory technology offers
high-density integrated Flash memory blocks, enabling
savings in cost, power, and board area relative to
external Flash solutions, while providing increased
flexibility and performance. The Flash memory blocks
and integrated analog peripherals enable true mixed-
mode programmable logic designs. Two examples
include using an on-chip soft processor to implement a
fully functional Flash MCU, or using high-speed FPGA
logic to offer system and power supervisory capabilities.
Live at power-up and capable of operating from a single
3.3 V supply, the Fusion family is ideally suited for system
management and control applications.
The devices in the Fusion family are categorized by FPGA
core density. Each family member contains many
peripherals, including Flash memory blocks, analog to
digital converter (ADC), high-drive outputs, both RC and
crystal oscillators, and real-time counter (RTC). This
provides the user with a high level of flexibility and
integration to support a wide variety of mixed-signal
applications. The Flash memory block capacity ranges
from 2 Mbits to 8 Mbits. The integrated 12-bit ADC
supports up to 30 independently configurable input
channels. The on-chip crystal and RC oscillators work in
conjunction with the integrated phase-locked loops
(PLLs) to provide clocking support to the FPGA array and
on-chip resources. In addition to supporting typical RTC
uses such as watchdog timer, the Fusion RTC can control
the on-chip voltage regulator to power down the device
(FPGA fabric, Flash memory block, and ADC), enabling a
low power standby mode.
Flash-based Fusion devices are live at power-up. As soon
as system power is applied and within normal operating
specifications, Fusion devices are working. Fusion devices
have a 128-bit Flash-based lock and industry-leading AES
decryption, used to secure programmed intellectual
property (IP) and configuration data. Actel Fusion
devices are the most comprehensive single-chip analog
and digital programmable logic solution available today.
To support this new ground-breaking technology, Actel
has developed a series of major tool innovations to help
maximize designer productivity. Implemented as
extensions to the popular Actel Libero® Integrated
Design Environment (IDE), these new tools will allow
designers to easily instantiate and configure peripherals
within a design, establish links between peripherals,
create or import building blocks or reference designs,
and perform hardware verification. This tools suite will
Advanced v0.7
1-1
Fusion Family of Mixed-Signal Flash FPGAs
The Actel Fusion family offers revolutionary features,
never before available in an FPGA. The nonvolatile Flash
technology gives the Fusion family the advantage of
being a secure, low power, single-chip solution that is
live at power-up. Fusion is reprogrammable and offers
time to market benefits at an ASIC-level unit cost. These
features enable designers to create high-density systems
using existing ASIC or FPGA design flows and tools.
standard was adopted by the National Institute of
Standards and Technology (NIST) in 2000 and replaces
the DES standard, which was adopted in 1977. Fusion
devices have a built-in AES decryption engine and a
Flash-based AES key that make Fusion devices the most
comprehensive programmable logic device security
solution available today. Fusion devices with AES-based
security allow for secure remote field updates over
public networks, such as the Internet, and ensure that
valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. As an
additional security measure, the FPGA configuration
data of a programmed Fusion device cannot be read
back, although secure design verification is possible.
During design, the user controls and defines both
internal and external access to the Flash memory blocks.
The family has up to 1.5 M system gates, supported with
up to 270 kbits of true dual-port SRAM, up to 8 Mbits of
Flash memory, 1 kbit of user FlashROM, and up to 278
user I/Os. With integrated Flash memory, the Fusion
family is the ultimate soft processor platform. The
AFS600 and AFS1500 devices both support the Actel
ARM7 core (CoreMP7). The ARM-enabled versions are
identified with the M7 prefix as M7AFS600 and
M7AFS1500.
Security, built into the FPGA fabric, is an inherent
component of the Fusion family. The Flash cells are
located beneath seven metal layers and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. Fusion with FlashLock
and AES security is unique in being highly resistant to
both invasive and noninvasive attacks. Your valuable IP is
protected, making secure remote ISP possible. A Fusion
device provides the most impenetrable security for
programmable logic designs.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost,
high performance, and ease of use. The Flash-based
Fusion devices are live at power-up and do not need to
be loaded from an external boot PROM. On-board
security mechanisms prevent access to the programming
information and enable secure remote updates of the
FPGA logic. Designers can perform secure remote in-
system reprogramming to support future design
iterations and field upgrades with confidence that
valuable intellectual property (IP) cannot be
compromised or copied. Secure ISP can be performed
using the industry standard AES algorithm, with MAC
data authentication on-board the device. The Fusion
family device architecture mitigates the need for ASIC
migration at higher user volumes. This makes the Fusion
family a cost-effective ASIC replacement solution for
applications in the consumer, networking and
communications, computing, and avionics markets.
Single Chip
Flash-based FPGAs store the configuration information
in on-chip Flash cells. Once programmed, the
configuration data is an inherent part of the FPGA
structure and no external configuration data needs to be
loaded at system power-up (unlike SRAM-based FPGAs).
Therefore, Flash-based Fusion FPGAs do not require
system configuration components such as EEPROMs or
microcontrollers to load the device configuration data.
This reduces bill-of-materials costs and printed circuit
board (PCB) area, and increases security and system
reliability.
Live at Power-Up
Security
Flash-based Fusion devices are Level 0 live at power-up
(LAPU). LAPU Fusion devices greatly simplify total system
design and reduce total system cost by eliminating the
need for Complex Programmable Logic Devices (CPLDs).
The Fusion LAPU clocking (PLLs) replaces off-chip
clocking resources. The Fusion mix of LAPU clocking and
analog resources makes these devices an excellent choice
for both system supervisor and system management
functions. LAPU from a single 3.3 V source enables Fusion
devices to initiate, control, and monitor multiple voltage
supplies, while also providing system clocks. In addition,
glitches and brownouts in system power will not corrupt
the Fusion device Flash configuration. Unlike SRAM-
based FPGAs, the device will not have to be reloaded
when system power is restored. This enables reduction or
complete removal of the expensive voltage monitor and
As the nonvolatile, Flash-based Fusion family requires no
boot PROM, there is no vulnerable external bitstream.
Fusion devices incorporate FlashLock, which provides a
unique combination of reprogrammability and design
security without external overhead, advantages that
only an FPGA with nonvolatile, Flash programming can
offer.
Fusion devices utilize a 128-bit Flash-based key lock and a
separate AES key used to secure programmed
intellectual property (IP) and configuration data. The
FlashROM data in the Fusion devices can also be
encrypted prior to loading. Additionally, the Flash
memory blocks can be programmed during runtime
using the industry-leading AES-128 block cipher
encryption standard (FIPS Publication 192). The AES
1-2
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
brownout detection devices from the PCB design. Flash-
based Fusion devices simplify total system design and
reduce cost and design risk, while increasing system
reliability.
Advanced Architecture
The proprietary Fusion architecture provides granularity
comparable to standard-cell ASICs. The Fusion device
consists of several distinct and programmable
architectural features, including the following (Figure 1-1
on page 1-5):
Firm Errors
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. Another source of radiation-induced
firm errors comes from alpha particles. For an alpha to
cause a soft or firm error, its source must be in very close
proximity to the affected circuit. The alpha source must
be in the package molding compound or in the die itself.
While low alpha molding compounds are being
increasingly used, this helps reduce but does not entirely
eliminate alpha-induced firm errors.
•
Embedded memories
–
–
–
Flash memory blocks
FlashROM
SRAM and FIFO
•
Clocking resources
–
–
–
–
PLL and CCC
RC oscillator
Crystal oscillator
No Glitch MUX (NGMUX)
•
•
•
Digital I/Os with advanced I/O standards
FPGA VersaTiles
Firm errors are impossible to prevent in SRAM FPGAs.
The consequence of this type of error can be a complete
system failure. Firm errors do not occur in Fusion Flash-
based FPGAs. Once it is programmed, the Flash cell
configuration element of Fusion FPGAs cannot be
altered by high-energy neutrons and is therefore
immune to errors from them.
Analog components
–
–
Analog-to-digital converter (ADC)
Analog I/Os supporting voltage, current, and
temperature monitoring
–
–
1.5 V on-board voltage regulator
Real-time counter
Recoverable (or soft) errors occur in the user data SRAMs
of all FPGA devices. These can easily be mitigated by
using error detection and correction (EDAC) circuitry
built into the FPGA fabric.
The FPGA core consists of a sea of VersaTiles. Each
VersaTile can be configured as a three-input logic lookup
table (LUT) equivalent or a D-flip-flop or latch (with or
without enable) by programming the appropriate Flash
switch interconnections. This versatility allows efficient
use of the FPGA fabric. The VersaTile capability is unique
to the Actel families of Flash-based FPGAs. VersaTiles and
larger functions are connected with any of the four
levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile,
reconfigurable interconnect programming. Maximum
core utilization is possible for virtually any design.
Low Power
Flash-based Fusion devices exhibit power characteristics
similar to those of an ASIC, making them an ideal choice
for power-sensitive applications. With Fusion devices,
there is no power-on current surge and no high current
transition, both of which occur on many FPGAs.
Fusion devices also have low dynamic power
consumption and support both low power standby mode
and very low power sleep mode, offering further power
savings.
In addition, extensive on-chip programming circuitry
allows for rapid (3.3 V) single-voltage programming of
the Fusion devices via an IEEE 1532 JTAG interface.
Advanced Flash Technology
The Fusion family offers many benefits, including
nonvolatility and reprogrammability through an
advanced Flash-based, 130-nm LVCMOS process with 7
layers of metal. Standard CMOS design techniques are
used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant Flash switches allows
very high logic utilization (much higher than competing
SRAM technologies) without compromising device
routability or performance. Logic functions within the
device are interconnected through a four-level routing
hierarchy.
Unprecedented Integration
Integrated Analog Blocks and Analog I/Os
Fusion devices offer a robust and flexible analog mixed-
signal capability in addition to the high-performance
Flash FPGA fabric and Flash memory block. The many
built-in analog peripherals include a configurable 32:1
input analog multiplexer (MUX), up to 10 independent
metal-oxide
semiconductor
field-effect
transistor
Advanced v0.7
1-3
Fusion Family of Mixed-Signal Flash FPGAs
(MOSFET) gate driver outputs, and a configurable ADC.
The ADC supports 8-, 10-, and 12-bit modes of operation
with a cumulative sample rate up to 600 k samples per
second (ksps), differential nonlinearity (DNL) < 1.0 LSB,
and Total Unadjusted Error (TUE) of 4 LSB in 10-bit
mode. The TUE is used for characterization of the
conversion error, and includes errors from all sources,
such as offset and linearity. Internal bandgap circuitry
offers 1% voltage reference accuracy with the flexibility
of utilizing an external reference voltage. The ADC
channel sampling sequence and sampling rate are
programmable and implemented in the FPGA logic using
Designer and Libero IDE software tool support.
With Fusion, Actel also introduces the Analog Quad I/O
structure (Figure 1-1 on page 1-5). Each quad consists of
three analog inputs and one gate driver. Each quad can
be configured in various built-in circuit combinations,
such as three pre-scaler circuits, three digital input
circuits, a current monitor circuit, or a temperature
monitor circuit. Each pre-scaler has multiple scaling
factors programmed by FPGA signals to support a large
range of analog inputs with positive or negative polarity.
The input range for voltage signals is from –12 V to +12
V with full-scale output values from 0.125 V to 16 V.
When the current monitor circuit is selected, two
adjacent analog inputs measure the voltage drop across
a small external sense resistor. Built-in operational
amplifiers (op amps) amplify small voltage signals (2 mV
sensitivity) for accurate current measurement. One
analog input in each quad may be connected to an
external temperature monitor diode and achieves
detection accuracy of 2ꢀC with calibration. In addition
to the external temperature monitor diode(s), a Fusion
device can monitor an internal temperature diode using
dedicated channel 31 of the ADCMUX.
Two channels of the 32-channel ADCMUX are dedicated.
Channel 0 is connected internally to VCC and can be used
to monitor core power supply. Channel 31 is connected
to an internal temperature diode which can be used to
monitor device temperature. The 30 remaining channels
can be connected to external analog signals. The exact
number of I/Os available for external connection signals
is device-dependent (refer to Table 1 on page i for
details).
Figure 1-1 on page 1-5 illustrates a typical use of the
Analog Quad I/O structure. The Analog Quad shown is
configured to monitor and control an external power
supply. The AV pad is measuring the source of the power
supply. The AC pad is measuring the voltage drop across
an external sense resistor in order to calculate current.
The AG MOSFET gate driver pad turns the external
MOSFET on and off. The AT pad is measuring the load
side voltage level.
1-4
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Power
Line Side
Load Side
Off-Chip
Rpullup
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Pre-
Scaler
Pre-
Scaler
Pre-
Scaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor/Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 1-1 • Analog Quad
Advanced v0.7
1-5
Fusion Family of Mixed-Signal Flash FPGAs
Embedded Memories
Flash Memory Blocks
•
•
Block Buffer – Contains the contents of the last
block accessed. A block contains 128 data bits.
The Flash memory available in each Fusion device is
composed of 1 to 4 Flash blocks, each 2 Mbits in density.
Each block operates independently with a dedicated Flash
controller and interface. Fusion Flash memory blocks
combine fast access times (60 ns random access and 10 ns
access in Read-Ahead mode) with a configurable 8-, 16-,
or 32-bit datapath, enabling high-speed Flash operation
without wait states. The memory block is organized in
pages and sectors. Each page has 128 bytes, with 33 pages
comprising one sector and 64 sectors per block. The Flash
block can support multiple partitions. The only constraint
on size is that partition boundaries must coincide with
page boundaries. The flexibility and granularity enable
many use models and allow added granularity in
programming updates.
ECC Logic – The Flash memory stores error
correction information with each block to perform
single-bit error correction and double-bit error
detection on all data blocks.
User Nonvolatile FlashROM
In addition to the Flash blocks, Actel Fusion devices have
1 kbit of user-accessible, nonvolatile FlashROM on-chip.
The FlashROM is organized as 8x128-bit pages. The
FlashROM can be used in diverse system applications:
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Fusion devices support two methods of external access to
the Flash memory blocks. The first method is a serial
interface that features a built-in JTAG-compliant port,
which allows in-system programmability during user or
monitor/test modes. This serial interface supports
programming of an AES-encrypted stream. Secure data
can be passed through the JTAG interface, decrypted, and
then programmed in the Flash block. The second method
is a soft parallel interface.
Subscription-based business models (for example,
set-top boxes)
•
Secure key storage for secure communications
algorithms
•
•
•
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IEEE 1532
JTAG programming interface. Pages can be individually
programmed (erased and written). On-chip AES
decryption can be used selectively over public networks
to securely load data such as security keys stored in the
FlashROM for a user design.
FPGA logic or an on-chip soft microprocessor can access
Flash memory through the parallel interface. Since the
Flash parallel interface is implemented in the FPGA fabric,
it can potentially be customized to meet special user
requirements. The Flash memory parallel interface
provides configurable byte-wide (x8), word-wide (x16), or
dual word-wide (x32) data port options. Through the
programmable Flash parallel interface, the on-chip and
off-chip memories can be cascaded for wider or deeper
configurations.
The FlashROM can be programmed (erased and written)
via the JTAG programming interface, and its contents
can be read back either through the JTAG programming
interface or via direct FPGA core addressing.
The Flash memory has built-in security. The user can
configure either the entire Flash block or the small blocks
to prevent unintentional or intrusive attempts to change
or destroy the storage contents. Each on-chip Flash
memory block has a dedicated controller, enabling each
block to operate independently.
The FlashPoint tool in the Actel Fusion development
software solutions, Libero IDE and Designer, has
extensive support for Flash memory blocks and
FlashROM memory. One such feature is auto-generation
of sequential programming files for applications
requiring a unique serial number in each part. Another
feature allows the inclusion of static data for system
version control. Data for the FlashROM can be generated
quickly and easily using Actel Libero IDE and Designer
software tools. Comprehensive programming file
support is also included to allow for easy programming
of large numbers of parts with differing FlashROM
contents.
The Flash block logic consists of the following sub-blocks:
•
Flash block – Contains all stored data. The Flash
block contains 64 sectors and each sector contains
33 pages of data.
•
Page Buffer – Contains the contents of the current
page that is being modified. A page contains 8
blocks of data.
1-6
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
SRAM and FIFO
Fusion devices have embedded SRAM blocks along the
north and south sides of the device. Each variable-aspect-
ratio SRAM block is 4,608 bits in size. Available memory
configurations are 256x18, 512x9, 1kx4, 2kx2, and
4kx1 bits. The individual blocks have independent read
and write ports that can be configured with different bit
widths on each port. For example, data can be written
through a 4-bit port and read as a single bitstream. The
SRAM blocks can be initialized from the Flash memory
blocks or via the device JTAG port (ROM emulation
mode), using the UJTAG macro.
–
–
–
–
70 ps at 350 MHz
90 ps at 100 MHz
180 ps at 24 MHz
Worst case < 2.5% × clock period
•
•
Maximum acquisition time = 150 µs
Low Power Consumption of 5 mW
Global Clocking
Fusion devices have extensive support for multiple
clocking domains. In addition to the CCC and PLL support
described above, there are on-chip oscillators as well as a
comprehensive global clock distribution network.
In addition, every SRAM block has an embedded FIFO
control unit. The control unit allows the SRAM block to
be configured as a synchronous FIFO without using
additional core VersaTiles. The FIFO width and depth are
programmable. The FIFO also features programmable
Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags in
addition to the normal EMPTY and FULL flags. The
embedded FIFO control unit contains the counters
necessary for the generation of the read and write
address pointers. The SRAM/FIFO blocks can be cascaded
to create larger configurations.
The integrated RC oscillator generates a 100 MHz clock.
It is used internally to provide a known clock source to
the Flash memory read and write control. It can also be
used as a source for the PLLs.
The crystal oscillator supports the following operating
modes:
•
•
•
Crystal (32.768 kHz to 20 MHz)
Ceramic (500 kHz to 8 MHz)
RC (32.768 kHz to 4 MHz)
Each VersaTile input and output port has access to nine
VersaNets: six main and three quadrant global networks.
The VersaNets can be driven by the CCC or directly
accessed from the core via MUXes. The VersaNets can be
used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
Clock Resources
PLL and Clock Conditioning Circuitry (CCC)
Fusion devices provide designers with very flexible clock
conditioning capabilities. Each member of the Fusion
family contains six CCCs. In the two larger family
members, two of these CCCs also include a PLL; the
smaller devices support one PLL.
Digital I/Os with Advanced I/O Standards
The Fusion family of FPGAs features a flexible digital I/O
structure, supporting a range of voltages (1.5 V, 1.8 V,
2.5 V, and 3.3 V). Fusion FPGAs support many different
digital I/O standards, both single-ended and differential.
The inputs of the CCC blocks are accessible from the
FPGA core or from one of several I/O inputs with
dedicated CCC block connections.
The I/Os are organized into banks, with four or five banks
per device. The configuration of these banks determines
the I/O standards supported. The banks along the east and
west sides of the device support the full range of I/O
standards (single-ended and differential). The south bank
supports the Analog Quads (analog I/O). In the family's
two smaller devices, the north bank supports multiple
single-ended digital I/O standards. In the family’s larger
devices, the north bank is divided into two banks of
digital Pro I/Os, supporting a wide variety of single-ended,
differential, and voltage-referenced I/O standards.
The CCC block has the following key features:
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz to
350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to
350 MHz
Clock phase adjustment via programmable and
fixed delays from –6.275 ns to +8.75 ns
•
•
•
Clock skew minimization (PLL)
Clock frequency synthesis (PLL)
On-chip analog clocking resources usable as
inputs:
Each I/O module contains several input, output, and enable
registers. These registers allow the implementation of the
following applications:
–
–
100 MHz on-chip RC oscillator
Crystal oscillator
•
•
Single-Data-Rate (SDR) applications
Additional CCC specifications:
Double-Data-Rate (DDR) applications—DDR LVDS I/O
for chip-to-chip communications
•
•
•
Internal phase shift = 0°, 90°, 180°, and 270°
Output duty cycle = 50% 1.5%
•
Fusion banks support LVPECL, LVDS, BLVDS and M-LVDS
with 20 multi-drop points.
Low output jitter. Samples of peak-to-peak period
jitter when a single global network is used:
Advanced v0.7
1-7
Fusion Family of Mixed-Signal Flash FPGAs
VersaTiles
The Fusion core consists of VersaTiles, which are also used in the successful Actel ProASIC3 family. The Fusion VersaTile
supports the following:
•
•
•
All three-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set and optional enable
Refer to Figure 1-2 for the VersaTile configuration arrangement.
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
Data
CLK
CLR
Y
X1
X2
X3
Data
CLK
Enable
Y
D-FF
LUT-3
D-FFE
Y
CLR
Figure 1-2 • VersaTile Configurations
Related Documents
Application Briefs
Context Save and Reload with Real-Timestamp
Using Fusion RAM as Multipliers
http://www.actel.com/documents/
Fusion_ContextSaving_AB.pdf
http://www.actel.com/documents/
Fusion_Multipliers_AN.pdf
Power Sequencing and Management
Prototyping with AFS600 for Smaller Devices
http://www.actel.com/documents/
Fusion_Power_Sequencing_AB.pdf
http://www.actel.com/documents/
Fusion_Prototyp_AN.pdf
Real-Time Clock in Actel Fusion FPGAs
http://www.actel.com/documents/Fusion_RTC_AB.pdf
User’s Guides
Designer User's Guide
Lower Power Operation with the Fusion Device
http://www.actel.com/documents/
Fusion_LowPower_AB.pdf
http://www.actel.com/documents/designer_UG.pdf
Fusion Design Flow Tutorial
Smart Battery Management Applications
http://www.actel.com/documents/fusion_df_ug.pdf
Fusion and ProASIC3/E Macro Library Guide
http://www.actel.com/documents/pa3_libguide_ug.pdf
Peripherals User’s Guide
http://www.actel.com/documents/
Fusion_SmartBat_AB.pdf
Application Notes
Fusion FlashROM
http://www.actel.com/documents/peripheral_ug.pdf
SmartGen, FlashROM, Flash Memory System Builder, and
Analog System Builder User's Guide
http://www.actel.com/documents/Fusion_FROM_AN.pdf
Fusion SRAM/FIFO Blocks
http://www.actel.com/documents/genguide_ug.pdf
http://www.actel.com/documents/
Fusion_RAM_FIFO_AN.pdf
White Papers
Fusion Technology
Using DDR in Fusion Devices
http://www.actel.com/documents/Fusion_DDR_AN.pdf
Fusion Security
http://www.actel.com/documents/Fusion_Tech_WP.pdf
http://www.actel.com/documents/
Fusion_Security_AN.pdf
1-8
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Device Architecture
Fusion Stack Architecture
To manage the unprecedented level of integration in
Fusion devices, Actel developed the Fusion technology
stack (Figure 2-1). This layered model offers a flexible
design environment, enabling design at very high and
very low levels of abstraction. Fusion peripherals include
hard analog IP and hard and soft digital IP. Peripherals
will communicate across the FPGA fabric via a layer of
soft gates—the Fusion backbone. Much more than a
common bus interface, this Fusion backbone integrates a
micro-sequencer within the FPGA fabric and will
configure the individual peripherals and support low-
level processing of peripheral data. Fusion applets are
application building blocks that can control and respond
to peripherals and other system signals. Applets can be
rapidly combined to create large applications. The
technology is scalable across devices, families, design
types, and user expertise, and supports a well-defined
interface for external IP and tool integration.
Connecting and controlling access to the peripherals is
the Fusion backbone, Level 1. The backbone is a soft-
gate structure and is scalable to any number of
peripherals. The backbone is a bus and much more; it
manages peripheral configuration to ensure proper
operation. Leveraging the common peripheral interface
and a low-level state machine, the backbone efficiently
offloads peripheral management from the system
design. The backbone can set and clear flags based upon
peripheral behavior and define performance criteria. The
flexibility of the stack enables a designer to configure
the silicon, directly bypassing the backbone if that level
of control is desired.
One step up from the backbone is the Fusion applet,
Level 2. The applet is an application building block that
implements a specific function in FPGA gates. It can react
to stimuli and board-level events coming through the
backbone, or from other sources, and responds to these
stimuli by accessing and manipulating peripherals via the
backbone or initiating some other action. An applet
controls or responds to the peripheral(s). Applets can be
easily imported or exported from the design
environment. The applet structure is open and well-
defined, enabling users to import applets from Actel,
system developers, third parties, and user groups.
At the lowest level, Level 0, are Fusion peripherals. These
are configurable functional blocks that can be hardwired
structures such as a PLL or analog input channel, or soft
(FPGA-gate) blocks such as a UART or two-wire serial
interface. The Fusion peripherals are configurable and
support a standard interface to facilitate communication
and implementation.
Optional ARM or 8051 Processor
User Applications
Level 3
Level 2
Level 1
Fusion Applets
Flash
Memory
Fusion Smart Backbone
Smart Peripherals
in FPGA
Fabric
(e.g. logic, PLL, FIFO)
Analog
Smart
Peripheral 2 Peripheral n
Analog
Smart
Analog
Smart
Peripheral 1
Level 0
Note: Levels 1, 2, and 3 are implemented in FPGA logic gates.
Figure 2-1 • Fusion Architecture Stack
Advanced v0.7
2-1
Fusion Family of Mixed-Signal Flash FPGAs
The system application, Level 3, is the larger user
application that utilizes one or more applets. Designing
at the highest level of abstraction supported by the Actel
Fusion technology stack, the application can be easily
created in FPGA gates by importing and configuring
multiple applets.
As illustrated in Figure 2-2, there are four inputs in a
logic VersaTile cell, and each VersaTile can be configured
using the appropriate Flash switch connections:
•
•
•
•
Any three-input logic function
Latch with clear or set
D-flip-flop with clear or set
In fact, in some cases an entire FPGA system design can
be created without any HDL coding.
Enable D-flip-flop with clear or set (on a fourth
input)
An optional MCU enables a combination of software and
HDL-based design methodologies. The MCU can be on-
chip or off-chip as system requirements dictate. System
portioning is very flexible, allowing the MCU to reside
above the applets or to absorb applets, or applets and
backbone, if desired.
VersaTiles can flexibly map the logic and sequential gates
of a design. The inputs of the VersaTile can be inverted
(allowing bubble pushing), and the output of the tile can
connect to high-speed, very-long-line routing resources.
VersaTiles and larger functions are connected with any of
the four levels of routing hierarchy.
The Actel Fusion technology stack enables a very flexible
design environment. Users can engage in design across a
continuum of abstraction from very low to very high.
When the VersaTile is used as an enable D-flip-flop, the
SET/CLR signal is supported by a fourth input, which can
only be routed to the core cell over the VersaNet (global)
network.
Core Architecture
The output of the VersaTile is F2 when the connection is
to the ultra-fast local lines, or YL when the connection is
to the efficient long-line or very-long-line resources
(Figure 2-2).
VersaTile
Based upon successful Actel ProASIC3/E logic architecture,
Fusion devices provide granularity comparable to gate
arrays. The Fusion device core consists of a sea-of-
VersaTiles architecture.
0
1
Y
pin 1
Data
X3
0
1
0
1
F2
YL
0
1
CLK
X2
CLR/
Enable
X1
CLR
XC*
Ground
Legend:
Via (hard connection)
Switch (Flash connection)
Note: *This input can only be connected to the global clock distribution network.
Figure 2-2 • Fusion Core VersaTile
2-2
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
VersaTile Characteristics
Sample VersaTile Specifications—Combinatorial Module
The Fusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are
presented for a sample of the library (Figure 2-3). For more details, refer to the Fusion and ProASIC3/E Macro Library
Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
XOR3
A
B
C
A
B
Y
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-3 • Sample of Combinatorial Cells
Advanced v0.7
2-3
Fusion Family of Mixed-Signal Flash FPGAs
tPD
A
NAND2 or
Y
Any Combinatorial
Logic
B
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD9(FR)
)
where edges are applicable for the particular combinatorial cell
VCCA
50%
50%
A, B, C
GND
VCCA
50%
50%
OUT
OUT
GND
tPD(FF)
tPD(RR)
V
CCA
tPD(FR)
50%
50%
tPD(RF)
GND
Figure 2-4 • Combinatorial Timing Model and Waveforms
2-4
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Timing Characteristics
Table 2-1 • Combinatorial Cell Propagation Delays
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Combinatorial Cell
Equation
Y = !A
Parameter
–2
–1
Std.
0.54
0.63
0.63
0.65
0.65
0.99
0.93
1.17
0.68
0.75
Units
ns
INV
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
tPD
0.40
0.47
0.47
0.49
0.49
0.74
0.70
0.87
0.51
0.56
0.46
0.54
0.54
0.55
0.55
0.84
0.79
1.00
0.58
0.64
AND2
NAND2
OR2
Y = A · B
ns
Y = !(A · B)
Y = A + B
ns
ns
NOR2
XOR2
MAJ3
XOR3
MUX2
AND3
Y = !(A + B)
Y = A ⊕ B
Y = MAJ (A, B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
ns
ns
ns
ns
ns
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Sample VersaTile Specifications—Sequential Module
The Fusion library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and
optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from
the library (Figure 2-5). For more details, refer to the Fusion and ProASIC3/E Macro Library Guide.
DATA
CLK
OUT
DATA
OUT
D
Q
D
Q
EN
DFN1
DFN1E1
CLK
PRE
DATA
OUT
DATA
OUT
Q
D
D
Q
EN
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-5 • Sample of Sequential Cells
Advanced v0.7
2-5
Fusion Family of Mixed-Signal Flash FPGAs
tCKMPWH tCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tHD
tSUD
50%
50%
Data
EN
0
tWPRE
50%
tRECPRE
50%
50%
tREMPRE
50%
tHE
PRE
CLR
Out
tSUE
tRECCLR
50%
tWCLR
50%
tREMCLR
50%
tPRE2Q
tCLR2Q
50%
50%
50%
tCLKQ
Figure 2-6 • Sequential Timing Model and Waveforms
Sequential Timing Characteristics
Table 2-2 • Register Delays
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tCLKQ
Description
–2
–1
Std.
0.74
0.57
0.00
0.61
0.00
0.53
0.53
0.00
0.30
0.00
0.30
0.33
0.33
0.48
0.54
Units
ns
Clock-to-Q of the Core Register
0.55
0.43
0.00
0.45
0.00
0.40
0.40
0.00
0.22
0.00
0.22
0.25
0.25
0.36
0.41
0.63
0.49
0.00
0.52
0.00
0.45
0.45
0.00
0.25
0.00
0.25
0.28
0.28
0.41
0.46
tSUD
Data Setup time for the Core Register
ns
tHD
Data Hold time for the Core Register
ns
tSUE
Enable Setup time for the Core Register
ns
tHE
Enable Hold time for the Core Register
ns
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal time for the Core Register
Asynchronous Clear Recovery time for the Core Register
Asynchronous Preset Removal time for the Core Register
Asynchronous Preset Recovery time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
ns
ns
ns
ns
ns
ns
ns
tWPRE
ns
tCKMPWH
tCKMPWL
ns
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-6
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Array Coordinates
During many place-and-route operations in the Actel
Designer software tool, it is possible to set constraints
that require array coordinates. Table 2-3 is provided as a
reference. The array coordinates are measured from the
lower left (0, 0). They can be used in region constraints
for specific logic groups/blocks, designated by a wildcard,
and can contain core cells, memories, and I/Os.
cells and edge core cells. In addition, the I/O coordinate
system changes depending on the die/package
combination. It is not listed in Table 2-3. The Designer
ChipPlanner tool provides array coordinates of all I/O
locations. I/O and cell coordinates are used for placement
constraints. However, I/O placement is easier by package
pin assignment.
Table 2-3 provides array coordinates of core cells and
memory blocks.
Figure 2-7 illustrates the array coordinates of an AFS600
device. For more information on how to use array
coordinates for region/placement constraints, see the
Designer User's Guide or online help (available in the
software) for Fusion software tools.
I/O and cell coordinates are used for placement
constraints. Two coordinate systems are needed because
there is not a one-to-one correspondence between I/O
Table 2-3 • Array Coordinates
VersaTiles
Memory Rows
All
Min.
Max.
Bottom
Top
(x, y)
(3, 26)
(3, 50)
(3, 76)
(3, 100)
Min.
(x, y)
(0, 0)
(0, 0)
(0, 0)
(0, 0)
Max.
(x, y)
Device
AFS090
AFS250
AFS600
AFS1500
x
3
3
3
3
y
2
2
4
4
x
y
(x, y)
None
None
(3, 2)
(3, 2)
66
25
49
75
99
(69, 29)
(133, 53)
(197, 79)
(261, 103)
130
194
258
I/O Tile
Top Row (7, 79) to (189, 79)
Bottom Row (5, 78) to (192, 78)
(0, 79)
(197, 79)
Memory
Blocks
(3, 77)
(3, 76)
(194, 77)
(194, 76)
Memory
Blocks
VersaTile (Core)
(3, 75)
(194, 75)
VersaTile (Core)
(194, 4)
VersaTile(Core)
VersaTile (Core)
(3, 4)
(194, 3) Memory
Blocks
(194, 2)
Memory
Blocks
(3, 3)
(3, 2)
(197, 1)
(197, 0)
(0, 0)
UJTAG FlashROM
I/O Tile to Analog Block
Top Row (5, 1) to (168, 1)
Top Row (169, 1) to (192, 1)
Bottom Row (7, 0) to (165, 0)
Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates
are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}.
Figure 2-7 • Array Coordinates for AFS600
Advanced v0.7
2-7
Fusion Family of Mixed-Signal Flash FPGAs
Routing Architecture
The routing structure of Fusion devices is designed to
provide high performance through a flexible four-level
hierarchy of routing resources: ultra-fast local resources;
efficient long-line resources; high-speed, very-long-line
resources; and the high-performance VersaNet networks.
The high-speed, very-long-line resources, which span the
entire device with minimal delay, are used to route very
long or high-fanout nets: length +/–12 VersaTiles in the
vertical direction and length +/–16 in the horizontal
direction from a given core VersaTile (Figure 2-10 on
page 2-10). Very long lines in Fusion devices, like those in
The ultra-fast local resources are dedicated lines that allow
the output of each VersaTile to connect directly to every
input of the eight surrounding VersaTiles (Figure 2-8). The
exception to this is that the SET/CLR input of a VersaTile
configured as a D-flip-flop is driven only by the VersaNet
global network.
ProASIC3, have been enhanced. This provides
significant performance boost for long-reach signals.
a
The high-performance VersaNet global networks are low-
skew, high-fanout nets that are accessible from external
pins or from internal logic (Figure 2-11 on page 2-11).
These nets are typically used to distribute clocks, reset
signals, and other high-fanout nets requiring minimum
skew. The VersaNet networks are implemented as clock
trees, and signals can be introduced at any junction. These
can be employed hierarchically with signals accessing
every input on all VersaTiles.
The efficient, long-line resources provide routing for
longer distances and higher fanout connections. These
resources vary in length (spanning one, two, or four
VersaTiles), run both vertically and horizontally, and
cover the entire Fusion device (Figure 2-9 on page 2-9).
Each VersaTile can drive signals onto the efficient long-
line resources, which can access every input of every
VersaTile. Active buffers are inserted automatically by
routing software to limit the loading effects.
Long Lines
L
L
L
L
L
L
Inputs
Ultra-Fast Local Lines
(connects a VersaTile to the
adjacent VersaTile, I/O buffer,
or memory block)
L
L
L
Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection.
Figure 2-8 • Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors
2-8
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Spans Four VersaTiles
Spans One VersaTile
Spans Two VersaTiles
L
VersaTile
L
L
L
L
L
L
L
L
L
L
L
L
Spans One VersaTile
L
L
L
L
L
Spans Two VersaTiles
Spans Four VersaTiles
L
L
L
L
L
L
L
L
L
L
L
L
Figure 2-9 • Efficient Long-Line Resources
Advanced v0.7
2-9
Fusion Family of Mixed-Signal Flash FPGAs
High-Speed, Very-Long-Line Resources
Pad Ring
SRAM
16×12 Block of VersaTiles
Figure 2-10 • Very-Long-Line Resources
2-10
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Global Resources (VersaNets)
Fusion devices offer powerful and flexible control of
circuit timing through the use of analog circuitry. Each
chip has six clock conditioning circuits (CCCs). The west
CCC also contains a phase-locked loop (PLL) core. In the
two larger devices (AFS600 and AFS1500), both the west
and the east CCC contain a PLL. The PLLs include delay
lines, a phase shifter (0°, 90°, 180°, 270°), and clock
multipliers/dividers. Each CCC has all the circuitry needed
for the selection and interconnection of inputs to the
VersaNet global network. The east and west CCCs each
have access to three VersaNet global lines on each side of
the chip (six lines total). The CCCs at the four corners
each have access to three quadrant global lines on each
quadrant of the chip.
addition, Fusion devices have three regional globals
(quadrant globals) in each of the four chip quadrants. Each
core VersaTile has access to nine global network resources:
three quadrant and six chip (main) global networks. There
are a total of 18 global networks on the device. Each of
these networks contains spines and ribs that reach all
VersaTiles in all quadrants (Figure 2-12 on page 2-12). This
flexible VersaNet global network architecture allows users
to map up to 180 different internal/external clocks in a
Fusion device. Details on the VersaNet networks are given
in Table 2-4 on page 2-12. The flexibility of the Fusion
VersaNet global network allows the designer to address
several design requirements. User applications that are
clock-resource-intensive can easily route external or gated
internal clocks using VersaNet global routing networks.
Designers can also drastically reduce delay penalties and
minimize resource usage by mapping critical, high-fanout
nets to the VersaNet global network.
Advantages of the VersaNet Approach
One of the architectural benefits of Fusion is the set of
powerful and low-delay VersaNet global networks. Fusion
offers six chip (main) global networks that are distributed
from the center of the FPGA array (Figure 2-11). In
Quadrant Global Pads
High-Performance
VersaNet Global Network
Pad Ring
Top Spine
Main (chip)
Global Network
Global
Pads
Chip (main)
Global Pads
Global Spine
Global Ribs
Bottom Spine
Spine-Selection
Tree MUX
Figure 2-11 • Overview of Fusion VersaNet Global Network
Advanced v0.7
2-11
Fusion Family of Mixed-Signal Flash FPGAs
Northwest Quadrant Global Network
CCC
CCC
3
3
3
3
3
Chip (main)
Global
Network
6
6
6
6
6
6
6
CCC
3
CCC
6
3
3
3
3
CCC
CCC
Southeast Quadrant Global Network
Figure 2-12 • Global Network Architecture
Table 2-4 • Globals/Spines/Rows by Device
AFS090
AFS250
AFS600
9
AFS1500
Global VersaNets (Trees)*
VersaNet Spines/Tree
Total Spines
9
4
9
8
9
12
20
36
72
108
180
VersaTiles in Each Top or Bottom Spine
Total VersaTiles
384
2,304
768
6,144
1,152
13,824
1,920
38,400
Note: *There are six chip (main) globals and three globals per quadrant.
2-12
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
VersaNet Global Networks and Spine Access
The Fusion architecture contains a total of 18 segmented
global networks that can access the VersaTiles, SRAM
memory, and I/O tiles on the Fusion device. There are 6
chip (main) global networks that access the entire device
and 12 quadrant networks (3 in each quadrant). Each
device has a total of 18 globals. These VersaNet global
networks offer fast, low-skew routing resources for high-
fanout nets, including clock signals. In addition, these
highly segmented global networks offer users the
flexibility to create low-skew local networks using spines
for up to 180 internal/external clocks (in an AFS1500
device) or other high-fanout nets in Fusion devices.
Optimal usage of these low-skew networks can result in
significant improvement in design performance on
Fusion devices.
The spines are the vertical branches of the global
network tree, shown in Figure 2-11 on page 2-11. Each
spine in a vertical column of a chip (main) global
network is further divided into two equal-length spine
segments: one in the top and one in the bottom half of
the die.
Each spine and its associated ribs cover a certain area of the
Fusion device (the "scope" of the spine; see Figure 2-11 on
page 2-11). Each spine is accessed by the dedicated global
network MUX tree architecture, which defines how a
particular spine is driven—either by the signal on the global
network from a CCC, for example, or another net defined
by the user (Figure 2-13). Quadrant spines can be driven
from user I/Os on the north and south sides of the die, via
analog I/Os configured as direct digital inputs. The ability to
drive spines in the quadrant global networks can have a
significant effect on system performance for high-fanout
inputs to a design.
The nine spines available in a vertical column reside in
global networks with two separate regions of scope: the
quadrant global network, which has three spines, and
the chip (main) global network, which has six spines.
Note that there are three quadrant spines in each
quadrant of the device. There are four quadrant global
network regions per device (Figure 2-12 on page 2-12).
Details of the chip (main) global network spine-selection
MUX are presented in Figure 2-13. The spine drivers for
each spine are located in the middle of the die.
Quadrant spines are driven from a north or south rib.
Access to the top and bottom ribs is from the corner CCC
or from the I/Os on the north and south sides of the
device.
Internal/External
Signals
Internal/External
Signals
Tree Node MUX
Tree Node MUX
Internal/External
Signal
Tree Node MUX
Global Rib
Internal/External
Signal
Global Driver MUX
Spine
Figure 2-13 • Spine-Selection MUX of Global Tree
Advanced v0.7
2-13
Fusion Family of Mixed-Signal Flash FPGAs
Clock Aggregation
Clock aggregation allows for multi-spine clock domains.
A MUX tree provides the necessary flexibility to allow
long-lines or I/Os to access domains of one, two, or four
global spines. Signal access to the clock aggregation
system is achieved through long-line resources in the
central rib, and also through local resources in the north
and south ribs, allowing I/Os to feed directly into the
clock system. As Figure 2-14 indicates, this access system
is contiguous.
There is no break in the middle of the chip for the north
and south I/O VersaNet access. This is different from the
quadrant clocks, located in these ribs, which only reach
the middle of the rib.
Global Spine
Global Rib
Global Driver and MUX
Tree Node MUX
I/O Tiles
I/O Access
Internal Signal Access
Global Signal Access
Figure 2-14 • Clock Aggregation Tree Architecture
2-14
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Global Resource Characteristics
AFS600 VersaNet Topology
Clock delays are device-specific. Figure 2-15 is an example of a global tree used for clock routing. The global tree
presented in Figure 2-15 is driven by a CCC located on the west side of the AFS600 device. It is used to drive all D-flip-
flops in the device.
Central
Global RIb
CCC
VersaTile
Rows
Global Spine
Figure 2-15 • Example of Global Tree Use in an AFS600 Device for Clock Routing
Advanced v0.7
2-15
Fusion Family of Mixed-Signal Flash FPGAs
VersaNet Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input
buffer clock delays, as these are dependent upon I/O standard, and the clock may be driven and conditioned internally
by the CCC module. Table 2-5, Table 2-6, and Table 2-7 present minimum and maximum global clock delays within the
device. Minimum and maximum delays are measured with minimum and maximum loading, respectively.
Timing Characteristics
Table 2-5 • AFS600 Global Resource Timing
Commercial Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Max.2
Parameter
tRCKL
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Min.1
1.28
Max.2
1.51
Min.1
1.46
Max.2
1.72
Min.1
1.71
Units
ns
2.02
2.08
tRCKH
1.28
1.55
1.45
1.77
1.71
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
tRCKSW
FRMAX
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
ns
0.27
0.31
0.37
ns
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a lightly
loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row
(all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Table 2-6 • AFS250 Global Resource Timing
Commercial Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Min.1
Parameter
tRCKL
Description
Min.1 Max.2
Min.1
1.36
Max.2
1.62
Max.2
1.91
Units
ns
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
1.19
1.19
1.42
1.46
1.59
1.59
tRCKH
1.35
1.66
1.96
ns
tRCKMPWH
tRCKMPWL
tRCKSW
ns
ns
0.27
0.31
0.37
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded
row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-16
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-7 • AFS090 Global Resource Timing
Commercial Case Conditions: TJ = 70°C, VCC = 1.425 V
–2
–1
Std.
Max.2 Min.1 Max.2
Parameter
tRCKL
Description
Min.1
1.18
Max.2
1.41
Min.1
1.34
Units
ns
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
1.60
1.64
1.58
1.57
1.89
1.93
tRCKH
1.17
1.44
1.33
ns
tRCKMPWH
tRCKMPWL
tRCKSW
ns
ns
0.27
0.31
0.37
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a
lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded
row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-17
Fusion Family of Mixed-Signal Flash FPGAs
Clocking Resources
The Fusion family has a robust collection of clocking
peripherals, as shown in the block diagram in Figure 2-16.
These on-chip resources enable the creation,
manipulation, and distribution of many clock signals. The
Fusion integrated RC oscillator produces a 100 MHz clock
source with no external components. For systems
requiring more precise clock signals, the Actel Fusion
family supports an on-chip crystal oscillator circuit. The
integrated PLLs in each Fusion device can use the RC
oscillator, crystal oscillator, or another on-chip clock
signal as a source. These PLLs offer a variety of
capabilities to modify the clock source (multiply, divide,
synchronize, advance, or delay). Utilizing the CCC found
in the popular Actel ProASIC3 family, Fusion incorporates
six CCC blocks. The CCCs allow access to Fusion global
and local clock distribution nets, as described in the
"Global Resources (VersaNets)" section on page 2-11.
Off-Chip On-Chip
100 MHz
RC Oscillator
GND_OSC
VCC_OSC
Clock Out to FPGA Core through CCC
XTAL1
GLINT
Crystal Oscillator
XTAL2
To Core
Xtal Clock
PLL/ GLA
NGMUX
CCC
External
Crystal
External
RC
Clock I/Os
GLC
or
CLKOUT
From FPGA Core
Figure 2-16 • Fusion Clocking Options
2-18
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
RC Oscillator
The RC oscillator is an on-chip free running clock source
generating a 100 MHz clock. It can be used as a source
clock for both on-chip and off-chip resources. When used
in conjunction with the Fusion PLL and CCC circuits, the
RC oscillator clock source can be used to generate clocks
of varying frequency and phase.
The Fusion RC oscillator is very accurate at 1% over
commercial and industrial temperature ranges. It is an
automated clock, requiring no setup or configuration by
the user. It requires only that the power and GND_OSC
pins be connected; no external components are required.
The RC oscillator can be used to drive either a PLL or
another internal signal.
RC Oscillator Characteristics
Table 2-8 • Electrical Characteristics of RC Oscillator
Parameter
Description
Operating Frequency
Accuracy
Condition
Min.
Typ.
100
1
Max.
Units
MHz
%
FRC
Temperature: 0°C to 85°C
Voltage: 3.3 V +/– 5%
Temperature: –40°C to 125°C
Voltage: 3.3 V +/– 5%
3
%
Output Jitter
Period Jitter (at 5 k cycles)
100
100
150
ps
ps
ps
Cycle–Cycle Jitter (at 5 k cycles)
Period Jitter (at 5 k cycles) with 1 kHz / 300 mV
peak-to-peak noise on power supply
Cycle–Cycle Jitter (at 5 k cycles) with 1 kHz /
300 mV peak-to-peak noise on power supply
150
ps
Output Duty Cycle
Operating Current
50
1
%
IDYNRC
mA
Advanced v0.7
2-19
Fusion Family of Mixed-Signal Flash FPGAs
Crystal Oscillator
The on-chip crystal oscillator circuit works with an off-
chip crystal to generate a high precision clock. It has an
accuracy of 100 ppm (0.01%) and is capable of providing
system clocks for Fusion peripherals and other system
clock networks, both on-chip and off-chip. When
combined with the on-chip CCC/PLL blocks, a wide range
of clock frequencies can be created to support various
design requirements.
configurations at a time. Typical design practices dictate
that the desired mode for the crystal oscillator be
determined and the board designed for a single
configuration. The crystal oscillator supports four modes
of operation, defined in Table 2-9.
In Mode 0, the oscillator is configured to work with an
external RC network. The RC components are connected
to the XTAL1 pin, with XTAL2 left floating. The
frequency generated by the circuit in Mode 0 is
determined by the RC time constant of the selected
components (Figure 2-18).
The on-chip circuitry is designed to work with an
external crystal, ceramic resonator, or a resistor-capacitor
(RC) network. It can only support one of these
Table 2-9 • Crystal Oscillator Mode Definition
Mode
RTCMODE/MODE[1:0]
Recommended Capacitor
Frequency Range (MHz)
N/A
RC network (Mode 0)
Low gain (Mode 1)
Medium gain (Mode 2)
High gain (Mode 3)
00
01
10
11
N/A
100 pF
100 pF
15 pF
0.032 to 0.20
0.20 to 2.0
2.0 to 20.0
XTL
CLKOUT
SELMODE
RTCMODE[1:0]
MODE[1:0]
Figure 2-17 • Crystal Oscillator Macro
RC Time Constant Values vs. Frequency
1.00E-0.3
1.00E-0.4
1.00E-0.5
1.00E-0.6
1.00E-0.7
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Frequency (MHz)
Figure 2-18 • Crystal Oscillator: RC Time Constant Values vs. Frequency (typical)
2-20
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
In Modes 1 to 3, the crystal oscillator is configured to
support an external crystal or ceramic resonator. These
modes correspond to low, medium, and high gain. They
differ in the frequency of crystal or resonator that is
supported. The crystal or resonator is connected to the
XTAL1 and XTAL2 pins. Additionally, a capacitor is
required on both XTAL1 and XTAL2 pins to ground
(Figure 2-16 on page 2-18). Table 2-9 on page 2-20
details each crystal oscillator mode, supported frequency
range, and recommended capacitor value.
A use model supported by the Fusion device involves
powering down the core while the real-time counter
(RTC) continues to run, clocked by the crystal oscillator.
When powered down, the core cannot control crystal
oscillator mode pins. Also, some designers may wish to
avoid the RTC altogether. To support both situations, the
crystal oscillator can be controlled by either the RTC or
the FGPA core. If the RTC is instantiated in the design, it
will by default use RTCMODE[1:0] to set the crystal
oscillator control pins (the default). If the RTC is not used
in the design, the FPGA core will set the crystal oscillator
control pins with MODE[1:0].
Crystal Oscillator Characteristics
Table 2-10 • Electrical Characteristics of the Crystal Oscillator
Parameter
Description
Condition
Using External Crystal
Using Ceramic Resonator
Using RC Network
Min.
0.032
0.5
Typ.
Max.
Units
MHz
MHz
MHz
%
FXTAL
Operating Frequency
20
8
0.032
4
Output Duty Cycle
Output Jitter
50
50
With 10 MHz Crystal
RC
ps RMS
mA
IDYNXTAL
Operating Current
0.6
0.6
0.6
0.6
10
0.032–0.2 MHz
0.2–2.0 MHz
2.0–20.0 MHz
mA
mA
mA
ISTBXTAL
PSRRXTAL
VIHXTAL
VILXTAL
Sleep Current
µA
Power Supply Noise Tolerance
Input Logic Level High
Input Logic Level Low
0.5
Vp–p
V
90% of VCC
10% of VCC
V
Advanced v0.7
2-21
Fusion Family of Mixed-Signal Flash FPGAs
Clock Conditioning Circuits
In Fusion devices, the CCCs are used to implement
frequency division, frequency multiplication, phase
shifting, and delay operations.
Each global buffer, as well as the PLL reference clock, can
be driven from one of the following:
•
•
•
Three dedicated single-ended I/Os using
hardwired connection
a
The CCCs are available in six chip locations—each of the
four chip corners and in the middle of the east and west
chip sides.
Two dedicated differential I/Os using a hardwired
connection
Each CCC can implement up to three independent global
buffers (with or without programmable delay), or a PLL
function (programmable frequency division/multiplication,
phase shift, and delays) with up to three global outputs.
Unused global outputs of a PLL can be used to
The FPGA core
The CCC block is fully configurable, either via Flash
configuration bits set in the programming bitstream or
through an asynchronous interface. This asynchronous
interface is dynamically accessible from inside the Fusion
device to permit parameter changes (such as divide
ratios) during device operation. To increase the
versatility and flexibility of the clock conditioning
system, the CCC configuration is determined either by
the user during the design process, with configuration
data being stored in Flash memory as part of the device
programming procedure, or by writing data into a
dedicated shift register during normal device operation.
This latter mode allows the user to dynamically
reconfigure the CCC without the need for core
programming. The shift register is accessed through a
simple serial interface. Refer to the "CCC and PLL
Characteristics" section on page 2-28 for more
information.
implement independent global buffers, up to
maximum of three global outputs for a given CCC.
a
A global buffer can be placed in any of the three global
locations (CLKA-GLA, CLKB-GLB, and CLKC-GLC) of a
given CCC.
A PLL macro uses the CLKA CCC input to drive its reference
clock. It uses the GLA and, optionally, the GLB and GLC
global outputs to drive the global networks. A PLL macro
can also drive the YB and YC regular core outputs. The
GLB (or GLC) global output cannot be reused if the YB (or
YC) output is used (Figure 2-19). Refer to the "PLL Macro"
section on page 2-27 for more information.
Clock Source
Clock Conditioning
Output
CLKA
EXTFB
POWERDOWN
OADIVRST
GLA
LOCK
Input LVDS/LVPECL Macro
GLA
or
PADN
PADP
Y
GLB
YB
GLC
YC
GLA and (GLB or YB)
or
GLA and (GLC or YC)
or
GLA and (GLB or YB) and
(GLC or YC)
INBUF2 Macro
Y
OADIVHALF
OADIV[4:0]
OAMUX[2:0]
DLYGLA[4:0]
OBDIV[4:0]
OBMUX[2:0]
DLYYB[4:0]
DLYGLB[4:0]
OCDIV[4:0]
OCMUX[2:0]
DLYYC[4:0]
DLYGLC[4:0]
FINDIV[6:0]
FBDIV[6:0]
PAD
FBDLY[4:0]
FBSEL[1:0]
XDLYSEL
VCOSEL[2:0]
Notes:
1. Visit the Actel website for future application notes concerning dynamic PLL reconfiguration. Refer to the "PLL Macro" section on
page 2-27 for signal descriptions.
2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family.
Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro
2-22
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-11 • Available Selections of I/O Standards within
Global Buffers with No Programmable
Delays
CLKBUF and CLKBUF_LVDS/LVPECL Macros
CLKBUF Macros
CLKBUF_LVCMOS5
CLKBUF_LVCMOS33 1
CLKBUF_LVCMOS18
CLKBUF_LVCMOS15
CLKBUF_PCI
The CLKBUF and CLKBUF_LVPECL/LVDS macros are
composite macros that include an I/O macro driving a
global buffer, which are hardwired together (Figure 2-20).
The CLKINT macro provides a global buffer function
driven by the FPGA core.
The CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros
are pass-through clock sources and do not use the PLL or
provide any programmable delay functionality.
CLKBUF_LVDS 2
Many specific CLKBUF macros support the wide variety of
single-ended and differential I/O standards supported by
Fusion devices. The available CLKBUF macros are
described in the Fusion and ProASIC3/E Macro Library
Guide.
CLKBUF_LVPECL
Notes:
1. This is the default macro. For more details refer to the
Fusion and ProASIC3/E Macro Library Guide.
2. BLVDS and M-LVDS standards are supported with
CLKBUF_LVDS.
Clock Source
Clock Conditioning
Output
GLA
or
CLKBUF_LVDS/LVPECL Macro
PADN
CLKBUF Macro
PAD
CLKINT Macro
None
GLB
or
Y
Y
A
Y
PADP
GLC
Figure 2-20 • Global Buffers with No Programmable Delay
Advanced v0.7
2-23
Fusion Family of Mixed-Signal Flash FPGAs
Global Buffers with Programmable Delay
The CLKDLY macro is a pass-through clock source that
does not use the PLL, but provides the ability to delay the
clock input using a programmable delay (Figure 2-21).
The CLKDLY macro takes the selected clock input and
adds a user-defined delay element. This macro generates
an output clock phase shift from the input clock.
The CLKDLY macro can be driven directly from the FPGA
core.
The CLKDLY macro can also be driven from an I/O that is
routed through the FPGA regular routing fabric. In this
case, users must instantiate a special macro, PLLINT, to
differentiate from the hardwired I/O connection
described earlier.
The CLKDLY macro can be driven by an INBUF macro to
create a composite macro, where the I/O macro drives
the global buffer (with programmable delay) using a
hardwired connection. In this case, the I/O must be
placed in one of the dedicated global I/O locations.
The visual CLKDLY configuration in the SmartGen part of
the Libero IDE and Designer tools allows the user to
select the desired amount of delay, and configures the
delay elements appropriately. SmartGen also allows the
user to select the input clock source. SmartGen will
automatically instantiate the special macro, PLLINT,
when needed.
Many specific INBUF macros support the wide variety of
single-ended and differential I/O standards supported by
the Fusion family. The available INBUF macros are
described in the Fusion and ProASIC3/E Macro Library
Guide.
Clock Source
Clock Conditioning
Output
GLA
or
Input LVDS/LVPECL Macro
CLK
GL
PADN
PADP
Y
GLB
or
DLYGL[4:0]
GLC
INBUF* Macro
Y
PAD
Figure 2-21 • Fusion CCC Options: Global Buffers with Programmable Delay
2-24
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Global Input Selections
Each global buffer, as well as the PLL reference clock, can be driven from one of the following (Figure 2-22):
•
•
•
Three dedicated single-ended I/Os using a hardwired connection
Two dedicated differential I/Os using a hardwired connection
The FPGA core
Each shaded box represents an
input buffer called out by the
appropriate name: INBUF or
INBUF_LVDS/LVPECL.
To Core
Sample Pin Names
GAA01
GAA11
+
Source for CCC
(CLKA or CLKB or CLKC)
Routed Clock
(from FPGA Core)2
GAA21
+
GAA[0:2]: GA represents global in the northwest corner
of the device. A[0:2]: designates specific A clock source.
Notes:
1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric.
Refer to the "User I/O Naming Convention" section on page 2-120 for more information.
2. Instantiate the routed clock source input as follows:
a) Connect the output of a logic element to the clock input of the PLL, CLKDLY, or CLKINT macro.
b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location.
3. LVDS-based clock sources are available in the east and west banks on all Fusion devices.
Figure 2-22 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT
Advanced v0.7
2-25
Fusion Family of Mixed-Signal Flash FPGAs
CCC Programming
CCC Physical Implementation
The CCC circuit is composed of the following (Figure 2-23):
The CCC block is fully configurable. It is configured via
static Flash configuration bits in the array, set by the user
in the programming bitstream, or configured through an
asynchronous dedicated shift register dynamically
accessible from inside the Fusion device. The dedicated
shift register permits parameter changes such as PLL
divide ratios and delays during device operation. This
latter mode allows the user to dynamically reconfigure
the PLL without the need for core programming. The
register file is accessed through a simple serial interface.
•
•
•
•
PLL core
Three phase selectors
Six programmable delays and one fixed delay
Five programmable frequency dividers that
provide frequency multiplication/division (not
shown in Figure 2-23 because they are
automatically configured based on the user's
required frequencies)
•
One dynamic shift register that provides CCC
dynamic reconfiguration capability (not shown).
CLKA
Four-Phase Output
GLA
Programmable
Delay Type 2
Phase
Select
PLL Core
Programmable
Delay Type 1
Fixed Delay
Programmable
Delay Type 2
GLB
YB
Phase
Select
Programmable
Delay Type 1
Programmable
Delay Type 2
GLC
Phase
Select
YC
Programmable
Delay Type 1
Note: Clock divider and multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured based on the
user's required frequencies.
Figure 2-23 • PLL Block
2-26
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
PLL Macro
The PLL functionality of the clock conditioning block is
supported by the PLL macro. Note that the PLL macro
reference clock uses the CLKA input of the CCC block,
which is only accessible from the global A[0:2] package
pins. Refer to Figure 2-22 on page 2-25 for more
information.
As illustrated, the PLL supports three distinct output
frequencies from a given input clock. Two of these (GLB
and GLC) can be routed to the B and C global networks,
respectively, and/or routed to the device core (YB and YC).
There are five delay elements to support phase control
on all five outputs (GLA, GLB, GLC, YB, and YC).
The PLL macro provides five derived clocks (three
independent) from a single reference clock. The PLL
feedback loop can be driven either internally or
externally. The PLL macro also provides power-down input
and lock output signals. During power-up, POWERDOWN
should be asserted low until VCC is up. See Figure 2-19 on
page 2-22 for more information.
There is also a delay element in the feedback loop that
can be used to advance the clock relative to the
reference clock.
The PLL macro reference clock can be driven by an INBUF
macro to create a composite macro, where the I/O macro
drives the global buffer (with programmable delay)
using a hardwired connection. In this case, the I/O must
be placed in one of the dedicated global I/O locations.
Inputs:
•
•
CLKA: selected clock input
The PLL macro reference clock can be driven directly
from the FPGA core.
POWERDOWN (active low): disables PLLs. The
default state is power-down on (active low).
The PLL macro reference clock can also be driven from an
I/O that is routed through the FPGA regular routing
fabric. In this case, users must instantiate a special macro,
PLLINT, to differentiate it from the hardwired I/O
connection described earlier.
Outputs:
•
•
•
LOCK (active high): indicates that PLL output has
locked on the input reference signal
GLA, GLB, GLC: outputs to respective global
networks
The visual PLL configuration in SmartGen, available with
the Libero IDE and Designer tools, will derive the
necessary internal divider ratios based on the input
frequency and desired output frequencies selected by
the user. SmartGen allows the user to select the various
delays and phase shift values necessary to adjust the
phases between the reference clock (CLKA) and the
derived clocks (GLA, GLB, GLC, YB, and YC). SmartGen
also allows the user to select where the input clock is
coming from. SmartGen automatically instantiates the
special macro, PLLINT, when needed.
YB, YC: allows output from the CCC to be routed
back to the FPGA core
As previously described, the PLL allows up to five flexible
and independently configurable clock outputs. Figure 2-23
on page 2-26 illustrates the various clock output options
and delay elements.
Advanced v0.7
2-27
Fusion Family of Mixed-Signal Flash FPGAs
CCC and PLL Characteristics
Timing Characteristics
Table 2-12 • Fusion CCC/PLL Specification
Parameter
Min.
1.5
Typ.
Max.
350
Unit
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks1, 2
Number of Programmable Values in Each Programmable Delay Block
Input Period Jitter
0.75
350
200
32
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
24 MHz to 100 MHz
0.50%
1.00%
1.75%
2.50%
0.70%
1.20%
2.00%
5.60%
150
100 MHz to 250 MHz
250 MHz to 350 MHz
Acquisition Time
µs
%
ns
ns
ns
Output Duty Cycle
48.5
0.6
51.5
Delay Range in Block: Programmable Delay 1 1, 2
Delay Range in Block: Programmable Delay 2 1, 2
Delay Range in Block: Fixed Delay 1, 2
Notes:
5.56
0.025
5.56
2.2
1. This delay is a function of voltage and temperature. See Table 3-7 on page 3-7 for deratings.
2. TJ = 25°C, VCC = 1.5 V
2-28
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
No Glitch MUX (NGMUX)
Positioned downstream from the PLL/CCC blocks, the
NGMUX provides a special switching sequence between
two asynchronous clock domains that prevents generating
any unwanted narrow clock pulses. The NGMUX is used to
switch the source of a global between three different
clock sources. Allowable inputs are either two PLL/CCC
outputs or a PLL/CCC output and a regular net, as shown
in Figure 2-24. The GLMUXCFG[1:0] configuration bits
determine the source of the CLK inputs (i.e., internal
signal, GLA, or GLC). These are set by SmartGen during
design, but can also be changed by dynamically
reconfiguring the PLL. The GLMUXSEL[1:0] bits control
which clock source is passed through the NGMUX to the
global network (GL). See Table 2-13.
Crystal Oscillator
RC Oscillator
W I/O Ring
GLMUXCFG[1:0]
CCC/PLL
GLINT
To Clock Rib Driver
NGMUX
PLL/
CCC
GLA
GLC
GL
Clock I/Os
From FPGA Core
PWR UP
GLMUXSEL[1:0]
Figure 2-24 • NGMUX
Table 2-13 • NGMUX Configuration and Selection Table
GLMUXCFG[1:0]
GLMUXSEL[1:0]
Selected Input Signal
MUX Type
00
X
X
X
X
X
X
0
0
1
1
0
1
0
1
0
1
0
1
0
1
GLA
GLC
2-to-1 GLMUX
01
10
11
GLA
2-to-1 GLMUX
2-to-1 GLMUX
3-to-1 GLMUX
GLINT
GLC
GLINT
GLA
GLC
GLINT
GND
Advanced v0.7
2-29
Fusion Family of Mixed-Signal Flash FPGAs
The NGMUX macro is simplified to show the two clock options that have been selected by the GLMUXCFG[1:0] bits.
Figure 2-25 illustrates the NGMUX macro. During design, the two clock sources are connected to CLK0 and CLK1 and
are controlled by GLMUXSEL[1:0] to determine which signal is to be passed through the MUX.
CLK0
GL
CLK1
GLMUXSEL[1:0]
Figure 2-25 • NGMUX Macro
The sequence of switching between two clock sources (from CLK0 to CLK1) is as follows (Figure 2-26):
•
•
•
•
GLMUXSEL[1:0] transitions to initiate a switch.
GL drives one last complete CLK0 positive pulse (i.e., one rising edge followed by one falling edge).
From that point, GL stays low until the second rising edge of CLK1 occurs.
At the second CLK1 rising edge, GL will begin to continuously deliver CLK1 signal.
Minimum tsw = 0.05 ns at 25°C (typical conditions).
For examples of NGMUX operation, refer to the Peripherals User’s Guide.
tSW
CLK0
CLK1
GLMUXSEL[1:0]
GL
Figure 2-26 • NGMUX Waveform
2-30
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Real-Time Counter System
The addition of the RTC system enables Fusion devices to
support both standby and sleep modes of operation,
greatly reducing power consumption in many
applications.
•
•
•
Voltage regulator initialization
Voltage regulator logic
1.5 V voltage regulator
The RTC provides a counter as well as a MATCH output
signal that may be used in the FPGA and, optionally, to
power-up the on-chip 1.5 V voltage regulator and
provide a 1.5 V power source (in conjunction with an
external pass transistor) to the FPGA fabric portion of the
Fusion silicon device. The FPGA fabric can then be used
to power-down the 1.5 V voltage regulator.
The RTC system comprises six blocks that work together to
provide this increased functionality and reduced power
consumption. Figure 2-27 shows these blocks and how they
are connected.
•
•
•
RTC (Figure 2-28)
Crystal oscillator
VCC33UP detector
1.5 V FPGA Supply Input
FPGA Fabric
1.5/3.3 Volt Level Shift Circuitry
3.3 V
From
Core Flash
Bits
RTC
VR Logic
Crystal Oscillator
1.5 V Voltage
Regulator
MODE [1:0]
0
VR Init
ACM
External
RTCMATCH
Pass
PTBASE
FPGA_VRON
VRFPD
Flash Bits
VRINITSTATE
Transistor
RTCMODE [1:0]
EN
SELMODE
XTAL1
PTEM
PUB
RTCPSMMATCH
VRON
RTCPSMMATCH
1.5 V
Output
XTAL2
VRPU
CLKOUT
RTCCLK
VCC33UP
~ VRPSM
Power Up/Down
Toggle Control
Switch
Figure 2-27 • Real-Time Counter System
Analog Configuration MUX (ACM) Interface
Control/Status
Register
Main
Registers
40-Bit
7-Bit Pre-Scaler
(Crystal ÷ 128)
40-Bit
Read-Hold
Counter
Register
40-Bit Match
Register
Match
Bits
40 XNORs
Match
Figure 2-28 • RTC Block Diagram
Advanced v0.7
2-31
Fusion Family of Mixed-Signal Flash FPGAs
Real-Time Counter
The RTC can be configured to power up the FPGA fabric
at a specific time or periodically. Custom user logic or a
soft microcontroller within the FPGA fabric portion of
the Fusion device can be programmed to read and
modify the registers in the RTC. Based on this
information or other internal or external conditions, the
FPGA may decide to power down the voltage regulator
and thereby shut off the FPGA fabric.
over 136 years of elapsed timekeeping with a minimum
period of 1/256 second, which will be the toggle rate of
the LSB bit of the 40-bit counter.
Frequencies other than 32.768 kHz can be used as a clock
source, with the appropriate scaling of the LSB time
interval. Maximum input clock frequency is 20 MHz (the
crystal oscillator limit).
The RTC signals are included in the Analog Block macro.
The signal functions and descriptions are listed in
Table 2-14.
The 3.3 V supply must be valid and the crystal oscillator
(nominally 32.768 kHz) enabled for self-time wake-up/
restart operation. When operating from the 3.3 V supply
and the 1.5 V core voltage is disabled, the ACM interface
to the FPGA is disabled.
A Fusion use model includes the RTC controlling the
power-up state of the FPGA core via the 1.5 V regulator.
To support this model, the crystal oscillator must be
running and configured when the FPGA is powered off.
Hence, when the RTC is enabled in the system design, it
will configure the crystal oscillator via the
RTCXTLMODE[1:0] and RTCXTLSEL pins.
A 40-bit loadable counter is used as the primary
timekeeping element within the RTC. This counter can be
configured to reset itself when a count value is reached
that matches the value set within a 40-bit match register.
Note that the only exception to this self-clearing
mechanism occurs when the 40-bit counter is equal to 0
(0x0000000000), since the counter would never
increment from zero. When the device is first powered
up (i.e., when the 3.3 V supply becomes valid) the 40-bit
counter and 40-bit match register are cleared to logic 0,
and the MATCH output signal is active (logic 1). At any
time when the 40-bit counter value does not match the
value in the 40-bit match register, the MATCH output
signal will become inactive (logic 0).
A 7-bit pre-scaler block is used to divide the source clock
(from the external crystal) by 128. This pre-scaled 50%-
duty-cycle clock signal is then used by the counter logic
as its reference clock. Given an external crystal frequency
of 32.768 kHz, the pre-scaler output clock will toggle at a
rate of 32.768 kHz / 128 = 256 Hz.
The RTC is built from and controlled by a set of registers,
denoted "Main Registers" in Figure 2-27 on page 2-31.
These registers are accessed via the ACM.
The FPGA fabric portion of the Fusion device must be
powered up and active at least once to write to the
various registers within the RTC to initialize them for the
user’s application. Users set up the RTC by configuring it
from the Actel SmartGen tool implementing custom
logic, or programming a soft microcontroller.
Both the counter and match registers are addressable
(read/write) from the FPGA and through
a JTAG
instruction. The RTC is considered part of the analog
system and is accessed via ACM. Refer to the "Analog
Configuration MUX" section on page 2-89 for detailed
instructions on writing to the RTC via the ACM. The
counter action can be suspended/resumed by clearing/
setting the Cntr_En bit in the Control/Status Register.
The 40-bit counter and match register are each divided
into five bytes. Each byte is directly addressable by the
ACM. The address map of registers accessed through the
ACM and used by the RTC is shown in Table 2-15 on
page 2-33.
If a 32.768 kHz external crystal is connected to the crystal
oscillator pad, the 40-bit counter will have a maximum
count of 4,294,967,296 seconds, which equates to just
Table 2-14 • RTC Macro Signal Description
Signal Name
RTCMATCH
Number of Bits
Direction
Out
Function
1
1
Match between 40-bit counter and match register
RTCPSMMATCH
Out
RTCMATCH connected to voltage regulator power supply
monitor (VRPSM) (Figure 2-30 on page 2-36)
RTCXTLMODE[1:0]
RTCXTLSEL
2
1
1
Out
Out
In
Drives XTLOSC RTCMODE[1:0] pins
Drives XTLOSC SELMODE pin
RTCCLK
RTC clock input from XTLOSC CLKOUT pin
2-32
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-15 • RTC ACM Memory Map
ACM_ADDR[7:0]
0x40
Decimal
64
Register Name
COUNTER0
Description
Counter bits 7:0
Use
Used to preload the counter to a
specified start point. Default setting is
all zeroes.
0x41
65
COUNTER1
Counter bits 15:8
0x42
66
COUNTER2
Counter bits 23:16
0x43
67
COUNTER3
Counter bits 31:24
0x44
68
COUNTER4
Counter bits 39:32
0x48
72
MATCHREG0
MATCHREG1
MATCHREG2
MATCHREG3
MATCHREG4
MATCHBITS0
MATCHBITS1
MATCHBITS2
MATCHBITS3
MATCHBITS4
CTRL_STAT
Match register bits 7:0
Match register bits 15:8
Match register bits 23:16
Match register bits 31:24
Match register bits 39:32
Individual Match bits 7:0
Individual Match bits 15:8
Individual Match bits 23:16
Individual Match bits 31:24
Individual Match bits 39:32
The RTC uses a 40-bit register to
compare against the 40-bit counter
value to determine when a match
occurs. This 40-bit match register, like
the counter, is broken into 5 bytes
(MATCHREG0–4).
0x49
73
0x4a
74
0x4b
75
0x4c
76
0x50
80
Each bit of the 40-bit counter is
compared to each bit of the 40-bit
match register via XNOR gates. These
40 match bits are partitioned into 5
bytes.
0x51
81
0x52
82
0x53
83
0x54
84
0x58
88
Control (write) / Status (read) register Control (write) / Status (read) register
bits 7:0
bits 7:0
0x59
89
TEST_REG
Test register(s)
Test register(s)
Advanced v0.7
2-33
Fusion Family of Mixed-Signal Flash FPGAs
The control/status register (CTRL_STAT) is an 8-bit
register that defines the operation of the RTC. The
control register can reset the RTC, enabling operation to
begin with all zeroes in the counter. The RTC can be
configured to clear upon a match with the Match
register, or it can continue to count while still setting the
match signal. To enable the Fusion device to power up at
a specific time or at periodic intervals, the RTC can be
configured to turn on the 1.5 V voltage regulator.
Table 2-16 details the CTRL_STAT settings.
Table 2-16 • RTC Control/Status Register
Bit
Name
Description
7
rtc_rst
RTC Reset: Writing a logic 1 to this bit causes an RTC reset.2 Writing a logic 0 to this bit will allow
synchronous deassertion of reset after 2 ACM_CLK cycles if VCC33UP = 1.3
6
cntr_en
Counter Enable: A logic 1 in this bit will enable the counter if the RTC is not in reset.
It takes 64 RTCCLK positive edges (1/2 of the pre-scaler division factor), after reset is removed and
cntr_en = 1, before the counter is incremented.4
A logic 0 in this bit resets the pre-scaler and therefore suspends incrementing the counter, but the
counter is not reset.
Before writing to the counter registers, the counter must be disabled.
5
vr_en_mat
Voltage Regulator Enable on Match: Writing a logic 1 to this bit will allow the RTCMATCH output port
to go to logic 1 when a match occurs between the 40-bit counter and the 40-bit match register.
Logic 0 forces RTCMATCH to logic 0, to prevent enabling the voltage regulator from the RTC.
4:3
xt_mode[1:0]
Crystal Oscillator Mode: These bits control the RTCXTLMODE[1:0] output ports that are connected to
the RTCMODE[1:0] input pins of the crystal oscillator pad. For 32 kHz crystal operation, this should be
set to '01'.
(See the "Crystal Oscillator" section on page 2-20.)
2
rst_cnt_omat
Reset Counter on Match: A logic 1 written to this bit allows the counter to clear itself when a match
occurs. In this situation, the 40-bit counter clears on the next rising edge of the pre-scaled clock,
approximately 4 ms after the match occurs (the pre-scaled clock toggles at a rate of 256 Hz, given a
32.768 kHz external crystal).
A logic 0 written to this bit allows the counter to increment indefinitely, while still allowing match
events to occur.
1
0
rstb_cnt
xtal_en
Counter Reset: A logic 0 resets the 40-bit counter value to 0. A logic 1 allows the counter to count.4
Crystal Oscillator Enable: This bit controls the RTCXTLSEL output port that is connected to the
SELMODE input pin of the crystal oscillator. If a logic 0 is written to this bit, only the FPGA fabric can be
used to control the crystal oscillator EN and MODE[1:0] inputs.
xtal_en = ‘1’: RTC takes control of XTAL oscillator. For example, RTC Mode bits configure the XTAL
oscillator (not the FPGA mode bits).
To enable sleep mode: set xtal_en = ‘0’, so the crystal is controlled from the FPGA EN signal then, when
the FPGA is powered down, the from the FPGA will be 0 EN, disabling the crystal oscillator.
Notes:
1. Default state (set when VCC33UP = 0) for bits 0–7 is logic 0.
2. Reset of all RTC states (except this Control/Status register) occurs asynchronously if VCC33UP = 0 or CTRL_STAT bit 7 (rtc_rst) is set to 1.
3. Reset is removed synchronously after 2 rising edges of ACM_CLK, following both VCC33UP = 1 and rtc_rst = 0.
4. Counter will first increment on the 64th rising edge of RTCCLK after all of the following are true:
a. reset is removed
b. rstb_cnt (CTRL_STAT bit 1) is set to 1
c. cntr_en (CTRL_STAT bit 6) is set to 1
and will then increment every 128 RTCCLK cycles.
2-34
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Crystal Oscillator (Xtal Osc)
Voltage Regulator (VR) Logic
When used as the clock source for the RTC, the crystal
oscillator will be configured by the RTC with the
RTCXTLMODE[1:0] RTC macro pins. Refer to the "Crystal
Oscillator" section on page 2-20 for specific details on
crystal oscillator operation.
The Voltage Regulator Logic block, along with the VR,
combines commands from the FPGA, RTC, VR Init block,
VCC33UP detector, and PUB pad, to determine whether or
not the VR is enabled.
The VR can be enabled from several sources: the PUB pin,
the RTC_MATCH signal from the RTC block, or triggered
by the VR Init block. Once triggered, the VR will remain
on. Only the FPGA fabric can disable the VR, unless the
VCC33A supply falls below the VCC33UP threshold and a
reset occurs.
The crystal oscillator input to the RTC is divided by 128, so
bit 0 of the RTC toggles at the frequency of the crystal
oscillator divided by 128. The frequencies of the RTC are
gated by those of the crystal oscillator; from 32.768 kHz to
20 MHz. When used with a 32.768 kHz crystal, bit 0 of the
of RTC has a period of ~7.8 ms, and bit 7 has a period of 1
second.
1.5 V Voltage Regulator
The VR generates a 1.5 V power supply from the 3.3 V
power supply. The 1.5 V output is intended to supply all
1.5 V needs of the Fusion device. This regulator requires
an external bipolar pass transistor(Figure 2-29). The VR
can drive up to 20 mA of current through the PTBASE
pad. The amount of 1.5 V current available is dependent
upon the gain of the external pass transistor used.
Enable for this block is generated in the VR Logic block
or from the PUB pin.
Voltage Regulator Initialization (VR Init)
The VR Init block determines voltage regulator behavior
when the 3.3 V supply is valid. The Fusion devices
support different use models. Some of these require the
1.5 V voltage regulator to turn on when the 3.3 V supply
is stable. Other use models require additional conditions
to be met before the 1.5 V VR turns on. Since the FPGA is
not operating when the 3.3 V supply is off, the VR Init
lets the user define VR behavior at design time. Two bits
can be set within the core, which the VR Init will read as
it comes out of reset and either turn on the VR or leave it
in an off state.
The 1.5 V is not supplied internally to the Fusion device.
It must be routed externally to the VCC pins on the
device. Therefore the user is not required to use the VR
and can use an off-chip 1.5 V supply if desired.
On-Chip Off-Chip
VCC33A
VCC33A
RTC
FPGA
PTBASE
PTEM
1.5 V
Regulator
1.5 V Out
PDVR
VCC33A
1 µA
PUB
Power-Up/Down Control Circuit
Figure 2-29 • Voltage Regulator
Advanced v0.7
2-35
Fusion Family of Mixed-Signal Flash FPGAs
Voltage Regulator Power Supply Monitor (VRPSM)
As the functions of the VR Logic and Power System
Monitor work closely together to control the power-up
state of the FPGA core, these functions were combined
into a single VRPSM macro (Figure 2-30).
The signals for the VRPSM macro are listed in Table 2-17.
The PUB input comes from the PUB pin on the device and
can be pulled low by a signal external to the Fusion
device. This can be used to wake up the device. The
inputs VRINITSTATE and RTCPSMMTACH come from the
VR Init and RTC blocks, respectively, and either can
initiate a VR power-up.
PUB
FPGAGOOD
PUCORE
VRPU
VRINITSTATE
RTCPSMMATCH
Figure 2-30 • VRPSM Macro
Table 2-17 • Signals for VRPSM Macro
Signal Name
Number of Bits
Direction
Function
PUB
1
Input
Active low signal to power up the FPGA core via the 1.5 V
regulator.
In this reference design, PUB is on the top level connected to an
external switch.
VRPU
1
1
Input
Input
When this pin is at logic '1', the FPGA core will be turned off via
the voltage regulator.
VRINITSTATE
This feature is not used in this reference design and is not shown
in the macro generated by SmartGen. If used, the signal enables
you to set your voltage regulator output at power-up (ON or
OFF).
RTCPSMMATCH
1
Input
This feature is not used in this reference design. If used, this
active high signal is driven by the RTC’s match signal to indicate
that the RTC counter value matches with the pre-defined Match
Register value set in SmartGen.
FPGAGOOD
PUCORE
1
1
Output
Output
Logic '1' indicates that FPGA is logically functional.
Logic '1' indicates that FPGA is logically functional.
2-36
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Embedded Memories
Fusion devices include four types of embedded memory: Flash block, FlashROM, SRAM, and FIFO.
Flash Memory Block
Fusion is the first FPGA that offers a Flash memory block (FB). Each FB block stores 2 Mbits of data. The Flash memory
block macro is illustrated in Figure 2-31. The port pin name and descriptions are detailed on Table 2-18 on page 2-38.
All Flash memory block signals are active high, except for CLK and active low RESET. All Flash memory operations are
synchronous to the rising edge of CLK.
ADDR[17:0]
WD[31:0]
RD[31:0]
BUSY
STATUS[1:0]
DATAWIDTH[1:0]
REN
READNEXT
PAGESTATUS
WEN
ERASEPAGE
PROGRAM
SPAREPAGE
AUXBLOCK
UNPROTECTPAGE
OVERWRITEPAGE
DISCARDPAGE
OVERWRITEPROTECT
PAGELOSSPROTECT
PIPE
LOCKREQUEST
CLK
RESET
Figure 2-31 • Flash Memory Block
Advanced v0.7
2-37
Fusion Family of Mixed-Signal Flash FPGAs
Flash Memory Block Pin Names
Table 2-18 • Flash Memory Block Pin Names
Interface Name Width
Direction
Description
Byte offset into the FB. Byte based address.
ADDR[17:0]
AUXBLOCK
18
1
In
In
When asserted, the page addressed is used to access the auxiliary block within that
page.
BUSY
CLK
1
1
Out
In
When asserted, indicates that the FB is performing an operation.
User interface clock. All operations and status are synchronous to the rising edge of this
clock.
DATAWIDTH[1:0]
2
In
Data width
00 = 1 byte in RD/WD[7:0]
01 = 2 bytes in RD/WD[15:0]
1x = 4 bytes in RD/WD[31:0]
DISCARDPAGE
ERASEPAGE
1
1
1
1
1
In
In
In
In
In
When asserted, the contents of the Page Buffer are discarded so that a new page write
can be started.
When asserted, the contents of the Page Buffer are discarded so that a new page write
can be started.
LOCKREQUEST
OVERWRITEPAGE
When asserted, indicates to the JTAG controller that the FPGA interface is accessing the
FB.
When asserted, the page addressed is overwritten with the contents of the Page Buffer
if the page is writable.
OVERWRITEPROTEC
T
When asserted, all program operations will set the overwrite protect bit of the page
being programmed.
PAGESTATUS
1
1
In
In
When asserted with REN, initiates a read page status operation.
PAGELOSSPROTECT
When asserted, a modified Page Buffer must be programmed or discarded before
accessing a new page.
PIPE
1
1
In
In
Adds a pipeline stage to the output for operation above 50 MHz.
PROGRAM
RD[31:0]
When asserted, writes the contents of the Page Buffer into the FB page addressed.
32
Out
Read data; data will be valid from the first non-busy cycle (BUSY=0) after REN has been
asserted.
READNEXT
REN
1
1
1
1
In
In
In
In
When asserted with REN, initiates a read-next operation.
When asserted, initiates a read operation.
RESET
When asserted, resets the state of the FB (active low).
SPAREPAGE
When asserted, the sector addressed is used to access the spare page within that
sector.
STATUS[1:0]
2
Out
Status of the last operation completed:
00: Successful completion
01: Read/Unprotect-Page: single error detected and corrected
Write: operation addressed a write-protected page
Erase-Page: protection violation
Program: Page Buffer is unmodified
Protection violation
10: Read/Unprotect-Page: two or more errors detected
11: Write: attempt to write to another page before programming current page
Erase-Page/Program: page write count has exceeded the 10-year retention
threshold
UNPROTECTPAGE
1
In
When asserted, the page addressed is copied into the Page Buffer and the Page Buffer
is made writable.
WD[31:0]
WEN
32
1
In
In
Write data
When asserted, store WD in the page buffer.
2-38
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
All Flash memory block input signals are active high, except for RESET.
Flash Memory Block Diagram
A simplified diagram of the Flash memory block is shown in Figure 2-32.
Output
MUX
ECC
Logic
Flash Array = 64 Sectors
Page Buffer = 8 Blocks
RD[31:0]
Plus AUX Block
Block Buffer
(128 Bits)
WD[31 :0]
ADDDR[17:0]
DATAWIDTH[1:0]
REN
READNEXT
PAGESTATUS
WEN
ERASEPAGE
PROGRAM
SPAREPAGE
AUXBLOCK
UNPROTECTPAGE
OVERWRITEPAGE
DISCARDPAGE
OVERWRITEPROTECT
PAGELOSSPROTECT
PIPE
Control
Logic
LOCKREQUEST
CLK
RESET
STATUS[1:0]
BUSY
Figure 2-32 • Flash Memory Block Diagram
The logic consists of the following sub-blocks:
•
•
•
•
Flash Array
Contains all stored data. The Flash array contains 64 sectors, and each sector contains 33 pages of data.
Page Buffer
Is a page-wide volatile register. A page contains 8 blocks of data and an AUX block.
Block Buffer
Contains the contents of the last block accessed. A block contains 128 data bits.
ECC Logic
The FB stores error correction information with each block to perform single-bit error correction and double-bit
error detection on all data blocks.
Advanced v0.7
2-39
Fusion Family of Mixed-Signal Flash FPGAs
Flash Memory Block Addressing
Figure 2-33 shows a graphical representation of the Flash memory block.
Spare Page
Page 31
.
ages
. . .
33 P
n
r
o
t
c
Se
Page 3
Page 2
Page 1
Page 0
1
0
r
r
o
t
t
c
c
Se
o
Se
1190
140
Block
0
1
2
3
4
5
6
7
Notes:
1 block = 128 bits
1 page = 8 blocks plus the AUX block
1 sector = 33 pages
Block Organization
1 Flash array = 64 sectors
Figure 2-33 • Flash Memory Block Organization
Each FB is partitioned into sectors, pages, blocks, and bytes. There are 64 sectors in an FB, and each sector contains 32
pages and 1 spare page. Each page contains 8 data blocks and 1 auxiliary block. Each data block contains 16 bytes of
user data, and the auxiliary block contains 4 bytes of user data.
Addressing for the FB is shown in Table 2-19.
Table 2-19 • FB Address Bit Allocation ADDR[17:0]
17
12
11
7
6
4
3
0
Sector
Page
Block
Byte
2-40
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
When the spare page of
(SPAREPAGE active), ADDR[11:7] are ignored.
a sector is addressed
LOCKREQUEST
The LOCKREQUEST signal is used to give the user
interface control over simultaneous access of the FB from
both the User and JTAG interfaces. When LOCKREQUEST
is asserted, the JTAG interface will hold off any access
attempts until LOCKREQUEST is deasserted.
When the Auxiliary block is addressed (AUXBLOCK
active), ADDR[6:2] are ignored.
Note: The spare page of sector 0 is unavailable for any
user data. Writes to this page will return an error, and
reads will return all zeroes.
Flash Memory Block Operations
Data operations are performed in widths of 1 to 4 bytes.
A write to a location in a page that is not already in the
Page Buffer will cause the page to be read from the FB
Array and stored in the Page Buffer. The block that was
addressed during the write will be put into the Block
Buffer and the data written by WD will overwrite the
data in the Block Buffer. After the data is written to the
Block Buffer, the Block Buffer is then written to the Page
Buffer to keep both buffers in sync. Subsequent writes to
the same block will overwrite the Block Buffer and the
Page Buffer. A write to another block in the page will
cause the addressed block to be loaded from the Page
Buffer, and the write will be performed as described
previously.
FB Operation Priority
The FB provides for priority of operations when multiple
actions are requested simultaneously. Table 2-21 shows
the priority order (priority 0 is the highest).
Table 2-21 • FB Operation Priority
Operation
System initialization
FB reset
Priority
0
1
2
3
4
5
6
7
Read
Write
Erase page
Program
The data width can be selected dynamically via the
DATAWIDTH input bus. The truth table for the data
width settings is detailed in Table 2-20. The minimum
resolvable address is one 8-bit byte. For data widths
greater than 8 bits, the corresponding address bits are
ignored (when DATAWIDTH = 0 (2 bytes), ADDR[0] is
ignored and when DATAWIDTH = 10 or 11 (4 bytes),
ADDR[1:0] is ignored). Data pins are LSB-oriented and
unused WD data pins must be grounded.
Unprotect page
Discard page
Access to the FB is controlled by the BUSY signal. The
BUSY output is synchronous to the CLK signal. FB
operations are only accepted in cycles where BUSY is
logic 0.
Write Operation
Table 2-20 • Data Width Settings
Write operations are initiated with the assertion of the
WEN signal. Figure 2-34 on page 2-42 illustrates the
multiple write operations.
DATAWIDTH[1:0]
Data Width
1 byte [7:0]
00
When a write operation is initiated to a page that is
currently not in the Page Buffer, the FB control logic will
issue a BUSY signal to the user interface while the page is
loaded from the FB Array into the Page Buffer. (Note:
The number of clock cycles that the BUSY output is
asserted during the load of the Page Buffer is variable.)
After loading the page to the Page Buffer, the addressed
data block is loaded from the Page Buffer into the Block
Buffer. Subsequent writes to the same block of the page
will incur no busy cycles. A write to another block in the
page will assert BUSY for four cycles (five cycles when
PIPE is asserted), to allow the data to be written to the
Page Buffer and have the current block loaded into the
Block Buffer.
01
2 byte [15:0]
4 bytes [31:0]
10, 11
Flash Memory Block Protection
Page Loss Protection
When the PAGELOSSPROTECT pin is set to logic 1, it
prevents writes to any other page except the current
page in the Page Buffer, until the page is either
discarded or programmed.
A write to another page while the current page is page
loss protected will return a STATUS of '11'.
Overwrite Protection
Any page that is overwrite protected will result in the
STATUS being set to '01' when an attempt is made to
either write, program, or erase it. To set the Overwrite
Protection state for a page, set the OVERWRITEPROTECT
pin when a program operation is undertaken. To clear
the Overwrite Protect state for a given page, an
Unprotect Page operation must be performed on the
page, and then the page must be programmed with the
OVERWRITEPROTECT pin cleared to save the new page.
Write operations are considered successful as long as the
STATUS output is '00'. A non-zero STATUS indicates an
error was detected during the operation and the write
was not performed. Note that the STATUS output is
"sticky;" it is unchanged until another operation is
started.
Advanced v0.7
2-41
Fusion Family of Mixed-Signal Flash FPGAs
CLK
WEN
A0
D0
A1
D1
A2
A3 A4
A5
D5
A6
D6
ADDR[17:0]
WD[31:0]
D2 D3 D4
DATAWIDTH[1:0]
PAGELOSSPROTECT
BUSY
STATUS[1:0]
S0
S1
S2
S3
S4
S5
S6
Figure 2-34 • FB Write Waveform
Only one word can be written at a time. Write word
width is controlled by the DATAWIDTH bus. Users are
responsible for keeping track of the contents of the Page
Buffer and when to program it to the array. Just like a
regular RAM, writing to random addresses is possible.
Users can write into the Page Buffer in any order, but will
incur additional BUSY cycles. It is not necessary to modify
the entire Page Buffer before saving it to nonvolatile
memory.
During a Program operation, the sector and page
addresses on ADDR are compared with the stored
address for the page (and sector) in the Page Buffer. If
there is a mismatch between the two addresses, the
program operation will be aborted and an error will be
reported on the STATUS output.
It is possible to write the Page Buffer to a different page
in memory. When asserting the PROGRAM pin, if
OVERWRITEPAGE is asserted as well, the FB will write the
contents of the Page Buffer to the sector and page
designated on the ADDR inputs, if the destination page
is not overwrite protected.
Write errors include the following:
1. Attempting to write a page that is Overwrite
Protected (STATUS
performed.
= 01). The write is not
A program operation may be utilized to either modify
the contents of the page in the Flash memory block or
change the protections for the page. Setting the
OVERWRITEPROTECT bit on the interface while asserting
the PROGRAM pin will put the page addressed into
Overwrite Protect Mode. Overwrite Protect Mode
safeguards a page from being inadvertently overwritten
during subsequent program or erase operations.
2. Attempting to write to a page that is not in the
Page Buffer when Page Loss Protection is enabled
(STATUS = 11). The write is not performed.
Program Operation
A program operation is initiated by asserting the
PROGRAM signal on the interface. Program operations
save the contents of the Page Buffer to the FB Array. Due
to the technologies inherent in the FB, a program
operation is a time consuming operation (~8 ms). While
the FB is writing the data to the array, the BUSY signal
will be asserted.
2-42
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Program operations that result in a STATUS value of '01'
do not modify the addressed page. For all other values of
STATUS, the addressed page is modified.
4. The Write Count of the page programmed
exceeding the Write Threshold defined in the part
specification (STATUS = 11)
Program errors include the following:
5. The ECC Logic determining that there is an
uncorrectable error within the programmed page
(STATUS = 10)
1. Attempting to program a page that is Overwrite
Protected (STATUS = 01)
6. Attempting to program to a page that is not in
the Page Buffer when OVERWRITEPAGE is not set
and the page in the Page Buffer is modified
(STATUS = 01)
2. Attempting to program to a page that is not in
the Page Buffer when the Page Buffer has entered
Page Loss Protection mode (STATUS = 01)
3. Attempting to perform
a
program with
7. Attempting to program the page that is in the
Page Buffer when the Page Buffer is not
modified.
OVERWRITEPAGE set when the page addressed
has been Overwrite Protected (STATUS = 01)
The waveform for a program operation is shown in
Figure 2-35.
CLK
PROGRAM
Page
ADDR[17:0]
OVERWRITEPAGE
OVERWRITEPROTECT
PAGELOSSPROTECT
BUSY
0
Valid
STATUS[1:0]
Figure 2-35 • FB Program Waveform
Advanced v0.7
2-43
Fusion Family of Mixed-Signal Flash FPGAs
Note: OVERWRITEPAGE is only sampled when the
A waveform for an Erase Page operation is shown in
Figure 2-36.
PROGRAM
or
ERASEPAGE
pins
are
asserted.
OVERWRITEPAGE is ignored in all other operations.
Erase errors include the following:
Erase Page Operation
1. Attempting to erase a page that is Overwrite
Protected (STATUS = 01)
The Erase Page operation is initiated when the
ERASEPAGE pin is asserted. The Erase Page operation
allows the user to erase (set user data to '0') any page
within the FB.
2. Attempting to erase a page that is not in the Page
Buffer when the Page Buffer has entered Page
Loss Protection mode (STATUS = 01)
The use of the OVERWRITEPAGE and PAGELOSSPROTECT
pins is the same for erase as for a Program Page
operation.
3. The Write Count of the erased page exceeding the
Write Threshold defined in the part specification
(STATUS = 11)
As with the Program Page operation, a STATUS of '01'
indicates that the addressed page is not erased.
4. The ECC Logic determining that there is an
uncorrectable error within the erased page
(STATUS = 10)
CLK
ERASE
Page
ADDR[17:0]
OVERWRITEPROTECT
PAGELOSSPROTECT
BUSY
STATUS[1:0]
Valid
Figure 2-36 • FB Erase Page Waveform
2-44
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Read Operation
Read operations are designed to read data from the FB
Array, Page Buffer, Block Buffer or status registers. Read
operations support a normal read and a read-ahead
mode (done by asserting READNEXT). Also, the timing
for Read operations is dependent on the setting of PIPE.
The following diagrams illustrate representative timing
for Non-Pipe Mode (Figure 2-37) and Pipe Mode
(Figure 2-38) reads of the Flash memory block interface.
CLK
REN
A0
A1
A2
A3
A4
ADDR[17:0]
DATAWIDTH[1:0]
BUSY
0
0
S0
S1
S2
S3
0
0
S4
STATUS[1:0]
RD[31:0]
D0 D1 D2
D3
D4
0
Figure 2-37 • Read Waveform (Non-Pipe Mode, 32-Bit Access)
CLK
REN
A0
A1
A2
A3
A4
ADDR[17:0]
DATAWIDTH[1:0]
BUSY
0
0
S0
S1
S2
S3
0
S4
D4
STATUS[1:0]
RD[31:0]
D0 D1 S2
D3
0
X
0
Figure 2-38 • Read Waveform (Pipe Mode, 32-Bit Access)
Advanced v0.7
2-45
Fusion Family of Mixed-Signal Flash FPGAs
The following error indications are possible for Read
operations:
In addition to data reads, users can read the status of any
page in the FB by asserting PAGESTATUS along with REN.
The format of the data returned by a page status read is
shown in Table 2-22, and the definition of the page
status bits is shown in Table 2-23.
1. STATUS = 01 when a single-bit data error was
detected and corrected within the block
addressed.
2. STATUS = 10 when a double-bit error was detected
in the block addressed (note that the error is
uncorrected).
Table 2-22 • Page Status Read Data Format
31
8
7
4
3
2
1
0
Write Count
Reserved
Over Threshold Read Protected Write Protected Overwrite Protected
Table 2-23 • Page Status Bit Definition
Page Status Bits
Bit Definition
31–8
7–4
3
The number of times the page addressed has been programmed/erased
Reserved; read as 0
Over threshold indicator (see the"Program Operation" section on page 2-42)
Read protected; read protect bit for page which is set via the JTAG interface
Write protected; write protect bit for page which is set via the JTAG interface
2
1
0
Overwrite protected; designates that the user has set the OVERWRITEPROTECT bit on the interface while doing
a program operation. The page cannot be written without first performing an Unprotect Page operation.
2-46
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Read Next Operation
The Read Next operation is a feature by which the next
block relative to the block in the Block Buffer is read
from the FB Array while performing reads from the Block
Buffer. The goal is to minimize wait states during
consecutive sequential read operations.
•
•
Reads of the last sector will wrap around to sector 0.
Reads of Auxiliary blocks will read the next linear
page's Auxiliary block.
When an address on the ADDR input does not agree
with the predetermined look-ahead address, there is a
time penalty for this access. The FB will be busy finishing
the current look-ahead read before it can start the next
read. The worst case is a total of nine BUSY cycles before
data is delivered.
The Read Next operation is performed in
a
predetermined manner because it does look-ahead
reads. The general look-ahead function is as follows:
•
•
•
Within a page, the next block fetched will be the
next in the linear address.
The Non-Pipe Mode and Pipe Mode waveforms for Read
Next operations are illustrated in Figure 2-39 and
Figure 2-40.
When reading the last data block of a page, it will
fetch the first block of the next page.
When reading spare pages, it will read the first
block of the next sector's spare page.
CLK
REN
READNEXT
ADDR[17:0]
A0
A1
A2
A3
A4
A5
S4
A6
A7
A8
A9
DATAWIDTH[1:0]
BUSY
STATUS[1:0]
RD[31:0]
0
0
S0
S1
S2
S3
0
0
S5
S6
S7
0
0
S8 S9
D8 D9
D0 D1 D2 D3
D4 D5 D6 D7
Figure 2-39 • Read Next Waveform (Non-Pipe Mode, 32-Bit Access)
CLK
REN
READNEXT
A0
A1
A2
A3
A4
A5
A6
A7
A8
ADDR[17:0]
BUSY
S0
S1
D1
S2
D2
S3
D3
0
0
S4
D4
S5
D5
S6
D6
S7
0
0
STATUS[1:0]
RD[31:0]
0
D0
D7
Figure 2-40 • Read Next WaveForm (Pipe Mode, 32-Bit Access)
Advanced v0.7
2-47
Fusion Family of Mixed-Signal Flash FPGAs
Unprotect Page Operation
An Unprotect Page operation will clear the protection
for a page addressed on the ADDR input. It is initiated by
setting the UNPROTECTPAGE signal on the interface
along with the page address on ADDR.
If the page is not in the Page Buffer, the Unprotect Page
operation will copy the page into the Page Buffer. The
copy page operation occurs only if the current page in
the Page Buffer is not Page Loss Protected.
The waveform for an Unprotect Page operation is shown
in Figure 2-41.
CLK
UNPROTECTPAGE
Page
ADDR[17:0]
BUSY
STATUS[1:0]
Valid
Figure 2-41 • FB Unprotected Page Waveform
The Unprotect Page operation can incur the following
error conditions:
3. If the copy of the page to the Page Buffer
determines that at least one block in the page has a
double-bit uncorrectable error, then STATUS = 10
and the Page Buffer will contain the corrupted data.
1. If the copy of the page to the Page Buffer
determines that the page has
a single-bit
correctable error in the data, it will report a
STATUS = 01.
Discard Page Operation
If the contents of the modified Page Buffer have to be
discarded, the DISCARDPAGE signal should be asserted.
This command results in the Page Buffer being marked as
unmodified.
2. If the address on ADDR does not match the
address of the Page Buffer, PAGELOSSPROTECT is
asserted, and the Page Buffer has been modified,
then the STATUS = 11 and the addressed page is
not loaded into the Page Buffer.
The timing for the operation is shown in Figure 2-42. The
BUSY signal will remain asserted until the operation has
completed.
CLK
DISCARDPAGE
BUSY
Figure 2-42 • FB Discard Page Waveform
2-48
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Flash Memory Block Characteristics
CLK
RESET
Active Low, Asynchronous
BUSY
Figure 2-43 • Reset Timing Diagram
Table 2-24 • Flash Memory Block Timing
Commercial-Case Conditions: TJ = 25°C, Typical Case, VCC = 1.5 V
Parameter
tCLKQ5CYC
tCLKQ6CYC
tDSUNVM
Description
Min.
Typ.
7.5
Max.
Units
ns
Clock-to-Q in 5-cycle read mode of the Control Logic
Clock-to-Q in 6-cycle read mode of the Control Logic
Data Input Setup time for the Control Logic
2.3
ns
1.5
0
ns
tDHNVM
Data Input Hold time for the Control Logic
ns
tASUNVM
Address Input Setup time for the Control Logic
Address Input Hold time for the Control Logic
Asynchronous Reset Minimum Pulse Width for the Control Logic
Clock Minimum Pulse Width for the Control Logic
4.9
0
ns
tAHNVM
ns
tMPWARNVM
tMPWCLKNVM
10
5
ns
ns
Advanced v0.7
2-49
Fusion Family of Mixed-Signal Flash FPGAs
FlashROM
Fusion devices have 1 kbit of on-chip nonvolatile Flash
memory that can be read from the FPGA core fabric. The
FlashROM is arranged in 8 banks of 128 bits during
programming. The 128 bits in each bank are addressable
as 16 bytes during the read back of the FlashROM from
the FPGA core (Figure 2-44).
The maximum FlashROM access clock is 20 MHz. Figure 2-45
shows the timing behavior of FlashROM access cycle— the
address has to be setup on the rising edge of clock for DOUT
to be valid on the next clock falling edge.
If the address is unchanged for 2 cycles:
•
D0 becomes invalid 10 ns after the second rising
edge of clock
The FlashROM can only be programmed via the IEEE
1532 JTAG port. It cannot be programmed directly from
the FPGA core. When programming, each of the 8
128-bit banks can be selectively reprogrammed. The
FlashROM can only be reprogrammed on a bank
boundary. Programming involves an automatic, on-chip
bank erase prior to reprogramming the bank. The
FlashROM supports a synchronous read and can be read
on byte boundaries. The upper 3 bits of the FlashROM
address from the FPGA core define the bank that is being
accessed. The lower 4 bits of the FlashROM address from
the FPGA core define which of the 16 bytes in the bank is
being accessed.
•
D0 becomes valid again 10 ns after second falling
edge
If the address unchanged for 3 cycles:
•
•
•
•
D0 becomes invalid 10 ns after the second rising
edge of clock
D0 becomes valid again 10 ns after second falling
edge
D0 becomes invalid 10 ns after the third rising
edge of clock
D0 becomes valid again 10 ns after third falling
edge
Byte Number in Bank
4 LSB of ADDR (READ)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 2-44 • FlashROM Architecture
FlashROM Characteristics
t
t
t
SU
SU
SU
CLK
t
t
t
HOLD
HOLD
HOLD
Address
Data
A0
A1
10 ns
10 ns
10 ns
D1
D0
D0
Figure 2-45 • FlashROM Timing Diagram
2-50
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
SRAM and FIFO
All Fusion devices have SRAM blocks along the north side
of the device. Additionally, AFS600 and AFS1500 devices
have an SRAM block on the south side of the device. To
meet the needs of high-performance designs, the
memory blocks operate strictly in synchronous mode for
both read and write operations. The read and write
clocks are completely independent, and each may
operate at any desired frequency less than or equal to
350 MHz.
The Fusion architecture enables the read and write sizes
of RAMs to be organized independently, allowing for
bus conversion. This is done with the WW (write width)
and RW (read width) pins. The different D×W
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1.
For example, the write size can be set to 256×18 and the
read size to 512×9.
Both the write and read widths for the RAM blocks can
be specified independently with the WW (write width)
and RW (read width) pins. The different DxW
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1.
•
•
•
4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—two
read, two write or one read, one write)
512×9, 256×18 (two-port RAM—one read and one
write)
Refer to the allowable RW and WW values supported for
each of the RAM macro types in Table 2-25 on page 2-53.
Sync write, sync pipelined/nonpipelined read
When widths of one, two, or four are selected, the ninth
bit is unused. For example, when writing nine-bit values
and reading four-bit values, only the first four bits and
the second four bits of each nine-bit value are
addressable for read operations. The ninth bit is not
accessible.
The Fusion SRAM memory block includes dedicated FIFO
control logic to generate internal addresses and external
flag logic (Full, Empty, AFULL, AEMPTY).
During RAM operation, addresses are sourced by the
user logic and the FIFO controller is ignored. In FIFO
mode, the internal addresses are generated by the FIFO
controller and routed to the RAM array by internal
MUXes. Refer to Figure 2-46 for more information about
the implementation of the embedded FIFO controller.
Conversely, when writing four-bit values and reading
nine-bit values, the ninth bit of a read operation will be
undefined. The RAM blocks employ Little Endian byte
order for read and write operations.
RD
RD[17:0]
WD[17:0]
RCLK
WD
RCLK
WCLK
WCLK
RAM
RADD[J:0]
WADD[J:0]
REN
WEN
FREN
FWEN
CNT 12
E
RBLK
REN
=
FULL
ESTOP
AFVAL
AFULL
AEVAL
AEMPTY
EMPTY
CNT 12
E
SUB 12
WBLK
WEN
=
FSTOP
Reset
Figure 2-46 • Fusion RAM Block with Embedded FIFO Controller
Advanced v0.7
2-51
Fusion Family of Mixed-Signal Flash FPGAs
RAM4K9 Description
RAM4K9
ADDRA11 DOUTA8
DOUTA7
ADDRA10
DOUTA0
ADDRA0
DINA8
DINA7
DINA0
WIDTHA1
WIDTHA0
PIPEA
WMODEA
BLKA
WENA
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
ADDRB0
DOUTB0
DINB8
DINB7
DINB0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
RESET
Figure 2-47 • RAM4K9
2-52
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
The following signals are used to configure the RAM4K9
memory element:
RESET
This active low signal resets the output to zero and
disables reads and/or writes from the SRAM block as well
as clears the data hold registers when asserted. It does
not reset the contents of the memory.
WIDTHA and WIDTHB
These signals enable the RAM to be configured in one of
four allowable aspect ratios (Table 2-25).
ADDRA and ADDRB
Table 2-25 • Allowable Aspect Ratio Settings for
These are used as read or write addresses, and they are 12
bits wide. When a depth of less than 4 k is specified, the
unused high-order bits must be grounded (Table 2-26).
WIDTHA[1:0]
WIDTHA1, WIDTHA0
WIDTHB1, WIDTHB0
D×W
4k×1
2k×2
1k×4
512×9
00
01
10
11
00
01
10
11
Table 2-26 • Address Pins Unused/Used for Various
Supported Bus Widths
ADDRx
DxW
4k×1
2k×2
1k×4
512×9
Unused
None
Used
[11:0]
[10:0]
[9:0]
Note: The aspect ratio settings are constant and cannot be
changed on the fly.
[11]
[11:10]
[11:9]
BLKA and BLKB
These signals are active low and will enable the
respective ports when asserted. When a BLKx signal is
deasserted, the corresponding port’s outputs hold the
previous value.
[8:0]
Note: The "x" in ADDRx implies A or B.
DINA and DINB
WENA and WENB
These are the input data signals, and they are nine bits
wide. Not all nine bits are valid in all configurations.
When a data width less than nine is specified, unused
high-order signals must be grounded (Table 2-27).
These signals switch the RAM between read and write
modes for the respective ports. A low on these signals
indicates a write operation, and a high indicates a read.
CLKA and CLKB
DOUTA and DOUTB
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
These are the nine-bit output data signals. Not all nine
bits are valid in all configurations. As with DINA and
DINB, high-order bits may not be used (Table 2-27). The
output data on unused pins is undefined.
PIPEA and PIPEB
These signals are used to specify pipelined read on the
output. A low on PIPEA or PIPEB indicates a nonpipelined
read and the data appears on the corresponding output
in the same clock cycle. A high indicates a pipelined read
and data appears on the corresponding output in the
next clock cycle.
Table 2-27 • Unused/Used Input and Output Data Pins for
Various Supported Bus Widths
DINx/DOUTx
DxW
4k×1
2k×2
1k×4
512×9
Unused
[8:1]
Used
[0]
WMODEA and WMODEB
[8:2]
[1:0]
[3:0]
[8:0]
These signals are used to configure the behavior of the
output when RAM is in write mode. A low on these
signals makes the output retain data from the previous
read. A high indicates pass-through behavior, wherein
the data being written will appear immediately on the
output. This signal is overridden when the RAM is being
read.
[8:4]
None
Note: The "x" in DINx and DOUTx implies A or B.
Advanced v0.7
2-53
Fusion Family of Mixed-Signal Flash FPGAs
RAM512X18 Description
RAM512X18
RADDR8
RADDR7
RD17
RD16
RADDR0
RD0
RW1
RW0
PIPE
REN
RCLK
WADDR8
WADDR7
WADDR0
WD17
WD16
WD0
WW1
WW0
WEN
WCLK
RESET
Figure 2-48 • RAM512X18
2-54
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
RAM512X18 exhibits slightly different behavior from the
RAM4K9, as it has dedicated read and write ports.
Fusion devices support inversion (bubble pushing)
throughout the FPGA architecture, including the clock
input to the SRAM modules. Inversions added to the
SRAM clock pin on the design schematic or in the HDL
code will be automatically accounted for during design
compile without incurring additional delay in the clock
path.
WW and RW
These signals enable the RAM to be configured in one of
the two allowable aspect ratios (Table 2-28).
Table 2-28 • Aspect Ratio Settings for WW[1:0]
The two-port SRAM can be clocked on the rising edge or
falling edge of WCLK and RCLK.
WW[1:0]
01
RW[1:0]
01
D×W
512×9
If negative-edge RAM and FIFO clocking is selected for
memory macros, clock edge inversion management
(bubble pushing) is automatically used within the Fusion
development tools, without performance penalty.
10
10
256×18
Reserved
00, 11
00, 11
WD and RD
Modes of Operation
These are the input and output data signals, and they
are 18 bits wide. When a 512×9 aspect ratio is used for
write, WD[17:9] are unused and must be grounded. If
this aspect ratio is used for read, then RD[17:9] are
undefined.
There are two read modes and one write mode:
•
Read Nonpipelined (synchronous—one clock
edge): In the standard read mode, new data is
driven onto the RD bus in the same clock cycle
following RA and REN valid. The read address is
registered on the read port clock active edge and
data appears at RD after the RAM access time.
Setting PIPE to OFF enables this mode.
WADDR and RADDR
These are read and write addresses, and they are nine
bits wide. When the 256×18 aspect ratio is used for write
or read, WADDR[8] or RADDR[8] are unused and must be
grounded.
•
Read Pipelined (synchronous—two clock edges):
The pipelined mode incurs an additional clock
delay from the address to the data but enables
operation at a much higher frequency. The read
address is registered on the read port active clock
edge, and the read data is registered and appears
at RD after the second read clock edge. Setting
PIPE to ON enables this mode.
WCLK and RCLK
These signals are the write and read clocks, respectively.
They are both active high.
WEN and REN
These signals are the write and read enables,
respectively. They are both active low by default. These
signals can be configured as active high.
•
Write (synchronous—one clock edge): On the
write clock active edge, the write data is written
into the SRAM at the write address when WEN is
high. The setup times of the write address, write
enables, and write data are minimal with respect
to the write clock. Write and read transfers are
described with timing requirements in the "SRAM
Characteristics" section on page 2-56 and "FIFO
Characteristics" section on page 2-63.
RESET
This active low signal resets the output to zero and
disables reads and/or writes from the SRAM block as well
as clears the data hold registers when asserted. It does
not reset the contents of the memory.
PIPE
This signal is used to specify pipelined read on the
output. A low on PIPE indicates a nonpipelined read and
the data appears on the output in the same clock cycle. A
high indicates a pipelined read and data appears on the
output in the next clock cycle.
RAM Initialization
Each SRAM block can be individually initialized on
power-up by means of the JTAG port using the UJTAG
mechanism (refer to the "JTAG IEEE 1532" section on
page 2-172 and the Fusion SRAM/FIFO Blocks application
note). The shift register for a target block can be selected
and loaded with the proper bit configuration to enable
serial loading. The 4,608 bits of data can be loaded in a
single operation.
Clocking
The dual-port SRAM blocks are only clocked on the rising
edge. SmartGen allows falling-edge triggered clocks by
adding inverters to the netlist, hence achieving dual-port
SRAM blocks that are clocked on either edge (rising or
falling). For dual-port SRAM, each port can be clocked on
either edge or by separate clocks, by port.
Advanced v0.7
2-55
Fusion Family of Mixed-Signal Flash FPGAs
SRAM Characteristics
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
BLK_B
WEN_B
DO
tBKS
tBKH
tENS
tENH
tCKQ1
Dn
D0
D1
D2
tDOH1
Figure 2-49 • RAM Read for Flow-Through Output
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
BLK_B
WEN_B
DO
tBKS
tBKH
tENH
tENS
tCKQ2
Dn
D0
D1
tDOH2
Figure 2-50 • RAM Read for Pipelined Output
2-56
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
tCYC
tCKH
tAH
tCKL
CLK
tAS
A0
tBKS
A1
A2
ADD
BLK_B
WEN_B
DI
tBKH
tENS
tENH
tDS
tDH
DI1
DI0
Dn
D2
DO
Figure 2-51 • RAM Write, Output Retained (WMODE = 0)
tCYC
tCKH
tCKL
CLK
ADD
tAS tAH
A0
A1
A2
tBKS
tBKH
BLK_B
WEN_B
DI
tENS
tDS
tDH
DI1
DI0
DI2
DO
Dn
DI0
DI1
(flow-through)
DO
DI
Dn
DI1
0
(Pipelined)
Figure 2-52 • RAM Write, Output as Write Data (WMODE = 1)
Advanced v0.7
2-57
Fusion Family of Mixed-Signal Flash FPGAs
CLK1
tAS tAH
A0
A2
D2
A3
D3
ADD1
DI1
tDS tDH
D0
tWRO
CLK2
ADD2
tAS
tAH
A0
A1
A4
tCKQ1
DO2
(flow-through)
Dn
D0
D1
tCKQ2
DO2
(Pipelined)
Dn
D0
Figure 2-53 • One Port Write/Other Port Read Same
tCYC
tCKH
tCKL
CLK
RESET_B
DO
tRSTBQ
Dm
Dn
Figure 2-54 • RAM Reset
2-58
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Timing Characteristics
Table 2-29 • RAM4K9
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tAS
Description
–2
–1
Std.
0.33
0.00
0.19
0.13
0.31
0.02
0.25
0.00
2.39
3.15
1.20
1.23
1.23
0.33
1.98
0.29
2.66
Units
ns
Address Setup time
0.25
0.00
0.14
0.10
0.23
0.02
0.18
0.00
1.79
2.36
0.89
0.92
0.92
0.25
1.49
0.22
1.99
0.28
0.00
0.16
0.11
0.27
0.02
0.21
0.00
2.03
2.68
1.02
1.05
1.05
0.28
1.68
0.25
2.26
tAH
Address Hold time
ns
tENS
REN_B,WEN_B Setup time
REN_B, WEN_B Hold time
BLK_B Setup time
ns
ns
ns
tENH
tBKS
tBKH
BLK_B Hold time
ns
tDS
Input data (DI) Setup time
Input data (DI) Hold time
ns
ns
ns
tDH
tCKQ1
Clock High to New Data Valid on DO (output retained, WMODE = 0)
Clock High to New Data Valid on DO (flow-through, WMODE = 1)
Clock HIGH to New Data Valid on DO (pipelined)
RESET_B Low to Data Out Low on DO (flow through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
ns
ns
tCKQ2
tRSTBQ
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
ns
RESET_B Recovery
RESET_B Minimum Pulse Width
ns
ns
Clock Cycle time
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Table 2-30 • RAM512X18
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tAS
Description
–2
–1
Std.
0.33
0.00
0.24
0.08
0.25
0.00
2.89
1.20
1.23
1.23
0.33
1.98
0.29
2.66
Units
ns
Address Setup time
0.25
0.00
0.18
0.06
0.18
0.00
2.16
0.90
0.92
0.92
0.25
1.49
0.22
1.99
0.28
0.00
0.20
0.07
0.21
0.00
2.46
1.02
1.05
1.05
0.28
1.68
0.25
2.26
tAH
Address Hold time
ns
tENS
REN_B,WEN_B Setup time
REB_B, WEN_B Hold time
Input data (DI) Setup time
Input data (DI) Hold time
ns
tENH
ns
tDS
ns
tDH
ns
tCKQ1
tCKQ2
tRSTBQ
Clock High to New Data Valid on DO (output retained, WMODE = 0)
Clock High to New Data Valid on DO (pipelined)
RESET_B Low to Data Out Low on DO (flow through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
ns
Clock Cycle time
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-59
Fusion Family of Mixed-Signal Flash FPGAs
FIFO4K18 Description
FIFO4K18
RD17
RD16
RW2
RW1
RW0
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEMPTY
AEVAL11
AEVAL10
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-55 • FIFO4KX18
2-60
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
The following signals are used to configure the FIFO4K18
memory element:
WD
This is the input data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. When a data width
less than 18 is specified, unused higher-order signals
must be grounded (Table 2-32).
WW and RW
These signals enable the FIFO to be configured in one of
the five allowable aspect ratios (Table 2-31).
RD
Table 2-31 • Aspect Ratio Settings for WW[2:0]
This is the output data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. Like the WD bus, high-
order bits become unusable if the data width is less than
18. The output data on unused pins is undefined
(Table 2-32).
WW2, WW1, WW0
RW2, RW1, RW0
D×W
4k×1
000
000
001
001
2k×2
010
010
1k×4
ESTOP, FSTOP
011
011
512×9
256×18
Reserved
ESTOP is used to stop the FIFO read counter from further
counting once the FIFO is empty (i.e., the Empty flag
goes high). A high on this signal inhibits the counting.
100
100
101, 110, 111
101, 110, 111
FSTOP is used to stop the FIFO write counter from further
counting once the FIFO is full (i.e., the Full flag goes
high). A high on this signal inhibits the counting.
WBLK and RBLK
These signals are active low and will enable the
respective ports when low. When the RBLK signal is high,
the corresponding port’s outputs hold the previous
value.
For more information on these signals, refer to the
"ESTOP and FSTOP Usage" section on page 2-62.
FULL, EMPTY
When the FIFO is full and no more data can be written,
the Full flag asserts high. The Full flag is synchronous to
WCLK to inhibit writing immediately upon detection of a
full condition and to prevent overflows. Since the write
address is compared to a resynchronized (and thus time-
delayed) version of the read address, the Full flag will
remain asserted until two WCLK active edges after a read
operation eliminates the full condition.
WEN and REN
Read and write enables. WEN is active low and REN is
active high by default. These signals can be configured as
active high or low.
WCLK and RCLK
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
When the FIFO is empty and no more data can be read,
the Empty flag asserts high. The Empty flag is
synchronous to RCLK to inhibit reading immediately
upon detection of an empty condition and to prevent
underflows. Since the read address is compared to a
resynchronized (and thus time delayed) version of the
write address, the Empty flag will remain asserted until
two RCLK active edges, after a write operation, removes
the empty condition.
RPIPE
This signal is used to specify pipelined read on the
output. A low on RPIPE indicates a nonpipelined read
and the data appears on the output in the same clock
cycle. A high indicates a pipelined read and data appears
on the output in the next clock cycle.
RESET
This active low signal resets the output to zero when
asserted. It resets the FIFO counters. It also sets all the RD
pins low, the Full and AFULL pins low, and the Empty and
AEMPTY pins high (Table 2-32).
For more information on these signals, refer to the "FIFO
Flag Usage Considerations" section on page 2-62.
AFULL, AEMPTY
These are programmable flags and will be asserted on
the threshold specified by AFVAL and AEVAL,
respectively.
Table 2-32 • Input Data Signal Usage for Different Aspect
Ratios
DxW
4k×1
WD/RD Unused
WD[17:1], RD[17:1]
WD[17:2], RD[17:2]
WD[17:4], RD[17:4]
WD[17:9], RD[17:9]
–
When the number of words stored in the FIFO reaches
the amount specified by AEVAL while reading, the
AEMPTY output will go high. Likewise, when the number
of words stored in the FIFO reaches the amount specified
by AFVAL while writing, the AFULL output will go high.
2k×2
1k×4
512×9
256×18
Advanced v0.7
2-61
Fusion Family of Mixed-Signal Flash FPGAs
AFVAL, AEVAL
The AEVAL and AFVAL pins are used to specify the
almost-empty and almost-full threshold values,
respectively. They are 12-bit signals. For more
information on these signals, refer to the "FIFO Flag
Usage Considerations" section on page 2-62.
The AEMPTY flag is asserted when the difference
between the write address and the read address is less
than a predefined value. In the example above, a value
of 200 for AEVAL means that the AEMPTY flag will be
asserted when a read causes the difference between the
write address and the read address to drop to 200. It will
stay asserted until that difference rises above 200. Note
that the FIFO can be configured with different read and
write widths; in this case the AFVAL setting is based on
the number of write data entries and the AEVAL setting
is based on the number of read data entries. For aspect
ratios of 512×9 and 256×18, only 4,096 bits can be
addressed by the 12 bits of AFVAL and AEVAL. The
number of words must be multiplied by 8 and 16, instead
of 9 and 18. The SmartGen tool automatically uses the
proper values. To avoid half-words being written or read,
which could happen if different read and write aspect
ratios are specified, the FIFO will assert Full or Empty as
soon as at least a minimum of one word cannot be
written or read. For example, if a two-bit word is written
and a four-bit word is being read, FIFO will remain in the
Empty state when the first word is written. This occurs
even if the FIFO is not completely empty, because in this
case a complete word cannot be read. The same is
applicable in the Full state. If a four-bit word is written
and a two-bit word is read, the FIFO is full and one word
is read. The FULL flag will remain asserted because a
complete word cannot be written at this point.
ESTOP and FSTOP Usage
The ESTOP pin is used to stop the read counter from
counting any further once the FIFO is empty (i.e., the
EMPTY flag goes high). Likewise, the FSTOP pin is used to
stop the write counter from counting any further once
the FIFO is full (i.e., the Full flag goes high).
The FIFO counters in the Fusion device start the count at
0, reach the maximum depth for the configuration (e.g.,
511 for a 512×9 configuration), and then restart at 0. An
example application for the ESTOP, where the read
counter keeps counting, would be writing to the FIFO
once and reading the same content over and over
without doing another write.
FIFO Flag Usage Considerations
The AEVAL and AFVAL pins are used to specify the 12-bit
AEMPTY and AFULL threshold values, respectively. The
FIFO contains separate 12-bit write address (WADDR)
and read address (RADDR) counters. WADDR is
incremented every time a write operation is performed,
and RADDR is incremented every time a read operation is
performed. Whenever the difference between WADDR
and RADDR is greater than or equal to AFVAL, the AFULL
output is asserted. Likewise, whenever the difference
between WADDR and RADDR is less than or equal to
AEVAL, the AEMPTY output is asserted. To handle
different read and write aspect ratios, AFVAL and AEVAL
are expressed in terms of total data bits instead of total
data words. When users specify AFVAL and AEVAL in
terms of read or write words, the SmartGen tool
translates them into bit addresses and configures these
signals automatically. SmartGen configures the AFULL
flag, AFULL, to assert when the write address exceeds the
read address by at least a predefined value. In a 2k×8
FIFO, for example, a value of 1,500 for AFVAL means that
the AFULL flag will be asserted after a write when the
difference between the write address and the read
address reaches 1,500 (there have been at least 1500
more writes than reads). It will stay asserted until the
difference between the write and read addresses drops
below 1,500.
2-62
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
FIFO Characteristics
Timing Waveforms
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET_B
EMPTY
AEMPTY
FULL
tRSTFG
tRSTAF
tRSTFG
tRSTAF
AFULL
WA/RA
(Address Counter)
MATCH (A0)
Figure 2-56 • FIFO Reset
tCYC
RCLK
tRCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
(Address Counter)
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 2-57 • FIFO EMPTY Flag and AEMPTY Flag Assertion
Advanced v0.7
2-63
Fusion Family of Mixed-Signal Flash FPGAs
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-58 • FIFO FULL and AFULL Flag Assertion
WCLK
MATCH
WA/RA
NO MATCH
NO MATCH
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(EMPTY)
(Address Counter)
1st rising
2nd rising
edge
edge
after 1st
write
after 1st
write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-59 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
2-64
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
RCLK
WA/RA
(Address Counter) MATCH (FULL)
NO MATCH
NO MATCH
NO MATCH
NO MATCH
Dist = AFF_TH - 1
1st rising
1st rising
edge
after 1st
read
edge
after 2nd
read
WCLK
FULL
t
WCKF
t
CKAF
AFULL
Figure 2-60 • FIFO FULL Flag and AFULL Flag Deassertion
Timing Characteristics
Table 2-33 • FIFO
Commercial Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
–2
–1
Std.
1.22
0.00
0.34
0.00
0.25
0.00
3.15
1.20
2.30
2.18
4.99
2.27
4.90
1.23
1.23
0.38
2.01
0.30
2.79
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REN_B,WEN_B Setup time
0.91
0.00
0.25
0.00
0.18
0.00
2.36
0.89
1.72
1.63
3.72
1.69
3.66
0.92
0.92
0.29
1.50
0.30
2.79
1.04
0.00
0.29
0.00
0.21
0.00
2.68
1.02
1.96
1.86
4.24
1.93
4.17
1.05
1.05
0.33
1.71
0.30
2.79
tENH
REN_B, WEN_B Hold time
tBKS
BLK_B Setup time
tBKH
BLK_B Hold time
tDS
Input data (DI) Setup time
tDH
Input data (DI) Hold time
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock High to New Data Valid on DO (flow-through)
Clock High to New Data Valid on DO (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET_B Low to Empty/Full Flag valid
RESET_B Low to Almost-Empty/Full Flag Valid
RESET_B Low to Data out Low on DO (flow-through)
RESET_B Low to Data out Low on DO (pipelined)
RESET_B Removal
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle time
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-65
Fusion Family of Mixed-Signal Flash FPGAs
Analog Block
With the Fusion family, Actel has introduced the world's
first mixed-mode FPGA solution. Supporting a robust
analog peripheral mix, Fusion devices will support a wide
variety of applications. It is this Analog Block that
separates Fusion from all other FPGA solutions on the
market today.
VAREF
GNDREF
AV0
AC0
AT0
DAVOUT0
DACOUT0
DATOUT0
By combining both Flash and high-speed CMOS processes
in a single chip, these devices offer the best of both
worlds. The high-performance CMOS is used for building
RAM resources. These high performance structures
support device operation up to 350 MHz. Additionally,
the advanced Actel 0.13 µm Flash process incorporates
high-voltage transistors and a high-isolation, triple-well
process. Both of these are suited for the Flash-based
programmable logic and nonvolatile memory structures.
AV9
AC9
AT9
ATRETURN01
DAVOUT9
DACOUT9
DATOUT9
AG0
AG1
ATRETURN9
DENAV0
DENAC0
DENAT0
AG9
High-voltage transistors support the integration of
analog technology in several ways. They aid in noise
immunity so that the analog portions of the chip can be
better isolated from the digital portions, increasing
analog accuracy. Because they support high voltages,
Actel Flash FPGAs can be connected directly to high-
voltage input signals, eliminating the need for external
resistor divider networks, reducing component count,
and increasing accuracy. By supporting higher internal
voltages, the Actel advanced Flash process enables high-
dynamic range on analog circuitry, increasing precision
and signal/noise ratio. Actel Flash FPGAs also drive high-
voltage outputs, eliminating the need for external level
shifters and drivers.
DENAV0
DENAC0
DENAT0
CMSTB0
CSMTB9
GDON0
GDON9
TMSTB0
TMSTB9
MODE[3:0]
TVC[7:0]
STC[7:0]
CHNUMBER[4:0]
BUSY
CALIBRATE
DATAVALID
SAMPLE
The unique triple-well process enables the integration of
high-performance analog features with increased noise
immunity and better isolation. By increasing the
efficiency of analog design, the triple-well process also
enables a smaller overall design size, reducing die size
and cost.
TMSTINT
RESULT[11:0]
RTCMATCH
RTCXTLMODE
RTCXTLSEL
ADCSTART
VAREFSEL
PWRDWN
ADCRESET
RTCPSMMATCH
The Analog Block consists of the Analog Quad I/O
structure, real-time counter (for details refer to the "Real-
Time Counter System" section on page 2-31), analog to
digital converter (ADC), and analog configuration
multiplexer (ACM). All of these elements are combined in
the single Analog Block macro, with which the user
implements this functionality (Figure 2-61).
RTCCLK
SYSCLK
ACMWEN
ACMRESET
ACMWDATA
ACMADDR
ACMCLK
ACMRDATA[7:0]
AB
Figure 2-61 • Analog Block Macro
2-66
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-34 describes each pin in the Analog Block. Each function within the Analog Block will be explained in detail in
in the following sections.
Table 2-34 • Analog Block Pin Description
Number
of Bits
Location of
Details
Signal Name
Direction
Function
VAREF
1
Input/Output
Voltage reference for ADC; used as either
input or output, depending on VREFSEL.
Needs to connect a 10 uF capacitor with
placement as close as to the VAREF pin.
ADC
GNDREF
1
4
1
8
8
1
1
1
1
1
1
12
1
1
1
Input
Input
External ground reference
ADC operating mode
External system clock
Clock divide control
ADC
ADC
MODE[3:0]
SYSCLK
Input
TVC[7:0]
Input
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
STC[7:0]
Input
Sample time control
ADCSTART
PWRDWN
ADCRESET
BUSY
Input
Start of conversion
Input
Comparator power-down if 1
ADC initialize if 1
Input
Output
Output
Output
Output
Input
1 – Running conversion
1 – Power-up calibration
1 – Valid conversion result
Conversion result
CALIBRATE
DATAVALID
RESULT[11:0]
TMSTBINT
SAMPLE
Internal temp. monitor strobe
1 – Analog input is sampled
Output
Input
VAREFSEL
0 = Output internal voltage reference
(2.56 V) to VAREF
1 = Input external voltage reference from
VAREF and GNDREF
CHNUMBER[4:0]
ACMCLK
5
1
Input
Input
Input
Input
Input
Output
Input
Input
Analog input channel select
ACM clock
Input multiplexer
ACM
ACMWEN
1
ACM write enable – active high
ACM reset – active low
ACM write data
ACM
ACMRESET
1
ACM
ACMWDATA[7:0]
ACMRDATA[7:0]
ACMADDR[7:0]
CMSTB0 to CMSTB9
8
ACM
8
ACM read data
ACM
8
ACM address
ACM
10
Current monitor strobe – 1 per quad,
active high
Analog Quad
GDON0 to GDON9
TMSTB0 to TMSTB9
10
10
Input
Input
Control to power MOS – 1 per quad
Analog Quad
Analog Quad
Temperature monitor strobe – 1 per quad;
active high
DAVOUT0, DACOUT0, DATOUT0 to
DAVOUT9, DACOUT9, DATOUT9
30
30
Output
Input
Digital outputs – 3 per quad
Digital input enables – 3 per quad
Analog Quad 0
Analog Quad
Analog Quad
DENAV0,
DENAC0,
DENAT0
to
DENAV9, DENAC9, DENAT9
AV0
AC0
AG0
1
1
1
Input
Input
Analog Quad
Analog Quad
Analog Quad
Output
Advanced v0.7
2-67
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-34 • Analog Block Pin Description (Continued)
Number
of Bits
Location of
Details
Signal Name
AT0
Direction
Input
Function
1
1
Analog Quad
Analog Quad
ATRETURN01
Input
Temperature monitor return shared by
Analog Quads 0 and 1
AV1
1
1
1
1
1
1
1
1
1
Input
Input
Analog Quad 1
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
AC1
AG1
Output
Input
AT1
AV2
Input
Analog Quad 2
AC2
Input
AG2
Output
Input
AT2
ATRETURN23
Input
Temperature monitor return shared by
Analog Quads 2 and 3
AV3
1
1
1
1
1
1
1
1
1
Input
Input
Analog Quad 3
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
AC3
AG3
Output
Input
AT3
AV4
Input
Analog Quad 4
AC4
Input
AG4
Output
Input
AT4
ATRETURN45
Input
Temperature monitor return shared by
Analog Quads 4 and 5
AV5
1
1
1
1
1
1
1
1
1
Input
Input
Analog Quad 5
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
AC5
AG5
Output
Input
AT5
AV6
Input
Analog Quad 6
AC6
Input
AG6
Output
Input
AT6
ATRETURN67
Input
Temperature monitor return shared by
Analog Quads 6 and 7
AV7
AC7
AG7
AT7
AV8
AC8
AG8
AT8
1
1
1
1
1
1
1
1
Input
Input
Analog Quad 7
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Output
Input
Input
Analog Quad 8
Input
Output
Input
2-68
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Location of
Table 2-34 • Analog Block Pin Description (Continued)
Number
Signal Name
of Bits
Direction
Function
Details
ATRETURN89
1
Input
Temperature monitor return shared by
Analog Quads 8 and 9
Analog Quad
AV9
1
1
1
1
1
1
2
1
1
Input
Input
Analog Quad 9
Analog Quad
Analog Quad
Analog Quad
Analog Quad
RTC
AC9
AG9
Output
Input
AT9
RTCMATCH
RTCPSMMATCH
RTCXTLMODE[1:0]
RTCXTLSEL
RTCCLK
Output
Output
Output
Output
Input
MATCH
MATCH connected to VRPSM
Drives XTLOSC RTCMODE[1:0] pins
Drives XTLOSC MODESEL pin
RTC clock input
RTC
RTC
RTC
RTC
Analog Quad
With the Fusion family, Actel introduces the Analog
Quad, shown in Figure 2-62 on page 2-70, as the basic
analog I/O structure. The Analog Quad is a four-channel
system used to precondition a set of analog signals
before sending to the ADC for conversion into a digital
signal. In order to maximize the usefulness of the Analog
Quad, the analog input signals may also be configured as
LVTTL digital input signals. The Analog Quad is divided
into four sections.
The third part of the Analog Quad is called the Gate
Driver Block and its output pin is named AG. This section
is used to drive an external FET. There are two modes
available: a high current drive mode and a current source
control mode. Both negative and positive voltage
polarities are available and in the current source control
mode, four different current levels are available.
The fourth section of the Analog Quad is called the
Temperature Monitor Block and its input pin name is AT.
This block is similar to the Voltage Monitor Block except
that it has an additional function: it can be used to
monitor the temperature of an external diode connected
transistor. It has a modified pre-scaler and is limited to
positive voltages only.
The first section is called the Voltage Monitor Block and
its input pin is named AV. It contains a 2-channel analog
multiplexer which allows an incoming analog signal to
be routed directly to the ADC or allows the signal to be
routed to a pre-scaler circuit before being sent to the
ADC. The pre-scaler can be configured to accept analog
signals between –12 V and 0, or between 0 and +12 V.
The pre-scaler circuit scales the voltage applied to the
ADC input pad such that it is compatible with the ADC
input voltage range. The AV pin may also be used as a
digital input pin.
The Analog Quad can be configured during design time
by Actel Libero IDE; however, the Analog Configuration
MUX (ACM) can be used to change the parameters of
any of these I/Os during runtime. This type of change is
referred to as a context switch. The Analog Quad is a
modular structure that is replicated to generate the
analog I/O resources. Each Fusion device supports
between 5 and 10 Analog Quads.
The second section of the Analog Quad is called the
Current Monitor Block. Its input pin is named AC. The
Current Monitor Block contains all the same functions as
the Voltage Monitor Block with one addition, which is a
current monitoring function. A small external current
sensing resistor (typically less than 1 Ω) is connected
between the AV and AC pins and is in series with a
power source. The Current Monitor Block contains a
current monitor circuit that converts the current through
the external resistor to a voltage which can then be read
using the ADC.
The analog pads are numbered to clearly identify both
the type of pad (voltage, current, gate driver, or
temperature pad) and its corresponding Analog Quad
(AV0, AC0, AG0, AT0, AV1, …, AC9, AG9, and AT9). There
are three types of input pads (AVx, ACx, and ATx) and
one type of analog output pad (AGx). Since there can be
up to 10 Analog Quads on a device, there can be a
maximum of 30 analog input pads and 10 analog out
pads.
Advanced v0.7
2-69
Fusion Family of Mixed-Signal Flash FPGAs
Off-Chip
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Pre-Scaler
Pre-Scaler
Pre-Scaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor/Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 2-62 • Analog Quad
2-70
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Voltage Monitor
The Fusion Analog Quad offers a robust set of voltage
monitoring capabilities unique in the FPGA industry. The
Analog Quad is comprised of three analog input pads—
Analog Voltage (AV), Analog Current (AC), and Analog
Temperature (AT)—and a single gate driver output pad,
Analog Gate (AG). There are many common
characteristics among the analog input pads. Each
analog input can be configured to connect directly to the
input MUX of the ADC. When configured in this manner
(Figure 2-63), there will be no prescaling of the input
signal. Care must be taken in this mode not to drive the
ADC into saturation by applying an input voltage greater
than the reference voltage. The internal reference
voltage of the ADC is 2.56 V. Optionally, an external
reference can be supplied by the user. The external
reference can be a maximum of 3.3 V DC.
Off-Chip
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Pre-Scaler
Pre-Scaler
Pre-Scaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor/Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 2-63 • Analog Quad Direct Connect
Advanced v0.7
2-71
Fusion Family of Mixed-Signal Flash FPGAs
The Analog Quad inputs are tolerant up to 12 V 10%.
The Analog Quad offers a wide variety of prescaling
options to enable the ADC to resolve the input signals.
Figure 2-64 shows the path through the Analog Quad for
a signal that is to be prescaled prior to conversion. The
ADC internal reference voltage and the pre-scaler factors
were selected to make both prescaling and postscaling of
the signals easy, binary calculations (refer to Table 2-45 on
page 2-93 for details). When an analog input pad is
configured with a pre-scaler, there will be a 1 MΩ resistor
to ground. This occurs even when the device is in power
down mode. On low power standby or sleep mode (VCC is
OFF, VCC33A is ON; VCCI is ON) or when the resource is not
used, Analog inputs are pulled-down to ground through a
1 MΩ resistor. The gate driver output is floating (or
tristated), and there is no extra current on VCC33A
.
These scaling factors hold true whether the particular
pad is configured to accept a positive or negative
voltage. Note that while the AV and AC pads support the
same prescaling factors, the AT pad supports a reduced
set of prescaling factors and support positive voltages
only.
Typical scaling factors are given in Table 2-45 on page 2-93,
and the gain error (which contributes to the minimum and
maximum) is in Table 2-40 on page 2-86.
Each I/O will draw power when connected to power
(3 mA at 3 V).
Off-Chip
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Pre-Scaler
Pre-Scaler
Pre-Scaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor/Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 2-64 • Analog Quad Pre-Scaler Input Configuration
2-72
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Direct Digital Input
The AV, AC, and AT pads can also be configured as high
voltage digital inputs (Figure 2-65). As these pads are
12 V tolerant, the digital input can also be up to 12 V.
However, the frequency at which these pads can operate
is limited to 10 MHz.
respectively) and y is 0 to 9, corresponding to the
appropriate Analog Quad.
When the pad is configured as a digital input, this signal
will come out of the Analog Block macro on the
appropriate DAxOUTy pin, where x represents the pad
type (V for AV pad, C for AC pad, or T for AT pad) and y
represents the appropriate Analog Quad number.
Example: if the AT pad in Analog Quad 5 is configured as
a digital input, it will come out on the DATOUT5 pin of
the Analog Block macro.
To enable one of these analog input pads to operate as a
digital input, its corresponding Digital Input enable
(DENAxy) pin on the Analog Block must be pulled high,
where x is either V, C, or T (for AV, AC, or AT pads
Off-Chip
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Pre-Scaler
Pre-Scaler
Pre-Scaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor/Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 2-65 • Analog Quad Direct Digital Input Configuration
Advanced v0.7
2-73
Fusion Family of Mixed-Signal Flash FPGAs
Current Monitor
The Fusion Analog Quad is an excellent element for
voltage and current monitoring applications. In addition
to supporting the functionality offered by the AV pad,
the AC pad may be configured to monitor current across
an external sense resistor (Figure 2-66). To support this
current monitor function, the 10x differential amplifier
passes the amplified difference between the AV and AC
pads to the ADC. The potential on the AV pad MUST be
greater than the AC pad in current monitor mode. The
amplifier enables the user to use very small resistor
values, thereby limiting any impact on the circuit. This
function of the AC pad does not affect the AV pad
operation. The current monitor can resolve differences
between the AV and AC pads as low as 1 mV.
The current monitor is activated via the Current Monitor
Strobe pin (CMST) on the Analog Block macro. There is a
CMST pin for each Analog Quad present on the device
(CMST0–CMST9).
Power
Off-Chip
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Pre-Scaler
Pre-Scaler
Pre-Scaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor/Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 2-66 • Analog Quad Current Monitor Configuration
2-74
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Figure 2-67 illustrates the current monitor operation
with an example of the AC pad operating in current
monitor mode. In this example, a 10 V supply is passed
across a 0.10 Ω resistor. The difference between the AV
and AC pad passes through the 10x amplifier and is then
converted by the ADC. In this example, the current
drawn from a 10 V supply is measured by the voltage
drop it creates across the 0.1 Ω current sampling resistor.
This voltage drop is in turn amplified by ten times by the
10x amplifier and then measured by the ADC.
Considering the values shown in Figure 2-67, and making
use of Ohm's law, it can be seen that the 1 A current
creates a voltage drop across the sampling resistor of
0.1 V, which becomes 1 V after amplification. Thus, the
ADC measures a current of 1 A as 1 V, and a current of
0.2 A would therefore be read as 0.2 V by the ADC.
Note that because of the 10x amplification of the
voltage difference between these pads, the maximum
measurable difference between the AV and AC pads is
the ADC reference voltage divided by 10. A larger AV-to-
AC voltage drop will result in ADC saturation, i.e., the
digital code output by the ADC will stay stuck at the full
scale value for the chosen ADC reference voltage.
Therefore, the user must select the external sense
resistor appropriately. Another important consideration
is that the absolute value of the voltage on the AV pin
should be greater than or equal to the absolute value of
the voltage on the AC pin for the current monitor to
function correctly. If voltage available for reading by the
ADC the current monitor output voltage available for
reading by the ADC will be zero.
1A
0.1 Ω
10 V
10 V
9.9 V
AC
AV
1 V
10x
To ADC
Figure 2-67 • Current Monitor Example
Advanced v0.7
2-75
Fusion Family of Mixed-Signal Flash FPGAs
Gate Driver
The Fusion Analog Quad includes
a
Gate Driver,
pull-up or pull-down resistor. If 1 V is forced on the drain,
the current sinking/sourcing will exceed the ability of the
transistor, and the device could be damaged.
connected to the quad's AG pin (Figure 2-68). Designed
to work with external P-Channel or N-Channel MOSFETs,
the Gate driver is a configurable current sink or source
and requires an external pull-up or a pull-down resistor.
The AG supports 4 selectable gate drive levels: 1 µA, 3
µA, 10 µA, and 30 µA (Figure 2-69 on page 2-77). The AG
also supports a High Current Drive mode in which it can
sink 25 mA. Modeled on an open drain style output, it
does not output a voltage level without an appropriate
The AG pad is turned on via the corresponding GDONx
pin in the Analog Block macro, where x is the number of
the corresponding Analog Quad for AG pad to be
enabled (GDON0 to GDON9). The maximum AG pad
switching frequency is 1.25 MHz.
Power
Line Side
Load Side
Off-Chip
Rpullup
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Pre-Scaler
Pre-Scaler
Pre-Scaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor/Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 2-68 • Gate Driver
The gate-to-source voltage (Vgs) of the external MOSFET
is limited to the programmable drive current times the
external pull-up or pull-down resistor value (EQ 2-1).
The rate at which the gate voltage of the external
MOSFET slews is determined by the current Ig sourced or
sunk by the AG pin and the gate to source capacitance
CGS of the external MOSFET. As an approximation, the
slew rate is given by EQ 2-2.
Vgs ≤ lg × (Rpullup or Rpulldown
)
EQ 2-1
dv ⁄ dt = lg ⁄ CGS
EQ 2-2
2-76
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
CGS is not a fixed capacitance but, depending on the circuitry connected to its drain terminal, can vary significantly
during the course of a turn-on or turn-off transient. Thus EQ 2-2 on page 2-76 can only be used for a first order
estimate of the switching speed of the external MOSFET.
1µA
3µA
10 µA
30 µA
AG
High
Current
1µA
3µA
10 µA
30 µA
Figure 2-69 • Gate Driver Example
Advanced v0.7
2-77
Fusion Family of Mixed-Signal Flash FPGAs
Temperature Monitor
The final pin in the Analog Quad is the Analog
Temperature (AT) pin. The AT pin is used to implement
an accurate temperature monitor in conjunction with an
external diode connected bipolar transistor (Figure 2-70).
For improved temperature measurement accuracy, it is
important to use the ATRTN pin for the return path of
the current sourced by the AT pin. Each ATRTN pin is
shared between two adjacent Analog Quads.
Additionally, if not used for temperature monitoring, the
AT pin can provide functionality similar to that of the AV
pad. However, in this mode only positive voltages may be
applied to the AT pin and only two pre-scaler factors are
available (16 V and 4 V full scale—refer to Table 2-34 on
page 2-67).
Discrete
Bipolar
Transistor
Off-Chip
ATRTN
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Pre-Scaler
Pre-Scaler
Pre-Scaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor/Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 2-70 • Temperature Monitor Quad
2-78
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
The well-known temperature dependence of the current
versus voltage characteristics of a PN junction form the
basis of the temperature measurement scheme
implemented in the Fusion devices. Figure 2-71 shows a
simplified schematic of this implementation. The diode
connected bipolar transistor is used as the temperature
sensor. The 12.5x amplifier is a switched-capacitor based
design and as such can make pseudo-differential
measurements i.e., it multiplies by 12.5 the difference
between the voltages that appears across the diode
connected bipolar transistor with the 90 µA current
source switched in (diode current = 100 µA) and when it
is switched out (diode current = 10 µA). The voltage
applied to the ADC is then given in EQ 2-3.
where
n = Ideality factor of the diode connected transistor.
It is typically 1.008 for the Actel recommended
transistor type 2N3904. It does vary from
transistor to transistor even of the same type and
so for very accurate results calibration is needed.
k = 1.3806 x 10-23 J/K is the Boltzman constant
q = 1.602 x 10-19 C is the charge of a proton and as
such the ADC reads the temperature T in degrees
Kelvin
The temperature monitor block is accurate to 5°C. This
accuracy is limited by the ideality of the external diode
connected bipolar transistor. From the above equation it
can be seen that voltage output by the temperature
monitor block is about 2.50 mV per degree Kelvin. Thus,
it is essential to observe good design practices to reduce
noise coupled to the on-board and off-board wiring
associated with the diode connected bipolar transistor.
VADC = 12.5[(nkT ⁄ q) in (100 µA ⁄ 10 µA)] = 250 × 10-3 × T
EQ 2-3
A temperature reading is initiated via the Temperature
Monitor Strobe (TMSTB) pin associated with a particular
Analog Quad. There are up to 10 TMSTB pins in the
device (TMSTB0 – TMSTB9).
10 µA
90 µA
To ADC
12.5X
AT
ATRTN Pin
Figure 2-71 • Temperature Monitor Circuit
Advanced v0.7
2-79
Fusion Family of Mixed-Signal Flash FPGAs
Analog to Digital Converter Block
At the heart of the Fusion analog system is a programmable Successive Approximation Register (SAR) analog to digital
converter (ADC). The ADC can support 8-, 10-, or 12-bit modes of operation. In 12-bit mode, the ADC can resolve 500
ksps. All results are MSB justified in the ADC. The input to the ADC is a large 32:1 analog input multiplexer. A
simplified block diagram of the Analog Quads, analog input multiplexer, and ADC is shown in Figure 2-72. The ADC
offers multiple self-calibrating modes to ensure consistent high performance at both power-up and during runtime.
VCC(1.5 V)
0
1
Pads
AV0
AC0
AG0
AT0
Analog
Quad 0
These are hardwired
connections within
Analog Quad.
ATRETURN01
AV1
AC1
AG1
AT1
Analog
Quad 1
AV2
AC2
AG2
AT2
Analog
Quad 2
ATRETURN23
AV3
AC3
AG3
AT3
Analog
Quad 3
AV4
AC4
AG4
AT4
Analog
Quad 4
12
Analog MUX
(32 to1)
ATRETURN45
ADC
AV5
AC5
AG5
AT5
AV6
AC6
AG6
AT6
Analog
Quad 5
Digital Output to FPGA
Analog
Quad 6
ATRETURN67
AV7
AC7
AG7
AT7
Analog
Quad 7
AV8
AC8
AG8
AT8
Analog
Quad 8
ATRETURN89
AV9
AC9
AG9
AT9
Analog
Quad 9
31
Temperature
Monitor
CHNUMBER[4:0]
Internal Diode
Figure 2-72 • ADC Block Diagram
2-80
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
page i of this datasheet for the number of quads per
device. Regardless of the number of quads populated in a
device, the internal connections to both VCC and internal
temperature diode remain on Channels 0 and 31
respectively. In order to sample the internal temperature
monitor, it must be strobed (similar to the AT pads). The
TMSTBINT pin on the Analog Block macro is the control
for strobing the internal temperature measurement
diode.
ADC Input Multiplexer
At the input to the Fusion ADC is a 32:1 multiplexer. Of
the 32 input channels, up to 30 are user definable. Two of
these channels are hardwired internally. Channel 31
connects to an internal temperature diode, so that the
temperature of the Fusion device itself can be monitored.
Channel 0 is wired to the FPGA’s 1.5 V VCC supply, enabling
the Fusion device to monitor its own power supply. Doing
this internally makes it unnecessary to use an analog I/O to
support these functions. The balance of MUX inputs are
connected to Analog Quads (see the "Analog Quad"
section on page 2-69). Table 2-35 defines which Analog
Quad inputs are associated with which specific analog
MUX channel. The number of Analog Quads present is
device-dependent; refer to the family list in Table 1 on
To determine which channel is selected for conversion,
there is
a 5-pin interface on the Analog Block,
CHNUMBER[4:0], defined in Table 2-36 on page 2-82.
Table 2-35 shows the correlation between the analog
MUX input channels and the analog input pins.
Table 2-35 • Analog MUX Channels
Analog MUX Channel
Signal
Vcc_analog
AV0
Analog Quad Number
0
1
Analog Quad 0
2
AC0
AT0
3
4
AV1
Analog Quad 1
Analog Quad 2
Analog Quad 3
Analog Quad 4
Analog Quad 5
Analog Quad 6
Analog Quad 7
Analog Quad 8
5
AC1
AT1
6
7
AV2
8
AC2
AT2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AV3
AC3
AT3
AV4
AC4
AT4
AV5
AC5
AT5
AV6
AC6
AT6
AV7
AC7
AT7
AV8
AC8
Advanced v0.7
2-81
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-35 • Analog MUX Channels (Continued)
Analog MUX Channel
Signal
Analog Quad Number
27
28
29
30
31
AT8
AV9
Analog Quad 9
AC9
AT9
Internal temperature monitor
Table 2-36 • Channel Selection
Channel Number
CHNUMBER[4:0]
0
1
2
3
.
00000
00001
00010
00011
.
.
.
.
.
30
31
11110
11111
2-82
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
ADC Description
The Actel Fusion ADC is a 12-bit SAR ADC. It offers a wide variety of configurations to support many customer use
models. It can be programmed to operate in 8-, 10-, or 12-bit modes. This is controlled by MODE[3:0], as defined in
Table 2-37.
The conversion time can vary greatly depending on the SYSCLK frequency, ADCCLK frequency (determined by TVC),
the STC settings, and the conversion bit-resolution (MODE). See EQ 2-4 through EQ 2-6.
t_conv = t_sync_read + t_sample + t_distrib + t_post_cal + t_sync_write
EQ 2-4
t_conv = SYSCLK period + ((2 + STC) * ADCCLK period) +
(8, 10 or 12 * ADCCLK period) + (2 * ADCCLK period) + SYSCLK period
EQ 2-5
ADCCLK = SYSCLK/4 * (1 + TVC)
EQ 2-6
where:
t_sync_read = Time for latching the input data
t_sample = Time for sampling the analog signal
t_distrib = Time for charge distribution
t_post_cal = Time for post-calibration
t_sync_write = Time for latching the output data
Table 2-37 • MODE[3:0] Truth Table
ADC Mode
Mode[3]
Mode[2]
Mode[1]
Mode[0]
10-bit
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
12-bit
8-bit
Reserved
10-bit without internal power-down after conversion
12-bit without internal power-down after conversion
8-bit without internal power-down after conversion
Reserved
10-bit without internal calibration
12-bit without internal calibration
8-bit without internal calibration
Reserved
10-bit without internal calibration and without internal power-down
after conversion
12-bit without internal calibration and without internal power-down
after conversion
1
1
1
1
1
1
0
1
1
1
0
1
8-bit without internal calibration and without internal power-down after
conversion
Reserved
Advanced v0.7
2-83
Fusion Family of Mixed-Signal Flash FPGAs
In addition to the resolution, the ADC offers many different timing configurations. The clock for the ADC is brought
into the ADC via the SYSCLK pin on the Analog Block. This base clock can be divided down to suit ADC performance
requirements. The clock divider for the ADC clock is TVC[7:0], defined in Table 2-38.
Table 2-38 • ADC Clock Divider
TVC[7:0]
ADC Clock = SYSCLK/(4 × (TVC + 1))
0
00000000
SYSCLK/4
1
00000001
SYSCLK/8
.
.
.
.
.
.
126
127
128
.
01111110
01111111
10000000
SYSCLK/508
SYSCLK/5012
SYSCLK/516
.
255
11111111
SYSCLK/1024
The amount of time allocated for a single sample is also programmable. The clock period defined by 1/ADC clock is the
basic unit of measurement for the Sample Time Control (STC). The Sample Time Control table details how the STC can
be configured via the STC[7:0] pins on the Analog Block, defined in Table 2-39.
Table 2-39 • Sample Time Control (STC)
STC[7:0]
00000000
00000001
Sample Time = (STC + 2) × ADC_CLK Period
2 ADC clock periods
0
1
3 ADC clock periods
.
.
254
255
11111110
11111111
256 ADC clock periods
257 ADC clock periods
2-84
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
The Fusion device has an integrated on-chip 2.56 V
reference for the ADC. The value of this reference
voltage was chosen to make the pre-scaling and
postscaling factors for the pre-scaler blocks change in a
binary fashion. However, if desired an external reference
voltage of up to 3.3 V can be connected between the
VAREF and GNDREF pins. The VAREFSEL control pin is
used to select the reference voltage.
The offset/linearity error calibration is carried out in two
ways. First, a power-up calibration is carried out when
the ADC comes out of reset. This is initiated by the
CALIBRATE output of the Analog Block macro and is a
fixed number of ADC_CLK cycles (3,840 cycles). In this
mode, the linearity and offset errors of the capacitors are
calibrated. Secondly, to compensate for drift and
temperature-dependent effects, every conversion is
followed by calibration of either the offset or a bit of the
main capacitor array. The calibration procedure takes
two additional ADC clock cycles. This ensures that over
time and with temperature, the ADC remains consistent.
•
0 = Output internal voltage reference (2.56 V) to
VAREF
•
1 = Input external voltage reference from VAREF
and GNDREF
After both calibration and setting the appropriate
configurations as explained above, the ADC is ready for
operation. Driving the ADCSTART signal will start a
sampling and conversion of a given channel number,
which is set using CHNUMBER[4:0]. Status signals
SAMPLE and BUSY will show when the ADC is sampling
and converting (see Table 2-36 on page 2-82). When the
conversion is completed, the DATAVALID pin will go high
(BUSY will go low), indicating that the digital result is
available on the RESULT[11:0] pins.
The ADC can be powered down independently of the
FPGA core as an additional control or for power saving
considerations, via the PWRDWN pin of the Analog
Block.
Once the ADC has powered up and been released from
reset, ADCRESET, the ADC will initiate a calibration
routine designed to provide optimal ADC performance.
The Fusion ADC offers a robust calibration scheme to
reduce integrated offset and linearity errors. The offset
and linearity errors of the main capacitor array are
compensated with an 8-bit calibration capacitor array.
Advanced v0.7
2-85
Fusion Family of Mixed-Signal Flash FPGAs
Analog System Characteristics
Table 2-40 • Electrical Specifications
Parameter
Description
Condition
Min.
Typ.
Max.
Units
All Analog Inputs (Direct Input)
VINAD
CINAD
Input Voltage
–0.2
≤ VREF
V
pF
Input Capacitance
Channel not selected
7
8
Channel selected but not sampling
Channel selected and sampling
8-bit mode
pF
18
4
pF
ZINAD
Input Impedance
kΩ
kΩ
kΩ
10-bit mode
4
12-bit mode
4
All Analog Inputs (Using Pre-Scaler)
VINAP
Input Voltage1
–12
12
V
%
Accuracy
Positive DC Inputs
Negative DC Inputs
1
2
%
Offset
2
0.2%
mV
of range
Bandwidth
100
kHz
ZINAP
Impedance (2, 4, 8, and 12-V
ranges)
1
MΩ
Scaling Factor
Pre-Scaler Modes (Table 2-45 on
page 2-93)
Settling Time
To 0.1% of final value
10
VREFADC/10
12
µs
Current Monitor (Potential on the AV Pad Must be Greater Than the AC Pad)
VRSM2
Maximum Differential Input
Resolution
mV
mV
V
1
Common Mode Range
Gain
–12
10
60
CMRR
Common mode rejection ratio DC – 1 kHz
dB
dB
1 kHz – 10 kHz
50
> 10 kHz
30
dB
Pole
100
kHz
µs
TMPWC
VOFFC
Strobe
Minimum Pulse Width (High and Low)
10
Offset Inaccuracy
–2 – (0.05
* (AV–
AC))
2 + (0.05 *
(AV–AC))
mv
Notes:
1. The input voltage range for the Temperature Monitor Block Pre-Scaler is 0 to 14 V.
2. VRSM is the maximum voltage drop across the current sense resistor.
3. Analog inputs used as digital inputs can tolerate up to 14V (same as analog inputs). There is no reliability concern on digital inputs
as long as VIND does not exceed this maximum input voltage.
4. VIND is limited to AVDD+0.2 to allow reaching 10Mhz input frequency.
2-86
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-40 • Electrical Specifications
Parameter Description
Condition
Min.
Typ.
Max.
Units
Temperature Monitor (Can be Used for Monitoring Positive Voltage Only)
Resolution
Accuracy
1
3
ºC
ºC
µs
TMPWT
Strobe
Minimum Pulse Width (High and Low)
10
Analog Input as a Digital Input
VIND3, 4
VHYSDIN
VIHDIN
VILDIN
Input Voltage
Hysteresis
–0.2
AVDD + 0.2
V
V
0.3
1.2
0.9
Input High
V
Input Low
V
VMPWDIN
VFDIN
Minimum Pulse Width
Maximum Frequency
Sleep Current
Dynamic Current
Input Delay
50
ns
10
20
20
MHz
nA
µA
ns
ISTBDIN
IDYNDIN
tINDIN
10
25
Analog Output Pad (G Pad)
VG
IG
Voltage Range
–12
12
V
Minimum Output Current High Current Mode at 1.0 V
Drive
mA
Low Current Mode—1 µA
Low Current Mode—3 µA
1
3
µA
µA
µA
µA
nA
Low Current Mode—10 µA
10
30
100
Low Current Mode—30 µA
IOFFG
Maximum Off Current
Notes:
1. The input voltage range for the Temperature Monitor Block Pre-Scaler is 0 to 14 V.
2. VRSM is the maximum voltage drop across the current sense resistor.
3. Analog inputs used as digital inputs can tolerate up to 14V (same as analog inputs). There is no reliability concern on digital inputs
as long as VIND does not exceed this maximum input voltage.
4. VIND is limited to AVDD+0.2 to allow reaching 10Mhz input frequency.
Advanced v0.7
2-87
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-41 • ADC Characteristics in Direct Input Mode
Parameter
Description
Reference Voltage
Condition
Internal Reference
External Reference
Min.
Typ.
Max.
Units
VREFADC
2.56
V
V
2.527
VCC33A
+ 0.05
DC Accuracy
TUE
Total Unadjusted Error (external 8-bit mode
reference)
0.1186
LSB
10-bit mode
12-bit mode
0.8112
2.4112
0.2
LSB
LSB
LSB
INL
Integral Non-linearity (external 8-bit mode
reference)
10-bit mode
12-bit mode
0.35
1.75
0.2
LSB
LSB
LSB
DNL
Differential
Non-linearity 8-bit mode
(external reference)
(No Missing Codes)
10-bit mode
12-bit mode
0.6
2.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Offset Error (external reference) 8-bit mode
0.01
0.156
0.125
0.5
10-bit mode
12-bit mode
Gain Error (external reference) 8-bit mode
10-bit mode
2.26
3.6
12-bit mode
Conversion Rate
Conversion Time
Sample Rate1
8-bit mode
10-bit mode
12-bit mode
8-bit mode
10-bit mode
12-bit mode
1.67
1.82
2
µs
µs
µs
600
550
500
ksps
ksps
ksps
Notes:
1. The Sample Rate is time-shared among active analog inputs.
2. Internal voltage reference can handle a load up to 100 µA.
2-88
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Analog Configuration MUX
The Analog Configuration MUX (ACM) is the interface
between the FPGA, the Analog Block configurations, and
the real-time counter. The Actel Libero IDE Tool will
generate IPs that will load and configure the Analog
Block via the ACM. However, users are not limited to only
using the Libero IDE IP. This section provides a detailed
description of the ACM's register map, truth tables for
proper configuration of the Analog Block and RTC, as
well as timing waveforms so users can access and control
the ACM directly from their designs.
act as configuration bits for Analog Quads. The ACM
block runs from the core voltage supply (1.5 V).
Access to the ACM is achieved via 8-bit address and data
buses with enables. The pin list is provided in Table 2-34
on page 2-67. The ACM clock speed is limited to a
maximum of 10 MHz operation, more than sufficient to
handle the low bandwidth requirements of configuring
the Analog Block and the RTC (sub-block of the Analog
Block).
Table 2-42 decodes the ACM address space and maps it
to the corresponding Analog Quad and configuration
byte for that quad.
The Analog Block contains four 8-bit latches per Analog
Quad that are initialized through the ACM. These latches
Table 2-42 • ACM Address Decode Table for Analog Quad
ACMADDR [7:0] in
Decimal
Name
–
Description
–
Associated Peripheral
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
Analog Quad
RTC
0
1
AQ0
AQ0
AQ0
AQ0
AQ1
Byte 0
Byte 1
Byte 2
Byte 3
Byte 0
2
3
4
5
.
.
.
.
.
36
37
38
39
40
41
.
AQ8
AQ9
AQ9
AQ9
AQ9
Byte 3
Byte 0
Byte 1
Byte 2
Byte3
Undefined
Undefined
.
Undefined
.
Undefined
63
64
65
66
67
68
72
Undefined
COUNTER0
COUNTER1
COUNTER2
COUNTER3
COUNTER4
MATCHREG0
Counter bits 7:0
Counter bits 15:8
Counter bits 23:16
Counter bits 31:24
Counter bits 39:32
RTC
RTC
RTC
RTC
RTC
Match register bits 7:0
RTC
Advanced v0.7
2-89
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-42 • ACM Address Decode Table for Analog Quad (Continued)
ACMADDR [7:0] in
Decimal
Name
Description
Match register bits 15:8
Match register bits 23:16
Match register bits 31:24
Match register bits 39:32
Individual match bits 7:0
Individual match bits 15:8
Individual match bits 23:16
Individual match bits 31:24
Individual match bits 39:32
Associated Peripheral
73
MATCHREG1
MATCHREG2
MATCHREG3
MATCHREG4
MATCHBITS0
MATCHBITS1
MATCHBITS2
MATCHBITS3
MATCHBITS4
CTRL_STAT
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
74
75
76
80
81
82
83
84
88
Control (write)
register bits 7:0
/
status (read)
89
TEST_REG
Test register(s)
RTC
Note: ACMADDR bytes 1 to 40 pertain to the Analog Quads, while bytes 64 to 89 pertain to the RTC.
2-90
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
1
ACM Characteristics
ACMCLK
tSUEACM
tHEACM
ACMWEN
tSUDACM
tHDACM
ACMWDATA
D0
D1
A1
tSUAACM
tHAACM
ACMADDRESS
A0
Figure 2-73 • ACM Write Waveform
tMPWCLKACM
ACMCLK
ACMADDRESS
ACMRDATA
A0
A1
tCLKQACM
RD0
RD1
Figure 2-74 • ACM Read Waveform
Timing Characteristics
Table 2-43 • Analog Configuration Multiplexer (ACM) Timing
Commercial-Case Conditions: TJ = 25°C, Typical Case, VCC = 1.5 V
Parameter
tCLKQACM
tSUDACM
Description
Clock-to-Q of the ACM
Min.
10
10
0
Typ.
Max.
Units
ns
Data Setup time for the ACM
ns
tHDACM
Data Hold time for the ACM
ns
tSUAACM
Address Setup time for the ACM
10
0
ns
tHAACM
Address Hold time for the ACM
ns
tSUEACM
Enable Setup time for the ACM
10
0
ns
tHEACM
Enable Hold time for the ACM
ns
tMPWARACM
tREMARACM
tRECARACM
tMPWCLKACM
Asynchronous Reset Minimum Pulse Width for the ACM
Asynchronous Reset Removal time for the ACM
Asynchronous Reset Recovery time for the ACM
Clock Minimum Pulse Width for the ACM
10
10
10
50
ns
ns
ns
ns
1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the rc_osc, byte_en, and
aq_wen signals have no impact.
Advanced v0.7
2-91
Fusion Family of Mixed-Signal Flash FPGAs
Analog Quad ACM Description
Table 2-44 maps out the Analog Configuration MUX (ACM) space associated with configuration of the Analog Quads
within the Analog Block. Table 2-44 shows the byte assignment within each quad and function of each bit within each
byte. Subsequent tables will explain each bit setting and how that corresponds to a particular configuration. After
3.3 V and 1.5 V is applied to Fusion, analog quad configuration registers are loaded with default setting until
initialization and configuration state machine changes it to user defined setting.
Table 2-44 • Analog Quad ACM Byte Assignment
Byte
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Signal (Bx)
B0[0]
B0[1]
B0[2]
B0[3]
B0[4]
B0[5]
B0[6]
B0[7]
B1[0]
B1[1]
B1[2]
B1[3]
B1[4]
B1[5]
B1[6]
B1[7]
B2[0]
B2[1]
B2[2]
B2[3]
B2[4]
B2[5]
B2[6]
B2[7]
B3[0]
B3[1]
B3[2]
B3[3]
B3[4]
B3[5]
B3[6]
B3[7]
Function
Default Setting
Byte 0
(AV)
Scaling factor control – pre-scaler Highest voltage Range
Analog MUX select
Pre-Scaler
Off
Current monitor switch
Direct analog input switch
Selects V-pad polarity
pre-scaler op-amp mode
Off
Positive
Power-down
Byte 1
(AC)
Scaling factor control – pre-scaler Highest voltage range
Analog MUX select
Pre-Scaler
Direct analog input switch
Selects C-pad polarity
Pre-scaler op-amp mode
Chip temperature monitor
Spare
Off
Positive
Power-down
Off
Byte 2
(AG)
–
Current drive control
Lowest current
Spare
–
–
Spare
Selects G-pad polarity
Selects low/high drive
Positive
Low drive
Byte 3
(AT)
Scaling factor control – pre-scaler Highest voltage range
Analog MUX select
Pre-Scaler
Off
Direct analog input switch
–
–
Pre-scaler op-amp mode
Power-down
2-92
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-45 details the settings available to control the pre-scaler values of the AV, AC, and AT pins. Note that the AT
pin has a reduced number of available pre-scaler values.
Table 2-45 • Pre-Scaler Control Truth Table (AV (x = 0), AC (x = 1), and AT (x = 3))
Scaling
LSB for an 8-Bit LSB for a 10-Bit LSB for a 12-Bit
Control Lines Factor Pad to
Conversion
(mV)
Conversion
(mV)
Conversion
(mV)
Full Scale
Voltage
Bx[2:0]
000*
001
ADC Input
0.15625
0.3125
0.625
1.25
Range Name
16 V
64
32
16
8
16
8
4
2
16.368 V
8.184 V
8 V
010*
011
4
1
4.092 V
4 V
2
0.5
2.046 V
2 V
100
2.5
4
1
0.25
0.125
0.0625
0.03125
1.023 V
1 V
101
5.0
2
0.5
0.25
0.125
0.5115 V
0.25575 V
0.127875 V
0.5 V
110
10.0
1
0.25 V
0.125 V
111
20.0
0.5
Note: *These are the only valid ranges for the Temperature Monitor Block Pre-Scaler.
Table 2-46 details the settings available to control the
MUX within each of the AV, AC, and AT circuits. This
MUX determines whether the signal routed to the ADC is
the direct analog input, prescaled signal, or output of
either current monitor or temperature monitor blocks.
Table 2-48 details the settings available to control the
polarity of the signals coming to the AV, AC, and AT pins.
Note that the only valid setting for the AT pin is logic 0
to support positive voltages.
Table 2-48 • Voltage Polarity Control Truth Table (AV (x =
0), AC (x = 1), and AT (x = 3)*)
Table 2-46 • Analog Multiplexer Truth Table (AV (x = 0),
AC (x = 1), and AT (x = 3))
Control Lines
Bx[6]
Input Signal Polarity
Positive
Control Lines
Bx[4]*
Control Lines
Bx[3]
ADC Connected To
Pre-scaler
0
1
0
0
1
0
1
0
Negative
Direct input
Note: *The B3[6] signal for the AT pad should be kept at a
logic level 0 to accept only positive voltages.
Current
amplifier/
Temperature Monitor
Table 2-49 details the settings available to either power
down or enable the pre-scaler associated with the
analog inputs AV, AC, and AT.
1
1
Not valid
Note: *This pin is not available for the Voltage Monitor Block.
Table 2-49 • Pre-Scaler Op-Amp Power-Down Truth Table
Table 2-47 details the settings available to control the
Direct Analog Input switch for the AV, AC, and ACT pins.
(AV (x = 0), AC (x = 1), and AT (x = 3))
Control Lines
Table 2-47 • Direct Analog Input Switch Control Truth
Bx[7]
Pre-Scaler Op-Amp
Power-down
Table (AV (x = 0), AC (x = 1), and AT (x = 3))
0
1
Control Lines
Bx[5]
Direct Input Switch
Operational
0
1
Off
On
Advanced v0.7
2-93
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-50 details the settings available to enable the
current monitor block associated with the AC pin.
Table 2-52 details the settings available to set the
polarity of the gate driver (either P-channel or
N-Channel type devices).
Table 2-50 • Current Monitor Input Switch Control Truth
Table (AV (x = 0))
Table 2-52 • Gate Driver Polarity Truth Table (AG)
Control Lines
Control Lines
B0[4]
Current Monitor Input Switch
B2[6]
Gate Driver Polarity
Positive
0
1
Off
On
0
1
Negative
Table 2-51 details the settings available to configure the
drive strength of the gate drive when not in high drive
mode.
Table 2-53 details the settings available to turn on the
Gate Driver and set whether the high drive mode is on or
off.
Table 2-51 • Low Drive Gate Driver Current Truth Table (AG)
Table 2-53 • Gate Driver Control Truth Table (AG)
Control Lines
B2[3]
Control Lines
B2[2]
Control Lines
Current (µA)
B2[7]
GDON
Gate Driver
Off
0
0
1
1
0
1
0
1
1
3
0
0
1
1
0
1
0
1
Low drive on
Off
10
30
High drive on
2-94
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
User I/Os
Introduction
I/O Banks and I/O Standards Compatibility
Fusion devices feature a flexible I/O structure, supporting
a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V)
through a bank-selectable voltage. Table 2-55, Table 2-56,
Table 2-57, and Table 2-58 on page 2-98 show the
voltages and the compatible I/O standards. I/Os provide
programmable slew rates, drive strengths, weak pull-up,
and weak pull-down circuits. 3.3 V PCI and 3.3 V PCI-X are
5 V tolerant. See the "5 V Input Tolerance" section on
page 2-107 for possible implementations of 5 V tolerance.
The digital I/Os are grouped into I/O voltage banks. There
are three digital I/O banks on the AFS090 and AFS250
devices and four digital I/O banks on the AFS600 and
AFS1500 devices. Figure 2-89 on page 2-120 and Figure 2-
90 on page 2-121 show the bank configuration by device.
The north side of I/O in the AFS600 and AFS1500 devices is
comprised of two banks of Actel Pro I/Os. The Actel Pro I/Os
support a wide number of voltage referenced I/O standards
in addition to the multitude of single-ended and
differential I/O standards common throughout all of the
Actel digital I/Os. Each I/O voltage bank has dedicated
input/output supply and ground voltages (VMV/GNDQ for
input buffers and VCCI/GND for output buffers). Because of
these dedicated supplies, only I/Os with compatible
standards can be assigned to the same I/O voltage bank.
Table 2-56 and Table 2-57 on page 2-97 show the required
voltage compatibility values for each of these voltages.
All I/Os are in a known state during power-up and any
power-up sequence is allowed without current impact.
Refer to the "I/O Power-Up and Supply Voltage
Thresholds for Power-On Reset (Commercial and
Industrial)" section on page 3-4 for more information.
On low power standby or sleep mode (VCC is OFF, VCC33A
is ON; VCCI is ON) or when the resource is not used,
digital inputs are tristated; digital outputs are tristated;
digital bibufs (input/output) are tristated.
For more information about I/O and global assignments
to I/O banks, refer to the specific pin table of the device
in the "Package Pin Assignments" section on page 4-1
and the "User I/O Naming Convention" section on
page 2-120.
I/O Tile
The Fusion I/O tile provides a flexible, programmable
structure for implementing a large number of I/O
standards. In addition, the registers available in the I/O
tile in selected I/O banks can be used to support high-
performance register inputs and outputs, with register
enable if desired (Figure 2-75 on page 2-96). The
registers can also be used to support the JESD-79C
Double Data Rate (DDR) standard within the I/O
structure (see the "Double Data Rate (DDR) Support"
section on page 2-102 for more information).
Each Pro I/O bank is divided into minibanks. Any user I/O
in a VREF minibank (a minibank is the region of scope of
a VREF pin) can be configured as a VREF pin (Figure 2-75
on page 2-96). Only one VREF pin is needed to control the
entire VREF minibank. The location and scope of the VREF
minibanks can be determined by the I/O name. For
details, see the "User I/O Naming Convention" section on
page 2-120.
Table 2-57 on page 2-97 shows the I/O standards
supported by the Fusion devices and the corresponding
voltage levels.
As depicted in Figure 2-76 on page 2-101, all I/O registers
share one CLR port. The output register and output
enable register share one CLK port. Refer to the "I/O
Registers" section on page 2-101 for more information.
I/O standards are compatible if:
•
•
Their VCCI and VMV values are identical
If both of the standards need a VREF, their VREF
values must be identical (Pro I/O only)
Advanced v0.7
2-95
Fusion Family of Mixed-Signal Flash FPGAs
CCC
CCC
CCC
Bank 0
Bank 1
Up to five VREF
minibanks within
an I/O bank
Common VREF
V
REF signal scope is
signal for all I/Os
in VREF minibanks
between 8 and 18 I/Os.
If needed, the VREF for a given
minibank can be provided by
any I/O within the minibank.
I/O Pad
Figure 2-75 • Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side of AFS600 and AFS1500)
Table 2-54 • I/O Standard Supported by Bank Type
Differential I/O
I/O Bank
Single-Ended I/O Standard
Standard
Voltage-Referenced
Hot-Swap
Hot-Swap LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V/1.8 V/
1.5 V, LVCMOS2.5/5.0 V
–
–
Yes
LVDS
LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V/1.8 V/ LVPECL and LVDS
1.5 V, LVCMOS2.5/5.0 V, 3.3 V PCI/3.3 V PCI-X
–
–
Pro I/O
LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V/1.8 V/ LVPECL and LVDS GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V,
Yes
1.5 V, LVCMOS2.5/5.0 V, 3.3 V PCI/3.3 V PCI-X
HSTL Class I and II, SSTL2 Class I and
II, SSTL3 Class I and II
2-96
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-55 • I/O Bank Support by Device
I/O Bank
AFS090
AFS250
AFS600
AFS1500
Hot-Swap
N
E, W
–
N
E, W
–
–
E, W
N
–
E, W
N
LVDS, BLVDS, M-LVDS
Pro I/O
Analog Quad
S
S
S
S
Note: E = East side of the device
W = West side of the device
N = North side of the device
S = South side of the device
Table 2-56 • Fusion VCCI Voltages and Compatible Standards
CCI and VMV (typical)
V
Compatible Standards
3.3 V
2.5 V
1.8 V
1.5 V
LVTTL/LVCMOS 3.3, PCI 3.3, SSTL3 (Class I and II)*, GTL+ 3.3, GTL 3.3*, LVPECL
LVCMOS 2.5, LVCMOS 2.5/5.0, SSTL2 (Class I and II)*, GTL+ 2.5*, GTL 2.5*, LVDS, BLVDS, M-LVDS
LVCMOS 1.8
LVCMOS 1.5, HSTL (Class I)*, HSTL (Class II)*
Note: *I/O standard supported by Pro I/O banks.
Table 2-57 • Fusion VREF Voltages and Compatible Standards*
V
REF (typical)
Compatible Standards
SSTL3 (Class I and II)
SSTL2 (Class I and II)
GTL+ 2.5, GTL+ 3.3
1.5 V
1.25 V
1.0 V
0.8 V
GTL 2.5, GTL 3.3
0.75 V
HSTL (Class I), HSTL (Class II)
Note: *I/O standard supported by Pro I/O banks.
Advanced v0.7
2-97
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-58 • Fusion Standard and LVDS I/O Features
3.3 V
2.5 V
–
0.80 V
1.00 V
1.50 V
–
0.80 V
1.00 V
1.25 V
–
1.8 V
1.5 V
–
0.75 V
Note: White box: Allowable I/O standard combinations.
Gray box: Illegal I/O standard combinations.
2-98
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Features Supported on Every I/O
Table 2-59 lists all features supported by transmitter/receiver for single-ended and differential I/Os.
Table 2-59 • Fusion Pro I/O Features
Feature
Description
Single-ended and voltage-referenced
transmitter features
•
Hot insertion in every mode except PCI or 5 V input tolerant (these modes use
clamp diodes and do not allow hot insertion)
•
•
•
•
Activation of hot insertion (disabling the clamp diode) is selectable by I/Os
Weak pull-up and pull-down
Two slew rates
Skew between output buffer enable/disable time: 2 ns delay (rising edge) and 0
ns delay (falling edge) (see "Selectable Skew Between Output Buffer Enable/Dis-
able Time" on page 2-112 for more information)
•
•
•
Five drive strengths
5 V tolerant receiver ("5 V Input Tolerance" section on page 2-107)
LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs ("5 V Output Toler-
ance" section on page 2-110)
•
•
•
•
High Performance (Table 2-63 on page 2-106)
Schmitt trigger option
Single-ended receiver features
ESD protection
Programmable Delay: 0 ns if bypassed, 0.625 ns with 000 setting, 6.575 ns with
111 setting, 0.85 ns intermediate delay increments (at 25C, 1.5V)
•
•
High performance (Table 2-63 on page 2-106)
Separate ground and power planes, GNDQ/VMV, for input buffers only to avoid
output-induced noise in the input circuitry
Voltage-referenced differential receiver
features
•
Programmable Delay: 0 ns if bypassed, 0.625 ns with 000 setting, 6.575 ns with
111 setting, 0.85 ns intermediate delay increments (at 25°C, 1.5 V)
•
•
High performance (Table 2-63 on page 2-106)
Separate ground and power plane, GNDQ, and VMV pins for input buffers only
to avoid output-induced noise in the input circuitry
CMOS-style LVDS, BLVDS, M-LVDS, or LVPECL • Two I/Os and external resistors are used to provide a CMOS style LVDS, BLVDS, M-
transmitter
LVDS, or LVPECL transmitter solution.
Activation of hot insertion (disabling the clamp diode) is selectable by I/Os
Weak pull-up and pull-down
•
•
•
•
•
•
Fast slew rate
LVDS/LVPECL differential receiver features
ESD protection
High performance (Table 2-63 on page 2-106)
Programmable Delay: 0.625 ns with 000 setting, 6.575 ns with 111 setting, 0.85
ns intermediate delay increments (at 25°C, 1.5 V)
•
Separate input buffer ground and power planes to avoid output-induced noise in
the input circuitry
Advanced v0.7
2-99
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-60 • Maximum I/O Frequency for Single-Ended, Voltage-Referenced, and Differential I/Os
Specification
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI
Performance Up To
200 MHz
250 MHz
200 MHz
130 MHz
200 MHz
200 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
350 MHz
200 MHz
200 MHz
300 MHz
PCI-X
HSTL-I
HSTL-II
SSTL2-I
SSTL2-II
SSTL3-I
SSTL3-II
GTL+ 3.3 V
GTL+ 2.5 V
GTL 3.3 V
GTL 2.5 V
LVDS
BLVDS
M-LVDS
LVPECL
2-100
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to Figure 2-76 for a simplified
representation of the I/O block.
The number of input registers is selected by a set of switches (not shown in Figure 2-76) between registers to
implement single or differential data transmission to and from the FPGA core. The Designer software sets these
switches for the user.
A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does
not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O registers combining must satisfy some
rules.
1
I/O / Q0
2
Input
Reg
Input
Reg
Y
Pull-Up/Down
Resistor Control
CLR/PRE
To FPGA Core
3
I/O / Q1
Input
Reg
PAD
ICE
CLR/PRE
I/O / ICLK
Signal Drive Strength
and Slew-Rate Control
E = Enable Pin
A
4
I/O / D0
Output
Reg
OCE
ICE
From FPGA Core
CLR/PRE
5
I/O / D1 / ICE
Output
Reg
CLR/PRE
I/O / OCLK
I/O / OE
6
Output
Enable
Reg
OCE
CLR/PRE
I/O / CLR or I/O / PRE / OCE
Note: Fusion I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-102 for more
information).
Figure 2-76 • I/O Block Logical Representation
Advanced v0.7
2-101
Fusion Family of Mixed-Signal Flash FPGAs
incoming data, which is presented to the core on each
rising edge of the I/O register clock.
Double Data Rate (DDR) Support
Fusion Pro I/Os support 350 MHz DDR inputs and
outputs. In DDR mode, new data is present on every
transition of the clock signal. Clock and data lines have
identical bandwidths and signal integrity requirements,
making it very efficient for implementing very high-
speed systems.
Each I/O tile on Fusion devices supports DDR inputs.
Output Support for DDR
The basic DDR output structure is shown in Figure 2-78
on page 2-103. New data is presented to the output
every half clock cycle. Note: DDR macros and I/O registers
do not require additional routing. The combiner
automatically recognizes the DDR macro and pushes its
registers to the I/O register area at the edge of the chip.
The routing delay from the I/O registers to the I/O buffers
is already taken into account in the DDR macro.
DDR interfaces can be implemented using HSTL, SSTL,
LVDS, and LVPECL I/O standards. In addition, high-speed
DDR interfaces can be implemented using LVDS I/O.
Input Support for DDR
The basic structure to support a DDR input is shown in
Figure 2-77. Three input registers are used to capture
Refer to the Actel application note Using DDR for Fusion
Devices for more information.
Input DDR
A
D
Out_QF
(To Core)
Data
INBUF
FF1
E
B
Out_QR
(To Core)
CLK
CLKBUF
FF2
C
CLR
INBUF
DDR_IN
Figure 2-77 • DDR Input Register Support in Fusion Devices
2-102
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
A
Data_F
(From Core)
FF1
FF2
Out
B
C
D
0
CLK
E
CLKBUF
OUTBUF
1
Data_R
(From Core)
B
C
CLR
INBUF
DDR_OUT
Figure 2-78 • DDR Output Support in Fusion Devices
Advanced v0.7
2-103
Fusion Family of Mixed-Signal Flash FPGAs
Hot-Swap Support
Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a
powered-up system. The levels of hot-swap support and examples of related applications are described in Table 2-61.
The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required.
Table 2-61 • Levels of Hot-Swap Support
Device
Example of
Hot
Power
Card
Circuitry
Application with
Swapping
Level
Applied
Ground Connected Cards that Contain
Fusion Devices
Compliance of
Fusion Devices
Description to Device Bus State Connection to Bus Pins
1
Cold-Swap
No
–
–
–
System and card with Compliant I/Os can but
Actel FPGA chip are do not have to be set to
powered down, then the hot-insertion mode.
card gets plugged into the
system, then the power
supplies are turned on for
the system but not for the
FPGA on the card.
2
Hot-Swap
while reset
Yes
Held in reset Mustbemade
–
In
PCI
hot-plug Compliant I/Os can but
Reset do not have to be set to
state
and
specification,
maintained
for 1 msec
before,
during, and
after
control circuitry isolates hot-insertion mode.
the card busses until the
card supplies are at their
nominal operating levels
and stable.
insertion/
removal
3
Hot-Swap
Yes
Held idle (no Same as Level Must remain Board bus shared with Compliant with cards
while bus idle
ongoing I/O
processes
during
insertion/
removal)
2
glitch-free card bus is "frozen," and with two levels of
during there is no toggling staging. I/Os have to be
power- up or activity on the bus,. It is set to hot-insertion
power-down critical that the logic mode.
states set on the bus
signal
do
not
get
disturbed during card
insertion/removal.
4
Hot-Swap on
an active bus
Yes
Busmayhave Same as Level
Same as There is activity on the Compliant with cards
active I/O
processes
2
Level 3
system bus, and it is with two levels of
critical that the logic staging. I/Os have to be
states set on the bus set to hot-insertion
ongoing, but
device being
inserted or
removed
signal
do
not
get mode.
disturbed during card
insertion/removal.
must be idle
2-104
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
For Fusion devices requiring level 3 and/or level 4
compliance, the board drivers connected to Fusion I/Os
need to have 10 kΩ (or lower) output drive resistance at
hot insertion, and 1 kΩ (or lower) output drive resistance
at hot removal. This resistance is the transmitter
resistance sending signal towards the Fusion I/O and no
additional resistance is needed on the board. If that
cannot be assured, three levels of staging can be used to
meet level 3 and/or level 4 compliance. Cards with two
levels of staging should have the following sequence:
calculated based on decoupling capacitance on a given
power supply on the board (this decoupling capacitor is
in parallel with this resistor). The RC constant should
ensure full discharge of supplies before cold-sparing
functionality is required. The resistor is necessary to
ensure that the power pins get discharged to ground
every time there is an interruption of power supply on
the device.
Electrostatic Discharge (ESD) Protection
Fusion devices are tested per JEDEC Standard JESD22-
A114-B.
•
•
Grounds
Powers, I/Os, other pins
Fusion devices contain clamp diodes at every I/O, global,
and power pad. Clamp diodes protect all device pads
against damage from ESD as well as from excessive
voltage transients.
Cold-Sparing Support
Cold-sparing means that a subsystem with no power
applied (usually a circuit board) is electrically connected
to the system that is in operation. This means that all
input buffers of the subsystem must present very high
input impedance with no power applied so as not to
disturb the operating portion of the system.
Each I/O has two clamp diodes. One diode has its
positive (P) side connected to the pad and its negative
(N) side connected to VCCI. The second diode has its P
side connected to GND, and its N side connected to the
pad. During operation, these diodes are normally
biased in the Off state, except when transient voltage is
significantly above VCCI or below GND levels.
Fusion devices support cold-sparing for all I/O
configurations. Configurations such as PCI standard
requiring clamp diodes on the I/Os can also achieve cold-
sparing compliance as the clamp diodes get disconnected
internally when the supplies are at 0 V.
By selecting the appropriate I/O configuration, the diode
is turned on or off. Refer to Table 2-62 for more
information about the I/O standards and the clamp
diode.
In designs where Fusion devices are expected to be
cold-sparing compliant after supplies are turned off, a
discharge resistor, switched resistor, or discharge path
needs to be provided from each power supply to ground.
If the resistor is chosen, the resistor value must be
The second diode is always connected to the pad,
regardless of the I/O configuration selected.
Table 2-62 • Fusion Standard, LVDS, and Standard Plus Hot-Swap I/O Hot-Swap and 5 V Input Tolerance Capabilities
Clamp Diode Hot Insertion
5 V Input Tolerance1
Standard Standard Standard Standard Standard Standard
Hot-
Swap I/O
and LVDS Hot-Swap and LVDS Hot-Swap and LVDS
Input
Buffer
Output
Buffer
I/O Assignment
3.3 V LVTTL/LVCMOS
3.3 V PCI, 3.3 V PCI-X
LVCMOS 2.5 V
I/O
Yes
Yes
Yes
Yes
Yes
Yes
Yes
I/O
Yes
N/A
Yes
Yes
Yes
Yes
N/A
I/O
No
No
No
No
No
No
No
I/O
Yes1
N/A
Yes1
Yes1
No
I/O
Yes1
Yes1
Yes2
Yes2
No
No
N/A
No
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
LVCMOS 2.5 V / 5.0 V
LVCMOS 1.8 V
No
No
LVCMOS 1.5 V
No
No
No
Differential, LVDS/BLVDS/
M-LVDS/ LVPECL 3
N/A
N/A
No
Notes:
1. Can be implemented with an external IDT bus switch, resistor divider, or zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. Bidirectional LVPECL buffers are not supported. I/Os can either be configured as input buffers or output buffers.
Advanced v0.7
2-105
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-63 • Fusion Pro I/O Hot-Swap and 5 V Input Tolerance Capabilities
5 V Input
Tolerance
I/O Assignment
Clamp Diode Hot Insertion
Input Buffer Output Buffer
Enabled/Disabled
3.3 V LVTTL/LVCMOS
3.3 V PCI, 3.3 V PCI-X
LVCMOS 2.5 V 3
No
Yes
No
Yes
No
No
No
No
Yes
No
Yes1
Yes1
No
Enabled/Disabled
Yes
No
Enabled/Disabled
LVCMOS 2.5 V / 5.0 V 3
Yes2
Enabled/Disabled
LVCMOS 1.8 V
Yes
Yes
Yes
Yes
No
Enabled/Disabled
LVCMOS 1.5 V
No
Enabled/Disabled
Voltage-Referenced Input Buffer
Differential, LVDS/BLVDS/M-LVDS/LVPECL4
Notes:
No
Enabled/Disabled
No
Enabled/Disabled
1. Can be implemented with an external IDT bus switch, resistor divider, or zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. In the SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User's Guide, select the LVCMOS5 macro for
the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O standard.
4. Bidirectional LVPECL buffers are not supported. I/Os can either be configured as input buffers or output buffers.
2-106
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Example 1 (high speed, high current):
5 V Input Tolerance
Rtx_out_high = Rtx_out_low = 10 Ω
I/Os can support 5 V input tolerance when LVTTL 3.3 V,
LVCMOS 3.3 V, LVCMOS 2.5 V / 5 V, and LVCMOS 2.5 V
configurations are used (see Table 2-64 on page 2-110
for more details). There are four recommended solutions
(see Figure 2-79 to Figure 2-82 on page 2-110 for details
of board and macro setups) to achieve 5 V receiver
tolerance. All the solutions meet a common requirement
of limiting the voltage at the I/O input to 3.6 V or less. In
fact, the I/O absolute maximum voltage rating is 3.6 V,
and any voltage above 3.6 V may cause long-term gate
oxide failures.
R1 = 36 Ω (+/–5%), P(r1)min = 0.069 Ω
R2 = 82 Ω (+/–5%), P(r2)min = 0.158 Ω
Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 +10) = 45.04 mA
t
RISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes
up to 25% safety margin)
tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up
to 25% safety margin)
Example 2 (low-medium speed, medium current):
Rtx_out_high = Rtx_out_low = 10 Ω
Solution 1
R1 = 220 Ω (+/–5%), P(r1)min = 0.018 Ω
The board-level design needs to ensure that the
reflected waveform at the pad does not exceed the limits
provided in Table 3-4 on page 3-3. This is a long-term
reliability requirement.
R2 = 390 Ω (+/–5%), P(r2)min = 0.032 Ω
Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 +10) = 9.17 mA
t
RISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up
to 25% safety margin)
tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up
This scheme will also work for
a
3.3 V PCI / PCI-X
configuration, but the internal diode should not be used for
clamping, and the voltage must be limited by the two
external resistors as explained below. Relying on the
diode clamping would create an excessive pad DC
voltage of 3.3 V + 0.7 V = 4 V.
to 25% safety margin)
Other values of resistors are also allowed as long as the
resistors are sized appropriately to limit the voltage at
the receiving end to 2.5 V < Vin(rx) < 3.6 V* when the
transmitter sends a logic '1'. This range of Vin_dc(rx)
must be assured for any combination of transmitter
supply (5 V +/- 0.5 V), transmitter output resistance, and
board resistor tolerances.
Here are some examples of possible resistor values
(based on a simplified simulation model with no line
effects, and 10 Ω transmitter output resistance, where
Rtx_out_high = (VCCI – VOH)/ IOH, Rtx_out_low = VOL / IOL).
Temporary overshoots are allowed according to Table 3-4
on page 3-3.
Solution 1
Fusion I/O Input
On-Chip
Off-Chip
3.3 V
5.5 V
Rext1
Rext2
Requires two board resistors,
LVCMOS 3.3 V I/Os
Figure 2-79 • Solution 1
Advanced v0.7
2-107
Fusion Family of Mixed-Signal Flash FPGAs
Solution 2
The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4
on page 3-3. This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping,
and the voltage must be limited by the external resistors and zener, as shown in Figure 2-80. Relying on the diode
clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 2
Fusion I/O Input
Off-Chip On-Chip
3.3 V
5.5 V
Rext1
Zener
3.3 V
Requires one board resistor, one
Zener 3.3 V diode, LVCMOS 3.3 V I/Os
Figure 2-80 • Solution 2
2-108
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Solution 3
The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4
on page 3-3. This is a long-term reliability requirement.
This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping,
and the voltage must be limited by the bus switch, as shown in Figure 2-81. Relying on the diode clamping would
create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 3
Fusion I/O Input
Off-Chip
Bus
On-Chip
3.3 V
Switch
IDTQS32X23
5.5 V
5.5 V
Requires a bus switch on the board,
LVTTL/LVCMOS 3.3 V I/Os.
Figure 2-81 • Solution 3
Advanced v0.7
2-109
Fusion Family of Mixed-Signal Flash FPGAs
Solution 4
Solution 4
Fusion I/O Input
Off-Chip
5.5 V
On-Chip
2.5 V On-Chip
3.3 V
Clamp
Diode
Rext1
Requires one board resistor.
Available for all LVDS I/O standards
excluding 3.3 V I/O standards.
Figure 2-82 • Solution 4
Table 2-64 • Comparison Table for 5-V-Compliant Receiver Scheme
Scheme
Board Components
Two resistors
Speed
Current Limitations
1
2
3
4
Low to High1 Limited by transmitter's drive strength
Resistor and Zener 3.3 V
Bus switch
Minimum resistor value2
Medium
High
Limited by transmitter's drive strength
N/A
Medium
Maximum diode current at 100% duty cycle, signal constantly at "1"
•
•
•
R = 47 Ω at TJ = 70°C
R = 150 Ω at TJ = 85°C
R = 420 Ω at TJ = 100°C
•
•
•
52.7 mA at TJ =70°C / 10-year lifetime
16.5 mA at TJ = 85°C / 10-year lifetime
5.9 mA at TJ = 100°C / 10-year lifetime
For duty cycles other than 100%, the currents can be increased by
a factor = 1/duty cycle
Example: 20% duty cycle at 70°C
Maximum current = (1/0.2) * 52.7 mA = 5 * 52.7 mA = 263.5 mA
Notes:
1. Speed and current consumption increase as the board resistance values decrease.
2. Resistor values ensure I/O diode long term reliability.
5 V Output Tolerance
Fusion I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS
mode to reliably drive 5 V TTL receivers. It is also critical
that there be NO external I/O pull-up resistor to 5 V, since
this resistor would pull the I/O pad voltage beyond the
3.6 V absolute maximum value, and consequently cause
damage to the I/O.
When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, Fusion I/Os
can directly drive signals into 5 V TTL receivers. In fact,
VOL = 0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and 3.3 V
LVCMOS modes exceed the VIL = 0.8 V and VIH = 2 V level
requirements of 5 V TTL receivers. Therefore, level '1'
and level '0' will be recognized correctly by 5 V TTL
receivers.
2-110
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Simultaneous Switching Outputs and Printed Circuit Board Layout
Simultaneously switching outputs (SSO) can produce
signal integrity problems on adjacent signals that are not
part of SSO bus. Both inductive and capacitive coupling
parasitics of bond wires inside packages and of traces on
PCB boards will transfer noise from SSO busses onto
signals adjacent to those busses. Additionally, SSOs can
produce ground bounce noise and VCCI dip noise. These
two noise types are caused by rapidly changing currents
through GND and VCCI package pin inductances during
switching activities:
In-package shielding can be achieved in several ways; the
required shielding will vary depending on whether pins
next to SSO bus are LVTTL/LVCMOS inputs, LVTTL/
LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL inputs
and outputs. Board traces in the vicinity of the SSO bus
have to be adequately shielded from mutual coupling
and inductive noise that can be generated by SSO bus.
Also, noise generated by SSO bus needs to be reduced
inside the package.
Printed circuit boards (PCB) perform an important
function in feeding stable supply voltage to the IC and at
the same time maintain signal integrity between devices.
•
•
Ground bounce noise voltage = L (GND) * di/dt
CCI dip noise voltage = L (VCCI) * di/dt
V
Key issues that need to considered are:
Any group of four or more input pins switching on the
same clock edge is considered an SSO bus. The shielding
should be done both on the board and inside the
package unless otherwise described.
•
Power and Ground plane design and decoupling
network design
•
Transmission Line Reflections and Terminations
Advanced v0.7
2-111
Fusion Family of Mixed-Signal Flash FPGAs
Selectable Skew Between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion
(disable) time.
Output Enable
ENABLE (IN)
(from FPGA core)
ENABLE (OUT)
MUX
Skew Circuit
I/O Output
Buffers
Skew Select
Figure 2-83 • Block Diagram of Output Enable Path
ENABLE (IN)
ENABLE (OUT)
Less than
0.1 ns
Less than
0.1 ns
Figure 2-84 • Timing Diagram (Option1: Bypasses Skew Circuit)
ENABLE (IN)
ENABLE (OUT)
1.2 ns
(typical)
Less than
0.1 ns
Figure 2-85 • Timing Diagram (Option 2: Enables Skew Circuit)
2-112
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
At the system level, the skew circuit can be used in
applications where transmission activities on
skew circuit implementation in
a
bidirectional
communication system. Figure 2-87 shows how bus
contention is created, and Figure 2-88 on page 2-114
shows how it can be avoided with the skew circuit.
bidirectional data lines need to be coordinated. This
circuit, when selected, provides a timing margin that can
prevent bus contention and subsequent data loss and/or
transmitter overstress due to transmitter-to-transmitter
current shorts. Figure 2-86 presents an example of the
Transmitter
ENABLE/
DISABLE
Transmitter 1: Fusion I/O
Transmitter 2: Generic I/O
Routing
Skew or
Routing
EN(b1)
EN(b2)
EN(r1)
ENABLE(t2)
Bypass
Skew
Delay (t1)
Delay (t2)
ENABLE(t1)
Bidirectional Data Bus
Figure 2-86 • Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using Fusion Devices
EN (b1)
EN (b2)
ENABLE (r1)
ENABLE (t1)
Transmitter 1: OFF
ENABLE (t2)
Transmitter 1: OFF
Transmitter 1: ON
Transmitter 2: ON
Transmitter 2: OFF
Bus
Contention
Figure 2-87 • Timing Diagram (Bypasses Skew Circuit)
Advanced v0.7
2-113
Fusion Family of Mixed-Signal Flash FPGAs
EN (b1)
EN (b2)
ENABLE (t1)
Transmitter 1: OFF
ENABLE (t2)
Transmitter 1: OFF
Transmitter 1: ON
Transmitter 2: ON
Transmitter 2: OFF
Result: No Bus Contention
Figure 2-88 • Timing Diagram (with Skew Circuit Selected)
The output slew rate and multiple drive strength
controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS
2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and
LVCMOS 1.5 V. All other I/O standards have a high output
slew rate by default.
Weak Pull-Up and Weak Pull-Down
Resistors
Fusion devices support optional weak pull-up and pull-
down resistors per I/O pin. When the I/O is pulled up, it is
connected to the VCCI of its corresponding I/O bank.
When it is pulled-down it is connected to GND. Refer to
Table 2-80 on page 2-131 for more information.
For Fusion slew rate and drive strength specifications,
refer to the appropriate I/O bank table:
•
•
•
Fusion hot-swap I/O (Table 2-65 on page 2-115)
Fusion LVDS I/O (Table 2-66 on page 2-115)
Fusion Pro I/O (Table 2-67 on page 2-115)
Slew Rate Control and Drive Strength
Fusion devices support output slew rate control: high
and low. The Standard hot-swap I/Os do not support slew
rate control. The high slew rate option is recommended
to minimize the propagation delay. This high-speed
option may introduce noise into the system if
appropriate signal integrity measures are not adopted.
Selecting a low slew rate reduces this kind of noise but
adds some delays in the system. Low slew rate is
recommended when bus transients are expected. Drive
strength should also be selected according to the design
requirements and noise immunity of the system.
Table 2-69 on page 2-117 lists the default values for the
above selectable I/O attributes as well as those that are
preset for that I/O standard.
Refer to Table 2-65, Table 2-66, and Table 2-67 on
page 2-115 for SLEW and OUT_DRIVE settings. Table 2-68
on page 2-116 lists the I/O default attributes. Table 2-69
on page 2-117 lists the voltages for the supported I/O
standards.
2-114
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
OUT_DRIVE (mA)
Table 2-65 • Fusion Hot-Swap I/O Standards—OUT_DRIVE Settings
I/O Standards
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
2
✓
✓
✓
✓
4
✓
✓
✓
–
8
✓
✓
–
LVCMOS 1.8 V
LVCMOS 1.5 V
–
Table 2-66 • Fusion LVDS I/O Standards—SLEW and OUT_DRIVE Settings
OUT_DRIVE (mA)
I/O Standards
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
2
✓
✓
✓
✓
4
✓
✓
✓
✓
6
✓
✓
✓
–
8
✓
✓
✓
–
12
✓
✓
–
16
✓
–
Slew
High
High
High
High
Low
Low
Low
Low
LVCMOS 1.8 V
–
LVCMOS 1.5 V
–
–
Table 2-67 • Fusion Pro I/O Standards—SLEW and OUT_DRIVE Settings
OUT_DRIVE (mA)
I/O Standards
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
2
✓
✓
✓
✓
✓
4
✓
✓
✓
✓
✓
6
✓
✓
✓
✓
✓
8
✓
✓
✓
✓
✓
12
✓
16
✓
✓
✓
✓
–
24
✓
✓
✓
–
Slew
High
Low
Low
Low
Low
Low
✓
High
High
High
High
LVCMOS 2.5 V/5.0 V
LVCMOS 1.8 V
✓
✓
LVCMOS 1.5 V
✓
–
Advanced v0.7
2-115
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-68 • Fusion Pro I/O Default Attributes
I/O Standards
LVTTL/LVCMOS 3.3 V Refer to the
Refer to the
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
35pF
35 pF
35 pF
35 pF
35 pF
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
20 pF
20 pF
30 pF
30 pF
0 pF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
following tables for following tables for
more information:
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
more information:
•
•
•
Table 2-65
page 2-115
on • Table 2-65 on
page 2-115
Table 2-66
page 2-115
on • Table 2-66 on
page 2-115
Table 2-67
on • Table 2-67 on
page 2-115
PCI-X (3.3 V)
page 2-115
GTL+ (3.3 V)
GTL+ (2.5 V)
GTL (3.3 V)
GTL (2.5 V)
HSTL Class I
HSTL Class II
SSTL2 Class I and II
SSTL3 Class I and II
LVDS, BLVDS, M-LVDS
LVPECL
0 pF
2-116
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-69 • Fusion Pro I/O Supported Standards and the Corresponding VREF and VTT Voltages
Input/Output Supply
Input Reference Voltage
Board Termination Voltage
I/O Standard
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 2.5 V/5.0 V Input
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI 3.3 V
Voltage (VMVtyp/VCCI_TYP
)
(VREF_TYP
)
(VTT_TYP)
3.30 V
2.50 V
2.50 V
1.80 V
1.50 V
3.30 V
3.30 V
3.30 V
2.50 V
3.30 V
2.50 V
1.50 V
1.50 V
3.30 V
3.30 V
2.50 V
2.50 V
2.50 V
3.30 V
–
–
–
–
–
–
–
–
–
–
–
–
PCI-X 3.3 V
–
–
GTL+ 3.3 V
1.00 V
1.00 V
0.80 V
0.80 V
0.75 V
0.75 V
1.50 V
1.50 V
1.25 V
1.25 V
–
1.50 V
1.50 V
1.20 V
1.20 V
0.75 V
0.75 V
1.50 V
1.50 V
1.25 V
1.25 V
–
GTL+ 2.5 V
GTL 3.3 V
GTL 2.5 V
HSTL Class I
HSTL Class II
SSTL3 Class I
SSTL3 Class II
SSTL2 Class I
SSTL2 Class II
LVDS, BLVDS, M-LVDS
LVPECL
–
–
Advanced v0.7
2-117
Fusion Family of Mixed-Signal Flash FPGAs
I/O Software Support
In the Fusion development software, default settings have been defined for the various I/O standards that are
supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are
applicable for all I/O standards. Table 2-70 and Table 2-71 list the valid I/O attributes that can be manipulated by the
user for each I/O standard.
Single-ended I/O standards in Fusion support up to five different drive strengths.
Table 2-70 • Fusion Standard and LVDS I/O Attributes vs. I/O Standard Applications
SLEW
(output
only)
OUT_DRIVE
(output
only)
SKEW (all
macros with
OE)*
OUT_LOAD
(output
only)
I/O Standards
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
RES_PULL
COMBINE_REGISTER
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
PCI-X (3.3 V)
✓
LVDS, BLVDS,
M-LVDS
LVPECL
✓
Note: *This does not apply to the north I/O bank on AFS090 and AFS250 devices.
Table 2-71 • Fusion Pro I/O Attributes vs. I/O Standard Applications
I/O Standards
LVTTL/LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
PCI-X (3.3 V)
✓
GTL+ (3.3 V)
✓
✓
✓
GTL+ (2.5 V)
GTL (3.3 V)
2-118
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-71 • Fusion Pro I/O Attributes vs. I/O Standard Applications (Continued)
I/O Standards
GTL (2.5 V)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
HSTL Class I
HSTL Class II
SSTL2 Class I and II
SSTL3 Class I and II
LVDS, BLVDS, M-LVDS
LVPECL
Table 2-72 lists the default values for the above selectable I/O attributes as well as those that are preset for that I/O
standard. See Table 2-65, Table 2-66, and Table 2-67 on page 2-115 for SLEW and OUT_DRIVE settings.
Table 2-72 • I/O Default Attributes
SKEW)
(tribuf and
(output only) bibuf only) RES_PULL
OUT_LOAD
(output
only)
SLEW
OUT_DRIVE
I/O Standards
(output only)
COMBINE_REGISTER
LVTTL/LVCMOS 3.3 V Refer to the
Refer to the
Off
Off
Off
Off
Off
Off
Off
Off
None
None
None
None
None
None
None
None
35 pF
35 pF
35 pF
35 pF
35 pF
10 pF
10 pF
–
–
–
–
–
–
–
–
–
following tables for following tables for
more information:
LVCMOS 2.5 V
LVCMOS 2.5/5.0 V
LVCMOS 1.8 V
LVCMOS 1.5 V
PCI (3.3 V)
more information:
•
•
•
Table 2-65
page 2-115
on • Table 2-65 on
page 2-115
Table 2-66
page 2-115
on • Table 2-66 on
page 2-115
Table 2-67
on • Table 2-67 on
page 2-115
PCI-X (3.3 V)
page 2-115
LVDS, BLVDS,
M-LVDS
LVPECL
Off
None
–
–
Advanced v0.7
2-119
Fusion Family of Mixed-Signal Flash FPGAs
User I/O Naming Convention
Due to the comprehensive and flexible nature of Fusion device user I/Os, a naming scheme is used to show the details
of the I/O (Figure 2-89 and Figure 2-90 on page 2-121). The name identifies to which I/O bank it belongs, as well as the
pairing and pin polarity for differential I/Os.
I/O Nomenclature = Gmn/IOuxwByVz
Gmn is only used for I/Os that also have CCC access – i.e., global pins.
G
= Global
m
= Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east
middle), D (southeast corner), E (southwest corner), and F (west middle).
n
= Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1, or
C2. Figure 2-22 on page 2-25 shows the three input pins per each clock source MUX at the CCC location m.
u
x
= I/O pair number in the bank, starting at 00 from the northwest I/O bank in a clockwise direction.
= P (Positive) or N (Negative) for differential pairs, or R (Regular – single-ended) for the I/Os that support single-
ended and voltage-referenced I/O standards only. U (Positive-LVDS only) or V (Negative-LVDS only) restrict the I/O
differential pair from being selected as LVPECL pair.
w
= D (Differential Pair), P (Pair), S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out
to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded
out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For
Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency
does not meet the requirements for a true differential pair.
B
y
= Bank
= Bank number [0..3]. The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise
direction.
V
z
= Reference voltage
= Minibank number
Hot-Swap I/O Bank
CCC
"A"
CCC
"B"
Bank 0
Bank 3
Bank 1
AFS090
AFS250
CCC/PLL
"F"
CCC
"C"
Bank 3
Bank 1
CCC
"E"
CCC
"D"
Bank 2 (analog)
Analog Quads
Figure 2-89 • Naming Conventions of Fusion Devices with Three Digital I/O Banks
2-120
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Pro I/O Bank
CCC
"A"
CCC
"B"
Bank 0
Bank 1
Bank 4
Bank 2
AFS600
AFS1500
CCC/PLL
"F"
CCC/PLL
"C"
Bank 4
Bank 2
CCC
"E"
CCC
"D"
Bank 3 (analog)
Analog Quads
Figure 2-90 • Naming Conventions of Fusion Devices with Four I/O Banks
Advanced v0.7
2-121
Fusion Family of Mixed-Signal Flash FPGAs
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Y
Combinational Cell
Y
LVPECL
tPD = 0.56 ns
tPD = 0.49 ns
tDP = 1.60 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
LVTTL/LVCMOS
Output drive strength = 12 mA
High slew rate
tDP = 2.74 ns
tPD = 0.87 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
I/O Module
(Registered)
LVTTL/LVCMOS
Output drive strength = 24 mA
High slew rate
tDP = 2.39 ns
tPY= 1.31 ns
tPD = 0.51 ns
LVPECL
D
Q
I/O Module
(Non-Registered)
Combinational Cell
Y
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
tICLKQ = 0.63 ns
tISUD= 0.43 ns
tDP = 3.30 ns
tPD = 0.47 ns
Input LVTTL/LVCMOS
Clock
I/O Module
(Registered)
Register Cell
Register Cell
Combinational Cell
Y
tPY= 0.90 ns
D
Q
D
Q
D
Q
GTL+ 3.3V
tDP = 1.53 ns
I/O Module
tPD = 0.47 ns
(Non-Registered)
tPY= 1.51 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tOCLKQ = 0.63 ns
OSUD = 0.43 ns
LVDS,
BLVDS,
M-LVDS
t
Input LVTTL/LVCMOS
Clock
Input LVTTL/LVCMOS
Clock
tPY = 0.90 ns
tPY = 0.90 ns
Figure 2-91 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case VCC = 1.425 V
2-122
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
tPY
tPYS
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
tPY = MAX(tPY (R), tPY (F))
tPYS = MAX(tPYS (R), tPYS (F))
tDIN = MAX(tDIN (R), tDIN(F))
V
IH
Vtrip
Vtrip
VCC
VIL
PAD
Y
50%
50%
GND
tPY
(R)
tPY
(F)
tPYS
(R)
tPYS
(F)
VCC
50%
50%
DIN
GND
tDOUT
(R)
tDOUT
(F)
Figure 2-92 • Input Buffer Timing Model and Delays (example)
Advanced v0.7
2-123
Fusion Family of Mixed-Signal Flash FPGAs
tDOUT
D Q
tDP
PAD
DOUT
CLK
D
Standard Load
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
tDOUT
(F)
VCC
(R)
50%
50%
VCC
D
0 V
50%
50%
0 V
DOUT
PAD
VOH
Vtrip
Vtrip
VOL
tDP
(R)
tDP
(F)
Figure 2-93 • Output Buffer Model and Delays (example)
2-124
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
tEOUT
D Q
CLK
tZL,tZH,tHZ,tLZ, tZLS, tZHS
E
EOUT
D Q
CLK
PAD
DOUT
D
tEOUT= MAX(tEOUT (R), tEOUT (F))
VCC
I/O Interface
D
E
Vcc
50%
tEOUT (R)
50%
tEOUT (F)
Vcc
50%
tLZ
50%
50%
tZH
50%
tHZ
EOUT
PAD
t
VCCI
ZL
90% VCCI
V
V
trip
trip
VOL
10% VCCI
VCC
D
VCC
50%
50%
E
tEOUT (F)
tEOUT (R)
50%
Vcc
50%
tZHS
EOUT
PAD
50%
VOH
tZLS
V
V
trip
trip
VOL
Figure 2-94 • Tristate Output Buffer Timing Model and Delays (example)
Advanced v0.7
2-125
Fusion Family of Mixed-Signal Flash FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software Settings
Table 2-73 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial
Conditions
V
V
V
V
I
I
OH
IL
IH
OL
OH
OL
Drive
Strength
Slew
Rate
I/O Standard
Min, V
Max, V
Min, V
Max, V
Max, V
Min, V
mA
mA
3.3 V LVTTL /
12 mA
High
–0.3
0.8
2
3.6
0.4
2.4
12
12
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12 mA
12 mA
High
High
High
–0.3
–0.3
–0.3
0.7
1.7
3.6
3.6
3.6
0.7
1.7
12
12
12
12
12
12
0.35 * VCCI 0.65 * VCCI
0.30VCCI 0.7 * VCCI
0.45
VCCI – 0.45
0.25 * VCCI 0.75 * VCCI
Per PCI Specification
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
Per PCI-X Specification
25 mA2
25 mA2
35 mA
33 mA
8 mA
15 mA2
15 mA
18 mA
14 mA
21 mA
High
High
High
High
High
High
High
High
High
High
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
VREF – 0.05 VREF + 0.05
VREF – 0.05 VREF + 0.05
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
–
25
25
51
40
8
25
25
51
40
8
–
VREF – 0.1
VREF – 0.1
VREF – 0.1
VREF – 0.1
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
0.6
–
0.6
–
0.4
0.4
0.54
0.35
0.7
0.5
VCCI – 0.4
VCCI – 0.4
VCCI – 0.62
VCCI – 0.43
VCCI – 1.1
VCCI – 0.9
HSTL (II)
15
15
18
14
21
15
15
18
14
21
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
1. Currents are measured at 85°C junction temperature.
2. Output drive strength is below JEDEC specification.
2-126
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-74 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL
µA
10
IIH
µA
10
IIL
µA
15
IIH
µA
15
DC I/O Standards
3.3 V LVTTL /
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
3.3 V PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Notes:
1. Commercial range (0°C < TJ < 70°C)
2. Industrial range (–40°C < TJ < 85°C)
Advanced v0.7
2-127
Fusion Family of Mixed-Signal Flash FPGAs
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-75 • Summary of AC Measuring Points
Input Reference Voltage
Board Termination
Standard
(VREF_TYP
)
Voltage (VTT_REF
)
Measuring Trip Point (Vtrip)
3.3 V LVTTL /
–
–
1.4 V
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
–
–
–
–
–
–
–
–
1.2 V
0.90 V
0.75 V
0.285 * VCCI (RR)
0.615 * VCCI (FF))
3.3 V PCI-X
–
–
0.285 * VCCI (RR)
0.615 * VCCI (FF)
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
0.8 V
0.8 V
1.0 V
1.0 V
0.75 V
0.75 V
1.25 V
1.25 V
1.5 V
1.5 V
–
1.2 V
1.2 V
1.5 V
1.5 V
0.75 V
0.75 V
1.25 V
1.25 V
1.485 V
1.485 V
–
VREF
VREF
VREF
VREF
VREF
HSTL (II)
VREF
SSTL2 (I)
VREF
SSTL2 (II)
VREF
SSTL3 (I)
VREF
SSTL3 (II)
VREF
LVDS, BLVDS, M-LVDS
LVPECL
Cross point
Cross point
–
–
Table 2-76 • I/O AC Parameter Definitions
Parameter
Definition
tDP
Data to Pad delay through the Output Buffer
tPY
Pad to Data delay through the Input Buffer with Schmitt trigger disabled
Data to Output Buffer delay through the I/O interface
tDOUT
tEOUT
tDIN
tPYS
tHZ
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Pad to Data delay through the Input Buffer with Schmitt trigger enabled
Enable to Pad delay through the Output Buffer—high to Z
tZH
Enable to Pad delay through the Output Buffer—Z to high
tLZ
Enable to Pad delay through the Output Buffer—low to Z
tZL
Enable to Pad delay through the Output Buffer—Z to low
tZHS
tZLS
Enable to Pad delay through the Output Buffer with delayed enable—Z to high
Enable to Pad delay through the Output Buffer with delayed enable—Z to low
2-128
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-77 • Summary of I/O Timing Characteristics – Software Default Settings
–2 Speed Grade, Commercial-Case Conditions: TJ= 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
I/O Standard
3.3 V LVTTL /
12 mA
High
35
–
0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81
ns
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
12 mA
12 mA
12 mA
High
High
High
35
35
35
10
10
–
–
–
0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28
0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98
0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
ns
ns
ns
ns
ns
Per PCI spec High
25 2 0.49 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.45 2.70 3.80 3.16
25 2 0.49 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.45 2.70 3.80 3.16
3.3 V PCI-X
Per PCI-X
spec
High
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25 mA
25 mA
35 mA
33 mA
8 mA
High
High
High
High
High
High
High
High
High
High
High
10
10
10
10
20
20
30
30
30
30
–
25 0.49 1.55 0.03 2.19
25 0.49 1.59 0.03 1.83
25 0.49 1.53 0.03 1.19
25 0.49 1.65 0.03 1.13
50 0.49 2.37 0.03 1.59
25 0.49 2.26 0.03 1.59
50 0.49 1.59 0.03 1.00
25 0.49 1.62 0.03 1.00
50 0.49 1.72 0.03 0.93
25 0.49 1.54 0.03 0.93
–
–
–
–
–
–
–
–
–
–
–
0.32 1.52 1.55
0.32 1.61 1.59
0.32 1.56 1.53
0.32 1.68 1.57
0.32 2.42 2.35
0.32 2.30 2.03
0.32 1.62 1.38
0.32 1.65 1.32
0.32 1.75 1.37
0.32 1.57 1.25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.19 3.22
3.28 3.26
3.23 3.20
3.35 3.24
4.09 4.02
3.97 3.70
3.29 3.05
3.32 2.99
3.42 3.04
3.24 2.92
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL (II)
15 mA
15 mA
18 mA
14 mA
21 mA
24 mA
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
LVDS, BLVDS,
M-LVDS
–
0.49 1.57 0.03 1.51
–
–
–
–
–
LVPECL
24 mA
High
–
–
0.49 1.60 0.03 1.31
–
–
–
–
–
–
–
–
ns
Notes:
1. For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-99 on page 2-143 for connectivity.
This resistor is not required during normal operation.
Detailed I/O DC Characteristics
Table 2-78 • Input Capacitance
Symbol
CIN
Definition
Input capacitance
Conditions
Min.
Max.
Units
pF
VIN = 0, f = 1.0 MHz
8
8
CINCLK
Input capacitance on the clock pin VIN = 0, f = 1.0 MHz
pF
Advanced v0.7
2-129
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-79 • I/O Output Buffer Maximum Resistances1
RPULL-DOWN
(Ohms)2
100
50
RPULL-UP
(Ohms)3
300
150
75
Standard
Drive Strength
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
8 mA
12 mA
16 mA
24 mA
4 mA
25
17
50
11
33
2.5 V LVCMOS
1.8 V LVCMOS
100
50
200
100
50
8 mA
12 mA
16 mA
24 mA
2 mA
25
20
40
11
22
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
12 mA
16 mA
2 mA
20
22
20
22
1.5 V LVCMOS
200
100
67
224
112
75
4 mA
6 mA
8 mA
33
37
12 mA
Per PCI/PCI-X specification
25 mA
25 mA
35 mA
33 mA
8 mA
33
37
3.3 V PCI/PCI-X
3.3 V GTL
2.5 V GTL
3.3 V GTL+
2.5 V GTL+
HSTL (I)
25
75
11
–
14
–
12
–
15
–
50
50
HSTL (II)
15 mA
15 mA
18 mA
14 mA
21 mA
25
25
SSTL2 (I)
27
31
SSTL2 (II)
SSTL3 (I)
13
15
44
69
SSTL3 (II)
Notes:
18
32
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive
strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
2-130
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-80 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R((WEAK PULL-UP)
(Ohms)
R(WEAK PULL-DOWN)
(Ohms)
VCCI
Min.
10 k
11 k
18 k
19 k
Max.
45 k
55 k
70 k
90 k
Min.
10 k
12 k
17 k
19 k
Max.
3.3 V
2.5 V
1.8 V
1.5 V
Notes:
45 k
74 k
110 k
140 k
1. R(WEAK PULL-DOWN-MAX) = (VOLspec) / IWEAK PULL-DOWN-MIN
2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN
Table 2-81 • I/O Short Currents IOSH/IOSL
Drive Strength
IOSH (mA)*
IOSL (mA)*
27
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
8 mA
25
51
103
132
268
16
32
65
83
169
9
54
12 mA
16 mA
24 mA
4 mA
109
127
181
18
2.5 V LVCMOS
8 mA
37
12 mA
16 mA
24 mA
2 mA
74
87
124
11
1.8 V LVCMOS
4 mA
17
35
45
91
91
13
25
32
66
66
22
6 mA
44
8 mA
51
12 mA
16 mA
2 mA
74
74
1.5 V LVCMOS
16
4 mA
33
6 mA
39
8 mA
55
12 mA
55
Note: *TJ = 100°C
Advanced v0.7
2-131
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-82 • Short Current Event Duration Before Failure
The length of time an I/O can withstand IOSH/IOSL events
depends on the junction temperature. The reliability
data below is based on a 3.3 V, 36 mA I/O setting, which
is the worst case for this type of analysis.
Temperature
–40°C
0°C
Time Before Failure
> 20 years
> 20 years
> 20 years
5 years
For example, at 110°C, the short current condition would
have to be sustained for more than three months to
cause a reliability concern. The I/O design does not
contain any short circuit protection, but such protection
would only be needed in extremely prolonged stress
conditions.
25°C
70°C
85°C
2 years
100°C
110°C
6 months
3 months
Table 2-83 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (Typ)
3.3 V LVTTL/LVCMOS / PCI / PCI-X (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
240 mV
140 mV
80 mV
60 mV
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
Table 2-84 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (Min.)
No requirement
Input Rise/Fall Time (Max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger disabled)
LVTTL/LVCMOS (Schmitt trigger enabled)
10 ns*
20 years (110°C)
No requirement
No requirement, but input noise voltage 20 years (110°C)
cannot exceed Schmitt hysteresis
HSTL/SSTL/GTL
No requirement
No requirement
10 ns*
10 ns*
10 years (100°C)
10 years (100°C)
LVDS/BLVDS/M-LVDS/LVPECL
Note: *The Maximum Input rise/fall time is related only to the noise induced into the input buffer trace. If the noise is low, then the rise
time and fall time of input buffers, when Schmitt trigger is disabled, can be increased beyond the maximum value. The longer the
rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/
characterization of the system to ensure that there is no excessive noise coupling into input signals.
2-132
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL
input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as part of the 3.3 V LVTTL
support.
Table 2-85 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V Min, V Max, V Max, V Min, V mA
mA Max, mA1 Max, mA1 µA2
µA2
10
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
4
4
27
54
25
51
10
10
10
10
10
8 mA
8
8
10
12 mA
16 mA
24 mA
Notes:
12
16
24
12
16
24
109
127
181
103
132
268
10
10
10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Data Path
35 pF
35 pF for tZH /tZHS /t /t
ZL ZLS
5 pF for tHZ /tLZ
Figure 2-95 • AC Loading
Table 2-86 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.4
V
REF (Typ) (V)
CLOAD (pF)
0
3.3
–
35
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Advanced v0.7
2-133
Fusion Family of Mixed-Signal Flash FPGAs
Timing Characteristics
Table 2-87 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Speed
Grade tZLS tZHS Units
Drive
Strength(mA)
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
4 mA
Std.
–1
0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
9.36 0.04 1.02 1.33 0.36 9.54 7.70 2.29 2.08 11.44 9.60
8.22 0.03 0.90 1.17 0.32 8.37 6.76 2.01 1.82 10.04 8.43
7.86 0.04 1.20 1.57 0.43 8.01 6.44 3.04 3.06 10.24 8.68
6.69 0.04 1.02 1.33 0.36 6.81 5.48 2.58 2.61 8.71 7.38
5.87 0.03 0.90 1.17 0.32 5.98 4.81 2.27 2.29 7.65 6.48
6.03 0.04 1.20 1.57 0.43 6.14 5.02 3.28 3.47 8.37 7.26
5.13 0.04 1.02 1.33 0.36 5.22 4.27 2.79 2.95 7.12 6.17
4.50 0.03 0.90 1.17 0.32 4.58 3.75 2.45 2.59 6.25 5.42
5.62 0.04 1.20 1.57 0.43 5.72 4.72 3.32 3.58 7.96 6.96
4.78 0.04 1.02 1.33 0.36 4.87 4.02 2.83 3.04 6.77 5.92
4.20 0.03 0.90 1.17 0.32 4.27 3.53 2.48 2.67 5.94 5.20
5.24 0.04 1.20 1.57 0.43 5.34 4.69 3.39 3.96 7.58 6.93
4.46 0.04 1.02 1.33 0.36 4.54 3.99 2.88 3.37 6.44 5.89
3.92 0.03 0.90 1.17 0.32 3.99 3.50 2.53 2.96 5.66 5.17
–2
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Table 2-88 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0
Drive
Strength(mA)
Speed
Grade
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS tZHS Units
4 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
7.88 0.04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94
6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73 7.60
5.89 0.03 0.90 1.17 0.32 6.00 5.01 2.01 1.93 7.67 6.67
5.08 0.04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41 6.38
4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30 5.43
3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.28 2.40 5.53 4.76
3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97 5.11
3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34
2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81
3.46 0.04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76 4.84
2.95 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90 4.12
2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30 3.62
3.21 0.04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50 4.39
2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68 3.74
2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11 3.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Notes:
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-134
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5 V
applications. It uses a 5-V-tolerant input buffer and push-pull output buffer.
Table 2-89 • Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V Min, V Max, V Max, V Min, V mA
mA Max, mA1 Max, mA1 µA2
µA2
10
4 mA
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
3.6
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
4
4
18
37
16
32
10
10
10
10
10
8 mA
8
8
10
12 mA
16 mA
24 mA
Notes:
12
16
24
12
16
24
74
65
10
87
83
10
124
169
10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Data Path
35 pF
35 pF for tZH /tZHS /t /t
ZL ZLS
5 pF for tHZ /tLZ
Figure 2-96 • AC Loading
Table 2-90 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.2
VREF (Typ) (V)
CLOAD (pF)
0
2.5
–
35
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Advanced v0.7
2-135
Fusion Family of Mixed-Signal Flash FPGAs
Timing Characteristics
Table 2-91 • 2.5 V LVCMOS Low Slew
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
Drive Strength Speed
Grade tZLS tZHS Units
(mA)
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
4 mA
Std.
–1
0.66 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85
0.56 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34
8.73 0.04 1.51 1.66 0.43 8.89 8.01 3.10 2.93 11.13 10.25
7.43 0.04 1.29 1.41 0.36 7.57 6.82 2.64 2.49 9.47 8.72
6.52 0.03 1.13 1.24 0.32 6.64 5.98 2.32 2.19 8.31 7.65
6.77 0.04 1.51 1.66 0.43 6.90 6.11 3.37 3.39 9.14 8.34
5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10
5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23
6.31 0.04 1.51 1.66 0.43 6.42 5.73 3.42 3.52 8.66 7.96
5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77
4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95
5.93 0.04 1.51 1.66 0.43 6.04 5.70 3.49 4.00 8.28 7.94
5.05 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75
4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.99 6.18 5.93
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Table 2-92 • 2.5 V LVCMOS High Slew
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
Drive Strength
(mA)
Speed
Grade
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS tZHS Units
4 mA
Std.
–1
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
8.82 0.04 1.51 1.66 0.43 8.13 8.82 2.72 2.29 10.37 11.05
7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40
6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25
5.27 0.04 1.51 1.66 0.43 5.27 5.27 3.10 3.03 7.50 7.51
4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 6.38
3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61
3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73
3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15 4.87
2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28
3.53 0.04 1.51 1.66 0.43 3.59 3.12 3.42 3.62 5.83 5.35
3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55
2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00
3.26 0.04 1.51 1.66 0.43 3.32 2.48 3.49 4.11 5.56 4.72
2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01
2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
8 mA
Std.
–1
–2
12 mA
16 mA
24 mA
Notes:
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-136
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
1.8 V LVCMOS
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.8 V
applications. It uses 1.8 V input buffer and push-pull output buffer.
Table 2-93 • Minimum and Maximum DC Input and Output Levels
1.8 V LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V
Min, V Max, V Max, V Min, V
mA mA Max, mA1 Max, mA1 µA2 µA2
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
3.6
3.6
3.6
3.6
3.6
3.6
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
0.45 VCCI – 0.45
2
4
6
8
2
4
11
22
44
51
74
74
9
10
10
10
10
10
10
10
10
10
10
10
10
4 mA
17
35
45
91
91
6 mA
6
8 mA
8
12 mA
16 mA
Notes:
0.45 VCCI – 0.45 12
0.45 VCCI – 0.45 16
12
16
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Data Path
35 pF
35 pF for tZH /tZHS /t /t
ZL ZLS
5 pF for tHZ /tLZ
Figure 2-97 • AC Loading
Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
0.9
V
REF (Typ) (V)
CLOAD (pF)
0
1.8
–
35
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Advanced v0.7
2-137
Fusion Family of Mixed-Signal Flash FPGAs
Timing Characteristics
Table 2-95 • 1.8 V LVCMOS Low Slew
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V
Drive Strength Speed
Grade tZLS tZHS Units
(mA)
tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
2 mA
Std.
–1
0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07
0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37
0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50
0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
4 mA
6 mA
8 mA
12 mA
16 mA
Std.
–1
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
9.69 0.04 1.23 1.62 0.36 9.87 9.15 2.77 2.36 11.77 11.05
8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70
8.97 0.04 1.45 1.91 0.43 9.14 8.10 3.57 3.36 11.37 10.33
7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79
6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72
8.35 0.04 1.45 1.91 0.43 8.50 7.59 3.64 3.52 10.74 9.82
7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35
6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33
7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80
6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33
5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32
7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80
6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33
5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Std.
–1
–2
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-138
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-96 • 1.8 V LVCMOS High Slew
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V
Drive Strength Speed
(mA)
Grade tDOUT tDP
tDIN
0.66 12.10 0.04
0.56 10.30 0.04
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
Std.
–1
1.45
1.23
1.08
1.45
1.23
1.08
1.45
1.23
1.08
1.45
1.23
1.08
1.45
1.23
1.08
1.45
1.23
1.08
1.91
1.62
1.42
1.91
1.62
1.42
1.91
1.62
1.42
1.91
1.62
1.42
1.91
1.62
1.42
1.91
1.62
1.42
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
9.59 12.10 2.78
8.16 10.30 2.37
1.64 11.83 14.34
1.39 10.06 12.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
9.04
7.05
6.00
5.27
4.52
3.85
3.38
4.12
3.51
3.08
3.80
3.23
2.83
3.80
3.23
2.83
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
7.16
6.20
5.28
4.63
4.47
3.80
3.33
4.20
3.57
3.14
3.87
3.29
2.89
3.87
3.29
2.89
9.04
7.05
6.00
5.27
4.52
3.85
3.38
3.99
3.40
2.98
3.09
2.63
2.31
3.09
2.63
2.31
2.08
3.25
2.76
2.43
3.57
3.04
2.66
3.63
3.09
2.71
3.73
3.18
2.79
3.73
3.18
2.79
1.22
2.86
2.44
2.14
3.47
2.95
2.59
3.62
3.08
2.71
4.24
3.60
3.16
4.24
3.60
3.16
8.83 10.71
4 mA
Std.
–1
8.44
7.18
6.30
6.70
5.70
5.00
6.43
5.47
4.81
6.10
5.19
4.56
6.10
5.19
4.56
9.29
7.90
6.94
6.76
5.75
5.05
6.23
5.30
4.65
5.32
4.53
3.98
5.32
4.53
3.98
–2
6 mA
Std.
–1
–2
8 mA
Std.
–1
–2
12 mA
16 mA
Notes:
Std.
–1
–2
Std.
–1
–2
1. Software default selection highlighted in gray.
2. For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-139
Fusion Family of Mixed-Signal Flash FPGAs
1.5 V LVCMOS (JESD8-11)
Low-voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.5 V
applications. It uses a 1.5 V input buffer and push-pull output buffer.
Table 2-97 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
IIH
Drive
Strength Min, V Max, V
Min, V Max, V Max, V
Min, V
mA mA Max, mA1 Max, mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3 0.30 * VCCI 0.7 * VCCI
3.6
3.6
3.6
3.6
3.6
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
2
4
6
8
2
4
16
33
39
55
55
13
25
32
66
66
10
10
10
10
10
10
10
10
10
10
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
–0.3 0.30 * VCCI 0.7 * VCCI
6
8
0.25 * VCCI 0.75 * VCCI 12
12
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 1 k
Test Point
Enable Path
Test Point
Data Path
35 pF
35 pF for tZH /tZHS /t /t
ZL ZLS
5 pF for tHZ /tLZ
Figure 2-98 • AC Loading
Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
CLOAD (pF)
0
1.5
0.75
–
35
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
2-140
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Timing Characteristics
Table 2-99 • 1.5 V LVCMOS Low Slew
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V
Drive
Strength
(mA)
Speed
Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
4 mA
6 mA
8 mA
12 mA
Std.
–1
0.66 14.11 0.04
0.56 12.00 0.04
0.49 10.54 0.03
0.66 11.23 0.04
1.70
1.44
1.27
1.70
1.44
1.27
1.70
1.44
1.27
1.70
1.44
1.27
1.70
1.44
1.27
2.14
1.82
1.60
2.14
1.82
1.60
2.14
1.82
1.60
2.14
1.82
1.60
2.14
1.82
1.60
0.43 14.37 13.14 3.40
0.36 12.22 11.17 2.90
2.68 16.61 15.37
2.28 14.13 13.08
2.00 12.40 11.48
3.36 13.68 12.10
2.86 11.63 10.29
2.51 10.21 9.04
3.55 12.88 11.48
3.02 10.96 9.76
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
0.32 10.73 9.81
0.43 11.44 9.87
2.54
3.77
3.21
2.81
3.84
3.27
2.87
3.97
3.38
2.97
3.97
3.38
2.97
Std.
–1
0.56
0.49
9.55
8.39
0.04
0.03
0.36
0.32
9.73
8.54
8.39
7.37
–2
Std.
–1
0.66 10.45 0.04
0.43 10.65 9.24
0.56
0.49
8.89
7.81
0.04
0.03
0.36
0.32
9.06
7.95
7.86
6.90
–2
2.65
9.62
8.57
Std.
–1
0.66 10.02 0.04
0.43 10.20 9.23
4.22 12.44 11.47
3.59 10.58 9.75
0.56
0.49
8.52
7.48
0.04
0.03
0.36
0.32
8.68
7.62
7.85
6.89
–2
3.15
9.29
8.56
Std.
–1
0.66 10.02 0.04
0.43 10.20 9.23
4.22 12.44 11.47
3.59 10.58 9.75
0.56
0.49
8.52
7.48
0.04
0.03
0.36
0.32
8.68
7.62
7.85
6.89
–2
3.15
9.29
8.56
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-141
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-100 • 1.5 V LVCMOS High Slew
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V
Drive Strength Speed
(mA)
Grade tDOUT tDP
tDIN
tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
tZLS
tZHS Units
2 mA
Std.
–1
0.66 8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.56 7.26 0.04 1.44 1.82 0.36
0.49 6.37 0.03 1.27 1.60 0.32
6.18 7.26 2.89 2.37 8.08 9.16
5.42 6.37 2.53 2.08 7.09 8.04
–2
4 mA
6 mA
8 mA
12 mA
Notes:
Std.
–1
0.66 5.41 0.04 1.70 2.14 0.43 5.22 5.41 3.75 3.48 7.45 7.65
0.56 4.60 0.04 1.44 1.82 0.36
0.49 4.04 0.03 1.27 1.60 0.32
4.44 4.60 3.19 2.96 6.34 6.50
3.89 4.04 2.80 2.60 5.56 5.71
–2
Std.
–1
0.66 4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13 6.98
0.56 4.09 0.04 1.44 1.82 0.36
0.49 3.59 0.03 1.27 1.60 0.32
4.16 4.04 3.26 3.12 6.06 5.94
3.65 3.54 2.86 2.74 5.32 5.21
–2
Std.
–1
0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86
0.56 3.76 0.04 1.44 1.82 0.36
0.49 3.30 0.03 1.27 1.60 0.32
3.83 3.08 3.37 3.72 5.73 4.98
3.36 2.70 2.96 3.27 5.03 4.37
–2
Std.
–1
0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86
0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98
0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37
–2
1. Software default selection highlighted in gray.
2. For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-142
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications.
Table 2-101 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
Drive Strength
Per PCI specification
Notes:
VIL
VIH
VOL
VOH
IOL
IOH
mA Max, mA1 Max, mA1 μA2 μA2
10 10
IOSL
IOSH
IIL
IIH
Min, V Max, V Min, V Max, V Max, V Min, V mA
Per PCI curves
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
AC loadings are defined per the PCI/PCI-X specifications for the data path; Actel loadings for enable path
characterization are described in Figure 2-99.
R to VCCI for tDP (F)
R to GND for tDP (R)
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
R = 25
Test Point
Data Path
R = 1 k
Test Point
Enable Path
10 pF for tZH /tZHS/tZL/tZLS
5 pF for tHZ /tLZ
Figure 2-99 • AC Loading
AC loading are defined per PCI/PCI-X specifications for the data path; Actel loading for tristate is described in Table 2-
102.
Table 2-102 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
–
10
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-103 • 3.3 V PCI/PCI-X
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.81
2.39
2.09
tDIN
0.04
0.04
0.03
tPY
1.05
0.89
0.78
tPYS
1.67
1.42
1.25
tEOUT
0.43
0.36
0.32
tZL
tZH
2.00
1.70
1.49
tLZ
tHZ
3.61
3.07
2.70
tZLS
5.09
4.33
3.80
tZHS Units
Std.
–1
2.86
2.43
2.13
3.28
2.79
2.45
4.23
3.60
3.16
ns
ns
ns
–2
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-143
Fusion Family of Mixed-Signal Flash FPGAs
Voltage Referenced I/O Characteristics
3.3 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and
an open drain output buffer. The VCCI pin should be connected to 3.3 V.
Table 2-104 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL
Drive
Strength Min, V Max, V
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Min, V Max, V Max, V Min, V mA
mA Max, mA1 Max, mA1 µA2
25 181 268 10
µA2
25 mA3
–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 25
–
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-100 • AC Loading
Table 2-105 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF - 0.05
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
1.2
CLOAD (pF)
V
VREF + 0.05
0.8
0.8
10
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-106 • 3.3 V GTL
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V VREF = 0.8 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.08
1.77
1.55
tDIN
0.04
0.04
0.03
tPY
2.93
2.50
2.19
tEOUT
0.43
0.36
0.32
tZL
tZH
2.08
1.77
1.55
tLZ
tHZ
tZLS
4.27
3.63
3.19
tZHS Units
Std.
–1
2.04
1.73
1.52
4.31
3.67
3.22
ns
ns
ns
–2
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-144
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and
an open drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-107 • Minimum and Maximum DC Input and Output Levels
2.5 GTL
VIL
VIH
Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 25 25 124 169 10 10
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V
25 mA3
–
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
GTL
25
Test Point
10 pF
Figure 2-101 • AC Loading
Table 2-108 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
VREF - 0.05
VREF + 0.05
0.8
0.8
1.2
10
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-109 • 2.5 V GTL
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V VREF = 0.8 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.13
1.81
1.59
tDIN
0.04
0.04
0.03
tPY
2.46
2.09
1.83
tEOUT
0.43
0.36
0.32
tZL
tZH
2.13
1.81
1.59
tLZ
tHZ
tZLS
4.40
3.74
3.28
tZHS Units
Std.
–1
2.16
1.84
1.61
4.36
3.71
3.26
ns
ns
ns
–2
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-145
Fusion Family of Mixed-Signal Flash FPGAs
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer
and an open drain output buffer. The VCCI pin should be connected to 3.3 V.
Table 2-110 • Minimum and Maximum DC Input and Output Levels
3.3 V GTL+
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL IIH
Drive Strength Min, V Max, V
Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
35 mA
–0.3
VREF – 0.1 VREF + 0.1
3.6
0.6
–
35
35
181
268
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 2-102 • AC Loading
Table 2-111 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF – 0.1
Input High (V)
Measuring Point* (V)
V
REF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
V
VREF + 0.1
1.0
1.0
1.5
10
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-112 • 3.3 V GTL+
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V, VREF = 1.0 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.06
1.75
1.53
tDIN
0.04
0.04
0.03
tPY
1.59
1.35
1.19
tEOUT
0.43
0.36
0.32
tZL
tZH
2.06
1.75
1.53
tLZ
tHZ
tZLS
4.33
3.68
3.23
tZHS
4.29
3.65
3.20
Units
ns
Std.
–1
2.09
1.78
1.56
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-146
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer
and an open drain output buffer. The VCCI pin should be connected to 2.5 V.
Table 2-113 • Minimum and Maximum DC Input and Output Levels
2.5 V GTL+
VIL
VIH
Min, V Max, V Max, V Min, V mA
VREF – 0.1 VREF + 0.1 3.6 0.6 33
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL IIH
Drive Strength Min, V Max, V
mA Max, mA1 Max, mA1 µA2 µA2
33 mA
–0.3
–
33
124
169
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
GTL+
25
Test Point
10 pF
Figure 2-103 • AC Loading
Table 2-114 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF - 0.1
Input High (V)
Measuring Point* (V)
V
REF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
V
VREF + 0.1
1.0
1.0
1.5
10
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-115 • 2.5 V GTL+
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V, VREF = 1.0 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.21
1.88
1.65
tDIN
0.04
0.04
0.03
tPY
tEOUT
0.43
0.36
0.32
tZL
tZH
2.10
1.79
1.57
tLZ
tHZ
tZLS
4.48
3.81
3.35
tZHS
4.34
3.69
3.24
Units
ns
Std.
–1
1.59
1.35
1.19
2.25
1.91
1.68
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-147
Fusion Family of Mixed-Signal Flash FPGAs
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). Fusion devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-116 • Minimum and Maximum DC Input and Output Levels
HSTL Class I
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
8 mA
–0.3
VREF – 0.1 VREF + 0.1
3.6
0.4 VCCI – 0.4
8
8
39
32
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
HSTL
Class I
50
Test Point
20 pF
Figure 2-104 • AC Loading
Table 2-117 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF – 0.1
Input High (V)
Measuring Point* (V)
V
REF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
V
VREF + 0.1
0.75
0.75
0.75
20
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-118 • HSTL Class I
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V, VREF = 0.75 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
3.18
2.70
2.37
tDIN
0.04
0.04
0.03
tPY
2.12
1.81
1.59
tEOUT
0.43
0.36
0.32
tZL
tZH
3.14
2.67
2.35
tLZ
tHZ
tZLS
5.47
4.66
4.09
tZHS
5.38
4.58
4.02
Units
ns
Std.
–1
3.24
2.75
2.42
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-148
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). Fusion devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Table 2-119 • Minimum and Maximum DC Input and Output Levels
HSTL Class II
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V
Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
15 mA3
–0.3
VREF – 0.1 VREF + 0.1
3.6
0.4 VCCI – 0.4 15
15
55
66
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
VTT
HSTL
Class II
25
Test Point
20 pF
Figure 2-105 • AC Loading
Table 2-120 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF – 0.1
Input High (V)
Measuring Point* (V)
V
REF (Typ) (V) VTT (Typ) (V)
CLOAD (pF)
V
VREF + 0.1
0.75
0.75
0.75
20
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-121 • HSTL Class II
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V, VREF = 0.75 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
3.02
2.57
2.26
tDIN
0.04
0.04
0.03
tPY
2.12
1.81
1.59
tEOUT
0.43
0.36
0.32
tZL
tZH
2.71
2.31
2.03
tLZ
tHZ
tZLS
5.32
4.52
3.97
tZHS
4.95
4.21
3.70
Units
ns
Std.
–1
3.08
2.62
2.30
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-149
Fusion Family of Mixed-Signal Flash FPGAs
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class I. This provides a
differential amplifier input buffer and a push-pull output buffer.
Table 2-122 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class I
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V Min, V Max, V Max, V Min, V
–0.3 VREF – 0.2 VREF + 0.2 3.6 0.54
mA
mA Max, mA1 Max, mA1 µA2 µA2
15 mA
VCCI – 0.62 15
15
87
83
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class I
50
Test Point
25
30 pF
Figure 2-106 • AC Loading
Table 2-123 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
1.25
VREF (Typ) (V)
1.25
VTT (Typ) (V)
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.25
30
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-124 • SSTL 2 Class I
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V, VREF = 1.25 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.13
1.81
1.59
tDIN
0.04
0.04
0.03
tPY
1.33
1.14
1.00
tEOUT
0.43
0.36
0.32
tZL
tZH
1.85
1.57
1.38
tLZ
tHZ
tZLS
4.40
3.74
3.29
tZHS
4.08
3.47
3.05
Units
ns
Std.
–1
2.17
1.84
1.62
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-150
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
SSTL2 Class II
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class II. This provides a
differential amplifier input buffer and a push-pull output buffer.
Table 2-125 • Minimum and Maximum DC Input and Output Levels
SSTL2 Class II
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V
mA mA Max, mA1 Max, mA1 µA2 µA2
18 mA
–0.3 VREF – 0.2 VREF + 0.2 3.6
0.35 VCCI – 0.43 18
18
124
169
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL2
Class II
25
Test Point
25
30 pF
Figure 2-107 • AC Loading
Table 2-126 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
V
REF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.25
1.25
1.25
30
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-127 • SSTL 2 Class II
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V, VREF = 1.25 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.17
1.84
1.62
tDIN
0.04
0.04
0.03
tPY
1.33
1.14
1.00
tEOUT
0.43
0.36
0.32
tZL
tZH
1.77
1.51
1.32
tLZ
tHZ
tZLS
4.44
3.78
3.32
tZHS
4.01
3.41
2.99
Units
ns
Std.
–1
2.21
1.88
1.65
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-151
Fusion Family of Mixed-Signal Flash FPGAs
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class I. This provides a
differential amplifier input buffer and a push-pull output buffer.
Table 2-128 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class I
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL IIH
Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
14 mA
–0.3
VREF – 0.2 VREF + 0.2
3.6
0.7
VCCI – 1.1 14
14
54
51
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class I
50
Test Point
25
30 pF
Figure 2-108 • AC Loading
Table 2-129 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF – 0.2
Input High (V)
Measuring Point* (V)
V
REF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
V
VREF + 0.2
1.5
1.5
1.485
30
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-130 • SSTL3 Class I
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V, VREF = 1.5 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.31
1.96
1.72
tDIN
0.04
0.04
0.03
tPY
1.25
1.06
0.93
tEOUT
0.43
0.36
0.32
tZL
tZH
1.84
1.56
1.37
tLZ
tHZ
tZLS
4.59
3.90
3.42
tZHS
4.07
3.46
3.04
Units
ns
Std.
–1
2.35
2.00
1.75
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-152
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class II. This provides a
differential amplifier input buffer and a push-pull output buffer.
Table 2-131 • Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA1 Max, mA1 µA2 µA2
21 mA
–0.3 VREF – 0.2 VREF + 0.2 3.6
0.5 VCCI – 0.9 21
21
109
103
10
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
VTT
SSTL3
Class II
25
Test Point
25
30 pF
Figure 2-109 • AC Loading
Table 2-132 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
REF – 0.2
Input High (V)
Measuring Point* (V)
V
REF (Typ) (V)
VTT (Typ) (V) CLOAD (pF)
1.485 30
V
VREF + 0.2
1.5
1.5
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-133 • SSTL3- Class II
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V, VREF = 1.5 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.07
1.76
1.54
tDIN
0.04
0.04
0.03
tPY
1.25
1.06
0.93
tEOUT
0.43
0.36
0.32
tZL
tZH
1.67
1.42
1.25
tLZ
tHZ
tZLS
4.34
3.69
3.24
tZHS
3.91
3.32
2.92
Units
ns
Std.
–1
2.10
1.79
1.57
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-153
Fusion Family of Mixed-Signal Flash FPGAs
data bit is carried through two signal lines; so two pins
are needed. It also requires external resistor termination.
Differential I/O Characteristics
Configuration of the I/O modules as a differential pair is
handled by the Actel Designer software when the user
instantiates a differential I/O macro in the design.
The full implementation of the LVDS transmitter and
receiver is shown in an example in Figure 2-110. The
building blocks of the LVDS transmitter-receiver are one
transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVPECL implementation,
because the output standard specifications are
different.
Differential I/Os can also be used in conjunction with the
embedded Input Register (InReg), Output Register
(OutReg), Enable Register (EnReg), and Double Data
Rate (DDR). However, there is no support for
bidirectional I/Os or tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a
high-speed, differential I/O standard. It requires that one
Bourns Part Number: CAT16-LV4F12
FPGA
FPGA
OUTBUF_LVDS
P
P
165 Ω
165 Ω
Z0 = 50 Ω
INBUF_LVDS
+
-
140 Ω
Z0 = 50 Ω
100 Ω
N
N
Figure 2-110 • LVDS Circuit Diagram and Board-Level Implementation
Table 2-134 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
2.375
0.9
Typ.
2.5
Max.
Units
2.625
1.25
1.6
V
V
VOL
Output Low Voltage
1.075
1.425
VOH
Output High Voltage
1.25
0
V
VI
Input Voltage
2.925
450
V
VODIFF
VOCM
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
250
350
1.25
1.25
350
mV
V
1.125
0.05
100
1.375
2.35
VICM
V
VIDIFF
mV
Notes:
1. +/- 5%
2. Differential input voltage = +/-350 mV
Table 2-135 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
1.075
1.325
Cross point
–
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
2-154
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Timing Characteristics
Table 2-136 • LVDS
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.10
1.79
1.57
tDIN
0.04
0.04
0.03
tPY
2.02
1.72
1.51
Units
ns
Std.
–1
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
be implemented using TRIBUF_LVDS and BIBUF_LVDS
macros along with appropriate terminations. Multi-point
designs using Actel LVDS macros can achieve up to
200 MHz with a maximum of 20 loads. A sample
application is given in Figure 2-111. The input and
output buffer delays are available in the LVDS section in
Table 2-136.
BLVDS/M-LVDS
Bus LVDS (BLVDS) and Multi-Point LVDS (M-LVDS)
specifications extend the existing LVDS standard to high-
performance multi-point bus applications. Multidrop and
multi-point bus configurations may contain any
combination of drivers, receivers and transceivers. Actel
LVDS drivers provide the higher drive current required by
BLVDS and M-LVDS to accommodate the loading. The
driver requires series terminations for better signal
quality and to control voltage swing. Termination is also
required at both ends of the bus since the driver can be
located anywhere on the bus. These configurations can
Example: For a bus consisting of 20 equidistant loads, the
following terminations provide the required differential
voltage, in worst case Industrial operating conditions, at
the farthest receiver: RS = 60 Ω and RT = 70 Ω, given
Z0 = 50 Ω (2") and a Zstub = 50 Ω (~1.5").
Receiver
Transceiver
Driver
D
Receiver
Transceiver
EN
EN
EN
EN
EN
BIBUF_LVDS
R
T
R
T
+
-
+
-
+
-
+
-
+
-
RS RS
Zstub
RS RS
RS RS
Zstub
RS RS
RS RS
Zstub
Z0
Zstub
Z0
Zstub
Zstub
Z0
Zstub
Z0
Zstub
...
Z0
Z0
Z0
Z0
RT
RT
Z0
Z0
Z0
Z0
Figure 2-111 • BLVDS/M-LVDS Multi-Point Application Using LVDS I/O Buffers
Advanced v0.7
2-155
Fusion Family of Mixed-Signal Flash FPGAs
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is
another differential I/O standard. It requires that one
data bit is carried through two signal lines. Like LVDS,
two pins are needed. It also requires external resistor
termination.
building blocks of the LVPECL transmitter-receiver are
one transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVDS implementation,
because the output standard specifications are different.
The full implementation of the LVDS transmitter and
receiver is shown in an example in Figure 2-112. The
Bourns Part Number: CAT16-PC4F12
FPGA
FPGA
P
P
OUTBUF_LVPECL
100 Ω
100 Ω
Z0 = 50 Ω
187 W
Z0 = 50 Ω
INBUF_LVPECL
+
-
100 Ω
N
N
Figure 2-112 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-137 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
Description
Supply Voltage
Min.
Max.
Min.
Max.
Min.
Max.
Units
3.0
3.3
3.6
V
V
VOL
Output Low Voltage
0.96
1.8
1.27
2.11
3.3
1.06
1.92
0
1.43
2.28
3.6
1.30
2.13
0
1.57
2.41
3.9
VOH
Output High Voltage
V
VIL, VIH
VODIFF
VOCM
Input Low, Input High voltages
Differential Output Voltage
Output Common Mode Voltage
Input Common Mode Voltage
Input Differential Voltage
0
V
0.625
1.762
1.01
300
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
0.625
1.762
1.01
300
0.97
1.98
2.57
V
V
VICM
V
VIDIFF
mV
Table 2-138 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
1.64
1.94
Cross point
–
Note: *Measuring point = Vtrip. See Table 2-75 on page 2-128 for a complete table of trip points.
Timing Characteristics
Table 2-139 • LVPECL
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Speed Grade
tDOUT
0.66
0.56
0.49
tDP
2.14
1.82
1.60
tDIN
0.04
0.04
0.03
tPY
1.75
1.49
1.31
Units
ns
Std.
–1
ns
–2
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-156
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Preset
L
D
DOUT
EOUT
Data_out
PRE
DFN1E1P1
F
PRE
DFN1E1P1
Y
E
Core
Array
Data
Enable
CLK
D
Q
D
Q
C
G
E
E
B
H
I
A
PRE
DFN1E1P1
J
D
Q
K
Data Input I/O Register with:
Active High Enable
E
Active High Preset
Positive Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive Edge Triggered
CLKBUF
INBUF
INBUF
Figure 2-113 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Advanced v0.7
2-157
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-140 • Parameter Definition and Measuring Nodes
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Measuring Nodes (From, To)*
Clock-to-Q of the Output Data Register
H, DOUT
F, H
Data Setup time for the Output Data Register
tOHD
Data Hold time for the Output Data Register
F, H
tOSUE
Enable Setup time for the Output Data Register
Enable Hold time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset removal time for the Output Data Register
Asynchronous Preset Recovery time for the Output Data Register
Clock-to-Q of the Output Enable Register
G, H
G, H
L,DOUT
L, H
tOHE
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
tOEHD
L, H
H, EOUT
J, H
Data Setup time for the Output Enable Register
Data Hold time for the Output Enable Register
Enable Setup time for the Output Enable Register
Enable Hold time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal time for the Output Enable Register
Asynchronous Preset Recovery time for the Output Enable Register
Clock-to-Q of the Input Data Register
J, H
tOESUE
K, H
K, H
I, EOUT
I, H
tOEHE
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
I, H
A, E
tISUD
Data Setup time for the Input Data Register
C, A
C, A
B, A
tIHD
Data Hold time for the Input Data Register
tISUE
Enable Setup time for the Input Data Register
tIHE
Enable Hold time for the Input Data Register
B, A
tIPRE2Q
tIREMPRE
tIRECPRE
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal time for the Input Data Register
Asynchronous Preset Recovery time for the Input Data Register
D, E
D, A
D, A
Note: *See Figure 2-113 on page 2-157 for more information.
2-158
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1E1C1
DFN1E1C1
GG
EOUT
E
E
Enable
CLK
CLR
BB
CLR
LL
HH
AA
DD
JJ
D
Q
CLR
DFN1E1C1
KK
E
CLR
Data Input I/O Register with
Active High Enable
Active High Clear
Positive Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
INBUF
INBUF
CLKBUF
Positive Edge Triggered
Figure 2-114 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Advanced v0.7
2-159
Fusion Family of Mixed-Signal Flash FPGAs
Table 2-141 • Parameter Definition and Measuring Nodes
Parameter Name
tOCLKQ
tOSUD
Parameter Definition
Measuring Nodes (From, To)*
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
Data Setup time for the Output Data Register
tOHD
Data Hold time for the Output Data Register
FF, HH
tOSUE
Enable Setup time for the Output Data Register
Enable Hold time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal time for the Output Data Register
Asynchronous Clear Recovery time for the Output Data Register
Clock-to-Q of the Output Enable Register
GG, HH
GG, HH
LL, DOUT
LL, HH
tOHE
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
tOEHD
LL, HH
HH, EOUT
JJ, HH
Data Setup time for the Output Enable Register
Data Hold time for the Output Enable Register
Enable Setup time for the Output Enable Register
Enable Hold time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal time for the Output Enable Register
Asynchronous Clear Recovery time for the Output Enable Register
Clock-to-Q of the Input Data Register
JJ, HH
tOESUE
KK, HH
KK, HH
II, EOUT
II, HH
tOEHE
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup time for the Input Data Register
tIHD
Data Hold time for the Input Data Register
tISUE
Enable Setup time for the Input Data Register
tIHE
Enable Hold time for the Input Data Register
tICLR2Q
tIREMCLR
tIRECCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal time for the Input Data Register
Asynchronous Clear Recovery time for the Input Data Register
Note: *See Figure 2-114 on page 2-159 for more information.
2-160
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Input Register
tICKMPWH tICKMPWL
50%
tISUD
50%
50%
50%
50%
50%
50%
1
CLK
t
IHD
50%
50%
0
Data
tIREMPRE
tIRECPRE
tIWPRE
Enable
Preset
50%
tIHE
50%
50%
50%
t
ISUE
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-115 • Input Register Timing Diagram
Timing Characteristics
Table 2-142 • Input Data Register Propagation Delays
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tICLKQ
Description
–2
–1
Std.
Units
ns
Clock-to-Q of the Input Data Register
0.63
0.43
0.00
0.43
0.00
0.63
0.45
0.00
0.22
0.00
0.22
0.25
0.25
0.36
0.41
0.71
0.49
0.00
0.49
0.00
0.71
0.51
0.00
0.25
0.00
0.25
0.28
0.28
0.41
0.46
0.84
0.57
0.00
0.57
0.00
0.84
0.60
0.00
0.30
0.00
0.30
0.33
0.33
0.48
0.54
tISUD
Data Setup time for the Input Data Register
ns
tIHD
Data Hold time for the Input Data Register
ns
tISUE
Enable Setup time for the Input Data Register
ns
tIHE
Enable Hold time for the Input Data Register
ns
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal time for the Input Data Register
Asynchronous Clear Recovery time for the Input Data Register
Asynchronous Preset Removal time for the Input Data Register
Asynchronous Preset Recovery time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
ns
ns
ns
ns
ns
ns
ns
tIWPRE
ns
tICKMPWH
tICKMPWL
ns
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-161
Fusion Family of Mixed-Signal Flash FPGAs
Output Register
tOCKMPWHtOCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOSUD tOHD
50%
50%
1
0
Data_out
Enable
Preset
50%
tOWPRE tORECPRE
50%
tOREMPRE
50%
tOHE
50%
tOSUE
tOWCLR
tOREMCLR
50%
tORECCLR
50%
50%
Clear
tOPRE2Q
50%
tOCLKQ
50%
50%
DOUT
tOCLR2Q
Figure 2-116 • Output Register Timing Diagram
Timing Characteristics
Table 2-143 • Output Data Register Propagation Delays
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tOCLKQ
Description
–2
–1
Std. Units
Clock-to-Q of the Output Data Register
0.63
0.43
0.00
0.43
0.00
0.63
0.45
0.00
0.22
0.00
0.22
0.25
0.25
0.36
0.41
0.71
0.49
0.00
0.49
0.00
0.71
0.51
0.00
0.25
0.00
0.25
0.28
0.28
0.41
0.46
0.84
0.57
0.00
0.57
0.00
0.84
0.60
0.00
0.30
0.00
0.30
0.33
0.33
0.48
0.54
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup time for the Output Data Register
tOHD
Data Hold time for the Output Data Register
tOSUE
Enable Setup time for the Output Data Register
Enable Hold time for the Output Data Register
tOHE
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
tOWPRE
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal time for the Output Data Register
Asynchronous Clear Recovery time for the Output Data Register
Asynchronous Preset Removal time for the Output Data Register
Asynchronous Preset Recovery time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
tOCKMPWH
tOCKMPWL
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-162
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Output Enable Register
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tOESUD tOEHD
50%
50%
0
1
D_Enable
Enable
Preset
50%
tOEWPRE
50%
tOEREMPRE
tOERECPRE
50%
50%
tOESUEOEHE
t
tOEREMCLR
50%
tOEWCLR tOERECCLR
50%
50%
Clear
EOUT
tOECLR2Q
50%
tOEPRE2Q
50%
50%
tOECLKQ
Figure 2-117 • Output Enable Register Timing Diagram
Timing Characteristics
Table 2-144 • Output Enable Register Propagation Delays
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tOECLKQ
Description
–2
–1
Std. Units
Clock-to-Q of the Output Enable Register
0.63 0.71 0.84
0.43 0.49 0.57
0.00 0.00 0.00
0.43 0.49 0.57
0.00 0.00 0.00
0.63 0.71 0.84
0.45 0.51 0.60
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.25 0.28 0.33
0.25 0.28 0.33
0.36 0.41 0.48
0.41 0.46 0.54
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOESUD
Data Setup time for the Output Enable Register
tOEHD
Data Hold time for the Output Enable Register
tOESUE
Enable Setup time for the Output Enable Register
tOEHE
Enable Hold time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
tOECKMPWH
tOECKMPWL
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal time for the Output Enable Register
Asynchronous Clear Recovery time for the Output Enable Register
Asynchronous Preset Removal time for the Output Enable Register
Asynchronous Preset Recovery time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width High for the Output Enable Register
Clock Minimum Pulse Width Low for the Output Enable Register
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-163
Fusion Family of Mixed-Signal Flash FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
A
D
Out_QF
(To Core)
Data
INBUF
FF1
E
B
Out_QR
(To Core)
CLK
CLKBUF
FF2
C
CLR
INBUF
DDR_IN
Figure 2-118 • Input DDR Timing Model
Table 2-145 • Parameter Definitions
Parameter Name
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Parameter Definition
Measuring Nodes (From, To)
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup time of DDR input
Data Hold time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
tDDRIHD
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
Clear Recovery
2-164
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
CLK
tDDRISUD
tDDRIHD
8
Data
CLR
1
2
3
4
5
6
7
9
tDDRIRECCLR
tDDRIREMCLR
tDDRICLKQ1
tDDRICLR2Q1
Out_QF
Out_QR
6
2
4
tDDRICLKQ2
tDDRICLR2Q2
7
3
5
Figure 2-119 • Input DDR Timing Diagram
Timing Characteristics
Table 2-146 • Input DDR Propagation Delays
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tDDRICLKQ1
tDDRICLKQ2
tDDRISUD
Description
–2
–1
Std.
0.84
0.76
0.71
0.00
0.76
0.76
0.00
0.30
Units
ns
Clock-to-Out Out_QR for Input DDR
0.63
0.57
0.53
0.00
0.57
0.57
0.00
0.22
0.71
0.65
0.61
0.00
0.65
0.65
0.00
0.25
Clock-to-Out Out_QF for Input DDR
ns
Data Setup for Input DDR
ns
tDDRIHD
Data Hold for Input DDR
ns
tDDRICLR2Q1
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRIWCLR
tDDRICKMPWH
tDDRICKMPWL
FDDRIMAX
Asynchronous Clear to Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal time for Input DDR
Asynchronous Clear Recovery time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
ns
ns
ns
ns
ns
ns
ns
MHz
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-165
Fusion Family of Mixed-Signal Flash FPGAs
Output DDR
A
Data_F
(From Core)
FF1
FF2
Out
B
C
D
0
1
CLK
E
CLKBUF
OUTBUF
Data_R
(From Core)
B
C
CLR
INBUF
DDR_OUT
Figure 2-120 • Output DDR Timing Model
Table 2-147 • Parameter Definitions
Parameter Name
Parameter Definition
Measuring Nodes (From, To)
tDDROCLKQ
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROSUD1
tDDROSUD2
tDDROHD1
Clock-to-Out
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
tDDROHD2
2-166
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
CLK
tDDROHD2
tDDROSUD2
3
4
5
Data_F
1
2
tDDROHD1
tDDROSUD1
Data_R 6
CLR
7
8
9
10
tDDRORECCLR
11
tDDROREMCLR
tDDROCLKQ
tDDROCLR2Q
Out
7
2
8
3
9
4
10
Figure 2-121 • Output DDR Timing Diagram
Timing Characteristics
Table 2-148 • Output DDR Propagation Delays
Commercial Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Parameter
tDDROCLKQ
tDDROSUD1
tDDROSUD2
tDDROHD1
Description
–2
–1
Std.
0.84
0.57
0.57
0.00
0.00
0.76
0.00
0.30
Units
ns
Clock-to-Out of DDR for Output DDR
0.63
0.43
0.43
0.00
0.00
0.57
0.00
0.22
0.71
0.49
0.49
0.00
0.00
0.65
0.00
0.25
Data_F Data Setup for Output DDR
ns
Data_R Data Setup for Output DDR
ns
Data_F Data Hold for Output DDR
ns
tDDROHD2
Data_R Data Hold for Output DDR
ns
tDDROCLR2Q
tDDROREMCLR
tDDRORECCLR
tDDROWCLR1
tDDROCKMPWH
tDDROCKMPWL
FDDOMAX
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal time for Output DDR
Asynchronous Clear Recovery time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
ns
ns
ns
ns
ns
ns
MHz
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
Advanced v0.7
2-167
Fusion Family of Mixed-Signal Flash FPGAs
Pin Descriptions
Supply Pins
V
Analog Power Supply (3.3 V)
CC33PMP
3.3 V clean analog power supply input for use by the
analog charge pump. To avoid high current draw,
VCC33PMP should be powered up before or
simultaneously with VCC33A
.
GND
Ground
V
Flash Memory Block Power Supply
(1.5 V)
CCNVM
Ground supply voltage to the core, I/O outputs, and I/O
logic.
1.5 V power supply used by the Fusion device's Flash
memory block module(s). To avoid high current draw VCC
should be powered up before or simultaneously with
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O
banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise
originated from the output buffer ground domain. This
minimizes the noise transfer within the package, and
improves input signal integrity. GNDQ needs to always
be connected on the board to GND.
VCCNVM
.
V
Oscillator Power Supply (3.3 V)
CCOSC
Power supply for both integrated RC oscillator and
crystal oscillator circuit.
V
Core Supply Voltage
CC
ADCGNDREF
Analog Reference Ground
Supply voltage to the FPGA core, nominal 1.5 V. VCC is
also required for powering the JTAG state machine in
addition to VJTAG. Even when a Fusion device is in bypass
mode in a JTAG chain of interconnected devices, both
VCC and VJTAG must remain powered to allow JTAG
signals to pass through the Fusion device.
Analog ground reference used by the ADC. This pad
should be connected to a quiet analog ground.
GNDA
Ground (analog)
Quiet ground supply voltage to the Analog Block of the
Fusion devices. The use of a separate analog ground
helps isolate the analog functionality of the Fusion
device from any digital switching noise.
V
Bx
I/O Supply Voltage
CCI
Supply voltage to the bank's I/O output buffers and I/O
logic. Bx is the I/O bank number. There are either 4
(AFS090 and AFS250) or 5 (AFS600 and AFS1500) I/O
banks on the Fusion devices plus a dedicated VJTAG bank.
GNDAQ
Ground (analog quiet)
Quiet ground supply voltage to the analog I/O of the
Fusion devices. The use of a separate analog ground
helps isolate the analog functionality of the Fusion
device from any digital switching noise.
Each bank can have a separate VCCI connection. All I/Os in
a bank will run off the same VCCIBx supply. VCCI can be
1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O
banks should have their corresponding VCCI pins tied to
GND.
GNDNVM
Flash Memory Ground
Ground supply used by the Fusion device's Flash memory
block module(s).
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O
bank. X is the bank number. Within the package, the
VMV plane is decoupled from the simultaneous
switching noise originated from the output buffer VCCI
domain. This minimizes the noise transfer within the
package, and improves input signal integrity. Each bank
must have at least one VMV connection. All I/Os in a
bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of
each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V
nominal voltage. Unused I/O banks should have their
corresponding VMV and VCCI pins tied to GND. VMV and
VCCI must be connected to the same power supply and
VCCI pins within a given I/O bank. Used VMV pins must be
connected to the corresponding VCCI pins of the same
bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
GNDOSC
Oscillator Ground
Ground supply for both integrated RC oscillator and
crystal oscillator circuit.
V
Analog Power Supply (1.5 V)
CC15A
1.5 V clean analog power supply input for use by the
1.5 V portion of the analog circuitry.
V
Analog Power Supply (3.3 V)
CC33A
3.3 V clean analog power supply input for use by the
3.3 V portion of the analog circuitry.
V
Negative 3.3 V output
CC33N
VOLTAGE CONVERTER OUTPUT is the –3.3 V output from
the voltage converter. A 2.2 µF capacitor must be
connected from this pin to ground.
2-168
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
V
PLL Supply Voltage
out on this pin for use by the system. The pin in this can
would either open or 2.56 V output.
CCPLA/B
Supply voltage to analog PLL, nominal 1.5 V, where A
and B refer to the PLL. The AFS090 and AFS250 each have
a single PLL. The AFS600 and AFS1500 devices each have
two PLLs. If unused, VCCPLA/B should be tied to GND.
If a different reference voltage is required, it can be
supplied on this pin and used by the ADC. The valid
range of values that can be supplied to the ADC is
between 1. 0 V and 3.3 V.
V
PLL Ground8
COMPLF
Ground to analog PLL, where A and B refer to the PLL.
The AFS090 and AFS250 each have a single PLL. The
AFS600 and AFS1500 devices each have two PLLs. Unused
VCOMPLF pin should be connected to GND.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected. Unused I/O
pins are configured as inputs with pull-up resistors.
V
JTAG Supply Voltage
JTAG
Fusion devices have a separate bank for the dedicated
JTAG pins. The JTAG pins can be run at any voltage from
1.5 V to 3.3 V (nominal). Isolating the JTAG power supply
in a separate I/O bank gives greater flexibility with
supply selection and simplifies power supply and printed
circuit board design. If the JTAG interface is not used nor
planned to be used, the VJTAG pin together with the TRST
pin could be tied to GND. It should be noted that VCC is
required to be powered for JTAG operation; VJTAG alone
is insufficient. If a Fusion device is in a JTAG chain of
interconnected boards, and it is desired to power down
the board containing the Fusion device, this may be done
provided both VJTAG and VCC to the Fusion part remain
powered; otherwise, JTAG signals will not be able to
transition the Fusion device, even in bypass mode.
During programming, I/Os become tristated and weakly
pulled up to VCCI. With VCCI, VMV and VCC supplies
continuously powered-up, and the device transitions
from programming to operating mode, the I/Os get
instantly configured to the desired user configuration.
Axy
Analog Input/Output
Analog I/O pin where x is the analog pad type
(C = current pad, G = Gate driver pad, T = Temperature
pad, V = Voltage pad) and y is the Analog Quad number
(0 to 9).
ATRTNx
Temperature Monitor Return
AT RETURN are the returns for the temperature sensors.
The cathode terminal of the external diodes should be
connected to these pins. There is 1 analog return pin for
every two analog quads. The x in the ATRTNx designator
indicates the quad pairing (x = 0 for AQ1 and AQ2, x = 1
for AQ2 and AQ3..., x = 4 for AQ8 and AQ9). These
signals that drive these pins are called out as ATRETUNxy
in the software (where x and y refer to the quads that
share the return signal).
V
Programming Supply Voltage
PUMP
Fusion devices support single-voltage ISP programming
of the configuration Flash and FlashROM. For
programming, VPUMP should be 3.3 V nominal. During
normal device operation, VPUMP can be left floating or
can be tied (pulled up) to any voltage between 0 V and
3.6 V.
GL
Globals
User-Defined Supply Pins
GL I/Os have access to certain clock conditioning circuitry
(and the PLL) and/or have direct access to the global
network (spines). Additionally, the global I/Os can be
used as Pro I/Os, since they have identical capabilities.
Unused GL pins are configured as inputs with pull-up
resistors. See more detailed descriptions of global I/O
connectivity in the "Clock Conditioning Circuits" section
on page 2-22.
V
I/O Voltage Reference
REF
Reference voltage for I/O minibanks. Both the AFS600
(north bank only) and AFS1500 (all digital I/O banks)
support Actel Pro I/O. These I/O banks support voltage
reference standard I/O. The VREF pins are configured by
the user from regular I/Os, and any I/O in a bank, except
JTAG I/Os, which can be designated as the voltage
reference I/O. Only certain I/O standards require a
voltage reference – HSTL (I) and (II), SSTL2 (I) and (II),
SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support
the number of I/Os available in its minibank.
Refer to the "User I/O Naming Convention" section on
page 2-120 for a description of naming of global pins.
JTAG Pins
VAREF
Analog Reference Voltage
Fusion devices have a separate bank for the dedicated
JTAG pins. The JTAG pins can be run at any voltage from
1.5 V to 3.3 V (nominal). VCC must also be powered in
order for the JTAG state machine to operate even if the
Analog reference voltage to be used by analog to digital
converter. The Fusion device provides a 2.56 V internal
reference voltage that can be used by the ADC.
Optionally this voltage can be configured to be brought
Advanced v0.7
2-169
Fusion Family of Mixed-Signal Flash FPGAs
device is in bypass mode; VJTAG alone is insufficient.
Both VJTAG and VCC to the Fusion part must be supplied
to allow JTAG signals to transition the Fusion device.
Isolating the JTAG power supply.
circuitry. There is an internal weak pull-up resistor on the
TRST pin. If JTAG is not used, an external pull-down
resistor could be included to ensure the TAP is held in
reset mode. The resistor values must be chosen from
Table 2-149 and must satisfy the parallel resistance value
requirement. The values in Table 2-149 correspond to the
resistor recommended when a single device is used and
to the equivalent parallel resistor when multiple devices
are connected via a JTAG chain.
in a separate I/O bank gives greater flexibility with
supply selection and simplifies power supply and printed
circuit board design. If the JTAG interface is not used nor
planned to be used, the VJTAG pin together with the TRST
pin could be tied to GND.
In critical applications, an upset in the JTAG circuit could
allow entering an undesired JTAG state. In such cases,
Actel recommends tying off TRST to GND through a
resistor placed close to the FPGA pin.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG.
The TCK pin does not have an internal pull-up/down
resistor. If JTAG is not used, Actel recommends tying off
TCK to GND or VJTAG through a resistor placed close to
the FPGA pin. This prevents JTAG operation in case TMS
enters an undesired state.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements.
Special Function Pins
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements. Refer to Table 2-149 for
more information.
NC
No Connect
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
Table 2-149 • Recommended Tie-Off Values for the TCK and
TRST Pins
VJTAG
Tie Off Resistance2, 3
200 Ω to 1 kΩ
DC
Don't Connect
VJTAG at 3.3 V
VJTAG at 2.5 V
This pin should not be connected to any signals on the
printed circuit board (PCB). These pins should be left un-
connected.
200 Ω to 1 kΩ
VJTAG at 1.8 V
500 Ω to 1 kΩ
NCAP
Negative Capacitor
VJTAG at 1.5 V
500 Ω to 1 kΩ
NEGATIVE CAPACITOR is where the negative terminal of
the charge pump capacitor is connected.
Notes:
1. Equivalent parallel resistance if more than one device is on
JTAG chain.
PCAP
Positive Capacitor
2. The TCK pin can be pulled-up/down.
3. The TRST pin can only be pulled-down.
POSITIVE CAPACITOR is where the positive terminal of
the charge pump capacitor is connected.
PUB
Power Up Bar
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ
will satisfy the requirements.
PUSH BUTTON is the connection for the external
momentary switch which is used to turn on the 1.5 V
voltage regulator and can be floating if not used.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG
usage. There is an internal weak pull-up resistor on the
TDI pin.
PTBASE
Pass Transistor Base
PASS TRANSISTOR BASE is the control signal of the
voltage regulator. This pin should be connected to the
base of the external pass transistor used with the 1.5 V
internal voltage regulator and can be floating if not
used.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG
usage.
TMS
Test Mode Select
PTEM
Pass Transistor Emitter
The TMS pin controls the use of the IEEE1532 boundary
scan pins (TCK,TDI, TDO, TRST). There is an internal weak
pull-up resistor on the TMS pin.
PASS TRANSISTOR EMITTER is the feedback input of
the voltage regulator.
This pin should be connected to the Emitter of the
external pass transistor used with the 1.5 V internal
voltage regulator and can be floating if not used.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active low input to
asynchronously initialize (or reset) the boundary scan
2-170
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
V
Analog Power Filter
•
SmartPower – a sophisticated power analysis
environment that gives designers the ability to
quickly determine the power consumption of an
FPGA or its components
PinEditor – a graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor – displays all assigned and
unassigned I/O macros and their attributes in a
spreadsheet format
CC33ACAP
Analog power pin for the analog power supply low pass
filter. An external 1 µF capacitor should be connected
between this pin and ground.
•
•
XTAL1
Crystal Oscillator Circuit Input
Input to crystal oscillator circuit. Pin for connecting
external crystal, ceramic resonator, RC network, or
external clock input. When using an external crystal or
ceramic oscillator external capacitors are also
recommended (< 2 MHz 100 pF, > 2 MHz – 15 pF).
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, the Actel back-
annotation flow is compatible with all the major
simulators. Included in the Designer software is
SmartGen core generator, which easily creates commonly
used logic functions for implementation into your
Fusion-based schematic or HDL design.
If using external RC network or clock input, XTAL1
should be used and XTAL2 left unconnected.
XTAL2
Crystal Oscillator Circuit Input
Input to crystal oscillator circuit. Pin for connecting
external crystal, ceramic resonator, RC network, or
external clock input. When using an external crystal or
ceramic oscillator external capacitors are also
recommended (<2 MHz 100 pF, >2 MHz – 15 pF).
Actel Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Cadence®, Magma®, Mentor
Graphics, Synopsys, and Synplicity. The Designer software
is available for both the Windows® and UNIX operating
systems.
If using external RC network or clock input, XTAL1
should be used and XTAL2 left unconnected.
Software Tools and Programming
CoreMP7 Software Tools
CoreConsole is the Intellectual Property Deployment
Platform (IDP) that assists the developer in programming
the soft ARM (CoreMP7) core onto M7 Fusion devices.
CoreConsole provides the seamless environment to work
with Libero IDE and Designer FPGA development
software tools concurrently.
Overview of Tools Flow
The Fusion family of FPGAs is fully supported by both
Actel Libero IDE and Designer FPGA Development
software. Actel Libero IDE is an integrated design
manager that seamlessly integrates design tools while
guiding the user through the design flow, managing all
design and log files, and passing necessary design data
among tools. Additionally, Libero IDE allows users to
integrate both schematic and HDL synthesis into a single
flow and verify the entire design in a single environment
(see the Libero IDE flow diagram located on the Actel
website). Libero IDE includes Synplify® AE from
Synplicity®, ViewDraw® AE from Mentor Graphics®,
ModelSim® HDL Simulator from Mentor Graphics,
WaveFormer Lite™ AE from SynaptiCAD®, PALACE™ AE
Physical Synthesis from Magma Design Automation™,
and Designer software from Actel.
Security
Fusion devices have a built-in 128-bit AES decryption
core. The decryption core facilitates secure, in-system
programming of the FPGA core array fabric and the
FlashROM. The FlashROM and the FPGA core fabric can
be programmed independently from each other,
allowing the FlashROM to be updated without the need
for change to the FPGA core fabric. The AES master key is
stored in on-chip nonvolatile memory (Flash). The AES
master key can be preloaded into parts in a secure
programming environment (such as the Actel in-house
programming center) and then "blank" parts can be
shipped to an untrusted programming or manufacturing
center for final personalization with an AES encrypted
bitstream. Late stage product changes or personalization
can be implemented easily and securely by simply
sending a STAPL file with AES encrypted data. Secure
remote field updates over public networks (such as the
Internet) are possible by sending and programming a
STAPL file with AES encrypted data. For more
information, refer to the Fusion Security application
note.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of back-end support
tools for FPGA development. The Designer software
includes the following:
•
SmartTime – a world-class integrated static timing
analyzer and constraints editor that supports
timing-driven place-and-route
•
•
NetlistViewer – a design netlist schematic viewer
ChipPlanner – a graphical floorplanning viewer
and editor
Advanced v0.7
2-171
Fusion Family of Mixed-Signal Flash FPGAs
unprogrammed state, all user I/O pins are disabled. This is
achieved by keeping the global IO_EN signal deactivated,
which also has the effect of disabling the input buffers.
Consequently, the SAMPLE instruction will have no effect
while the Fusion device is in this unprogrammed state—
different behavior from that of the ProASICPLUS® device
family. This is done because SAMPLE is defined in the
IEEE1532 specification as a noninvasive instruction. If the
input buffers were to be enabled by SAMPLE temporarily
turning on the I/Os, then it would not truly be a
noninvasive instruction.
128-Bit AES Decryption
The 128-bit AES standard (FIPS-192) block cipher is the
National Institute of Standards and Technology (NIST)
replacement for the DES (Data Encryption Standard
FIPS46-2). AES has been designed to protect sensitive
government information well into the 21st century. It
replaces the aging DES, which NIST adopted in 1977 as a
Federal Information Processing Standard used by federal
agencies to protect sensitive, unclassified information.
The 128-bit AES standard has 3.4x1038 possible 128-bit
key variants, and it has been estimated that it would
take 1,000 trillion years to crack 128-bit AES cipher text
using exhaustive techniques. Keys are stored (securely) in
Fusion devices in nonvolatile Flash memory. All
programming files sent to the device can be
authenticated by the part prior to programming to
ensure that bad programming data is not loaded into
the part that may possibly damage it. All programming
verification is performed on-chip, ensuring that the
contents of Fusion devices remain secure.
Boundary Scan
Fusion devices are compatible with IEEE Standard 1149.1,
which defines a hardware architecture and the set of
mechanisms for boundary scan testing. The basic Fusion
boundary scan logic circuit is composed of the test access
port (TAP) controller, test data registers, and instruction
register (Figure 2-122 on page 2-173). This circuit
supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS) and the optional
IDCODE instruction (Table 2-151 on page 2-173).
AES decryption can also be used on the 1,024-bit
FlashROM to allow for secure remote updates of the
FlashROM contents. This allows for easy, secure support
for subscription model products.
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI, TDO (test
data input and output), TMS (test mode selector), and
TRST (test reset input). TMS, TDI, and TRST are equipped
with pull-up resistors to ensure proper operation when
no input data is supplied to them. These pins are
dedicated for boundary scan test usage. Refer to the
"JTAG Pins" section on page 2-169 for pull-up/down
recommendations for TDO and TCK pins. The TAP
controller is a 4-bit state machine (16 states) that
operates as shown in Figure 2-122 on page 2-173. The 1s
and 0s represent the values that must be present at TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
AES for Flash Memory
AES decryption can also be used on the Flash memory
blocks. This allows for the secure update of the Flash
memory blocks. During runtime, the encrypted data can
be clocked in via the JTAG interface. The data can be
passed through the internal AES decryption engine, the
decrypted data can then be stored in the Flash memory
block.
Programming
Programming can be performed using various
programming tools, such as Silicon Sculptor II (BP Micro
Systems) or FlashPro3 (Actel).
Table 2-150 • TRST and TCK Pull-Down Recommendations
VJTAG
Tie-off Resistance*
200 Ω to 1 kΩ
The user can generate *.stp programming files from the
Designer software and can use these files to program a
device.
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
200 Ω to 1 kΩ
500 Ω to 1 kΩ
Fusion devices can be programmed in system.
500 Ω to 1 kΩ
ISP
Note: *Equivalent parallel resistance if more than one device
is on JTAG chain.
Fusion devices support IEEE 1532 ISP via JTAG and require
a single VPUMP voltage of 3.3 V during programming. In
addition, programming via a Microcontroller (MCU) in a
target system can be achieved.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles. The TRST pin
may also be used to asynchronously place the TAP
controller in the Test-Logic-Reset state.
JTAG IEEE 1532
Programming with IEEE 1532
Fusion devices support the JTAG-based IEEE1532 standard
for ISP. As part of this support, when a Fusion device is in an
2-172
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Fusion devices support three types of test data registers:
bypass, device identification, and boundary scan. The
bypass register is selected when no other register needs
to be accessed in a device. This speeds up test data
transfer to other devices in a test data path. The 32-bit
device identification register is a shift register with four
fields (LSB, ID number, part number, and version). The
boundary scan register observes and controls the state of
each I/O pin. Each I/O cell has three boundary scan
register cells, each with a serial-in, serial-out, parallel-in,
and parallel-out pin.
The serial pins are used to serially connect all the
boundary scan register cells in a device into a boundary
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic I/O tile and the input, output, and
control ports of an I/O buffer to capture and load data
into the register to control or observe the logic state of
each I/O.
I/O
I/O
I/O
I/O
I/O
Test Data
Registers
Bypass Register
Instruction
Register
TAP
Controller
Device
Logic
I/O
I/O
I/O
I/O
I/O
Figure 2-122 • Boundary Scan Chain in Fusion
Table 2-151 • Boundary Scan Opcodes
Hex Opcode
EXTEST
00
07
0E
01
0F
05
FF
HIGHZ
USERCODE
SAMPLE/PRELOAD
IDCODE
CLAMP
BYPASS
Advanced v0.7
2-173
Fusion Family of Mixed-Signal Flash FPGAs
IEEE 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the
corresponding standard selected, refer to the I/O Timing characteristics for more details.
Table 2-152 • JTAG 1532
Commercial Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tDISU
Description
Test Data Input Setup Time
–2
–1
Std.
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (Data Out)
Reset to Q (Data Out)
ns
tTMSSU
ns
tTMDHD
tTCK2Q
ns
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
ns
TCK maximum frequency
ResetB Removal time
20
20
20
MHz
ns
ResetB Recovery time
ns
ResetB minimum pulse
ns
Note: For the derating values at specific junction-temperature and voltage-supply levels, refer to Table 3-7 on page 3-7.
2-174
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
DC and Power Characteristics
General Specifications
DC and switching characteristics for –F speed grade targets are based only on simulation.
The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in the Table 3-1 may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not
be operated outside the recommended operating ranges specified in Table 3-2 on page 3-2.
Table 3-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
Limits
Units
–0.3 to 1.65
V
V
V
V
V
V
V
VJTAG
VPUMP
VCCPLL
VCCI
JTAG DC voltage
–0.3 to 3.75
Programming voltage
–0.3 to 3.75
Analog power supply (PLL)
DC I/O output buffer supply voltage
DC I/O input buffer supply voltage
I/O input voltage
–0.3 to 1.65
–0.3 to 3.75
VMV
VI
–0.3 to 3.75
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when
I/O hot-insertion mode is disabled)
VCC33A
VAREF
(+3.3 V) power supply
–0.3 to 3.75
1.0 to 3.75
–0.3 to 1.65
–0.3 to 1.65
–0.3 to 3.75
V
V
V
V
V
Voltage reference for ADC
Digital Power supply for the analog system
Embedded Flash power supply
Oscillator power supply
VCC15A
VCCNVM
VCCOSC
Notes:
1. Device performance is not guaranteed if storage temperature exceeds 110°C.
2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or
overshoot according to the limits shown in Table 3-4 on page 3-3.
Advanced v0.7
3-1
Fusion Family of Mixed-Signal Flash FPGAs
Table 3-2 • Recommended Operating Conditions
Symbol
TA, TJ
Parameter
Ambient and Junction temperature
1.5 V DC core supply voltage
JTAG DC voltage
Commercial
0 to +70
Industrial
–40 to +85
1.425 to 1.575
1.4 to 3.6
Units
°C
V
VCC
1.425 to 1.575
1.4 to 3.6
VJTAG
V
VPUMP
Programming voltage
Programming mode
Operation3
3.0 to 3.6
3.0 to 3.6
V
0 to 3.6
0 to 3.6
V
VCCPLL
Analog power supply (PLL)
1.4 to 1.6
1.4 to 1.6
V
V
CCI and VMV 1.5 V DC supply voltage
1.425 to 1.575
1.7 to 1.9
1.425 to 1.575
1.7 to 1.9
V
1.8 V DC supply voltage
2.5 V DC supply voltage
3.3 V DC supply voltage
LVDS differential I/O
V
2.3 to 2.7
2.3 to 2.7
V
3.0 to 3.6
3.0 to 3.6
V
2.375 to 2.625
3.0 to 3.6
2.375 to 2.625
3.0 to 3.6
V
LVPECL differential I/O
(+3.3 V) power supply
Voltage reference for ADC
V
VCC33A
VAREF
2.97 to 3.63
2.527 to 2.593
1.425 to 1.575
1.425 to 1.575
2.97 to 3.63
2.97 to 3.63
2.527 to 2.593
1.425 to 1.575
1.425 to 1.575
2.97 to 3.63
V
V
VCC15A
VCCNVM
VCCOSC
Notes:
Digital Power supply for the analog system
Embedded Flash power supply
Oscillator power supply
V
V
V
1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given
in Table 2-73 on page 2-126. VMV and VCCI must be connected to the same power supply and VCCI pins within a given I/O bank.
2. All parameters representing voltages are measured with respect to GND unless otherwise specified.
3. VPUMP can be left floating during normal operation (not programming mode).
Table 3-3 • Required Conditions to Avoid Stress on Analog Input Pads
Input Resistance
Pads
Pad Configuration
Direct input*
Polarity
Prescaler Range
16 V, 8 V, 4 V, 2 V
1 V, 0.5 V, 0.25 V, 0.125 V
16 V, 8 V, 4 V, 2 V
1 V, 0.5 V, 0.25 V, 0.125 V
16 V, 8 V, 4 V, 2 V
1 V, 0.5 V, 0.25 V, 0.125 V
16 V, 8 V, 4 V, 2 V
16 V, 8 V, 4 V, 2 V
16 V, 8 V, 4 V, 2 V
16 V, 4 V
to Ground
1 MΩ (typ)
> 10 MΩ
AV, AC
Positive
Postive Prescaler
Positive
1 MΩ (typ)
> 10 MΩ
Negative Prescaler
Negative
1 MΩ (typ)
> 10 MΩ
Digital input
Positive
Positive
Negative
Positive
Positive
Positive
Positive
1 MΩ (typ)
1 MΩ (typ)
1 MΩ (typ)
1 MΩ (typ)
1 MΩ (typ)
1 MΩ (typ)
> 10 MΩ
Positive Current Monitor
Negative Current Monitor
Direct input
AT
Postive Prescaler
Digital input
16 V, 4 V
16 V, 4 V
Temprature Monitor
16 V, 4 V
Note: *AFS600 should always use high prescaler ranges in Direct input mode.
3-2
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 3-4 • Overshoot and Undershoot Limits (as measured on quiet I/Os)1
Average VCCI-GND Overshoot or Undershoot Duration as a
Percentage of Clock Cycle2
Maximum Overshoot/
Undershoot)2
VCCI and VMV
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3.0 V
3.3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
10%
5%
3.6 V
10%
5%
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one cycle out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at
1 out of 2 cycles, then the maximum overshoot/undershoot has to be reduced by 0.15 V.
Table 3-5 • FPGA Programming, Storage, and Operating Limits
Maximum Operating
Grade
Programming
Cycles
Storage Temperature
Junction
Program
Retention
Products
Min.
0
Max.
Temperature TJ (°C)
Commercial
500
1 k
20 years
20 years
5 years
110
110
110
110
110
110
110
110
110
110
110
110
0
15 k
500
1 k
0
Industrial
20 years
20 years
5 years
-40
-40
-40
15 k
Note: This is a stress rating only. Functional operation at any other condition other than those indicated is not implied.
Advanced v0.7
3-3
Fusion Family of Mixed-Signal Flash FPGAs
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and
Industrial)
Sophisticated power-up management circuitry is
designed into every Fusion device. These circuits ensure
easy transition from the powered-off state to the
powered-up state of the device. The many different
supplies can power-up in any sequence with minimized
current spikes or surges. In addition, the I/O will be in a
known state through the power-up sequence. The basic
principle is shown in Figure 3-1.
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV
higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up
oscillations and current surges. Note the following:
•
During programming, I/Os become tristated and
weakly pulled up to VCCI
JTAG supply, PLL power supplies, and charge pump
PUMP supply have no influence on I/O behavior.
There are five regions to consider during power-up.
.
Fusion I/Os are activated only if ALL of the following
three conditions are met:
•
V
1. VCC and VCCI are above the minimum specified trip
points (Figure 3-1).
Internal Power-Up Activation Sequence
2. VCCI > VCC – 0.75 V (Typical).
3. Chip is in the operating mode.
1. Core
2. Input buffers
V
CCI Trip Point:
3. Output buffers, after 200 ns delay from input
buffer activation.
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
V
= V + VT
CCI
CC
Where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
V
CC
V
= 1.575 V
CC
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
speed, VIH/VIL , VOH/VOL , etc.
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH/VIL levels, and output
buffers do not meet VOH/VOL levels.
V
= 1.425 V
CC
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
Activation trip point:
V = 0.85 V 0.25 V
a
Deactivation trip point:
Region 1: I/O buffers are OFF
V
= 0.75 V 0.25 V
d
V
Activation trip point:
CCI
Min V datasheet specification
CCI
V = 0.9 V 0.3 V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
a
Deactivation trip point:
V
= 0.8 V 0.3 V
d
Figure 3-1 • I/O State as a Function of VCCI and VCC Voltage Levels
3-4
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software
refers to the junction temperature, not the ambient,
case, or board temperatures. This is an important
distinction because dynamic and static power
consumption will cause the chip's junction temperature
to be higher than the ambient, case, or board
temperatures. EQ 3-1 and EQ 3-3 give the relationship
between thermal resistance, temperature gradient, and
power.
where:
Junction-to-air thermal resistance
Junction-to-board thermal resistance
Junction-to-case thermal resistance
Junction temperature
θJA
θJB
θJC
TJ
=
=
=
=
=
=
Ambient temperature
TA
Board temperature (measured 1.0 mm away
from the package edge)
TB
TJ – θA
θJA = ----------------
P
Case temperature
TC
P
=
=
EQ 3-1
Total power dissipated by the device
TJ – TB
θJB = ----------------
P
EQ 3-2
TJ – TC
θJC = ----------------
P
EQ 3-3
Table 3-6 • Package Thermal Resistance
θJA
Product
Still Air
TBD
1.0 m/s
TBD
2.5 m/s
TBD
θJC
TBD
TBD
TBD
TBD
TBD
TBD
TBD
5.80
TBD
8.28
TBD
TBD
θJB
TBD
TBD
TBD
TBD
TBD
TBD
TBD
16.40
TBD
10.87
TBD
TBD
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
AFS090-QN108
AFS090-QN180
AFS250-QN180
AFS250-PQ208
AFS600-PQ208
AFS090-FG256
AFS250-FG256
AFS600-FG256
AFS1500-FG256
AFS600-FG484
AFS1500-FG484
AFS1500-FG676
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
36.86
TBD
25.11
TBD
22.62
TBD
30.67
TBD
19.00
TBD
17.00
TBD
TBD
TBD
TBD
Advanced v0.7
3-5
Fusion Family of Mixed-Signal Flash FPGAs
Theta-JA
Calculation for Heat Sink
Junction-to-ambient
thermal
resistance
(θJA)
is
For example, in a design implemented in an AFS600-
FG484 package with 2.5 m/s airflow, the power
consumption value using the power calculator is 3.00 W.
The user-dependent Ta and Tj are given as follows:
determined under standard conditions specified by
JEDEC (JESD-51), but it has little relevance in actual
performance of the product. It should be used with
caution but is useful for comparing the thermal
performance of one package to another.
TJ
=
=
110.00°C
70.00°C
TA
A sample calculation showing the maximum power
dissipation allowed for the AFS600-FG484 package under
forced convection of 1.0 m/s and 75°C ambient
temperature is as follows:
From the datasheet:
θJA
θJC
=
=
17.00°C/W
8.28°C/W
T
J(MAX) – TA(MAX)
Maximum Power Allowed = ------------------------------------------
θJA
EQ 3-4
TJ – TA
110°C – 70°C
17.00 W
P = ---------------- = ---------------------------------- = 2.35 W
where:
θJA
θJA
=
19.00°C/W (taken from Table 3-6 on page 3-5).
75.00°C
EQ 3-5
The 2.35 W power is less than the required 3.00 W. The
design therefore requires a heat sink, or the airflow
where the device is mounted should be increased. The
design's total junction-to-air thermal resistance
requirement can be estimated by EQ 3-6:
TA
=
110.00°C – 75.00°C
Maximum Power Allowed = --------------------------------------------------- = 1.84 W
19.00°C/W
The power consumption of a device can be calculated
using the Actel power calculator. The device's power
consumption must be lower than the calculated
maximum power dissipation by the package. If the
power consumption is higher than the device's maximum
allowable power dissipation, then a heat sink can be
attached on top of the case or the airflow inside the
system must be increased.
TJ – TA
θja(total) = ---------------- = ---------------------------------- = 13.33°C/W
3.00 W
110°C – 70°C
P
EQ 3-6
EQ 3-7
Determining the heat sink's thermal performance:
θJA(TOTAL) = θJC + θCS + θSA
where:
Theta-JB
Junction-to-board thermal resistance (θJB) measures the
ability of the package to dissipate heat from the surface
of the chip to the printed circuit board. As defined by the
JEDEC (JESD-51) standard, the thermal resistance from
junction to board uses an isothermal ring cold plate zone
concept. The ring cold plate is simply a means to
generate an isothermal boundary condition at the
perimeter. The cold plate is mounted on a JEDEC
standard board with a minimum distance of 5.0 mm
away from the package edge.
θJA
=
=
0.37 °C/W
Thermal resistance of the interface material
between the case and the heat sink, usually
provided by the thermal interface manufacturer
θSA
=
Thermal resistance of the heat sink in °C/W
θSA = θJA(TOTAL) – θJC – θCS
EQ 3-8
θSA = 13.33°C/W – 8.28°C/W – 0.37°C/W = 5.01°C/W
Theta-JC
Junction-to-case thermal resistance (θJC) measures the
ability of a device to dissipate heat from the surface of
the chip to the top or bottom surface of the package. It
is applicable for packages used with external heat sinks.
Constant temperature is applied to the surface in
consideration and acts as a boundary condition. This only
applies to situations where all or nearly all of the heat is
dissipated through the surface in consideration.
A heat sink with a thermal resistance of 5.01°C/W or
better should be used. Thermal resistance of heat sinks is
a function of airflow. The heat sink performance can be
significantly improved with increased airflow.
Carefully estimating thermal resistance is important in
the long-term reliability of an Actel FPGA. Design
engineers should always correlate the power
consumption of the device with the maximum allowable
power dissipation of the package selected for that
device.
3-6
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard (JESD-51) and
assumptions made in building the model. It may not be realized in actual application and therefore should be used
with a degree of caution. Junction-to-case thermal resistance assumes that all power is dissipated through the case.
Temperature and Voltage Derating Factors
Table 3-7 • Temperature and Voltage Derating Factors for Timing Delays
(Normalized to TJ = 70°C, VCC = 1.425 V)
Junction Temperature (°C)
Array Voltage
VCC (V)
–40°C
0°C
0.93
0.88
0.85
25°C
0.95
0.90
0.86
70°C
1.00
0.95
0.91
85°C
1.02
0.96
0.93
100°C
1.05
1.425
0.88
1.500
0.83
0.99
1.575
0.80
0.96
Calculating Power Dissipation
Quiescent Supply Current
1
Table 3-8 • Quiescent Supply Current Characteristics (IDDQ
)
Parameter
Conditions and Modes
Maximum in operating mode (85°C) 2
Maximum in operating mode (70°C) 2
Typical in operating mode (25°C) 2
Typical in standby mode (25°C) 3
Typical in sleep mode (25°C) 4
AFS600
45 mA
30 mA
5 mA
AFS250
30 mA
20 mA
3 mA
AFS090
15 mA
10 mA
2 mA
IDC1
IDC2
200 µA
10 µA
200 µA
10 µA
200 µA
10 µA
IDC3
Notes:
1. –F speed grade devices may experience higher Quiescent Supply current of up to five times the standard IDD and higher I/O
leakage.
2.
I
DC1 includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 3-9 on
page 3-8 and Table 3-10 on page 3-9.
3. IDC2 represents the current from the VCC33A supply when the RTC (and the crystal oscillator) is ON, the FPGA is OFF, and voltage
regulator is OFF.
4. IDC3 represents the current from the VCC33A supply when the RTC (and the crystal oscillator), the FPGA, and the voltage regulator
are OFF.
Advanced v0.7
3-7
Fusion Family of Mixed-Signal Flash FPGAs
Power Per I/O Pin
Table 3-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings1, 2
Static Power
Dynamic Power
PAC9 (µW/MHz)4
VMV (V)
PDC7 (mW)3
Single-Ended
3.3 V LVTTL/LVCMOS
3.3 V LVTTL/LVCMOS – Schmitt trigger
2.5 V LVCMOS
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
3.3
3.3
3.3
3.3
–
–
–
–
–
–
–
–
–
–
–
–
17.39
25.51
5.76
2.5 V LVCMOS – Schmitt trigger
1.8 V LVCMOS
7.16
2.72
1.8 V LVCMOS – Schmitt trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
3.3 V PCI
2.80
2.08
2.00
18.82
20.12
18.82
20.12
3.3 V PCI – Schmitt trigger
3.3 V PCI-X
3.3 V PCI-X – Schmitt trigger
Voltage-Referenced
3.3 V GTL
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
2.90
2.13
2.81
2.57
0.17
0.17
1.38
1.38
3.21
3.21
8.23
4.78
4.14
3.71
2.03
2.03
4.48
4.48
9.26
9.26
2.5 V GTL
3.3 V GTL +
2.5 V GTL +
HSTL (I)
HSTL (II)
SSTL2 (I)
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS, BLVDS, M-LVDS
LVPECL
2.5
3.3
2.26
5.71
1.50
2.17
Notes:
1. Input buffer power values provided in this table correspond to Pro I/Os. Pins assigned to east and west peripheries may have slightly
lower power characteristics.
2. For a different pin location, Actel recommends using the Actel power calculator or SmartPower in Actel Libero IDE software.
3. PDC7 is the static power (where applicable) measured on VMV.
4. PAC9 is the total dynamic power measured on VCC and VMV.
3-8
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Table 3-10 • Summary of I/O Output Buffer Power (Per Pin)—Default I/O Software Settings1, 2, 3
Static Power
PDC8 (mW)4
Dynamic Power
PAC10 (µW/MHz)5
CLOAD (pF)
VCCI (V)
Single-Ended
3.3 V LVTTL/LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
35
35
35
35
10
10
3.3
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
–
474.70
270.73
151.78
104.55
204.61
204.61
3.3 V PCI-X
Voltage-Referenced
3.3 V GTL
10
10
10
10
20
20
30
30
30
30
3.3
2.5
3.3
2.5
1.5
1.5
2.5
2.5
3.3
3.3
–
24.08
13.52
2.5 V GTL
–
3.3 V GTL+
–
24.10
2.5 V GTL+
–
13.54
HSTL (I)
7.08
13.88
16.69
25.91
26.02
42.21
26.22
HSTL (II)
27.22
SSTL2 (I)
105.56
116.60
114.87
131.76
SSTL2 (II)
SSTL3 (I)
SSTL3 (II)
Differential
LVDS, BLVDS, M-LVDS
LVPECL
–
–
2.5
3.3
7.70
89.62
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. Output buffer power values provided in this table correspond to Pro I/Os. Output buffers assigned to east and west peripheries may
have slightly lower power characteristics.
3. For a different pin location, output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or
SmartPower in Actel Libero IDE software.
4. PDC8 is the static power (where applicable) measured on VCCI
.
5. PAC10 is the total dynamic power measured on VCC and VCCI
.
Advanced v0.7
3-9
Fusion Family of Mixed-Signal Flash FPGAs
Dynamic Power Consumption of Various Internal Resources
Table 3-11 • Different Components Contributing to the Dynamic Power Consumption in Fusion Devices
Device-Specific Dynamic
Contributions
Power Supply
Parameter
PAC1
Definition
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Name Setting AFS600 AFS250 AFS090
Units
VCC
VCC
VCC
VCC
1.5 V
1.5 V
1.5 V
1.5 V
12.8
1.9
12.8
1.9
12.8
1.9
µW/MHz
µW/MHz
µW/MHz
µW/MHz
PAC2
PAC3
0.81
0.11
0.81
0.11
0.81
0.11
PAC4
Clock contribution of
sequential module
a VersaTile used as a
PAC5
PAC6
PAC7
First contribution of a VersaTile used as a sequential
module
VCC
VCC
VCC
VCC
1.5 V
1.5 V
1.5 V
1.5 V
0.07
0.29
0.29
0.70
0.07
0.29
0.29
0.70
0.07
0.29
0.29
0.70
µW/MHz
µW/MHz
µW/MHz
µW/MHz
Second contribution of a VersaTile used as a
sequential module
Contribution of a VersaTile used as a combinatorial
module
PAC8
PAC9
Average contribution of a routing net
Contribution of an I/O input pin (standard VMV/
dependent) VCC
See Table 3-9 on page 3-8
PAC10
PAC11
PAC12
Contribution of an I/O output pin (standard VCCI/VCC
dependent)
See Table 3-10 on page 3-9
Average contribution of a RAM block during a read
operation
VCC
1.5 V
1.5 V
25.00
30.00
25.00
30.00
25.00
30.00
µW/MHz
µW/MHz
Average contribution of a RAM block during a write
operation
VCC
PAC13
PAC14
PAC15
First contribution of a PLL
VCC
VCC
VCC
1.5 V
1.5 V
1.5 V
4.00
2.00
4.00
2.00
4.00
2.00
µW/MHz
µW/MHz
µW/MHz
Second contribution of a PLL
Contribution of NVM block during a read operation
(F < 33MHz)
358.00
358.00
358.00
PAC16
PAC17
1st contribution of NVM block during a read
operation (F > 33MHz)
VCC
VCC
1.5 V
1.5 V
12.88
4.80
12.88
4.80
12.88
4.80
mW
2nd contribution of NVM block during a read
operation (F > 33MHz)
µW/MHz
PAC18
PAC19
PAC20
Crystal Oscillator contribution
VCC33A
VCC33A
VCC
3.3 V
3.3 V
1.5 V
0.63
3.30
3.00
0.63
3.30
3.00
0.63
3.30
3.00
mW
mW
mW
RC Oscillator contribution
Analog Block dynamic power contribution of ADC
3-10
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Static Power Consumption of Various Internal Resources
Table 3-12 • Different Components Contributing to the Static Power Consumption in Fusion Devices
Device-Specific Static
Power Supply
Contributions
Parameter
Definition
Name
VCC
Setting
AFS600
AFS250
AFS090
Units
PDC1
Core static power contribution in
operating mode
1.5 V
7.50
4.50
3.00
mW
PDC2
PDC3
Device static power contribution in VCC33A
standby mode
3.3 V
3.3 V
0.03
0.03
0.03
0.03
0.03
0.03
mW
mW
Device static power contribution in VCC33A
sleep mode
PDC4
PDC5
NVM static power contribution
VCC
1.5 V
3.3 V
1.19
8.25
1.19
8.25
1.19
8.25
mW
mW
Analog
Block
static
power VCC33A
contribution of ADC
PDC6
PDC7
PDC8
Analog Block
contribution per Quad
static
power VCC33A
3.3 V
3.30
3.30
3.30
mW
Static contribution per input pin – VMV/
standard dependent contribution VCC
See Table 3-9 on page 3-8
See Table 3-10 on page 3-9
Static contribution per input pin – VMV/
standard dependent contribution VCC
Advanced v0.7
3-11
Fusion Family of Mixed-Signal Flash FPGAs
Power Calculation Methodology
The section below describes a simplified method to estimate power consumption of an application. For more accurate
and detailed power estimations, use the SmartPower tool in the Libero IDE software.
The power calculation methodology described below uses the following variables:
•
•
•
•
•
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
The number of NVM blocks used in the design
The number of Analog quads used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-13 on page 3-16
Enable rates of output buffers—guidelines are provided for typical applications in Table 3-14 on page 3-16
Read rate and write rate to the RAM—guidelines are provided for typical applications in Table 3-14 on page 3-16.
Read rate to the NVM blocks
The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—P
TOTAL
Operating Mode, Standby Mode, and Sleep Mode
P
TOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
P
DYN is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
Operating Mode
P
STAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5+ (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8)
NNVM-BLOCKS is the number of NVM blocks available in the device.
NQUADS is the number of Analog Quads used in the design.
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
Standby Mode
PSTAT = PDC2
Sleep Mode
PSTAT = PDC3
Total Dynamic Power Consumption—P
Operating Mode
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC + PRC-OSC + PAB
Standby Mode
PDYN = PXTL-OSC
Sleep Mode
PDYN = 0 W
3-12
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Global Clock Dynamic Contribution—P
CLOCK
Operating Mode
P
CLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in Table 3-13 on page 3-16.
ROW is the number of VersaTile rows used in the design—guidelines are provided in Table 3-13 on page 3-16.
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
N
F
N
Standby Mode and Sleep Mode
PCLOCK = 0 W
Sequential Cells Dynamic Contribution—P
Operating Mode
S-CELL
P
S-CELL = NS-CELL * (PAC5 + (α1 / 2) * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is
used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-16.
FCLK is the global clock signal frequency.
Standby Mode and Sleep Mode
PS-CELL = 0 W
Combinational Cells Dynamic Contribution—P
Operating Mode
C-CELL
P
C-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-16.
FCLK is the global clock signal frequency.
Standby Mode and Sleep Mode
PC-CELL = 0 W
Routing Net Dynamic Contribution—P
Operating Mode
NET
P
NET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design.
C-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-16.
CLK is the global clock signal frequency.
N
F
Standby Mode and Sleep Mode
PNET = 0 W
Advanced v0.7
3-13
Fusion Family of Mixed-Signal Flash FPGAs
I/O Input Buffer Dynamic Contribution-P
INPUTS
Operating Mode
P
INPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-16.
FCLK is the global clock signal frequency.
Standby Mode and Sleep Mode
PINPUTS = 0 W
I/O Output Buffer Dynamic Contribution—P
Operating Mode
OUTPUTS
P
OUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-16.
β1 is the I/O buffer enable rate—guidelines are provided in Table 3-14 on page 3-16.
F
CLK is the global clock signal frequency.
Standby Mode and Sleep Mode
POUTPUTS = 0 W
RAM Dynamic Contribution—P
Operating Mode
MEMORY
P
MEMORY = (NBLOCKS * PAC11 * β2 * FREAD-CLOCK) + (NBLOCK * PAC12 * β3 * FWRITE-CLOCK
)
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations—guidelines are provided in Table 3-14 on page 3-16.
β3 the RAM enable rate for write operations—guidelines are provided in Table 3-14 on page 3-16.
FWRITE-CLOCK is the memory write clock frequency.
Standby Mode and Sleep Mode
PMEMORY = 0 W
PLL/CCC Dynamic Contribution—P
Operating Mode
PLL
P
PLL = PAC13 * FCLKIN + Σ (PAC14 * FCLKOUT)
F
CLKIN is the input clock frequency.
CLKOUT is the output clock frequency.1
F
Standby Mode and Sleep Mode
PLL = 0 W
P
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula output clock by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL
contribution.
3-14
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Nonvolatile Memory Dynamic Contribution—P
NVM
Operating Mode
The NVM dynamic power consumption is a piece-wise linear function of frequency.
P
P
NVM = NNVM-BLOCKS * β4 * PAC15 * FREAD-NVM
NVM = NNVM-BLOCKS * β4 *(PAC16 + PAC17 * FREAD-NVM) when FREAD-NVM > 33 MHz
NVM-BLOCKS is the number of NVM blocks used in the design (2 in AFS600)
β4 is the NVM enable rate for read operations. Default is 0 (NVM mainly in idle state)
READ-NVM is the NVM read-clock frequency
when FREAD-NVM ≤ 33 MHz,
N
F
Standby Mode and Sleep Mode
PNVM = 0 W
Crystal Oscillator Dynamic Contribution—P
Operating Mode
XTL-OSC
P
XTL-OSC= PAC18
Standby Mode
XTL-OSC= PAC18
Sleep Mode
XTL-OSC= 0 W
P
P
RC Oscillator Dynamic Contribution—P
RC-OSC
Operating Mode
P
RC-OSC= PAC19
Standby Mode and Sleep Mode
RC-OSC= 0 W
P
Analog System Dynamic Contribution—P
AB
Operating Mode
P
AB = PAC20
Standby Mode and Sleep Mode
AB = 0 W
P
Advanced v0.7
3-15
Fusion Family of Mixed-Signal Flash FPGAs
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of
a net is 100%, this means that this net switches at half the clock frequency. Below are some examples:
•
•
The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock frequency.
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1 = 50%
Bit 2 = 25%
…
Bit 7 (MSB) = 0.78125%
The average toggle rate is = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate
output buffers are used, the enable rate should be 100%.
Table 3-13 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
α1
α2
10%
Table 3-14 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
100%
β1
β2
β3
β4
I/O output buffer enable rate
RAM enable rate for read operations
RAM enable rate for write operations
NVM enable rate for read operations
12.5%
12.5%
0%
3-16
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Example of Power Calculation
This example considers a shift register with 5,000 storage tiles including a counter and memory that stores analog
information. The shift register is clocked at 50 MHz and stores and reads information from a RAM.
The device used is a commercial AFS600 device operating in typical conditions.
The calculation below uses the power calculation methodology previously presented and shows how to determine the
dynamic and static power consumption of resources used in the application.
Also included in the example is the calculation of power consumption in operating, standby, and sleep modes to
illustrate the benefit of power-saving modes.
Global Clock Contribution—P
CLOCK
FCLK = 50 MHz
Number of Sequential VersaTiles: NS-CELL = 5,000
Estimated number of Spines: NSPINES = 5
Estimated number of Rows: NROW = 313
Operating Mode
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
PCLOCK = (0.0128 + 5*0.0019 + 313*0.00081 + 5,000*0.00011)*50
P
CLOCK = 41.28 mW
Standby Mode and Sleep Mode
PCLOCK = 0 W
Logic – Sequential Cells, Combinational Cells, and Routing Net Contributions—P
, P
, and P
S-CELL C-CELL NET
FCLK = 50 MHz
Number of Sequential VersaTiles: NS-CELL = 5,000
Number of Combinational VersaTiles: NC-CELL = 6,000
Estimated Toggle rate of VersaTile outputs: α1 = 0.1 (10%)
Operating Mode
PS-CELL = NS-CELL * (PAC5+ (α1 / 2) * PAC6) * FCLK
PS-CELL = 5,000*(0.00007 + (0.1/2)*0.00029) * 50
P
S-CELL = 21.13 mW
P
C-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK
PC-CELL = 6,000 * (0.1/2) * 0.00029 * 50
P
C-CELL = 4.35 mW
P
NET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK
PNET = (5,000+6,000) * (0.1/2) * 0.0007 * 50
PNET = 19.25 mW
PLOGIC = PS-CELL + PC-CELL + PNET
PLOGIC = 21.13 mW + 4.35m W + 19.25 mW
PLOGIC = 44.73 mW
Advanced v0.7
3-17
Fusion Family of Mixed-Signal Flash FPGAs
Standby Mode and Sleep Mode
P
P
S-CELL = 0 W
C-CELL = 0 W
PNET = 0 W
PLOGIC = 0 W
I/O Input and Output Buffer Contribution—P
I/O
This example uses LVTTL 3.3 V I/O cells. The output buffers are 12 mA capable configured with high output slew and
are driving a 35 pF output load.
FCLK = 50 MHz
Number of input pin used: NINPUTS = 30
Number of output pins used: NOUTPUTS = 40
Estimated I/O buffer toggle rate: α2 = 0.1 (10%)
Estimated IO buffer enable rate: β1 = 1 (100%)
Operating Mode
PINPUTS = NINPUTS * (α2 /2) * PAC9 * FCLK
PINPUTS = 30 * (0.1/2) * 0.01739 * 50
P
INPUTS = 1.30 mW
P
OUTPUTS = NOUTPUTS * (α2 /2) * β1 * PAC10 * FCLK
POUTPUTS = 40 * (0.1/2) * 1 * 0.4747 * 50
P
OUTPUTS = 47.47 mW
PIO = PINPUTS + POUTPUTS
PIO = 1.30 mW + 47.47 mW
PIO = 48.77 mW
Standby Mode and Sleep Mode
PINPUTS = 0 W
P
P
OUTPUTS = 0 W
I/O = 0 W
RAM Contribution—P
MEMORY
Frequency of Read-Clock: FREAD-CLOCK = 10 MHz
Frequency of Write-Clock: FWRITE-CLOCK = 10 MHz
Number of Ram Blocks: NBLOCKS = 20
Estimated RAM Read Enable Rate: β2 = 0.125 (12.5%)
Estimated RAM Write Enable Rate: β3 = 0.125 (12.5%)
Operating Mode
PMEMORY = (NBLOCKS * PAC11 * β2 * FREAD-CLOCK) + (NBLOCK * PAC12 * β3 * FWRITE-CLOCK
)
PMEMORY =( 20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10)
PMEMORY = 1.38 mW
3-18
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Standby Mode and Sleep Mode
MEMORY = 0 W
PLL/CCC Contribution—P
P
PLL
PLL is not used in this application.
PLL = 0 W
Nonvolatile Memory—P
P
NVM
Nonvolatile memory is not used in this application.
NVM = 0 W
Crystal Oscillator—P
P
XTL-OSC
The application utilizes standby mode. The crystal oscillator is assumed to be active.
Operating Mode
PXTL-OSC = PAC18
PXTL-OSC = 0.63 mW
Standby Mode
PXTL-OSC = PAC18
PXTL-OSC = 0.63 mW
Sleep Mode
PXTL-OSC = 0 W
RC Oscillator—P
RC-OSC
Operating Mode
RC-OSC = PAC19
P
PRC-OSC = 3.30 mW
Standby Mode and Sleep Mode
PRC-OSC = 0 W
Analog System—P
AB
Number of Quads used: NQUADS = 4
Operating Mode
PAB = PAC20
PAB = 3.00 mW
Standby Mode and Sleep Mode
PAB = 0 W
Total Dynamic Power Consumption—P
Operating Mode
DYN
P
DYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC + PRC-OSC + PAB
PDYN = 41.28 mW + 21.1 mW + 4.35 mW + 19.25 mW + 1.30 mW + 47.47 mW + 1.38 mW + 0 + 0 + 0.63 mW + 3.30 mW + 3.00 mW
DYN = 143.06 mW
P
Standby Mode
PDYN = PXTL-OSC
PDYN = 0.63 mW
Advanced v0.7
3-19
Fusion Family of Mixed-Signal Flash FPGAs
Sleep Mode
P
DYN =0 W
Total Static Power Consumption—P
STAT
Number of Quads used: NQUADS = 4
Number of NVM blocks available AFS600: NNVM-BLOCKS = 2
Number of Input pins used: NINPUTS = 30
Number of Output pins used: NOUTPUTS = 40
Operating Mode
PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5+ (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8
)
P
P
STAT = 7.50 mW + (2 * 1.19 mW) + 8.25 mW + (4 * 3.30 mW) + (30 * 0.00) + (40 * 0.00)
STAT = 31.33 mW
Standby Mode
PSTAT = PDC2
PSTAT = 0.03 mW
Sleep Mode
PSTAT = PDC3
PSTAT = 0.03 mW
Total Power Consumption—P
TOTAL
In operating mode, the total power consumption of the device is 174.39 mW:
TOTAL = PSTAT + PDYN
PTOTAL = 143.06 mW + 31.33 mW
TOTAL = 174.39 mW
In standby mode, the total power consumption of the device is limited to 0.66 mW:
TOTAL = PSTAT + PDYN
PTOTAL = 0.03 mW + 0.63 mW
TOTAL = 0.66 mW
In sleep mode, the total power consumption of the device drops as low as 0.03 mW:
TOTAL = PSTAT + PDYN
PTOTAL = 0.03 mW
P
P
P
P
P
3-20
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Power Consumption
Table 3-15 • Power Consumption
Parameter
Crystal Oscillator
ISTBXTAL
Description
Condition
Min.
Typ.
Max.
Units
Standby Current of Crystal Oscillator
Operating Current
10
0.6
0.6
0.6
0.6
µA
mA
mA
mA
mA
IDYNXTAL
RC
0.032–0.2
0.2–2.0
2.0–20.0
RC Oscillator
IDYNRC
Operating Current
1
mA
ACM
Operating Current (Fixed Clock)
Operating Current (User Clock)
200
30
µA/MHz
µA
NVM System
NVM Array Operating Power
Idle
795
µA
Read
See
See
operation
Table 3-12on
page 3-11.
Table 3-12 on
page 3-11.
Erase
Write
900
900
20
µA
µA
PNVMCTRL
NVM Controller Operating Power
uW/MHz
Advanced v0.7
3-21
Fusion Family of Mixed-Signal Flash FPGAs
Package Pin Assignments
108-Pin QFN
A56
A44
B52
B41
Pin A1 Mark
A1
B1
A43
B40
B28
A30
B14
A15
B15
A16
B27
A29
Figure 4-1 • 108-Pin QFN (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
Advanced v0.7
4-1
Fusion Family of Mixed-Signal Flash FPGAs
108-Pin QFN
108-Pin QFN
108-Pin QFN
Pin Number
A1
AFS090 Function
Pin Number
AFS090 Function
GND
Pin Number
AFS090 Function
NC
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
B1
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
AV1
AC2
A2
GNDQ
GCB1/IO35PDB1V0
GCB2/IO33PDB1V0
GBA2/IO31PDB1V0
NC
A3
GAA2/IO52PDB3V0
ATRTN1
AG3
A4
GND
A5
GFA1/IO47PDB3V0
AV3
A6
GEB1/IO45PDB3V0
GBA1/IO30RSB0V0
GBB1/IO28RSB0V0
GND
VCC33ACAP
VAREF
PUB
A7
VCCOSC
A8
XTAL2
A9
GEA1/IO44PPB3V0
VCC
VCC33A
PTBASE
VCCNVM
VCC
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
GEA0/IO44NPB3V0
GBC1/IO26RSB0V0
IO21RSB0V0
GEB2/IO42PDB3V0
VCCNVM
VCC15A
PCAP
IO19RSB0V0
IO09RSB0V0
VCC
GAC0/IO04RSB0V0
TDI
NC
V
CCIB0
TDO
GNDA
AV0
GND
VJTAG
GAB0/IO02RSB0V0
GAA0/IO00RSB0V0
VCOMPLA
GDC0/IO38NDB1V0
AG0
VCCIB1
ATRTN0
AT1
GCB0/IO35NDB1V0
GCC2/IO33NDB1V0
GBB2/IO31NDB1V0
VMV1
B2
VMV3
AC1
B3
GAB2/IO52NDB3V0
AV2
B4
VCCIB3
AG2
B5
GFA0/IO47NDB3V0
GEB0/IO45NDB3V0
XTAL1
GNDQ
AT2
B6
GBA0/IO29RSB0V0
AT3
B7
VCCIB0
AC3
B8
GNDOSC
GEC2/IO43PSB3V0
GEA2/IO42NDB3V0
VCC
GBB0/IO27RSB0V0
GBC0/IO25RSB0V0
IO20RSB0V0
GNDAQ
ADCGNDREF
NC
B9
B10
B11
B11
B12
B13
B14
B15
B16
B17
B18
B19
IO10RSB0V0
GNDA
PTEM
VCC
GAC1/IO05RSB0V0
GAB1/IO03RSB0V0
VCC
GNDNVM
NCAP
GNDNVM
VPUMP
VCC33PMP
VCC33N
GAA1/IO01RSB0V0
VCCPLA
TCK
TMS
GNDAQ
TRST
AC0
GDB1/IO39PSB1V0
GDC1/IO38PDB1V0
AT0
AG1
4-2
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
180-Pin QFN
A64
B60
C56
A49
B46
C43
Pin A1 Mark
A48
B45
A1
B1
C1
C42
C14
B15
A16
C29
B31
A33
Optional Corner
Pad (4X)
C15
B16
A17
C28
B30
A32
Figure 4-2 • 180-Pin QFN (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
Advanced v0.7
4-3
Fusion Family of Mixed-Signal Flash FPGAs
180-Pin QFN
180-Pin QFN
180-Pin QFN
Pin Number
A1
AFS090 Function
Pin Number
AFS090 Function
TDI
Pin Number
AFS090 Function
GNDQ
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
B1
B11
B12
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
GEB2/IO42PDB3V0
A2
VMV3
TDO
VCC
A3
GAB2/IO52NDB3V0
VJTAG
VCC
A4
GFA2/IO51NDB3V0
GDB1/IO39PPB1V0
GDC1/IO38PDB1V0
VCC
VCCNVM
A5
GFC2/IO50NDB3V0
VCCIB3
GFA1/IO47PPB3V0
GEB0/IO45NDB3V0
XTAL1
VCC15A
A6
NCAP
A7
GCB0/IO35NPB1V0
GCC1/IO34PDB1V0
VCCIB1
VCC33N
A8
GNDAQ
A9
AC0
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
GNDOSC
GEC2/IO43PPB3V0
IO43NPB3V0
NC
GBC2/IO32PPB1V0
VMV1
AT0
AT1
NC
AV1
GBA0/IO29RSB0V0
VCCIB0
AC2
GNDNVM
PCAP
ATRTN1
GBB0/IO27RSB0V0
GBC1/IO26RSB0V0
IO24RSB0V0
IO21RSB0V0
VCCIB0
AG3
VCC33PMP
NC
AV3
AG4
AV0
ATRTN2
AG0
NC
VCC33ACAP
VAREF
ATRTN0
AG1
IO15RSB0V0
IO10RSB0V0
IO07RSB0V0
GAC0/IO04RSB0V0
GAB1/IO03RSB0V0
VCC
AC1
PUB
AV2
PTEM
AT2
GNDNVM
VCC
AT3
AC3
GAA1/IO01RSB0V0
NC
VCC
AV4
TCK
AC4
VCOMPLA
TMS
AT4
B2
GAA2/IO52PDB3V0
GAC2/IO51PDB3V0
GFB2/IO50PDB3V0
VCC
TRST
NC
B3
GDB2/IO41PSB1V0
GDC0/IO38NDB1V0
VCCIB1
NC
B4
ADCGNDREF
VCC33A
GNDA
B5
B6
GFC0/IO49NDB3V0
GEB1/IO45PDB3V0
VCCOSC
GCA1/IO36PDB1V0
GCC0/IO34NDB1V0
GCB2/IO33PSB1V0
VCC
B7
PTBASE
VCCNVM
VPUMP
B8
B9
XTAL2
B10
GEA0/IO44NDB3V0
GBA2/IO31PDB1V0
4-4
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
180-Pin QFN
180-Pin QFN
Pin Number
AFS090 Function
Pin Number
AFS090 Function
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
C1
GNDQ
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
NC
GBA1/IO30RSB0V0
NC
GBB1/IO28RSB0V0
NC
VCC
GNDAQ
GBC0/IO25RSB0V0
NC
IO23RSB0V0
NC
IO20RSB0V0
NC
VCC
NC
IO11RSB0V0
GND
IO08RSB0V0
NC
GAC1/IO05RSB0V0
NC
VCCIB0
NC
GAB0/IO02RSB0V0
GND
GAA0/IO00RSB0V0
GDB0/IO39NPB1V0
VCCPLA
GDA1/IO37NSB1V0
NC
GCA0/IO36NDB1V0
C2
NC
GCB1/IO35PPB1V0
C3
GND
GND
C4
NC
GCA2/IO32NPB1V0
C5
GFC1/IO49PDB3V0
GBB2/IO31NDB1V0
C6
GFA0/IO47NPB3V0
NC
NC
C7
VCCIB3
C8
GND
NC
C9
GEA1/IO44PDB3V0
GND
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
GEA2/IO42NDB3V0
NC
NC
NC
IO22RSB0V0
GND
GND
NC
IO13RSB0V0
IO09RSB0V0
IO06RSB0V0
GND
NC
GNDA
NC
NC
NC
NC
NC
NC
NC
AG2
NC
Advanced v0.7
4-5
Fusion Family of Mixed-Signal Flash FPGAs
180-Pin QFN
180-Pin QFN
180-Pin QFN
Pin Number
A1
AFS250 Function
GNDQ
Pin Number
AFS250 Function
TDO
Pin Number
AFS250 Function
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
B1
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
VCC
VCCNVM
VCC15A
NCAP
A2
VMV3
VJTAG
A3
IO74NDB3V0
IO71NDB3V0
IO69NPB3V0
GDA1/IO54PPB1V0
GDB1/IO53PDB1V0
VCC
A4
A5
VCC33N
GNDAQ
AC0
A6
VCCIB3
GCB0/IO48NPB1V0
GCC1/IO47PDB1V0
VCCIB1
A7
GFB1/IO67PPB3V0
NC
A8
AT0
A9
XTAL1
GBB2/IO41PPB1V0
VMV1
AT1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
GNDOSC
AV1
GEA1/IO61PPB3V0
GEA0/IO61NPB3V0
NC
AC2
GBB1/IO37RSB0V0
ATRTN1
AG3
VCCIB3
VCCIB0
GNDNVM
PCAP
VCC33PMP
NC
GBC0/IO34RSB0V0
IO33RSB0V0
AV3
AG4
IO29RSB0V0
ATRTN2
AC5
IO26RSB0V0
AV0
VCCIB0
VCC33ACAP
VAREF
PUB
AG0
IO21RSB0V0
IO13RSB0V0
IO10RSB0V0
IO06RSB0V0
GAC1/IO05RSB0V0
VCC
ATRTN0
AG1
PTEM
AC1
GNDNVM
VCC
AV2
AT2
VCC
AT3
GAB0/IO02RSB0V0
NC
TCK
AC3
TMS
AV4
VCOMPLA
TRST
AC4
B2
GAC2/IO74PDB3V0
GFA2/IO71PDB3V0
GFB2/IO70PSB3V0
VCC
GDA2/IO55PSB1V0
GDB0/IO53NDB1V0
AT4
B3
AG5
B4
VCCIB1
AV5
B5
GCA1/IO49PDB1V0
GCC0/IO47NDB1V0
GBC2/IO42PSB1V0
VCC
ADCGNDREF
VCC33A
GNDA
PTBASE
VCCNVM
VPUMP
TDI
B6
GFC0/IO68NDB3V0
NC
B7
B8
VCCOSC
B9
XTAL2
GBA2/IO40PDB1V0
GNDQ
B10
B11
B12
GFA0/IO66NDB3V0
IO60NDB3V0
VCC
GBA0/IO38RSB0V0
GBC1/IO35RSB0V0
4-6
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
180-Pin QFN
180-Pin QFN
Pin Number
AFS250 Function
VCC
Pin Number
AFS250 Function
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
C1
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
NC
NC
IO31RSB0V0
IO28RSB0V0
IO25RSB0V0
VCC
NC
NC
GND
IO14RSB0V0
IO11RSB0V0
IO08RSB0V0
NC
NC
NC
VCCIB0
GND
GAC0/IO04RSB0V0
GDA0/IO54NPB1V0
GDC0/IO52NSB1V0
GCA0/IO49NDB1V0
GCB1/IO48PPB1V0
GND
GAA1/IO01RSB0V0
VCCPLA
NC
C2
VCCIB3
C3
GND
IO41NPB1V0
IO40NDB1V0
NC
C4
GFC2/IO69PPB3V0
C5
GFC1/IO68PDB3V0
C6
GFB0/IO67NPB3V0
GBA1/IO39RSB0V0
GBB0/IO36RSB0V0
GND
C7
NC
C8
GND
C9
GFA1/IO66PDB3V0
IO30RSB0V0
IO27RSB0V0
GND
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
GEC2/IO60PDB3V0
GEA2/IO58PSB3V0
NC
GND
NC
IO16RSB0V0
IO12RSB0V0
IO09RSB0V0
GND
NC
GNDA
NC
GAB1/IO03RSB0V0
GAA0/IO00RSB0V0
NC
NC
NC
NC
AG2
NC
NC
NC
AT5
GNDAQ
Advanced v0.7
4-7
Fusion Family of Mixed-Signal Flash FPGAs
208-Pin PQFP
208
1
208-Pin PQFP
Figure 4-3 • 208-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
4-8
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
208-Pin PQFP
208-Pin PQFP
208-Pin PQFP
Pin Number
AFS250 Function
VCCPLA
Pin Number
AFS250 Function
GEC2/IO60PDB3V0
IO60NDB3V0
GND
Pin Number
73
AFS250 Function
AV1
1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
2
VCOMPLA
74
AV2
3
GNDQ
75
AC2
4
VMV3
V
CCIB3
76
AG2
5
GAA2/IO76PDB3V0
IO76NDB3V0
GAB2/IO75PDB3V0
IO75NDB3V0
NC
GEB2/IO59PDB3V0
77
AT2
6
IO59NDB3V0
GEA2/IO58PDB3V0
IO58NDB3V0
VCC
78
ATRTN1
AT3
7
79
8
80
AG3
9
81
AC3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
VCCNVM
GNDNVM
GND
82
AV3
VCC
83
AV4
GND
84
AC4
VCCIB3
VCC15A
PCAP
85
AG4
IO72PDB3V0
IO72NDB3V0
GFA2/IO71PDB3V0
IO71NDB3V0
GFB2/IO70PDB3V0
IO70NDB3V0
GFC2/IO69PDB3V0
IO69NDB3V0
VCC
86
AT4
NCAP
VCC33PMP
VCC33N
GNDA
GNDAQ
NC
87
ATRTN2
AT5
88
89
AG5
90
AC5
91
AV5
92
NC
NC
93
NC
NC
94
NC
GND
NC
95
NC
VCCIB3
NC
96
NC
GFC1/IO68PDB3V0
GFC0/IO68NDB3V0
GFB1/IO67PDB3V0
GFB0/IO67NDB3V0
VCCOSC
NC
97
NC
NC
98
NC
NC
99
NC
NC
100
101
102
103
104
105
106
107
108
NC
AV0
GNDAQ
VCC33ACAP
ADCGNDREF
VAREF
PUB
XTAL1
AC0
XTAL2
AG0
GNDOSC
AT0
GEB1/IO62PDB3V0
GEB0/IO62NDB3V0
GEA1/IO61PDB3V0
GEA0/IO61NDB3V0
ATRTN0
AT1
VCC33A
GNDA
PTEM
AG1
AC1
Advanced v0.7
4-9
Fusion Family of Mixed-Signal Flash FPGAs
208-Pin PQFP
208-Pin PQFP
Pin Number
208-Pin PQFP
Pin Number
Pin Number
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
AFS250 Function
PTBASE
AFS250 Function
GCB1/IO48PDB1V0
GCC0/IO47NDB1V0
GCC1/IO47PDB1V0
IO42NDB1V0
GBC2/IO42PDB1V0
VCCIB1
AFS250 Function
IO21RSB0V0
IO20RSB0V0
IO19RSB0V0
IO18RSB0V0
IO17RSB0V0
IO16RSB0V0
IO15RSB0V0
VCCIB0
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GNDNVM
VCCNVM
VCC
VPUMP
GNDQ
VMV1
GND
TCK
VCC
TDI
IO41NDB1V0
GBB2/IO41PDB1V0
IO40NDB1V0
GBA2/IO40PDB1V0
GBA1/IO39RSB0V0
GBA0/IO38RSB0V0
GBB1/IO37RSB0V0
GBB0/IO36RSB0V0
GBC1/IO35RSB0V0
VCCIB0
GND
TMS
VCC
TDO
IO14RSB0V0
IO13RSB0V0
IO12RSB0V0
IO11RSB0V0
IO10RSB0V0
IO09RSB0V0
IO08RSB0V0
IO07RSB0V0
IO06RSB0V0
GAC1/IO05RSB0V0
VCCIB0
TRST
VJTAG
IO57NDB1V0
GDC2/IO57PDB1V0
IO56NDB1V0
GDB2/IO56PDB1V0
VCCIB1
GND
GND
IO55NDB1V0
GDA2/IO55PDB1V0
GDA0/IO54NDB1V0
GDA1/IO54PDB1V0
GDB0/IO53NDB1V0
GDB1/IO53PDB1V0
GDC0/IO52NDB1V0
GDC1/IO52PDB1V0
IO51NSB1V0
VCCIB1
VCC
GBC0/IO34RSB0V0
IO33RSB0V0
IO32RSB0V0
IO31RSB0V0
IO30RSB0V0
IO29RSB0V0
IO28RSB0V0
IO27RSB0V0
IO26RSB0V0
IO25RSB0V0
VCCIB0
GND
VCC
GAC0/IO04RSB0V0
GAB1/IO03RSB0V0
GAB0/IO02RSB0V0
GAA1/IO01RSB0V0
GAA0/IO00RSB0V0
GND
VCC
IO50NDB1V0
IO50PDB1V0
GCA0/IO49NDB1V0
GCA1/IO49PDB1V0
GCB0/IO48NDB1V0
GND
VCC
IO24RSB0V0
IO23RSB0V0
IO22RSB0V0
4-10
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
208-Pin PQFP
208-Pin PQFP
208-Pin PQFP
Pin Number
AFS600 Function
VCCPLA
Pin Number
AFS600 Function
Pin Number
73
AFS600 Function
AV3
1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
GEB1/IO62PDB4V0
2
VCOMPLA
GEB0/IO62NDB4V0
GEA1/IO61PDB4V0
GEA0/IO61NDB4V0
GEC2/IO60PDB4V0
IO60NDB4V0
VMV4
74
AV4
3
GAA2/IO85PDB4V0
IO85NDB4V0
GAB2/IO84PDB4V0
IO84NDB4V0
GAC2/IO83PDB4V0
IO83NDB4V0
IO77PDB4V0
IO77NDB4V0
IO76PDB4V0
IO76NDB4V0
VCC
75
AC4
4
76
AG4
5
77
AT4
6
78
ATRTN2
AT5
7
79
8
GNDQ
80
AG5
9
VCC
81
AC5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VCCNVM
GNDNVM
GND
82
AV5
83
AV6
84
AC6
VCC15A
PCAP
85
AG6
GND
86
AT6
VCCIB4
NCAP
87
ATRTN3
AT7
GFA2/IO75PDB4V0
IO75NDB4V0
GFC2/IO73PDB4V0
IO73NDB4V0
VCCOSC
VCC33PMP
VCC33N
GNDA
88
89
AG7
90
AC7
GNDAQ
AV0
91
AV7
92
AV8
XTAL1
AC0
93
AC8
XTAL2
AG0
94
AG8
GNDOSC
AT0
95
AT8
GFC1/IO72PDB4V0
GFC0/IO72NDB4V0
GFB1/IO71PDB4V0
GFB0/IO71NDB4V0
GFA1/IO70PDB4V0
GFA0/IO70NDB4V0
IO69PDB4V0
IO69NDB4V0
VCC
ATRTN0
AT1
96
ATRTN4
AT9
97
AG1
98
AG9
AC1
99
AC9
AV1
100
101
102
103
104
105
106
107
108
AV9
AV2
GNDAQ
VCC33ACAP
ADCGNDREF
VAREF
PUB
AC2
AG2
AT2
GND
ATRTN1
AT3
VCCIB4
VCC33A
GNDA
PTEM
GEC1/IO63PDB4V0
GEC0/IO63NDB4V0
AG3
AC3
Advanced v0.7
4-11
Fusion Family of Mixed-Signal Flash FPGAs
208-Pin PQFP
208-Pin PQFP
Pin Number
208-Pin PQFP
Pin Number
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
AFS600 Function
PTBASE
AFS600 Function
IO40NDB2V0
GCB2/IO40PDB2V0
IO39NDB2V0
GCA2/IO39PDB2V0
IO31NDB2V0
GBB2/IO31PDB2V0
IO30NDB2V0
GBA2/IO30PDB2V0
VMV2
Pin Number
AFS600 Function
VCCIB0
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GNDNVM
GND
VCCNVM
VCC
VCC
IO10PPB0V1
IO09PPB0V1
IO10NPB0V1
IO09NPB0V1
IO08PPB0V1
IO07PPB0V1
IO08NPB0V1
IO07NPB0V1
IO06PPB0V0
IO05PPB0V0
IO06NPB0V0
IO04PPB0V0
IO05NPB0V0
IO04NPB0V0
GAC1/IO03PDB0V0
GAC0/IO03NDB0V0
VCCIB0
VPUMP
NC
TCK
TDI
TMS
TDO
GNDQ
TRST
VCOMPLB
VJTAG
VCCPLB
IO57NDB2V0
GDC2/IO57PDB2V0
IO56NDB2V0
GDB2/IO56PDB2V0
IO55NDB2V0
GDA2/IO55PDB2V0
GDA0/IO54NDB2V0
GDA1/IO54PDB2V0
VCCIB2
VMV1
GNDQ
GBB1/IO27PPB1V1
GBA1/IO28PPB1V1
GBB0/IO27NPB1V1
GBA0/IO28NPB1V1
VCCIB1
GND
VCC
GND
GND
GBC1/IO26PDB1V1
GBC0/IO26NDB1V1
IO24PPB1V1
IO23PPB1V1
IO24NPB1V1
IO23NPB1V1
IO22PPB1V0
IO21PPB1V0
IO22NPB1V0
IO21NPB1V0
IO20PSB1V0
IO19PSB1V0
IO14NSB0V1
IO12PDB0V1
IO12NDB0V1
VCC
VCC
GAB1/IO02PDB0V0
GAB0/IO02NDB0V0
GAA1/IO01PDB0V0
GAA0/IO01NDB0V0
GNDQ
GCA0/IO45NDB2V0
GCA1/IO45PDB2V0
GCB0/IO44NDB2V0
GCB1/IO44PDB2V0
GCC0/IO43NDB2V0
GCC1/IO43PDB2V0
IO42NDB2V0
IO42PDB2V0
IO41NDB2V0
GCC2/IO41PDB2V0
VCCIB2
VMV0
GND
VCC
4-12
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
A1 Ball Pad Corner
1
7
6
4
5
3
2
16 15 14 13 12 11 10 9
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Figure 4-4 • 256-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
Advanced v0.7
4-13
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number
A1
AFS090 Function
GND
Pin Number
AFS090 Function
VCCIB0
Pin Number
AFS090 Function
IO22RSB0V0
GND
C5
C6
E9
E10
E11
E12
E13
E14
E15
E16
F1
A2
VCCIB0
GAC1/IO05RSB0V0
IO09RSB0V0
IO14RSB0V0
IO15RSB0V0
NC
A3
GAB0/IO02RSB0V0
GAB1/IO03RSB0V0
GND
C7
IO24RSB0V0
NC
A4
C8
A5
C9
VCCIB1
A6
IO07RSB0V0
IO10RSB0V0
IO11RSB0V0
IO16RSB0V0
IO17RSB0V0
IO18RSB0V0
GND
C10
C11
C12
C13
C14
C15
C16
D1
GCC2/IO33NDB1V0
A7
IO20RSB0V0
VCCIB0
GCB2/IO33PDB1V0
A8
GND
A9
GBB1/IO28RSB0V0
VMV1
GFB0/IO48NDB3V0
A10
A11
A12
A13
A14
A15
A16
B1
F2
GFB1/IO48PDB3V0
GND
F3
GFC0/IO49NDB3V0
VCCIB1
F4
NC
GBC0/IO25RSB0V0
GBA0/IO29RSB0V0
VCCIB0
GFA2/IO51NDB3V0
GAC2/IO51PDB3V0
GAB2/IO52NDB3V0
GAA2/IO52PDB3V0
NC
F5
GFC1/IO49PDB3V0
D2
F6
NC
D3
F7
NC
GND
D4
F8
NC
VCOMPLA
D5
F9
NC
B2
VCCPLA
D6
GAC0/IO04RSB0V0
IO08RSB0V0
NC
F10
F11
F12
F13
F14
F15
F16
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
NC
B3
GAA0/IO00RSB0V0
GAA1/IO01RSB0V0
NC
D7
NC
B4
D8
NC
B5
D9
NC
NC
NC
B6
IO06RSB0V0
VCCIB0
D10
D11
D12
D13
D14
D15
D16
E1
IO21RSB0V0
IO23RSB0V0
NC
B7
GCC1/IO34PDB1V0
GCC0/IO34NDB1V0
GEC0/IO46NPB3V0
VCCIB3
B8
IO12RSB0V0
IO13RSB0V0
VCCIB0
B9
GBA2/IO31PDB1V0
GBB2/IO31NDB1V0
GBC2/IO32PDB1V0
GCA2/IO32NDB1V0
GND
B10
B11
B12
B13
B14
B15
B16
C1
IO19RSB0V0
GBB0/IO27RSB0V0
GBC1/IO26RSB0V0
GBA1/IO30RSB0V0
NC
GEC1/IO46PPB3V0
GFA1/IO47PDB3V0
GND
E2
GFC2/IO50NDB3V0
GFB2/IO50PDB3V0
VCCIB3
GFA0/IO47NDB3V0
GND
E3
NC
E4
VCC
VCCIB3
E5
NC
GND
C2
GND
E6
NC
VCC
C3
VMV3
E7
GND
GDA1/IO37NDB1V0
GND
C4
NC
E8
NC
4-14
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number
AFS090 Function
IO37PDB1V0
GCB0/IO35NPB1V0
VCCIB1
Pin Number
AFS090 Function
Pin Number
M5
AFS090 Function
G13
G14
G15
G16
H1
K1
K2
NC
NC
VCCIB3
M6
NC
K3
NC
M7
NC
AG1
GCB1/IO35PPB1V0
GEB1/IO45PDB3V0
GEB0/IO45NDB3V0
XTAL2
K4
NC
M8
K5
GND
M9
NC
H2
K6
NC
M10
M11
M12
M13
M14
M15
M16
N1
AC2
H3
K7
VCC
AG3
H4
XTAL1
K8
GND
VPUMP
VCCIB1
TMS
H5
GNDOSC
K9
VCC
H6
VCCOSC
K10
K11
K12
K13
K14
K15
K16
L1
GND
H7
VCC
NC
TRST
H8
GND
GND
GND
H9
VCC
NC
GEB2/IO42PDB3V0
GEA2/IO42NDB3V0
NC
H10
H11
H12
H13
H14
H15
H16
J1
GND
NC
N2
GDC0/IO38NDB1V0
GDC1/IO38PDB1V0
GDB1/IO39PDB1V0
GDB0/IO39NDB1V0
GCA0/IO36NDB1V0
GCA1/IO36PDB1V0
GEA0/IO44NDB3V0
GEA1/IO44PDB3V0
IO43NDB3V0
GEC2/IO43PDB3V0
NC
VCCIB1
N3
NC
N4
VCC33PMP
VCC15A
NC
NC
N5
L2
NC
N6
L3
NC
N7
AC1
L4
NC
N8
NC
L5
NC
N9
NC
J2
L6
NC
N10
N11
N12
N13
N14
N15
N16
P1
AG2
J3
L7
GNDA
AC4
J4
L8
AC0
GNDA
VCC33A
VCCNVM
TCK
J5
L9
NC
J6
NC
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
NC
J7
GND
PTEM
J8
VCC
TDO
TDI
J9
GND
VJTAG
VCCNVM
GNDNVM
GNDA
NC
J10
J11
J12
J13
J14
J15
J16
VCC
NC
P2
GDC2/IO41NPB1V0
NC
GDB2/IO41PPB1V0
P3
NC
GND
NC
P4
NC
P5
NC
GDA0/IO40PDB1V0
NC
P6
NC
NC
P7
AG0
GDA2/IO40NDB1V0
VCCIB3
P8
NC
Advanced v0.7
4-15
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
Pin Number
P9
AFS090 Function
GNDA
AC3
Pin Number
AFS090 Function
GNDA
T13
T14
T15
T16
P10
P11
P12
P13
P14
P15
P16
R1
VCC33ACAP
VAREF
AV4
AG4
GND
NC
ADCGNDREF
PTBASE
GNDNVM
VCCIB3
PCAP
NC
R2
R3
R4
NC
R5
AV0
R6
AT0
R7
AV1
R8
NC
R9
AV2
R10
R11
R12
R13
R14
R15
R16
T1
AT3
AV3
NC
NC
NC
PUB
VCCIB1
GND
T2
NCAP
VCC33N
NC
T3
T4
T5
AT1
T6
ATRTN0
NC
T7
T8
NC
T9
AT2
T10
T11
T12
ATRTN1
AT4
ATRTN2
4-16
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number
AFS250 Function
GND
Pin Number
AFS250 Function
VCCIB0
Pin Number
E9
AFS250 Function
NC
A1
A2
C5
C6
VCCIB0
GAC1/IO05RSB0V0
IO12RSB0V0
IO22RSB0V0
IO23RSB0V0
IO30RSB0V0
IO31RSB0V0
VCCIB0
E10
E11
E12
E13
E14
E15
E16
F1
GND
A3
GAA0/IO00RSB0V0
GAA1/IO01RSB0V0
GND
C7
GBB1/IO37RSB0V0
IO50PPB1V0
A4
C8
A5
C9
VCCIB1
A6
IO11RSB0V0
IO14RSB0V0
IO15RSB0V0
IO24RSB0V0
IO25RSB0V0
IO26RSB0V0
GND
C10
C11
C12
C13
C14
C15
C16
D1
IO42NDB1V0
GBC2/IO42PDB1V0
GND
A7
A8
A9
GBC1/IO35RSB0V0
VMV1
NC
A10
A11
A12
A13
A14
A15
A16
B1
F2
NC
GND
F3
IO72NDB3V0
IO72PDB3V0
NC
VCCIB1
F4
GBA0/IO38RSB0V0
IO32RSB0V0
VCCIB0
IO75NDB3V0
GAB2/IO75PDB3V0
IO76NDB3V0
GAA2/IO76PDB3V0
GAB0/IO02RSB0V0
GAC0/IO04RSB0V0
IO13RSB0V0
IO20RSB0V0
IO21RSB0V0
IO28RSB0V0
GBB0/IO36RSB0V0
NC
F5
D2
F6
GAC2/IO74PPB3V0
IO09RSB0V0
IO19RSB0V0
NC
D3
F7
GND
D4
F8
VCOMPLA
D5
F9
B2
VCCPLA
D6
F10
F11
F12
F13
F14
F15
F16
G1
IO29RSB0V0
IO43NDB1V0
IO43PDB1V0
IO44NDB1V0
GCA2/IO44PDB1V0
GCB2/IO45PDB1V0
IO45NDB1V0
IO70NPB3V0
VCCIB3
B3
IO07RSB0V0
IO06RSB0V0
GAB1/IO03RSB0V0
IO10RSB0V0
VCCIB0
D7
B4
D8
B5
D9
B6
D10
D11
D12
D13
D14
D15
D16
E1
B7
B8
IO16RSB0V0
IO17RSB0V0
VCCIB0
B9
GBA2/IO40PDB1V0
IO40NDB1V0
GBB2/IO41PDB1V0
IO41NDB1V0
GND
B10
B11
B12
B13
B14
B15
B16
C1
G2
IO27RSB0V0
GBC0/IO34RSB0V0
GBA1/IO39RSB0V0
IO33RSB0V0
NC
G3
GFB2/IO70PPB3V0
GFA2/IO71PDB3V0
GND
G4
G5
E2
IO73NDB3V0
IO73PDB3V0
VCCIB3
G6
IO71NDB3V0
GND
E3
G7
NC
E4
G8
VCC
VCCIB3
E5
IO74NPB3V0
IO08RSB0V0
GND
G9
GND
C2
GND
E6
G10
G11
G12
VCC
C3
VMV3
E7
GCC0/IO47NDB1V0
GND
C4
NC
E8
IO18RSB0V0
Advanced v0.7
4-17
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number
G13
G14
G15
G16
H1
AFS250 Function
GCC1/IO47PDB1V0
IO46NPB1V0
VCCIB1
Pin Number
AFS250 Function
Pin Number
AFS250 Function
K1
K2
IO65NPB3V0
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
IO58NPB3V0
NC
V
CCIB3
K3
IO65PPB3V0
IO64PDB3V0
GND
NC
GCC2/IO46PPB1V0
GFC2/IO69PDB3V0
IO69NDB3V0
XTAL2
K4
AG1
K5
AC2
H2
K6
IO64NDB3V0
VCC
AC4
H3
K7
AG5
H4
XTAL1
K8
GND
VPUMP
VCCIB1
TMS
H5
GNDOSC
K9
VCC
H6
VCCOSC
K10
K11
K12
K13
K14
K15
K16
L1
GND
H7
VCC
GDC2/IO57PPB1V0
GND
TRST
H8
GND
GND
H9
VCC
GDA0/IO54NDB1V0
GDA2/IO55PPB1V0
VCCIB1
GEB2/IO59PDB3V0
IO59NDB3V0
GEA2/IO58PPB3V0
VCC33PMP
VCC15A
NC
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
IO51NDB1V0
IO51PDB1V0
GCA1/IO49PDB1V0
GCA0/IO49NDB1V0
GCB0/IO48NDB1V0
GCB1/IO48PDB1V0
GFA0/IO66NDB3V0
GFA1/IO66PDB3V0
GFB0/IO67NDB3V0
GFB1/IO67PDB3V0
GFC0/IO68NDB3V0
GFC1/IO68PDB3V0
GND
N3
GDB1/IO53PPB1V0
GEC1/IO63PDB3V0
GEC0/IO63NDB3V0
GEB1/IO62PDB3V0
GEB0/IO62NDB3V0
IO60NDB3V0
GEC2/IO60PDB3V0
GNDA
N4
N5
L2
N6
L3
N7
AC1
L4
N8
AG3
L5
N9
AV3
J2
L6
N10
N11
N12
N13
N14
N15
N16
P1
AG4
J3
L7
NC
J4
L8
AC0
GNDA
VCC33A
VCCNVM
TCK
J5
L9
AV2
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
AC3
J7
PTEM
J8
VCC
TDO
TDI
J9
GND
VJTAG
VCCNVM
GNDNVM
GNDA
NC
J10
J11
J12
J13
J14
J15
J16
VCC
IO57NPB1V0
GDB2/IO56PPB1V0
IO55NPB1V0
GND
P2
IO56NPB1V0
GDB0/IO53NPB1V0
GDA1/IO54PDB1V0
GDC1/IO52PPB1V0
IO50NPB1V0
GDC0/IO52NPB1V0
P3
P4
P5
NC
GEA1/IO61PDB3V0
GEA0/IO61NDB3V0
VCCIB3
P6
NC
P7
AG0
P8
AG2
4-18
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
Pin Number AFS250 Function
Pin Number
AFS250 Function
GNDA
AC5
P9
P10
P11
P12
P13
P14
P15
P16
R1
T13
T14
T15
T16
GNDA
VCC33ACAP
VAREF
NC
NC
GND
NC
ADCGNDREF
PTBASE
GNDNVM
VCCIB3
PCAP
NC
R2
R3
R4
NC
R5
AV0
R6
AT0
R7
AV1
R8
AT3
R9
AV4
R10
R11
R12
R13
R14
R15
R16
T1
AT5
AV5
NC
NC
NC
PUB
VCCIB1
GND
T2
NCAP
VCC33N
NC
T3
T4
T5
AT1
T6
ATRTN0
AT2
T7
T8
ATRTN1
AT4
T9
T10
T11
T12
ATRTN2
NC
NC
Advanced v0.7
4-19
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number
A1
AFS600 Function
GND
Pin Number
AFS600 Function
VCCIB0
Pin Number
AFS600 Function
IO20NDB1V0
GND
C5
C6
E9
E10
E11
E12
E13
E14
E15
E16
F1
A2
VCCIB0
GAC1/IO03PDB0V0
IO06NDB0V0
IO16PDB1V0
IO16NDB1V0
IO25NDB1V1
IO25PDB1V1
VCCIB1
A3
GAA0/IO01NDB0V0
GAA1/IO01PDB0V0
GND
C7
GBB1/IO27PDB1V1
IO33PSB2V0
A4
C8
A5
C9
VCCIB2
A6
IO10PDB0V1
IO12PDB0V1
IO12NDB0V1
IO22NDB1V0
IO22PDB1V0
IO24NDB1V1
GND
C10
C11
C12
C13
C14
C15
C16
D1
IO32NDB2V0
GBC2/IO32PDB2V0
GND
A7
A8
A9
GBC1/IO26PPB1V1
VMV2
IO79NDB4V0
IO79PDB4V0
IO76NDB4V0
IO76PDB4V0
IO82PSB4V0
GAC2/IO83PPB4V0
IO04PPB0V0
IO08NDB0V1
IO20PDB1V0
IO23NDB1V1
IO36NDB2V0
IO36PDB2V0
IO39NDB2V0
GCA2/IO39PDB2V0
GCB2/IO40PDB2V0
IO40NDB2V0
IO74NPB4V0
VCCIB4
A10
A11
A12
A13
A14
A15
A16
B1
F2
GND
F3
VCCIB2
F4
GBA0/IO28NDB1V1
IO29NDB1V1
VCCIB1
IO84NDB4V0
GAB2/IO84PDB4V0
IO85NDB4V0
GAA2/IO85PDB4V0
GAB0/IO02NPB0V0
GAC0/IO03NDB0V0
IO06PDB0V0
IO14NDB0V1
IO14PDB0V1
IO23PDB1V1
GBB0/IO27NDB1V1
VMV1
F5
D2
F6
D3
F7
GND
D4
F8
VCOMPLA
D5
F9
B2
VCCPLA
D6
F10
F11
F12
F13
F14
F15
F16
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
B3
IO00NDB0V0
IO00PDB0V0
GAB1/IO02PPB0V0
IO10NDB0V1
VCCIB0
D7
B4
D8
B5
D9
B6
D10
D11
D12
D13
D14
D15
D16
E1
B7
B8
IO18NDB1V0
IO18PDB1V0
VCCIB1
B9
GBA2/IO30PDB2V0
IO30NDB2V0
GBB2/IO31PDB2V0
IO31NDB2V0
GND
B10
B11
B12
B13
B14
B15
B16
C1
IO24PDB1V1
GBC0/IO26NPB1V1
GBA1/IO28PDB1V1
IO29PDB1V1
VCCPLB
GFB2/IO74PPB4V0
GFA2/IO75PDB4V0
GND
E2
IO81NDB4V0
IO81PDB4V0
VCCIB4
IO75NDB4V0
GND
E3
VCOMPLB
E4
VCC
VCCIB4
E5
IO83NPB4V0
IO04NPB0V0
GND
GND
C2
GND
E6
VCC
C3
VMV4
E7
GCC0/IO43NDB2V0
GND
C4
VMV0
E8
IO08PDB0V1
4-20
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number
AFS600 Function
GCC1/IO43PDB2V0
IO41NPB2V0
VCCIB2
Pin Number
AFS600 Function
Pin Number
M5
AFS600 Function
IO58NPB4V0
AV0
G13
G14
G15
G16
H1
K1
K2
IO67NPB4V0
V
CCIB4
M6
K3
IO67PPB4V0
IO65PDB4V0
GND
M7
AC1
GCC2/IO41PPB2V0
GFC2/IO73PDB4V0
IO73NDB4V0
XTAL2
K4
M8
AG3
K5
M9
AC4
H2
K6
IO65NDB4V0
VCC
M10
M11
M12
M13
M14
M15
M16
N1
AC6
H3
K7
AG7
H4
XTAL1
K8
GND
VPUMP
H5
GNDOSC
K9
VCC
VCCIB2
TMS
H6
VCCOSC
K10
K11
K12
K13
K14
K15
K16
L1
GND
H7
VCC
GDC2/IO57PPB2V0
GND
TRST
H8
GND
GND
H9
VCC
GDA0/IO54NDB2V0
GDA2/IO55PPB2V0
VCCIB2
GEB2/IO59PDB4V0
IO59NDB4V0
GEA2/IO58PPB4V0
VCC33PMP
VCC15A
AG0
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
IO47NDB2V0
IO47PDB2V0
GCA1/IO45PDB2V0
GCA0/IO45NDB2V0
GCB0/IO44NDB2V0
GCB1/IO44PDB2V0
GFA0/IO70NDB4V0
GFA1/IO70PDB4V0
GFB0/IO71NDB4V0
GFB1/IO71PDB4V0
GFC0/IO72NDB4V0
GFC1/IO72PDB4V0
GND
N3
GDB1/IO53PPB2V0
GEC1/IO63PDB4V0
GEC0/IO63NDB4V0
GEB1/IO62PDB4V0
GEB0/IO62NDB4V0
IO60NDB4V0
GEC2/IO60PDB4V0
GNDA
N4
N5
L2
N6
L3
N7
AC3
L4
N8
AG5
L5
N9
AV5
J2
L6
N10
N11
N12
N13
N14
N15
N16
P1
AG6
J3
L7
AC8
J4
L8
AC2
GNDA
VCC33A
VCCNVM
TCK
J5
L9
AV4
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
AC5
J7
PTEM
J8
VCC
TDO
TDI
J9
GND
VJTAG
VCCNVM
GNDNVM
GNDA
AC0
J10
J11
J12
J13
J14
J15
J16
VCC
IO57NPB2V0
GDB2/IO56PPB2V0
IO55NPB2V0
GND
P2
IO56NPB2V0
GDB0/IO53NPB2V0
GDA1/IO54PDB2V0
GDC1/IO52PPB2V0
IO51NSB2V0
GDC0/IO52NPB2V0
P3
P4
P5
AG1
GEA1/IO61PDB4V0
GEA0/IO61NDB4V0
VCCIB4
P6
AV1
P7
AG2
P8
AG4
Advanced v0.7
4-21
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
Pin Number
P9
AFS600 Function
GNDA
AC7
Pin Number
AFS600 Function
GNDA
T13
T14
T15
T16
P10
P11
P12
P13
P14
P15
P16
R1
VCC33ACAP
VAREF
AV8
AG8
GND
AV9
ADCGNDREF
PTBASE
GNDNVM
VCCIB4
PCAP
AT1
R2
R3
R4
AT0
R5
AV2
R6
AT2
R7
AV3
R8
AT5
R9
AV6
R10
R11
R12
R13
R14
R15
R16
T1
AT7
AV7
AT9
AG9
AC9
PUB
VCCIB2
GND
T2
NCAP
VCC33N
ATRTN0
AT3
T3
T4
T5
T6
ATRTN1
AT4
T7
T8
ATRTN2
AT6
T9
T10
T11
T12
ATRTN3
AT8
ATRTN4
4-22
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number
AFS1500 Function
GND
Pin Number
AFS1500 Function
VCCIB0
Pin Number
E9
AFS1500 Function
IO27NDB1V1
GND
A1
A2
C5
C6
VCCIB0
GAC1/IO03PDB0V0
IO09NDB0V1
IO23PDB1V0
IO23NDB1V0
IO31NDB1V1
IO31PDB1V1
VCCIB1
E10
E11
E12
E13
E14
E15
E16
F1
A3
GAA0/IO01NDB0V0
GAA1/IO01PDB0V0
GND
C7
GBB1/IO41PDB1V2
IO48PSB2V0
A4
C8
A5
C9
VCCIB2
A6
IO07PDB0V1
IO13PDB0V2
IO13NDB0V2
IO24NDB1V0
IO24PDB1V0
IO29NDB1V1
GND
C10
C11
C12
C13
C14
C15
C16
D1
IO46NDB2V0
GBC2/IO46PDB2V0
GND
A7
A8
A9
GBC1/IO40PPB1V2
VMV2
IO111NDB4V0
IO111PDB4V0
IO112NDB4V0
IO112PDB4V0
IO120PSB4V0
GAC2/IO123PPB4V0
IO05PPB0V1
IO11NDB0V1
IO27PDB1V1
IO37NDB1V2
IO50NDB2V0
IO50PDB2V0
IO59NDB2V0
GCA2/IO59PDB2V0
GCB2/IO60PDB2V0
IO60NDB2V0
IO109NPB4V0
VCCIB4
A10
A11
A12
A13
A14
A15
A16
B1
F2
GND
F3
VCCIB2
F4
GBA0/IO42NDB1V2
IO43NDB1V2
VCCIB1
IO124NDB4V0
GAB2/IO124PDB4V0
IO125NDB4V0
GAA2/IO125PDB4V0
GAB0/IO02NPB0V0
GAC0/IO03NDB0V0
IO09PDB0V1
IO15NDB0V2
IO15PDB0V2
IO37PDB1V2
GBB0/IO41NDB1V2
VMV1
F5
D2
F6
D3
F7
GND
D4
F8
VCOMPLA
D5
F9
B2
VCCPLA
D6
F10
F11
F12
F13
F14
F15
F16
G1
B3
IO00NDB0V0
IO00PDB0V0
GAB1/IO02PPB0V0
IO07NDB0V1
VCCIB0
D7
B4
D8
B5
D9
B6
D10
D11
D12
D13
D14
D15
D16
E1
B7
B8
IO22NDB1V0
IO22PDB1V0
VCCIB1
B9
GBA2/IO44PDB2V0
IO44NDB2V0
GBB2/IO45PDB2V0
IO45NDB2V0
GND
B10
B11
B12
B13
B14
B15
B16
C1
G2
IO29PDB1V1
GBC0/IO40NPB1V2
GBA1/IO42PDB1V2
IO43PDB1V2
VCCPLB
G3
GFB2/IO109PPB4V0
GFA2/IO110PDB4V0
GND
G4
G5
E2
IO118NDB4V0
IO118PDB4V0
VCCIB4
G6
IO110NDB4V0
GND
E3
G7
VCOMPLB
E4
G8
VCC
VCCIB4
E5
IO123NPB4V0
IO05NPB0V1
GND
G9
GND
C2
GND
E6
G10
G11
G12
VCC
C3
VMV4
E7
GCC0/IO62NDB2V0
GND
C4
VMV0
E8
IO11PDB0V1
Advanced v0.7
4-23
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
256-Pin FBGA
Pin Number
G13
G14
G15
G16
H1
AFS1500 Function
GCC1/IO62PDB2V0
IO61NPB2V0
VCCIB2
Pin Number
AFS1500 Function
Pin Number
AFS1500 Function
IO85NPB4V0
AV0
K1
K2
IO92NPB4V0
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
VCCIB4
K3
IO92PPB4V0
IO96PDB4V0
GND
AC1
GCC2/IO61PPB2V0
GFC2/IO108PDB4V0
IO108NDB4V0
XTAL2
K4
AG3
K5
AC4
H2
K6
IO96NDB4V0
VCC
AC6
H3
K7
AG7
H4
XTAL1
K8
GND
VPUMP
H5
GNDOSC
K9
VCC
VCCIB2
TMS
H6
VCCOSC
K10
K11
K12
K13
K14
K15
K16
L1
GND
H7
VCC
GDC2/IO84PPB2V0
GND
TRST
H8
GND
GND
H9
VCC
GDA0/IO81NDB2V0
GDA2/IO82PPB2V0
VCCIB2
GEB2/IO86PDB4V0
IO86NDB4V0
GEA2/IO85PPB4V0
VCC33PMP
VCC15A
AG0
H10
H11
H12
H13
H14
H15
H16
J1
GND
N2
IO69NDB2V0
IO69PDB2V0
GCA1/IO64PDB2V0
GCA0/IO64NDB2V0
GCB0/IO63NDB2V0
GCB1/IO63PDB2V0
GFA0/IO105NDB4V0
GFA1/IO105PDB4V0
GFB0/IO106NDB4V0
GFB1/IO106PDB4V0
GFC0/IO107NDB4V0
GFC1/IO107PDB4V0
GND
N3
GDB1/IO80PPB2V0
GEC1/IO90PDB4V0
GEC0/IO90NDB4V0
GEB1/IO89PDB4V0
GEB0/IO89NDB4V0
IO87NDB4V0
GEC2/IO87PDB4V0
GNDA
N4
N5
L2
N6
L3
N7
AC3
L4
N8
AG5
L5
N9
AV5
J2
L6
N10
N11
N12
N13
N14
N14
N15
N16
P1
AG6
J3
L7
AC8
J4
L8
AC2
GNDA
J5
L9
AV4
VCC33A
VCCNVM
VCCNVM
TCK
J6
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
AC5
J7
PTEM
J8
VCC
TDO
J9
GND
VJTAG
TDI
J10
J11
J12
J13
J14
J15
J16
VCC
IO84NPB2V0
GDB2/IO83PPB2V0
IO82NPB2V0
GND
VCCNVM
VCCNVM
GNDNVM
GNDNVM
GNDA
IO83NPB2V0
GDB0/IO80NPB2V0
GDA1/IO81PDB2V0
GDC1/IO79PPB2V0
IO77NSB2V0
GDC0/IO79NPB2V0
P1
P2
P2
GEA1/IO88PDB4V0
GEA0/IO88NDB4V0
VCCIB4
P3
P4
AC0
P5
AG1
4-24
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
256-Pin FBGA
256-Pin FBGA
Pin Number
AFS1500 Function
AV1
Pin Number
AFS1500 Function
AT6
P6
P7
T9
AG2
T10
T11
T12
T13
T14
T15
T16
ATRTN3
AT8
P8
AG4
P9
GNDA
AC7
ATRTN4
GNDA
P10
P11
P12
P13
P14
P15
P16
P16
R1
AV8
VCC33ACAP
VAREF
AG8
AV9
GND
ADCGNDREF
PTBASE
GNDNVM
GNDNVM
VCCIB4
PCAP
AT1
R2
R3
R4
AT0
R5
AV2
R6
AT2
R7
AV3
R8
AT5
R9
AV6
R10
R11
R12
R13
R14
R15
R16
T1
AT7
AV7
AT9
AG9
AC9
PUB
VCCIB2
GND
T2
NCAP
VCC33N
ATRTN0
AT3
T3
T4
T5
T6
ATRTN1
AT4
T7
T8
ATRTN2
Advanced v0.7
4-25
Fusion Family of Mixed-Signal Flash FPGAs
484-Pin FBGA
A1 Ball Pad Corner
22 21201918 171615 1413 121110 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
Figure 4-5 • 484-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
4-26
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number
AFS600 Function
GND
Pin Number
AFS600 Function
Pin Number
B7
AFS600 Function
GND
A1
A2
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
AG8
GNDA
AG9
VCC
B8
IO10NDB0V1
IO13PDB0V1
GND
A3
GAA1/IO01PDB0V0
GAB0/IO02NDB0V0
GAB1/IO02PDB0V0
IO07NDB0V1
IO07PDB0V1
IO10PDB0V1
IO14NDB0V1
IO14PDB0V1
IO17PDB1V0
IO18PDB1V0
IO19NDB1V0
IO19PDB1V0
IO24NDB1V1
IO24PDB1V1
GBC0/IO26NDB1V1
GBA0/IO28NDB1V1
IO29NDB1V1
IO29PDB1V1
VCC
B9
A4
VAREF
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
A5
VCCIB2
IO17NDB1V0
IO18NDB1V0
GND
A6
PTEM
GND
A7
A8
VCC
IO21NDB1V0
IO21PDB1V0
GND
A9
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AB2
VCC
AB3
NC
GBC1/IO26PDB1V1
GBA1/IO28PDB1V1
GND
AB4
GND
AB5
VCC33N
AT0
AB6
VCCPLB
AB7
ATRTN0
AT1
GND
AB8
VCC
AB9
AT2
IO82PDB4V0
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
B1
ATRTN1
AT3
C2
C3
IO00NDB0V0
IO00PDB0V0
VCCIB0
AT6
C4
ATRTN3
AT7
C5
GND
C6
IO06NDB0V0
IO06PDB0V0
VCCIB0
VCC
AT8
C7
GND
ATRTN4
AT9
C8
VMV4
C9
IO13NDB0V1
IO11PDB0V1
VCCIB0
V
CCIB4
VCC33ACAP
GND
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
PCAP
AG0
NC
VCCIB1
GNDA
AG1
VCC
IO20NDB1V0
IO20PDB1V0
VCCIB1
GND
AG2
VCC
GNDA
AG3
B2
GND
IO25NDB1V1
GBB0/IO27NDB1V1
VCCIB1
B3
GAA0/IO01NDB0V0
GND
AG6
B4
GNDA
AG7
B5
IO05NDB0V0
IO05PDB0V0
VCOMPLB
B6
GBA2/IO30PDB2V0
Advanced v0.7
4-27
Fusion Family of Mixed-Signal Flash FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number
C21
C22
D1
AFS600 Function
NC
Pin Number
AFS600 Function
Pin Number
AFS600 Function
VCCIB4
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
GND
NC
G5
G6
GBB2/IO31PDB2V0
IO82NDB4V0
GND
NC
NC
G7
VMV4
D2
VCCIB1
G8
GND
D3
IO83NDB4V0
GAC2/IO83PDB4V0
GAA2/IO85PDB4V0
GAC0/IO03NDB0V0
GAC1/IO03PDB0V0
IO09NDB0V1
IO09PDB0V1
IO11NDB0V1
IO16NDB1V0
IO16PDB1V0
NC
GND
NC
G9
IO04NDB0V0
IO04PDB0V0
IO12NDB0V1
IO12PDB0V1
NC
D4
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
D5
IO33PDB2V0
VCCIB2
D6
D7
IO32NDB2V0
GBC2/IO32PDB2V0
IO80NDB4V0
IO80PDB4V0
NC
D8
NC
D9
GND
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
F2
NC
F3
NC
F4
IO84NDB4V0
GND
VCCIB2
F5
IO36PDB2V0
IO36NDB2V0
GND
IO23NDB1V1
IO23PDB1V1
IO25PDB1V1
GBB1/IO27PDB1V1
VMV2
F6
VCOMPLA
F7
VCCPLA
F8
VMV0
IO35NDB2V0
IO77NDB4V0
IO76PDB4V0
VCCIB4
F9
IO08NDB0V1
IO08PDB0V1
VCCIB0
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
G2
G3
G4
H2
NC
H3
IO30NDB2V0
GND
VCCIB1
H4
IO79NDB4V0
IO79PDB4V0
NC
IO22NDB1V0
IO22PDB1V0
VMV1
H5
IO31NDB2V0
IO81NDB4V0
IO81PDB4V0
VCCIB4
H6
H7
GND
E2
NC
H8
VCC
E3
NC
H9
VCCIB0
E4
GAB2/IO84PDB4V0
IO85NDB4V0
GND
GND
H10
H11
H12
H13
H14
H15
H16
H17
H18
GND
E5
IO33NDB2V0
IO34PDB2V0
IO34NDB2V0
IO35PDB2V0
IO77PDB4V0
GND
VCCIB0
E6
VCCIB1
GND
E7
VCCIB0
E8
NC
VCCIB1
E9
NC
GND
GND
E10
E11
E12
GND
IO15NDB1V0
IO15PDB1V0
IO78NDB4V0
IO78PDB4V0
NC
IO38PDB2V0
4-28
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number
AFS600 Function
Pin Number
AFS600 Function
VCC
Pin Number
M3
AFS600 Function
VCCIB4
H19
H20
H21
H22
J1
GCA2/IO39PDB2V0
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
V
CCIB2
GND
M4
GNDOSC
IO37NDB2V0
VCC
M5
GFC0/IO72NDB4V0
IO37PDB2V0
GND
M6
VCCIB4
NC
GND
M7
GFB0/IO71NDB4V0
J2
IO76NDB4V0
IO40NDB2V0
NC
M8
VCCIB4
VCC
J3
GFB2/IO74PDB4V0
M9
J4
GFA2/IO75PDB4V0
GND
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
VCC
J5
NC
NC
J6
NC
IO41NDB2V0
GND
GND
VCC
J7
NC
J8
VCCIB4
IO42NDB2V0
IO73NDB4V0
VCCOSC
VCCIB4
GND
J9
GND
VCCIB2
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
VCC
L2
IO48NDB2V0
GND
L3
VCCIB2
VCC
GND
L4
XTAL2
IO46NDB2V0
L5
GFC1/IO72PDB4V0
VCCIB4
GCA0/IO45NDB2V0
VCC
L6
VCCIB2
VCCIB2
L7
GFB1/IO71PDB4V0
VCCIB4
GCB0/IO44NDB2V0
GCB2/IO40PDB2V0
NC
L8
GCB1/IO44PDB2V0
L9
GND
NC
IO38NDB2V0
IO39NDB2V0
GCC2/IO41PDB2V0
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
VCC
N2
GND
GND
N3
IO68PDB4V0
VCC
N4
NC
GND
N5
GND
IO42PDB2V0
GFC2/IO73PDB4V0
GND
VCC
N6
NC
VCCIB2
N7
NC
IO48PDB2V0
N8
GND
IO74NDB4V0
IO75NDB4V0
GND
VCCIB2
N9
GND
IO46PDB2V0
GCA1/IO45PDB2V0
VCCIB2
N10
N11
N12
N13
N14
N15
N16
VCC
GND
NC
VCC
NC
GCC0/IO43NDB2V0
GCC1/IO43PDB2V0
NC
GND
VCC
GND
VCC
GND
GND
XTAL1
GDB2/IO56PDB2V0
Advanced v0.7
4-29
Fusion Family of Mixed-Signal Flash FPGAs
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number
N17
N18
N19
N20
N21
N22
P1
AFS600 Function
NC
Pin Number
AFS600 Function
Pin Number
AFS600 Function
IO67PDB4V0
IO67NDB4V0
GEC1/IO63PDB4V0
GEC0/IO63NDB4V0
GND
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCC33A
U1
U2
GND
GNDA
IO47NDB2V0
IO47PDB2V0
GND
VCC33A
U3
GNDA
U4
VCC33A
U5
IO49PDB2V0
GFA1/IO70PDB4V0
GFA0/IO70NDB4V0
IO68NDB4V0
IO65PDB4V0
IO65NDB4V0
NC
GNDA
U6
VCCNVM
VCC
U7
VCCIB4
P2
GND
U8
VCC15A
P3
NC
U9
GNDA
P4
GDA0/IO54NDB2V0
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
AC4
P5
GDB0/IO53NDB2V0
VCC33A
P6
VCCIB2
GNDA
P7
NC
IO50NDB2V0
AG5
P8
VCCIB4
IO50PDB2V0
GNDA
P9
VCC
NC
PUB
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
GND
T2
GND
VCCIB2
VCC
T3
IO66PDB4V0
TDI
GND
T4
IO66NDB4V0
GND
VCC
T5
VCCIB4
IO57NDB2V0
GDC2/IO57PDB2V0
NC
GND
T6
NC
VCCIB2
T7
GNDNVM
IO56NDB2V0
NC
T8
GNDA
GDC0/IO52NDB2V0
GEB1/IO62PDB4V0
GEB0/IO62NDB4V0
VCCIB4
T9
NC
GDA1/IO54PDB2V0
GDB1/IO53PDB2V0
IO51NDB2V0
IO51PDB2V0
IO49NDB2V0
IO69PDB4V0
IO69NDB4V0
VCCIB4
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
AV4
V2
NC
V3
AV5
V4
GEA1/IO61PDB4V0
GEA0/IO61NDB4V0
GND
AC5
V5
NC
GNDA
V6
V7
VCC33PMP
NC
R2
NC
V8
R3
NC
V9
VCC33A
R4
IO64PDB4V0
IO64NDB4V0
NC
VCCIB2
V10
V11
V12
V13
V14
AG4
R5
IO55NDB2V0
GDA2/IO55PDB2V0
GND
AT4
R6
ATRTN2
R7
GND
AT5
R8
GND
GDC1/IO52PDB2V0
VCC33A
4-30
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
484-Pin FBGA
484-Pin FBGA
Pin Number
AFS600 Function
Pin Number
AFS600 Function
VCC33A
AC1
V15
V16
V17
V18
V19
V20
V21
V22
W1
NC
Y7
VCC33A
Y8
GND
Y9
AC2
TMS
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
VCC33A
AC3
VJTAG
VCCIB2
AC6
TRST
VCC33A
AC7
TDO
NC
AC8
W2
GND
VCC33A
AC9
W3
NC
W4
GEB2/IO59PDB4V0
ADCGNDREF
PTBASE
GNDNVM
VCCNVM
VPUMP
W5
IO59NDB4V0
W6
AV0
W7
GNDA
W8
AV1
W9
AV2
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
GNDA
AV3
AV6
GNDA
AV7
AV8
GNDA
AV9
VMV2
NC
TCK
GND
NC
GEC2/IO60PDB4V0
IO60NDB4V0
GEA2/IO58PDB4V0
IO58NDB4V0
NCAP
Y2
Y3
Y4
Y5
Y6
AC0
Advanced v0.7
4-31
Fusion Family of Mixed-Signal Flash FPGAs
676-Pin FBGA
A1 Ball Pad Corner
2625 2423 2221 201918 171615 1413 121110 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Figure 4-6 • 676-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
4-32
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (Advanced v0.7)
Page
Advanced v0.6
(October 2006)
The AFS1500-FG484 and AFS1500-FG676 user I/O counts were updated in the "Package I/Os:
Single/Double-Ended (Analog)" table.
ii
Advanced v0.5
(June 2006)
The second paragraph of the "PLL Macro" section was updated to include information about
POWERDOWN.
2-27
The description for bit 0 was updated in Table 2-16 • RTC Control/Status Register.
3.9 was changed to 7.8 in the "Crystal Oscillator (Xtal Osc)" section.
All function descriptions in Table 2-17 • Signals for VRPSM Macro.
In Table 2-18 • Flash Memory Block Pin Names, the RD[31:0] description was updated.
The "RESET" section was updated.
2-34
2-35.
2-36
2-38
2-53
2-55
2-65
2-67
2-71
The "RESET" section was updated.
Table 2-33 • FIFO was updated.
The VAREF function description was updated in Table 2-34 • Analog Block Pin Description.
The "Voltage Monitor" section was updated to include information about low power mode and
sleep mode.
The text in the "Current Monitor" section was changed from 2 mV to 1 mV.
2-74
2-76
2-80
The "Gate Driver" section was updated to include information about forcing 1 V on the drain.
The "Analog to Digital Converter Block" section was updated with the following statement:
"All results are MSB justified in the ADC."
The information about the ADCSTART signal was updated in the "ADC Description" section.
Table 2-40 • Electrical Specifications was updated.
2-83
2-86
2-88
2-89
2-92
Table 2-41 • ADC Characteristics in Direct Input Mode was updated.
Table 2-42 • ACM Address Decode Table for Analog Quad was updated.
In Table 2-44 • Analog Quad ACM Byte Assignment, the Function and Default Setting for Bit 6 in
Byte 3 was updated.
The "Introduction" section was updated to include information about digital inputs, outputs, and
bibufs.
2-95
2-99
In Table 2-59 • Fusion Pro I/O Features, the programmable delay descriptions were updated for the
following features:
•
•
•
Single-ended receiver
Voltage-referenced differential receiver
LVDS/LVPECL differential receiver features
The "User I/O Naming Convention" section was updated to include "V" and "z" descriptions
2-120
Advanced v0.7
5-1
Fusion Family of Mixed-Signal Flash FPGAs
Previous Version Changes in Current Version (Advanced v0.7)
Page
Advanced v0.5
(June 2006)
The "VCC33PMP Analog Power Supply (3.3 V)" section was updated to include information about
avoiding high current draw.
2-168
The "VCCNVM Flash Memory Block Power Supply (1.5 V)" section was updated to include
information about avoiding high current draw.
2-168
2-168
2-170
2-170
2-170
The "VMVx I/O Supply Voltage (quiet)" section was updated to include this statement: VMV and
VCCI must be connected to the same power supply and VCCI pins within a given I/O bank.
The "PUB Power Up Bar" section was updated to include information about leaving the pin floating
if it is not used.
The "PTBASE Pass Transistor Base" section was updated to include information about leaving the
pin floating if it is not used.
The "PTEM Pass Transistor Emitter" section was updated to include information about leaving the
pin floating if it is not used.
Table 3-3 • Required Conditions to Avoid Stress on Analog Input Pads is new.
The heading was incorrect in the "208-Pin PQFP" table. It should be AFS250 and not AFS090.
The low power modes of operation were updated and clarified.
3-2
4-9
N/A
i
Advanced v0.4
(April 2006)
The AFS1500 digital I/O count was updated in Table 1 • Fusion Family.
The AFS1500 digital I/O count was updated in the "Package I/Os: Single/Double-Ended (Analog)"
table.
ii
The "Voltage Regulator Power Supply Monitor (VRPSM)" section was updated.
Figure 2-45 • FlashROM Timing Diagram was updated.
2-36
2-50
4-23
iii
The "256-Pin FBGA" table for the AFS1500 is new.
Advanced v0.3
(April 2006)
The G was moved in the "Product Ordering Codes" section.
Advanced v0.2
(April 2006)
The "Features and Benefits" section was updated.
i
Table 1 • Fusion Family table was updated.
i
"Package I/Os: Single/Double-Ended (Analog)" section was updated.
"Product Ordering Codes" section was updated.
ii
iii
"Temperature Grade Offerings" section was updated.
The "General Description" section was updated to include ARM information.
The "FlashROM" section was updated.
iv
1-1
2-50
2-53
2-55
2-31
2-38
2-39
2-40
2-42
"RESET" section was updated.
"RESET" section was updated.
Figure 2-27 • Real-Time Counter System was updated.
Table 2-18 • Flash Memory Block Pin Names was updated.
Figure 2-32 • Flash Memory Block Diagram was updated to include AUX block information.
Figure 2-33 • Flash Memory Block Organization was updated to include AUX block information.
The note in the "Program Operation" section was updated.
5-2
Advanced v0.7
Fusion Family of Mixed-Signal Flash FPGAs
Previous Version Changes in Current Version (Advanced v0.7)
Page
2-77
2-92
Advanced v0.2
(continued)
Figure 2-69 • Gate Driver Example was updated.
The "Analog Quad ACM Description" section was updated.
Information about the maximum pad input frequency was added to the "Gate Driver" section.
Figure 2-61 • Analog Block Macro was updated.
Figure 2-61 • Analog Block Macro was updated.
The "Analog Quad" section was updated.
2-76
2-76
2-66
2-69
2-71
2-73
2-74
2-76
2-78
2-83
2-83
2-18
2-86
2-105
The "Voltage Monitor" section was updated.
The "Direct Digital Input" section was updated.
The "Current Monitor" section was updated.
Information about the maximum pad input frequency was added to the "Gate Driver" section.
The "Temperature Monitor" section was updated.
EQ 2-6 is new.
The "ADC Description" section was updated.
Figure 2-16 • Fusion Clocking Options was updated.
Table 2-40 • Electrical Specifications was updated.
The notes in Table 2-62 • Fusion Standard, LVDS, and Standard Plus Hot-Swap I/O Hot-Swap and 5
V Input Tolerance Capabilities were updated.
The "Simultaneous Switching Outputs and Printed Circuit Board Layout" section is new.
2-111
2-118
LVPECL and LVDS were updated in Table 2-70 • Fusion Standard and LVDS I/O Attributes vs. I/O
Standard Applications.
LVPECL and LVDS were updated in Table 2-71 • Fusion Pro I/O Attributes vs. I/O Standard
Applications.
2-118
The "Timing Model" section was updated.
2-122
N/A
All voltage-referenced Minimum and Maximum DC Input and Output Level tables were updated.
All Timing Characteristic tables were updated
N/A
Table 2-73 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to
Commercial and Industrial Conditions was updated.
2-126
Table 2-77 • Summary of I/O Timing Characteristics – Software Default Settings was updated.
Table 2-79 • I/O Output Buffer Maximum Resistances1 was updated.
2-129
2-130
2-155
The "BLVDS/M-LVDS" section is new. BLVDS and M-LVDS are two new I/O standards included in the
datasheet.
The "CoreMP7 Software Tools" section is new.
2-171
3-7
Table 3-8 • Quiescent Supply Current Characteristics (IDDQ)1 was updated.
Table 3-11 • Different Components Contributing to the Dynamic Power Consumption in Fusion
Devices was updated.
3-10
Table 3-12 • Different Components Contributing to the Static Power Consumption in Fusion
Devices was updated.
3-11
Advanced v0.7
5-3
Fusion Family of Mixed-Signal Flash FPGAs
Previous Version Changes in Current Version (Advanced v0.7)
Page
3-17
3-21
4-2
Advanced v0.2
(continued)
The "Example of Power Calculation" section was updated.
The Analog System information was deleted from Table 3-15 • Power Consumption.
The "108-Pin QFN" table for the AFS090 device is new.
The "180-Pin QFN" table for the AFS090 device is new.
The "208-Pin PQFP" table for the AFS090 device is new.
The "256-Pin FBGA" table for the AFS090 device is new.
The "256-Pin FBGA" table for the AFS090 device is new.
4-6
4-9
4-14
4-17
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Datasheet
Supplement.” The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
Export Administration Regulations (EAR)
The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could
require an approved export license prior to export from the United States. An export includes release of product or
disclosure of technology to a foreign national inside or outside the United States.
5-4
Advanced v0.7
Actel and the Actel logo are registered trademarks of Actel Corporation.
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