RTAX1000-SLB624E [ACTEL]

RTAX-S/SL RadTolerant FPGAs; RTAX -S / SL FPGA的RadTolerant


型号：	RTAX1000-SLB624E
厂家：	Actel Corporation
描述：	RTAX-S/SL RadTolerant FPGAs RTAX -S / SL FPGA的RadTolerant
文件：	总170页 (文件大小：2256K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

v5.3

RTAX-S/SL RadTolerant FPGAs

Radiation Performance

Leading-Edge Performance

•

SEU-Hardened Registers Eliminate the Need for Triple-

Module Redundancy (TMR)

•

High-Performance Embedded FIFOs

350+ MHz System Performance

500+ MHz Internal Performance

700 Mb/s LVDS Capable I/Os

–

Immune to Single-Event Upsets (SEU) to LET

> 37

MeV-cm /mg

-10

–

SEU Rate

Errors/Bit-Day in Worst-Case

Geosynchronous Orbit

Specifications

-10

•

Expected SRAM Upset Rate of <10

Errors/Bit-Day with

Use of Error Detection and Correction (EDAC) IP (included)

with Integrated SRAM Scrubber

•

Up to 4 Million Equivalent System Gates or 500 k

Equivalent ASIC Gates

–

Single-Bit Correction, Double-Bit Detection

Variable-Rate Background Refreshing

•

Up to 20,160 SEU-Hardened Flip-Flops

Up to 840 I/Os

•

Total Ionizing Dose Up to 300 krad (Si, Functional)

Up to 540 kbits Embedded SRAM

Single-Event Latch-Up Immunity (SEL) to LET > 117 MeV-

Manufactured on Advanced 0.15 μm CMOS Antifuse

Process Technology, 7 Layers of Metal

Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883,

TM3015)

cm /mg

•

TM1019 Test Data Available

Single Event Transient (SET) – No Anomalies up to 150 MHz

•

Processing Flows

Features

•

B-Flow – MIL-STD-883B

•

Single-Chip, Nonvolatile Solution

1.5 V Core Voltage for Low Power

Flexible, Multi-Standard I/Os:

E-Flow – Actel Extended Flow

EV-Flow – Class V Equivalent Flow Processing Consistent

with MIL-PRF 38535

–

1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation

Bank-Selectable I/Os – 8 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI

JTAG Boundary Scan Testing (as per IEEE 1149.1)

Differential I/O Standards: LVPECL and LVDS

Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,

SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

Prototyping Options

•

Commercial

Verification

Axcelerator

Devices

for

Functional

•

RTAX-S PROTO Devices with Same Functional and Timing

Characteristics as Flight Unit in a Non-Hermetic Package

–

Hot-Swap Compliant with Cold-Sparing Support

(Except PCI)

•

Embedded Memory with Variable Aspect Ratio and

Organizations:

RTAX-SL Low Power Option

–

Independent, Width-Configurable Read and Write Ports

Programmable Embedded FIFO Control Logic

ROM Emulation Capability

•

Offers Approximately Half the Standby Current of the

Standard RTAX-S Device at Worst-Case Conditions

•

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Debug Capability

Table 1 • RTAX-S/SL Family Product Profile

Device

RTAX250S/SL

RTAX1000S/SL

RTAX2000S/SL

RTAX4000S

Capacity

Equivalent System Gates

ASIC Gates

250,000

30,000

1,000,000

125,000

2,000,000

250,000

4,000,000

500,000

Modules

Combinatorial (C-cells)

Flip-Flops (maximum)

1,408

2,816

6,048

12,096

10,752

21,504

20,160

40,320

Embedded RAM/FIFO (without EDAC)

Core RAM Blocks

Core RAM Bits (K = 1,024)

54 k

162 k

288 k

120

540 k

Clocks (segmentable)

Hardwired

Routed

I/Os

I/O Banks

User I/Os (maximum)

I/O Registers

198

744

418

1,548

684

2,052

840

2,520

Package

CCGA/LGA

CQFP

–

624

352

624, 1152

256, 352

1272

352

208, 352

October 2008

See the Actel website for the latest version of the datasheet.

All RTAX4000S information is preliminary.

RTAX-S/SL RadTolerant FPGAs

Ordering Information

RTAX2000S/SL

CGS

624

Application

= MIL-STD 883 Class B

= E-Flow (Actel Space-Level Flow)

EV = Class V Equivalent Flow Processing Consistent with MIL-PRF 38535

Package Lead Count

Package Type

Ceramic Quad Flat Pack

Ceramic Column Grid Array

Land Grid Array

Six Sigma Column

BAE Column

Speed Grade

Blank Standard Speed

Approximately 15% Faster than Standard

Part Number

S = Standard Family

SL = Low-Power Option

RTAX250S/SL = 250,000 Equivalent System Gates

RTAX1000S/SL = 1,000,000 Equivalent System Gates

RTAX2000S/SL = 2,000,000 Equivalent System Gates

RTAX4000S = 4,000,000 Equivalent System Gates

Note: PROTO refers to the RTAX-S/SL Prototype Units. All CCGA PROTO units will be offered with the Six Sigma Column.

Temperature Grade Offerings

Package

RTAX250S/SL

RTAX1000S/SL

RTAX2000S/SL

RTAX4000S

CQ208

B, E, EV

–

CQ256

–

B, E, EV

–

CQ352

B, E, EV

CG624*/LG624

CG1152/LG1152

CG1272/LG1272

–

B, E, EV

–

B, E, EV

Note: *Indicates that the CG624 package will be offered as CGS624 for the Six Sigma column and CGB624 for the BAE column. The

other CCGA offerings (1152 and 1272) will be offered as Six Sigma columns.

B = MIL-STD-883 Class B

E = E-Flow (Actel Space-Level Flow)

EV = Actel "V" Equivalent Flow (Class V processing consistent with MIL-PRF 38535)

v5.3

RTAX-S/SL RadTolerant FPGAs

Speed Grade and Temperature Grade Matrix

Std

–1

✓

Contact your local Actel representative for device availability.

Device Resources

User I/Os (Including Clock Buffers)

Device

RTAX250S/SL

RTAX1000S/SL

RTAX2000S/SL

RTAX4000S

CQ208

115

–

CQ256

138

198

418

684

–

CQ352

198

–

198

418

–

166

–

CG624/LG624

CG1152/LG1152

CG1272/LG1272

–

840

Note: CQFP = Ceramic Quad Flat Pack and CCGA = Ceramic Column Grid Array, LGA = Land Grid Array

v5.3

iii

RTAX-S/SL RadTolerant FPGAs

Actel MIL-STD-883 Class B Product Flow

Table 2 • Actel MIL-STD-883 Class B Product Flow for RTAX-S/SL^{1, 2}

Step

Screen

Method

Requirement

100%

Internal Visual

2010, Condition B

Serialization

100%

Temperature Cycling

Constant Acceleration

1010, Condition C, 10 cycles minimum

100%

2001, Y1 Orientation Only

Condition B for CQ352, LG624, LG1152

Condition D for CQ208

100%

TBD for LG1272

Particle Impact Noise Detection

Seal (Fine & Gross Leak Test)

Pre-Burn-In Electrical Parameters

2020, Condition A

1014

100%

In accordance with applicable Actel device

specification

Dynamic Burn-In

1015, Condition D,

160 hours at 125°C or 80 hours at 150°C minimum

100%

Interim (Post-Burn-In) Electrical Parameters

In accordance with applicable Actel device

specification

Percent Defective Allowable (PDA) Calculation

Final Electrical Test²

All Lots

100%

In accordance with applicable Actel device

specification, which includes a, b, and c:

a. Static Tests

(1) 25°C

(2) –55°C and +125°C

5005, Table 1, Subgroup 1

5005, Table 1, Subgroup 2, 3

b. Functional Tests

(1) 25°C

(2) –55°C and +125°C

5005, Table 1, Subgroup 7

5005, Table 1, Subgroup 8a, 8b

5005, Table 1, Subgroup 9

2009

c. Switching Tests at 25°C

External Visual

100%

Notes:

1. For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical visual are

performed after solder column attachment.

2. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the I_CCAcurrent limits at 125°C final electrical

test.

v5.3

RTAX-S/SL RadTolerant FPGAs

Actel Extended Flow

Table 3 • Actel Extended Flow for RTAX-S/SL ^{1, 2, 3, 4}

Step

Screen

Destructive Bond Pull⁵

Method

Requirement

Extended Sample

100%

2011, Condition D

2010, Condition A

Internal Visual

Serialization

100%

Temperature Cycling

Constant Acceleration

1010, Condition C, 10 cycles minimum

100%

2001, Y1 Orientation Only

Condition B for CQ352, LG624, LG1152

Condition D for CQ208

TBD for LG1272

Particle Impact Noise Detection

Radiographic (X-Ray)

2020, Condition A

100%

2012, One View (Y1 Orientation) Only

Pre-Burn-In Electrical Parameters

In accordance with applicable Actel device

specification

Dynamic Burn-In

1015, Condition D,

100%

240 hours at 125°C or 120 hours at 150°C

minimum

Interim

Parameters

(Post-Dynamic-Burn-In)

Electrical In accordance with applicable Actel device

specification

100%

Static Burn-In

1015, Condition C, 72 hours at 150°C or 144

hours at 125°C minimum

Interim (Post-Static-Burn-In) Electrical Parameters

In accordance with applicable Actel device

specification

Percent Defective Allowable (PDA) Calculation

Final Electrical Test⁴

5% Overall, 3% Functional Parameters at 25°C

All Lots

100%

In accordance with applicable Actel device

specification, which includes a, b, and c:

a. Static Tests

(1) 25°C

(2) –55°C and +125°C

5005, Table 1, Subgroup 1

5005, Table 1, Subgroup 2, 3

b. Functional Tests

(1) 25°C

(2) –55°C and +125°C

5005, Table 1, Subgroup 7

5005, Table 1, Subgroup 8a, 8b

5005, Table 1, Subgroup 9

c. Switching Tests at 25°C

Seal (Fine & Gross Leak Test)

1014

2009

100%

External Visual

Notes:

1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Actel is offering this

Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S.

2. The Quality Conformance Inspection (QCI) for Extended Flow devices still comply to MIL-STD-833, Class B requirement.

3. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are

performed after solder column attachment.

4. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the I_CCAcurrent limits at 125°C final electrical

test.

5. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method

2011 Condition D on an extended sample basis.

v5.3

RTAX-S/SL RadTolerant FPGAs

Actel "EV" Flow (Class V Flow Equivalent Processing)

Table 4 • Actel "EV" Flow (Class V Equivalent Flow Processing) for RTAX-S/SL^{1, 2, 3}

Step

Screen

Destructive Bond Pull⁴

Method

Requirement

Extended Sample

100%

2011, Condition D

2010, Condition A

Internal Visual

Serialization

100%

Temperature Cycling

Constant Acceleration

1010, Condition C, 50 cycles minimum

100%

2001, Y1 Orientation Only

Condition B for CQ352, LG624, LG1152

Condition D for CQ208

100%

TBD for LG1272

Particle Impact Noise Detection

Radiographic (X-Ray)

2020, Condition A

100%

2012, One View (Y1 Orientation) Only

Pre-Burn-In Electrical Parameters

In accordance with applicable Actel device

specification

Dynamic Burn-In

1015, Condition D,

100%

240 hours at 125°C or 120 hours at 150°C

minimum

Interim (Post-Dynamic-Burn-In) Electrical Parameters In accordance with applicable Actel device

specification

100%

Static Burn-In

1015, Condition C, 72 hours at 150°C or 144 hours

at 125°C minimum

Interim (Post-Static-Burn-In) Electrical Parameters

In accordance with applicable Actel device

specification

Percent Defective Allowable (PDA) Calculation

Final Electrical Test³

5% Overall, 3% Functional Parameters at 25°C

All Lots

100%

In accordance with applicable Actel device

specification, which includes a, b, and c:

a. Static Tests

(1) 25°C

(2) –55°C and +125°C

5005, Table 1, Subgroup 1

5005, Table 1, Subgroup 2, 3

b. Functional Tests

(1) 25°C

(2) –55°C and +125°C

5005, Table 1, Subgroup 7

5005, Table 1, Subgroup 8a, 8b

5005, Table 1, Subgroup 9

c. Switching Tests at 25°C

Seal (Fine & Gross Leak Test)

1014

100%

External Visual

2009

Wafer Lot Specific Life Test (Group C)

MIL-PRF-38535, Appendix B, sec. B.4.2.c

All Wafer Lots

Notes:

1. Actel offers "EV" flow for users requiring full compliance to MIL-PRF-38535 class V requirement.

The "EV" process flow is expanded from the existing E-flow requirement (it still meets the full SMD requirement for current E-flow

devices) with the intention to be in full compliance to MIL-PRF-38535 Table IA and Appendix B requirement, but without the official

class V certification from DSCC.

2. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual are

performed after solder column attachment.

3. RTAX-S and RTAX-SL devices have the same silicon and are distinguished by screening the I_CCAcurrent limits at 125°C final electrical

test.

4. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method

2011 Condition D on an extended sample basis.

v5.3

RTAX-S/SL RadTolerant FPGAs

Table of Contents

General Description

Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Low-Cost Prototyping Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Detailed Specifications

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44

Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84

Package Pin Assignments

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

1152-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38

1272-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

v5.3

vii

RTAX-S/SL RadTolerant FPGAs

General Description

RTAX-S/SL offers high performance at densities of up to

two million equivalent system gates for space-based

applications. Based upon the Actel commercial

Axcelerator^®family, RTAX-S/SL has several system-level

features such as embedded SRAM (with built-in FIFO

control logic), segmentable clocks, chip-wide highway

routing, and carry logic.

the entire floor of the RTAX-S/SL device is covered with a

grid of logic modules, with virtually no chip area lost to

interconnect elements or routing.

Programmable Interconnect

Element

The RTAX-S/SL family uses a patented metal-to-metal

antifuse programmable interconnect element that resides

between the upper two layers of metal (Figure 1-2 on

page 1-2). This completely eliminates the channels of

routing and interconnect resources between logic

modules (as implemented on traditional FPGAs) and

enables the efficient sea-of-modules architecture. The

antifuses are normally open circuit and, when

Featuring SEU-hardened flip-flops that offer the benefits

of user-implemented Triple Module Redundancy (TMR)

without the associated overhead, the RTAX-S/SL family is

the second generation Actel product offering for space

applications. The RTAX-S/SL devices are manufactured

using a 0.15 µm technology at a UMC facility in Taiwan.

These devices offer levels of radiation survivability far in

excess of typical CMOS devices.

programmed, form

permanent, passive, low-

impedance connection, leading to the fastest signal

propagation in the industry. In addition, the extremely

small size of these interconnect elements gives the

RTAX-S family abundant routing resources.

Device Architecture

Actel RTAX-S/SL architecture, derived from the highly-

successful A54SX-A sea-of-modules architecture, has

been designed for high performance and total logic

module utilization (Figure 1-1). Unlike traditional FPGAs,

Routing

Switch

Matrix

Logic Block

Sea-of-Modules

Architecture

Traditional FPGA

Architecture

Logic

Modules

Figure 1-1 • Sea-of-Modules Comparison

v5.3

1-1

RTAX-S/SL RadTolerant FPGAs

Figure 1-2 • RTAX-S/SL Family Interconnect Elements

The very nature of Actel's nonvolatile antifuse

technology provides excellent protection against design

pirating and cloning (FuseLock^®technology). Cloning is

impossible (even if the security fuse is left

unprogrammed) as no bitstream or programming file is

ever downloaded or stored in the device. Reverse

engineering is virtually impossible due to the difficulty of

trying to distinguish between programmed and

unprogrammed antifuses and also due to the

programming methodology of antifuse devices (see

"Security" on page 2-83).

taken in the layout to ensure that a single ion strike

could not affect more than one latch (see "R-Cell" on

page 2-48 for more details).

The R-cell contains a flip-flop featuring asynchronous

clear, asynchronous preset, and active-low enable control

signals (Figure 1-3 on page 1-3). The R-cell registers

feature programmable clock polarity selectable on a

flexibility (e.g., easy mapping of dual-data-rate functions

into the FPGA) while conserving valuable clock resources.

The clock source for the R-cell can be chosen from the

hardwired clocks, routed clocks, or internal logic.

Actel's RTAX-S/SL family provides two types of logic

modules: the register cell (R-cell) and the combinatorial

cell (C-cell). The RTAX-S/SL C-cell can implement more

than 4,000 combinatorial functions of up to five inputs

(Figure 1-3 on page 1-3). The C-cell contains carry logic

for even more efficient implementation of arithmetic

functions. With its small size, the C-cell structure is

extremely synthesis-friendly, simplifying the overall

design as well as reducing design time.

Two C-cells, a single R-cell, and two Transmit (TX) and two

Receive (RX) routing buffers form a Cluster, while two

Clusters comprise a SuperCluster (Figure 1-4 on page 1-3).

Each SuperCluster also contains an independent Buffer (B)

module, which supports buffer insertion on high-fanout

nets by the place-and-route tool, minimizing system

delays while improving logic utilization.

The logic modules within the SuperCluster are arranged

so that two combinatorial modules are side-by-side,

giving a C–C–R – C–C–R pattern to the SuperCluster. This

C–C–R pattern enables efficient implementation

(minimum delay) of two-bit carry logic for improved

arithmetic performance (Figure 1-5 on page 1-3).

While each SEU-hardened R-cell appears as a single

D-Type flip-flop to the user, each is implemented in

silicon using triple redundancy to achieve a LET threshold

of greater than 60 MeV-mg/cm². Each TMR R-cell consist

of three master-slave latch pairs, each with asynchronous

self-correcting feedback paths. The output of each latch

on the master or slave side votes with the outputs of the

other two latches on that side. If one of the three latches

is struck by an ion and starts to change state, the voting

with the other two latches prevents that change from

feeding back and permanently latching. Care was also

The RTAX-S/SL architecture is fully fracturable, meaning

that if one or more of the logic modules in a

SuperCluster are used by a particular signal path, the

other logic modules are still available for use by other

paths.

1-2

v5.3

RTAX-S/SL RadTolerant FPGAs

FCI

A[0:1]

B[0:1]

D[0:3]

CLK

PRE

CLR

C-cell

CFN

(Positive Edge Triggered)

FCO

C-Cell

R-Cell

Figure 1-3 • RTAX-S/SL C-Cell and R-Cell

C C R

Figure 1-4 • RTAX-S/SL SuperCluster

FCI

DCOUT

C-Cell

Carry Logic

FCO

Figure 1-5 • RTAX-S/SL Two-Bit Carry Logic

v5.3

1-3

RTAX-S/SL RadTolerant FPGAs

At the chip level, SuperClusters are organized into core

tiles, which are arrayed to build up the full chip. For

example, the RTAX1000S/SL is composed of a 3×3 array

of nine core tiles. Surrounding the array of core tiles are

blocks of I/O Clusters and the I/O bank ring (Table 1-1).

Each core tile consists of an array of 336 SuperClusters

and four SRAM blocks (176 SuperClusters and three

SRAM blocks for the RTAX250S/SL). The SRAM blocks are

arranged in a column on the west side of the tile

(Figure 1-6).

Table 1-1 • Number of Core Tiles per Device

Device

Number of Core Tiles

4 smaller tiles

RTAX250S/SL

RTAX1000S/SL

RTAX2000S/SL

RTAX4000S

9 regular tiles

16 regular tiles

30 regular tiles

SuperCluster

RAMC SC

RAM/

FIFO

RAMC SC

RAM/

FIFO

RAMC SC

RAM/

FIFO

Chip Layout

RAMC SC

Core Tile

RAM/

FIFO

RAMC SC

I/O Structure

Figure 1-6 • RTAX-S/SL Device Architecture (RTAX1000S/SL shown)

1-4

v5.3

RTAX-S/SL RadTolerant FPGAs

Embedded Memory

I/O Logic

The RTAX-S/SL family of FPGAs features a flexible I/O

structure, supporting a range of mixed voltages with its

bank-selectable I/Os: 1.5 V, 1.8 V, 2.5 V, and 3.3 V. In all,

RTAX-S/SL FPGAs support at least 14 different I/O

As mentioned earlier, each core tile has either three (in a

smaller tile) or four (in the regular tile) embedded SRAM

blocks along the west side, and each variable-aspect-

ratio SRAM block is 4,608 bits in size. Available memory

configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or

4kx1 bits. The individual blocks have separate read and

write ports that can be configured with different bit

widths on each port. For example, data can be written in

by eight and read out by one.

standards

(single-ended,

differential,

voltage-

referenced). The I/Os are organized into banks, with

eight banks per device (two per side). The configuration

of these banks determines the I/O standards supported

(see "User I/Os" on page 2-12 for more information). All

I/O standards are available in each bank.

In addition, every SRAM block has an embedded FIFO

control unit. The control unit allows the SRAM block to

be configured as a synchronous FIFO without using core

logic modules. The FIFO width and depth are

programmable. The FIFO also features programmable

ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL)

flags in addition to the normal EMPTY and FULL flags. In

addition to the flag logic, the embedded FIFO control

unit also contains the counters necessary for the

generation of the read and write address pointers as well

as control circuitry to prevent metastability and

erroneous operation. The embedded SRAM/FIFO blocks

can be cascaded to create larger configurations.

Each I/O module has an input register (InReg), an output

(Figure 1-7 on page 1-6). An I/O Cluster includes two I/O

modules, four RX modules, two TX modules, and a buffer

(B) module.

By design, all user flip-flops in the RTAX-S FPGAs are

immune to SEUs including the following three registers

located in every I/O cell buffer: InReg, OutReg, and

EnReg.

Routing

The FIFO control unit was not implemented with SEU-

hardened registers. Designs requiring high SEU tolerance

should implement the FIFO control unit from hardened

core logic.

The RTAX-S/SL hierarchical routing structure ties the logic

modules, the embedded memory blocks, and the I/O

modules together (Figure 1-8 on page 1-6). At the lowest

level, in and between SuperClusters, there are three local

routing structures: FastConnect, DirectConnect, and

CarryConnect routing. DirectConnects provide the highest

performance routing inside the SuperClusters by

connecting a C-cell to the adjacent R-cell. DirectConnects

do not require an antifuse to make the connection and

achieve a signal propagation time of less than 0.1 ns.

SRAM structures are inherently susceptible to upsets

caused by high-energy particles encountered in space.

High-energy particles can cause an SRAM cell to change

state, resulting in the loss or corruption of a valuable

data bit. Actel has enhanced the SEU tolerance of the

embedded SRAM within RTAX-S/SL by employing the use

of two upset-mitigation techniques:

FastConnects provide high-performance, horizontal

routing inside the SuperCluster and vertical routing to

the SuperCluster immediately below it. Only one

programmable connection is used in a FastConnect path,

delivering a maximum routing delay of 0.4 ns.

•

Actel has developed Error Detection and Correction

(EDAC) IP for use with RTAX-S/SL. EDAC can be

accomplished by the use of SmartGen-generated

Error Correcting Codes (ECC) IP, which employs the

use of shortened Hamming Codes

CarryConnects are used for routing carry logic between

adjacent SuperClusters. They connect the carry-logic FCO

output of one C-cell pair to the carry-logic FCI input of

the C-cell pair of the SuperCluster below. CarryConnects

do not require an antifuse to make the connection and

achieve a signal propagation time of less than 0.1 ns.

•

background memory-refresher, or scrubber

circuitry, which has been embedded into the EDAC IP.

The embedded scrubber circuitry periodically

refreshes memory in the background to ensure that

no data corruption occurs while the memory is not in

use.

The next level contains the core tile routing. Over the

SuperClusters within a core tile, both vertical and

horizontal tracks run across rows or columns,

respectively. At the chip level, vertical and horizontal

tracks extend across the full length of the device, both

north-to-south and east-to-west. These tracks are

composed of highway routing that extend the entire

length of the device (segmented at core tile boundaries)

as well as segmented routing of varying lengths.

The use of EDAC IP combined with the embedded

memory scrubber circuitry, gives the RTAX-S/SL an SEU

radiation performance level of better than 10^-10errors/

bit-day. See the application note Using EDAC RAM for

RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs.

v5.3

1-5

RTAX-S/SL RadTolerant FPGAs

I/O Module

InReg

OutReg

EnReg

RAM/

FIFO

I/O

Module

I/O

Module

I/O Cluster

RX RX

RAM/

FIFO

RAM/

FIFO

CoreTile

RAM/

FIFO

Figure 1-7 • I/O Cluster Arrangement

Figure 1-8 • RTAX-S/SL Routing Structures

1-6

v5.3

RTAX-S/SL RadTolerant FPGAs

functions for implementation into your schematic or HDL

design.

Global Resources

Each family member has three types of global signals

available to the designer: HCLK, CLK, and GCLR/GPSET.

There are four hardwired clocks (HCLK) per device that

can directly drive the clock input of each R-cell. Each of

the four routed clocks (CLK) can drive the clock, clear,

preset, or enable pin of an R-cell or any input of a C-cell

(Figure 1-3 on page 1-3).

Actel Designer software is compatible with the most

popular FPGA design entry and verification tools from

EDA vendors, such as Mentor Graphics, Synplicity,

Synopsys, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

Global clear (GCLR) and global preset (GPSET) drive the

clear and preset inputs of each R-cell as well as each I/O

Programming

Programming support is provided through Actel Silicon

Sculptor 3, a single-site programmer driven via a

PC-based GUI. Factory programming is available for high-

volume production needs.

Design Environment

The RTAX-S/SL family of FPGAs is fully supported by both

Actel Libero^®Integrated Design Environment (IDE) and

Designer FPGA Development software. Actel Libero IDE

is an integrated design manager that seamlessly

integrates design tools while guiding the user through

the design flow, managing all design and log files, and

passing necessary design data among tools. Additionally,

Libero IDE allows users to integrate both schematic and

HDL synthesis into a single flow and verify the entire

design in a single environment (see the Libero IDE Flow

diagram located on the Actel website). Libero IDE

includes Synplify^®AE from Synplicity^®, ViewDraw^®AE

from Mentor Graphics^®, ModelSim^®HDL Simulator from

Mentor Graphics, WaveFormer Lite™ AE from

SynaptiCAD^®, and Designer software from Actel.

Low-Cost Prototyping Solutions

Since the enhanced radiation characteristics of radiation-

tolerant devices are not required during the prototyping

phase of the design, Actel has developed two prototyping

options for RTAX-S/SL. For early design development and

functional verification, Actel offers the commercial

Axcelerator devices while for final flight design verification

in hardware, Actel offers the RTAX-S PROTO device that has

the same form, fit, and function as the flight silicon.

Prototyping with Axcelerator Units

The prototyping solution using the commercial Axcelerator

devices consists of two parts:

Actel's Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

the following:

•

A well-documented design flow that allows the

customer to target an RTAX-S/SL design to the

equivalent commercial Axcelerator device

A set of Actel Extender circuit boards that map the

commercial device package to the appropriate

RTAX-S package footprint

•

Timer – a world-class integrated static timing analyzer

and constraints editor which support timing-driven

place-and-route

This methodology provides the user with a cost-effective

solution while maintaining the short time-to-market

associated with Actel FPGAs.

•

NetlistViewer – a design netlist schematic viewer

ChipPlanner – a graphical floorplanner viewer and editor

SmartPower – allows the designer to quickly estimate

the power consumption of a design

Prototyping with RTAX-S PROTO Units

•

PinEditor – a graphical application for editing pin

assignments and I/O attributes

The RTAX-S PROTO units offer a prototyping solution

that can be used for final timing verification of the flight

design. The RTAX-S PROTO prototype units have the

same timing attributes as the RTAX-S/SL flight units.

I/O Attribute Editor – displays all assigned and

unassigned I/O macros and their attributes in a

spreadsheet format

Prototype units are offered in non-hermetic ceramic

packages. The prototype units include "PROTO" in their

part number, and “PROTO” is marked on devices to

indicate that they are not intended for space flight. They

also are not intended for applications, which require the

quality of space-flight units, such as qualification of

space-flight hardware. RT-PROTO units offer no

guarantee of hermeticity, and no MIL-STD-883B

processing. At a minimum, users should plan on using

class B level devices for all qualification activities.

With the Designer software, a user can lock the design

pins before layout while minimally impacting the results

of place-and-route. Additionally, the Actel back-

annotation flow is compatible with all the major

simulators and the simulation results can be cross-probed

with Silicon Explorer II, the Actel integrated verification

and logic analysis tool. Another tool included in the

Designer software is the SmartGen core generator, which

easily creates popular and commonly used logic

v5.3

1-7

RTAX-S/SL RadTolerant FPGAs

The RT-PROTO units are electrically tested in a manner to

guarantee their performance over the full military

temperature range. The RT-PROTO units will also be

offered in -1 or standard speed grades, so as to enable

customers to validate the timing attributes of their

space designs using actual flight silicon.

serial port of a PC and communicates with the FPGA via

the JTAG port (See "Silicon Explorer II Probe Interface"

on page 2-84).

In addition, Actel offers a Configurable Logic Analyzer

Module (CLAM), which allows a real-time verification

and debug capability to be embedded into IP

programmed into Actel FPGAs. CLAM allows signals from

the inside of the IP core to be routed to the exterior of

the chip for verification purposes.

Please see the application note Prototyping for RTAX-S

and RTAX-SL Devices for more details.

In-System Diagnostic and Debug

Capabilities

The RTAX-S/SL family of FPGAs includes internal probe

circuitry, allowing the designer to dynamically observe

and analyze any signal inside the FPGA without disturbing

normal device operation. Up to four individual signals can

be brought out to dedicated probe pins (PRA/B/C/D) on

the device. The probe circuitry is accessed and controlled

via Silicon Explorer II (Figure 1-9), the Actel integrated

verification and logic analysis tool that attaches to the

Summary

The Actel RTAX-S/SL family of FPGAs extends the

successful RTSX-SU family of radiation-tolerant FPGAs,

adding embedded RAM, FIFOs, and high-speed I/Os. With

the support of a suite of robust software tools, design

engineers can incorporate high gate counts and fixed

pins into an RTAX-S/SL design yet still achieve high

performance and efficient device utilization in an SEU-

hardened device.

RTAX-S/SL FPGAs

16-Pin

Connection

TDI*

TCK*

Serial

Connection

TMS*

Silicon Explorer II

TDO*

PRA*

PRB*

22-Pin

Connection

CH3/PRC*

CH4/PRD*

Additional 14 Channels

(Logic Analyzer)

Note: *Refer to the "Pin Descriptions" on page 2-11 for more information.

Figure 1-9 • Probe Setup

1-8

v5.3

RTAX-S/SL RadTolerant FPGAs

Related Documents

Application Notes

Simultaneous Switching Noise and Signal Integrity

http://www.actel.com/documents/SSN_AN.pdf

Differences Between RTAX-S/SL and Axcelerator

http://www.actel.com/documents/RTAXS_AX_Features_AN.pdf

Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs

http://www.actel.com/documents/EDAC_AN.pdf

Prototyping for RTAX-S and RTAX-SL Devices

http://www.actel.com/documents/PrototypingRTAXS_AN.pdf

Implementation of Security in Actel Antifuse FPGAs

http://www.actel.com/documents/Antifuse_Security_AN.pdf

Actel CQFP to FBGA Adapter Socket Instructions

http://www.actel.com/documents/CCGA_FBGA_AN.pdf

Actel CCGA to FBGA Adapter Socket Instructions

http://www.actel.com/documents/CQ352-FPGA_Adapter_AN.pdf

IEEE Standard 1149.1 (JTAG) in the Axcelerator Family

http://www.actel.com/documents/AX_JTAG_AN.pdf

User’s Guides and Manuals

Antifuse Macro Library Guide

http://www.actel.com/documents/libguide_UG.pdf

SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User’s Guide

http://www.actel.com/documents/smarttime_ug.pdf

Silicon Sculptor User’s Guide

http://www.actel.com/documents/SiliSculptII_Sculpt3_ug.pdf

Silicon Explorer II User’s Guide

http://www.actel.com/documents/Silexpl_UG.pdf

White Papers

Design Security in Nonvolatile Flash and Antifuse FPGAs

http://www.actel.com/documents/DesignSecurity_WP.pdf

Understanding Actel Antifuse Device Security

http://www.actel.com/documents/AntifuseSecurityWP.pdf

RTAX-S/SL Testing and Reliability Update

http://www.actel.com/documents/RTAXS_Rel_Test_WP.pdf

Miscellaneous

Libero IDE flow diagram

http://www.actel.com/products/software/libero/#flow

v5.3

1-9

RTAX-S/SL RadTolerant FPGAs

Detailed Specifications

Table 2-1 • I/O Features Comparison

Hot Insertion /

Cold Sparing

I/O Assignment

LVTTL

Clamp Diode

5V Tolerance

Input Buffer

Output Buffer

Yes

Yes¹

Enabled/Disabled

3.3 V PCI

Enabled/Disabled

LVCMOS2.5 V

Yes

LVCMOS1.8 V

LVCMOS1.5 V (JESD8-11)

Voltage-Referenced Input Buffer

Differential, LVDS/LVPECL, Input

Differential, LVDS/LVPECL, Output

Notes:

Enabled

Disabled

Disabled²

Enabled³

1. Can be implemented with an external resistor.

2. The OE input of the output buffer is automatically deasserted by Designer.

3. The OE input of the output buffer is automatically asserted by Designer.

5 V Tolerance

3.3 V PCI is the only I/O standard that directly allows 5 V

tolerance. This standard provides an internal clamp diode

between the input pad, and the V_CCIpad so that the

voltage at the input pin is clamped as shown in EQ 2-1:

An external series resistor (~100 Ω) is required between

the input pin and the 5 V signal source to limit the

current (Figure 2-1).

V_input= V_CCI+ V_diode= 3.3 V + 0.8 V = 4.1 V

Non-Actel Part

Actel FPGA

3.3 V 3.3 V

EQ 2-1

5 V

PCI

clamp

diode

ext

PCI

clamp

diode

Figure 2-1 • Use of an External Resistor for 5 V Tolerance

v5.3

2-1

RTAX-S/SL RadTolerant FPGAs

Operating Conditions

Absolute Maximum Conditions

Stresses beyond those listed in Table 2-2 may cause permanent damage to the device. Exposure to Absolute Maximum

rated conditions for extended periods may affect device reliability. Devices should not be operated outside the

recommended operating conditions in Table 2-3.

Table 2-2 • Absolute Maximum Ratings

Symbol

V_CCA

V_CCI

V_REF

V_I

Parameter

AC Core Supply Voltage¹

DC Core Supply Voltage

DC I/O Supply Voltage

DC I/O Reference Voltage

Input Voltage

Limits

Units

–0.3 to 1.8

–0.3 to 1.7

–0.3 to 3.75

–0.5 to 3.75

–60 to +150

–0.3 to 3.75

V_O

Output Voltage

T_STG

Storage Temperature

Supply Voltage for Differential I/Os

°C

V_CCDA

Notes:

1. The AC transient V_CCAlimit is for radiation-induced transients less than 10 µs duration and not intended for repetitive use. Core

voltage spikes from a single event transient will not negatively affect the reliability of the device if, for this non-repetitive event, the

transient does not exceed 1.8 V at any time and the total time that the transient exceeds 1.575 V does not exceed 10 µs in

duration.

2. V_CCDAmust be greater than or equal to the highest V_CCIvoltage

Table 2-3 • RTAX-S/SL Recommended Operating Conditions

Parameter Range

Ambient Temperature (T_A)¹

Military

–55 to +125

1.425 to 1.575

1.71 to 1.89

2.375 to 2.625

3.0 to 3.6

Units

°C

1.5 V Core Supply Voltage

1.5 V I/O Supply Voltage

1.8 V I/O Supply Voltage

2.5 V I/O Supply Voltage

3.3 V I/O Supply Voltage

2.5 V V_CCDAI/O Supply Voltage (no differential I/O used)

3.3 V V_CCDAI/O Supply Voltage (differential or voltage-referenced I/O used)²

3.3 V V_PUMPSupply Voltage

2.375 to 2.625

3.0 to 3.6

Notes:

1. Ambient temperature (T_A) is used for commercial and industrial grades; case temperature (T_C) is used for military grades.

2. Please see "V_CCDASupply Voltage" on page 2-11 more detail.

3. T_{j (max)}= 125ºC.

Overshoot/Undershoot Limits

For AC signals, the input signal may undershoot during

transitions to –1.0 V for no longer than 10% of the

period or 11 ns (whichever is smaller). Current during the

transition must not exceed 95 mA.

period or 11 ns (whichever is smaller). Current during the

transition must not exceed 95 mA.

Note: The above specification does not apply to the PCI

standard. The RTAX-S/SL PCI I/Os are compliant to the PCI

standard including the PCI overshoot/undershoot

specifications.

For AC signals, the input signal may overshoot during

transitions to V_CCI+ 1.0 V for no longer than 10% of the

2-2

v5.3

RTAX-S/SL RadTolerant FPGAs

Power-Up/Down Sequence

V_CCA, V_CCI, and V_CCDAcan be powered up or powered down in any sequence. During power-up, all RTAX-S/SL I/Os are

tristated until reaching the state defined by the design.

Calculating Power Dissipation

Table 2-4 • RTAX-S Standby Current

Device

Temperature

Typical 25ºC

125ºC

_CCA(mA)

TBD

I_CCI(mA)

I_CCDA(mA)

I_CCDIFFA(mA)

TBA

I_IL/I_IH

TBD

RTAX4000S

TBD

TBA

TBD

RTAX2000S

RTAX1000S

RTAX250S

Notes:

Typical 25ºC

125ºC

3.13

1 μA

5 μA

1 μA

5 μA

1 μA

5 μA

500

2.96

Typical 25ºC

125ºC

3.13

450

2.96

Typical 25ºC

125ºC

3.13

250

2.96

1. For calculating the leakage values, use a pull-down/pull-up resistor value of 60 Ω.

2. Above values are maximum.

3. Values in the I_CCDAcolumn refer to the current consumed by all the I/Os.

4. Values in the I_CCDIFFAcolumn refer to the current flowing per pair through differential amplifiers when using differential pairs or

voltage references pins.

Table 2-5 • RTAX-SL Standby Current

Device

Temperature

Typical 25ºC

125ºC

_CCA(mA)

I_CCI(mA)

I_CCDA(mA) I_CCDIFFA(mA)

I_IL/I_IH

1 μA

5 μA

1 μA

5 μA

1 μA

5 μA

RTAX2000SL

150

3.13

2.96

3.13

2.96

3.13

2.96

RTAX1000SL

RTAX250SL

Notes:

Typical 25ºC

125ºC

Typical 25ºC

125ºC

1. For calculating the leakage values, use a pull-down/pull-up resistor value of 60 Ω.

2. Above values are maximum.

3. Values in the I_CCDAcolumn refer to the current consumed by all the I/Os.

4. Values in the I_CCDIFFAcolumn refer to the current flowing per pair through differential amplifiers when using differential pairs or

voltage references pins.

v5.3

2-3

RTAX-S/SL RadTolerant FPGAs

Table 2-6 • Default C_load/ V_CCI

C_load(pF)

V_CCI(V)

P_load(µW/MHz)

P10 (µW/MHz)

PI/O (µW/MHZ)*

Single-Ended without V_REF

LVCMOS – 15 (JESD8-11)

LVCMOS –18

1.5

1.8

2.5

3.3

78.75

113.4

127.7

186.8

373.8

499.4

519.2

531.5

549.8

511

73.4

LVCMOS – 25

218.75

381.15

108.9

155

LVTTL 8 mA Low Slew

LVTTL 12 mA Low Slew

LVTTL 16 mA Low Slew

LVTTL 24 mA Low Slew

LVTTL 8 mA High Slew

LVTTL 12 mA High Slew

LVTTL 16 mA High Slew

LVTTL 24 mA High Slew

PCI

118.2

138.1

150.3

168.7

129.8

165.4

224.6

267

546.5

605.7

648.1

326.9

271.3

218

PCI-X

108.9

162.4

Single-Ended with V_REF

SSTL2-I

2.5

3.3

1.5

3.3

–

171.2

147.8

327.2

288.4

40.9

171.2

147.8

327.2

288.4

40.9

SSTL2-II

SSTL3-I

SSTL3-II

HSTL-I

GTLP – 33

67.6

Differential

LVPECL – 33

N/A

3.3

2.5

–

260.1

145.3

260.1

145.3

LVDS – 25

Note: *P_I/O= P₁₀+ C_load* V_CCI

Table 2-7 • Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices

Device-Specific Value (in µW/MHz)

RTAX250S/ RTAX1000S/ RTAX2000S/

Symbol

Power Component

85.8

0.6

7.7

1.8

0.9

8.6

1.6

1.4

10.0

227.5

0.6

378.0

0.6

RTAX4000S

Core tile HCLK power component

700

0.6

R-cell power component

HCLK signal power dissipation

23.2

227.5

0.9

31.0

378.0

0.9

Core tile RCLK power component

700

0.9

R-cell power component

RCLK signal power dissipation

25.7

1.6

34.3

1.6

Power dissipation due to the switching activity on the R-cell

Power dissipation due to the switching activity on the C-cell

Power component associated with the input voltage

Power component associated with the output voltage

1.6

1.4

10.0

P10

See Table 2-4 and Table 2-5 on page 2-3 for per pin

contribution.

2-4

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-7 • Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices (Continued)

Device-Specific Value (in µW/MHz)

RTAX250S/ RTAX1000S/ RTAX2000S/

Symbol

Power Component

RTAX4000S

P11

Power component associated with the read operation in the

RAM block

25.0

P12

Power component associated with the write operation in

the RAM block

30.0

P_total= P_dc+ P_ac

P_dc

I_CCA* V_CCA+ I_CCI* V_CCI* N_banks+ I_CCDA* V_CCDA+ I_CCDIFFA* V_CCDA* N_{b_da_pairs}

P_HCLK+ P_CLK+ P_R-cells+ P_C-cells+ P_inputs+ P_outputs+ P_memory

number of banks

P_ac

N_banks

N_{b_da_pairs}

number of differential pairs or voltage referenced pins used

P_HCLK= (P1 + P2 * s + P3 * sqrt[s]) * Fs

number of R-cells clocked by this clock

clock frequency

_CLK= (P4 + P5 * s + P6 * sqrt[s]) * Fs

number of R-cells clocked by this clock

clock frequency

P_R-cells= P7 * ms * Fs

number of R-cells switching at each Fs cycle

clock frequency

_C-cells= P8 * mc * Fs

number of C-cells switching at each Fs cycle

clock frequency

_inputs= P9 * pi * F_pi

number of inputs

F_pi

average input frequency

P_outputs= (P10 + C_load* V_CCI²) * po * F_po

C_load

V_CCI

output load (technology dependent)

output voltage (technology dependent)

number of outputs

F_po

average output frequency

_memory= P11 * N_block* F_RCLK+ P12 * N_block* F_WCLK

N_block

F_RCLK

F_WCLK

number of RAM/FIFO blocks (1 block = 4k)

read-clock frequency of the memory

write-clock frequency of the memory

v5.3

2-5

RTAX-S/SL RadTolerant FPGAs

Power Estimation Example

This example employs an RTAX1000S/SL shift-register design with 1,080 R-cells, one C-cell, one reset input, and one

output. This design also uses a single clock (HCLK) at 100 MHz and is operated under room temperature.

ms = 1,080 (in a shift register 100% of R-cells are toggling at each clock cycle)

100 MHz

1,080

=> P_HCLK= (P1 + P2 * s + P3 * sqrt[s]) * Fs = 163.8 mW

and Fs = 100 MHz

=> P_R-cells= P7 * ms * Fs = 172.8 mW

1 (1 C-cell in this design)

and Fs = 100 MHz

=> P_C-cells= P8 * mc * Fs = 0.14 mW

_pi~ 0 MHz

and pi= 1 (1 reset input => this is why F_pi= 0)

=> P_inputs= P9 * pi * F_pi= 0 mW

F_po

50 MHz

_load= 35 pF

_CCI= 3.3 V

and po = 1

=> P_outputs= (P10 + C_load* V_CCI²) * po * F_po= 23.6 mW

No RAM/FIFO in this shift-register

=> P_memory= 0 mW

P_ac

P_dc

P_total

P_HCLK+ P_CLK+ P_R-cells+ P_C-cells+ P_inputs+ P_outputs+ P_memory= 360.4 mW

I_CCA* V_CCA+ I_CCI* V_CCI* N_banks+ I_CCDA* V_CCDA+ I_CCDIFFA* V_CCDA* N_{b_da_pairs}= 101.1 mW

P_dc+ P_ac= 360.4 mW + 101.1 mW = 461.5 mW

2-6

v5.3

RTAX-S/SL RadTolerant FPGAs

Thermal Characteristics

The temperature variable in Actel Designer software

refers to the junction temperature, not the ambient, case

or board temperature. This is an important distinction

because dynamic and static power consumption causes

the chip's junction temperature to be higher than the

ambient, case or board temperature. EQ 2-2, EQ 2-3, and

EQ 2-4 show the relationship between thermal

resistance, temperature, and power.

Where:

Thermal resistance from junction to air

Thermal resistance from junction to case

Thermal resistance from junction to board

T_j

T_a

T_c

T_b

= Junction Temperature

= Ambient Temperature

= Case Temperature

= Board Temperature

= Power

T_j– T

--------------^a-

θ_ja

θ_jc

θ_jb

EQ 2-2

EQ 2-3

EQ 2-4

T_j– T_c

---------------

T_j– T

--------------^b-

Table 2-8 • Package Thermal Characteristics

Product

Package Type

CQ208

θ_ja

19.9

16.8

13.3

10.8

15.8

12.3

9.7

θ_jc

0.8

0.7

0.4

5.6

0.25

0.2

4.3

2.0

0.2

2.0

θ_jb

Units

C/W

RTAX250S/SL

N/A

4.5

N/A

3.5

2.6

N/A

2.2

CQ352

RTAX1000S/SL

RTAX2000S/SL

CQ352

CG624

CQ256

CQ352

CG624

CG1152

CQ352

9.0

RTAX4000S

12.3

8.0

CG1272

Notes:

1. θ_jaare estimated at still air.

2. θ_jcfor CQFP refers to the thermal resistance between the junction and the bottom surface of the package.

3. θ_jcfor CG packages refers to the thermal resistance between the junction and the top surface of the package.

4. The θ_jbvalues in the table are simulated under conduction heat transfer only.

v5.3

2-7

RTAX-S/SL RadTolerant FPGAs

Calculation for Power

Sample Case 1: Convection

A sample calculation of the power dissipation allowed for an RTAX1000S/SL-CG624 in still air is shown below. Assume

that the maximum junction temperature is maintained at 110°C and the ambient temperature is 50°C. The maximum

power allowed can be estimated using the equation below.

T_j= 110°C

T_a= 50°C

110°C – 50°C

----------------------------------

θ_ja= 10.8°C/W =

= 5.55 W

Air

Solder Columns

PCB

Figure 2-2 • Heat Flow when Air is Present

Sample Case 2: Convection = 0

A sample calculation of the power dissipation when there is no air in the environment is shown below. An RTAX1000S/

SL-CQ352 is attached to the board with a thermal adhesive between the package body. The thermal resistance of the

paste is 0.58°C/W. Since air is not present in the environment, most of the heat will be flowing through the bottom of

the package, through the thermal paste, and to the board. Neglecting the heat flowing through the package leads,

the maximum power allowed can be estimated as shown in the equations below.

T_j= 110°C

θ_cb= Thermal resistance of the thermal paste from case to board (i.e., = 0.58°C/W)

T_b= 70°C

θ_{jb (Total)}= θ_jc+ θ_cb

110°C – 70°C

----------------------------------

θ_jc+ θ_cb

110°C – 70°C

----------------------------------

0.4°C/W + 0.58°C/W =

110°C – 70°C

----------------------------------

θ_{jb (Total)}

= 40.8 W

Thermal Adhesive

PCB

Figure 2-3 • Heat Flow in a Vacuum

The thermal resistances, shown in Table 2-8 on page 2-7, are based on the simulations done with test conditions and test

boards configurations specified in JEDEC specification JESD51.

2-8

v5.3

RTAX-S/SL RadTolerant FPGAs

Timing Characteristics

RTAX-S/SL devices are manufactured in a CMOS process, therefore, device performance varies according to

temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage,

minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating

voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-9 should

be applied to all timing data contained within this datasheet.

Table 2-9 • Temperature and Voltage Timing Derating Factors

(Normalized to Worst-Case Military, T_J= 125°C, V_CCA= 1.4 V)

Junction Temperature

V_CCA

1.4V

–55°C

0.74

0.72

0.69

0.66

0.65

–40°C

0.75

0.74

0.71

0.68

0.67

0°C

0.80

0.79

0.75

0.72

0.71

25°C

0.84

0.82

0.78

0.75

0.74

70°C

0.89

0.88

0.84

0.80

0.79

85°C

0.92

0.91

0.86

0.83

0.82

125°C

1.00

0.98

0.94

0.90

0.89

1.425V

1.5V

1.575V

1.6V

Notes:

1. The user can set the junction temperature in Designer software to be any integer value in the range of –55°C to 125°C.

2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V.

All timing numbers listed in this datasheet represent sample timing characteristics of RTAX-S/SL devices. Actual timing

delay values are design-specific and can be derived from the Timer tool in Actel’s Designer software after place-and-

route.

v5.3

2-9

RTAX-S/SL RadTolerant FPGAs

Timing Model

I/O Module

(Nonregistered)

Carry Chain

t_PY= 2.45 ns

I/O

Combinatorial

Cell

Combinatorial

Cell

LVPECL

FCO

I/O

t_CCY= 0.76 ns

t_PDC= 0.70 ns

I/O Module

(Registered)

I/O Module

(Nonregistered)

t_RD2= 0.84 ns

Combinatorial

Cell

_DP= 1.83 ns

Buffer

Module

Buffer

Module

t_PY= 3.51 ns

LVPECL

LVTTL

Output Drive Strength = 4 (24mA)

High Slew Rate

t_BFPD= 0.17 ns

t_PD= 0.95 ns

t_BFPD= 0.17 ns

_ICLKQ= 0.91 ns

t_RD1= 0.66 ns

t_SUD= 0.31 ns

t_RD2= 0.84 ns

t_RD3= 1.07 ns

LVTTL

t_DP= 1.85 ns

Routed or Hardwired

t_HCKH= 3.65 ns

_MAX(external) = 350 MHz

F_MAX(internal) = 700 MHz

Combinatorial

Cell

_RD1= 0.66 ns

_RCO= 0.96 ns

_SUD= 0.21 ns

I/O Module

_OCLKQ= 0.91 ns

_SUD= 0.31 ns

Buffer

Module

t_PY= 1.26 ns

I/O Module

(Non- registered)

GTL + 3.3V

_BPFD= 0.21ns

t_PD= 0.95 ns

t_RCO= 0.96 ns

t_SUD= 0.21 ns

LVDS

t_RCKL= 3.54 ns

t_RCKH= 3.71 ns

_RCKL= 3.54 ns

F_MAX(external) = 350 MHz

F_MAX(internal) = 700 MHz

t_DP= 2.00 ns

Routed Clock

LVTTL

_DP= 1.85 ns

t_HCKL= 3.48 ns

_RCKL= 3.55 ns

Hardwired or Routed Clock

LVTTL

_DP= 1.85 ns

Note: Timing data is for the RTAX2000S/SL, –1 speed.

Figure 2-4 • Timing Model

Hardwired Clock

Routed Clock

External Setup

(t_DP+ t_RD2+ t_SUD) – t_HCKH

(1.85 + 0.84 + 0.31) – 3.65

–0.61

(t_DP+ t_RD2+ t_SUD) – t_RCKH

(1.85 + 0.84 + 0.31) – 3.54

–0.71 ns

Clock-to-Out (Pad-to-Pad)

t_HCKH+ t_RCO+ t_RD1+ t_PY

t_RCKH+ t_RCO+ t_RD1+ t_PY

3.65 + 0.90 + 0.66 + 3.51

8.72 ns

3.71 + 0.90 + 0.66 + 3.51

8.78 ns

2-10

v5.3

RTAX-S/SL RadTolerant FPGAs

I/O Specifications

User-Defined Supply Pins

Pin Descriptions

Supply Voltage

REF

Supply Pins

GND

Reference voltage for I/O banks. V_REFpins are configured

by the user from regular I/O pins; V_REFare not in fixed

locations. There can be one or more V_REFpins in an I/O

bank.

Ground

Low supply voltage.

Supply Voltage

CCA

Global Pins

Supply voltage for array (1.5 V).

HCLKA/B/C/D

Dedicated (Hardwired)

Clocks A, B, C, and D

Supply Voltage

CCIBx

Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See

"User I/Os" on page 2-12 for more information.

These pins are the clock input for sequential modules.

Input levels are compatible with all supported I/O

standards (there is a P/N pin pair for support of

differential I/O standards). This input is directly wired to

each R-cell and offers clock speeds independent of the

number of R-cells being driven. When the HCLK pins are

unused, it is recommended that they are tied to the

ground.

Supply Voltage

CCDA

Supply voltage for the I/O differential amplifier and JTAG

and probe interfaces. V_CCDAis either 3.3 V or 2.5 V and

must use 3.3 V when voltage-referenced and/or

differential is used. Additionally, V_CCDA

than or equal to any V_CCIvoltages (i.e. V_CCDA

^must≥^beV_C^g_C^r_I^eB^ax^t).^er

CLKE/F/G/H

Global Clocks E, F, G, and H

Supply Voltage (External Pump)

PUMP

These pins are clock inputs for clock distribution

networks. Input levels are compatible with all supported

I/O standards (there is a P/N pin pair for support of

differential I/O standards). The clock input is buffered

prior to clocking the R-cells. When the CLK pins are

unused, Actel recommends that they are tied to a known

state.

In low-power mode, V_PUMPwill be used to access an

external charge pump (if the user desires to bypass the

internal charge pump to further reduce power). The

device starts using the external charge pump when the

voltage level on V_PUMPreaches 3.3 V.¹In normal device

operation, when using the internal charge pump, V_PUMP

should be tied to GND.

1. When V_PUMP= 3.3V, it shuts off the internal charge pump.

v5.3

2-11

RTAX-S/SL RadTolerant FPGAs

JTAG/Probe Pins

Special Functions

PRA/B/C/D

Probes A, B, C, and D

No Connection

The probe pins are used to output data from any user-

defined design node within the device (controlled with

Silicon Explorer II). These independent diagnostic pins

can be used to allow real-time diagnostic output of any

signal path within the device. The pins’ probe

capabilities can be permanently disabled to protect

programmed design confidentiality.

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

User I/Os

Introduction

TCK

Test Clock

The RTAX-S/SL family features a flexible I/O structure,

supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V,

and 3.3 V) with its bank-selectable I/Os. Table 2-10 on

page 2-13 contains the I/O standards supported by the

RTAX-S/SL family.

Test clock input for JTAG boundary-scan testing and

diagnostic probe (Silicon Explorer II).

TDI

Test Data Input

Serial input for JTAG boundary-scan testing and

diagnostic probe. TDI is equipped with an internal pull-

up resistor with approximately 10 kΩ resistance.

Unused I/Os are configured as follows:

•

Output buffer is disabled (with tristated value of

Hi-Z)

TDO

Test Data Output

•

Input buffer is disabled (with tristated value of Hi-Z)

No pull-up/pull-down is programmed

Serial output for JTAG boundary-scan testing.

TMS

Test Mode Select

In Actel Designer Software, unused RTAX-S/SL I/Os are

configured as tristate with no pull-up resistors.

The TMS pin controls the use of the IEEE 1149.1

boundary-scan pins (TCK, TDI, TDO, TRST). TMS is

equipped with an internal pull-up resistor with

approximately 10 kΩ resistance.

Each I/O provides programmable slew rates, drive

strengths, and weak pull-up and weak pull-down circuits.

All I/O standards are 3.3 V tolerant, and I/O standards,

except 3.3 V PCI, are capable of hot insertion and cold

sparing. 3.3 V PCI is also 5 V tolerant with the aid of an

external resistor (see "5 V Tolerance" on page 2-1).

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active-low input to

asynchronously initialize or reset the boundary scan

circuit. The TRST pin is equipped with a programmable

pull-up resistor with approximately 10 kΩ resistance (i.e.

with or without the pull-up resistor). This pin must be

hardwired to ground for flight.

Each I/O includes three registers: an input (InReg), an

output (OutReg), and an enable register (EnReg).

I/Os are organized into banks, and there are eight banks per

device – two per side (Figure 2-7 on page 2-20). Each I/O

bank has a common V_CCI, the supply voltage for its I/Os.

For voltage-referenced I/Os, each bank also has a

common reference-voltage bus, V_REF. While V_REFmust

have a common voltage for an entire I/O bank, its

location is user-selectable. In other words, any user I/O in

the bank can be selected to be a V_REF

2. Actel recommends that you use a series termination resistor on every probe connector (TDI, TCK, TDO, PRA, PRB, PRC, and

PRD). The series termination is used to prevent data transmission corruption (i.e., due to reflection from the FPGA to the probe

connector) during probing and reading back the checksum. With an internal setup we have seen 70-ohm termination resistor

improved the signal transmission. Since the series termination depends on the setup, Actel recommends users to calculate the

termination resistor for their own setup. Below is a guideline on how to calculate the resistor value.

The resistor value should be chosen so that the sum of it and the probe signal’s driver impedance equals the effective trace

impedance.

Z0 = Rs + Zd

Z0 = trace impedance (silicon explorer’s breakout cable’s resistance + PCB trace impedance), Rs = series termination,

Zd = probe signal’s driver impedance.

The termination resistor should be placed as close as possible to the driver.

Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and hence the

driver impedances needs to be calculated from RTAX-S IBIS Models (Mixed Voltage Operation). PRA, PRB, PRC, PRD, and TDO

are driven by the FPGA and driver impedance can also be calculated from the IBIS Model.

Silicon explorer’s breakout cable’s resistance is usually close to 1 ohm.

3. Do not use an external resistor to pull the I/O above V_CCIfor a higher logic “1” voltage level. The desired higher logic “1”

voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above V_CCI

2-12

v5.3

RTAX-S/SL RadTolerant FPGAs

The location of the V_REFpin should be selected according

to the following rules:

The differential amplifier supply voltage V_CCDAshould be

connected to 3.3 V. When neither voltage-referenced nor

differential I/Os are used, V_CCDAmay be connected to

2.5 V when V_CCI<= 2.5 V in a given I/O bank; however, it

is still recommended to connect V_CCDAto 3.3 V.

•

Any pin that is assigned as a V_REFcan control a

maximum of eight user I/O pad locations in each

direction (16 total maximum) within the same I/O

bank.

The user can gain access to the various I/O standards in

three ways:

•

I/O package locations listed as no-connects are

counted as part of the 16 maximum. In many

cases, this leads to fewer than eight user I/O

package pins in each direction being controlled by

a V_REFpin.

•

Instantiate specific library macros that represent

the desired specific standard

•

Use generic I/O macros and then use Actel

Designer’s PinEditor to specify the desired I/O

standards. (Please note that this is not applicable

to differential standards.)

•

Dedicated I/O pins (GND, V_CCI...) are not counted

as part of the 16.

The user I/O pad immediately adjacent on either

side of the V_REFpin may only be used as an input.

The exception is when there is a V_CCI/GND pair

separating the V_REFpin and the user I/O pad

location.

•

A combination of the first two methods

Please refer to the I/O Features in Axcelerator Family

Devices application note and the Antifuse Macro Library

Guide for more details.

Table 2-10 • I/O Standards Supported by the RTAX-S/SL Family

Input/Output Supply Input Reference Voltage

Board Termination Voltage

(V_TT)

I/O Standard

LVTTL

Voltage (V_CCI

)

(V_REF

N/A

1.0

)

3.3

2.5

1.8

1.5

3.3

2.5

1.5

3.3

2.5

3.3

N/A

1.2

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V (JDEC8-11)

3.3 V PCI

GTL+ 3.3 V

GTL+ 2.5 V^*

HSTL Class 1

SSTL3 Class 1 and II

SSTL2 Class1 and II

LVDS

1.0

1.2

0.75

1.5

0.75

1.5

1.25

N/A

1.25

N/A

LVPECL

Note: * 2.5 V GTL+ is not supported across the full military temperature range.

v5.3

2-13

RTAX-S/SL RadTolerant FPGAs

Table 2-12 • Compatible I/O Standards for Different V_CCI

Simultaneous Switching Outputs (SSO)

Actel defines SSOs as any outputs that transition in phase

within a 1 ns window. The measurements made by Actel

are based on the following worst-case conditions:

Values

V_CCI

Compatible Standards

V_REF

1.0

3.3 V

2.5 V

1.8 V

1.5 V

Notes:

LVTTL, PCI, LVPECL, GTL+ 3.3V

SSTL 3 (Class I and II), LVTTL, PCI, LVPECL

LVCMOS 2.5V, GTL+ 2.5V, LVDS²

1. The switching outputs are adjacent to the quiet

output on either side.

1.5

1.0

2. All unused I/O buffers are tristated so they do not

LVCMOS 2.5V, SSTL 2 (Classes I and II), LVDS²1.25

help either ground or V_CC

LVCMOS 1.8V

N/A

3. A worst-case package was used.

LVCMOS 1.5V, HSTL Class I

0.75

When multiple output drivers switch simultaneously,

they induce a voltage drop in the chip/package power

distribution. This simultaneous switching momentarily

raises the ground voltage within the device relative to

the system ground. This apparent shift in the ground

potential to a non-zero value is known as simultaneous

switching noise (SSN) or more commonly, ground

bounce.

1. V_CCIis used for both inputs and outputs.

2. V_CCItolerance is 5%.

Table 2-13 on page 2-15 summarizes the different

combinations of voltages and I/O standards that can be

used together in the same I/O bank. Note that two I/O

standards are compatible if:

SSN becomes more of an issue in high pin count

packages and when using high performance devices such

as the RTAX-S/SL family.

•

Their V_CCIvalues are identical

Their V_REFstandards are identical (if applicable)

Please refer to the Simultaneous Switching Noise and

Signal Integrity application note for more information.

For example, if LVTTL 3.3 V (V_REF= 1.0V) is used, then the

other available (i.e. compatible) I/O standards in the

same bank are LVTTL 3.3 V PCI, GTL+, and LVPECL.

I/O Banks and Compatibility

Also note that when multiple I/O standards are used

within a bank, the voltage tolerance will be limited to

the minimum tolerance of all I/O standards used in the

bank. For instance, when using LVCMOS2.5 (+/-8% V_CCI

tolerance) and LVDS (+/-5% V_CCItolerance) within an I/O

bank, the maximum voltage tolerance of the bank will

Since each I/O bank has its own user-assigned input

reference voltage (V_REF) and an input/output supply

voltage (V_CCI), only I/Os with compatible standards can

be assigned to the same bank.

Table 2-11 shows the compatible I/O standards for a

common V_REF(for voltage-referenced standards).

Similarly, Table 2-12 shows compatible standards for a

be +/-5% V_CCI

common V_CCI

Table 2-11 • Compatible I/O Standards for Different V_REF

Values

V_REF

Compatible Standards

SSTL 3 (Class I and II)

SSTL 2 (Class I and II)

GTL+ (2.5 V and 3.3 V Outputs)

HSTL (Class I)

1.5 V

1.25 V

1.0 V

0.75 V

2-14

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-13 • Legal I/O Usage Matrix

I/O Standard

LVTTL 3. 3V (V_REF=1.0V)

LVTTL 3. 3V(V_REF=1.5V)

LVCMOS 2.5 V (V_REF=1.0V)

LVCMOS 2.5 V (V_REF=1.25V)

LVCMOS1.8 V

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

LVCMOS1.5 V (V_REF=1.75 V) (JESD8-11)

3.3 V PCI (V_REF=1.0V)

3.3 V PCI (V_REF=1.5V)

GTL+ (3.3 V)

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

GTL+ (2.5 V)

✓

–

✓

–

HSTL Class I

–

SSTL2 Class I & II

–

✓

–

✓

–

✓

–

SSTL3 Class I & II

✓

–

✓

–

✓

–

✓

–

LVDS (V_REF=1.0 V)

LVDS (V_REF=1.25 V)

LVPECL (V_REF=1.0 V)

LVPECL (V_REF=1.5 V)

Notes:

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

✓

–

1. Note that GTL+2.5 V is not supported across the full military temperature range.

2. A "✓" indicates whether standards can be used within a bank at the same time.

Examples:

a) LVTTL can be used with 3.3 V PCI and GTL+ (3.3 V), when V_REF= 1.0 V (GTL+ requirement).

b) LVTTL can be used with 3.3 V PCI and SSTL3 Class I and II, when V_REF= 1.5 V (SSTL3 requirement).

c) LVDS V_CCI= 2.5 V 5%.

v5.3

2-15

RTAX-S/SL RadTolerant FPGAs

I/O Clusters

Each I/O cluster incorporates two I/O modules, four RX modules and two TX modules, and a buffer module. In turn,

each I/O module contains one Input Register (InReg), one Output Register (OutReg), and one Enable Register (EnReg)

(Figure 2-5).

I/O CLUSTER

P PAD

EnReg

DIN YOUT

OEP

Routed Input Track

OutREg

Routed Input Track

Output Track

Routed Input Track

Output Track

UOP

UIP

YOUT

DIN

I/O

Slew Rate

Drive Strength

InReg

DCIN

V_REF

N PAD

EnReg

DIN YOUT

Routed Input Track

OEN

UON

Routed Input Track

OutREg

Routed Input Track

Output Track

I/O

YOUT

DIN

Slew Rate

Drive Strength

InReg

DCIN

Output Track

UIN

V_REF

Figure 2-5 • I/O Cluster Interface

Using an I/O Register

To access the I/O registers, registers must be instantiated

in the netlist and then connected to the I/Os. Usage of

each I/O register (register combining) is individually

controlled and can be selected/deselected using the

PinEditor tool in Actel's Designer software. I/O register

combining can also be controlled at the device level,

affecting all I/Os. Please note, the I/O register option is

deselected by default in any given design.⁴

Fuse option in the Designer software, when checked,

causes all I/O registers to output logic HIGH at device

power-up.

Using the Weak Pull-Up and Pull-Down

Circuits

Each RTAX-S/SL I/O comes with a weak pull-up/down

circuit (on the order of 10 kΩ). I/O macros are provided

for combinations of pull up/down for LVTTL, LVCMOS

(2.5 V, 1.8 V, and 1.5 V) standards. These macros can be

instantiated if a keeper circuit for any input buffer is

required.

In addition, Designer software provides a global option to

enable/disable the usage of registers in the I/Os. This option

is design specific. The setting for each individual I/O

overrides this global option. Furthermore, the Global Set

4. Please note that register combining for multi fanout nets is not supported.

2-16

v5.3

RTAX-S/SL RadTolerant FPGAs

Customizing the I/O

RTAX-S/SL I/O slew-rates and drive strength can be

customized:

Macros for Specific I/O Standards

There are different macro types for any I/O standard or

feature that determine the required V_CCIand V_REF

voltages for an I/O. The generic buffer macros require

the LVTTL standard with slow slew rate and 24 mA-drive

strength. LVTTL can support high slew rate but this

should only be used for critical signals.

•

The slew-rate value for the LVTTL output buffer

can be programmed and can be set to either slow

or fast.

•

The drive strength value for LVTTL output buffers

can be programmed as well. There are four

different drive strength values—8 mA, 12 mA,

16 mA, or 24 mA—that can be specified in

Designer.⁵

Most of the macro symbols represent variations of the six

generic symbol types:

•

CLKBUF: Clock Buffer

HCLKBUF: Hardwired Clock Buffer

INBUF: Input Buffer

Using the Differential I/O Standards

OUTBUF: Output Buffer

TRIBUF: Tristate Buffer

BIBUF: Bidirectional Buffer

Differential I/O macros should be instantiated in the

netlist. The settings for these I/O standards cannot be

changed inside Designer. Note that there are no tristated

or bidirectional I/O buffers for differential standards.

Other macros include the following:

•

Differential I/O standard macros: The LVDS and

LVPECL macros either have a pair of differential

inputs (e.g. INBUF_LVDS) or a pair of differential

outputs (e.g. OUTBUF_LVPECL).

Using the Voltage-Referenced I/O Standards

Using these I/O standards is similar to that of single-

ended I/O standards. Their settings can be changed in

Designer.

•

Pull-up and pull-down variations of the INBUF,

BIBUF, and TRIBUF macros. These are available

only with TTL and LVCMOS thresholds. They can

be used to model the behavior of the pull-up and

pull-down resistors available in the architecture.

Whenever an input pin is left unconnected, the

output pin will either go high or low rather than

unknown. This allows users to leave inputs

unconnected without having the negative effect

on simulation of propagating unknowns.

Using DDR (Double Data Rate)

In Double Data Rate mode, new data is present on every

transition of the clock signal. Clock and data lines have

identical bandwidth and signal integrity requirements,

making it very efficient for implementing very high-

speed systems.

To implement a DDR, users must do the following:

1. Instantiate an input buffer (with the required I/O

standard).

•

DDR_REG macro. It can be connected to any I/O

standard input buffers (i.e., INBUF) to implement a

double data rate register. Designer software will

map it to the I/O module in the same way it maps

the other registers to the I/O module.

2. Instantiate the DDR_REG macro (Figure 2-6).

3. Connect the output from the Input buffer to the

input of the DDR macro.

4. DDR supports all I/O standards.

5. The DDR macro in SmartGen can be used to

implement DDR.

6. Bit width and I/O standard can be chosen in

SmartGen.

PRE

CLK

CLR

Figure 2-6 • DDR Register

5. These values are minimum drive strengths.

v5.3

2-17

RTAX-S/SL RadTolerant FPGAs

Table 2-14, Table 2-15, and Table 2-16 on page 2-19 list all the available macro names differentiated by I/O standard,

type, slew rate, and drive strength.

Table 2-14 • Macros for Single-Ended I/O Standards

Standard

V_CCI

Macro Names

LVTTL

3.3 V

CLKBUF, HCLKBUF

INBUF,

OUTBUF,

OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24,

OUTBUF_H_8, OUTBUF_H_12, OUTBUF_H_16, OUTBUF_H_24,

TRIBUF,

TRIBUF_S_8, TRIBUF_S_12, TRIBUF_S_16, TRIBUF_S_24,

TRIBUF_H_8, TRIBUF_H_12, TRIBUF_H_16, TRIBUF_H_24,

BIBUF,

BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24,

BIBUF_H_8, BIBUF_H_12, BIBUF_H_16, BIBUF_H_24,

3.3V PCI

3.3 V

2.5 V

CLKBUF_PCI, HCLKBUF_PCI,

INBUF_PCI,

OUTBUF_PCI,

TRIBUF_PCI,

BIBUF_PCI

LVCMOS25

CLKBUF_LVCMOS25,

HCLKBUF_LVCMOS25,

INBUF_LVCMOS25,

OUTBUF_LVCMOS25,

TRIBUF_LVCMOS25,

BIBUF_LVCMOS25

LVCMOS18

1.8 V

1.5 V

CLKBUF_LVCMOS18,

HCLKBUF_LVCMOS18,

INBUF_LVCMOS18,

OUTBUF_LVCMOS18,

TRIBUF_LVCMOS18,

BIBUF_LVCMOS18

LVCMOS15 (JESD8-11)

CLKBUF_LVCMOS15,

HCLKBUF_LVCMOS15,

INBUF_LVCMOS15,

OUTBUF_LVCMOS15,

TRIBUF_LVCMOS15,

BIBUF_LVCMOS15

2-18

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-15 • I/O Macros for Differential I/O Standards

Standard

V_CCI

Macro Names

CLKBUF_LVPECL, HCLKBUF_LVPECL,

LVPECL

3.3 V

INBUF_LVPECL, OUTBUF_LVPECL

LVDS

2.5 V

CLKBUF_LVDS, HCLKBUF_LVDS,

INBUF_LVDS, OUTBUF_LVDS

Table 2-16 • I/O Macros for Voltage-Referenced I/O Standards

Standard

V_CCI

V_REF

Macro Names

GTL+

3.3 V

1.0 V CLKBUF_GTP33, HCLKBUF_GTP33, INBUF_GTP33, OUTBUF_GTP33, TRIBUF_GTP33,

BIBUF_GTP33

GTL+

2.5 V

3.3 V

1.5 V

1.0 V CLKBUF_GTP25, HCLKBUF_GTP25, INBUF_GTP25, OUTBUF_GTP25, TRIBUF_GTP25,

BIBUF_GTP25

SSTL2 Class I

SSTL2 Class II

SSTL3 Class I

SSTL3 Class II

HSTL Class I

1.25 V CLKBUF_SSTL2_I, HCLKBUF_SSTL2_I, TRIBUF_SSTL2_I, BIBUF_SSTL2_I, INBUF_SSTL2_I,

OUTBUF_SSTL2_I

1.25 V CLKBUF_SSTL2_II, HCLKBUF_SSTL2_II, TRIBUF_SSTL2_II, BIBUF_SSTL2_II, INBUF_SSTL2_II,

OUTBUF_SSTL2_II

1.5 V CLKBUF_SSTL3_I, HCLKBUF_SSTL3_I, TRIBUF_SSTL3_I, BIBUF_SSTL3_I, INBUF_SSTL3_I,

OUTBUF_SSTL3_I

1.5 V CLKBUF_SSTL3_II, HCLKBUF_SSTL3_II, TRIBUF_SSTL3_II, BIBUF_SSTL3_II, INBUF_SSTL3_II,

OUTBUF_SSTL3_II

0.75 V CLKBUF_HSTL_I, BIBUF_HSTL_I, HCLKBUF_HSTL_I, INBUF_HSTL_I, OUTBUF_HSTL_I,

TRIBUF_HSTL_I

v5.3

2-19

RTAX-S/SL RadTolerant FPGAs

User I/O Naming Conventions

Due to the complex and flexible nature of the RTAX-S/SL family’s user I/Os, a naming scheme is used to show the details

of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for

differential I/Os (Figure 2-7).

GND

V_CCDA

Corner1

I/O BANK 0

I/O BANK 1

Corner2

GND

_CCI7

GND

_CCI2

V_CCA

GND

V_CCDA

GND

V_CCDA

RTAX-S/SL

_CCI6

V_CCI3

GND

V_CCA

GND

V_CCA

GND

V_CCDA

GND

V_CCDA

Corner4

I/O BANK 5

I/O BANK 4

Corner3

Figure 2-7 • I/O Bank and Dedicated Pin Layout

IOxxXBxFx

Examples:

IO12PB1F1 Is the positive pin of the thirteenth pair of the

first I/O bank (IOB NE). IO12PB1 combined

with IO12NB1 form a differential pair.

For those I/Os that can be employed

either as a user I/O or as a special

function, the following nomenclature

is used:

Pair number in the

bank, starting at 00,

clockwise from IOB NW

P - Positive Pin/ N- Negative Pin

Bank I/D 0 through 7,

clockwise from IOB NW

IOxxXBxFx/special_function_name

IOxxPB1Fx/CLKx This pin can be configured as a clock

input or as a user I/O

Fx refers to an

unimplemented feature

and can be ignored

Figure 2-8 • General Naming Schemes

2-20

v5.3

RTAX-S/SL RadTolerant FPGAs

I/O Standard Electrical Specifications

Table 2-17 • Input Capacitance

Symbol

C_IN

Parameter

Input Capacitance

Input Capacitance on Clock Pin

Conditions

Min.

Max.

Units

V_IN= 0, f =1.0 MHz

C_INCLK

Table 2-18 • I/O Weak Pull-Up/Pull-Down Resistances¹

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

R(Pull up) (kΩ)²R(Pull down) (kΩ)³

I/O Configuration (V_CCI

)

Min.

Max.

Min.

Max.

3.3 V

2.5 V

1.8 V

1.5 V

Notes:

102

1. Min and Max correspond to combinations of process voltage and temperature at military conditions.

2. R(pull up) = (V_CCI– V_OH)/I_OH

3. R(pull down) = V_OL/I_OL

Table 2-19 • I/O Input Rise Time and Fall Time*

Input Buffer

LVTTL

Input Rise/Fall Time (Min)

No Requirement

Input Rise/Fall Time (Max)

50 ns

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI

PCIX

GTL+

HSTL

SSTL2

HSTL3

LVDS

LVPECL

Note: *Input Rise/Fall time applies to all inputs, including clock or data. Inputs have to ramp up/down linearly, in a monotonic way.

Glitches or a plateau may cause double-clocking. They must be avoided. For Output Rise/Fall time, refer to IBIS Models for

extraction.

v5.3

2-21

RTAX-S/SL RadTolerant FPGAs

INBUF

V_trip

PAD

Input High

V_trip

V_CCA

50%

t_DP

(Rising)

t_DP

GND

(Falling)

Figure 2-9 • Input Buffer Delays

OUT Pad

TRIBUF

To AC test loads (shown below)

V_CCA

50%

V_CCA

50%

V_OH

V_trip

50%

GND

V_CCI/V_TT

VTT

Out

V_trip

V_OH

V_trip

Out

V_OL

10%

90%

V_OL

t_PY

V_TT

ENHZ

Out

GND/V_TT

)

DLH

DHL

t_ENLZ

Figure 2-10 • Output Buffer Delays

2-22

v5.3

RTAX-S/SL RadTolerant FPGAs

I/O Module Timing Characteristics

Out

OutReg

EnReg

InReg

CLK

(Routed or

Hardwired)

Figure 2-11 • Timing Model

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_ICLKQ

t_HASYNt_REASYN

t_WASYN

CLR

t_HASYN

t_REASYN

t_CLR

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-12 • Input Register Timing Characteristics

v5.3

2-23

RTAX-S/SL RadTolerant FPGAs

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_OCLKQ

t_HASYNt_REASYN

t_WASYN

CLR

t_HASYN

t_REASYN

t_CLR

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-13 • Output Register Timing Characteristics

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_OCLKQ

t_HASYNt_REASYN

t_WASYN

CLR

t_HASYN

t_REASYN

t_CLR

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-14 • Output Enable Register Timing Characteristics

2-24

v5.3

RTAX-S/SL RadTolerant FPGAs

3.3 V LVTTL

Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL

input buffer and push-pull output buffer.

Table 2-20 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.4

V_OH

Min,V

2.4

I_OL

I_OH

–24

Min,V

Max,V

Min,V

Max,V

–0.3

0.8

2.0

3.6

AC Loadings

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

R=1 k

Test Point

for tristate

Test Point

for t_pd

35 pF for t_pzh/t_pzl

35 pF

_phz/t_plz

5 pF for

Figure 2-15 • AC Test Loads

Table 2-21 • AC Waveforms, Measuring Points, and Capacitive Load

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

3.0

1.40

N/A

* Measuring Point = V_trip

Timing Characteristics

Table 2-22 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVTTL I/O Module Drive Strength = 4 (24 mA) /Low Slew Rate

t_DP

Input buffer

1.85

11.41

0.91

2.17

13.41

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.91

1.07

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

v5.3

2-25

RTAX-S/SL RadTolerant FPGAs

Table 2-22 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C (Continued)

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVTTL I/O Module Drive Strength = 3 (16 mA) / Low Slew Rate

t_DP

Input buffer

1.85

12.04

0.91

2.17

14.16

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.91

1.07

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

LVTTL I/O Module Drive Strength = 2 (12 mA) / Low Slew Rate

t_DP

Input buffer

1.85

13.26

0.91

2.17

15.58

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.91

1.07

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

2-26

v5.3

RTAX-S/SL RadTolerant FPGAs

'Std.' Speed

Table 2-22 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C (Continued)

'–1' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVTTL I/O Module Drive Strength = 1 (8 mA) / Low Slew Rate

t_DP

Input buffer

1.85

15.82

0.91

2.17

18.60

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.91

1.07

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

LVTTL I/O Module Drive Strength = 4 (24 mA) / High Slew Rate

t_DP

Input buffer

1.85

3.51

0.91

2.17

4.12

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

v5.3

2-27

RTAX-S/SL RadTolerant FPGAs

Table 2-22 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C (Continued)

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVTTL I/O Module Drive Strength = 3 (16 mA) / High Slew Rate

t_DP

Input buffer

1.85

3.66

0.91

2.17

4.31

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

LVTTL I/O Module Drive Strength = 2 (12 mA) / High Slew Rate

t_DP

Input buffer

1.85

3.87

0.91

2.17

4.55

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

2-28

v5.3

RTAX-S/SL RadTolerant FPGAs

'Std.' Speed

Table 2-22 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C (Continued)

'–1' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVTTL I/O Module Drive Strength = 1 (8 mA) / High Slew Rate

t_DP

Input buffer

1.85

4.78

0.91

2.17

5.62

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

v5.3

2-29

RTAX-S/SL RadTolerant FPGAs

2.5 V LVCMOS

Low-Voltage Complementary Metal-Oxide Semiconductor for 2.5 V is an extension of the LVCMOS standard (JESD8-5)

used for general-purpose 2.5 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer.

Table 2-23 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.4

V_OH

Min,V

2.0

I_OL

I_OH

–12

Min,V

Max,V

Min,V

Max,V

–0.3

0.7

1.7

3.6

AC Loadings

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

R=1 k

Test Point

for tristate

Test Point

for t_pd

35 pF for t_pzh/t_pzl

35 pF

_phz/t_plz

5 pF for

Figure 2-16 • AC Test Loads

Table 2-24 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V) Measuring Point* (V)

2.5 1.25

_REF(typ) (V)

C_load(pF)

N/A

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-25 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 2.3 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVCMOS25 I/O Module Timing

t_DP

Input buffer

2.13

3.59

0.91

2.51

4.22

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

0.31

0.37

t_PRESET

Asynchronous Preset-to-Q

2-30

v5.3

RTAX-S/SL RadTolerant FPGAs

1.8 V LVCMOS

Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8 V is an extension of the LVCMOS standard (JESD8-5)

used for general-purpose 1.8 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer.

Table 2-26 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.2

V_OH

I_OL

8mA

I_OH

Min,V

Max,V

Min,V

Max,V

Min,V

V_CCI-0.2

–0.3

0.2V_CCI

0.7V_CCI

2.1

–8mA

AC Loadings

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

R=1 k

Test Point

for tristate

Test Point

for t_pd

35 pF for t_pzh/t_pzl

35 pF

_phz/t_plz

5 pF for

Figure 2-17 • AC Test Loads

Table 2-27 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

1.8

0.5V_CCI

N/A

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-28 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 1.7 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVCMOS18 I/O Module Timing

t_DP

Input buffer

3.57

4.97

0.91

4.19

5.85

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

0.31

0.37

t_PRESET

Asynchronous Preset-to-Q

v5.3

2-31

RTAX-S/SL RadTolerant FPGAs

1.5 V LVCMOS (JESD8-11)

Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5 V is an extension of the LVCMOS standard (JESD8-5)

used for general-purpose 1.5 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer.

Table 2-29 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.4

V_OH

I_OL

8mA

I_OH

Min,V

Max,V

Min,V

Max,V

Min,V

V_CCI-0.4

–0.5

0.35V_CCI

0.65V_CCI

1.95

–8mA

AC Loadings

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

R=1 k

Test Point

for tristate

Test Point

for t_pd

35 pF for t_pzh/t_pzl

35 pF

_phz/t_plz

5 pF for

Figure 2-18 • AC Test Loads

Table 2-30 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V) Measuring Point* (V)

1.5 0.5V_CCI

_REF(typ) (V)

C_load(pF)

N/A

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-31 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 1.4 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVCMOS15 I/O Module Timing

t_DP

Input buffer

3.93

6.60

0.91

4.62

7.76

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

0.31

0.37

t_PRESET

Asynchronous Preset-to-Q

2-32

v5.3

RTAX-S/SL RadTolerant FPGAs

3.3 V PCI

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI bus applications. It

uses an LVTTL input buffer and a push-pull output buffer. The input and output buffers are 5V tolerant with the aid of

external components. The RTAX-S/SL 3.3 V PCI buffer is compliant with the PCI Local Bus Specification Rev. 2.1.

Table 2-32 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

I_OH

Min,V

Max,V

Min,V

Max,V

Min,V

PCI

–0.5

0.3V_CCI

0.5V_CCI

V_CCI+0.5

(per PCI specification)

AC Loadings

Per PCI Specification except for tristate. Actel loading for tristate is in the figure below.

R to V

R to GND for t_ph

for t_pl

CCI

R = 25

Test point for data

R =1 k

Test Point

R to V_CCIfor t_plz/t_pzl

R to GND for t_phz/t_pzh

for tristate

10 pF

35 pF for t_pzl/t_pzh

5 pF for t_phz/t_plz

GND

Figure 2-19 • AC Test Loads

Table 2-33 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

(Per PCI Spec)

N/A

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-34 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

3.3 V PCI I/O Module Timing

t_DP

Input buffer

1.72

2.02

t_PY

Output buffer

2.25

0.91

2.64

1.07

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

0.31

0.37

t_PRESET

Asynchronous Preset-to-Q

v5.3

2-33

RTAX-S/SL RadTolerant FPGAs

Voltage-Referenced I/O Standards

GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential amplifier input buffer

and an open drain output buffer. The V_CCIpin should be connected to 2.5 V or 3.3 V. Note that 2.5 V GTL+ is not

supported across the full military temperature range.

Table 2-35 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.6

V_OH

Min,V

I_OL

I_OH

Min,V

Max,V

_REF-0.1

Min,V

Max,V

N/A

V_REF+0.1

N/A

AC Loadings

V_TT

Test Point

10 pF

Figure 2-20 • AC Test Loads

Table 2-36 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

V_REF-0.2

Input High (V)

Measuring Point* (V)

V_REF(typ) (V)

C_load(pF)

V_REF+0.2

V_REF

1.0

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-37 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

3.3 V GTL+ I/O Module Timing

t_DP

Input buffer

2.01

1.26

0.91

2.36

1.49

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

0.31

0.37

t_PRESET

Asynchronous Preset-to-Q

2-34

v5.3

RTAX-S/SL RadTolerant FPGAs

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). The RTAX-S/SL devices

support Class I. This requires a differential amplifier input buffer and a push-pull output buffer.

Table 2-38 • DC Input and Output Levels

V_IL

V_IH

V_OL

Max,V

0.4

V_OH

I_OL

I_OH

–8

Min,V

Max,V

Min,V

Max,V

Min,V

V_CC-0.4

–0.3

V_REF-0.1

V_REF+0.1

3.6

AC Loadings

V_TT

Test Point

20 pF

Figure 2-21 • AC Test Loads

Table 2-39 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

V_REF-0.5

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

V_REF+0.5

V_REF

0.75

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-40 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 1.4 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

1.5 V HSTL Class I I/O Module Timing

t_DP

Input buffer

2.12

5.35

0.91

2.49

6.29

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

v5.3

2-35

RTAX-S/SL RadTolerant FPGAs

SSTL2

Stub Series Terminated Logic for 2.5 V is a general-purpose 2.5 V memory bus standard (JESD8-9). The RTAX-S/SL

devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output

buffer.

Class I

Table 2-41 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

7.6

I_OH

–7.6

Min,V

Max,V

_REF-0.2

Min,V

Max,V

V_REF-0.57

Min,V

–0.3

V_REF+0.2

3.6

V_REF+0.57

AC Loadings

V_TT

Test Point

30 pF

Figure 2-22 • AC Test Loads

Table 2-42 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

V_REF-0.75

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

V_REF+0.75

V_REF

1.25

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-43 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 2.3 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

2.5 V SSTL2 Class I I/O Module Timing

t_DP

Input buffer

2.14

2.61

0.91

2.52

3.07

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

2-36

v5.3

RTAX-S/SL RadTolerant FPGAs

Class II

Table 2-44 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

15.2

I_OH

Min,V

Max,V

Min,V

Max,V

V_REF-0.8

Min,V

V_REF+0.8

–0.3

V_REF-0.2

V_REF+0.2

3.6

–15.2

AC Loadings

V_TT

Test Point

30 pF

Figure 2-23 • AC Test Loads

Table 2-45 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

V_REF-0.75

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

V_REF+0.75

V_REF

1.25

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-46 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 2.3 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

2.5 V SSTL2 Class II I/O Module Timing

t_DP

Input buffer

2.22

2.61

0.91

2.61

3.07

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

v5.3

2-37

RTAX-S/SL RadTolerant FPGAs

SSTL3

Stub Series Terminated Logic for 3.3 V is a general-purpose 3.3 V memory bus standard (JESD8-8). The RTAX-S/SL

devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output

buffer.

Class I

Table 2-47 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

I_OH

–8

Min,V

Max,V

_REF-0.2

Min,V

Max,V

V_REF-0.6

Min,V

V_REF+0.6

–0.3

V_REF+0.2

3.6

AC Loadings

V_TT

Test Point

30 pF

Figure 2-24 • AC Test Loads

Table 2-48 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

V_REF-1.0

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

V_REF+1.0

V_REF

1.50

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-49 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

3.3 V SSTL3 Class I I/O Module Timing

t_DP

Input buffer

2.09

2.55

0.91

2.46

2.99

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

2-38

v5.3

RTAX-S/SL RadTolerant FPGAs

Class II

Table 2-50 • DC Input and Output Levels

V_IL

V_IH

V_OL

V_OH

I_OL

I_OH

–16

Min,V

Max,V

Min,V

Max,V

V_REF-0.8

Min,V

V_REF+0.8

–0.3

V_REF-0.2

V_REF+0.2

3.6

AC Loadings

V_TT

Test Point

30 pF

Figure 2-25 • AC Test Loads

Table 2-51 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

_REF-1.0

Input High (V)

Measuring Point* (V)

_REF(typ) (V)

C_load(pF)

V_REF+1.0

V_REF

1.50

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-52 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

3.3 V SSTL3 Class II I/O Module Timing

t_DP

Input buffer

2.17

2.55

0.91

2.55

2.99

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.31

0.37

t_PRESET

v5.3

2-39

RTAX-S/SL RadTolerant FPGAs

Differential Standards

Physical Implementation

Implementing differential I/O standards requires the

configuration of a pair of external I/O pads, resulting in a

single internal signal. To facilitate construction of the

differential pair, a single I/O cluster contains the

resources for a pair of I/Os. Configuration of the I/O

Cluster as a differential pair is handled by Actel's

(OutReg), and Enable Register (EnReg). However, there is

no support for bidirectional I/Os or tristates with these

standards.

LVDS

Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a

high-speed differential I/O standard. It requires that one

data bit is carried through two signal lines, so two pins

are needed. It also requires an external resistor

termination. The voltage swing between these two

signal lines is approximately 350 mV.

Designer software when the user instantiates

differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the

embedded Input Register (InReg), Output Register

FPGA

OUTBUF_LVDS

165 Ω

ZO = 50 Ω

INBUF_LVDS

–

140 Ω

ZO = 50 Ω

100 Ω

165 Ω

Figure 2-26 • LVDS Circuit

The LVDS circuit consists of

connected to a terminated receiver through a constant-

impedance transmission line. The receiver is a wide-

differential driver

current of 3.5 mA. When this current flows through a

100 Ω termination resistor on the receiver side, a voltage

swing of 350 mV is developed across the resistor. The

direction of the current flow is controlled by the data fed

to the driver.

common-mode-range

differential

amplifier.

The

common-mode range is from 0.2 V to 2.2 V for a

differential input with 400 mV swing.

An external-resistor network (three resistors) is needed

to reduce the voltage swing to about 350 mV. Therefore,

four external resistors are required, three for the driver

and one for the receiver.

To implement the driver for the LVDS circuit, drivers from

two adjacent I/O cells are used to generate the

differential signals (Note that the driver is not a current-

mode driver). This driver provides a nominal constant

Table 2-53 • DC Input and Output Levels

DC Parameter

Description

Min.

2.375

1.25

–

Typ.

2.5

–

Max.

2.625

–

Units

V_CCI

Supply voltage

V_OH

Output high voltage

Output low voltage

V_OL

–

1.25

450

V_ODIFF

Differential output voltage

Output common mode voltage

Input common mode voltage

250

350

1.25

V_OCM

1.125

0.2

1.375

2.2

V_ICM

Notes:

1. +/- 5%

2. Differential input voltage = 400 mV.

2-40

v5.3

RTAX-S/SL RadTolerant FPGAs

AC Loadings

For AC test loads, see the above LVDS circuit.

Table 2-54 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

1.2-0.125

Input High (V)

Measuring Point* (V)

_load(pF)

1.2+0.125

1.2

N/A

Note: *Measuring Point = V_trip

Timing Characteristics

Table 2-55 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 2.3 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVDS I/O Module Timing

t_DP

Input buffer

2.00

2.54

0.91

2.35

2.99

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

0.31

0.37

t_PRESET

Asynchronous Preset-to-Q

v5.3

2-41

RTAX-S/SL RadTolerant FPGAs

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit

is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The

voltage swing between these two signal lines is approximately 850 mV.

FPGA

100 Ω

ZO = 50 Ω

187 Ω

ZO = 50 Ω

OUTBUF_LVPECL

–

INBUF_LVPECL

100 Ω

Figure 2-27 • LVPECL Circuit

The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the

receiver. The values for the three driver resistors are different from that of LVDS, since the output voltage levels are

different. Please note that the V_OHlevels are 200 mV below the standard LVPECL levels.

Table 2-56 • DC Input and Output Levels

Min.

Typ.

Max.

DC Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

V_CCI

3.3

3.6

V_OH

1.8

0.96

1.49

0.86

0.3

2.11

1.27

1.92

1.06

1.49

0.86

0.3

2.28

1.43

2.13

1.3

2.41

1.57

V_OL

V_IH

2.72

1.49

0.86

0.3

2.72

V_IL

2.125

Differential Input Voltage

AC Loadings

For AC test loads, See the above LVPECL circuit.

Table 2-57 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

1.6-0.3

Input High (V)

Measuring Point* (V)

_load(pF)

1.6+0.3

1.6

N/A

Note: *Measuring Point = V_trip

2-42

v5.3

RTAX-S/SL RadTolerant FPGAs

Timing Characteristics

Table 2-58 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

LVPECL I/O Module Timing

t_DP

Input buffer

1.83

2.45

0.91

2.15

2.88

1.07

t_PY

Output buffer

t_ICLKQ

t_OCLKQ

t_SUD

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and the I/O enable register

Data input setup

0.31

0.35

0.00

0.39

0.37

0.17

0.00

0.37

0.41

0.00

0.39

0.37

0.21

0.00

t_SUE

Enable input setup

t_HD

Data input hold

t_HE

Enable input hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock pulse width High to Low

Clock pulse width Low to High

Asynchronous pulse width

Asynchronous recovery time

Asynchronous removal time

Asynchronous Clear-to-Q

0.31

0.37

t_PRESET

Asynchronous Preset-to-Q

v5.3

2-43

RTAX-S/SL RadTolerant FPGAs

Module Specifications

•

Inverter (DB input) can be used to drive a

complement signal of any of the inputs to the

C-cell.

C-Cell

Introduction

A carry input and a carry output. The carry input

signal of the C-cell is the carry output from the

C-cell directly to the north.

The C-cell is one of the two logic module types in the

RTAX-S/SL architecture. It is the combinatorial logic

resource in the RTAX-S/SL device. The RTAX-S/SL

architecture implements a new Combinatorial Cell that is

an extension of the C-cell implemented in the A54SX-A

family. The main enhancement of the new C-cell is the

addition of carry-chain logic.

•

Carry connect for carry-chain logic with a signal

propagation time of less than 0.1 ns.

A hardwired connection (direct connect) to the

adjacent R-cell (Register Cell) for all C-cells on the

The C-cell can be used in a carry-chain mode to construct

arithmetic functions. If carry-chain logic is not required,

it can be disabled.

east side of

propagation time of less than 0.1 ns.

a SuperCluster with a signal

This layout of the C-cell (and the C-cell Cluster) enables

the implementation of over 4,000 functions of up to five

bits. For example, two C-cells can be used together to

implement a four-input XOR function in a single cell

delay.

The C-cell features the following (Figure 2-28):

•

Eight-input MUX (data: D0-D3, select: A0, A1, B0,

B1). User signals can be routed to any one of these

inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0,

B1) can be tied to one of the four routed clocks

(CLKE/F/G/H).

The carry-chain configuration is handled automatically

for the user with the extensive Actel macro library. Refer

to the Actel Antifuse Macro Library Guide for a complete

listing of available RTAX-S/SL macros.

FCI

CFN

D1 D3 B0 B1

0 1

D0 D2

FCO

Figure 2-28 • C-Cell

2-44

v5.3

RTAX-S/SL RadTolerant FPGAs

Timing Model and Waveforms

V_CCA

50%

A, B, D, FCI

GND

V_CCA

50%

Y, FCO

GND

t_PD, t_PDC

V_CCA

Y, FCO

50%

t_PD, t_PDC

50%

GND

t_PD, t_PDC

Figure 2-29 • C-Cell Timing Model and Waveforms

Timing Characteristics

Table 2-59 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

C-Cell Propagation Delays

t_PD

Any input to output

0.95

0.70

1.49

0.76

0.10

1.11

0.82

1.75

0.90

0.12

t_PDC

t_PDB

t_CCY

t_CC

Any input to carry chain output (FCO)

Any input thorough DB when 1 input is used

Input carry chain (FCI) to Y

Input carry chain (FCI) to carry chain output (FCO)

v5.3

2-45

RTAX-S/SL RadTolerant FPGAs

Carry-Chain Logic

The RTAX-S/SL dedicated carry-chain logic offers a very

compact solution for implementing arithmetic functions

without sacrificing performance.

C-cell pair, drives the FCI input of the C-cell pair

immediately below it (Figure 1-5 on page 1-3 and

Figure 2-31 on page 2-47).

To implement the carry-chain logic, two C-cells in a

Cluster are connected together so the FCO (i.e., carry

out) for the two bits is generated in a Carry Look-ahead

scheme to achieve minimum propagation delay from the

FCI (i.e., carry in) into the two-bit Cluster. The two-bit

carry logic is shown in Figure 2-30.

The carry-chain logic is selected via the CFN input. When

carry logic is not required, this signal is deasserted to

save power. Again, this configuration is handled

automatically for the user through the Actel macro

library.

The signal propagation delay between two C-cells in the

carry-chain sequence is 0.1 ns.

The FCI of one C-cell pair is driven by the FCO of the

C-cell pair immediately above it. Similarly, the FCO of one

DCOUT

Figure 2-30 • RTAX-S/SL Two-Bit Carry Logic

2-46

v5.3

RTAX-S/SL RadTolerant FPGAs

FCI₁

R-cell1

DCIN

C-cell2

DCOUT

C-cell1

FCO₂

FCI₃

DCOUT

DCIN

FCO₄

FCI₅

n-2

Clusters

FCI_(2n-1)

R-celln

CDIN

C-cell

(2n-1)

C-cell2n

DCOUT

FCO_2n

Note: The carry-chain sequence can end on either C-cell.

Figure 2-31 • Carry-Chain Sequencing of C-Cells

Timing Characteristics

Refer to the C-cell timing characteristics in Table 2-59 on page 2-45 for more information on carry-chain timing.

v5.3

2-47

RTAX-S/SL RadTolerant FPGAs

R-Cell

•

Clock can be driven by any of the following (CKP

selects clock polarity):

Introduction

The R-cell, the sequential logic resource of the RTAX-S/SL

devices, is the second logic module type in the RTAX-S/SL

family architecture. The RTAX-S/SL R-cell is an enhanced

version of the A54SX-A R-cell. It includes additional clock

inputs for all eight global resources of the RTAX-S/SL

architecture as well as global presets and clears (Figure 2-

32).

–

One of the four high performance hardwired

fast clocks (HCLKs)

–

One of the four routed clocks (CLKs)

User signals

Global power-on clear (GCLR) and preset (GPSET),

which drive each flip-flop on a chip-wide basis.

The main features of the R-cell include the following:

–

When the Global Set Fuse option in the

Designer software is unchecked (by default),

GCLR = 0 and GPSET =1 at device power-up.

When the option is checked, GCLR = 1 and

GPSET= 0. Both pins are pulled HIGH when the

device is in user mode.

•

Direct connection to the adjacent logic module

through the hardwired connection DCIN. DCIN is

driven by the DCOUT of an adjacent C-cell via the

Direct-Connect routing resource, providing

connection with less than 0.1 ns of routing delay.

•

The R-cell can be used as a standalone flip-flop. It

can be driven by any C-cell or I/O modules through

the regular routing structure (using DIN as a

routable data input). This gives the option of

using the R-cell as a 2:1 MUXed flip-flop as well.

•

S0, S1, PSET, and CLR can be driven by routed

clocks CLKE/F/G/H or user signals.

DIN and S1 can be driven by user signals.

As with the C-cell, the configuration of the R-cell to

perform various functions is handled automatically for

the user through Actel's extensive macro library (please

see the Actel Macro Library Guide for a complete listing

of available RTAX-S/SL macros).

•

Provision of data enable-input (S0).

Independent active low asynchronous clear (CLR).

Independent active low asynchronous preset

(PSET). If both CLR and PSET are low, CLR has

higher priority.

CKP

DIN (user signals)

DCIN

SEU

Enhanced

D-FF

HCLKA/B/C/D

CLKE/F/G/H

Internal Logic

CKS

Figure 2-32 • R-Cell

2-48

v5.3

RTAX-S/SL RadTolerant FPGAs

SEU Hardened D Flip-Flop (DFF)

In order to meet the stringent SEU requirements of a LET_TH

greater than 37 MeV-cm²/mg, the internal design of the

R-cell was modified without changing the functionality of

the cell. Figure 2-33 illustrates a simplified representation

of how the D flip-flop in the SuperCluster is implemented in

the RTAX-S/SL architecture. The flip-flop consists of a master

and a slave latch gated by opposite edges of the clock. Each

latch is constructed by feeding back the output to the input

stage. The potential problem in a space environment is that

either of the latches can change state when hit by a particle

with enough energy.

the outputs of the other two latches. If one of the three

latches is struck by an ion and starts to change state, the

voting with the other two latches prevents the change

from feeding back and permanently latching. Care was

taken in the layout to ensure that a single ion strike

could not affect more than one latch. Figure 2-35 on

page 2-50 is a simplified schematic of the test circuitry

that has been added to test the functionality of all the

components of the flip-flop. The inputs to each of the

three latches are independently controllable, so the

voting circuitry in the asynchronous self-correcting

feedback paths can be tested exhaustively. This testing is

performed on an unprogrammed array during wafer

sort, final test, and post-burn-in test. This test circuitry

cannot be used to test the flip-flops once the device has

been programmed.

To achieve the SEU requirements, the D flip-flop in the

RTAX-S/SL R-cell is enhanced (Figure 2-34). Both the

master and slave "latches" are actually implemented

with three latches. The asynchronous self-correcting

feedback paths of each of the three latches is voted with

CLK

Figure 2-33 • RTAX-S/SL R-cell Implementation of D Flip-Flop

CLK

Voter

Gate

CLK

Figure 2-34 • RTAX-S/SL R-cell Implementation of D Flip-Flop Using Voter Gate Logic

v5.3

2-49

RTAX-S/SL RadTolerant FPGAs

Tst1

Tst2

Tst3

Voter

Gate

CLK

Test

Circuitry

Figure 2-35 • RTAX-S/SL R-Cell Implementation – Test Circuitry

Timing Models and Waveforms

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_RCO

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-36 • R-Cell Delays

2-50

v5.3

RTAX-S/SL RadTolerant FPGAs

Timing Characteristics

Table 2-60 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

R-Cell Propagation Delays

t_RCO

Sequential Clock to Q

0.96

0.63

0.76

1.12

0.74

0.89

t_CLR

Asynchronous Clear to Q

Asynchronous Preset to Q

FF Data input setup

t_PRESET

t_SUD

0.21

0.00

0.48

0.00

0.36

0.25

0.00

0.48

0.00

0.36

t_SUE

FF Enable input setup

t_HD

FF Data Hold

t_HE

FF Enable Hold time

t_WASYN

t_REASYN

t_HASYN

t_CPWHL

t_CPWLH

Asynchronous Pulse width

Asynchronous Recovery time

Asynchronous Removal time

Clock pulse width high to low

Clock pulse width low to high

Buffer Module

Introduction

An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3).

When a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has

been added to the RTAX-S/SL architecture to avoid logic duplication resulting from the hard fanout constraints. The

router utilizes this logic resource to save area and reduce loading and delays on medium-to-high-fanout nets.

Timing Models and Waveforms

V_CCA

50%

GND

OUT

V_CCA

50%

OUT

GND

Figure 2-37 • Buffer Module Timing Model

t_BFPD

Figure 2-38 • Buffer Module Waveform

Timing Characteristics

Table 2-61 • Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C

'–1' Speed

'Std.' Speed

Min. Max.

0.20

Parameter

Description

Min.

Max.

Units

t_BFPD

Any input to output Y

0.17

v5.3

2-51

RTAX-S/SL RadTolerant FPGAs

Routing Specifications

Routing Resources

The routing structure found in RTAX-S/SL devices enables

any logic module to be connected to any other logic

module while retaining high performance. There are

multiple paths and routing resources that can be used to

route one logic module to another, both within a

SuperCluster and elsewhere on the chip.

DirectConnect

DirectConnects provide

high-speed connection

between an R-cell and its adjacent C-cell (Figure 2-39).

This connection can be made from DCOUT of the C-cell

to DCIN of the R-cell by configuring of the S1 line of the

R-cell. This provides a connection that does not require

an antifuse and has a delay of less than 0.1 ns.

There are four primary types of routing within the RTAX-S/

SL architecture: DirectConnect, CarryConnect, FastConnect

and Vertical and Horizontal Routing.

Figure 2-39 • DirectConnect and CarryConnect

then be routed through a single antifuse connection to

drive the inputs of logic modules either within one

SuperCluster or in the SuperCluster immediately below

it.

CarryConnect

CarryConnects are used to build carry chains for

arithmetic functions (Figure 2-39). The FCO output of the

right C-cell of a two-C-cell Cluster drives the FCI input of

the left C-cell in the two-C-cell Cluster immediately

below it. This pattern continues down both sides of each

SuperCluster column.

Vertical and Horizontal Routing

Vertical and Horizontal Tracks provide both local and

long distance routing (Figure 2-41 on page 2-53). These

tracks are composed of both short-distance, segmented

routing and across-chip routing tracks (segmented at

core tile boundaries). The short-distance, segmented

routing resources can be concatenated through antifuse

connections to build longer routing tracks.

Similar to the DirectConnects, CarryConnects can be built

without an antifuse connection. This connection has a

delay of less than 0.1 ns from the FCO of one two-C-cell

Cluster to the FCI of the two-C-cell Cluster immediately

below it (see the "Carry-Chain Logic" on page 2-46 for

more information).

These short-distance routing tracks can be used within

and between SuperClusters or between modules of non-

adjacent SuperClusters. They can be connected to the

Output Tracks and to any logic module input (R-cell,

C-cell, Buffer, and TX module).

FastConnect

For high-speed routing of logic signals, FastConnects can

be used to build a short distance connection using a

single antifuse (Figure 2-40 on page 2-53). FastConnects

provide a maximum delay of 0.4 ns. The outputs of each

logic module connect directly to the Output Tracks

within a SuperCluster. Signals on the Output Tracks can

2-52

v5.3

RTAX-S/SL RadTolerant FPGAs

The across-chip horizontal and vertical routing provides

long-distance, routing resources. These resources

interface with the rest of the routing structures through

the RX and TX modules (Figure 2-41 on page 2-53). The

RX module is used to drive signals from the across-chip

horizontal and vertical routing to the Output Tracks

within the SuperCluster. The TX module is used to drive

vertical and horizontal across-chip routing from either

short-distance horizontal tracks or from Output Tracks.

The TX module can also be used to drive signals from

vertical across-chip tracks to horizontal across-chip tracks

and vice versa.

Figure 2-40 • FastConnect Routing

Figure 2-41 • Horizontal and Vertical Tracks

v5.3

2-53

RTAX-S/SL RadTolerant FPGAs

Timing Characteristics

Table 2-62 • RTAX250S/SL (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

Min. Max.

'Std.' Speed

Parameter

Description

Min.

Max.

Unit

Predicted Routing Delays

t_DC

Direct connect

Fast connect F01

Fanout 1

0.08

0.24

0.66

0.84

1.07

1.38

1.45

2.08

2.26

2.44

2.87

3.3

0.07

0.29

0.77

0.99

1.25

1.62

1.7

t_FC

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD9

t_RD10

Fanout 2

Fanout 3

Fanout 4

Fanout 5

Fanout 6

2.44

2.66

2.87

3.37

3.88

Fanout 7

Fanout 8

Fanout 9

Fanout 10

Table 2-63 • RTAX1000S/SL (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Min. Max.

Parameter

Description

Min.

Max.

Unit

Predicted Routing Delays

t_DC

Direct connect

Fast connect F01

Fanout 1

0.08

0.24

0.66

0.84

1.07

1.38

1.45

2.08

2.26

2.44

2.87

3.3

0.07

0.29

0.77

0.99

1.25

1.62

1.7

t_FC

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD9

t_RD10

Fanout 2

Fanout 3

Fanout 4

Fanout 5

Fanout 6

2.44

2.66

2.87

3.37

3.88

Fanout 7

Fanout 8

Fanout 9

Fanout 10

2-54

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-64 • RTAX2000S/SL (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Min. Max. Min. Max.

Parameter

Description

Unit

Predicted Routing Delays

t_DC

Direct connect

Fast connect F01

0.08

0.24

0.66

0.84

1.07

1.38

1.45

2.08

2.26

2.44

2.87

3.30

0.07

0.29

0.77

0.99

1.25

1.62

1.70

2.44

2.66

2.87

3.37

3.88

t_FC

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD9

t_RD10

Fanout 1

Fanout 2

Fanout 3

Fanout 4

Fanout 5

Fanout 6

Fanout 7

Fanout 8

Fanout 9

Fanout 10

Table 2-65 • RTAX4000S (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'Std.' Speed

Parameter

Description

Min.

Max.

Unit

Predicted Routing Delays

t_DC

Direct connect

0.07

0.29

0.77

0.99

1.25

1.62

1.7

t_FC

Fast connect F01

Fanout 1

Fanout 2

Fanout 3

Fanout 4

Fanout 5

Fanout 6

Fanout 7

Fanout 8

Fanout 9

Fanout 10

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD9

t_RD10

2.44

2.66

2.87

3.37

3.88

v5.3

2-55

RTAX-S/SL RadTolerant FPGAs

Global Resources

One of the most important aspects of any FPGA

architecture is its global resources or clocks. The RTAX-S/

SL family provides the user with flexible and easy-to-use

global resources, without the limitations normally found

in other FPGA architectures. In addition, these global

resources have been hardened to improve SEU

performance.

Hardwired Clocks

The hardwired (HCLK) is a low-skew network that can

directly drive the clock inputs of all sequential modules

(R-cells, I/O registers and embedded RAM/FIFOs) in the

device with no antifuse in the path. All four HCLKs are

available everywhere on the chip.

The RTAX-S/SL architecture contains two types of global

resources, the HCLK (hardwired clock) and CLK (routed

clock). Every RTAX-S/SL device is provided with four

HCLKs and four CLKs for a total of eight clocks,

regardless of device density.

Timing Characteristics

Table 2-66 • RTAX250S/SL (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Min. Max. Min. Max.

Parameter

t_HCKL

Description

Input Low to High

Input High to Low

Units

2.76

2.94

3.24

3.46

t_HCKH

Table 2-67 • RTAX250S/SL Worst-Case MPW (V_CCA= 1.575 V, V_CCI= 3.6 V, T_J= 125°C)

'–1' Speed

'Std.' Speed

Parameter

t_HPWH

Description

Minimum Pulse width High

Minimum Pulse width Low

Maximum frequency

Min.

0.77

0.26

Max.

Min.

0.77

0.26

Max.

Units

t_HPWL

f_HMAX

649

MHz

Note: *f_HMAX= 1000/(2*(MAX(t_HPWH,t_HPWL)))

Table 2-68 • RTAX1000S/SL (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Min. Max. Min. Max.

Parameter

t_HCKL

Description

Input Low to High

Input High to Low

Units

3.65

3.48

4.29

4.09

t_HCKH

Table 2-69 • RTAX1000S/SL Worst-Case MPW (V_CCA= 1.575 V, V_CCI= 3.6 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Max.

Parameter

t_HPWH

Description

Minimum Pulse width High

Minimum Pulse width Low

Maximum frequency

Min.

0.86

0.31

Min.

0.86

0.31

Max.

Units

t_HPWL

f_HMAX

581

MHz

Note: *f_HMAX= 1000/(2*(MAX(t_HPWH,t_HPWL)))

2-56

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-70 • RTAX2000S/SL (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Min. Max. Min. Max.

Parameter

t_HCKL

Description

Input Low to High

Input High to Low

Units

3.65

3.48

4.29

4.09

t_HCKH

Table 2-71 • RTAX2000S/SL Worst-Case MPW (V_CCA= 1.575 V, V_CCI= 3.6 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Max.

Parameter

t_HPWH

Description

Minimum Pulse width High

Minimum Pulse width Low

Maximum frequency

Min.

0.77

0.26

Min.

0.77

0.26

Max.

Units

t_HPWL

f_HMAX

649

MHz

Note: *f_HMAX= 1000/(2*(MAX(t_HPWH,t_HPWL)))

Table 2-72 • RTAX4000S (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'Std.' Speed

Parameter

t_HCKL

Description

Input Low to High

Input High to Low

Min.

Max.

4.37

Units

t_HCKH

4.16

Table 2-73 • RTAX4000S Worst-Case MPW (V_CCA= 1.575 V, V_CCI= 3.6 V, T_J= 125°C)

'Std.' Speed

Parameter

t_HPWH

Description

Minimum Pulse width High

Minimum Pulse width Low

Maximum frequency

Min.

TBD

Max.

Units

t_HPWL

TBD

f_HMAX

TBD

MHz

Note: *f_HMAX= 1000/(2*(MAX(t_HPWH,t_HPWL)))

v5.3

2-57

RTAX-S/SL RadTolerant FPGAs

Routed Clocks

The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in the device

(logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0 (Enable), S1, PSET, and CLR

input of a register (R-cells and I/O registers) as well as any of the inputs of any C-cell in the device. This allows CLKs to

be used not only as clocks, but also for other global signals or high fanout nets. All four CLKs are available everywhere

on the chip.

Timing Characteristics

Table 2-74 • RTAX250S/SL (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

Min. Max.

'Std.' Speed

Min. Max.

Parameter

t_RCKL

Description

Input Low to High

Units

2.78

2.92

1.40

1.81

3.26

3.43

1.65

2.13

t_RCKH

Input High to Low

t_RCKSW

Maximum skew – 16 Loads

Maximum skew – 24 Loads

Table 2-75 • RTAX250S/SL Worst-Case MPW (V_CCA= 1.575 V, V_CCI= 3.6 V, T_J= 125°C)

'–1' Speed

'Std.' Speed

Parameter

t_RPWH

Description

Minimum Pulse width High

Minimum Pulse width Low

Maximum frequency

Min.

0.79

0.27

Max.

Min.

0.79

0.27

Max.

Units

t_RPWL

f_RMAX

633

MHz

Note: *f_RMAX= 1000/(2*(MAX(t_RPWH,t_RPWL)))

Table 2-76 • RTAX1000S/SL (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Min. Max. Min. Max.

Parameter

t_RCKL

Description

Input Low to High

Units

3.71

3.54

1.39

1.80

1.87

4.37

4.16

1.64

2.12

2.20

t_RCKH

Input High to Low

t_RCKSW

Maximum skew – 16 Loads

Maximum skew – 24 Loads

Maximum skew – 36 Loads

Table 2-77 • RTAX1000S/SL Worst-Case MPW (V_CCA= 1.575 V, V_CCI= 3.6 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Max.

Parameter

t_RPWH

Description

Minimum Pulse width High

Minimum Pulse width Low

Maximum frequency

Min.

1.04

0.33

Min.

1.04

0.33

Max.

Units

t_RPWL

f_RMAX

481

MHz

Note: *f_RMAX= 1000/(2*(MAX(t_RPWH,t_RPWL)))

2-58

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-78 • RTAX2000S/SL (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Min. Max. Min. Max.

Parameter

t_RCKL

Description

Input Low to High

Units

3.71

3.54

1.39

1.80

2.12

4.37

4.16

1.64

2.12

2.49

t_RCKH

Input High to Low

t_RCKSW

Maximum skew – 16 Loads

Maximum skew – 24 Loads

Maximum skew – 36 Loads

Table 2-79 • RTAX2000S/SL Worst-Case MPW (V_CCA= 1.575 V, V_CCI= 3.6 V, T_J= 125°C)

'–1' Speed 'Std.' Speed

Max.

Parameter

t_RPWH

Description

Minimum Pulse width High

Minimum Pulse width Low

Maximum frequency

Min.

0.79

0.27

Min.

Max.

Units

t_RPWL

f_RMAX

633

MHz

Note: *f_RMAX= 1000/(2*(MAX(t_RPWH,t_RPWL)))

Table 2-80 • RTAX4000S (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'Std.' Speed

Parameter

t_RCKL

Description

Input Low to High

Min.

Max.

6.41

6.19

1.65

2.11

2.16

Units

t_RCKH

Input High to Low

t_RCKSW

Maximum skew – 16 Loads

Maximum skew – 24 Loads

Maximum skew – 36 Loads

Table 2-81 • RTAX4000S Worst-Case MPW (V_CCA= 1.575 V, V_CCI= 3.6 V, T_J= 125°C)

'Std.' Speed

Parameter

t_RPWH

Description

Minimum Pulse width High

Minimum Pulse width Low

Maximum frequency

Min.

TBD

Max.

Units

t_RPWL

TBD

f_RMAX

TBD

MHz

Note: *f_RMAX= 1000/(2*(MAX(t_RPWH,t_RPWL)))

v5.3

2-59

RTAX-S/SL RadTolerant FPGAs

Global Resource Distribution

At the root of each global resource is a ClockDistBuffer

(CDB). There are two groups of four CDBs for every device.

One group, located at the center of the north edge (in the

I/O ring) of the chip, sources the four HCLKs. The second

group, located at the center of the south edge (again in the

I/O ring), sources the four CLKs (Figure 2-42).

Regardless of the type of global resource, HCLK or CLK,

each of the eight resources reach the ClockTileDist (CTD)

Cluster located at the center of every core tile with zero

skew. From the ClockTileDist Cluster, all four HCLKs and four

CLKs are distributed through the core tile (Figure 2-43).

P N

CDB Cluster

HCLKA HCLKB HCLKC HCLKD

CLKE

CLKF

CLKG

CLKH

CDB Cluster

P N

Figure 2-42 • ClockDistBuffer Group

HCLK

CDB Cluster

CLK

ClockTileDist Cluster

CDB Cluster

Figure 2-43 • Example of HCLK and CLK Distributions on the RTAX2000S/SL

2-60

v5.3

RTAX-S/SL RadTolerant FPGAs

The ClockTileDist Cluster contains an HCLKMux (HM)

module for each of the four HCLK trees and a CLKMux

(CM) module for each of the CLK trees. The HCLK

branches then propagate horizontally through the

middle of the core tile to HCLKColDist (HD) modules in

every SuperCluster column. The CLK branches propagate

vertically through the center of the core tile to

CLKRowDist (RD) modules in every SuperCluster row.

Together, the HCLK and CLK branches provide for a low-

skew global fanout within the core tile (Figure 2-44 and

Figure 2-45).

Figure 2-44 • CTD, CD, and HD Module Layout

Figure 2-45 • HCLK and CLK Distribution within a Core Tile

v5.3

2-61

RTAX-S/SL RadTolerant FPGAs

The HM and CM modules can select between:

Global Resource Access Macros

•

The HCLK or CLK source

Global resources can be driven by one of three sources:

external pad(s) or an internal net. These connections can

be made by using one of two types of macros: CLKBUF

and CLKINT.

A local signal routed on generic routing resources

This allows each core tile to have eight clocks

independent of the other core tiles in the device.

Both HCLK and CLK are segmentable, meaning that

individual branches of the global resource can be used

independently.

CLKBUF and HCLKBUF

CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from

external pads. These macros can be used either

generically or with the specific I/O standard desired

(e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.)

(Figure 2-46).

Like the HM and CM modules, the HD and RD modules

can select between:

•

The HCLK or CLK source from the HM or CM

module, respectively

•

A local signal routed on generic routing resources

Again, an unused input can be tied to ground for power

savings.

Clock

Network

The RTAX-S/SL architecture is capable of supporting a

large number of local clocks – 24 segments per HCLK

driving north-south and 28 segments per CLK driving

east-west per core tile.

CLKBUF

HCLKBUF

Figure 2-46 • CLKBUF and HCLKBUF

Actel Designer software’s place-and-route takes

advantage of the segmented clock structure found in

RTAX-S/SL devices by turning off any unused clock

segments. This results in not only better performance but

also lower power consumption. Future releases of

Designer will give the user greater control over these

individual clock segments.

Package pins CLKEP and CLKEN are associated with

CLKE; package pins HCLKAP and HCLKAN are

associated with HCLKA, etc.

Note that when CLKBUF (HCLKBUF) is used with a

single-ended I/O standard, it must be tied to the P-

pad of the CLK (HCLK) package pin. In this case, the

CLK (HCLK) N-pad can be used for user signals.

CLKINT and HCLKINT

CLKINT (HCLKINT) is used to access the CLK (HCLK)

resourceinternallyfromtheusersignals(Figure 2-47).

Clock

Network

Logic

CLKINT

HCLKINT

Figure 2-47 • CLKINT and HCLKINT

2-62

v5.3

RTAX-S/SL RadTolerant FPGAs

Embedded Memory

The RTAX-S/SL architecture provides extensive, high-

speed memory resources to the user. Each 4,608-bit block

of RAM contains its own embedded FIFO controller,

allowing the user to configure each block as either RAM

or FIFO.

RD [(N-1):0]

RA [K:0]

REN

To meet the needs of high performance designs, the

memory blocks operate in synchronous mode for both

read and write operations. However, the read and write

clocks are completely independent, and each may

operate beyond 500 MHz.

RCLK

WD [(M-1):0]

WA [J:0]

WEN

No additional core logic resources are required to

cascade the address and data buses when cascading

different RAM blocks. Dedicated routing runs along each

column of RAM to facilitate cascading.

WCLK

PIPE

The RTAX-S/SL memory block includes dedicated FIFO

control logic to generate internal addresses and external

flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and

write operations can occur asynchronously to one another,

special control circuitry is included to prevent

metastability, overflow, and underflow. A block diagram

of the memory module is illustrated in Figure 2-48.

RW [2:0]

WW [2:0]

Figure 2-48 • RTAX-S/SL Memory Module

RAM

During RAM operation, read (RA) and write (WA)

addresses are sourced by user logic and the FIFO

controller is ignored. In FIFO mode, the internal

addresses are generated by the FIFO controller and

routed to the RAM array by internal MUXes. Enables

with programmable polarity are provided to create

upper address bits for cascading up to 16 memory blocks.

When cascading memory blocks, the bussed signals WA,

WD, WEN, RA, RD, and REN are internally linked to

eliminate external routing congestion.

Each memory block consists of 4,608 bits that can be

organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1

and are cascadable to create larger memory sizes. This

allows built-in bus width conversion (Table 2-82). Each

block has independent read and write ports, which

enable simultaneous read and write operations.

Simultaneous read and write operations to the same

address is not supported.

Table 2-82 • Memory Block WxD Options

Data-Word (in bits)

Depth

4,096

2,048

1,024

512

Address Bus

RA/WA[11:0]

RA/WA[10:0]

RA/WA[9:0]

RA/WA[8:0]

RA/WA[7:0]

RA/WA[6:0]

Data Bus

RD/WD[0]

RD/WD[1:0]

RD/WD[3:0]

RD/WD[8:0]

RD/WD[17:0]

RD/WD[35:0]

256

128

v5.3

2-63

RTAX-S/SL RadTolerant FPGAs

Clocks

The RCLK and the WCLK have independent source

polarity selection and can be sourced by any global or

local signal.

512x9, 1kx4, 2kx2, and 4kx1. The allowable RW and WW

values are shown in Table 2-84.

When widths of one, two, and four are selected, the

ninth bit is unused. For example, when writing nine-bit

values and reading four-bit values, only the first four bits

and the second four bits of each nine-bit value are

addressable for read operations. The ninth bit is not

accessible. Conversely, when writing four-bit values and

reading nine-bit values, the ninth bit of a read operation

will be undefined.

RAM Configurations

The RTAX-S/SL architecture allows the read side and

write side of RAMs to be organized independently,

allowing for bus conversion. For example, the write side

can be set to 256x18 and the read side to 512x9.

Both the write width and read width for the RAM blocks

can be specified independently and changed dynamically

with the WW (write width) and RW (read width) pins.

The available DxW configurations are: 128x36, 256x18,

Note that the RAM blocks employ little-endian byte

order for read and write operations.

Table 2-83 • RAM Signal Description

Signal

WCLK

Direction

Input

Description

Write clock (can be active on either edge).

WA[J:0]

Input

Write address bus.The value J is dependent on the RAM configuration and the number of cascaded

memory blocks. The valid range for J is from 6 to15.

WD[M-1:0]

Input

Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or

36.

RCLK

Input

Read clock (can be active on either edge).

RA[K:0]

Read address bus. The value K is dependent on the RAM configuration and the number of cascaded

memory blocks. The valid range for K is from 6 to 15.

RD[N-1:0]

REN

Output

Input

Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36.

Read enable. When this signal is valid on the active edge of the clock, data at location RA will be

driven onto RD.

WEN

Input

Write enable. When this signal is valid on the active edge of the clock, WD data will be written at

location WA.

RW[2:0]

WW[2:0]

Pipe

Input

Width of the read operation dataword.

Width of the write operation dataword.

Sets the pipeline option to be on or off.

Table 2-84 • Allowable RW and WW Values

RW(2:0)

000

WW(2:0)

000

D x W

4kx1

001

2kx2

010

1kx4

011

512x9

256x18

128x36

reserved

100

101

11x

2-64

v5.3

RTAX-S/SL RadTolerant FPGAs

Modes of Operation

Enhancing SEU Performance

There are two read modes and one write mode:

SRAM structures are inherently susceptible to upsets

caused by high-energy particles encountered in space.

High-energy particles can cause an SRAM cell to change

state, resulting in the loss or corruption of a valuable

data bit. To allow users to achieve high levels of SEU

performance, Actel has developed an intellectual

property (IP) core to enhance the SEU tolerance of the

embedded SRAM within RTAX-S/SL.

•

Read Nonpipelined (synchronous – one clock

edge):

In the standard read mode, new data is driven

onto the RD bus in the clock cycle immediately

following RA and REN valid. The read address is

registered on the read-port active-clock edge and

data appears at read-data after the RAM access

time. Setting PIPE to OFF enables this mode.

This IP employs two upset-mitigation techniques:

•

Error Detection and Correction (EDAC)

Read Pipelined (synchronous – two clock edges):

A background memory-refresher, or scrubber

The pipelined mode incurs an additional clock

delay from address to data, but enables operation

at a much higher frequency. The read-address is

registered on the read-port active-clock edge, and

the read data is registered and appears at RD after

the second read clock edge. Setting PIPE to ON

enables this mode.

The EDAC IP employs the use of shortened Hamming

Codes to provide the user with single-error correction/

double-error detection (SEC/DED) capabilities. These

shortened Hamming Codes provide the user with an

implementation that has a reduced number of logic

levels and less complexity than traditional Hamming

Codes. The SmartGen-generated EDAC IP supports RAM

widths of 8, 16, and 32 bits, with a variable RAM depth

from 256 to 4k words.

Write (synchronous – one clock edge):

On the write active-clock edge, the write data are

written into the SRAM at the write address when

WEN is high. The setup time of the write address,

write enables, and write data are minimal with

respect to the write clock.

The memory scrubber circuitry has also been embedded

in the EDAC IP as an optional block. The scrubber

circuitry periodically refreshes memory in the

background to ensure that no corruption of its contents

has taken place while the memory was not in use. The

refresh rate can be set by the user.

Write and read transfers are described with timing

requirements beginning in "Timing Characteristics" on

page 2-67.

The use of EDAC IP combined with the embedded

memory scrubber circuitry, gives the RTAX-S/SL an SEU

radiation performance level of better than 10^-10errors/

bit-day. See the application note Using EDAC RAM for

RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs.

v5.3

2-65

RTAX-S/SL RadTolerant FPGAs

Timing Model and Waveforms

WCLK

WEN

RCLK

REN

Table 2-85 • SRAM Model

t_WCKH

t_WCKP

t_WCKL

WCLK

t_WxxSU

t_WxxHD

WA<11:0>, WD<35:0>, WEN<4:0>

Figure 2-49 • RAM Write Timing Waveforms

t_RCKH

t_RCKL

t_RCKP

RCLK

t_RxxSU

t_RxxHD

RA<11:0>, REN<4:0>

t_RCK2RD1

t_RCK2RD2

RD <35:0>

Figure 2-50 • RAM Read Timing Waveforms

2-66

v5.3

RTAX-S/SL RadTolerant FPGAs

Timing Characteristics

Table 2-86 • One RAM Block (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

1.08

0.00

1.45

0.30

1.08

0.00

1.31

1.53

3.07

1.27

0.00

1.70

0.35

1.27

0.00

1.54

1.80

3.60

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

t_WENHD

t_WCKH

t_WCLKL

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

2.90

0.93

1.08

0.00

3.41

0.93

1.27

0.00

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

1.86

3.50

2.19

4.12

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

1.34

1.62

3.24

1.58

1.90

3.81

t_RCLKL

t_RCKP

v5.3

2-67

RTAX-S/SL RadTolerant FPGAs

Table 2-87 • Two RAM Blocks Are Cascaded (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

1.86

0.30

1.86

0.30

1.86

0.30

1.31

3.07

6.13

2.19

0.35

2.19

0.35

2.19

0.35

1.54

3.60

7.21

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

t_WENHD

t_WCKH

t_WCLKL

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

2.28

0.00

2.28

0.00

2.68

0.00

2.68

0.00

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

2.02

3.69

2.38

4.34

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

1.27

3.29

6.58

1.49

3.87

7.74

t_RCLKL

t_RCKP

2-68

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-88 • Four RAM Blocks Are Cascaded (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

3.17

0.30

3.17

0.30

3.17

0.30

1.31

4.37

8.75

3.73

0.35

3.73

0.35

3.73

0.35

1.54

5.14

10.28

Write Data Hold vs. WCLK

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

t_WENHD

t_WCKH

t_WCLKL

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

4.13

0.00

4.13

0.00

4.85

0.00

4.85

0.00

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

3.33

4.49

3.91

5.28

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

1.27

5.16

1.49

6.06

t_RCLKL

t_RCKP

10.31

12.12

v5.3

2-69

RTAX-S/SL RadTolerant FPGAs

Table 2-89 • Eight RAM Blocks Are Cascaded (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

7.73

0.30

7.73

0.30

7.73

0.30

1.31

8.94

17.87

9.09

0.35

9.09

0.35

9.09

0.35

1.54

10.51

21.01

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

t_WENHD

t_WCKH

t_WCLKL

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

9.04

0.00

9.04

0.00

10.63

0.00

t_RADHD

t_RENSU

10.63

0.00

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

4.77

7.33

5.61

8.62

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

1.27

10.05

20.10

1.49

11.82

23.63

t_RCLKL

t_RCKP

2-70

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-90 • Sixteen RAM Blocks Are Cascaded (Worst-Case Military Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

Description

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

22.14

0.30

26.03

0.35

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

22.14

0.30

26.03

0.35

22.14

0.30

26.03

0.35

t_WENHD

t_WCKH

1.31

1.54

t_WCLKL

23.34

46.69

27.44

54.88

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

24.27

0.00

28.53

0.00

t_RADHD

t_RENSU

24.27

0.00

28.53

0.00

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

17.02

18.62

20.01

21.89

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

1.27

25.10

50.21

1.49

29.51

59.02

t_RCLKL

t_RCKP

v5.3

2-71

RTAX-S/SL RadTolerant FPGAs

FIFO

Every memory block has its own embedded FIFO

controller. Each FIFO block has one read port and one

write port. This embedded FIFO controller uses no

internal FPGA logic and features:

•

The FULL flag is synchronous to WCLK. It allows

the FIFO to inhibit writing when full.

The EMPTY flag is synchronous to RCLK. It allows

the FIFO to inhibit reading at the empty condition.

•

Glitch-free FIFO Flags

Note: Actel recommends that the WCLK and the RCLK

are in phase with each other. For more information refer

to the application note, EMPTY and FULL Flag Behaviors

of the Axcelerator FIFO Controller.

Gray-code address counters/pointers to prevent

metastability problems

•

Overflow and underflow control

Gray code counters are used to prevent metastability

problems associated with flag logic. The depth of the

FIFO is dependent on the data width and the number of

memory blocks used to create the FIFO. The write

operations to the FIFO are synchronous with respect to

the WCLK, and the read operations are synchronous with

respect to the RCLK.

Both ports are configurable in various size from 4kx1 to

128x36, similar to the RAM block size. Each port is fully

synchronous.

Read and write operations can be completely

independent. Data on the appropriate WD pins are

written to the FIFO on every active WCLK edge as long as

WEN is high. Data is read from the FIFO and output on

the appropriate RD pins on every active RCLK edge as

long as REN is asserted.

The FIFO block may be reset to the empty state

The FIFO control unit was not implemented with SEU-

hardened registers. Designs requiring high SEU tolerance

should implement the FIFO control unit from hardened

core logic.

The FIFO block offers programmable Almost-Empty

(AEMPTY) and Almost-Full (AFULL) flags as well as

EMPTY and FULL flags (Figure 2-51):

RD [n-1:0]

WD [n-1:0]

RCLK

WCLK

RAM

RA [J:0]

WA [J:0]

REN

WEN

DEPTH[3:0]

CNT 16

FREN

FULL

AFULL

AFVAL

AEVAL

AEMPTY

EMPTY

CNT 16

FWEN

CLR

Figure 2-51 • RTAX-S/SL RAM with Embedded FIFO Controller

2-72

v5.3

RTAX-S/SL RadTolerant FPGAs

FIFO Flag Logic

The FIFO is user configurable into various depths and

widths. Figure 2-52 shows the FIFO address counter

details.

RAM block, whereas bits 13 and 12 will be used to specify

the RAM block.

The AFULL and AEMPTY flag threshold values are

programmable. The threshold values are AFVAL and

AEVAL, respectively. Although the trigger threshold for

each flag is defined with eight bits, the effective number

of threshold bits in the comparison depends on the

configuration. Note that the effective number of

threshold bits corresponds to the range of active bits in

the FIFO address space (Table 2-91).

•

Bits 11 to 5 are active for all modes.

As the data word size is reduced, more least-

significant bits are added to the address.

•

As the number of cascaded blocks increases, the

number of significant bits in the address increases.

For example, if four blocks are cascaded as a 1kx16 FIFO

with each block having a 1kx4 aspect ratio, bits 11 to 2 of

the address will be used to specify locations within each

FIFO Address Counters

Mode when

Active

Counter

Bits

FIFO Address

Alignment of

Threshold bits

R/W EN[3]

R/W EN[2]

CNTR [15]

activate

Cas 16 blks

Cas 8 blks

AEVAL/AFVAL[7]

AEVAL/AFVAL[6]

CNTR [14]

activate

[15:W]

Cas 4 blks

Cas 2 blks

CNTR [13]

activate

R/W EN[1]

R/W EN[0]

AEVAL/AFVAL[5]

AEVAL/AFVAL[4]

[14:W]

[13:W]

[12:W]

CNTR [12]

activate

4kx1

AEVAL/AFVAL[3:0] ^{128x36 256x18}

512x9

1kx4

2kx2

R/W ADD[11:8]

R/W ADD[7:5]

by 36

CNTR [11:5]

always active

not compared

[11:5]

[11:4]

[11:3]

by 18

by 9

CNTR [4]

activate

R/W ADD[4]

not compared

[11:2]

CNTR [3]

activate

[11:1]

R/W ADD[3]

R/W ADD[2]

[11:0]

by 4

by 2

by 1

CNTR [2]

activate

CNTR [1]

activate

R/W ADD[1]

R/W ADD[0]

CNTR [0]

activate

Variable Active Address Space

CNTR [15:0]

>> REN [4:0], RAD [11:0]

>> WEN [4:0], WAD [11:0]

Note: Inactive counter bits are set to zero.

Figure 2-52 • FIFO Address Counters

Table 2-91 • FIFO Flag Logic

Mode

Inactive AEVAL/AFVAL bits

Inactive DIFF bits (set to 0) DIFF comparison to AFVAL/AEVAL

Non-cascade

[7:4]

[7:5]

[7:6]

[7]

[15:12]

[15:13]

[15:14]

[15]

DIFF[11:8] withAE/FVAL[3:0]

DIFF[12:8] withAE/FVAL[4:0]

DIFF[13:8] withAE/FVAL[5:0]

DIFF[14:8] withAE/FVAL[6:0]

DIFF[15:8] withAE/FVAL[7:0]

Cascade 2 blocks

Cascade 4 blocks

Cascade 8 blocks

Cascade 16 blocks

None

v5.3

2-73

RTAX-S/SL RadTolerant FPGAs

Figure 2-53 illustrates flag generation. The Verilog statements for flag assignment are:

assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0;

assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0;

The number of DIFF-bits active depends on the configuration depth and width (Table 2-92). The active-high CLR pin is

used to reset the FIFO to the empty state, which sets FULL and AFULL low, and EMPTY and AEMPTY high.

Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active edge of the

clock. Write and read transfers are described with timing requirements in "Timing Characteristics" on page 2-77. For

more information refer to the application note, EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller.

AEMPTY

AEVAL [7:0], GND [7:0] (MSB....LSB)

WCNTR

[15:0]

WCLK

RCLK

X>=Y

(16-bit)

DIFF [15:0]

RCNTR

[15:0]

AFULL

AFVAL [7:0], GND [7:0] (MSB....LSB)

Figure 2-53 • ALMOST-EMPTY and ALMOST-FULL Logic

Table 2-92 • Number of Available Configuration Bits

Number of Blocks

Block DxW

Number of AEVAL/AFVAL Bits

1x1

1x2

2x1

1x4

2x2

4x1

1x8

2x4

4x2

8x1

1x16

2x8

4x4

8x2

16x1

2-74

v5.3

RTAX-S/SL RadTolerant FPGAs

EMPTY flag is set when the read and write addresses are

equal. To prevent underflow, the write address is double-

sampled by the read clock prior to comparison with the

read address (part A in Figure 2-54). To prevent overflow,

the read address is double-sampled by the write clock

prior to comparison to the write address (part B in

Figure 2-54).

Glitch Elimination

An analog filter is added to each FIFO controller to

guarantee, glitch-free FIFO-flag logic.

Overflow and Underflow Control

The counter MSB keeps track of the difference between

the read address (RA) and the write address (WA). The

EMPTY

FULL

RCLK

WCLK

Figure 2-54 • Overflow and Underflow Control

FIFO Configurations

Clock

Unlike the RAM, the FIFO's write width and read width

cannot be specified independently. For the FIFO, the

write and read widths must be the same. The WIDTH pins

are used to specify one of six allowable word widths, as

shown in Table 2-93.

As with RAM configuration, the RCLK and WCLK pins

have independent polarity selection

Table 2-93 • FIFO Width Configurations

WIDTH(2:0)

000

WxD

1x4k

The DEPTH pins allow RAM cells to be cascaded to create

larger FIFOs. The four pins allow depths of 2, 4, 8, and 16

to be specified. Table 2-82 on page 2-63 describes the

FIFO depth options for various data width and memory

blocks.

001

2x2k

010

4x1k

011

9x512

18x256

36x128

reserved

100

Interface

101

Figure 2-55 shows a logic block diagram of the RTAX-S/SL

FIFO module.

11x

Cascading FIFO Blocks

RD [35:0]

FULL

DEPTH [3:0]

WIDTH [2:0]

FIFO blocks can be cascaded to create deeper FIFO

functions. When building larger FIFO blocks, if the word

width can be fractured in a multi-bit FIFO, the fractured

word configuration is recommended over a cascaded

configuration. For example, 256x36 can be configured as

two blocks of 256x18. This should be taken into account

when building the FIFO blocks manually. However, when

using SmartGen, the user only needs to specify the depth

and width of the necessary FIFO blocks. SmartGen

automatically configures these blocks to optimize

performance.

PIPE

FREN

EMPTY

AFULL

RCLK

AEVAL [7:0]

AEMPTY

AFVAL [7:0]

WD [35:0]

FWEN

WCLK

CLR

Figure 2-55 • FIFO Block Diagram

v5.3

2-75

RTAX-S/SL RadTolerant FPGAs

Table 2-94 • FIFO Signal Description

Signal

WCLK

FWEN

Direction

Description

Input

Write clock (active either edge).

FIFO write enable. When this signal is asserted, the WD bus data is latched into the

FIFO, and the internal write counters are incremented.

WD[N-1:0]

FULL

Input

Write data bus. The value N is dependent on the RAM configuration and can be 1,

2, 4, 9, 18, or 36.

Output

Active high signal indicating that the FIFO is FULL. When this signal is set,

additional write requests are ignored.

AFULL

AFVAL

RCLK

Output

Input

Active high signal indicating that the FIFO is AFULL.

8-bit input defining the AFULL value of the FIFO.

Read clock (active either edge).

Input

FREN

Input

FIFO read enable.

RD[N-1:0]

Output

Read data bus. The value N is dependent on the RAM configuration and can be 1,

2, 4, 9, 18, or 36.

EMPTY

Output

Empty flag indicating that the FIFO is EMPTY. When this signal is asserted,

attempts to read the FIFO will be ignored.

AEMPTY

AEVAL

PIPE

Output

Input

Active high signal indicating that the FIFO is AEMPTY.

8-bit input defining the almost-empty value of the FIFO.

Sets the pipe option on or off.

CLR

Active high clear input.

DEPTH

WIDTH

Determines the depth of the FIFO and the number of FIFOs to be cascaded.

Determines the width of the dataword / width of the FIFO, and the number of the

FIFOs to be cascaded.

2-76

v5.3

RTAX-S/SL RadTolerant FPGAs

Timing Characteristics

AEMPTY

EMPTY

AFULL

FULL

FWEN

FREN

WCLK

RCLK

Clr

Figure 2-56 • FIFO Model

t_WCKH

t_WCKP

t_WCKL

WCLK

t_WSU

t_WHD

WD<35:0>, FWEN

t_CLR2HF

CLR

t_WCK2xF

t_CLR2xF

EMPTY, AEMPTY, AFULL, FULL

Figure 2-57 • FIFO Write Timing

v5.3

2-77

RTAX-S/SL RadTolerant FPGAs

t_RCKH

t_RCKL

t_RCKP

RCLK

FREN

t_RSUt_RHD

t_RCK2RD1

t_RCK2RD2

RD <35:0>

t_CLRHF

CLR

t_CLR2xF

t_CK2xF

EMPTY, AEMPTY, AFULL, FULL

Figure 2-58 • FIFO Read Timing

2-78

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-95 • One FIFO Block (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

0.88

0.30

1.31

1.53

0.88

0.35

1.54

1.80

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

Minimum WCLK Period

Read Setup

15.58

0.00

1.34

1.62

18.31

0.00

1.58

1.90

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.45

2.57

5.88

2.85

6.75

1.70

3.02

6.91

3.35

7.94

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Non-Pipelined)

1.86

3.50

2.19

4.12

Table 2-96 • Two FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

1.86

0.30

1.31

3.07

2.19

0.35

1.54

3.60

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

Minimum WCLK Period

Read Setup

2.28

0.00

1.27

3.29

2.68

0.00

1.49

3.87

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.45

2.57

5.88

2.85

6.75

1.70

3.02

6.91

3.35

7.94

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Non-Pipelined)

2.02

3.69

2.38

4.34

v5.3

2-79

RTAX-S/SL RadTolerant FPGAs

Table 2-97 • Four FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

Write Hold

WCLK High

WCLK Low

3.17

0.30

1.31

4.37

3.73

0.35

1.54

5.14

t_WHD

t_WCKH

t_WCKL

t_WCKP

t_RSU

Minimum WCLK Period

Read Setup

4.13

0.00

1.27

5.16

4.85

0.00

1.49

6.06

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.45

2.57

5.88

2.85

6.75

1.70

3.02

6.91

3.35

7.94

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Non-Pipelined)

3.33

4.49

3.91

5.28

Table 2-98 • Eight FIFO Blocks Are Cascaded (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

Write Hold

WCLK High

WCLK Low

7.73

0.30

1.31

8.94

9.09

0.35

t_WHD

t_WCKH

t_WCKL

t_WCKP

t_RSU

1.54

10.51

Minimum WCLK Period

Read Setup

9.04

0.00

10.63

0.00

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

1.27

1.49

RCLK Low

10.05

11.82

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.45

2.57

5.88

2.85

6.75

1.70

3.02

6.91

3.35

7.94

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Non-Pipelined)

4.77

7.33

5.61

8.62

2-80

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-99 • Sixteen FIFO Blocks are Cascaded (Worst-Case MIlitary Conditions V_CCA= 1.4 V, V_CCI= 3.0 V, T_J= 125°C)

'–1' Speed 'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

22.14

0.30

26.03

0.35

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

1.31

1.54

23.34

27.44

Minimum WCLK Period

Read Setup

24.27

0.00

28.53

0.00

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

1.27

1.49

RCLK Low

25.10

29.51

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

1.45

2.57

5.88

2.85

6.75

1.70

3.02

6.91

3.35

7.94

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Non-Pipelined)

17.02

18.62

20.01

21.89

Building RAM and FIFO Modules

RAM and FIFO modules can be generated and included in a design in two different ways:

•

Using the SmartGen core generator where the user defines the depth and width of the FIFO/RAM, and then

instantiates this block into the design (please refer to the Actel SmartGen, FlashROM, Analog System Builder,

and Flash Memory System Builder User’s Guide for more information).

•

The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all

unused data bits to ground.

v5.3

2-81

RTAX-S/SL RadTolerant FPGAs

Other Architectural Features

Charge Pump Bypass

To reduce power consumption, the internal charge pump

can be bypassed and an external power supply voltage

can be used instead. This saves the internal charge-pump

operating current, resulting in no DC current draw. The

RTAX-S/SL family devices have a dedicated "V_PUMP" pin

that can be used to access an external charge pump

device. In normal chip operation, when using the

internal charge pump, V_PUMPshould be tied to GND.

When the voltage level on V_PUMPis set to 3.3 V, the

internal charge pump is turned off, and the V_PUMP

voltage will be used as the charge pump voltage.

Adequate voltage regulation (i.e., high drive, low output

impedance, and good decoupling) should be used at

TRST

TRST (Test-Logic Reset) is an active-low asynchronous

reset signal to the TAP controller. The TRST input can be

used to reset the Test Access Port (TAP) Controller to the

TRST state. The TAP Controller can be held at this state

permanently by grounding the TRST pin. To hold the

JTAG TAP controller in the TRST state, it is recommended

to connect TRST directly to ground for flight.

There is an optional internal pull-up resistor available for

the TRST input that can be set by the user at

programming. Care should be exercised when using this

option in combination with an external tie-off to

ground.

V_PUMP

An on-chip power-on-reset (POWRST) circuit is included.

POWRST has the same function as "TRST," but it only

occurs at power-up or during recovery from a V_CCAand/

or V_CCDAvoltage drop.

JTAG

RTAX-S/SL offers a JTAG interface that is compliant with

the IEEE 1149.1 standard except for the device ID length

which is 33 bits. The user can employ the JTAG interface

for probing a design and executing any JTAG public

instructions as defined in the Table 2-100. The JTAG pins

and probes are configured as a LVTTL standard port.

Refer to the IEEE Standard 1149.1 (JTAG) in the

Axcelerator Family application note, which also applies

to the RTAX-S/SL family of devices. The JTAG pins

should not be left floating on flight systems.

TDO

TDO is normally tristated, and it is active only when the

TAP controller is in the "Shift_DR" state or "Shift_IR"

state. The least significant bit of the selected register

(i.e., IR or DR) is clocked out to TDO first by the falling

edge of TCK.

TAP Controller

The TAP Controller is compliant with the IEEE Standard

1149.1. It is a state machine of 16 states that controls the

Instruction Register (IR) and the Data Registers (such as

Boundary-Scan Register, IDCODE, USRCODE, BYPASS,

etc.). The TAP Controller steps into one of the states

depending on the sequence of TMS at the rising edges of

TCK.

Table 2-100 • JTAG Instruction Code

Instruction (IR4:IR0)

EXTEST

Binary Code

00000

PRELOAD / SAMPLE

INTEST

00001

00010

USERCODE

IDCODE

00011

Instruction Register (IR)

00100

The IR has five bits (IR4 to IR0). At the TRST state, IR is

reset to IDCODE. Each time when IR is selected, it goes

through "select IR-Scan," "Capture-IR," "Shift-IR," all the

way through "Update-IR." When there is no test error,

the first five data bits coming out of TDO during the

"Shift-IR" will be "10111." If a test error occurs, the last

three bits will contain one to three zeroes corresponding

to negatively asserted signals: "TDO_ERRORB,"

"PROBA_ERRORB," and "PROBB_ERRORB." The error(s)

will be erased when the TAP is at the "Update-IR" or the

TRST state. When in user mode start-up sequence, if the

micro-probe has not been used, the "PROBA_ERRORB" is

used as a "Power-up done successfully" flag.

HIGHZ

01110

CLAMP

01111

DIAGNOSTIC

Reserved

10000

All others

11111

BYPASS

Interface

The interface consists of four inputs: Test Mode Select

(TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller

Reset (TRST), and an output, Test Data Out (TDO). TMS,

TDI, and TRST have on-chip pull-up resistors.

During flight, the following configurations for all JTAG

and Probe pins are recommended (Table 2-101 on

page 2-83).

2-82

v5.3

RTAX-S/SL RadTolerant FPGAs

Table 2-101 • JTAG and Probe Pin Recommendations for Flight

JTAG and Probe Pins

Configurations

Can be hardwired to V_CCDAor ground

TCK

•

Can be driven to V_CCDAor ground

Must not be left unterminated

TDO

TDI

Must be left unconnected

•

Can be hardwired or driven to V_CCDA

Can be left unconnected (equipped with internal 10 k pull-up resistor)

Can be hardwired or driven to V_CCDA

TMS

Can be left unconnected (equipped with internal 10 k pull-up resistor)

TRST

Must be hardwired to ground (equipped with optional internal 10 k pull-up resistor)

Must be left unconnected

PRA/B/C/D

Data Registers (DRs)

Probing

Data registers are distributed throughout the chip. They

store testing/programming vectors. The MSB of a data

to TDO. There are different types of data registers.

Descriptions of the main registers are as follow:

Internal activities of the JTAG interface can be observed

via the Silicon Explorer II probes: "PRA," "PRB," "PRC,"

and "PRD."

Special Fuses

Security

1. IDCODE:

The IDCODE is a 33-bit hard coded JTAG Silicon

Signature. It is a hardwired device ID code, which

contains the Actel identity, part number, and version

number in a specific JTAG format. Refer to the IEEE

Standard 1149.1 (JTAG) in the Axcelerator Family

application note for more information.

Actel antifuse FPGAs, with FuseLock technology, offer

the highest level of design security available in a

programmable logic device. Since antifuse FPGAs are live

at power-up, there is no bitstream that can be

intercepted, and no bitstream or programming data is

ever downloaded to the device during power-up, thus

making device cloning impossible. In addition, special

security fuses are hidden throughout the fabric of the

device and may be programmed by the user to thwart

attempts to reverse engineer the device by attempting

to exploit either the programming or probing interfaces.

Both invasive and noninvasive attacks against an RTAX-S/

SL device that access or bypass these security fuses will

destroy access to the rest of the device. (refer to the

Design Security in Nonvolatile Flash and Antifuse FPGAs

white paper).

2. USERCODE:

The USERCODE is a 33-bit programmable JTAG Silicon

Signature. It is a supplementary identity code for the

user to program information to distinguish different

programmed parts. USERCODE fuses will read out as

"zeroes" when not programmed, so only the "1" bits

need to be programmed. Refer to the IEEE Standard

1149.1 (JTAG) in the Axcelerator Family application

note for more information.

3. Boundary-Scan Register (BSR):

Each I/O contains three BSR Cells. Each cell has a shift

scan cells are used for the Output-enable (E), Output

(O), and Input (I) registers. The bit order of the

boundary-scan cells for each of them is E-O-I. The

boundary-scan cells are then chained serially to form

the BSR. The length of the BSR is the number of I/Os

in the die (not the package) multiplied by three. This

excludes special function pins (TRST, TCK, TMS, TDI,

TDO, PRA, PRB, PRC, PRD, and VPUMP).

Look for this symbol to ensure your valuable IP is secure.

™

Figure 2-59 • FuseLock Logo

4. Bypass Register (BYR):

This is the "1-bit" register. It is used to shorten the

TDI-TDO serial chain in board-level testing to only

one bit per device not being tested. It is also selected

for all "reserved" or unused instructions.

v5.3

2-83

RTAX-S/SL RadTolerant FPGAs

To ensure maximum security in RTAX-S/SL devices, it is

recommended that the user program the device security

fuse (SFUS). When programmed, the Silicon Explorer II

testing probes are disabled to prevent internal probing,

and the programming interface is also disabled. All JTAG

public instructions are still accessible by the user.

Silicon Explorer II connects to the host PC using a

standard serial port connector. Connections to the circuit

board are achieved using a nine-pin D-Sub connector

(Figure 1-9 on page 1-8). Once the design has been

placed-and-routed, and the RTAX-S/SL device has been

programmed, Silicon Explorer II can be connected and

the Explorer software can be launched.

For more information, refer to Actel’s Implementation of

Security in Actel Antifuse FPGAs application note.

Silicon Explorer II comes with an additional optional PC

hosted tool that emulates an 18-channel logic analyzer.

Four channels are used to monitor four internal nodes,

and 14 channels are available to probe external signals.

The software included with the tool provides the user

with an intuitive interface that allows for easy viewing

and editing of signal waveforms.

Global Set Fuse

The Global Set Fuse determines if all R-cells and I/O

Registers (InReg, OutReg, and EnReg) are either cleared

or preset by driving the GCLR and GPSET inputs of all

R-cells and I/O Registers ("R-Cell" on page 2-48). Default

setting is to clear all registers (GCLR = 0 and GPSET =1) at

device power-up. When the GBSETFUS option is checked

during FUSE file generation, all registers are preset

(GCLR = 1 and GPSET= 0). A local CLR or PRESET will take

precedence overt this setting. Both pins are pulled HIGH

during normal device operation. For use details, see

Libero IDE online help.

Programming

Device programming is supported through the Silicon

Sculptor 3, a single-site, robust and compact device

programmer for the PC. Up to four Silicon Sculptor 3s can

be daisy-chained and controlled from a single PC host.

With standalone software for the PC, Silicon Sculptor 3 is

designed to allow concurrent programming of multiple

units from the same PC when daisy-chained.

Silicon Explorer II Probe Interface

Silicon Explorer II is an integrated hardware and

software solution that, in conjunction with the Designer

tools, allows users to examine any of the internal nets

(except I/O registers) of the device while it is operating in

a prototype or a production system. The user can probe

up to four nodes at a time without changing the

placement and routing of the design and without using

any additional device resources. Highlighted nets in

Designer’s ChipPlanner can be accessed using Silicon

Explorer II in order to observe their real time values.

Silicon Sculptor 3 programs devices independently to

achieve the fastest programming times possible. Each

fuse is verified by Silicon Sculptor 3 to ensure correct

programming. Furthermore, at the end of programming,

there are integrity tests that are run to ensure that

programming was completed properly. Not only does it

test programmed and nonprogrammed fuses, Silicon

Sculptor 3 also provides a self-test to test its own

hardware extensively.

Programming an RTAX-S/SL device using Silicon Sculptor

3 is similar to programming any other antifuse device.

The procedure is as follows:

Silicon Explorer II's noninvasive method does not alter

timing or loading effects, thus shortening the debug

cycle. In addition, Silicon Explorer II does not require

relayout or additional MUXes to bring signals out to an

external pin, which is necessary when using

programmable logic devices from other suppliers. By

eliminating multiple place-and-route program cycles the

integrity of the design is maintained throughout the

debug process.

1. Load the AFM file.

2. Select the device to be programmed.

3. Begin programming.

When the design is ready to go to production, Actel

offers device volume-programming services either

through distribution partners or via our In-House

Programming Center.

Each member of the RTAX-S/SL family has four external

pads: PRA, PRB, PRC, and PRD. These can be used to bring

out four probe signals from the RTAX-S/SL device. Each

core tile can has up to two probe signals. To disallow

probing, the SFUS security fuse in the silicon signature

has to be programmed (see "Special Fuses" on page 2-83

for more information).

For more details on programming the RTAX-S/SL devices,

please refer to the Silicon Sculptor User’s Guide.

2-84

v5.3

RTAX-S/SL RadTolerant FPGAs

Package Pin Assignments

208-Pin CQFP

156

155

154

153

Pin 1

Ceramic

Tie Bar

208-Pin CQFP

108

107

106

105

Figure 3-1 • 208-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit the Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.3

3-1

RTAX-S/SL RadTolerant FPGAs

208 CQFP

RTAX250S/SL Function Number

Bank 0

IO43PB2F2

IO44NB2F2

IO44PB2F2

134

131

133

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

IO78PB5F5

IO02NB0F0

IO03NB0F0

197

198

199

191

192

185

186

IO03PB0F0

Bank 3

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO48NB3F3

IO48PB3F3

IO50NB3F3

IO50PB3F3

IO55NB3F3

IO55PB3F3

IO57NB3F3

IO57PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO86NB5F5

IO87NB5F5

IO87PB5F5

IO88NB5F5

IO88PB5F5

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

180

181

174

175

170

171

165

166

161

162

159

160

IO89NB5F5

IO89PB5F5

Bank 6

IO91NB6F6

IO91PB6F6

IO16PB1F1

IO24NB1F1

IO92NB6F6

IO92PB6F6

IO24PB1F1

IO26NB1F1

IO93NB6F6

IO93PB6F6

IO26PB1F1

IO27NB1F1

IO94PB6F6

IO27PB1F1

IO96NB6F6

IO96PB6F6

Bank 2

IO29NB2F2

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

Bank 4

IO101NB6F6

IO101PB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

Bank 7

IO29PB2F2

IO62NB4F4

IO62PB4F4

100

103

101

102

IO30NB2F2

IO30PB2F2

IO63NB4F4

IO31PB2F2

IO63PB4F4

IO32NB2F2

IO64NB4F4

IO32PB2F2

IO64PB4F4

IO34NB2F2

IO72NB4F4

IO34PB2F2

IO72PB4F4

IO39NB2F2

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

IO39PB2F2

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO110NB7F7

IO40PB2F2

IO41NB2F2

IO41PB2F2

IO43NB2F2

IO76NB5F5/CLKGN

3-2

v5.3

RTAX-S/SL RadTolerant FPGAs

208 CQFP

RTAX250S/SL Function Number

IO110PB7F7

IO112NB7F7

IO112PB7F7

IO117NB7F7

IO117PB7F7

IO119NB7F7

IO119PB7F7

IO121PB7F7

IO122NB7F7

IO122PB7F7

IO123NB7F7

IO123PB7F7

GND

194

196

201

208

V_CCA

156

168

195

V_CCA

V_CCDA

105

130

157

167

182

202

193

200

163

172

135

149

112

124

Dedicated I/O

176

177

178

179

187

188

189

190

184

183

GND

_CCIB0

V_CCIB0

_CCIB1

_CCIB2

PRA

PRB

PRC

PRD

TCK

TDI

V_CCIB3

_CCIB3

_CCIB4

_CCIB5

205

204

203

206

207

104

113

119

125

136

143

150

155

164

169

173

TDO

TMS

TRST

V_CCA

V_CCIB6

_CCIB6

_CCIB7

V_PUMP

158

118

142

v5.3

3-3

RTAX-S/SL RadTolerant FPGAs

256-Pin CQFP

192

191

190

189

Pin 1

Ceramic

Tie Bar

256-Pin CQFP

132

131

130

129

Figure 3-2 • 208-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit the Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

3-4

v5.3

RTAX-S/SL RadTolerant FPGAs

256-Pin CQFP

RTAX2000S/SL Function Number

Bank 0 - Block 0

Bank 2 - Block 10

IO167PB3F15

Bank 4 - Block 17

IO181NB4F17

134

IO01NB0F0

IO01PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO08NB0F0

IO08PB0F0

248

249

246

247

242

243

240

241

IO107NB2F10

IO107PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

184

185

180

181

178

179

174

175

172

173

168

169

166

167

162

163

124

125

122

123

118

119

116

117

112

113

110

111

IO181PB4F17

IO182NB4F17

IO182PB4F17

IO183NB4F17

IO183PB4F17

IO184NB4F17

Bank 0 - Block 3

IO184PB4F17

IO37NB0F3

234

235

232

233

228

229

IO190NB4F17

IO37PB0F3

IO190PB4F17

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

IO192NB4F17

IO192PB4F17

Bank 4 - Block 19

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5 - Block 20

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

Bank 5 - Block 22

IO236NB5F22

104

105

100

101

Bank 1 - Block 4

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

220

221

216

217

Bank 3 - Block 13

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

158

159

154

155

152

153

148

149

146

147

140

141

142

143

136

137

Bank 1 - Block 6

IO65NB1F6

IO65PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO71NB1F6

IO71PB1F6

IO73NB1F6

IO73PB1F6

IO74NB1F6

IO74PB1F6

210

211

208

209

199

204

205

202

203

197

198

IO236PB5F22

IO238NB5F22

IO238PB5F22

IO240NB5F22

IO240PB5F22

IO242NB5F22

IO242PB5F22

Bank 2 - Block 8

IO243NB5F22

IO87NB2F8

IO87PB2F8

IO89PB2F8

187

188

186

Bank 3 - Block 15

IO243PB5F22

IO165NB3F15

IO167NB3F15

135

133

IO244NB5F22

IO244PB5F22

v5.3

3-5

RTAX-S/SL RadTolerant FPGAs

256-Pin CQFP

RTAX2000S/SL Function Number

Bank 6 - Block 24

IO320PB7F29

Bank 7 - Block 31

IO341NB7F31

IO341PB7F31

Dedicated I/O

GND

PRA

171

177

183

190

192

193

201

207

213

219

225

231

239

245

256

227

226

IO257PB6F24

IO258NB6F24

IO258PB6F24

Bank 6 - Block 26

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

GND

PRB

GND

PRC

GND

PRD

GND

TCK

253

252

250

254

255

GND

TDI

Bank 7 - Block 29

GND

TDO

TMS

TRST

V_CCA

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

GND

103

109

115

121

128

129

132

139

145

151

157

161

165

GND

108

127

131

150

170

189

GND

3-6

v5.3

RTAX-S/SL RadTolerant FPGAs

256-Pin CQFP

RTAX2000S/SL Function Number

V_CCA

191

212

238

V_CCIB3

156

102

114

120

V_CCIB4

V_CCA

V_CCDA

V_CCIB0

V_CCIB5

V_CCIB6

V_CCIB7

106

107

126

130

160

194

196

214

215

222

223

224

236

237

251

230

244

200

206

218

164

176

182

138

144

V_PUMP

195

V_CCIB0

V_CCIB1

V_CCIB2

V_CCIB3

v5.3

3-7

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

264

263

262

261

Pin 1

Ceramic

Tie Bar

223

222

221

220

219

218

217

216

215

352-Pin CQFP

180

179

178

177

Figure 3-3 • 352-Pin CQFP

Note:

The 352-pin CQFP pin assignments for both RTAX1000S/SL and RTAX2000S/SL are compatible except for the following

seven pins: 91, 130, 131, 174, 268, 307, and 308. On the RTAX1000S/SL, these pins are no connects (NC), and for

RTAX2000S/SL these pins are assigned to V_CCDA. Customers are therefore recommend to layout their board targeting

the RTAX2000S/SL device, in order to preserve interchangeability between the two devices.

For Package Manufacturing and Environmental information, visit the Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

3-8

v5.3

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX250S/SL Function Number

Bank 0

IO25NB1F1

IO25PB1F1

IO27NB1F1

IO27PB1F1

271

272

269

270

IO46PB3F3

IO47NB3F3

IO47PB3F3

IO48NB3F3

IO48PB3F3

IO49NB3F3

IO49PB3F3

IO51NB3F3

IO51PB3F3

IO52NB3F3

IO52PB3F3

IO53NB3F3

IO53PB3F3

IO54NB3F3

IO54PB3F3

IO55NB3F3

IO55PB3F3

IO56NB3F3

IO56PB3F3

IO57NB3F3

IO57PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

220

213

214

211

212

207

208

205

206

201

202

199

200

195

196

193

194

187

188

189

190

183

184

181

182

179

180

IO00NB0F0

IO00PB0F0

341

342

343

337

338

335

336

331

332

325

326

323

324

319

320

313

314

IO01NB0F0

IO02NB0F0

Bank 2

IO02PB0F0

IO29NB2F2

IO29PB2F2

IO30NB2F2

IO30PB2F2

IO31NB2F2

IO31PB2F2

IO33NB2F2

IO33PB2F2

IO34NB2F2

IO34PB2F2

IO35NB2F2

IO35PB2F2

IO36NB2F2

IO36PB2F2

IO37NB2F2

IO37PB2F2

IO38NB2F2

IO38PB2F2

IO39NB2F2

IO39PB2F2

IO41NB2F2

IO41PB2F2

IO42NB2F2

IO42PB2F2

IO43NB2F2

IO43PB2F2

IO44NB2F2

IO44PB2F2

261

262

259

260

255

256

249

250

253

254

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO04NB0F0

IO04PB0F0

IO06NB0F0

IO06PB0F0

IO08NB0F0

IO08PB0F0

IO10NB0F0

IO10PB0F0

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

305

306

299

300

289

290

295

296

287

288

283

284

277

278

281

282

275

276

IO16PB1F1

IO17NB1F1

IO17PB1F1

IO18NB1F1

Bank 4

IO18PB1F1

IO62NB4F4

IO62PB4F4

IO64NB4F4

IO64PB4F4

IO65NB4F4

IO65PB4F4

IO66NB4F4

IO66PB4F4

IO67NB4F4

172

173

166

167

170

171

164

165

160

IO20NB1F1

IO20PB1F1

IO22NB1F1

IO22PB1F1

IO23NB1F1

Bank 3

IO23PB1F1

IO45NB3F3

IO45PB3F3

IO46NB3F3

217

218

219

IO24NB1F1

IO24PB1F1

v5.3

3-9

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX250S/SL Function Number

IO67PB4F4

IO68NB4F4

161

158

159

154

155

152

153

146

147

142

143

136

137

IO90PB6F6

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO93NB6F6

IO93PB6F6

IO95NB6F6

IO95PB6F6

IO96NB6F6

IO96PB6F6

IO97NB6F6

IO97PB6F6

IO98NB6F6

IO98PB6F6

IO99NB6F6

IO99PB6F6

IO100NB6F6

IO100PB6F6

IO101NB6F6

IO101PB6F6

IO103NB6F6

IO103PB6F6

IO104NB6F6

IO104PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

Bank 7

IO110PB7F7

IO111NB7F7

IO111PB7F7

IO113NB7F7

IO113PB7F7

IO114NB7F7

IO114PB7F7

IO115NB7F7

IO115PB7F7

IO116NB7F7

IO116PB7F7

IO117NB7F7

IO117PB7F7

IO118NB7F7

IO118PB7F7

IO119NB7F7

IO119PB7F7

IO121NB7F7

IO121PB7F7

IO123NB7F7

IO123PB7F7

IO68PB4F4

IO70NB4F4

IO70PB4F4

IO72NB4F4

IO72PB4F4

IO73NB4F4

IO73PB4F4

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

IO76NB5F5/CLKGN

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

128

129

122

123

112

113

118

119

110

111

106

107

100

101

104

105

IO78PB5F5

IO79NB5F5

IO79PB5F5

Dedicated I/O

IO80NB5F5

GND

IO80PB5F5

IO82NB5F5

IO82PB5F5

IO84NB5F5

IO84PB5F5

IO85NB5F5

IO85PB5F5

IO86NB5F5

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO109NB7F7

IO109PB7F7

IO110NB7F7

IO86PB5F5

IO87NB5F5

IO87PB5F5

IO89NB5F5

IO89PB5F5

Bank 6

3-10

v5.3

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX250S/SL Function Number

GND

PRA

PRB

PRC

PRD

TCK

334

340

345

352

TDI

348

347

350

351

TDO

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

240

246

252

258

264

265

274

280

286

292

298

310

322

330

TMS

TRST

V_CCA

V_CCDA

117

124

125

126

127

130

131

138

139

140

141

148

174

268

294

301

302

303

304

307

308

315

316

317

318

327

328

312

311

135

134

349

102

114

150

162

175

191

209

233

251

263

279

291

329

339

116

132

149

178

221

266

293

309

346

321

_CCIB0

v5.3

3-11

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX250S/SL Function Number

V_CCIB0

333

344

273

285

297

227

239

245

257

185

V_CCIB3

197

203

215

144

156

168

V_CCIB6

_CCIB0

_CCIB1

_CCIB3

_CCIB4

_CCIB6

V_CCIB1

V_CCIB4

V_CCIB7

_CCIB2

_CCIB3

_CCIB4

_CCIB5

_CCIB7

267

108

120

V_PUMP

3-12

v5.3

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX1000S/SL Function Number

Bank 0

IO61NB1F5

IO61PB1F5

IO63NB1F5

IO63PB1F5

271

272

269

270

IO97PB3F9

IO99NB3F9

220

213

214

211

212

207

208

205

206

199

200

201

202

195

196

193

194

189

190

183

184

187

188

181

182

179

180

IO02NB0F0

IO02PB0F0

341

342

343

337

338

331

332

335

336

325

326

323

324

319

320

313

314

IO99PB3F9

IO03PB0F0

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO111NB3F10

IO111PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO127NB3F11

IO127PB3F11

IO128NB3F11

IO128PB3F11

IO04NB0F0

Bank 2

IO04PB0F0

IO64NB2F6

IO64PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

259

260

261

262

255

256

253

254

249

250

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO24NB0F2

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO38NB1F3

305

306

299

300

295

296

287

288

289

290

281

282

283

284

277

278

275

276

IO38PB1F3

IO54NB1F5

IO54PB1F5

IO55NB1F5

Bank 4

IO55PB1F5

IO130NB4F12

IO130PB4F12

IO131NB4F12

IO131PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO134NB4F12

172

173

170

171

166

167

164

165

160

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO59NB1F5

Bank 3

IO59PB1F5

IO96NB3F9

IO96PB3F9

IO97NB3F9

217

218

219

IO60NB1F5

IO60PB1F5

v5.3

3-13

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX1000S/SL Function Number

IO134PB4F12

IO136NB4F12

IO136PB4F12

161

158

159

154

155

152

153

146

147

142

143

136

137

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO223NB6F20

IO223PB6F20

IO224NB6F20

IO224PB6F20

IO238PB7F22

IO240NB7F22

IO240PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

IO137NB4F12

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO153NB4F14

IO153PB4F14

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO167NB5F15

IO167PB5F15

128

129

122

123

118

119

110

111

112

113

104

105

106

107

IO183NB5F17

IO183PB5F17

Dedicated I/O

IO184NB5F17

IO184PB5F17

GND

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

IO187NB5F17

IO187PB5F17

Bank 7

IO188NB5F17

IO188PB5F17

100

101

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO190NB5F17

IO190PB5F17

IO192NB5F17

IO192PB5F17

Bank 6

3-14

v5.3

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX1000S/SL Function Number

GND

334

340

345

352

V_CCA

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

240

246

252

258

264

265

274

280

286

292

298

310

322

330

V_CCA

124

125

126

127

130

131

138

139

140

141

174

268

301

302

303

304

307

308

315

316

317

318

312

311

135

134

349

348

347

350

351

V_CCA

102

114

150

162

175

191

209

233

251

263

279

291

329

339

V_CCA

V_CCDA

116

117

132

148

149

178

221

266

293

294

309

327

328

346

321

PRA

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

V_CCA

_CCIB0

v5.3

3-15

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX1000S/SL Function Number

V_CCIB0

333

344

273

285

297

227

239

245

257

185

V_CCIB3

197

203

215

144

156

168

V_CCIB6

V_CCIB0

V_CCIB1

_CCIB3

_CCIB4

_CCIB6

V_CCIB1

V_CCIB4

V_CCIB7

V_CCIB2

V_CCIB3

_CCIB4

_CCIB5

_CCIB7

267

108

120

V_PUMP

3-16

v5.3

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX2000S/SL Function Number

Bank 0

IO73NB1F6

IO73PB1F6

IO74NB1F6

IO74PB1F6

269

270

271

272

IO132PB3F12

IO137NB3F12

IO137PB3F12

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

IO161NB3F15

IO161PB3F15

IO163NB3F15

IO163PB3F15

IO165NB3F15

IO165PB3F15

IO167NB3F15

IO167PB3F15

218

213

214

211

212

205

206

207

208

199

200

201

202

193

194

195

196

189

190

183

184

187

188

181

182

179

180

IO01NB0F0

IO01PB0F0

341

342

343

337

338

335

336

331

332

325

326

323

324

319

320

313

314

IO02PB0F0

IO04NB0F0

Bank 2

IO04PB0F0

IO87NB2F8

IO87PB2F8

261

262

255

256

259

260

253

254

249

250

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO05NB0F0

IO05PB0F0

IO88NB2F8

IO08NB0F0

IO88PB2F8

IO08PB0F0

IO89NB2F8

IO37NB0F3

IO89PB2F8

IO37PB0F3

IO91NB2F8

IO38NB0F3

IO91PB2F8

IO38PB0F3

IO99NB2F9

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

IO99PB2F9

IO100NB2F9

IO100PB2F9

IO107NB2F10

IO107PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO48NB1F4

305

306

299

300

295

296

283

284

289

290

287

288

275

276

281

282

277

278

IO48PB1F4

IO65NB1F6

IO65PB1F6

IO66NB1F6

Bank 4

IO66PB1F6

IO181NB4F17

IO181PB4F17

IO182NB4F17

IO182PB4F17

IO183NB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

172

173

170

171

166

167

164

165

160

IO68NB1F6

IO68PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

Bank 3

IO70PB1F6

IO129NB3F12

IO129PB3F12

IO132NB3F12

219

220

217

IO71NB1F6

IO71PB1F6

v5.3

3-17

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX2000S/SL Function Number

IO185PB4F17

IO190NB4F17

IO190PB4F17

161

158

159

154

155

152

153

146

147

142

143

136

137

IO257PB6F24

IO258NB6F24

IO258PB6F24

IO261NB6F24

IO261PB6F24

IO262NB6F24

IO262PB6F24

IO265NB6F24

IO265PB6F24

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO294NB6F27

IO294PB6F27

IO296NB6F27

IO296PB6F27

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

IO320PB7F29

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO338NB7F31

IO338PB7F31

IO341NB7F31

IO341PB7F31

IO191NB4F17

IO191PB4F17

IO192NB4F17

IO192PB4F17

IO207NB4F19

IO207PB4F19

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO217NB5F20

IO217PB5F20

128

129

122

123

118

119

110

111

112

113

104

105

106

107

100

101

IO236NB5F22

IO236PB5F22

Dedicated I/O

IO237NB5F22

IO237PB5F22

GND

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO240PB5F22

Bank 7

IO242NB5F22

IO242PB5F22

IO300NB7F28

IO300PB7F28

IO303NB7F28

IO303PB7F28

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

Bank 6

3-18

v5.3

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX2000S/SL Function Number

GND

334

340

345

352

124

125

126

127

138

139

140

141

301

302

303

304

315

316

317

318

312

311

135

134

349

348

347

350

351

V_CCA

150

162

175

191

209

233

251

263

279

291

329

339

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

240

246

252

258

264

265

274

280

286

292

298

310

322

330

V_CCA

V_CCDA

116

117

130

131

132

148

149

174

178

221

266

268

293

294

307

308

309

327

328

346

321

PRA

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

V_CCA

102

114

_CCIB0

v5.3

3-19

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX2000S/SL Function Number

V_CCIB0

333

344

273

285

297

227

239

245

257

185

V_CCIB3

197

203

215

144

156

168

V_CCIB6

V_CCIB0

V_CCIB1

_CCIB3

_CCIB4

_CCIB6

V_CCIB1

V_CCIB4

V_CCIB7

V_CCIB2

V_CCIB3

_CCIB4

_CCIB5

_CCIB7

267

108

120

V_PUMP

3-20

v5.3

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX4000S Function Pin Number

Bank 0

352-Pin CQFP

RTAX4000S Function Pin Number

IO104PB2F12

IO106NB2F12

IO106PB2F12

IO107NB2F12

IO107PB2F12

IO111NB2F12

IO111PB2F12

IO139NB2F16

IO139PB2F16

IO140NB2F16

IO140PB2F16

IO141NB2F16

IO141PB2F16

IO142NB2F16

IO142PB2F16

IO143NB2F16

IO143PB2F16

IO144NB2F16

IO144PB2F16

IO145NB2F16

IO145PB2F16

IO146NB2F16

IO146PB2F16

260

253

254

257

258

251

252

241

242

245

246

235

236

239

240

229

230

233

234

223

224

227

228

IO182PB3F20

IO183NB3F20

IO183PB3F20

IO203NB3F23

IO203PB3F23

IO204NB3F23

IO204PB3F23

IO206NB3F23

IO206PB3F23

IO209NB3F23

IO209PB3F23

200

195

196

189

190

183

184

187

188

181

182

IO02NB0F0

IO02PB0F0

341

342

343

337

338

335

336

331

332

329

330

317

318

313

314

IO03PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO11NB0F0

IO11PB0F0

Bank 4

IO50NB0F4/HCLKAN

IO50PB0F4/HCLKAP

IO51NB0F4/HCLKBN

IO51PB0F4/HCLKBP

Bank 1

IO210NB4F24

IO210PB4F24

167

168

173

171

172

161

162

165

166

155

156

159

160

153

154

141

142

137

138

IO211NB4F24

IO213NB4F24

IO213PB4F24

IO52NB1F6/HCLKCN

IO52PB1F6/HCLKCP

IO53NB1F6/HCLKDN

IO53PB1F6/HCLKDP

IO94NB1F10

303

304

299

300

287

288

281

282

285

286

275

276

279

280

273

274

269

270

IO214NB4F24

IO214PB4F24

IO215NB4F24

IO215PB4F24

IO216NB4F24

IO94PB1F10

IO216PB4F24

IO97NB1F10

Bank 3

IO217NB4F24

IO97PB1F10

IO175NB3F20

IO175PB3F20

IO176NB3F20

IO176PB3F20

IO177NB3F20

IO177PB3F20

IO178NB3F20

IO178PB3F20

IO179NB3F20

IO179PB3F20

IO181NB3F20

IO181PB3F20

IO182NB3F20

213

214

217

218

207

208

211

212

205

206

201

202

199

IO217PB4F24

IO98NB1F10

IO219NB4F24

IO98PB1F10

IO219PB4F24

IO99NB1F10

IO260NB4F28/CLKEN

IO260PB4F28/CLKEP

IO261NB4F28/CLKFN

IO261PB4F28/CLKFP

Bank 5

IO99PB1F10

IO100NB1F10

IO100PB1F10

IO102NB1F10

IO102PB1F10

IO103NB1F10

IO103PB1F10

Bank 2

IO262NB5F30/CLKGN

IO262PB5F30/CLKGP

IO263NB5F30/CLKHN

IO263PB5F30/CLKHP

IO304NB5F34

127

128

123

124

111

IO104NB2F12

259

v5.3

3-21

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX4000S Function Pin Number

IO304PB5F34

IO305NB5F34

IO305PB5F34

IO307NB5F34

IO307PB5F34

IO308NB5F34

IO308PB5F34

IO309NB5F34

IO309PB5F34

IO310NB5F34

IO310PB5F34

IO312NB5F34

IO312PB5F34

IO313NB5F34

112

109

110

103

104

105

106

IO356PB6F40

Bank 7

GND

IO385NB7F44

IO385PB7F44

IO386NB7F44

IO386PB7F44

IO387NB7F44

IO387PB7F44

IO388NB7F44

IO388PB7F44

IO389NB7F44

IO389PB7F44

IO391NB7F44

IO391PB7F44

IO392NB7F44

IO392PB7F44

IO393NB7F44

IO393PB7F44

IO413NB7F47

IO413PB7F47

IO414NB7F47

IO414PB7F47

IO416NB7F47

IO416PB7F47

IO419NB7F47

IO419PB7F47

100

102

108

117

119

126

132

134

140

147

149

158

164

170

176

177

180

186

192

194

198

204

210

216

220

222

Bank 6

IO314PB6F36

IO316NB6F36

IO316PB6F36

IO317NB6F36

IO317PB6F36

IO319NB6F36

IO319PB6F36

IO349NB6F40

IO349PB6F40

IO350NB6F40

IO350PB6F40

IO351NB6F40

IO351PB6F40

IO352NB6F40

IO352PB6F40

IO353NB6F40

IO353PB6F40

IO354NB6F40

IO354PB6F40

IO355NB6F40

IO355PB6F40

IO356NB6F40

Dedicated I/O

GND

3-22

v5.3

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX4000S Function Pin Number

GND

PRA

226

232

238

244

248

250

256

262

264

265

272

278

284

293

295

302

308

310

316

323

325

334

340

345

352

312

311

136

135

349

348

347

350

351

V_CCA

V_CCDA

120

121

122

130

133

143

144

145

146

150

151

152

174

178

191

221

249

266

268

289

290

291

294

296

297

298

306

309

319

320

321

322

326

327

328

346

315

101

116

129

131

148

163

175

179

193

209

219

231

247

261

263

277

292

305

307

324

339

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

V_CCA

113

114

115

118

V_CCIB0

v5.3

3-23

RTAX-S/SL RadTolerant FPGAs

352-Pin CQFP

RTAX4000S Function Pin Number

V_CCIB0

333

344

271

283

301

225

237

243

255

185

V_CCIB3

197

203

215

139

157

169

V_CCIB6

267

_CCIB1

_CCIB2

_CCIB3

_CCIB4

_CCIB6

_CCIB7

V_CCIB2

V_CCIB5

V_CCIB7

_CCIB7

V_PUMP

_CCIB2

_CCIB3

_CCIB5

107

125

3-24

v5.3

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8 7 6 5 4 3 2 1

Figure 3-4 • 624-Pin CCGA/LGA (Bottom View)

Note:

The 624-pin CCGA/LGA pin assignments for both RTAX1000S/SL and RTAX2000S/SL are compatible except for the

following seven pins: A14, AA20, AB13, AD4, AE12, F21, G10. On the RTAX1000S/SL, these pins are no connects (NC),

and for RTAX2000S/SL these pins are assigned to V_CCDA. Customers are therefore recommend to layout their board

targeting the RTAX2000S/SL device, in order to preserve interchangeability between the two devices.

For Package Manufacturing and Environmental information, visit the Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

v5.3

3-25

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX1000S/SL Function Number

Bank 0

IO23NB0F2

IO23PB0F2

E11

F11

IO42NB1F4

IO42PB1F4

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO53NB1F4

IO53PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO58NB1F5

IO58PB1F5

IO60NB1F5

IO60PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

G21

G20

A16

A15

A20

A19

B17

B16

G17

H17

A17

C19

C18

B20

B19

H20

H19

A22

A21

C21

C20

B22

B21

J18

IO00NB0F0

IO00PB0F0

IO02NB0F0

IO02PB0F0

IO04NB0F0

IO04PB0F0

IO06NB0F0

IO06PB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO24NB0F2

IO24PB0F2

IO25PB0F2

B12

H11

G11

C11

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

J13

K13

F10

IO28PB0F2

IO29NB0F2

D10

IO29PB0F2

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

G13

G12

C13

C12

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO34NB1F3

G15

G14

B14

B13

G16

H16

C17

B18

H18

H15

H13

E15

F15

IO34PB1F3

IO35NB1F3

J19

IO35PB1F3

D18

D17

F20

IO36NB1F3

IO36PB1F3

D12

D11

B11

B10

A11

A10

H10

IO37NB1F3

F19

IO38NB1F3

E17

F17

IO38PB1F3

IO39NB1F3

D14

C14

D16

D15

F16

D20

D19

E18

F18

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F4

G19

3-26

v5.3

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX1000S/SL Function Number

IO63PB1F5

Bank 2

G18

IO84NB2F7

IO84PB2F7

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

M20

M21

E25

D25

L24

IO105NB3F9

IO105PB3F9

R23

P23

IO64NB2F6

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

IO72NB2F6

IO72PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

M17

G22

J21

IO106NB3F9

IO106PB3F9

R19

R20

IO107NB3F10

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO110NB3F10

IO110PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO120NB3F11

IO120PB3F11

IO122NB3F11

IO122PB3F11

IO124NB3F11

IO124PB3F11

IO126NB3F11

IO126PB3F11

IO128NB3F11

IO128PB3F11

AB24

R25

J20

K24

G24

F24

L23

P25

K20

F23

U25

T25

J25

E23

L18

G25

F25

U24

U23

T24

K18

E24

D24

H23

G23

L19

L25

K25

J24

R24

Y25

W25

V23

V24

AA24

Y24

AB25

AA25

T20

H24

J23

N24

M24

N25

M25

K19

J22

H22

N23

M23

N17

N16

L22

Bank 3

IO96NB3F9

IO96PB3F9

IO97NB3F9

IO97PB3F9

IO98NB3F9

IO98PB3F9

IO99NB3F9

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

IO104NB3F9

IO104PB3F9

T18

R18

N20

P24

P20

P19

P21

T22

W24

R22

P22

U19

T19

V20

U20

R21

W22

W23

V22

U22

Y23

AA23

V21

U21

Y22

Y21

K22

M19

M18

N19

N18

L21

L20

P18

P17

N22

M22

Bank 4

IO129NB4F12

IO129PB4F12

W20

Y20

v5.3

3-27

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX1000S/SL Function Number

IO131NB4F12

IO131PB4F12

IO133NB4F12

IO133PB4F12

IO135NB4F12

IO135PB4F12

IO137NB4F12

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

IO141PB4F13

IO142NB4F13

IO142PB4F13

IO143NB4F13

IO143PB4F13

IO144PB4F13

IO145NB4F13

IO145PB4F13

IO146NB4F13

IO146PB4F13

IO147NB4F13

IO147PB4F13

IO148PB4F13

IO149NB4F13

IO149PB4F13

IO150NB4F13

IO150PB4F13

IO151NB4F13

IO151PB4F13

IO152NB4F14

IO152PB4F14

V19

W19

Y18

IO153NB4F14

IO153PB4F14

Y15

Y16

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO177NB5F16

IO177PB5F16

IO178NB5F16

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO182NB5F17

IO182PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO189NB5F17

IO189PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

Y11

AB10

AB11

AC9

AE9

AA8

IO155NB4F14

V15

Y19

IO155PB4F14

V16

W18

V18

IO156NB4F14

AB14

AB15

AE14

AC18

AC15

AC19

W14

W15

AC13

AD13

IO156PB4F14

Y17

IO157NB4F14

AA17

AB19

AB18

AA19

U18

IO157PB4F14

IO158NB4F14

IO158PB4F14

Y10

W10

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

AC20

AC21

AD17

AD18

AD21

AD22

AB17

AC17

AE22

AE15

AE16

AD19

AD20

AD15

AD16

AE21

AD14

AC14

AE19

AE20

V17

AD9

AD10

AE10

AE11

AD7

AD8

AB9

AE6

AE7

AE4

AE5

AA9

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

W13

Y13

AC12

AD12

IO163PB5F15

V10

V11

T13

IO164NB5F15

IO164PB5F15

IO165NB5F15

U13

V13

W11

W12

AB6

AA6

IO165PB5F15

IO167NB5F15

IO167PB5F15

IO168NB5F15

AD5

AD6

AC5

AC6

AB7

AC7

IO168PB5F15

IO169NB5F15

IO169PB5F15

IO171NB5F16

IO171PB5F16

W17

AB16

W16

IO172NB5F16

AB8

AC8

AA11

Bank 6

IO172PB5F16

IO193NB6F18

IO193PB6F18

IO173NB5F16

3-28

v5.3

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX1000S/SL Function Number

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO199NB6F18

IO199PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO210NB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO215NB6F20

AA3

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO223NB6F20

IO223PB6F20

IO224NB6F20

IO224PB6F20

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO239NB7F22

IO239PB7F22

IO240NB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO243NB7F22

IO243PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO249NB7F23

IO249PB7F23

IO251NB7F23

IO251PB7F23

IO253NB7F23

IO253PB7F23

IO255NB7F23

IO255PB7F23

IO257NB7F23

IO257PB7F23

Bank 7

AA1

AB1

IO225NB7F21

IO225PB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

N10

AA2

AB2

Dedicated I/O

GND

A18

A24

A25

v5.3

3-29

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX1000S/SL Function Number

GND

AA10

AA16

AA18

AA21

AA5

AB22

AB4

AC10

AC16

AC23

AC3

AD1

AD2

AD24

AD25

AE1

GND

V25

H21

H25

K21

K23

A14

AA12

AA14

AA20

AB13

AD4

AE12

E12

E14

F12

L11

L12

L13

L14

L15

M11

M12

M13

M14

M15

N11

N12

N13

N14

N15

P11

P12

P13

P14

P15

R11

R12

R13

R14

R15

T21

T23

F14

F21

G10

H12

H14

J12

AE18

AE2

AE24

AE25

AE8

J14

U12

U14

V12

V14

Y12

Y14

F13

B24

B25

C10

C16

C23

PRA

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

V_CCA

A13

AB12

AE13

D22

E10

E16

E21

AB20

3-30

v5.3

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX1000S/SL Function Number

V_CCA

F22

V_CCIB0

V_CCIB5

AC4

AD3

AE3

T12

U10

U11

AA4

AB3

AC1

AC2

P10

_CCIB0

_CCIB1

_CCIB2

_CCIB3

_CCIB4

_CCIB5

_CCIB6

_CCIB7

V_CCA

J17

V_CCA

K10

K11

K15

K16

L10

L16

R10

R16

T10

T11

T15

T16

U17

J10

V_CCA

J11

V_CCA

K12

A23

B23

C22

D21

J15

V_CCA

J16

V_CCA

K14

C24

C25

D23

E22

V_CCA

K17

L17

V_CCDA

A12

AA13

AA15

AA7

AC11

AD11

AE17

B15

C15

M10

E20

M16

AA22

AB23

AC24

AC25

P16

V_PUMP

R17

T17

AB21

AC22

AD23

AE23

T14

D13

E13

E19

N21

U15

U16

AB5

W21

v5.3

3-31

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX2000S/SL Function Number

Bank 0

IO30NB0F2

IO30PB0F2

B11

B10

E11

F11

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO65NB1F6

IO66PB1F6

IO67NB1F6

IO67PB1F6

IO68NB1F6

IO68PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO70PB1F6

IO71PB1F6

IO73NB1F6

IO74NB1F6

IO74PB1F6

IO75NB1F6

IO75PB1F6

IO76NB1F7

IO76PB1F7

IO79NB1F7

IO79PB1F7

IO80NB1F7

IO80PB1F7

IO81NB1F7

IO81PB1F7

IO82NB1F7

IO82PB1F7

IO85NB1F7

D15

A22

A21

F16

G17

H17

B17

B16

H18

C17

B18

J18

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO11NB0F0

IO11PB0F0

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20PB0F1

IO23NB0F2

IO23PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

IO28PB0F2

IO31NB0F2

IO31PB0F2

IO33NB0F2

D12

D11

A11

A10

J13

IO33PB0F2

IO34NB0F3

IO34PB0F3

IO37NB0F3

IO37PB0F3

K13

H11

G11

B12

G13

G12

C13

C12

IO38NB0F3

IO38PB0F3

IO40PB0F3

J19

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

B20

B19

E17

F17

B22

B21

G18

G19

C19

C18

D18

D17

C21

C20

H20

H19

E18

F18

G21

G20

F20

F19

D20

D10

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO45NB1F4

G15

G14

B14

B13

H13

D14

C14

A16

A15

H15

E15

F15

IO47NB1F4

IO47PB1F4

IO48NB1F4

IO48PB1F4

IO49PB1F4

F10

IO51NB1F4

IO51PB1F4

C11

IO52NB1F4

A17

G16

H16

A20

A19

D16

IO55NB1F5

H10

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

3-32

v5.3

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX2000S/SL Function Number

IO85PB1F7

Bank 2

D19

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

IO118NB2F11

IO121NB2F11

IO121PB2F11

IO122NB2F11

IO122PB2F11

IO123NB2F11

IO123PB2F11

IO124NB2F11

IO124PB2F11

IO127NB2F11

IO127PB2F11

IO128NB2F11

IO128PB2F11

L24

K24

N17

M20

M21

N19

N18

J25

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO153NB3F14

IO153PB3F14

IO154NB3F14

IO154PB3F14

IO157NB3F14

IO157PB3F14

IO158NB3F14

IO158PB3F14

IO160PB3F14

IO161NB3F15

IO161PB3F15

IO162NB3F15

IO162PB3F15

IO163NB3F15

IO163PB3F15

IO164NB3F15

IO164PB3F15

IO166NB3F15

IO167NB3F15

IO167PB3F15

IO168NB3F15

IO168PB3F15

IO169NB3F15

IO169PB3F15

IO170NB3F15

IO170PB3F15

T24

R24

IO86NB2F8

IO86PB2F8

F23

E23

H23

G23

E24

D24

M17

G22

J22

T20

R20

IO87NB2F8

IO87PB2F8

U25

T25

IO88NB2F8

IO88PB2F8

T22

U19

T19

IO89NB2F8

IO89PB2F8

N24

M24

L25

Y25

W25

V20

U20

AB25

AA25

W24

U24

U23

AA24

Y24

V22

U22

V23

V24

AB24

V21

U21

Y23

AA23

W22

W23

Y22

Y21

IO91NB2F8

IO91PB2F8

H22

L18

K18

G24

F24

J21

K25

N22

M22

N23

M23

P18

IO92NB2F8

IO92PB2F8

IO96NB2F9

IO96PB2F9

IO97NB2F9

IO97PB2F9

J20

P17

IO98PB2F9

J23

N25

M25

IO99NB2F9

IO99PB2F9

L19

K19

E25

D25

K20

M19

M18

J24

Bank 3

IO100NB2F9

IO100PB2F9

IO103PB2F9

IO105NB2F9

IO105PB2F9

IO106NB2F9

IO106PB2F9

IO107NB2F10

IO107PB2F10

IO109NB2F10

IO109PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO129NB3F12

IO130PB3F12

IO131NB3F12

IO133NB3F12

IO133PB3F12

IO138NB3F12

IO138PB3F12

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO142NB3F13

IO142PB3F13

IO143PB3F13

IO145NB3F13

IO145PB3F13

N20

P24

P21

P20

P19

R23

P23

R22

P22

R19

R25

P25

R21

T18

R18

H24

L23

N16

L22

K22

G25

F25

L21

L20

Bank 4

IO171NB4F16

IO171PB4F16

AC20

AC21

v5.3

3-33

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX2000S/SL Function Number

IO172NB4F16

IO172PB4F16

IO173NB4F16

IO173PB4F16

IO174NB4F16

IO176NB4F16

IO176PB4F16

IO177NB4F16

IO177PB4F16

IO182NB4F17

IO182PB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO187PB4F17

IO188NB4F17

IO188PB4F17

IO189PB4F17

IO191NB4F17

IO191PB4F17

IO192PB4F17

IO195PB4F18

IO196NB4F18

IO197NB4F18

IO197PB4F18

IO198NB4F18

IO198PB4F18

IO199NB4F18

IO199PB4F18

IO200NB4F18

IO201NB4F18

IO201PB4F18

IO202NB4F18

IO202PB4F18

W20

Y20

IO206NB4F19

IO206PB4F19

AB14

AB15

AE15

AE16

W16

AE14

V15

IO229PB5F21

IO230NB5F21

IO233NB5F21

IO233PB5F21

IO234NB5F21

IO234PB5F21

IO236NB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO246NB5F23

IO246PB5F23

IO247NB5F23

IO247PB5F23

IO250NB5F23

IO250PB5F23

IO251NB5F23

IO251PB5F23

IO252NB5F23

IO252PB5F23

IO253NB5F23

IO253PB5F23

IO254NB5F23

IO254PB5F23

IO256NB5F23

IO256PB5F23

AD10

V11

AD7

AD8

AD21

AD22

AA19

Y18

IO207NB4F19

IO207PB4F19

IO208PB4F19

IO209NB4F19

V10

AC9

Y19

IO210NB4F19

AB19

AB18

V19

IO210PB4F19

V16

IO211NB4F19

AD14

AC14

W14

W15

AC13

AD13

IO211PB4F19

AE4

AE5

AB9

AA9

W19

AC19

AB17

AC17

AD19

AD20

AC18

Y17

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

AD5

AD6

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO216NB5F20

W13

Y13

AC12

AD12

U13

AB8

AC8

AB7

AC7

AA8

AA17

AE22

W18

V18

IO216PB5F20

V13

IO217NB5F20

AE10

AE11

W11

W12

AA11

Y11

U18

IO217PB5F20

AE21

AB16

AD17

AD18

V17

IO218NB5F20

IO218PB5F20

IO222NB5F20

IO222PB5F20

IO223PB5F21

AE9

AC5

AC6

W17

AE19

AE20

AC15

AD15

AD16

Y15

IO225NB5F21

AE6

IO225PB5F21

AE7

IO226NB5F21

Y10

IO226PB5F21

W10

T13

AB6

AA6

IO227PB5F21

IO228NB5F21

AB10

AB11

AD9

Bank 6

IO228PB5F21

IO257NB6F24

IO257PB6F24

Y16

IO229NB5F21

AA3

3-34

v5.3

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX2000S/SL Function Number

IO258NB6F24

IO258PB6F24

IO259NB6F24

IO259PB6F24

IO260NB6F24

IO260PB6F24

IO262NB6F24

IO262PB6F24

IO263NB6F24

IO263PB6F24

IO268NB6F25

IO268PB6F25

IO269PB6F25

IO272NB6F25

IO272PB6F25

IO273NB6F25

IO273PB6F25

IO274NB6F25

IO274PB6F25

IO275NB6F25

IO275PB6F25

IO277NB6F25

IO278NB6F26

IO278PB6F26

IO279PB6F26

IO280NB6F26

IO281NB6F26

IO281PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

AA2

AB2

IO288NB6F26

IO290NB6F27

IO291NB6F27

IO291PB6F27

IO292NB6F27

IO292PB6F27

IO293NB6F27

IO293PB6F27

IO294NB6F27

IO296NB6F27

IO296PB6F27

IO298NB6F27

IO298PB6F27

IO299NB6F27

IO299PB6F27

IO321NB7F30

IO321PB7F30

IO323NB7F30

IO323PB7F30

IO324NB7F30

IO324PB7F30

IO327NB7F30

IO327PB7F30

IO328NB7F30

IO328PB7F30

IO329NB7F30

IO329PB7F30

IO331PB7F30

IO332NB7F31

IO332PB7F31

IO333NB7F31

IO333PB7F31

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO337NB7F31

IO338NB7F31

IO338PB7F31

IO339NB7F31

IO339PB7F31

IO340NB7F31

IO340PB7F31

IO341NB7F31

IO341PB7F31

Bank 7

IO300NB7F28

IO300PB7F28

IO302NB7F28

IO304NB7F28

IO304PB7F28

IO308NB7F28

IO309NB7F28

IO309PB7F28

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO313NB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

N10

AA1

AB1

Dedicated I/O

GND

A18

A24

A25

v5.3

3-35

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX2000S/SL Function Number

GND

AA10

AA16

AA18

AA21

AA5

AB22

AB4

AC10

AC16

AC23

AC3

AD1

AD2

AD24

AD25

AE1

GND

V25

H21

H25

K21

K23

AA12

AA14

E12

E14

F12

F14

H12

H14

J12

L11

L12

L13

L14

L15

M11

M12

M13

M14

M15

N11

N12

N13

N14

N15

P11

P12

P13

P14

P15

R11

R12

R13

R14

R15

T21

T23

J14

U12

U14

V12

V14

Y12

Y14

F13

A13

AB12

AE13

AE18

AE2

AE24

AE25

AE8

PRA

PRB

PRC

PRD

TCK

TDI

B24

B25

TDO

TMS

TRST

V_CCA

C10

C16

C23

AB20

F22

D22

J17

E10

E16

K10

K11

K15

E21

3-36

v5.3

RTAX-S/SL RadTolerant FPGAs

624-Pin CCGA/LGA

RTAX2000S/SL Function Number

V_CCA

K16

L10

V_CCIB0

V_CCIB5

AC4

AD3

AE3

T12

U10

U11

AA4

AB3

AC1

AC2

P10

_CCIB0

_CCIB1

_CCIB2

_CCIB3

_CCIB4

_CCIB5

_CCIB6

_CCIB7

V_CCA

L16

V_CCA

R10

R16

T10

V_CCA

J10

V_CCA

J11

V_CCA

T11

K12

A23

B23

C22

D21

J15

V_CCA

T15

V_CCA

T16

V_CCA

U17

V_CCA

V_CCDA

A12

A14

AA13

AA15

AA20

AA7

AB13

AC11

AD11

AD4

AE12

AE17

B15

C15

J16

K14

C24

C25

D23

E22

K17

L17

M10

E20

M16

AA22

AB23

AC24

AC25

P16

V_PUMP

R17

T17

D13

E13

AB21

AC22

AD23

AE23

T14

E19

F21

G10

N21

U15

U16

AB5

W21

v5.3

3-37

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Figure 3-5 • 1152-Pin CCGA/LGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit the Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

3-38

v5.3

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL

Function

Number

Function

Number

Function

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO23NB0F2

IO23PB0F2

IO24NB0F2

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

IO28PB0F2

IO29NB0F2

IO29PB0F2

IO30NB0F2

IO30PB0F2

IO31NB0F2

IO31PB0F2

IO32NB0F2

IO32PB0F2

IO33NB0F2

IO33PB0F2

IO34NB0F3

IO34PB0F3

IO35NB0F3

IO35PB0F3

IO36NB0F3

Number

E11

E10

F13

Bank 0

IO36PB0F3

IO37NB0F3

A16

G16

G15

D16

C16

K16

L16

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO37PB0F3

H10

G13

A10

IO38NB0F3

IO38PB0F3

IO39NB0F3

K14

K13

B11

B10

C12

C11

A12

A11

H14

J14

IO39PB0F3

IO40NB0F3

D17

C17

E16

F16

IO40PB0F3

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

K10

J10

G17

F17

F10

G10

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO45NB1F4

G19

G18

E19

F19

C18

D18

A18

B18

K19

L19

C19

D19

K20

L20

A19

B19

H20

J20

D13

D12

F14

J11

K11

G14

E14

E13

B13

B12

C14

C13

H15

J15

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

K12

J12

G11

H11

G12

H12

IO47PB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

A14

B14

K15

L15

IO50NB1F4

IO50PB1F4

IO51NB1F4

H13

J13

IO51PB1F4

D15

D14

A15

B15

B16

IO52NB1F4

B20

A20

F20

E20

B21

IO52PB1F4

IO53NB1F4

F12

F11

IO53PB1F4

IO54NB1F5

v5.3

3-39

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL Pin

RTAX2000S/SL

Function

Number

A21

K21

J21

Function

IO73NB1F6

IO73PB1F6

IO74NB1F6

IO74PB1F6

IO75NB1F6

IO75PB1F6

IO76NB1F7

IO76PB1F7

IO77NB1F7

IO77PB1F7

IO78NB1F7

IO78PB1F7

IO79NB1F7

IO79PB1F7

IO80NB1F7

IO80PB1F7

IO81NB1F7

IO81PB1F7

IO82NB1F7

IO82PB1F7

IO83NB1F7

IO83PB1F7

IO84NB1F7

IO84PB1F7

IO85NB1F7

IO85PB1F7

Number

Function

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

IO96NB2F9

IO96PB2F9

IO97NB2F9

IO97PB2F9

IO98NB2F9

IO98PB2F9

IO99NB2F9

IO99PB2F9

IO100NB2F9

IO100PB2F9

IO101NB2F9

IO101PB2F9

IO102NB2F9

IO102PB2F9

IO103NB2F9

IO103PB2F9

IO104NB2F9

IO104PB2F9

IO105NB2F9

IO105PB2F9

IO106NB2F9

IO106PB2F9

IO107NB2F10

IO107PB2F10

IO108NB2F10

IO108PB2F10

IO109NB2F10

Number

K28

K27

J30

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

IO64NB1F6

IO64PB1F6

IO65NB1F6

IO65PB1F6

IO66NB1F6

IO66PB1F6

IO67NB1F6

IO67PB1F6

IO68NB1F6

IO68PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO70PB1F6

IO71NB1F6

IO71PB1F6

IO72NB1F6

IO72PB1F6

E26

E25

F26

D21

C21

G22

G21

E22

E21

D22

C22

B23

A23

H22

H21

C24

C23

F23

F25

H30

L28

K25

K24

D27

D26

B29

A29

D28

C28

H25

G25

F27

L27

K29

J29

K31

J31

J32

H32

M27

M26

L30

E27

K30

N25

N26

M29

L29

J25

J24

F22

D29

C29

H26

G26

F28

B24

A24

J22

L33

L32

K22

B25

A25

K23

J23

K34

K33

N28

M28

M34

L34

E28

H27

G27

Bank 2

F24

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

J28

J27

E24

C27

C26

H24

G24

H23

G23

B28

A28

P27

M25

L25

L26

K26

G31

F31

H29

G29

N27

M32

M31

P25

P26

N33

M33

P29

3-40

v5.3

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL

Function

Number

Function

Number

N29

P30

N30

R24

R25

P31

N31

R28

P28

P32

N32

R30

R29

P34

P33

R27

R26

R34

R33

T24

T25

T33

T34

T27

T26

T30

T29

U28

T28

T31

T32

U24

U25

U33

U34

U26

U27

Function

IO128NB2F11

IO128PB2F11

Number

IO109PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO116NB2F10

IO116PB2F10

IO117NB2F10

IO117PB2F10

IO118NB2F11

IO118PB2F11

IO119NB2F11

IO119PB2F11

IO120NB2F11

IO120PB2F11

IO121NB2F11

IO121PB2F11

IO122NB2F11

IO122PB2F11

IO123NB2F11

IO123PB2F11

IO124NB2F11

IO124PB2F11

IO125NB2F11

IO125PB2F11

IO126NB2F11

IO126PB2F11

IO127NB2F11

IO127PB2F11

U31

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

IO150NB3F14

IO150PB3F14

IO151NB3F14

IO151PB3F14

IO152NB3F14

IO152PB3F14

IO153NB3F14

IO153PB3F14

IO154NB3F14

IO154PB3F14

IO155NB3F14

IO155PB3F14

IO156NB3F14

IO156PB3F14

IO157NB3F14

IO157PB3F14

IO158NB3F14

IO158PB3F14

IO159NB3F14

IO159PB3F14

IO160NB3F14

IO160PB3F14

IO161NB3F15

IO161PB3F15

IO162NB3F15

IO162PB3F15

IO163NB3F15

IO163PB3F15

IO164NB3F15

AA29

AA30

AB30

AB29

AB32

AA32

AB27

AA27

AC31

AB31

AD33

AC33

AC28

AB28

AB25

AA25

AD32

AC32

AD29

AC29

AE30

AD30

AC26

AB26

AH33

AG33

AD27

AC27

AG32

AF32

AG31

AF31

AF29

AE29

AE28

AD28

AG30

U32

Bank 3

IO129NB3F12

IO129PB3F12

IO130NB3F12

IO130PB3F12

IO131NB3F12

IO131PB3F12

IO132NB3F12

IO132PB3F12

IO133NB3F12

IO133PB3F12

IO134NB3F12

IO134PB3F12

IO135NB3F12

IO135PB3F12

IO136NB3F12

IO136PB3F12

IO137NB3F12

IO137PB3F12

IO138NB3F12

IO138PB3F12

IO139NB3F13

IO139PB3F13

IO140NB3F13

IO140PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO143NB3F13

IO143PB3F13

IO144NB3F13

IO144PB3F13

IO145NB3F13

IO145PB3F13

V29

U29

V31

V32

V24

V25

W28

V28

W26

V26

W33

V33

W25

W24

W31

W32

Y30

W30

Y29

W29

Y27

W27

AA33

Y33

Y25

Y24

AA31

Y31

AA28

Y28

AA34

Y34

AA26

Y26

v5.3

3-41

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL Pin

RTAX2000S/SL

Function

Number

Function

Number

AE24

AH24

AH25

AG23

AG24

AL25

AL26

AP25

AP26

AK24

AK25

AF23

AE23

AN24

AM24

AH22

AH23

AJ23

Function

IO201NB4F18

IO201PB4F18

Number

AM21

AL21

AE20

AD20

AN21

AP21

AP20

AN20

AN19

AP19

AG20

AF20

AL19

AL20

AG19

AF19

AN18

AP18

AE19

AD19

AL18

AM18

AJ20

IO164PB3F15

IO165NB3F15

IO165PB3F15

IO166NB3F15

IO166PB3F15

IO167NB3F15

IO167PB3F15

IO168NB3F15

IO168PB3F15

IO169NB3F15

IO169PB3F15

IO170NB3F15

IO170PB3F15

AF30

IO182PB4F17

IO183NB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO186NB4F17

IO186PB4F17

IO187NB4F17

IO187PB4F17

IO188NB4F17

IO188PB4F17

IO189NB4F17

IO189PB4F17

IO190NB4F17

IO190PB4F17

IO191NB4F17

IO191PB4F17

IO192NB4F17

IO192PB4F17

IO193NB4F18

IO193PB4F18

IO194NB4F18

IO194PB4F18

IO195NB4F18

IO195PB4F18

IO196NB4F18

IO196PB4F18

IO197NB4F18

IO197PB4F18

IO198NB4F18

IO198PB4F18

IO199NB4F18

IO199PB4F18

IO200NB4F18

IO200PB4F18

AE26

AD26

AJ30

IO202NB4F18

IO202PB4F18

AH30

AG28

AF28

IO203NB4F19

IO203PB4F19

IO204NB4F19

IO204PB4F19

AF27

AE27

AH29

AG29

AD25

AC25

IO205NB4F19

IO205PB4F19

IO206NB4F19

IO206PB4F19

IO207NB4F19

IO207PB4F19

Bank 4

IO171NB4F16

IO171PB4F16

IO172NB4F16

IO172PB4F16

IO173NB4F16

IO173PB4F16

IO174NB4F16

IO174PB4F16

IO175NB4F16

IO175PB4F16

IO176NB4F16

IO176PB4F16

IO177NB4F16

IO177PB4F16

IO178NB4F16

IO178PB4F16

IO179NB4F16

IO179PB4F16

IO180NB4F16

IO180PB4F16

IO181NB4F17

IO181PB4F17

IO182NB4F17

AP29

AN29

AH26

AH27

AJ27

IO208NB4F19

IO208PB4F19

IO209NB4F19

IO209PB4F19

AJ24

IO210NB4F19

IO210PB4F19

AJ28

AG21

AG22

AP23

AP24

AN22

AN23

AM23

AL23

AF21

AF22

AL22

AM22

AE21

AE22

AJ21

AL27

AL28

AM28

AM29

AG25

AG26

AK26

AK27

AF25

AE25

AP28

AN28

AJ25

IO211NB4F19

IO211PB4F19

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

AK20

AJ18

AJ19

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO216NB5F20

IO216PB5F20

AJ16

AJ17

AJ15

AK15

AD16

AE17

AM17

AL17

AG16

AF16

AJ26

IO217NB5F20

IO217PB5F20

AM26

AM27

AF24

AJ22

AK21

AK22

IO218NB5F20

IO218PB5F20

3-42

v5.3

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL

Function

Number

Function

Number

AM16

AL16

AP16

AN16

AN15

AP15

AD15

AE16

AL14

AL15

AN14

AP14

AK13

AK14

AE15

AF15

AG14

AG15

AJ13

Function

Number

AJ12

AH11

AH12

AK10

AK11

AE12

AF12

AN10

AP10

AG11

AG12

AL9

IO219NB5F20

IO219PB5F20

IO220NB5F20

IO220PB5F20

IO221NB5F20

IO221PB5F20

IO222NB5F20

IO222PB5F20

IO223NB5F21

IO223PB5F21

IO224NB5F21

IO224PB5F21

IO225NB5F21

IO225PB5F21

IO226NB5F21

IO226PB5F21

IO227NB5F21

IO227PB5F21

IO228NB5F21

IO228PB5F21

IO229NB5F21

IO229PB5F21

IO230NB5F21

IO230PB5F21

IO231NB5F21

IO231PB5F21

IO232NB5F21

IO232PB5F21

IO233NB5F21

IO233PB5F21

IO234NB5F21

IO234PB5F21

IO235NB5F22

IO235PB5F22

IO236NB5F22

IO236PB5F22

IO237NB5F22

IO237PB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO240PB5F22

IO241NB5F22

IO241PB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

IO245NB5F23

IO245PB5F23

IO246NB5F23

IO246PB5F23

IO247NB5F23

IO247PB5F23

IO248NB5F23

IO248PB5F23

IO249NB5F23

IO249PB5F23

IO250NB5F23

IO250PB5F23

IO251NB5F23

IO251PB5F23

IO252NB5F23

IO252PB5F23

IO253NB5F23

IO253PB5F23

IO254NB5F23

IO254PB5F23

IO255NB5F23

IO255PB5F23

IO256NB5F23

IO256PB5F23

AL6

AM6

Bank 6

IO257NB6F24

IO257PB6F24

IO258NB6F24

IO258PB6F24

IO259NB6F24

IO259PB6F24

IO260NB6F24

IO260PB6F24

IO261NB6F24

IO261PB6F24

IO262NB6F24

IO262PB6F24

IO263NB6F24

IO263PB6F24

IO264NB6F24

IO264PB6F24

IO265NB6F24

IO265PB6F24

IO266NB6F24

IO266PB6F24

IO267NB6F25

IO267PB6F25

IO268NB6F25

IO268PB6F25

IO269NB6F25

IO269PB6F25

IO270NB6F25

IO270PB6F25

IO271NB6F25

IO271PB6F25

IO272NB6F25

IO272PB6F25

IO273NB6F25

IO273PB6F25

AG6

AH6

AD9

AE9

AF7

AG7

AH3

AH4

AH5

AJ5

AL10

AM8

AM9

AH10

AJ10

AF10

AF11

AJ9

AE6

AF6

AF5

AG5

AD8

AE8

AF3

AJ14

AM13

AM14

AE14

AF14

AN12

AP12

AG13

AH13

AL12

AL13

AE13

AF13

AN11

AP11

AM11

AM12

AJ11

AK9

AG3

AC10

AD10

AD7

AE7

AD5

AE5

AE4

AF4

AN7

AP7

AL7

AL8

AE10

AE11

AK8

AJ8

AH8

AB9

AC9

AC6

AD6

AB8

AC8

AE1

AE2

AH9

AN6

AP6

AG9

AG10

AJ7

AK7

v5.3

3-43

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL Pin

RTAX2000S/SL

Function

Number

AA10

AB10

AB7

AC7

AD1

AD2

AC4

AC3

AA8

AA9

AB5

AB6

Y10

Y11

AB3

AB4

Function

Number

Function

Number

IO274NB6F25

IO274PB6F25

IO275NB6F25

IO275PB6F25

IO276NB6F25

IO276PB6F25

IO277NB6F25

IO277PB6F25

IO278NB6F26

IO278PB6F26

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO283NB6F26

IO283PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO288NB6F26

IO288PB6F26

IO289NB6F27

IO289PB6F27

IO290NB6F27

IO290PB6F27

IO291NB6F27

IO291PB6F27

IO292NB6F27

IO292PB6F27

IO293NB6F27

IO293PB6F27

IO294NB6F27

IO294PB6F27

IO295NB6F27

IO295PB6F27

IO296NB6F27

IO296PB6F27

IO297NB6F27

IO297PB6F27

IO298NB6F27

IO298PB6F27

IO299NB6F27

IO299PB6F27

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO313NB7F29

IO313PB7F29

IO314NB7F29

IO314PB7F29

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO319NB7F29

IO319PB7F29

IO320NB7F29

IO320PB7F29

IO321NB7F30

IO321PB7F30

IO322NB7F30

IO322PB7F30

IO323NB7F30

IO323PB7F30

IO324NB7F30

IO324PB7F30

IO325NB7F30

IO325PB7F30

IO326NB7F30

IO326PB7F30

IO327NB7F30

IO327PB7F30

IO328NB7F30

IO328PB7F30

V10

V11

Bank 7

R10

R11

IO300NB7F28

IO300PB7F28

IO301NB7F28

IO301PB7F28

IO302NB7F28

IO302PB7F28

IO303NB7F28

IO303PB7F28

IO304NB7F28

IO304PB7F28

IO305NB7F28

IO305PB7F28

IO306NB7F28

IO306PB7F28

IO307NB7F28

IO307PB7F28

IO308NB7F28

IO308PB7F28

IO309NB7F28

IO309PB7F28

IO310NB7F29

U10

U11

AA7

AC2

AC1

P10

AA5

AA6

W10

W11

AA3

AA4

AA1

AA2

T11

T10

N10

3-44

v5.3

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL

Function

Number

Function

Number

Function

GND

Number

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AB1

IO329NB7F30

IO329PB7F30

IO330NB7F30

IO330PB7F30

IO331NB7F30

IO331PB7F30

IO332NB7F31

IO332PB7F31

IO333NB7F31

IO333PB7F31

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO336NB7F31

IO336PB7F31

IO337NB7F31

IO337PB7F31

IO338NB7F31

IO338PB7F31

IO339NB7F31

IO339PB7F31

IO340NB7F31

IO340PB7F31

IO341NB7F31

IO341PB7F31

GND

AK5

AL1

AL11

AL2

M10

AL24

AL3

AL31

AL32

AL33

AL34

AL4

AB13

AB22

AB34

AC12

AC23

AC30

AC5

AM1

AM10

AM15

AM2

AM20

AM25

AM3

AM31

AM32

AM33

AM34

AM4

AN1

AD11

AD24

AD31

AD4

AE3

AE32

AF2

AF33

AG1

AN2

AG27

AG34

AG8

AN26

AN3

Dedicated I/O

GND

A13

AN31

AN32

AN33

AN34

AN4

AH28

AH7

A22

A27

AJ29

AJ6

A31

A32

A33

AK12

AK17

AK18

AK23

AK30

AN9

AP13

AP2

AP22

AP27

v5.3

3-45

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL Pin

RTAX2000S/SL

Function

Number

AP3

AP31

AP32

AP33

AP4

AP8

Function

GND

Number

Function

GND

Number

P20

P21

R14

R15

R16

R17

R18

R19

R20

R21

GND

E12

E17

E18

E23

E30

F29

F30

B26

B31

B32

B33

B34

G28

R32

T14

T15

T16

T17

T18

T19

T20

T21

U14

U15

U16

U17

U18

U19

U20

U21

U30

H34

J33

C10

C15

K32

L11

L24

L31

C20

C25

C31

C32

C33

C34

M12

M23

M30

N13

N22

N34

P14

P15

P16

P17

P18

P19

D11

V14

V15

V16

V17

V18

V19

V20

D24

D31

D32

D33

D34

3-46

v5.3

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL

Function

Number

Function

GND

Number

Function

Number

AG2

AG4

AH1

V21

PRA

PRB

PRC

PRD

F32

F33

F34

V30

W14

W15

W16

W17

W18

W19

W20

W21

Y14

AH16

AH19

AH2

AH31

AH32

AH34

AJ1

G32

G33

G34

H16

H19

H31

H33

AJ2

AJ3

Y15

AJ31

AJ32

AJ33

AJ34

AJ4

Y16

Y17

J16

J19

Y18

Y19

Y20

AK16

AK19

AL29

AM19

AM7

AN13

AN17

AN25

AN27

AN8

J34

K17

K18

L17

L18

Y21

Y32

A17

A26

AB2

AB33

AC34

AD17

AD3

AD34

AE18

AE31

AE33

AE34

AF1

R31

AP17

AP9

B17

B22

V34

W34

J17

F18

AD18

AH18

B27

D10

AF17

AF18

AF34

D20

D23

D25

v5.3

3-47

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL Pin

RTAX2000S/SL

Function

Number

Function

Number

W13

W22

Y13

Y22

AF26

AF9

Function

Number

M15

M16

M17

A30

TCK

TDI

V_CCA

V_CCIB0

V_CCA

_CCIB0

_CCIB1

TDO

L10

V_CCA

TMS

V_CCA

TRST

V_CCA

V_CCDA

V_CCIB1

B30

AA13

AA22

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AF8

_CCIB1

_CCIB2

C30

AG17

AG18

AH14

AH15

AH17

AH20

AH21

AK29

AK6

E15

D30

L21

L22

L23

M18

M19

M20

M21

M22

E31

AK28

G30

E29

V_CCIB2

E32

_CCIB2

E33

F15

E34

N14

N15

N16

N17

N18

N19

N20

N21

P13

F21

M24

N23

G20

H17

H18

H28

J18

V_CCIB2

N24

_CCIB2

P23

P24

R23

T23

V27

U23

V_CCIB3

AA23

AA24

AB23

AB24

AC24

AK31

AK32

AK33

AK34

V23

P22

_CCIB0

_CCIB3

R13

R22

T13

T22

L12

U13

U22

V13

V22

V_CCIB0

L13

V_CCIB3

_CCIB0

L14

_CCIB3

M13

M14

3-48

v5.3

RTAX-S/SL RadTolerant FPGAs

1152-Pin CCGA/LGA

RTAX2000S/SL

1152-Pin CCGA/LGA

RTAX2000S/SL

Function

Number

Function

Number

Function

Number

AC16

AC17

AD12

AD13

AD14

AL5

V_CCIB3

W23

V_CCIB5

V_CCIB6

AK4

V12

W12

Y12

_CCIB3

_CCIB4

Y23

_CCIB5

_CCIB6

AC18

AC19

AC20

AC21

AC22

AD21

AD22

AD23

AL30

V_CCIB4

V_CCIB5

V_CCIB7

_CCIB4

_CCIB5

_CCIB6

_CCIB7

AM5

AN5

AP5

M11

N11

N12

P11

P12

R12

T12

U12

J26

AA11

AA12

AB11

AB12

AC11

AK1

AM30

AN30

AP30

AC13

AC14

AC15

AK2

V_CCIB5

V_CCIB6

AK3

V_PUMP

v5.3

3-49

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Figure 3-6 • 1272-Pin CCGA/LGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit the Resource center at

http://www.actel.com/products/solutions/package/docs.aspx.

3-50

v5.3

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

Bank 0

Number

RTAX4000S Function

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F2

IO21PB0F2

IO22NB0F2

IO22PB0F2

IO23NB0F2

IO23PB0F2

IO24NB0F2

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

IO28PB0F2

IO29NB0F2

IO29PB0F2

IO30NB0F2

IO30PB0F2

IO31NB0F2

IO31PB0F2

IO32NB0F2

IO32PB0F2

IO33NB0F3

IO33PB0F3

IO34NB0F3

IO34PB0F3

IO35NB0F3

IO35PB0F3

IO36NB0F3

Number

K13

K12

RTAX4000S Function

Number

IO36PB0F3

IO37NB0F3

J15

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

A11

A10

H15

H14

B16

B15

M16

M17

E16

IO37PB0F3

IO38NB0F3

H13

H12

C13

C12

M14

M13

B10

IO38PB0F3

J10

IO39NB0F3

IO39PB0F3

IO40NB0F3

IO40PB0F3

IO41NB0F3

IO41PB0F3

F16

IO42NB0F4

H17

J17

J14

IO42PB0F4

L13

L12

J13

IO43NB0F4

A14

A15

G16

H16

A17

A16

M18

M19

E18

IO43PB0F4

IO44NB0F4

G13

F13

D14

D13

L16

L15

B13

B12

C10

IO44PB0F4

F10

G10

D10

E10

H11

H10

IO45NB0F4

IO45PB0F4

IO46NB0F4

IO46PB0F4

IO47NB0F4

IO47PB0F4

E17

IO48NB0F4

G18

H18

C18

B18

J18

IO48PB0F4

IO49NB0F4

E15

E14

K15

K16

A13

A12

G15

F15

C15

D15

J16

IO49PB0F4

IO50NB0F4/HCLKAN

IO50PB0F4/HCLKAP

IO51NB0F4/HCLKBN

IO51PB0F4/HCLKBP

Bank 1

K18

D18

D17

J12

J11

D12

D11

F12

G12

E12

E11

IO52NB1F6/HCLKCN

IO52PB1F6/HCLKCP

IO53NB1F6/HCLKDN

IO53PB1F6/HCLKDP

IO54NB1F6

K19

J19

D20

D19

H19

v5.3

3-51

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

IO54PB1F6

IO55NB1F6

IO55PB1F6

IO56NB1F6

IO56PB1F6

IO57NB1F6

IO57PB1F6

IO58NB1F6

IO58PB1F6

IO59NB1F6

IO59PB1F6

IO60NB1F7

IO60PB1F7

IO61NB1F7

IO61PB1F7

IO62NB1F7

IO62PB1F7

IO63NB1F7

IO63PB1F7

IO64NB1F7

IO64PB1F7

IO65NB1F7

IO65PB1F7

IO66NB1F7

IO66PB1F7

IO67NB1F7

IO67PB1F7

IO68NB1F7

IO68PB1F7

IO69NB1F7

IO69PB1F7

IO70NB1F7

IO70PB1F7

IO71NB1F7

IO71PB1F7

IO72NB1F8

IO72PB1F8

Number

G19

B19

C19

M20

M21

E20

RTAX4000S Function

IO73NB1F8

IO73PB1F8

IO74NB1F8

IO74PB1F8

IO75NB1F8

IO75PB1F8

IO76NB1F8

IO76PB1F8

IO77NB1F8

IO77PB1F8

IO78NB1F8

IO78PB1F8

IO79NB1F8

IO79PB1F8

IO80NB1F8

IO80PB1F8

IO81NB1F8

IO81PB1F8

IO82NB1F9

IO82PB1F9

IO83NB1F9

IO83PB1F9

IO84NB1F9

IO84PB1F9

IO85NB1F9

IO85PB1F9

IO86NB1F9

IO86PB1F9

IO87NB1F9

IO87PB1F9

IO88NB1F9

IO88PB1F9

IO89NB1F9

IO89PB1F9

IO90NB1F9

IO90PB1F9

IO91NB1F9

Number

A25

A24

C28

C27

D24

D23

J24

RTAX4000S Function

IO91PB1F9

Number

A30

H27

H26

C33

B33

G27

F27

IO92NB1F9

IO92PB1F9

IO93NB1F9

IO93PB1F9

IO94NB1F10

IO94PB1F10

IO95NB1F10

IO95PB1F10

IO96NB1F10

IO96PB1F10

IO97NB1F10

IO97PB1F10

IO98NB1F10

IO98PB1F10

IO99NB1F10

IO99PB1F10

IO100NB1F10

IO100PB1F10

IO101NB1F10

IO101PB1F10

IO102NB1F10

IO102PB1F10

IO103NB1F10

IO103PB1F10

Bank 2

E19

H21

G21

A21

A20

H20

J20

J23

E27

D27

L24

B25

B24

F24

L25

G24

A28

A29

M24

M23

B28

B27

H25

H24

C25

C24

K25

K24

A33

A32

G25

F25

C31

C30

F28

A22

A23

D32

D31

F21

G28

B31

B30

J28

E21

J27

J22

E29

E30

D28

E28

D30

D29

J21

B22

B21

H23

H22

D22

C22

K22

K21

A27

A26

F22

IO104NB2F12

IO104PB2F12

IO105NB2F12

IO105PB2F12

IO106NB2F12

IO106PB2F12

IO107NB2F12

IO107PB2F12

IO108NB2F12

IO108PB2F12

IO109NB2F12

L29

L28

E26

D35

D34

H33

J33

E25

J26

J25

G22

E23

D26

D25

E31

F34

F33

E22

G33

G32

M28

L22

E32

A31

L21

3-52

v5.3

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

IO109PB2F12

IO110NB2F12

IO110PB2F12

IO111NB2F12

IO111PB2F12

IO112NB2F13

IO112PB2F13

IO113NB2F13

IO113PB2F13

IO114NB2F13

IO114PB2F13

IO115NB2F13

IO115PB2F13

IO116NB2F13

IO116PB2F13

IO117NB2F13

IO117PB2F13

IO118NB2F13

IO118PB2F13

IO119NB2F13

IO119PB2F13

IO120NB2F13

IO120PB2F13

IO121NB2F14

IO121PB2F14

IO122NB2F14

IO122PB2F14

IO123NB2F14

IO123PB2F14

IO124NB2F14

IO124PB2F14

IO125NB2F14

IO125PB2F14

IO126NB2F14

IO126PB2F14

IO127NB2F14

IO127PB2F14

Number

M27

K33

K32

K31

K30

K34

J34

RTAX4000S Function

IO128NB2F14

IO128PB2F14

IO129NB2F14

IO129PB2F14

IO130NB2F15

IO130PB2F15

IO131NB2F15

IO131PB2F15

IO132NB2F15

IO132PB2F15

IO133NB2F15

IO133PB2F15

IO134NB2F15

IO134PB2F15

IO135NB2F15

IO135PB2F15

IO136NB2F15

IO136PB2F15

IO137NB2F15

IO137PB2F15

IO138NB2F15

IO138PB2F15

IO139NB2F16

IO139PB2F16

IO140NB2F16

IO140PB2F16

IO141NB2F16

IO141PB2F16

IO142NB2F16

IO142PB2F16

IO143NB2F16

IO143PB2F16

IO144NB2F16

IO144PB2F16

IO145NB2F16

IO145PB2F16

IO146NB2F16

Number

N34

M34

P29

P28

N33

M33

R26

R25

K36

J36

RTAX4000S Function

Number

IO146PB2F16

IO147NB2F16

IO147PB2F16

IO148NB2F17

IO148PB2F17

IO149NB2F17

IO149PB2F17

IO150NB2F17

IO150PB2F17

IO151NB2F17

IO151PB2F17

IO152NB2F17

IO152PB2F17

IO153NB2F17

IO153PB2F17

IO154NB2F17

IO154PB2F17

IO155NB2F17

IO155PB2F17

IO156NB2F17

IO156PB2F17

R32

V25

U25

T36

R36

U29

U28

U33

T33

N26

M26

K28

K29

H32

J32

W25

Y25

V36

U36

V31

V30

V32

U32

V27

V28

W34

V34

R29

R28

N35

M35

F35

G35

G34

M29

M30

E33

F36

M36

L36

D33

M32

M31

E36

T26

T25

P33

P32

R31

R30

P36

N36

T28

T27

R35

R34

T32

T31

T35

T34

T30

T29

R33

Bank 3

D36

N28

N27

L33

IO157NB3F18

IO157PB3F18

IO158NB3F18

IO158PB3F18

IO159NB3F18

IO159PB3F18

IO160NB3F18

IO160PB3F18

IO161NB3F18

IO161PB3F18

IO162NB3F18

IO162PB3F18

IO163NB3F18

IO163PB3F18

IO164NB3F18

W29

V29

W35

V35

L32

W30

W31

AA36

Y36

N30

N29

K35

J35

W27

W28

Y32

P25

N25

H36

G36

N32

N31

W32

Y28

Y29

AC36

v5.3

3-53

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

IO164PB3F18

IO165NB3F18

IO165PB3F18

IO166NB3F19

IO166PB3F19

IO167NB3F19

IO167PB3F19

IO168NB3F19

IO168PB3F19

IO169NB3F19

IO169PB3F19

IO170NB3F19

IO170PB3F19

IO171NB3F19

IO171PB3F19

IO172NB3F19

IO172PB3F19

IO173NB3F19

IO173PB3F19

IO174NB3F19

IO174PB3F19

IO175NB3F20

IO175PB3F20

IO176NB3F20

IO176PB3F20

IO177NB3F20

IO177PB3F20

IO178NB3F20

IO178PB3F20

IO179NB3F20

IO179PB3F20

IO180NB3F20

IO180PB3F20

IO181NB3F20

IO181PB3F20

IO182NB3F20

IO182PB3F20

Number

AB36

AA26

AA25

AA33

Y33

RTAX4000S Function

IO183NB3F20

IO183PB3F20

IO184NB3F21

IO184PB3F21

IO185NB3F21

IO185PB3F21

IO186NB3F21

IO186PB3F21

IO187NB3F21

IO187PB3F21

IO188NB3F21

IO188PB3F21

IO189NB3F21

IO189PB3F21

IO190NB3F21

IO190PB3F21

IO191NB3F21

IO191PB3F21

IO192NB3F21

IO192PB3F21

IO193NB3F22

IO193PB3F22

IO194NB3F22

IO194PB3F22

IO195NB3F22

IO195PB3F22

IO196NB3F22

IO196PB3F22

IO197NB3F22

IO197PB3F22

IO198NB3F22

IO198PB3F22

IO199NB3F22

IO199PB3F22

IO200NB3F22

IO200PB3F22

IO201NB3F22

Number

AC29

AC28

AE34

AD34

AE26

AD26

AE33

AD33

AD30

AD29

AH35

AG35

AD32

AD31

AK35

AK36

AE32

AE31

AN36

AM36

AD27

AD28

AF32

AF33

AE30

AE29

AK34

AL34

AE28

AE27

AN33

AM33

AH31

AH30

AH34

AG34

AF29

RTAX4000S Function

IO201PB3F22

IO202NB3F23

IO202PB3F23

IO203NB3F23

IO203PB3F23

IO204NB3F23

IO204PB3F23

IO205NB3F23

IO205PB3F23

IO206NB3F23

IO206PB3F23

IO207NB3F23

IO207PB3F23

IO208NB3F23

IO208PB3F23

IO209NB3F23

IO209PB3F23

Bank 4

Number

AF28

AG32

AG33

AG31

AG30

AL33

AA32

AA31

AA34

AA35

AA29

AA30

AB32

AB33

AB31

AB30

AE36

AD36

AA27

AA28

AB34

AB35

AL35

AL36

AG36

AF36

AB25

AB26

AC32

AC33

AB29

AB28

AJ36

AK33

AK32

AK31

AH33

AJ33

AN34

AN35

AG29

AG28

AJ32

AH32

IO210NB4F24

IO210PB4F24

IO211NB4F24

IO211PB4F24

IO212NB4F24

IO212PB4F24

IO213NB4F24

IO213PB4F24

IO214NB4F24

IO214PB4F24

IO215NB4F24

IO215PB4F24

IO216NB4F24

IO216PB4F24

IO217NB4F24

IO217PB4F24

IO218NB4F24

IO218PB4F24

IO219NB4F24

AM28

AN28

AN29

AN30

AH27

AH28

AM30

AM29

AL28

AK28

AR30

AR31

AF24

AF25

AP30

AP31

AL27

AK27

AN27

AH36

AC25

AD25

AE35

AD35

3-54

v5.3

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

IO219PB4F24

IO220NB4F25

IO220PB4F25

IO221NB4F25

IO221PB4F25

IO222NB4F25

IO222PB4F25

IO223NB4F25

IO223PB4F25

IO224NB4F25

IO224PB4F25

IO225NB4F25

IO225PB4F25

IO226NB4F25

IO226PB4F25

IO227NB4F25

IO227PB4F25

IO228NB4F25

IO228PB4F25

IO229NB4F25

IO229PB4F25

IO230NB4F25

IO230PB4F25

IO231NB4F25

IO231PB4F25

IO232NB4F26

IO232PB4F26

IO233NB4F26

IO233PB4F26

IO234NB4F26

IO234PB4F26

IO235NB4F26

IO235PB4F26

IO236NB4F26

IO236PB4F26

IO237NB4F26

IO237PB4F26

Number

AM27

AJ26

RTAX4000S Function

IO238NB4F26

IO238PB4F26

IO239NB4F26

IO239PB4F26

IO240NB4F26

IO240PB4F26

IO241NB4F26

IO241PB4F26

IO242NB4F27

IO242PB4F27

IO243NB4F27

IO243PB4F27

IO244NB4F27

IO244PB4F27

IO245NB4F27

IO245PB4F27

IO246NB4F27

IO246PB4F27

IO247NB4F27

IO247PB4F27

IO248NB4F27

IO248PB4F27

IO249NB4F27

IO249PB4F27

IO250NB4F27

IO250PB4F27

IO251NB4F27

IO251PB4F27

IO252NB4F27

IO252PB4F27

IO253NB4F27

IO253PB4F27

IO254NB4F28

IO254PB4F28

IO255NB4F28

IO255PB4F28

IO256NB4F28

Number

AF21

AF22

AP24

AP25

AP27

AP28

AN23

AN24

AG21

AG22

AM22

AM23

AK22

AL22

AT24

AT25

AH21

AH22

AP22

AN22

AJ22

RTAX4000S Function

Number

IO256PB4F28

IO257NB4F28

IO257PB4F28

AE19

AM19

AM20

AK19

AJ19

AJ27

AT32

AT33

AN31

AN32

AT30

AT31

AH25

AH26

AN25

AN26

AL25

AK25

AM25

AM26

AG25

AG24

AR33

AP33

AJ24

IO258NB4F28

IO258PB4F28

IO259NB4F28

IO259PB4F28

AP19

AR19

AH19

AG19

AN19

AN20

IO260NB4F28/CLKEN

IO260PB4F28/CLKEP

IO261NB4F28/CLKFN

IO261PB4F28/CLKFP

Bank 5

IO262NB5F30/CLKGN

IO262PB5F30/CLKGP

IO263NB5F30/CLKHN

IO263PB5F30/CLKHP

IO264NB5F30

IO264PB5F30

AG18

AH18

AN17

AN18

AJ18

AK18

AR18

AP18

AE17

AE16

AM17

AM18

AJ16

IO265NB5F30

IO265PB5F30

IO266NB5F30

IO266PB5F30

AJ23

AJ25

AR21

AR22

AE21

AE20

AM21

AL21

AH20

AJ20

IO267NB5F30

IO267PB5F30

AT26

AT27

AE23

AE24

AR27

AR28

AH23

AH24

AT29

AT28

AK24

AL24

AR24

AR25

IO268NB5F30

IO268PB5F30

AK16

AT16

AT17

AF16

AF15

AT15

AT14

AH17

AJ17

IO269NB5F30

IO269PB5F30

IO270NB5F30

IO270PB5F30

AT23

AT22

AK21

AJ21

IO271NB5F30

IO271PB5F30

IO272NB5F31

IO272PB5F31

AT20

AT21

AE18

IO273NB5F31

IO273PB5F31

AL16

AM16

AH15

IO274NB5F31

v5.3

3-55

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

IO274PB5F31

IO275NB5F31

IO275PB5F31

IO276NB5F31

IO276PB5F31

IO277NB5F31

IO277PB5F31

IO278NB5F31

IO278PB5F31

IO279NB5F31

IO279PB5F31

IO280NB5F31

IO280PB5F31

IO281NB5F32

IO281PB5F32

IO282NB5F32

IO282PB5F32

IO283NB5F32

IO283PB5F32

IO284NB5F32

IO284PB5F32

IO285NB5F32

IO285PB5F32

IO286NB5F32

IO286PB5F32

IO287NB5F32

IO287PB5F32

IO288NB5F32

IO288PB5F32

IO289NB5F32

IO289PB5F32

IO290NB5F32

IO290PB5F32

IO291NB5F32

IO291PB5F32

IO292NB5F32

IO292PB5F32

Number

AH16

AR15

AR16

AJ14

AJ15

AN15

AP15

AG15

AG16

AT10

AT11

AL15

AK15

AM14

AM15

AE13

AE14

AT12

AT13

AP9

RTAX4000S Function

IO293NB5F33

IO293PB5F33

IO294NB5F33

IO294PB5F33

IO295NB5F33

IO295PB5F33

IO296NB5F33

IO296PB5F33

IO297NB5F33

IO297PB5F33

IO298NB5F33

IO298PB5F33

IO299NB5F33

IO299PB5F33

IO300NB5F33

IO300PB5F33

IO301NB5F33

IO301PB5F33

IO302NB5F34

IO302PB5F34

IO303NB5F34

IO303PB5F34

IO304NB5F34

IO304PB5F34

IO305NB5F34

IO305PB5F34

IO306NB5F34

IO306PB5F34

IO307NB5F34

IO307PB5F34

IO308NB5F34

IO308PB5F34

IO309NB5F34

IO309PB5F34

IO310NB5F34

IO310PB5F34

IO311NB5F34

Number

AP12

AP13

AG13

AF13

AP4

RTAX4000S Function

IO311PB5F34

IO312NB5F34

IO312PB5F34

IO313NB5F34

IO313PB5F34

Bank 6

Number

AM7

AG9

AG8

AN7

AN8

AR4

AG12

AF12

AM11

AM12

AK12

AL12

AN11

AN12

AN5

IO314NB6F36

IO314PB6F36

IO315NB6F36

IO315PB6F36

IO316NB6F36

IO316PB6F36

IO317NB6F36

IO317PB6F36

IO318NB6F36

IO318PB6F36

IO319NB6F36

IO319PB6F36

IO320NB6F36

IO320PB6F36

IO321NB6F36

IO321PB6F36

IO322NB6F37

IO322PB6F37

IO323NB6F37

IO323PB6F37

IO324NB6F37

IO324PB6F37

IO325NB6F37

IO325PB6F37

IO326NB6F37

IO326PB6F37

IO327NB6F37

IO327PB6F37

IO328NB6F37

IO328PB6F37

IO329NB6F37

AF8

AF9

AN2

AN3

AH4

AJ4

AL3

AL4

AK4

AK5

AE10

AE9

AG4

AG5

AE11

AD11

AG3

AH3

AG7

AG6

AH7

AH6

AJ5

AN6

AT6

AT7

AH11

AH12

AT4

AP10

AN13

AN14

AN9

AT5

AJ10

AJ11

AM10

AN10

AK10

AL10

AP6

AM9

AR12

AR13

AL13

AK13

AT9

AP7

AH5

AK2

AK3

AE7

AE8

AM4

AN4

AD9

AT8

AK9

AH13

AH14

AR9

AL9

AR6

AR7

AR10

AJ12

AJ13

AH9

AH10

AM8

3-56

v5.3

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

IO329PB6F37

IO330NB6F37

IO330PB6F37

IO331NB6F38

IO331PB6F38

IO332NB6F38

IO332PB6F38

IO333NB6F38

IO333PB6F38

IO334NB6F38

IO334PB6F38

IO335NB6F38

IO335PB6F38

IO336NB6F38

IO336PB6F38

IO337NB6F38

IO337PB6F38

IO338NB6F38

IO338PB6F38

IO339NB6F38

IO339PB6F38

IO340NB6F39

IO340PB6F39

IO341NB6F39

IO341PB6F39

IO342NB6F39

IO342PB6F39

IO343NB6F39

IO343PB6F39

IO344NB6F39

IO344PB6F39

IO345NB6F39

IO345PB6F39

IO346NB6F39

IO346PB6F39

IO347NB6F39

IO347PB6F39

Number

AD10

AM1

AN1

AE5

RTAX4000S Function

IO348NB6F39

IO348PB6F39

IO349NB6F40

IO349PB6F40

IO350NB6F40

IO350PB6F40

IO351NB6F40

IO351PB6F40

IO352NB6F40

IO352PB6F40

IO353NB6F40

IO353PB6F40

IO354NB6F40

IO354PB6F40

IO355NB6F40

IO355PB6F40

IO356NB6F40

IO356PB6F40

IO357NB6F40

IO357PB6F40

IO358NB6F41

IO358PB6F41

IO359NB6F41

IO359PB6F41

IO360NB6F41

IO360PB6F41

IO361NB6F41

IO361PB6F41

IO362NB6F41

IO362PB6F41

IO363NB6F41

IO363PB6F41

IO364NB6F41

IO364PB6F41

IO365NB6F41

IO365PB6F41

IO366NB6F41

Number

AC4

AC5

AB6

AB7

AC1

AD1

AA9

AA10

AB2

AB3

AA7

AA8

AA2

AA3

AA5

AA6

AB4

AB5

W12

Y12

AA1

AB1

RTAX4000S Function

IO366PB6F41

Bank 7

Number

IO367NB7F42

IO367PB7F42

IO368NB7F42

IO368PB7F42

IO369NB7F42

IO369PB7F42

IO370NB7F42

IO370PB7F42

IO371NB7F42

IO371PB7F42

IO372NB7F42

IO372PB7F42

IO373NB7F42

IO373PB7F42

IO374NB7F42

IO374PB7F42

IO375NB7F42

IO375PB7F42

IO376NB7F43

IO376PB7F43

IO377NB7F43

IO377PB7F43

IO378NB7F43

IO378PB7F43

IO379NB7F43

IO379PB7F43

IO380NB7F43

IO380PB7F43

IO381NB7F43

IO381PB7F43

IO382NB7F43

IO382PB7F43

IO383NB7F43

IO383PB7F43

IO384NB7F43

V10

AE6

AF4

AF5

AD8

AD7

AG2

AH2

AC12

AD12

AJ1

AK1

AC8

AC9

AD3

AE3

T11

T12

AD5

AD6

AD4

AE4

AB8

AB9

AG1

AH1

AA12

AB12

AD2

AE2

AA4

U12

V12

AA11

AB11

AE1

AF1

W10

T10

AL1

AL2

v5.3

3-57

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

IO384PB7F43

IO385NB7F44

IO385PB7F44

IO386NB7F44

IO386PB7F44

IO387NB7F44

IO387PB7F44

IO388NB7F44

IO388PB7F44

IO389NB7F44

IO389PB7F44

IO390NB7F44

IO390PB7F44

IO391NB7F44

IO391PB7F44

IO392NB7F44

IO392PB7F44

IO393NB7F44

IO393PB7F44

IO394NB7F45

IO394PB7F45

IO395NB7F45

IO395PB7F45

IO396NB7F45

IO396PB7F45

IO397NB7F45

IO397PB7F45

IO398NB7F45

IO398PB7F45

IO399NB7F45

IO399PB7F45

IO400NB7F45

IO400PB7F45

IO401NB7F45

IO401PB7F45

IO402NB7F45

IO402PB7F45

Number

RTAX4000S Function

IO403NB7F46

IO403PB7F46

IO404NB7F46

IO404PB7F46

IO405NB7F46

IO405PB7F46

IO406NB7F46

IO406PB7F46

IO407NB7F46

IO407PB7F46

IO408NB7F46

IO408PB7F46

IO409NB7F46

IO409PB7F46

IO410NB7F46

IO410PB7F46

IO411NB7F46

IO411PB7F46

IO412NB7F47

IO412PB7F47

IO413NB7F47

IO413PB7F47

IO414NB7F47

IO414PB7F47

IO415NB7F47

IO415PB7F47

IO416NB7F47

IO416PB7F47

IO417NB7F47

IO417PB7F47

IO418NB7F47

IO418PB7F47

IO419NB7F47

IO419PB7F47

Dedicated I/O

GND

Number

N10

RTAX4000S Function

GND

Number

AA15

AA17

AA19

AA21

AA23

AA24

AB14

AB16

AB18

AB20

AB22

AC11

AC13

AC15

AC17

AC19

AC21

AC23

AC24

AC26

AC3

R12

R11

GND

M10

GND

N12

P12

GND

M11

N11

GND

AC30

AC34

AC7

GND

AD13

AD14

AD16

AD18

AD19

AD21

AD23

AD24

AE15

AE25

AF10

AF11

AF14

GND

AA13

GND

3-58

v5.3

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

GND

Number

AF17

AF20

AF23

AF26

AF27

AF3

RTAX4000S Function

GND

Number

AP35

AP5

AP8

AR3

AR34

RTAX4000S Function

Number

L11

L14

L17

L20

L23

L26

L27

GND

AF30

AF34

AF7

GND

B34

C11

C14

C17

GND

L30

L34

GND

AJ29

AJ3

GND

AJ30

AJ34

AJ7

GND

C20

C23

C26

C29

C32

C35

M15

M25

N14

N16

N18

N19

N21

N23

N24

P11

P13

P14

P16

P18

P20

P22

P24

P26

GND

AK11

AK14

AK17

AK20

AK23

AK26

AK29

AK6

GND

E34

F30

GND

AK8

GND

AL18

AL31

AL7

GND

G11

G14

G17

G20

G23

G26

G29

GND

AM3

AM34

AP11

AP14

AP17

AP2

GND

P30

P34

GND

AP20

AP23

AP26

AP29

AP32

GND

H30

H34

GND

R15

R17

R19

R21

GND

J31

GND

L10

v5.3

3-59

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

GND

Number

R23

R27

T13

RTAX4000S Function

GND

Number

W26

RTAX4000S Function

V_CCA

Number

AC18

AC20

AC22

AE12

AL32

AL5

GND

Y11

GND

T14

Y14

GND

T16

Y16

GND

T18

Y18

GND

T20

Y20

AP3

AP34

AT18

GND

T22

Y22

GND

T24

Y26

GND

U11

U15

U17

U19

U21

U23

U26

GND

Y30

C34

J30

GND

Y34

GND

M12

P15

GND

AJ8

GND

W36

F18

P17

GND

PRA

P19

GND

PRB

A18

AL19

AT19

P21

GND

U30

U34

PRC

P23

GND

PRD

R14

GND

TCK

R16

GND

V13

V14

V16

V18

V20

V22

V24

V33

TDI

R18

GND

TDO

R20

GND

TMS

R22

GND

TRST

V_CCA

T15

GND

A19

AA14

AA16

AA18

AA20

AA22

AB15

AB17

AB19

AB21

AB23

AC14

AC16

T17

GND

T19

GND

T21

GND

T23

GND

U14

U16

U18

U20

U22

V15

V17

V19

V21

GND

W11

W13

W15

W17

W19

W21

W23

W24

GND

3-60

v5.3

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

V_CCA

Number

RTAX4000S Function

V_CCDA

Number

D16

D21

E13

E24

RTAX4000S Function

Number

V23

V_CCIB

B26

V_CCA

W14

W16

W18

W20

W22

W33

Y15

V_CCDA

V_CCIB1

B29

V_CCA

V_CCDA

B32

V_CCA

V_CCDA

F20

V_CCA

V_CCDA

V_CCIB

F23

V_CCA

V_CCDA

_CCIB1

F26

V_CCA

V_CCDA

F19

F31

G30

G31

_CCIB1

F29

V_CCA

V_CCDA

K20

V_CCA

Y17

V_CCDA

K23

V_CCA

Y19

V_CCDA

K26

V_CCA

Y21

V_CCDA

N20

N22

E35

V_CCA

Y23

V_CCDA

H28

H29

J29

V_CCDA

AB10

AB27

AE22

AF18

AF19

AH29

AH8

V_CCDA

_CCIB2

V_CCDA

H31

H35

K27

V_CCDA

L18

L19

M22

N13

R10

V11

V26

B11

B14

B17

V_CCDA

V_CCIB2

L31

V_CCDA

_CCIB2

L35

V_CCDA

P27

AJ28

AJ9

V_CCDA

P31

V_CCDA

P35

AK30

AK7

V_CCIB0

V_CCIB2

R24

_CCIB0

_CCIB2

_CCIB3

U24

U27

U31

U35

AB24

AC27

AC31

AC35

AF31

AF35

AG27

AJ31

AJ35

AM35

Y24

AL30

AL6

AM13

AM24

AM31

AM32

AM5

AM6

AN16

AN21

AP16

AP21

C16

F11

F14

F17

V_CCIB0

V_CCIB3

_CCIB0

_CCIB3

K11

K14

K17

N15

N17

B20

B23

V_CCIB0

_CCIB0

_CCIB1

V_CCIB3

_CCIB3

C21

v5.3

3-61

RTAX-S/SL RadTolerant FPGAs

1272-Pin CCGA/LGA

RTAX4000S Function

Number

RTAX4000S Function

Number

AG14

AG17

AL11

AL14

AL17

AL8

RTAX4000S Function

Number

AM2

Y10

Y13

V_CCIB3

Y27

V_CCIB5

V_CCIB6

_CCIB3

_CCIB4

Y31

_CCIB5

_CCIB6

Y35

AD20

AD22

AG20

AG23

AG26

AL20

AL23

AL26

AL29

AR20

AR23

AR26

AR29

AR32

AD15

AD17

AG11

V_CCIB4

V_CCIB5

V_CCIB6

_CCIB4

_CCIB5

_CCIB6

_CCIB7

AR11

AR14

AR17

AR5

K10

AR8

AB13

AC10

AC2

P10

AC6

R13

U10

U13

AF2

V_CCIB4

V_CCIB6

AF6

V_CCIB7

_CCIB5

_CCIB6

AG10

AJ2

_CCIB7

AJ6

V_PUMP

F32

3-62

v5.3

RTAX-S/SL RadTolerant FPGAs

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous version Changes in current version (v5.3)

Page

v5.2

In Table 2-5 • RTAX-SL Standby Current, the I_CCAspecifications were updated for 125°C.

2-3

(October 2007)

v5.1

The "I/O Logic" section was updated to include information about user flip-flops being immune to SEU.

1-5

(August 2007)

The "Low-Cost Prototyping Solutions" section was updated significantly.

Table 2-4 • RTAX-S Standby Current was updated to include I_IH/I_IL.

Table 2-5 • RTAX-SL Standby Current was updated to include I_IH/I_IL.

The CG1272 was updated in the "Package Thermal Characteristics" table.

1-7

2-3

2-7

2-9

The temperature in note 1 was changed from 175 to 125 in the "Temperature and Voltage Timing

Derating Factors" table.

In the "Timing Model", the Hardwired Clock was changed to Routed or Hardwired.

2-10

v5.0

(June 2007)

The "Ordering Information" section was updated to include the Sigma Six Column and BAE Column

designation. A note was added to the "Temperature Grade Offerings" table regarding the Sigma Six

Column and BAE Column.

v4.0

RTAX-SL information is new.

N/A

(May 2007)

EV Flow (Class V Flow Equivalent Processing) information is new.

The "Ordering Information" section was updated.

The "Actel MIL-STD-883 Class B Product Flow" table was updated.

The "Actel Extended Flow" table was updated.

The "Low-Cost Prototyping Solutions" section was updated to include RTAX-SL prototyping

information.

1-7

Table 2-5 • RTAX-SL Standby Current is new.

2-3

2-8

In the "Sample Case 2: Convection = 0" section, θ_cbwas changed to T_j.

The Axcelerator figure listed below the "V_CCDASupply Voltage" section was incorrect and has been 2-11

removed from the datasheet.

The "256-Pin CQFP" table for the RTAX2000S/SL device is new.

All information regarding the RTAX4000S device is new.

3-5

v3.0

N/A

September 2006

The "Timing Model" was updated.

2-10

The "Specifications" section was updated.

The SEL and SET information was updated in the "Designed for Space" section.

The maximum I/O counts for the RTAX250S and RTAX1000S were updated in Table 1 • RTAX-S/SL

Family Product Profile.

The "Device Resources" table was updated for CG1272/LG1272.

iii

The RTAX-S/SL Testing and Reliability Update white paper was added to the "White Papers"

1-9

section.

The "User I/Os" section was updated with information on configuring unused I/Os.

Implementing DDR was updated in the "Using DDR (Double Data Rate)" section.

PSET was changed to PRE and D was changed to E in Figure 2-6 • DDR Register.

2-12

2-17

v5.3

4-1

RTAX-S/SL RadTolerant FPGAs

Previous version Changes in current version (v5.3)

Page

2-82

2-1

v3.0

The "JTAG" section was updated with JTAG pin information.

(continued)

Figure 2-1 • Use of an External Resistor for 5 V Tolerance was updated.

Note 2 in Table 2-2 • Absolute Maximum Ratings was updated.

The "Calculating Power Dissipation" section was updated.

Table 2-25 • Worst-Case Military Conditions VCCA = 1.4 V, VCCI = 2.3 V, TJ = 125°C was updated.

The "Hardwired Clock" and "Routed Clock" equations were updated.

Table 2-4 • RTAX-S Standby Current was updated.

2-2

2-3

2-30

2-10

2-3

Table 2-6 • Default C_load/ V_CCIwas updated.

2-4

Table 2-9 • Temperature and Voltage Timing Derating Factors was updated.

All timing characteristic tables were updated.

2-9

N/A

3-21

3-51

N/A

The "352-Pin CQFP" table for the RTAX4000S is new.

The "1272-Pin CCGA/LGA" table for the RTAX4000S is new.

All Timing Characteristic tables were updated.

v2.2

May 2006

Cold Sparing was added to the Hot Insertion heading in Table 2-1 • I/O Features Comparison.

The "Thermal Characteristics" section was updated.

2-1

2-7

The "Simultaneous Switching Outputs (SSO)" section was updated.

The "Timing Model" has been updated.

2-14

2-10

2-4

The "Hardwired Clock" and "Routed Clock" equations were updated.

Table 2-6 • Default C_load/ V_CCIwas updated.

Table 2-18 • I/O Weak Pull-Up/Pull-Down Resistances¹is new.

A note was added to Table 2-56 • DC Input and Output Levels.

The LVDS Capable I/O specification was added to "Leading-Edge Performance".

2-21

2-42

i-i

v2.1

October 2005

Table 1 • RTAX-S/SL Family Product Profile was updated to include CQ256.

CQ256 was added to the"Temperature Grade Offerings" table.

CQ256 was is new and CQ352 for the RTAX1000S device was updated in the "Device Resources" table.

The "Overshoot/Undershoot Limits" section is new.

i-i

i-ii

i-iii

2-2

2-10

2-11

Table 2-2 • Absolute Maximum Ratings was updated.

Table 2-3 • RTAX-S/SL Recommended Operating Conditions was updated.

The "Timing Model" has been updated.

The "Hardwired Clock" and "Routed Clock" equations were updated.

This sentence was updated in the "CLKE/F/G/H Global Clocks E, F, G, and H" section:

When the CLK pins are unused, Actel recommends that they are tied to a known state.

Figure 2-27 • LVPECL Circuit was updated. The following labels were corrected:

INBUF_LVPECL

2-42

2-60

OUTBUF_LVPECL

The following sentence was removed from "Global Resource Distribution":

An unused input can be tied to ground for power savings.

The "RAM" section was updated.

2-63

3-4

The "256-Pin CQFP" package figure and is new.

v2.0

In Table 2-4, the I_CCAcolumn heading was changed to I_CCDAand note 3 is new.

2-3

4-2

v5.3

RTAX-S/SL RadTolerant FPGAs

Previous version Changes in current version (v5.3)

Page

i-i

Advanced v0.5

The "Designed for Space" section was updated.

Table 1 was updated to include 1152 CCGA/LGA.

i-i

The "Temperature Grade Offerings" table was updated to include the 1152 CCGA.

The RTAX1000S and the RTAX2000S columns were updated in the "Device Resources" table.

Figure 1-9 was updated and a note was added to the figure.

i-iii

1-8

Table 2-4 • RTAX-S Standby Current was updated.

2-3

In Table 2-4 the LVPECL and LVDS specifications were updated. A note was also added to the table.

The "Global Resource Access Macros" section was updated.

2-3

2-62

2-82

The "JTAG" section was updated.

In the "Data Registers (DRs)" section the IDCODE and USERCODE were changed from 32 bits to 33 bits. 2-82

150°C was changed to 125°C in the "Thermal Characteristics" section.

2-7

Table 2-8 • Package Thermal Characteristics was updated to include the 1152 CCGA. Values in the

table were updated.

A note was added to the "FIFO" section.

2-72

2-4

Table 2-7 • Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices

was updated.

Table 2-16 was updated.

2-19

All Timing Characteristic tables from Table 2-22 to Table 2-82 were updated.

2-25 to

2-63

In the "Actel MIL-STD-883 Class B Product Flow" table, #3 for the 883 Method was updated. A note

was also added to the table.

i-iv

In the "Actel Extended Flow" table, #5 for the Method column was updated. The notes were also added

to the table.

i-iv

In the "Pin Descriptions" section, the descriptions for the "HCLKA/B/C/D Dedicated (Hardwired) Clocks 2-11

A, B, C, and D" and "CLKE/F/G/H Global Clocks E, F, G, and H" were updated.

A footnote was added to the "PRA/B/C/D Probes A, B, C, and D", "TCK2 Test Clock", "TDI2 Test Data 2-12

Input", "TDO2 Test Data Output", and "TDO2 Test Data Output" descriptions.

The "1152-Pin CCGA/LGA" section is new.

3-38

i-i

Advanced v0.4

LET_THvalues for SEU and SEL updated under "Designed for Space".

"Ordering Information" was updated/ The "Temperature Grade Offerings", "Speed Grade and

Temperature Grade Matrix"tables are new and the "Device Resources" was updated.

i-ii

Sections "Actel MIL-STD-883 Class B Product Flow" and "Actel Extended Flow" are new.

"General Description" was updated.

i-iv, i-v

1-1

Table 2-7 • Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices

was updated.

2-4

The"Thermal Characteristics" section was updated.

2-7

Figure 2-4 • Timing Model, the "Hardwired Clock"section and the "Routed Clock" section were 2-10

updated.

v5.3

4-3

RTAX-S/SL RadTolerant FPGAs

Previous version Changes in current version (v5.3)

Page

2-12

2-14

2-17

2-21

Advanced v.04

(continued)

The "Introduction" section under "User I/Os" was updated to give details regarding V_REFusage.

The "Simultaneous Switching Outputs (SSO)" section under "User I/Os" was updated.

"Using DDR (Double Data Rate)" is new.

Table 2-17 was updated.

All Timing Characteristic Tables were updated.

2-25 to

2-81

"Introduction" was updated.

2-48

2-49

2-60

2-65

2-66

2-77

2-82

2-84

3-1

The "SEU Hardened D Flip-Flop (DFF)" section was moved under "R-Cell" and updated.

The "Global Resource Distribution" section is new.

The "Enhancing SEU Performance" section is new.

Figure 2-49 and Figure 2-50 were updated.

Figure 2-57 and Figure 2-58 were updated.

The "Charge Pump Bypass" section is new.

The "TRST" section was updated.

The "Global Set Fuse" section is new.

The "208-Pin CQFP" for both the RTAX250S and RTAX1000S were added.

The "352-Pin CQFP" pin tables for both the RTAX1000S and RTAX2000S were updated.

The "624-Pin CCGA/LGA" pin tables for both the RTAX1000S and RTAX2000S were updated.

The "Designed for Space" section was updated.

3-8

3-25

i-i

Advanced v0.3

A new device, the RTAX250S, was added to the "Designed for Space", "Ordering Information", i to iii

"Temperature Grade Offerings" and "Device Resources" sections.

2.5V GTL+ support across full military range was removed.

n/a

1-4

2-4

Table 1-1 • Number of Core Tiles per Device was updated.

Table 2-4 • RTAX-S Standby Current and Table 2-6 • Default C_load/ V_CCIwere updated.

Table 2-7 • Different Components Contributing to the Total Power Consumption in RTAX-S/SL Devices

was updated.

Table 2-13 • Legal I/O Usage Matrix was updated.

2-15

2-19

3-13

Table 2-16 • I/O Macros for Voltage-Referenced I/O Standards

Advanced v0.2

Advanced v0.1

In the "352-Pin CQFP" for the RTAX1000S, pin 80 has been changed from VCCI to VCCIB6.

In the "208 CQFP" and "352-Pin CQFP", the NC (V_PP) was changed to NC for all pins.

3-2 to

3-13

The 352-Pin CQFP for the RTAX1000S is new.

3-9

Pins 14 and 32 have been changed from VCCA to VCCI for the RTAX2000S in the "352-Pin CQFP".

The "624-Pin CCGA/LGA" for the RTAX1000S is new.

3-32

4-4

v5.3

RTAX-S/SL RadTolerant FPGAs

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Datasheet

Supplement.” The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advanced or production) containing general product

information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

International Traffic in Arms Regulations (ITAR)

The product described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR). They

require an approved export license prior to export from the United States. An export includes release of product or

disclosure of technology to a foreign national inside or outside the United States.

v5.3

4-5

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

www.actel.com

Actel Corporation

Actel Europe Ltd.

Actel Japan

Actel Hong Kong

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Mountain View, CA

94043-4655 USA

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Phone +81.03.3445.7671

Fax +81.03.3445.7668

Phone +852 2185 6460

Fax +852 2185 6488

Phone +44 (0) 1276 609 300

Fax +44 (0) 1276 607 540

http://jp.actel.com

www.actel.com.cn

5172169-11/10.08

RTAX1000-SLB624E [ACTEL]

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