RTSX72SU-1CC256B [ACTEL]

RTSX-SU RadTolerant FPGAs (UMC); RTSX -SU RadTolerant的FPGA （ UMC ）


型号：	RTSX72SU-1CC256B
厂家：	Actel Corporation
描述：	RTSX-SU RadTolerant FPGAs (UMC) RTSX -SU RadTolerant的FPGA （ UMC ）
文件：	总83页 (文件大小：735K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

v2.2

™

RTSX-SU RadTolerant FPGAs (UMC)

Designed for Space

Features

•

SEU-Hardened Registers Eliminate the Need to

Implement Triple-Module Redundancy (TMR)

•

Very Low Power Consumption (Up to 68 mW at

Standby)

–

Immune to Single-Event Upsets (SEU) to LET_th

•

3.3V and 5V Mixed Voltage

Configurable I/O Support for 3.3V/5V PCI, LVTTL,

TTL, and CMOS

> 40 MeV-cm²/mg,

–

SEU Rate < 10^–10Upset/Bit-Day in Worst-Case

Geosynchronous Orbit

–

5V Input Tolerance and 5V Drive Strength

Slow Slew Rate Option

Configurable Weak Resistor Pull-Up/Down for

Tristated Outputs at Power-Up

•

Up to 100 krad (Si) Total Ionizing Dose (TID)

–

Parametric Performance Supported with Lot-

Specific Test Data

–

Hot-Swap

Support

Compliant

with

Cold-Sparing

•

Single-Event Latch-Up (SEL) Immunity

TM1019.5 Test Data Available

QML Certified Devices

•

Secure Programming Technology Prevents Reverse

Engineering and Design Theft

100% Circuit Resource Utilization with 100% Pin

Locking

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Low-Cost Prototyping Option

Deterministic, User-Controllable Timing

JTAG Boundary Scan Testing in Compliance with

IEEE Standard 1149.1 – Dedicated JTAG Reset

(TRST) Pin

High Performance

•

230 MHz System Performance

310 MHz Internal Performance

9.5 ns Input Clock to Output Pad

•

Specifications

•

0.25 µm Metal-to-Metal Antifuse Process (UMC)

48,000 to 108,000 Available System Gates

Up to 2,012 SEU-Hardened Flip-Flops

Up to 360 User-Programmable I/O Pins

Table 1 • RTSX-SU Product Profile

Device

RTSX32SU

RTSX72SU

Capacity

Typical Gates

System Gates

32,000

48,000

72,000

108,000

Logic Modules

2,880

1,800

1,080

6,036

4,024

2,012

Combinatorial Cells

SEU-Hardened Register Cells (Dedicated Flip-Flops)

Maximum Flip-Flops

Maximum User I/Os

Clocks

1,980

227

4,024

360

Quadrant Clocks

Speed Grades

Std., –1

Package (by pin count)

CQFP

CCGA

CCLG

84, 208, 256

256

208, 256

624

March 2006

See the Actel website for the latest version of the datasheet

RTSX-SU RadTolerant FPGAs (UMC)

Ordering Information

RTSX72SU

256

Application (Temperature Range)

B = MIL-STD-883 Class B

E = E-Flow (Actel Space Level Flow)

= Military Temperature

Package Lead Count

Package Type

CQ Ceramic Quad Flat Pack

CG Ceramic Column Grid Aray

CC Ceramic Chip Carrier Land Grid

Speed Grade

Blank = Standard Speed

1 = Approximately 15% Faster than Standard

Part Number

RTSX32SU 32,000 RadTolerant Typical Gates

RTSX72SU 72,000 RadTolerant Typical Gates

Ceramic Device Resources

User I/Os (including clock buffers)

CQFP

CCLG

CCGA

Device

84-Pin

208-Pin

256-Pin

624-Pin

RTSX32SU

RTSX72SU

–

173

170

227

212

202

–

360

Note: The 256-Pin CCLG available in Mil-Temp only.

Temperature Grade and Application Offering

Package

CQ84

RTSX32SU

RTSX72SU

B, E

–

CQ208

CQ256

CC256

CG624

B, E

–

B, E

Note: M = Military Temperature

B = MIL-STD-883 Class B

E = E-Flow

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Speed Grade and Temperature/Application Matrix

Std.

-1

✓

QML Certification

Actel has achieved full QML certification, demonstrating that quality management procedures, processes, and controls

are in place and comply with MIL-PRF-38535 (the performance specification used by the U.S. Department of Defense

for monolithic integrated circuits).

Actel MIL-STD-883 Class B Product Flow

883–Class B

Step

Screen

883 Method

2010, Test Condition B

Requirement

Internal Visual

100%

Temperature Cycling

Constant Acceleration

1010, Test Condition C

100%

2001, Test Condition B or D,

Y₁, Orientation Only

100%

Particle Impact Noise Detection

2020, Condition A

1014

100%

Seal

a. Fine

b. Gross

100%

Visual Inspection

2009

100%

Pre-Burn-In

Electrical Parameters

In accordance with applicable Actel

device specification

Dynamic Burn-In

1015, Condition D,

160 hours at 125°C or 80 hours at 150°C

100%

All Lots

Interim (Post-Burn-In)

Electrical Parameters

In accordance with applicable Actel

device specification

10.

11.

Percent Defective Allowable

Final Electrical Test

In accordance with applicable Actel

device specification, which includes a, b, and c:

a. Static Tests

100%

(1)25°C

(Subgroup 1, Table I)

(2)–55°C and +125°C

(Subgroups 2, 3, Table I)

5005

b. Functional Tests

(1)25°C

(Subgroup 7, Table I)

(2)–55°C and +125°C

(Subgroups 8A and 8B, Table I)

5005

c. Switching Tests at 25°C

(Subgroup 9, Table I)

100%

5005

2009

12.

External Visual

v2.2

iii

RTSX-SU RadTolerant FPGAs (UMC)

Actel Extended Flow

Step

Screen

Method

Requirement

Sample

100%

1. Destructive In-Line Bond Pull³

2011, Condition D

2010, Condition A

2. Internal Visual

3. Serialization

100%

4. Temperature Cycling

5. Constant Acceleration

6. Particle Impact Noise Detection

7. Radiographic

1010, Condition C

100%

2001, Condition B or D, Y₁Orientation Only

2020, Condition A

100%

2012 (one view only)

100%

8. Pre-Burn-In Test

In accordance with applicable Actel device specification

100%

9. Dynamic Burn-In

1015, Condition D, 240 hours at 125°C or 120 hours at

150°C minimum

100%

10. Interim (Post-Burn-In) Electrical Parameters

11. Static Burn-In

In accordance with applicable Actel device specification

100%

1015, Condition C, 72 hours at 150°C or 144 hours at

125°C minimum

12. Interim (Post-Burn-In) Electrical Parameters

In accordance with applicable Actel device specification

5%, 3% Functional Parameters at 25°C

100%

13. Percent Defective Allowable (PDA)

Calculation

All Lots

14. Final Electrical Test

In accordance with Actel applicable device specification

which includes a, b, and c:

100%

a. Static Tests

(1)25°C

5005

(Subgroup 1, Table1)

(2)–55°C and +125°C

(Subgroups 2, 3, Table 1)

b. Functional Tests

(1)25°C

(Subgroup 7, Table 15)

(2)–55°C and +125°C

(Subgroups 8A and B, Table 1)

c. Switching Tests at 25°C

(Subgroup 9, Table 1)

100%

5005

100%

5005

1014

15. Seal

a. Fine

b. Gross

16. External Visual

2009

100%

Notes:

1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Actel offers this

Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The

exceptions to Method 5004 are shown in notes 2 and 4 below.

2. MIL-STD-883, Method 5004, requires a 100 percent radiation latch-up testing to Method 1020. Actel will NOT perform any

radiation testing, and this requirement must be waived in its entirety.

3. Method 5004 requires a 100 percent, nondestructive bond-pull to Method 2003. Actel substitutes a destructive bond-pull to

Method 2011 Condition D on a sample basis only.

4. Wafer lot acceptance complies to commercial standards only (requirement per Method 5007 is not performed).

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Table of Contents

General Description

Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Programmable Interconnect Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Low-Cost Prototyping Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Detailed Specifications

General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

Package Pin Assignments

84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

256-Pin CCLG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

624-Pin CCGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Export Administration Regulations (EAR) or International Traffic in Arms

Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

v2.1

RTSX-SU RadTolerant FPGAs (UMC)

General Description

RTSX-SU RadTolerant FPGAs are enhanced versions of

Actel’s SX-A family of devices, specifically designed for

enhanced radiation performance.

These antifuse interconnects reside between the top two

layers of metal and thereby enable the sea-of-modules

architecture in an FPGA.

Featuring SEU-hardened D-type flip-flops that offer the

benefits of Triple Module Redundancy (TMR) without the

associated overhead, the RTSX-SU family is a unique

product offering for space applications. Manufactured

using 0.25 µm technology at the United Microelectronics

Corporation (UMC) facility in Taiwan, RTSX-SU offers

levels of radiation survivability far in excess of typical

CMOS devices.

The extremely small size of these interconnect elements

gives the RTSX-SU family abundant routing resources and

provides excellent protection against design theft. Reverse

engineering is virtually impossible because it is extremely

difficult to distinguish between programmed and

unprogrammed antifuses. Additionally, since RTSX-SU is a

nonvolatile, single-chip solution, there is no configuration

bitstream to intercept.

The RTSX-SU interconnect (i.e., the antifuses and metal

tracks) also has lower capacitance and resistance than

that of any other device of similar capacity, leading to

the fastest signal propagation in the industry for the

radiation tolerance offered.

Device Architecture

Actel's RTSX-SU architecture, derived from the highly

successful SX-A sea-of-modules architecture, has been

designed to improve upset and total-dose performance

in radiation environments.

I/O Structure

The RTSX-SU family features a flexible I/O structure that

supports 3.3V LVTTL, 5V TTL, 5V CMOS, and 3.3V and 5V

PCI. All I/O standards are hot-swap compliant, cold-

sparing capable, and 5V tolerant (except for 3.3V PCI).

With three layers of metal interconnect in the RTSX32SU

and four metal layers in RTSX72SU, the RTSX-SU family

provides efficient use of silicon by locating the routing

interconnect resources between the top two metal

layers. This completely eliminates the channels of routing

and interconnect resources between logic modules as

In addition, each I/O on an RTSX-SU device can be

configured as an input, an output, a tristate output, or a

bidirectional pin. Mixed I/O standards are allowed and

can be set on a pin-by-pin basis. High or low slew rate

can be set on individual output buffers (except for PCI,

which defaults to high slew), as well as the power-up

configuration (either pull-up or pull-down).

found in traditional FPGAs. In

sea-of-modules

architecture, the entire floor of the FPGA is covered with

a grid of logic modules with virtually no chip area lost to

interconnect elements or routing.

The RTSX-SU architecture adds several enhancements

over the SX-A architecture to improve its performance in

radiation environments, such as SEU-hardened flip-flops,

wider clock lines, and stronger clock drivers.

Even without the inclusion of dedicated I/O registers,

these I/Os, in combination with array registers, can

achieve clock-to-output-pad timing as fast as 9.5 ns. In

most FPGAs, I/O cells that have embedded latches and

flip-flops require instantiation in HDL code; this is a

design complication not encountered in RTSX-SU FPGAs.

Fast pin-to-pin timing ensures that the device will have

little trouble interfacing with any other device in the

system, which in turn, enables parallel design of system

components and reduces overall design time.

Programmable Interconnect

Elements

Interconnection between logic modules is achieved using

Actel’s patented metal-to-metal programmable antifuse

interconnect elements. The antifuses are normally open

circuit and form

permanent, low-impedance

connection when programmed.

The metal-to-metal antifuse is made up of a combination

of amorphous silicon and dielectric material with barrier

metals and has a programmed (“on” state) resistance of

25 Ω with capacitance of 1.0 fF for low signal impedance

(Figure 1-1 on page 1-2).

v2.2

1-1

RTSX-SU RadTolerant FPGAs (UMC)

Routing Tracks

Amorphous Silicon/

Dielectric Antifuse

Tungsten Plug Via

Metal 4

Metal 3

Tungsten Plug Via

Metal 2

Metal 1

Tungsten Plug Contact

Silicon Substrate

Figure 1-1 • RTSX-SU Family Interconnect Elements

While each SEU-hardened R-cell appears as a single D-type

flip-flop to the user, each is implemented employing triple

redundancy to achieve a LET threshold of greater than 40

MeV-cm²/mg. Each TMR R-cell consists of three master-

slave latch pairs, each with asynchronous, self-correcting

feedback paths. The output of each latch on the master or

slave side is voted with the outputs of the other two

latches on that side. If one of the three latches is struck by

an ion and starts to change state, the voting with the

other two latches prevents the change from feeding back

and permanently latching. Care was taken in the layout to

ensure that a single ion strike could not affect more than

one latch (see the "R-Cell" section on page 2-23 for more

details).

Logic Modules

Actel’s RTSX-SU family provides two types of logic

modules to the designer (Figure 1-2 on page 1-3): the

The C-cell implements a range of combinatorial functions

with up to five inputs. Inclusion of the DB input and its

associated inverter function dramatically increases the

number of combinatorial functions that can be

implemented in a single module from 800 options (as in

previous architectures) to more than 4,000 in the RTSX-SU

architecture. An example of the improved flexibility

enabled by the inversion capability is the ability to

integrate a three-input exclusive-OR function into a single

C-cell. This facilitates the construction of nine-bit parity-

tree functions. At the same time, the C-cell structure is

extremely synthesis-friendly, simplifying the overall design

and reducing synthesis time.

Actel has arranged all C-cell and R-cell logic modules into

horizontal banks called Clusters. There are two types of

clusters: Type 1 contains two C-cells and one R-cell, while

Type 2 contains one C-cell and two R-cells.

The R-cell contains a flip-flop featuring asynchronous

clear, asynchronous preset, and clock enable (using the

S0 and S1 lines) control signals. The R-cell registers

feature programmable clock polarity, selectable on a

flexibility during mapping of synthesized functions into

the RTSX-SU FPGA. The clock source for the R-cell can be

chosen from the hardwired clock, the routed clocks, or

the internal logic.

To increase design efficiency and device performance,

Actel has further organized these modules into

SuperClusters. SuperCluster 1 is a two-wide grouping of

Type 1 clusters. SuperCluster 2 is a two-wide group

containing one Type 1 cluster and one Type 2 cluster.

RTSX-SU devices feature more SuperCluster 1 modules

than SuperCluster 2 modules because designers typically

require significantly more combinatorial logic than flip-

flops (Figure 1-2 on page 1-3).

1-2

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Routing

R-cells and C-cells within Clusters and SuperClusters can

be connected through the use of two innovative local

routing resources called FastConnect and DirectConnect,

which enable extremely fast and predictable

interconnection of modules within Clusters and

SuperClusters. This routing architecture also dramatically

reduces the number of antifuses required to complete a

circuit, ensuring the highest possible performance

(Figure 1-3 and Figure 1-4 on page 1-4).

FastConnect enables horizontal routing between any

two logic modules within a given SuperCluster and

vertical routing with the SuperCluster immediately

below it. Only one programmable connection is used in a

FastConnect path, delivering a maximum interconnect

propagation delay of 0.4 ns.

In addition to DirectConnect and FastConnect, the

architecture makes use of two globally-oriented routing

resources known as segmented routing and high-drive

routing. Actel’s segmented routing structure provides a

variety of track lengths for extremely fast routing

between SuperClusters. The exact combination of track

lengths and antifuses within each path is chosen by the

100-percent-automatic place-and-route software to

minimize signal propagation delays.

DirectConnect is a horizontal routing resource that

provides connections from a C-cell to its neighboring R-cell

in a given SuperCluster. DirectConnect uses a hardwired

signal path requiring no programmable interconnection to

achieve its fast signal propagation time of less than 0.1 ns.

C-Cell

R-Cell

Routed

Data Input

PRE

CLR

Direct

Connect

Input

HCLK

CLKA,

CLKB,

Internal Logic

CKS

CKP

A0 B0

A1 B1

Cluster 1

Cluster 2

Cluster 1

Type 1 SuperCluster

Figure 1-2 • R-Cell, C-Cell and Cluster Organization

Type 2 SuperCluster

v2.2

1-3

RTSX-SU RadTolerant FPGAs (UMC)

DirectConnect

• No antifuses for

smallest routing delay

FastConnect

• One antifuse

Routing Segments

• Typically 2 antifuses

• Max. 5 antifuses

Type 1 SuperClusters

Figure 1-3 • DirectConnect and FastConnect for SuperCluster 1’s

DirectConnect

• No antifuses for

smallest routing delay

FastConnect

• One antifuse

Routing Segments

• Typically 2 antifuses

• Max. 5 antifuses

Type 2 SuperClusters

Figure 1-4 • DirectConnect and FastConnect for SuperCluster 2’s

1-4

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Actel's Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

Global Resources

Actel’s high-drive routing structure provides three clock

networks: hardwired clocks (HCLK), routed clocks (CLKA,

CLKB), and quadrant clocks (QCLKA, QCLKB, QCLKC,

QCLKD) (Table 1-1).

timing-driven place-and-route, and

world-class

integrated static timing analyzer and constraints editor.

With the Designer software, a user can select and lock

package pins while only minimally impacting the results

of place-and-route. Additionally, the back-annotation

flow is compatible with all the major simulators and the

simulation results can be cross-probed with Silicon

Explorer II, Actel’s integrated verification and logic

analysis tool. Another tool included in the Designer

software is the SmartGen core generator, which easily

creates popular and commonly used logic functions for

implementation into your schematic or HDL design.

Actel's Designer software is compatible with the most

popular FPGA design entry and verification tools from

companies such as Mentor Graphics, Synplicity,

Synopsys®, and Cadence Design Systems. The Designer

software is available for both the Windows and UNIX

operating systems.

Table 1-1 • RTSX-SU Global Resources

RTSX32SU

RTSX72SU

Routed Clocks (CLKA, CLKB)

Hardwired Clocks (HCLK)

Quadrant Clocks (QCLKA,

QCLKB, QCLKC, QCLKD)

The first clock, called HCLK, is hardwired from the HCLK

buffer to the clock select MUX in each R-cell. HCLK

cannot be connected to combinational logic. This

provides a fast propagation path for the clock signal,

enabling

the

9.5 ns

clock-to-out

(pad-to-pad)

performance of the RTSX-SU devices.

The second type of clock, routed clocks (CLKA, CLKB), are

global clocks that can be sourced from either external

pins or internal logic signals within the device. CLKA and

CLKB may be connected to sequential cells (R-cells) or to

combinational logic (C-cells).

Programming

Programming support is provided through Actel's Silicon

Sculptor II, a single-site programmer driven via a PC-

based GUI. Factory programming is available as well.

The last type of clock, quadrant clocks, are only found in

the RTSX72SU. Similar to the routed clocks, the four

quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD) can be

sourced from external pins or from internal logic signals

within the device. Each of these clocks can individually

drive up to a quarter of the chip, or they can be grouped

together to drive multiple quadrants.

Low-Cost Prototyping Solution

Since the enhanced radiation characteristics of radiation-

tolerant devices are not required during the prototyping

phase of the design, Actel has developed a prototyping

solution for RTSX-SU that utilizes commercial SX-A

devices. The prototyping solution consists of two parts:

Design Environment

•

A well-documented design flow that allows the

customer to target an RTSX-SU design to the

equivalent commercial SX-A device

The RTSX-SU RadTolerant family of FPGAs is fully

supported by both Actel's Libero® Integrated Design

Environment (IDE) and Designer FPGA Development

software. Actel Libero IDE is a design management

environment, seamlessly integrating design tools while

guiding the user through the design flow, managing all

design and log files, and passing necessary design data

among tools. Additionally, Libero IDE allows users to

integrate both schematic and HDL synthesis into a single

•

Either footprint-compatible packages or prototyping

sockets to adapt commercial SX-A packages to the

RTSX-SU package footprints

This methodology provides the user with a cost-effective

solution while maintaining the short time-to-market

associated with Actel FPGAs. Please see the application

note Prototyping for the RTSX-S Enhanced Aerospace

FPGA for more details

flow and verify the entire design in

single

environment. Libero IDE includes Synplify® for Actel

from Synplicity®, ViewDraw for Actel from Mentor

Graphics, ModelSim™ HDL Simulator from Mentor

Graphics®, WaveFormer Lite™ from SynaptiCAD™, and

Designer software from Actel. Refer to the Libero IDE

flow (located on Actel’s website) diagram for more

information.

v2.2

1-5

RTSX-SU RadTolerant FPGAs (UMC)

In-System Diagnostic and Debug Capabilities

The RTSX-SU family of FPGAs includes internal probe

circuitry, allowing the designer to dynamically observe

and analyze any signal inside the FPGA without

disturbing normal device operation. Two individual

signals can be brought out to two multipurpose pins

(PRA and PRB) on the device. The probe circuitry is

accessed and controlled via Silicon Explorer II, Actel's

integrated verification and logic analysis tool, which

attaches to the serial port of a PC and communicates

with the FPGA via the JTAG port. See Figure 1-5.

RTSX-SU FPGA

TDI*

TCK*

TMS*

Silicon Explorer II

Serial Connection

TDO*

PRA*

PRB*

Note: *Refer to the "Pin Descriptions" section on page 2-7 for more information.

Figure 1-5 • Probe Setup

Radiation Survivability

The RTSX-SU RadTolerant devices have varying total-dose

radiation survivability. The ability of these devices to

survive radiation effects is both device and lot

dependent.

All radiation performance information is provided for

informational purposes only and is not guaranteed. Total

dose effects are lot-dependent, and Actel does not

guarantee that future devices will continue to exhibit

similar radiation characteristics. In addition, actual

performance can vary widely due to a variety of factors,

including but not limited to, characteristics of the orbit,

radiation environment, proximity to the satellite

exterior, the amount of inherent shielding from other

sources within the satellite, and actual bare die

variations. For these reasons, it is the sole responsibility

of the user to determine whether the device will meet

the requirements of the specific design.

Total-dose results are summarized in two ways. The first

summary is indicated by the maximum total-dose level

achieved before the device fails to meet an individual

performance specification but remains functional. For

Actel FPGAs, the parameter that first exceeds the

specification is I_CC(standby supply current). The second

summary is indicated by the maximum total dose

achieved prior to the functional failure of the device.

Actel provides total-dose radiation test data on each lot.

Reports are available on Actel’s website or from Actel’s

local sales representatives. Listings of available lots and

devices can also be provided.

Summary

The RTSX-SU family of RadTolerant FPGAs extends Actel’s

highly successful offering of FPGAs for radiation

environments with the industry’s first FPGA designed

specifically for enhanced radiation performance.

For a radiation performance summary, see Radiation

Data. This summary also shows single-event upset (SEU)

and single-event latch-up (SEL) testing that has been

performed on Actel FPGAs.

1-6

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Related Documents

Application Notes

Simultaneous Switching Noise and Signal Integrity

http://www.actel.com/documents/SSN_AN.pdf

Implementation of Security in Actel Antifuse FPGAs

http://www.actel.com/documents/Antifuse_Security_AN.pdf

Using A54SX72A and RT54SX72S Quadrant Clocks

http://www.actel.com/documents/QCLK_AN.pdf

Actel eX, SX-A and RTSX-S I/Os

http://www.actel.com/documents/AntifuseIO_AN.pdf

IEEE Standard 1149.1 (JTAG) in the SX/RTSX/SX-A/eX/RT54SX-S Families

http://www.actel.com/documents/SX_SXAJTAG_AN.pdf

Prototyping for the RT54SX-S Enhanced Aerospace FPGA

http://www.actel.com/documents/RTSXS_Proto_AN.pdf

Actel CQFP to FBFA Adapter Socket Instructions

http://www.actel.com/documents/CQ352-FPGA_Adapter_AN.pdf

Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications

http://www.actel.com/documents/HotSwapColdSparing_AN.pdf

User’s Guides and Manuals

Antifuse Macro Library Guide

http://www.actel.com/documents/libguide_ug.pdf

SmartGen Core Reference Guide

http://www.actel.com/documents/gen_refguide_ug.pdf

Libero IDE User's Guide

http://www.actel.com/documents/libero_ug.pdf

Silicon Sculptor II User’s Guide

http://www.actel.com/documents/SiliSculptII_Sculpt3_ug.pdf

Silicon Explorer User’s Guide

http://www.actel.com/documents/Silexpl_ug.pdf

White Papers

Design Security in Nonvolatile Flash and Antifuse FPGAs

http://www.actel.com/documents/DesignSecurity_WP.pdf

Understanding Actel Antifuse Device Security

http://www.actel.com/documents/AntifuseSecurityWP.pdf

v2.2

1-7

RTSX-SU RadTolerant FPGAs (UMC)

Detailed Specifications

General Conditions

Table 2-1 • Supply Voltages

V_CCA

V_CCI

3.3V

Maximum Input Tolerance

Maximum Output Drive

2.5V

5V*

3.3V

2.5V

Note: *3.3V PCI is not 5V tolerant

Table 2-2 • Characteristics for All I/O Configurations

I/O Standard

TTL, LVTTL

3.3V PCI

Hot Swappable

Slew Rate Control

Yes. Affects falling edge outputs only

No. High slew rate only

Power-Up Resistor Pull

Pull-up or Pull-down

Yes

5V PCI

Yes

No. High slew rate only

Table 2-3 • Time at which I/Os Become Active by Ramp Rate

(At room temperature and nominal operating conditions)

Ramp Rate

Units

0.25V/μs 0.025V/μs

5V/ms

2.5V/ms

0.5V/ms

0.25V/ms

0.1V/ms 0.025V/ms

μs

12.1

47.2

RTSX32SU

RTSX72SU

100

0.46

0.41

0.74

2.8

5.2

0.67

2.6

5.0

Power-Up and Power-Cycling

The RTSX-SU family does not require any specific power-up or power-cycling sequence.

v2.2

2-1

RTSX-SU RadTolerant FPGAs (UMC)

Operating Conditions

Absolute Maximum Conditions

Stresses beyond those listed in Table 2-4 may cause permanent damage to the device. Exposure to absolute maximum rated

conditions may affect device reliability. Devices should not be operated outside the recommendations in Table 2-5.

Table 2-4 • Absolute Maximum Conditions

Symbol

V_CCI

V_CCA

V_I

Parameter

Limits

–0.3 to +6.0

Units

DC Supply Voltage

Input Voltage

–0.3 to +3.0

–0.5 to + 6.0

–0.5 to +V_CCI+ 0.5

V_I

Input Voltage for Bidirectional I/Os when using

3.3V PCI

T_STG

Storage Temperature

–65 to +150

°C

Table 2-5 • Recommended Operating Conditions

Parameter

Military

–55 to +125

2.25 to 2.75

3.0 to 3.6

Units

Temperature Range (case temperature)

2.5V Power Supply Tolerance

3.3V Power Supply Tolerance

5V Power Supply Tolerance

°C

4.5 to 5.5

Power Dissipation

A critical element of system reliability is the ability of

electronic devices to safely dissipate the heat generated

during operation. The thermal characteristics of a circuit

depend on the device and package used, the operating

temperature, the operating current, and the system's

ability to dissipate heat.

Estimating Power Dissipation

The total power dissipation for the RTSX-SU family is the

sum of the DC power dissipation and the AC power

dissipation:

P_Total= P_DC+ P_AC

EQ 2-1

A complete power evaluation should be performed early

in the design process to help identify potential heat-

related problems in the system and to prevent the system

from exceeding the device’s maximum allowed junction

temperature.

DC Power Dissipation

The power due to standby current is typically a small

component of the overall power. The DC power

dissipation is defined as:

The actual power dissipated by most applications is

significantly lower than the power the package can

P_DC= (I_CC)*V_CCA+ (I_CC)*V_CCI

dissipate. However,

a thermal analysis should be

EQ 2-2

performed for all projects. To perform

evaluation, follow these steps:

a power

1. Estimate the power consumption of the application.

2. Calculate the maximum power allowed for the device

and package.

3. Compare the estimated power and maximum power

values.

2-2

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

AC Power Dissipation

The power dissipation of the RTSX-SU family is usually dominated by the dynamic power dissipation. Dynamic power

dissipation is a function of frequency, equivalent capacitance, and power supply voltage. The AC power dissipation is

defined as follows:

P_AC

P_C-Cells+ P_R-Cells+ P_CLKA+ P_CLKB+ P_HCLK+ P_{Output Buffer}+ P_{Input Buffer}

EQ 2-3

or:

P_AC

V_CCA²* [(m * C_EQCM* fm)_C-Cells+ (m * C_EQSM* fm)_R-Cells+ (n * C_EQI* f_n)_{Input Buffer}+ (p * (C_EQO+ C_L) * f_p)_{Output Buffer}

(0.5 * (q₁* C_EQCR* f_q1) + (r₁* f_q1))_CLKA+ (0.5 * (q₂* C_EQCR* f_q2)+ (r₂* f_q2))_CLKB+ (0.5 * (s₁* C_EQHV* f_s1) +

(C_EQHF* f_s1))_HCLK

]

EQ 2-4

Table 2-6 • Fixed Power Parameters

Where:

Parameter

C_EQCM

C_EQSM

C_EQI

RTSX32SU

3.00

1.40

7.40

3.50

4.30

300

RTSX72SU

3.00

1.30

7.40

3.50

4.30

690

Units

C_EQCM= Equivalent capacitance of combinatorial modules

(C-Cells) in pF

C_EQSM= Equivalent capacitance of sequential modules (R-Cells)

in pF

C_EQO

C_EQCR

C_EQHV

C_EQHF

r₁

C_EQI= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in pF

C_EQCR= Equivalent capacitance of CLKA/B in pF

C_EQHV= Variable capacitance of HCLK in pF

C_EQHF= Fixed capacitance of HCLK in pF

C_{L =}Output lead capacitance in pF

100

245

r₂

100

245

I_CC

f_m= Average logic module switching rate in MHz

f_n= Average input buffer switching rate in MHz

f_p= Average output buffer switching rate in MHz

f_q1= Average CLKA rate in MHz

Guidelines for Estimating Power

The following guidelines are meant to represent worst-

case scenarios; they can be generally used to predict the

upper limits of power dissipation:

Logic Modules (m) = 20% of modules

Inputs Switching (n) = # inputs/4

Outputs Switching (p) = # output/4

CLKA Loads (q1) = 20% of R-cells

CLKB Loads (q2) = 20% of R-cells

Load Capacitance (CL) = 35 pF

f_q2= Average CLKB rate in MHz

_s1= Average HCLK rate in MHz

m = Number of logic modules switching at fm

n = Number of input buffers switching at fn

p = Number of output buffers switching at fp

q₁= Number of clock loads on CLKA

q₂= Number of clock loads on CLKB

r₁= Fixed capacitance due to CLKA

r₂= Fixed capacitance due to CLKB

s_{1 =}Number of clock loads on HCLK

x = Number of I/Os at logic low

Average Logic Module Switching Rate (fm) = f/10

Average Input Switching Rate (fn) =f/5

Average Output Switching Rate (fp) = f/10

Average CLKA Rate (fq1) = f/2

Average CLKB Rate (fq2) = f/2

Average HCLK Rate (fs1) = f

HCLK loads (s1) = 20% of R-cells

To assist customers in estimating the power dissipations

of their designs, Actel has published the eX, SX-A and

RT54SX-S Power Calculator worksheet.

y = Number of I/Os at logic high

v2.2

2-3

RTSX-SU RadTolerant FPGAs (UMC)

Thermal Characteristics

Introduction

The temperature variable in Actel’s Designer software

refers to the junction temperature, not the ambient,

case, or board temperatures. This is an important

distinction because dynamic and static power

consumption cause the chip junction to be higher than

the ambient, case, or board temperatures. EQ 2-5, EQ 2-

6, and EQ 2-7 give the relationship between thermal

resistance, temperature gradient and power.

Where:

= Junction-to-air thermal resistance of the package.

θ numbers are located in Table 2-7.

= Junction-to-case thermal resistance of the

package. θ numbers are located in Table 2-7.

= Junction-to-board thermal resistance of the

package. θ_jbfor a 624-pin CCGA is located in the

notes for Table 2-7.

T_j– T_a

θ_ja= ----------------

EQ 2-5

T_j= Junction Temperature

T_a= Ambient Temperature

T_b= Board Temperature

T_c= Case Temperature

T_j– T_c

θ_jc= ---------------

EQ 2-6

T_j– T_b

θ_jb= ----------------

EQ 2-7

= Power

Package Thermal Characteristics

The device thermal characteristics θ_jcand θ_jaare given in Table 2-7. The thermal characteristics for θ_jaare shown with

two different air flow rates. Note that the absolute maximum junction temperature is 150°C.

Table 2-7 • Package Thermal Characteristics

θ_ja

Package Type

Pin Count

θ_jc

Still Air

_ja1.0m/s

33.0

_ja2.5m/s

30.0

18.0

15.0

15.7

14.2

9.1

Units

°C/W

Ceramic Quad Flat Pack (CQFP)

Ceramic Quad Flat Pack (CQFP) with heatsink

Ceramic Chip Carrier Land Grid (CCLG)

Ceramic Column Grid Array (CCGA)

Notes:

2.0 ¹

0.5 ¹

1.1 ¹

6.5 ²

208

19.8

256

16.5

208

21.0

19.0

12.1

8.9

17.3

256

15.7

256

10.0

624

8.5

8.0

1. θ_jcfor CQFP and CCLG packages refers to the thermal resistance between the junction and the bottom of the package.

2. θ_jcfor the CCGA 624 refers to the thermal resistance between the junction and the top surface of the package. Thermal resistance

from junction to board (θ_jb) for CG624 package is 3.4 °C/W.

Maximum Allowed Power Dissipation

Shown below are example calculations to estimate the maximum allowed power dissipation for a given device based

on two different thermal environments while maintaining the device junction temperature at or below worst-case

military operating conditions (125°C).

Example 1:

This example assumes that there is still air in the environment. The heat flow is shown by the arrows in Figure 2-1 on

page 2-5. The maximum ambient air temperature is assumed to be 50°C. The device package used is the 624-pin CCGA.

Max Junction Temp – Max. Ambient Temp

125°C – 50°C

8.9°C/W

Max. Allowed Power = --------------------------------------------------------------------------------------------------------------------- = ----------------------------------- = 8.43W

2-4

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Air

Solder Columns

PCB

Figure 2-1 • Hear Flow when Air is Present

Example 2:

This example assumes that the primary heat conduction path will be through the bottom of the package (neglecting

the heat conducted through the package pins) to the board for a package mounted with thermal paste. The heat flow

is shown by the arrows in Figure 2-2. The maximum board temperature is assumed to be 70°C. The device package

used is the 352-pin CQFP. The thermal resistance (θ_cb) of the thermal paste is assumed to be 0.58 °C/W.

T – T

125°C – 70°C

Max. Allowed Power = ----------------- = ----------------------- = ------------------------------------------------------- = 21.32W

+ θ 2.0°C/W + 0.58°C/W

Thermal Adhesive

PCB

Figure 2-2 • Heat Flow in a Vacuum

Timing Derating

RTSX-SU devices are manufactured in a CMOS process; therefore, device performance is dependent on temperature,

voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating

temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum

operating temperature, and worst-case processing. The derating factors shown in Table 2-8 should be applied to all

timing data contained within this datasheet.

Table 2-8 • Temperature and Voltage Derating Factors

(Normalized to Worst-Case Military Conditions, T_J= 125°C, V_CCA= 2.25V)

Junction Temperature (T_j)

V_CCA

2.25

2.50

2.75

–55°C

0.71

–40°C

0.72

0°C

0.78

0.73

0.69

25°C

0.80

0.75

0.70

70°C

0.90

0.84

0.79

85°C

0.94

0.87

0.82

125°C

1.00

0.67

0.93

0.62

0.63

0.88

Note: The user can set the junction temperature in Actel’s Designer software to be any integer value in the range of –55°C to 175°C, and

the core voltage to be any value between 2.25V and 2.75V.

v2.2

2-5

RTSX-SU RadTolerant FPGAs (UMC)

Timing Model

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

Combinatorial

Cell

= 0.8 ns

= 1.0 ns

I/O Module

RD1

RD2

= 0.7 ns

INYH

= 3.8 ns

DHL

= 1.2 ns

= 0.8 ns

RD1

= 1.5 ns

RD4

= 2.9 ns

RD8

I/O Module

= 3.8 ns

Cell

DHL

RD1

= 0.8 ns

= 0.0 ns

= 0.8 ns

SUD

= 2.5 ns

ENZL

Routed

Clock

= 5.3 ns

RCKH

= 1.0 ns

(100% Load)

RCO

I/O Module

= 3.8 ns

DHL

Cell

I/O Module

= 0.7 ns

INYH

RD1

= 0.8 ns

= 0.0 ns

= 0.8 ns

SUD

= 2.5 ns

ENZL

Hardwired

Clock

RCO

= 3.9 ns

= 1.0 ns

HCKH

Figure 2-3 • RTSX-SU Timing Model

Values shown for RTSX32SU, –1, 0 krad (Si), 5V TTL worst-case military conditions

Hardwired Clock

Routed Clock

External Setup

= (t_INYH+ t_RD2+ t_SUD) – t_HCKH

= 0.7 + 1.0 + 0.8 – 3.9 = –1.4 ns

Clock-to-Out (Pad-to-Pad)

= t_HCKH+ t_RCO+ t_RD1+ t_DHL

= 3.9 + 1.0 + 0.8 + 3.8 = 9.5 ns

= (t_INYH+ t_RD2+ t_SUD) – t_RCKH

= 0.7 + 1.0 + 0.8– 5.3= –2.8 ns

Clock-to-Out (Pad-to-Pad)

= t_RCKH+ t_RCO+ t_RD1+ t_DHL

= 5.3+ 1.0 + 0.8 + 3.8 = 10.9 ns

2-6

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

I/O Specifications

offer a built-in programmable pull-up or pull-down

resistor, active during power-up only.

Pin Descriptions

Supply Pins

HCLK

Dedicated (Hardwired) Array Clock

GND

Ground

This pin is the clock input for sequential modules. Input

levels are compatible with standard TTL, LVTTL, 3.3V PCI or

5V PCI specifications. This input is buffered prior to

clocking the R-cells. It offers clock speeds independent of

the number of R-cells being driven. When not used, this

pin must not be left floating. It must be set to Low or High

on the board. When used, this pin should be held Low or

High during power-up to avoid unwanted static power.

Low supply voltage.

Supply Voltage

CCI

Supply voltage for I/Os. See Table 2-1 on page 2-1.

Supply Voltage

CCA

Supply voltage for Array. See Table 2-1 on page 2-1.

Global Pins

CLKA/B

JTAG/Probe Pins

Routed Clock A and B

PRA/PRB , I/O

Probe A/B

These pins are clock inputs for clock distribution

networks. Input levels are compatible with standard TTL,

LVTTL, 3.3V PCI, or 5V PCI specifications. The clock input

is buffered prior to clocking the R-cells. When not used,

this pin must be set Low or High on the board. When

used, this pin should be held Low or High during power-

up to avoid unwanted static power.

The probe pin is used to output data from any user-

defined design node within the device. This independent

diagnostic pin can be used in conjunction with the other

probe pin to allow real-time diagnostic output of any

signal path within the device. The probe pin can be used

as a user-defined I/O when verification has been

completed. The pin’s probe capabilities can be

permanently disabled to protect programmed design

confidentiality.

For RTSX72SU, these pins can be configured as user I/Os.

When used, this pin offers a built-in programmable pull-

up or pull-down resistor active during power-up only.

TCK , I/O

Test Clock

QCLKA/B/C/D

Quadrant Clock A, B, C, and D / I/O

Test clock input for diagnostic probe and device

programming. In flexible mode, TCK becomes active

when the TMS pin is set Low (Table 2-32 on page 2-35).

This pin functions as an I/O when the boundary scan

state machine reaches the “logic reset” state.

These four pins are the quadrant clock inputs and are

only found on the RTSX72SU. They are clock inputs for

clock distribution networks. Input levels are compatible

with standard TTL, LVTTL, 3.3V PCI or 5V PCI

specifications. Each of these clock inputs can drive up to

a quarter of the chip, or they can be grouped together to

drive multiple quadrants. The clock input is buffered

prior to clocking the core cells.

TDI , I/O

Test Data Input

Serial input for boundary scan testing and diagnostic

probe. In flexible mode, TDI is active when the TMS pin is

set Low (Table 2-32 on page 2-35). This pin functions as

an I/O when the boundary scan state machine reaches

the “logic reset” state.

These pins can be configured as user I/Os. When not

used, these pins must not be left floating. They must be

set Low or High on the board. When used, these pins

1. Actel recommends that you use a series termination resistor on every probe connector (TDI, TCK, TDO, PRA, and PRB). The

series termination is used to prevent data transmission corruption (i.e., due to reflection from the FPGA to the probe

connector) during probing and reading back the checksum. With an internal set-up we have seen 70-ohm termination resistor

improved the signal transmission. Since the series termination depends on the setup, Actel recommends users to calculate the

termination resistor for their own setup. Below is a guideline on how to calculate the resistor value.

The resistor value should be chosen so that the sum of it and the probe signal’s driver impedance equals the effective trace

impedance.

Z0 = Rs + Zd

Z0 = trace impedance (Silicon Explorer’s breakout cable’s resistance + PCB trace impedance), Rs= series termination, Zd= probe

signal’s driver impedance.

The termination resistor should be placed as close as possible to the driver.

Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and hence the

driver impedances needs to be calculated from the SX08/SX16/SX32 IBIS Model IBIS Model (Mixed Voltage Operation). PRA,

PRB, and TDO are driven by the FPGA and driver impedance can also be calculated from the IBIS Model.

Silicon Explorer’s breakout cable’s resistance is usually close to 1 ohm.

v2.2

2-7

RTSX-SU RadTolerant FPGAs (UMC)

TDO , I/O

Test Data Output

Special Functions

Serial output for boundary scan testing. In flexible mode,

TDO is active when the TMS pin is set Low (Table 2-32 on

page 2-35). This pin functions as an I/O when the

boundary scan state machine reaches the "logic reset"

state. When Silicon Explorer II is being used, TDO will act

as an output when the "checksum" command is run. It

will return to user I/O when "checksum" is complete.

No Connection

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

User I/O

TMS

Test Mode Select

The RTSX-SU family features a flexible I/O structure that

supports 3.3V LVTTL, 5V TTL, 5V CMOS, and 3.3V and 5V

PCI. All I/O standards are hot-swap compliant, cold-

sparing capable, and 5V tolerant (except for 3.3V PCI).

The TMS pin controls the use of the IEEE 1149.1

boundary scan pins (TCK, TDI, TDO, TRST). In flexible

mode when the TMS pin is set Low, the TCK, TDI, and

TDO pins are boundary scan pins (Table 2-32 on page 2-

35). Once the boundary scan pins are in test mode, they

will remain in that mode until the internal boundary

scan state machine reaches the “logic reset” state. At this

point, the boundary scan pins will be released and will

function as regular I/O pins. The “logic reset” state is

reached five TCK cycles after the TMS pin is set High. In

dedicated test mode, TMS functions as specified in the

IEEE 1149.1 specifications.

Each I/O module has an available power-up resistor of

approximately 50 kΩ that can configure the I/O to a

known state during power-up. Just slightly before V_CCA

reaches 2.5V, the resistors are disabled so the I/Os will

behave normally. For more information about the

power-up resistors, please see Actel’s application note

SX-A and RTSX-S Devices in Hot-Swap and Cold Sparing

Applications.

RTSX-SU inputs should be driven by high-speed push-pull

devices with a low-resistance pull-up device. If the input

voltage is greater than V_CCIand a fast push-pull device is

NOT used, the high-resistance pull-up of the driver and

the internal circuitry of the RTSX-SU I/O may create a

voltage divider (when a user I/O is configured as an

input, the associated output buffer is tristated). This

voltage divider could pull the input voltage below

specification for some devices connected to the driver. A

logic ‘1’ may not be correctly presented in this case. For

example, if an open drain driver is used with a pull-up

resistor to 5V to provide the logic ‘1’ input, and V_CCIis set

to 3.3V on the RTSX-SU device, the input signal may be

pulled down by the RTSX-SU input.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active-low input to

asynchronously initialize or rest the boundary scan

circuit. The TRST pin is equipped with an internal pull-up

resistor. For flight applications, the TRST pin should be

hardwired to GND.

User I/O

I/O

Input/Output

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Input and output levels are

compatible with standard TTL, LVTTL, 3.3V/5V PCI, or 5V

CMOS specifications. Unused I/O pins are automatically

tristated by the Designer software. See the "User I/O"

section on page 2-8 for more details.

2. Actel recommends that you use a series termination resistor on every probe connector (TDI, TCK, TDO, PRA, and PRB). The

series termination is used to prevent data transmission corruption (i.e., due to reflection from the FPGA to the probe

connector) during probing and reading back the checksum. With an internal set-up we have seen 70-ohm termination resistor

improved the signal transmission. Since the series termination depends on the setup, Actel recommends users to calculate the

termination resistor for their own setup. Below is a guideline on how to calculate the resistor value.

The resistor value should be chosen so that the sum of it and the probe signal’s driver impedance equals the effective trace

impedance.

Z0 = Rs + Zd

Z0 = trace impedance (Silicon Explorer’s breakout cable’s resistance + PCB trace impedance), Rs= series termination, Zd= probe

signal’s driver impedance.

The termination resistor should be placed as close as possible to the driver.

Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and hence the

driver impedances needs to be calculated from the SX08/SX16/SX32 IBIS Model (Mixed Voltage Operation). PRA, PRB, and

TDO are driven by the FPGA and driver impedance can also be calculated from the IBIS Model.

Silicon Explorer’s breakout cable’s resistance is usually close to 1 ohm.

2-8

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

and I/O properties editor. See the PinEditor online help

for more information.

Hot Swapping

RTSX-SU I/Os can be configured to be hot swappable in

compliance with the Compact PCI Specification.

However, a 3.3V PCI device is not hot swappable. During

power-up/down, all I/Os are tristated. V_CCAand V_CCIdo

not have to be stable during power-up/down. After the

RTSX-SU device is plugged into an electrically active

system, the device will not degrade the reliability of or

cause damage to the host system. The device’s output

pins are driven to a high impedance state until normal

chip operating conditions are reached. Table 2-3 on

page 2-1 summarizes the V_CCAvoltage at which the I/Os

behave according to the user’s design for an RTSX-SU

device at room temperature for various ramp-up rates.

The data reported assumes a linear ramp-up profile to

2.5V. Refer to Actel’s application note, SX-A and RTSX-S

Devices in Hot-Swap and Cold-Sparing Applications for

more information on hot swapping.

Unused I/Os

All unused user I/Os are automatically tristated by Actel’s

Designer software. Although termination is not

required, it is recommended that the user tie off all

unused I/Os to GND externally. If the I/O clamp diode is

disabled, then unused I/Os are 5V tolerant, otherwise

unused I/Os are tolerant to V_CCI

I/O Macros

There are nine I/O macros available to the user for

RTSX-SU:

•

CLKBUF/CLKBUFI: Clock Buffer, noninverting and

inverting

CLKBIBUF/CLKBIBUFI: Bidirectional Clock Buffer,

noninverting and inverting

QCLKBUF/QCLKBUFI:

Quad

Clock

Buffer,

Customizing the I/O

noninverting and inverting

QCLKBIBUF/QCLKBIBUFI: Quad Bidirectional Clock

Buffer, noninverting and inverting

Each user I/O on an RTSX-SU device can be configured as

an input, an output, a tristate output, or a bidirectional

pin. Mixed I/O standards are allowed and can be set on a

pin-by-pin basis. High or low slew rates can be set on

individual output buffers (except for PCI which defaults

to high slew), as well as the power-up configuration

(either pull-up or pull-down).

•

HCLKBUF: Hardwired Clock Buffer

INBUF: Input Buffer

OUTBUF: Output Buffer

TRIBUF: Tristate Buffer

The user selects the desired I/O by setting the I/O

properties in PinEditor, Actel’s graphical pin-placement

BIBUF: Bidirectional Buffer

Table 2-9 • User I/O Features

Function

Description

Input Buffer Threshold Selections

•

5V: CMOS, PCI, TTL

3.3V: PCI, LVTTL

Flexible Output Driver

•

5V: CMOS, PCI, TTL

3.3V: PCI, LVTTL

Selectable on an individual I/O basis

Output Buffer

“Hot-Swap” Capability

•

I/Os on an unpowered device does not sink the current (Power supplies are at 0V)

Can be used for “cold sparing”

Individually selectable slew rate, high or low slew (The default is high slew rate). The slew

rate selection only affects the falling edge of an output. There is no change on the rising

edge of the output or any inputs

Power-Up

Individually selectable pull-ups and pull-downs during power-up (default is to power-up

in tristate mode)

Enables deterministic power-up of a device

V_CCAand V_CCIcan be powered in any order

v2.2

2-9

RTSX-SU RadTolerant FPGAs (UMC)

I/O Module Timing Characteristics

PAD To AC test loads (shown below)

TRIBUFF

V_CC

GND

50% 50%

V_OH

GND

10%

GND

90%

50% 50%

V_CC

50% 50%

V_OH

MEAS

Pad

VPad

GND

MEAS

V_OL

t_DLH

t_DHL

t_ENZL

t_ENLZ

t_ENZH

t_{EN HZ}

Figure 2-4 • Output Timing Model and Waveforms

CCI

50%

Pad

MEAS

PAD

INBUF

GND

50%

t_INYH

INYL

Figure 2-5 • Input Timing Model and Waveforms

Load 2

(Used to measure enable delays)

Load 3

(Used to measure disable delays)

Load 1

(Used to measure

propagation delay)

V_CC

GND

V_CC

GND

To the output

under test

35 pF

R to V_CCfor t_PZL

R to GND for t_PZH

R = 1 kΩ

R to V_CCfor t_PLZ

R to GND for t_PHZ

R = 1 kΩ

To the output

under test

To the output

under test

35 pF

5 pF

Figure 2-6 • AC Test Loads

2-10

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

5V TTL and 3.3V LVTTL

Table 2-10 • 5V TTL and 3.3V LVTTL Electrical Specifications

Military

Symbol

Parameter

Min.

Max.

Units

V_OH

V_CCI= Min.

V_I= V_IHor V_IL

(I_OH= –1mA)

(I_OH= –8mA)

(I_OL= 1mA)

0.9 V_CCI

V_CCI= Min.

2.4

V_I= V_IHor V_IL

V_OL

V_CCI= Min.

V_I= V_IHor V_IL

0.1 V_CCI

0.4

V_CCI= Min.

(I_OL= 12mA)

V_I= V_IHor V_IL

V_IL

Input Low Voltage

Input High Voltage

0.8

V_IH

2.0

I_IL/ I_IH

I_OZ

Input Leakage Current, V_IN= V_CCIor GND

(V_CCI≤ 5.25V)

(V_CCI≤ 5.5V)

–20

–70

µA

Tristate Output Leakage Current, V_OUT= V_CCIor GND

(V_CCI≤ 5.25V)

(V_CCI≤ 5.5V)

–20

–70

µA

t_R, t_F

Input Transition Time

C_IN

Input Pin Capacitance⁴

C_CLK

CLK Pin Capacitance⁴

V_MEAS

IV Curve⁵

Notes:

Trip point for Input buffers and Measuring point for Output buffers

Can be derived from the IBIS model on the web.

1.5

1. For AC signals, the input signal may undershoot during transitions to –1.2 V for no longer than 11 ns. Current during the transition

must not exceed 95 mA.

2. For AC signals, the input signal may overshoot during transitions to V_CCI+ 1.2 V for no longer than 11 ns. Current during the

transition must not exceed 95 mA.

3. If t_Ror t_Fexceeds the limit of 10 ns, Actel can guarantee reliability but not functionality.

4. Absolute maximum pin capacitance, which includes package and I/O input capacitance.

5. The IBIS model can be found at www.actel.com/techdocs/models/ibis.html.

v2.2

2-11

RTSX-SU RadTolerant FPGAs (UMC)

Timing Characteristics

Table 2-11 • RTSX32SU 5V TTL and 3.3V LVTTL I/O Module

Worst-Case Military Conditions V_CCA= 2.25V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed

Min. Max.

‘Std.’ Speed

Parameter

Description

Min.

Max.

Units

5V TTL Output Module Timing (V_CCI= 4.5V)

t_INYH

t_INYL

Input Data Pad-to-Y High

0.7

1.1

0.9

1.3

Input Data Pad-to-Y Low

t_DLH

Data-to-Pad Low to High

3.1

3.6

t_DHL

Data-to-Pad High to Low

3.8

4.4

t_DHLS

t_ENZL

t_DENZLS

t_ENZH

t_ENLZ

t_ENHZ

Data-to-Pad High to Low – low slew

Enable-to-Pad, Z to Low

9.8

11.5

3.0

2.5

Enable-to-Pad, Z to Low – low slew

Enable-to-Pad, Z to High

9.0

10.6

3.6

3.1

Enable-to-Pad, Low to Z

4.4

5.3

Enable-to-Pad, High to Z

3.8

4.4

d_TLH

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

Delta Delay vs. Load High to Low – low slew

0.036

0.029

0.049

0.046

0.038

0.064

ns/pF

d_THL

d_THLS

3.3V LVTTL Output Module Timing (V_CCI= 3.0V)

t_INYH

t_INYL

Input Data Pad-to-Y High

0.8

1.1

0.9

1.3

Input Data Pad-to-Y Low

t_DLH

Data-to-Pad Low to High

4.1

4.8

t_DHL

Data-to-Pad High to Low

3.7

4.4

t_DHLS

t_ENZL

t_DENZLS

t_ENZH

t_ENLZ

t_ENHZ

Data-to-Pad High to Low – low slew

Enable-to-Pad, Z to L

13.2

2.9

15.6

3.4

Enable-to-Pad, Z to Low – low slew

Enable-to-Pad, Z to H

12.7

4.1

14.9

4.8

Enable-to-Pad, L to Z

3.7

4.4

Enable-to-Pad, H to Z

3.7

4.4

d_TLH

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

Delta Delay vs. Load High to Low – low slew

0.064

0.031

0.069

0.081

0.040

0.088

ns/pF

d_THL

d_THLS

Notes:

1. Output delays based on 35 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI- 0.9*V_CCI)/ (C_load* d_TLH|d_THL|d_THLS

where C_loadis the load capacitance driven by the I/O in pF;

)

_TLH|d_THL|d_THLSis the worst case delta value from the datasheet in ns/pF.

2-12

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Table 2-12 • RTSX72SU 5V TTL and 3.3V LVTTL I/O Module

Worst-Case Military Conditions V_CCA= 2.25V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Units

5V TTL Output Module Timing (V_CCI= 4.5V)

t_INYH

t_INYL

Input Data Pad-to-Y High

0.7

1.1

0.9

1.3

Input Data Pad-to-Y Low

t_DLH

Data-to-Pad Low to High

3.2

3.7

t_DHL

Data-to-Pad High to Low

4.0

4.7

t_DHLS

t_ENZL

t_DENZLS

t_ENZH

t_ENLZ

t_ENHZ

Data-to-Pad High to Low – low slew

Enable-to-Pad, Z to Low

10.3

2.5

12.1

3.0

Enable-to-Pad, Z to Low – low slew

Enable-to-Pad, Z to High

9.0

10.6

3.7

3.2

Enable-to-Pad, Low to Z

4.4

5.3

Enable-to-Pad, High to Z

4.0

4.7

d_TLH

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

Delta Delay vs. Load High to Low – low slew

0.036

0.029

0.049

0.046

0.038

0.064

ns/pF

d_THL

d_THLS

3.3V LVTTL Output Module Timing (V_CCI= 3.0V)

t_INYH

t_INYL

Input Data Pad-to-Y High

1.0

2.2

1.2

2.5

Input Data Pad-to-Y Low

t_DLH

Data-to-Pad Low to High

4.0

4.6

t_DHL

Data-to-Pad High to Low

3.6

4.2

t_DHLS

t_ENZL

t_DENZLS

t_ENZH

t_ENLZ

t_ENHZ

Data-to-Pad High to Low – low slew

Enable-to-Pad, Z to L

12.7

2.9

14.9

3.4

Enable-to-Pad, Z to Low – low slew

Enable-to-Pad, Z to H

12.7

4.0

14.9

4.6

Enable-to-Pad, L to Z

3.9

4.4

Enable-to-Pad, H to Z

3.6

4.2

d_TLH

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

Delta Delay vs. Load High to Low – low slew

0.064

0.031

0.069

0.081

0.04

0.088

ns/pF

d_THL

d_THLS

Notes:

1. Output delays based on 35 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI- 0.9*V_CCI)/ (C_load* d_TLH|d_THL|d_THLS

where C_loadis the load capacitance driven by the I/O in pF;

)

_TLH|d_THL|d_THLSis the worst case delta value from the datasheet in ns/pF.

v2.2

2-13

RTSX-SU RadTolerant FPGAs (UMC)

5V CMOS

Table 2-13 • 5V CMOS Electrical Specifications

Military

Min.

V_CCI- 0.1

Symbol

Parameter

Max.

Units

V_OH

V_CCI= MIN,

V_I= V_CCIor GND

(I_OH= –20μA)

(I_OL20μA)

V_OL

V_CCI= MIN,

0.1

V_I= V_CCIor GND

V_IL

Input Low Voltage, V_OUT= V_VOL(max)

Input High Voltage, V_OUT= V_VOH(min)

0.3V_CC

V_IH

0.7V_CC

I_IL/I_IH

Input Leakage Current, V_IN= V_CCIor GND

(V_CCI≤ 5.25V)

(V_CCI≤ 5.5V)

–20

–70

µA

I_OZ

Tristate Output Leakage Current, V_OUT= V_CCIor GND

(V_CCI≤ 5.25V)

(V_CCI≤ 5.5V)

–20

–70

µA

t_R, t_F

C_IN

Input Transition Time

Input Pin Capacitance³

CLK Pin Capacitance³

C_CLK

V_MEAS

Trip point for Input buffers and Measuring point for Output buffers

2.5

IV Curve³Can be derived from the IBIS model on the web.

Notes:

1. For AC signals, the input signal may undershoot during transitions –1.2 V for no longer than 11 ns. Current during the transition

must not exceed 95 mA.

2. For AC signals, the input signal may overshoot during transitions V_CCI+ 1.2 V for no longer than 11 ns. Current during the

transition must not exceed 95 mA.

3. The IBIS model can be found at www.actel.com/techdocs/models/ibis.html.

2-14

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Timing Characteristics

Table 2-14 • RTSX32SU 5V CMOS I/O Module

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 4.5V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max. Min. Max.

Parameter

Description

Units

5V CMOS Output Module Timing

t_INYH

t_INYL

Input Data Pad-to-Y High

0.7

1.1

0.9

1.3

Input Data Pad-to-Y Low

t_DLH

Data-to-Pad Low to High

3.4

4.0

t_DHL

Data-to-Pad High to Low

3.6

4.2

t_DHLS

t_ENZL

t_DENZLS

t_ENZH

t_ENLZ

t_ENHZ

Data-to-Pad High to Low – low slew

Enable-to-Pad, Z to Low

8.7

10.3

2.8

2.3

Enable-to-Pad, Z to Low – low slew

Enable-to-Pad, Z to High

8.8

10.4

4.2

3.6

Enable-to-Pad, Low to Z

4.5

5.3

Enable-to-Pad, High to Z

3.4

4.0

d_TLH

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

Delta Delay vs. Load High to Low – low slew

0.036

0.029

0.049

0.046

0.038

0.064

ns/pF

d_THL

d_THLS

Notes:

1. Output delays based on 35 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI- 0.9*V_CCI)/ (C_load* d_TLH|d_THL|d_THLS

where C_loadis the load capacitance driven by the I/O in pF;

)

d_TLH|d_THL|d_THLSis the worst case delta value from the datasheet in ns/pF.

Table 2-15 • RTSX72SU 5V CMOS I/O Module

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 4.5V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed

Min. Max.

‘Std.’ Speed

Min. Max.

Parameter

Description

Units

5V CMOS Output Module Timing

t_INYH

t_INYL

Input Data Pad-to-Y High

0.7

0.0

0.9

0.0

Input Data Pad-to-Y Low

t_DLH

Data-to-Pad Low to High

3.6

4.2

t_DHL

Data-to-Pad High to Low

3.8

4.5

t_DHLS

t_ENZL

t_DENZLS

t_ENZH

t_ENLZ

t_ENHZ

Data-to-Pad High to Low – low slew

Enable-to-Pad, Z to Low

9.2

10.8

2.8

2.3

Enable-to-Pad, Z to Low – low slew

Enable-to-Pad, Z to High

8.8

10.4

4.5

3.8

Enable-to-Pad, Low to Z

4.5

5.3

Enable-to-Pad, High to Z

3.6

4.2

d_TLH

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

Delta Delay vs. Load High to Low – low slew

0.036

0.029

0.049

0.046

0.038

0.064

ns/pF

d_THL

d_THLS

Notes:

1. Output delays based on 35 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI- 0.9*V_CCI)/ (C_load* d_TLH|d_THL|d_THLS

where C_loadis the load capacitance driven by the I/O in pF;

)

_TLH|d_THL|d_THLSis the worst case delta value from the datasheet in ns/pF.

v2.2

2-15

RTSX-SU RadTolerant FPGAs (UMC)

5V PCI

The RTSX-SU family supports 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.

Table 2-16 • 5V PCI DC Specifications

Symbol

V_CCA

V_CCI

V_IH

Parameter

Condition

Min.

2.25

4.5

Max.

2.75

Units

Supply Voltage for Array

Supply Voltage for I/Os

Input High Voltage¹

Input Low Voltage¹

5.5

2.0

V_CCI+ 0.5

0.8

V_IL

–0.5

I_IH

Input High Leakage Current

Input Low Leakage Current

Output High Voltage

V_IN= 2.75

V_IN= 0.5

µA

I_IL

–70

V_OH

V_OL

I_OUT= –2 mA

I_OUT= 3 mA, 6 mA

2.4

Output Low Voltage²

0.55

C_IN

Input Pin Capacitance³

C_CLK

V_MEAS

Notes:

CLK Pin Capacitance

Trip Point for Input Buffers and Measuring Point for Output Buffers

1.5

1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter include,

FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and

ACK64#.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only devices,

which could be up to 16 pF in order to accommodate PGA packaging. This mean that components for expansion boards need to use

alternatives to ceramic PGA packaging (i.e., PBGA,PQFP, SGA, etc.).

200.0

Max. Specification

150.0

100.0

50.0

Min. Specification

0.0

0.5

1.5

2.5

3.5

4.5

5.5

–50.0

–100.0

–150.0

–200.0

Min. Specification

Max. Specification

Voltage Out (V)

Figure 2-7 • 5V PCI V/I Curve for RTSX-SU

Equation A

Equation B

I_OH= 11.9 * (V_OUT– 5.25) * (V_OUT+ 2.45)

I_OL= 78.5 * V_OUT* (4.4 – V_OUT

for 0V < V_OUT< 0.71V

)

for V_CCI> V_OUT> 3.1V

2-16

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Table 2-17 • 5V PCI AC Specifications

Symbol

Parameter

Condition

0 < V_OUT< 1.4 ¹

1.4 < V_OUT< 2.4 ^{1, 2}

Min.

–44

Max.

Units

I_OH(AC)

Switching Current High

(–44 + (V_OUT– 1.4)/0.024)

1, 3

3.1 < V_OUT< V_CCI

"Equation A" on

page 2-16

(Test Point)

_OUT= 3.1 ³

–142

I_OL(AC)

V_OUT= 2.2 ¹

Switching Current Low

2.2 > V_OUT> 0.55 ¹

0.71 > V_OUT> 0 ^{1, 3}

(V_OUT/0.023)

"Equation B" on

page 2-16

(Test Point)

V_OUT= 0.71

206

I_CL

Low Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–5 < V_IN≤ –1

–25 + (V_IN+ 1)/0.015

slew_R

slew_F

Notes:

0.4V to 2.4V load⁴

2.4V to 0.4V load⁴

V/ns

1. Refer to the V/I curves in Figure 2-7 on page 2-16. Switching current characteristics for REQ# and GNT# are permitted to be one

half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and

RST#, which are system outputs. The “Switching Current High” specification is not relevant to SERR#, INTA#, INTB#, INTC#, and

INTD#, which are open drain outputs.

2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than

toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.

3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A

and B) are provided with the respective curves in Figure 2-7 on page 2-16. The equation defined maximum should be met by the

design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.

4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any

point within the transition range. The specified load is optional; i.e., the designer may elect to meet this parameter with an

unloaded output per revision 2.0 of the PCI Local Bus Specification (Figure 2-8). However, adherence to both the maximum and

minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate

was not required prior to revision 2.1 of the specification, there may be components in the market that have faster edge rates;

therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should

ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.

output

buffer

50 pF

Figure 2-8 • 5V PCI Output Loading

v2.2

2-17

RTSX-SU RadTolerant FPGAs (UMC)

Timing Characteristics

Table 2-18 • RTSX32SU 5V PCI I/O Module

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 4.5V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max. Min. Max.

Parameter

Description

Units

5V PCI Output Module Timing

t_INYH

t_INYL

t_DLH

Input Data Pad-to-Y High

Input Data Pad-to-Y Low

0.7

1.1

0.9

1.3

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to Low

3.4

4.0

t_DHL

4.1

4.8

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

2.8

3.3

Enable-to-Pad, Z to High

Enable-to-Pad, Low to Z

3.4

4.0

4.9

5.8

Enable-to-Pad, High to Z

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

4.1

4.8

d_TLH

0.036

0.029

0.046

0.038

ns/pF

d_THL

Notes:

1. Output delays based on 35 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI- 0.9*V_CCI)/ (C_load* d_TLH|d_THL|d_THLS

where C_loadis the load capacitance driven by the I/O in pF;

)

d_TLH|d_THL|d_THLSis the worst case delta value from the datasheet in ns/pF.

Table 2-19 • RTSX72SU 5V PCI I/O Module

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 4.5V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed

Min. Max.

‘Std.’ Speed

Min. Max.

Parameter

Description

Units

5V PCI Output Module Timing

t_INYH

t_INYL

t_DLH

Input Data Pad-to-Y High

Input Data Pad-to-Y Low

0.7

1.1

0.9

1.3

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to Low

3.5

4.1

t_DHL

4.3

5.1

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

2.8

3.3

Enable-to-Pad, Z to High

Enable-to-Pad, Low to Z

3.5

4.1

4.9

5.8

Enable-to-Pad, High to Z

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

4.3

5.1

d_TLH

0.036

0.029

0.046

0.038

ns/pF

d_THL

Notes:

1. Output delays based on 35 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI- 0.9*V_CCI)/ (C_load* d_TLH|d_THL|d_THLS

where C_loadis the load capacitance driven by the I/O in pF;

)

d_TLH|d_THL|d_THLSis the worst case delta value from the datasheet in ns/pF.

2-18

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

3.3V PCI

The RTSX-SU family supports 3.3V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.

Table 2-20 • 3.3 V PCI DC Specifications

Symbol

V_CCA

V_CCI

V_IH

Parameter

Supply Voltage for Array

Condition

Min.

2.25

Max.

2.75

Units

Supply Voltage for I/Os

3.0

3.6

Input High Voltage

0.5V_CCI

–0.5

V_CCI+ 0.5

0.3V_CCI

V_IL

Input Low Voltage

I_IPU

Input Pull-up Voltage¹

0.7V_CCI

I_IL/I_IH

V_OH

Input Leakage Current²

0 < V_IN< V_CCI

μA

Output High Voltage

I_OUT= –500 µA

I_OUT= 1500 µA

0.9V_CCI

V_OL

Output Low Voltage

Input Pin Capacitance³

0.1V_CCI

C_IN

C_CLK

V_MEAS

CLK Pin Capacitance

Trip point for Input buffers

Output buffer measuring point - rising edge

Output buffer measuring point - falling edge

0.4 * V_CCI

0.285 * V_CCI

0.615 * V_CCI

Notes:

1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a

floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current

at this input V_IN.

2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-only

devices, which could be up to 16 pF, in order to accommodate PGA packaging. This means that components for expansion boards

would need to use alternatives to ceramic PGA packaging.

150.0

Max. Specification

100.0

50.0

Min. Specification

0.0

0.5

1.5

2.5

3.5

–50.0

–100.0

–150.0

Min. Specification

Max. Specification

Voltage Out (V)

Figure 2-9 • 3.3V PCI V/I Curve for the RTSX-SU Family

Equation C

Equation D

I_OH= (98.0/V_CCI) * (V_OUT– V_CCI) * (V_OUT+ 0.4V_CCI

)

I_OL= (256/V_CCI) * V_OUT* (V_CCI– V_OUT

)

for V_CCI> V_OUT> 0.7 V_CCI

for 0V < V_OUT< 0.18 V_CCI

v2.2

2-19

RTSX-SU RadTolerant FPGAs (UMC)

Table 2-21 • 3.3V PCI AC Specifications

Symbol

Parameter

Condition

Min.

–12V_CCI

Max.

Units

I_OH(AC)

Switching Current High

0 < V_OUT≤ 0.3V_CCI

0.3V_CCI≤ V_OUT< 0.9V_CCI

(–17.1 + (V_CCI– V_OUT))

1, 2

0.7V_CCI< V_OUT< V_CCI

"Equation C" on

page 2-19

(Test Point)

_OUT= 0.7V_CC

–32V_CCI

I_OL(AC)

Switching Current Low

V_CCI> V_OUT≥ 0.6V_CCI

16V_CCI

0.6V_CCI> V_OUT> 0.1V_CCI

0.18V_CCI> V_OUT> 0 ^{1, 2}

(26.7V_OUT)

"Equation D" on

page 2-19

(Test Point)

V_OUT= 0.18V_CC

38V_CCI

I_CL

Low Clamp Current

High Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–3 < V_IN≤ –1

–25 + (V_IN+ 1)/0.015

I_CH

V_CCI+ 4 > V_IN≥ V_CCI+ 1

0.2V_CCIto 0.6V_CCIload ³

0.6V_CCIto 0.2V_CCIload ³

25 + (V_IN– V_CCI– 1)/0.015

slew_R

slew_F

Notes:

V/ns

1. Refer to the V/I curves in Figure 2-9 on page 2-19. Switching current characteristics for REQ# and GNT# are permitted to be one

half of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and

RST#, which are system outputs. The “Switching Current High” specification is not relevant to SERR#, INTA#, INTB#, INTC#, and

INTD#, which are open drain outputs.

2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C

and D) are provided with the respective curves in Figure 2-9 on page 2-19. The equation defined maximum should be met by the

design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.

3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any

point within the transition range. The specified load is optional (Figure 2-10); i.e., the designer may elect to meet this parameter

with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and

minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain

outputs.

1/2 in. max.

Output

Buffer

Output

Buffer

10 pF

V_CC

1 k/25 Ω

10 pF

Figure 2-10 • 3.3V PCI Output Loading

2-20

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Timing Characteristics

Table 2-22 • RTSX32SU 3.3V PCI I/O Module

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 3.0V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max. Min. Max.

Parameter

Description

Units

3.3V PCI Output Module Timing

t_INYH

t_INYL

t_DLH

Input Data Pad-to-Y High

Input Data Pad-to-Y Low

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to Low

Enable-to-Pad, Z to High

Enable-to-Pad, Low to Z

Enable-to-Pad, High to Z

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

0.8

0.9

1.1

3.0

3.5

t_DHL

3.0

3.5

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

2.1

2.5

3.0

3.5

2.7

3.9

3.0

3.5

d_TLH

0.067

0.031

0.085

0.040

ns/pF

d_THL

Notes:

1. Output delays based on 35 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI- 0.9*V_CCI)/ (C_load* d_TLH|d_THL|d_THLS

where C_loadis the load capacitance driven by the I/O in pF;

)

d_TLH|d_THL|d_THLSis the worst case delta value from the datasheet in ns/pF.

Table 2-23 • RTSX72SU 3.3V PCI I/O Module

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 3.0V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed

Min. Max.

‘Std.’ Speed

Min. Max.

Parameter

Description

Units

3.3V PCI Output Module Timing

t_INYH

t_INYL

t_DLH

Input Data Pad-to-Y High

Input Data Pad-to-Y Low

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to Low

Enable-to-Pad, Z to High

Enable-to-Pad, Low to Z

Enable-to-Pad, High to Z

Delta Delay vs. Load Low to High

Delta Delay vs. Load High to Low

0.7

0.9

0.8

1.1

2.8

3.3

t_DHL

2.8

3.3

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

2.1

2.5

2.8

3.3

2.7

3.9

2.8

3.3

d_TLH

0.067

0.031

0.085

0.040

ns/pF

d_THL

Notes:

1. Output delays based on 35 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI- 0.9*V_CCI)/ (C_load* d_TLH|d_THL|d_THLS

where C_loadis the load capacitance driven by the I/O in pF;

)

d_TLH|d_THL|d_THLSis the worst case delta value from the datasheet in ns/pF.

v2.2

2-21

RTSX-SU RadTolerant FPGAs (UMC)

Module Specifications

C-Cell

•

Inverter (DB input) can be used to drive a

complement signal of any of the inputs to the C-cell.

Introduction

The C-cell is one of the two logic module types in the

RTSX-SU architecture. It is the combinatorial logic

resource in the device. The RTSX-SU architecture uses the

same C-cell configuration as found in the SX and SX-A

families.

A hardwired connection (direct connect) to the

associated R-cell with a signal propagation time of

less than 0.1 ns.

This layout of the C-cell enables the implementation of

over 4,000 functions of up to five bits. For example, two

C-cells can be used together to implement a four-input

XOR function in a single cell delay.

The C-cell features the following (Figure 2-11):

•

Eight-input MUX (data: D0-D3, select: A0, A1, B0,

B1). User signals can be routed to any one of these

inputs. C-cell inputs (A0, A1, B0, B1) can be tied to

one of the either the routed or quad clocks (CLKA/B

or QCLKA/B/C/D).

The C-cell configuration is handled automatically for the

user with Actel's extensive macro library (please see

Actel’s Antifuse Macro Library Guide for a complete

listing of available RTSX-SU macros).

A0 B0

A1 B1

Figure 2-11 • C-Cell

V_CC

GND

S, A or B

50% 50%

V_CC

50%

GND

t_PD

V_CC

50%

GND

t_PD

50%

t_PD

Figure 2-12 • C-Cell Timing Model and Waveforms

2-22

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Timing Characteristics

Table 2-24 • C-Cell

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 3.0V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max. Min. Max.

Parameter

Description

Units

C-cell Propagation Delays

t_PD

Internal Array Module

1.2

1.4

Note: For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDnor t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

R-Cell

•

Clock can be driven by any of the following (CKP

input selects clock polarity):

Introduction

The R-cell, the sequential logic resource of RTSX-SU

devices, is the second logic module type in the RTSX-SU

family architecture. The RTSX-SU R-cell is an SEU-

enhanced version of the SX and SX-A R-cell (Figure 2-13).

–

The high-performance, hardwired, fast clock

(HCLK)

–

One of the two routed clocks (CLKA/B)

The main features of the R-cell include the following:

One of the four quad clocks (QCLKA/B/C/D) in

the case of the RTSX72SU

•

Direct connection to the adjacent C-cell through

the hardwired connection DCIN. DCIN is driven by

the DCOUT of an adjacent C-cell via the Direct-

Connect routing resource, providing a connection

with less than 0.1 ns of routing delay.

–

User signals

•

S0, S1, PSETB, and CLRB can be driven by CLKA/B,

QCLKA/B/C/D (for the RTSX72SU) or user signals.

Routed Data Input and S1 can be driven by user

signals.

•

The R-cell can be used as a standalone flip-flop. It

can be driven by any other C-cell or I/O modules

through the regular routing structure (using DIN

as a routable data input). This gives the option of

using it as a 2:1 MUXed flip-flop as well.

As with the C-cell, the configuration of the R-cell to

perform various functions is handled automatically for

the user through Actel's extensive macro library (please

see Actel’s Antifuse Macro Library Guide for a complete

listing of available RTSX-SU macros).

•

Independent active-low asynchronous clear (CLRB).

Independent active-low asynchronous preset

(PSETB). If both CLRB and PSETB are Low, CLRB has

higher priority.

Routed

Data Input

PSETB

Direct

Connect

Input

HCLK

CLKA,

CLKB,

Internal Logic

CLRB

CKS

CKP

Figure 2-13 • R-Cell

v2.2

2-23

RTSX-SU RadTolerant FPGAs (UMC)

SEU-Hardened D Flip-Flop

In order to meet the stringent SEU requirements of a LET

threshold greater than 40MeV-cm²/gm, the internal

design of the R-cell was modified without changing the

functionality of the cell.

of each of the three latches is voted with the outputs of

the other two latches. If one of the three latches is struck

by an ion and starts to change state, the voting with the

other two latches prevents the change from feeding

back and permanently latching. Care was taken in the

layout to ensure that a single ion strike could not affect

more than one latch. Figure 2-16 shows a simplified

schematic of the test circuitry that has been added to

test the functionality of all the components of the flip-

flop. The inputs to each of the three latches are

independently controllable so the voting circuitry in the

asynchronous self-correcting feedback paths can be

tested exhaustively. This testing is performed on an

unprogrammed array during wafer sort, final test, and

post-burn-in test. This test circuitry cannot be used to

testtheflip-flops oncethedevicehasbeenprogrammed.

Figure 2-14 is a simplified representation of how the D

flip-flop in the R-cell is implemented in the SX-A

architecture. The flip-flop consists of a master and a slave

latch gated by opposite edges of the clock. Each latch is

constructed by feeding back the output to the input

stage. The potential problem in a space environment is

that either of the latches can change state when hit by a

particle with enough energy.

To achieve the SEU requirements, the D flip-flop in the

RTSX-SU R-cell is enhanced (Figure 2-15). Both the master

and slave "latches" are each implemented with three

latches. The asynchronous self-correcting feedback paths

CLK

Figure 2-14 • SX-A R-Cell Implementation of a D Flip-Flop

CLK

Voter

Gate

CLK

Figure 2-15 • RTSX-SU R-Cell Implementation of D Flip-Flop Using Voter Gate Logic

2-24

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Tst1

Tst2

Tst3

Voter

Gate

CLK

Test

Circuitry

Figure 2-16 • R-Cell Implementation – Test Circuitry

PRE

CLR

CLK

(Positive edge triggered)

t_HD

t_HPWH

t_RPWH

t_SUD

t_HP

CLK

t_RCO

t_HPWL

t_RPWL

t_PRESET

t_CLR

t_WASYN

CLR

PRESET

Figure 2-17 • R-Cell Timing Models and Waveforms

v2.2

2-25

RTSX-SU RadTolerant FPGAs (UMC)

Timing Characteristics

Table 2-25 • R-Cell

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 3.0V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max. Min. Max.

Parameter

Description

Units

R-Cell Propagation Delays

t_RCO

Sequential Clock-to-Q

1.0

0.8

1.1

0.8

0.0

2.8

0.7

1.2

1.0

1.3

1.0

0.0

3.3

0.8

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Hold Time

t_PRESET

t_SUD

t_HD

t_WASYN

t_RECASYN

t_HASYN

2-26

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Routing Specifications

Horizontal and Vertical Routing

Routing Resources

In addition to DirectConnect and FastConnect, the

architecture makes use of two globally-oriented routing

resources known as segmented routing and high-drive

routing. Actel’s segmented routing structure provides a

variety of track lengths for extremely fast routing

between SuperClusters. The exact combination of track

lengths and antifuses within each path is chosen by the

100-percent-automatic place-and-route software to

minimize signal propagation delays.

The routing structure found in RTSX-SU devices enables

any logic module to be connected to any other logic

module in the device while retaining high performance.

There are multiple paths and routing resources that can

be used to route one logic module to another, both

within a SuperCluster and elsewhere on the chip.

There are three primary types of routing within the

RTSX-SU architecture: DirectConnect, FastConnect, and

Vertical and Horizontal Routing.

Critical Nets and Typical Nets

DirectConnect

Propagation delays are expressed only for typical nets,

which are used for the initial design performance

evaluation. Critical net delays can then be applied to the

most time-critical paths. Critical nets are determined by

net property assignment prior to placement and routing.

Up to six percent of the nets in a design may be

designated as critical, while 90 percent of the nets in a

design are typical.

DirectConnects provide a high-speed connection between

an R-cell and its adjacent C-cell (Figure 1-3 and Figure 1-4

on page 1-4). This connection can be made from the Y

output of the C-cell to the DirectConnect input of the R-cell

by configuring of the S0 line of the R-cell. This provides a

connection that does not require an antifuse and has a

delay of less than 0.1 ns.

FastConnect

Long Tracks

For high-speed routing of logic signals, FastConnects can

be used to build a short distance connection using a

single antifuse (Figure 1-3 and Figure 1-4 on page 1-4).

FastConnects provide a maximum delay of 0.4 ns. The

outputs of each logic module connect directly to the

output tracks within a SuperCluster. Signals on the

output tracks can then be routed through a single

antifuse connection to drive the inputs of logic modules

either within one SuperCluster or in the SuperCluster

immediately below.

Some nets in the design use long tracks. Long tracks are

special routing resources that span multiple rows,

columns, or modules. Long tracks employ three and

sometimes five antifuse connections. This increases

capacitance and resistance results in longer net delays

for macros connected to long tracks. Typically up to six

percent of nets in a fully utilized device require long

tracks. Long tracks can cause a delay from 4.0 ns to

8.4 ns. This additional delay is represented statistically in

higher fanout routing delays in the "Timing

Characteristics" section on page 2-28.

v2.2

2-27

RTSX-SU RadTolerant FPGAs (UMC)

Timing Characteristics

Table 2-26 • RTSX32SU

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 3.0V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max. Min. Max.

Parameter Description

Units

Predicted Routing Delays

t_DC

FO=1 Routing Delay, DirectConnect

0.1

0.4

0.8

1.0

1.4

1.5

2.9

4.0

0.1

0.4

0.9

1.2

1.6

1.8

3.4

4.7

t_FC

FO=1 Routing Delay, FastConnect

FO=1 Routing Delay

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

Note: Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.

Table 2-27 • RTSX72SU

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 3.0V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed

Min. Max.

‘Std.’ Speed

Min. Max.

Parameter Description

Units

Predicted Routing Delays

t_DC

FO=1 Routing Delay, DirectConnect

0.1

0.4

0.9

1.2

1.8

1.9

3.7

5.1

0.1

0.4

1.0

1.4

2.0

2.3

4.3

6.0

t_FC

FO=1 Routing Delay, FastConnect

FO=1 Routing Delay

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO=2 Routing Delay

FO=3 Routing Delay

FO=4 Routing Delay

FO=8 Routing Delay

FO=12 Routing Delay

Note: Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.

2-28

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Global Resources

One of the most important aspects of any FPGA

architecture is its global resource or clock structure. The

RTSX-SU family provides flexible and easy-to-use global

resources without the limitations normally found in

other FPGA architectures.

the device (logically equivalent to the HCLK). CLK has the

added flexibility in that it can drive the S0 (Enable), S1,

PSETB, and CLRB inputs of R-cells as well as any of the

inputs of any C-cell in the device. This allows CLKs to be

used not only as clocks but also for other global signals

or high fanout nets. Both CLKs are available everywhere

on the chip.

The RTSX-SU architecture contains three types of global

resources, the HCLK (hardwired clock) and CLK (routed

clock) and in the RTSX72SU, QCLK (quadrant clock). Each

RTSX-SU device is provided with one HCLK and two CLKs.

The RTSX72SU has an additional four QCLKs.

If CLKA or CLKB pins are not used or sourced from

signals, then these pins must be set as Low or High on

the board. They must not be left floating (except in

RTSX72SU, where these clocks can be configured as

regular I/Os).

Hardwired Clock

The hardwired (HCLK) is a low-skew network that can

directly drive the clock inputs of all R-cells in the device

with no antifuse in the path. The HCLK is available

everywhere on the chip.

Quadrant Clocks

The RTSX72SU device provides four quadrant clocks

(QCLKA, QCLKB, QCLKC, QCLKD) to the user, which can

be sourced from external pins or from internal logic

signals within the device. Each of these clocks can

individually drive up to one full quadrant of the chip, or

they can be grouped together to drive multiple

quadrants (Figure 2-18). If QCLKs are not used as

quadrant clocks, they can behave as regular I/Os. See

Actel’s application note Using A54SX72A and RT54SX72S

Quadrant Clocks for more information.

Upon power-up of the RTSX-SU device, four clock pulses

must be detected on HCLK before the clock signal will be

propagated to registers in the device.

Routed Clocks

The routed clocks (CLKA and CLKB) are low-skew

networks that can drive the clock inputs of all R-cells in

4 QCLKBUFS

Quadrant 2

5:1

Quadrant 3

5:1

QCLKINT

(to array)

QCLKINT

(to array)

Quadrant 0

Quadrant 1

5:1

QCLKINT

(to array)

QCLKINT

(to array)

Figure 2-18 • RTSX-SU QCLK Structure

v2.2

2-29

RTSX-SU RadTolerant FPGAs (UMC)

Timing Characteristics

Table 2-28 • RTSX32SU at V_CCI= 3.0V

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 3.0V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Network

t_HCKH

t_HCKL

t_HPWH

t_HPWL

t_HCKSW

t_HP

Pad to R-Cell Input Low to High

Pad to R-Cell Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

3.9

4.6

2.1

2.5

1.6

1.9

Minimum Period

4.2

5.0

f_HMAX

Maximum Frequency

238

200

MHz

Routed Array Clock Networks

t_RCKH

t_RCHKL

t_RCKH

t_RCKL

Pad to R-cell Input High to Low (Light Load))

4.2

3.9

5.0

4.3

5.6

4.9

4.6

5.9

5.1

6.5

5.7

Pad to R-cell Input Low to High (Light Load))

Pad to R-cell Input Low to High (50% Load)

Pad to R-cell Input High to Low (50% Load)

Pad to R-cell Input Low to High (100% Load)

Pad to R-cell Input High to Low (100% Load)

Minimum Pulse Width High

t_RCKH

t_RCKL

t_RPWH

t_RPWL

t_RCKSW

t_RP

2.1

2.5

Minimum Pulse Width Low

Maximum Skew (Light Load)

2.8

3.3

Maximum Skew (50% Load)

Maximum Skew (100% Load)

Minimum Period

4.2

5.0

f_RMAX

Maximum Frequency

238

200

MHz

2-30

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Table 2-29 • RTSX32SU at V_CCI= 4.5V

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 4.5V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Network

t_HCKH

t_HCKL

t_HPWH

t_HPWL

t_HCKSW

t_HP

Pad to R-Cell Input Low to High

Pad to R-Cell Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

3.9

4.6

2.1

2.5

1.6

1.9

Minimum Period

4.2

5.0

f_HMAX

Maximum Frequency

238

200

MHz

Routed Array Clock Networks

t_RCKH

t_RCHKL

t_RCKH

t_RCKL

Pad to R-cell Input High to Low (Light Load))

3.9

3.7

4.7

4.1

5.3

4.7

4.6

4.4

5.6

4.9

6.2

5.5

Pad to R-cell Input Low to High (Light Load))

Pad to R-cell Input Low to High (50% Load)

Pad to R-cell Input High to Low (50% Load)

Pad to R-cell Input Low to High (100% Load)

Pad to R-cell Input High to Low (100% Load)

Minimum Pulse Width High

t_RCKH

t_RCKL

t_RPWH

t_RPWL

t_RCKSW

t_RP

2.1

2.5

Minimum Pulse Width Low

Maximum Skew (Light Load)

2.8

3.3

Maximum Skew (50% Load)

Maximum Skew (100% Load)

Minimum Period

4.2

5.0

f_RMAX

Maximum Frequency

238

200

MHz

v2.2

2-31

RTSX-SU RadTolerant FPGAs (UMC)

Table 2-30 • RTSX72SU at V_CCI= 3.0V

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 3.0V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Network

t_HCKH

t_HCKL

t_HPWH

t_HPWL

t_HCKSW

t_HP

Pad to R-cell Input Low to High

Pad to R-cell Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

3.2

3.5

3.8

4.1

2.7

3.2

2.7

3.1

Minimum Period

5.4

6.4

f_HMAX

Maximum Frequency

185

156

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RPWH

t_RPWL

t_RCKSW

t_RP

Pad to R-cell Input Low to High (Light Load))

5.7

6.5

5.7

6.5

5.7

6.5

6.7

7.7

6.7

7.7

6.7

7.7

Pad to R-cell Input High to Low (Light Load)

Pad to R-cell Input Low to High (50% Load)

Pad to R-cell Input High to Low (50% Load)

Pad to R-cell Input Low to High (100% Load)

Pad to R-cell Input High to Low (100% Load)

Minimum Pulse Width High

2.7

3.2

Minimum Pulse Width Low

Maximum Skew (Light Load)

5.1

4.9

6.0

5.8

Maximum Skew (50% Load)

Maximum Skew (100% Load)

Minimum Period

5.4

6.4

f_RMAX

Maximum Frequency

185

156

MHz

Quadrant Array Clock Networks

t_QCKH

t_QCKL

t_QCKH

t_QCKL

t_QCKH

t_QCKL

t_QPWH

t_QPWL

t_QCKSW

t_QP

Pad to R-cell Input Low to High (Light Load)

3.6

3.7

3.9

4.0

4.1

4.2

4.3

4.5

4.7

4.8

Pad to R-cell Input High to Low (Light Load)

Pad to R-cell Input Low to High (50% Load)

Pad to R-cell Input High to Low (50% Load)

Pad to R-cell Input Low to High (100% Load)

Pad to R-cell Input High to Low (100% Load)

Minimum Pulse Width High

2.7

3.2

Minimum Pulse Width Low

Maximum Skew (Light Load)

0.6

1.0

0.7

1.1

Maximum Skew (50% Load)

Maximum Skew (100% Load)

Minimum Period

5.4

6.4

f_QMAX

Maximum Frequency

185

156

MHz

2-32

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Table 2-31 • RTSX72SU at V_CCI= 4.5V

Worst-Case Military Conditions V_CCA= 2.25V, V_CCI= 4.5V, T_J= 125°C, Radiation Level = 0 krad (Si)

‘–1’ Speed ‘Std.’ Speed

Min. Max.

Parameter

Description

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Network

t_HCKH

t_HCKL

t_HPWH

t_HPWL

t_HCKSW

t_HP

Pad to R-cell Input Low to High

Pad to R-cell Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

4.1

4.8

2.8

3.3

3.2

3.7

Minimum Period

5.6

6.6

f_HMAX

Maximum Frequency

179

152

MHz

Routed Array Clock Networks

t_RCKHPad to R-cell Input Low to High (Light Load))

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

6.8

8.2

6.8

8.2

6.8

8.2

8.0

9.7

8.0

9.7

8.0

9.7

Pad to R-cell Input High to Low (Light Load)

Pad to R-cell Input Low to High (50% Load)

Pad to R-cell Input High to Low (50% Load)

Pad to R-cell Input Low to High (100% Load)

Pad to R-cell Input High to Low (100% Load)

Minimum Pulse Width High

t_RPWH

t_RPWL

t_RCKSW

t_QP

2.8

3.3

Minimum Pulse Width Low

Maximum Skew (Light Load)

7.0

6.8

8.2

8.0

Maximum Skew (50% Load)

Maximum Skew (100% Load)

Minimum Period

5.6

6.6

f_QMAX

Maximum Frequency

179

152

MHz

Quadrant Array Clock Networks

t_QCKH

t_QCKL

t_QCKH

t_QCKL

t_QCKH

t_QCKL

t_QPWH

t_QPWL

t_QCKSW

t_QP

Pad to R-cell Input Low to High (Light Load))

3.9

4.2

4.5

5.0

4.6

4.9

5.3

5.9

Pad to R-cell Input High to Low (Light Load)

Pad to R-cell Input Low to High (50% Load)

Pad to R-cell Input High to Low (50% Load)

Pad to R-cell Input Low to High (100% Load)

Pad to R-cell Input High to Low (100% Load)

Minimum Pulse Width High

2.8

3.3

Minimum Pulse Width Low

Maximum Skew (Light Load)

0.7

1.3

1.4

0.8

1.5

1.6

Maximum Skew (50% Load)

Maximum Skew (100% Load)

Minimum Period

5.6

6.6

f_QMAX

Maximum Frequency

179

152

MHz

v2.2

2-33

RTSX-SU RadTolerant FPGAs (UMC)

Global Resource Access Macros

The user can configure which global resource is used in

the design as well as how each global resource is driven

through the use of the following macros:

•

QCLKINT and QCLKINTI – noninverting and

inverting inputs used to drive quadrant routed

clocks (QCLKA/B/C/D) in the RTSX72SU from

internal logic

•

HCLKBUF – used to drive the hardwired clock

(HCLK) in both devices from an external pin

QCLKBIBUF and QCLUKBIBUFI – noninverting and

inverting inputs used to drive quadrant routed

•

CLKBUF and CLKBUFI – noninverting and inverting

inputs used to drive either routed clock (CLKA or

CLKB) in both devices from external pins

clocks

(QCLKA/B/C/D)

the

RTSX72SU

alternatively from either external pins or internal

logic

•

CLKINT and CLKINTI – noninverting and inverting

inputs used to drive either routed clock (CLKA or

CLKB) in both devices from internal logic

Figure 2-19, Figure 2-20, and Figure 2-21 illustrate the

various global-resource access macros.

QCLKBUF and QCLKBUFI – noninverting and

inverting inputs used to drive quadrant routed

clocks (QCLKA/B/C/D) in the RTSX72SU from

external pins

Constant Load

Clock Network

HCLKBUF

Figure 2-19 • Hardwired Clock Buffer

Clock Network

From Internal Logic

CLKBUF

CLKBUFI

CLKINT

CLKINTI

Figure 2-20 • Routed Clock Buffers in RTSX32SU

From Internal Logic

Clock Network

From Internal Logic

CLKBUF

CLKBUFI

CLKINT

CLKINTI

CLKBIBUF

CLKBIBUFI

QCLKBUF

QCLKBUFI

QCLKINT

QCLKINTI

QCLKBIBUF

QCLKBIBUFI

Figure 2-21 • Routed and Quadrant Clock Buffers in RTSX72SU

2-34

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Other Architectural Features

Flexible Mode

JTAG Interface

In flexible mode, TDI, TCK, and TDO may be employed as

either user I/Os or as JTAG input pins. The internal

resistors on the TMS and TDI pins are not present in

flexible JTAG mode.

All RTSX-SU devices are IEEE 1149.1 compliant and offer

superior diagnostic and testing capabilities by providing

Boundary Scan Testing (BST) and probing capabilities.

The BST function is controlled through special JTAG pins

(TMS, TDI, TCK, TDO, and TRST). The functionality of the

JTAG pins is defined by two available modes: dedicated

and flexible (Table 2-32). Note that TRST and TMS cannot

be employed as user I/Os in either mode.

To enter the flexible mode, users need to uncheck the

"Reserve JTAG" box in the "Device Selection Wizard" in

Designer software. TDI, TCK, and TDO pins may function

as user I/Os or BST pins in flexible mode. This

functionality is controlled by the BST TAP controller. The

TAP controller receives two control inputs: TMS and TCK.

Upon power-up, the TAP controller enters the Test-Logic-

Reset state. In this state, TDI, TCK, and TDO function as

user I/Os. The TDI, TCK, and TDO are transformed from

user I/Os into BST pins when a rising edge on TCK is

detected while TMS is at logic Low. To return to the Test-

Logic-Reset state, in the absences of TRST assertion, TMS

must be held High for at least five TCK cycles. An

external, 10 kΩ pull-up resistor tied to V_CCIshould be

placed on the TMS pin to pull it High by default.

Table 2-32 • Boundary Scan Pin Functionality

Dedicated Test Mode

Flexible Mode

TCK, TDI, TDO are dedicated

BST pins

TCK, TDI, TDO are flexible and

may be used as user I/Os

No need for pull-up resistor for Use a pull-up resistor of 10 kΩ

TMS

on TMS

Dedicated Mode

In dedicated mode, all JTAG pins are reserved for BST;

users cannot employ them as regular I/Os. An internal

pull-up resistor (on the order of 17 kΩ to 22 kΩ³) is

automatically enabled on both TMS and TDI pins, and

the TMS pin will function as defined in the IEEE 1149.1

(JTAG) specification.

Table 2-33 describes the different configurations of the

BST pins and their functionality in different modes.

Table 2-33 • JTAG Pin Configurations and Functions

Designer

"Reserve JTAG"

Selection

TAP Controller

State

To enter dedicated mode, users need to reserve the JTAG

pins in Actel’s Designer software during device selection.

To reserve the JTAG pins, users can check the "Reserve

JTAG" box in the "Device Selection Wizard" in Actel’s

Designer software (Figure 2-22).

Mode

Dedicated (JTAG)

Flexible (User I/O)

Flexible (JTAG)

Checked

Unchecked

Any

Test-Logic-Reset

Other

TRST Pin

The TRST pin functions as a dedicated boundary scan

reset pin. An internal pull-up resistor is permanently

enabled on the TRST pin. Additionally, the TRST pin must

be grounded for flight applications. This will prevent

Single-Event Upsets (SEU) in the TAP controller from

inadvertently placing the device into JTAG mode.

Figure 2-22 • Device Selection Wizard

Probing Capabilities

RTSX-SU devices also provide internal probing capability

that is accessed with the JTAG pins.

3. On a given device, the value of the internal pull-up resistor varies within 1 kΩ between the TMS and TDI pins.

v2.2

2-35

RTSX-SU RadTolerant FPGAs (UMC)

During probing, the Silicon Explorer II Diagnostic

Hardware is used to control the TDI, TCK, TMS, and TDO

pins to select the desired nets for debugging. The user

simply assigns the selected internal nets in the Silicon

Explorer II software to the PRA/PRB output pins for

observation. Probing functionality is activated when the

BST pins are in JTAG mode and the TRST pin is driven

High. If the TRST pin is held Low, the TAP controller will

remain in the Test-Logic-Reset state, so no probing can

be performed. Silicon Explorer II automatically places the

device into JTAG mode, but the user must drive the TRST

pin High or allow the internal pull-up resistor to pull

TRST High.

Silicon Explorer II Probe Interface

Actel’s Silicon Explorer II is an integrated hardware and

software solution that, in conjunction with Actel’s

Designer software, allows users to examine any of the

internal nets of the device while it is operating in a

prototype or a production system. The user can probe

two nodes at a time without changing the placement or

routing of the design and without using any additional

device resources. Highlighted nets in Designer’s

ChipEditor can be accessed using Silicon Explorer II in

order to observe their real time values.

Silicon Explorer II's noninvasive method does not alter

timing or loading effects, thus shortening the debug

cycle. In addition, Silicon Explorer II does not require

relayout or additional MUXes to bring signals out to

external pins, which is necessary when using

programmable logic devices from other suppliers. By

eliminating multiple place-and-route cycles, the integrity

of the design is maintained throughout the debug

process.

Silicon Explorer II connects to the host PC using a

standard serial port connector. Connections to the circuit

board are achieved using a nine-pin D-Sub connector

(Figure 1-5 on page 1-6). Once the design has been

placed-and-routed and the RTSX-SU device has been

programmed, Silicon Explorer II can be connected and

the Silicon Explorer software can be launched.

Silicon Explorer II comes with an additional optional PC-

hosted tool that emulates an 18-channel logic analyzer.

Two channels are used to monitor two internal nodes,

and 16 channels are available to probe external signals.

The software included with the tool provides the user

with an intuitive interface that allows for easy viewing

and editing of signal waveforms.

Both members of the RTSX-SU family have two external

pads: PRA and PRB. These can be used to bring out two

probe signals from the device. To disallow probing, the

SFUS security fuse in the silicon signature has to be

programmed. Table 2-34 shows the possible device

configuration options and their effects on probing.

Table 2-34 • Device Configuration Options for Probe Capability

Security Fuse

Programmed

JTAG Mode

Dedicated

Flexible

TRST

Low

High

–

PRA and PRB¹

User I/O²

TDI, TCK, and TDO¹

Probing Unavailable

User I/O²

Yes

User I/O²

Dedicated

Flexible

Probe Circuit Outputs

Probe Circuit Secured

Probe Circuit I/O

Probe Circuit Secured

–

Notes:

1. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports during probing. Since these pins are active during

probing, input signals will not pass through these pins and may cause contention.

2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by

the Designer software.

2-36

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

Security Fuses

Programming

Actel antifuse FPGAs, with FuseLock technology, offer

the highest level of design security available in a

programmable logic device. Since antifuse FPGAs are live

at power-up, there is no bitstream that can be

intercepted, and no bitstream or programming data is

ever downloaded to the device, thus making device

cloning impossible. In addition, special security fuses are

hidden throughout the fabric of the device and may be

programmed by the user to thwart attempts to reverse

engineer the device by attempting to exploit either the

programming or probing interfaces. Both invasive and

noninvasive attacks against an RTSX-SU device that

access or bypass these security fuses will destroy access to

the rest of the device. Refer to the Understanding Actel

Antifuse Device Security white paper for more

information.

Device programming is supported through the Silicon

Sculptor II, a single-site, robust and compact device-

programmer for the PC. Two Silicon Sculptor IIs can be

daisy-chained and controlled from a single PC host. With

standalone software for the PC, Silicon Sculptor II is

designed to allow concurrent programming of multiple

units from the same PC when daisy-chained.

Silicon Sculptor II programs devices independently to

achieve the fastest programming times possible. Each

fuse is verified by Silicon Sculptor II to ensure correct

programming. Furthermore, at the end of programming,

there are integrity tests that are run to ensure that

programming was completed properly. Not only does it

test programmed and nonprogrammed fuses, Silicon

Sculptor II also provides a self-test to extensively test its

own hardware.

Look for this symbol to ensure your valuable IP is secure

(Figure 2-23).

Programming an RTSX-SU device using Silicon Sculptor II

is similar to programming any other antifuse device. The

procedure is as follows:

1. Load the .AFM file

™

2. Select the device to be programmed

3. Begin programming

When the design is ready to go to production, Actel

offers volume programming services either through

distribution partners or via our In-House Programming

Center. For more details on programming the RTSX-SU

devices, please refer to the Silicon Sculptor II User’s

Guide.

Figure 2-23 • FuseLock Logo

To ensure maximum security in RTSX-SU devices, it is

recommended that the user program the device security

fuse (SFUS). When programmed, the Silicon Explorer II

testing probes are disabled to prevent internal probing,

and the programming interface is also disabled. All JTAG

public instructions are still accessible by the user. For

more information, refer to Actel’s Implementation of

Security in Actel Antifuse FPGAs application note.

v2.2

2-37

RTSX-SU RadTolerant FPGAs (UMC)

Package Pin Assignments

84-Pin CQFP

Pin 1 indicator

may be in a different

shape for different

devices.

Figure 3-1 • 84-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

v2.2

3-1

RTSX-SU RadTolerant FPGAs (UMC)

84-Pin CQFP

RTSX32SU Function

Pin Number

RTSX32SU Function

Pin Number

I/O

TMS

I/O

V_CCA

V_CCI

GND

I/O

V_CCI

GND

I/O

TRST

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

I/O

V_CCA

GND

I/O

GND

V_CCI

I/O

V_CCI

GND

I/O

CLKA

CLKB

PRA, I/O

I/O

PRB, I/O

HCLK

I/O

V_CCA

GND

I/O

GND

V_CCA

I/O

TDO, I/O

I/O

TCK, I/O

TDI, I/O

I/O

3-2

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

208-Pin CQFP

156

155

154

153

Pin 1

Ceramic

Tie Bar

208-Pin CQFP

108

107

106

105

Figure 3-2 • 208-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

v2.2

3-3

RTSX-SU RadTolerant FPGAs (UMC)

208-Pin CQFP

RTSX32SU

RTSX72SU

Function

RTSX32SU

Function

RTSX72SU

Function

Pin Number

Function

GND

TDI, I/O

I/O

Pin Number

GND

TDI, I/O

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

GND

V_CCA

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

TRST

I/O

TRST

I/O

Note: Pin 65 is a No Connect (NC) on Commercial A54SX32S-

PQ208.

3-4

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

208-Pin CQFP

RTSX32SU

Function

RTSX72SU

Function

RTSX32SU

Function

RTSX72SU

Function

Pin Number

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

I/O

QCLKA, I/O

I/O

PRB, I/O

GND

V_CCA

GND

PRB, I/O

GND

V_CCA

GND

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

GND

V_CCA

I/O

HCLK

I/O

HCLK

V_CCI

QCLKB, I/O

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

V_CCI

I/O

V_CCI

I/O

100

101

102

103

104

105

106

107

108

I/O

TDO, I/O

I/O

TDO, I/O

I/O

GND

I/O

GND

I/O

Note: Pin 65 is a No Connect (NC) on Commercial A54SX32S-

PQ208.

v2.2

3-5

RTSX-SU RadTolerant FPGAs (UMC)

208-Pin CQFP

RTSX32SU

RTSX72SU

Function

RTSX32SU

Function

RTSX72SU

Function

Pin Number

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Function

V_CCA

GND

I/O

Pin Number

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

V_CCA

GND

I/O

CLKB

CLKB, I/O

GND

V_CCA

GND

PRA, I/O

I/O

GND

V_CCA

GND

PRA, I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

QCLKC, I/O

I/O

GND

I/O

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

TCK, I/O

I/O

Note: Pin 65 is a No Connect (NC) on Commercial A54SX32S-

PQ208.

I/O

QCLKD, I/O

I/O

CLKA

CLKA, I/O

Note: Pin 65 is a No Connect (NC) on Commercial A54SX32S-

PQ208.

3-6

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CQFP

192

191

190

189

Pin 1

Ceramic

Tie Bar

256-Pin CQFP

132

131

130

129

Figure 3-3 • 256-Pin CQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

v2.2

3-7

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CQFP

RTSX32SU

RTSX72SU

Function

RTSX32SU

Function

RTSX72SU

Function

Pin Number

Function

GND

TDI, I/O

I/O

Pin Number

GND

TDI, I/O

I/O

V_CCA

I/O

GND

I/O

V_CCA

V_CCI

I/O

GND

I/O

GND

I/O

V_CCI

I/O

TMS

I/O

TMS

I/O

V_CCI

I/O

V_CCI

GND

V_CCA

GND

I/O

V_CCI

GND

V_CCA

GND

I/O

TRST

I/O

TRST

I/O

V_CCA

GND

I/O

3-8

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CQFP

RTSX32SU

Function

RTSX72SU

Function

RTSX32SU

Function

RTSX72SU

Function

Pin Number

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

I/O

V_CCI

I/O

QCLKA, I/O

PRB, I/O

GND

V_CCI

GND

V_CCA

I/O

TDO, I/O

I/O

TDO, I/O

I/O

PRB, I/O

GND

V_CCI

GND

V_CCA

I/O

GND

I/O

GND

I/O

HCLK

I/O

HCLK

I/O

QCLKB, I/O

I/O

100

101

102

103

104

105

106

107

108

109

110

111

I/O

V_CCA

I/O

V_CCA

V_CCI

GND

V_CCA

I/O

GND

I/O

GND

I/O

v2.2

3-9

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CQFP

RTSX32SU

Function

RTSX72SU

Function

RTSX32SU

Function

RTSX72SU

Function

Pin Number

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

Pin Number

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

I/O

GND

I/O

GND

I/O

GND

V_CCI

I/O

GND

V_CCI

V_CCA

I/O

V_CCI

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

QCLKD, I/O

CLKA, I/O

CLKB, I/O

V_CCI

GND

I/O

CLKA

CLKB

V_CCI

GND

I/O

V_CCI

I/O

3-10

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CQFP

RTSX32SU

Function

RTSX72SU

Function

Pin Number

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

GND

PRA, I/O

I/O

GND

PRA, I/O

I/O

V_CCA

I/O

QCLKC, I/O

I/O

GND

I/O

GND

I/O

V_CCI

I/O

TCK, I/O

v2.2

3-11

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG

Top View

A1 Index Corner

256

193

192

Extenral Wire-Bond Number

129

128

Bottom View

10 11 12 13 14 15 16

Figure 3-4 • 256-Pin CCLG

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

3-12

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG*

External Wire-

Bond Number

RTSX32SU

Function

External Wire-

Bond Number

RTSX32SU

Function

Pin Number

GND

TCK, I/O

I/O

252

249

245

239

230

226

218

210

201

197

211

178

195

GND

I/O

256

255

251

243

238

232

228

227

221

216

209

203

200

I/O

CLKA

I/O

C10

C11

C12

C13

C14

C15

C16

CLKB

I/O

A10

A11

A12

A13

A14

A15

A16

I/O

GND

I/O

242

I/O

GND

I/O

254

253

248

241

234

250

244

237

229

217

208

206

199

205

173

190

188

I/O

PRA, I/O

I/O

V_CCA

I/O

D10

D11

D12

D13

D14

D15

D16

I/O

222

220

212

207

202

198

I/O

B10

B11

B12

B13

B14

B15

B16

I/O

GND

I/O

196

I/O

TDI,I/O

I/O

Note: *This table was sorted by the pin number.

v2.2

3-13

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG*

External Wire-

Bond Number

RTSX32SU

Function

External Wire-

Bond Number

RTSX32SU

Function

Pin Number

I/O

GND

V_CCI

I/O

240

233

231

223

219

213

167

183

189

187

186

I/O

G10

G11

G12

G13

G14

G15

G16

I/O

E10

E11

E12

E13

E14

E15

E16

I/O

169

180

176

179

175

I/O

GND

I/O

V_CCA

I/O

160

V_CCA

TRST

I/O

TMS

I/O

108

V_CCI

GND

V_CCI

I/O

V_CCI

I/O

107

118

128

165

170

168

166

174

H10

H11

H12

H13

H14

H15

H16

F10

F11

F12

F13

F14

F15

F16

157

I/O

V_CCA

I/O

177

185

184

181

I/O

139

127

140

V_CCI

GND

I/O

V_CCI

Note: *This table was sorted by the pin number.

3-14

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG*

External Wire-

Bond Number

RTSX32SU

Function

External Wire-

Bond Number

RTSX32SU

Function

Pin Number

L11

L12

L13

L14

L15

L16

151

161

150

159

163

164

162

158

GND

V_CCI

I/O

103

149

146

148

145

147

I/O

PRB, I/O

I/O

J10

J11

J12

J13

J14

J15

J16

I/O

V_CCA

I/O

171

172

182

192

204

191

153

155

156

152

154

V_CCI

GND

V_CCI

I/O

101

105

114

111

141

142

137

144

M10

M11

M12

M13

M14

M15

M16

K10

K11

K12

K13

K14

K15

K16

I/O

194

214

235

246

V_CCI

109

117

112

124

N10

N11

N12

L10

Note: *This table was sorted by the pin number.

v2.2

3-15

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG*

External Wire-

RTSX32SU

Function

External Wire-

Bond Number

RTSX32SU

Function

Pin Number

N13

N14

N15

N16

Bond Number

121

133

135

136

Pin Number

I/O

R15

R16

225

193

236

GND

I/O

138

GND

I/O

224

102

110

116

122

125

129

247

V_CCA

I/O

T10

T11

T12

T13

T14

T15

T16

104

113

119

123

143

131

132

134

I/O

P10

P11

P12

P13

P14

P15

P16

I/O

V_CCA

I/O

TDO,I/O

GND

I/O

Note: *This table was sorted by the pin number.

I/O

215

GND

I/O

100

106

115

120

126

130

HCLK

I/O

R10

R11

R12

R13

R14

I/O

Note: *This table was sorted by the pin number.

3-16

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG*

External Wire-

Bond Number

RTSX32SU

Function

External Wire-

Bond Number

RTSX32SU

Function

Pin Number

A15

Pin Number

GND

V_CCI

TDI,I/O

I/O

TRST

I/O

GND

V_CCI

I/O

A16

I/O

GND

TMS

I/O

V_CCA

I/O

F10

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

B15

I/O

GND

V_CCI

GND

I/O

GND

V_CCA

I/O

Note: *This table was sorted by the wire-bond number.

v2.2

3-17

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG*

External Wire-

Bond Number

RTSX32SU

Function

External Wire-

Bond Number

RTSX32SU

Function

Pin Number

L11

100

101

102

I/O

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

I/O

M10

R10

I/O

GND

V_CCI

I/O

T11

M12

N11

P10

M11

R11

T12

N10

H10

P11

R12

N13

T13

P12

N12

T14

R13

I/O

G10

GND

I/O

GND

I/O

GND

V_CCI

I/O

G11

I/O

GND

V_CCI

TDO,I/O

I/O

H11

T15

R14

P14

P15

N14

P16

N15

N16

PRB, I/O

GND

V_CCA

I/O

F12

I/O

HCLK

I/O

T10

I/O

Note: *This table was sorted by the wire-bond number.

3-18

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG*

External Wire-

Bond Number

RTSX32SU

Function

External Wire-

Bond Number

RTSX32SU

Function

Pin Number

M15

Pin Number

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

I/O

GND

V_CCI

GND

I/O

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

V_CCI

GND

I/O

D14

H16

G16

G14

F13

I/O

M13

M14

P13

M16

L15

L13

L16

L14

L12

J11

I/O

V_CCA

I/O

C15

G15

G13

F16

I/O

V_CCA

GND

I/O

GND

I/O

E13

F15

V_CCI

GND

I/O

F14

I/O

K15

K12

K16

K13

K14

F11

J16

E16

E15

D16

E14

D15

K11

I/O

V_CCI

GND

V_CCI

I/O

J12

I/O

R16

V_CCA

GND

I/O

J10

C16

B16

C13

B14

D12

A14

C12

B13

A13

K10

J15

I/O

J13

I/O

J14

I/O

H12

H15

E12

H14

G12

H13

I/O

GND

Note: *This table was sorted by the wire-bond number.

v2.2

3-19

RTSX-SU RadTolerant FPGAs (UMC)

256-Pin CCLG*

External Wire-

RTSX32SU

Function

External Wire-

Bond Number

RTSX32SU

Function

Pin Number

D13

D11

B12

D10

A12

C11

C14

B11

E11

Bond Number

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

Pin Number

I/O

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

I/O

L10

T16

I/O

V_CCI

GND

I/O

V_CCI

GND

I/O

A11

I/O

C10

E10

B10

A10

I/O

TCK, I/O

I/O

Note: *This table was sorted by the wire-bond number.

V_CCA

GND

CLKA

CLKB

I/O

R15

PRA, I/O

I/O

V_CCI

GND

I/O

Note: *This table was sorted by the wire-bond number.

3-20

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

624-Pin CCGA

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Figure 3-5 • 624-Pin CCGA (Bottom View)

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/default.aspx.

v2.2

3-21

RTSX-SU RadTolerant FPGAs (UMC)

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

Pin Number

Function

Pin Number

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

Function

Pin Number

C22

C23

C24

C25

Function

I/O

GND

V_CCI

CLKB, I/O

I/O

GND

TDI, I/O

GND

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

I/O

GND

V_CCI

GND

I/O

GND

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

I/O

V_CCI

GND

I/O

QCLKD, I/O

I/O

GND

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

I/O

QCLKC, I/O

I/O

GND

V_CCI

GND

I/O

V_CCI

GND

I/O

PRA, I/O

CLKA, I/O

I/O

V_CCI

GND

I/O

B10

B11

I/O

TCK, I/O

I/O

3-22

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

Pin Number

Function

Pin Number

Function

Pin Number

Function

I/O

F17

I/O

F18

I/O

F19

I/O

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

I/O

F20

I/O

F21

I/O

V_CCA

GND

I/O

F22

I/O

F23

I/O

V_CCI

I/O

F24

I/O

F25

I/O

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

I/O

TMS

I/O

V_CCI

GND

V_CCI

I/O

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

I/O

V_CCI

I/O

GND

I/O

F10

F11

F12

F13

F14

F15

F16

I/O

V_CCI

I/O

GND

I/O

J10

J11

I/O

v2.2

3-23

RTSX-SU RadTolerant FPGAs (UMC)

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

Pin Number

Function

Pin Number

K22

K23

K24

K25

Function

Pin Number

Function

J12

I/O

J13

I/O

J14

I/O

J15

I/O

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

GND

J16

I/O

J17

V_CCI

I/O

J18

I/O

J19

I/O

J20

I/O

J21

V_CCA

I/O

J22

J23

I/O

J24

I/O

J25

I/O

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

GND

I/O

V_CCA

I/O

V_CCA

I/O

N10

N11

N12

N13

N14

N15

N16

GND

I/O

GND

I/O

3-24

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

Pin Number

N17

N18

N19

N20

N21

N22

N23

N24

N25

Function

Pin Number

Function

Pin Number

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

Function

GND

I/O

V_CCA

I/O

TRST

I/O

V_CCA

I/O

GND

I/O

V_CCI

I/O

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

GND

I/O

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

GND

I/O

V_CCI

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

I/O

GND

I/O

V_CCI

I/O

T10

T11

GND

I/O

v2.2

3-25

RTSX-SU RadTolerant FPGAs (UMC)

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

Pin Number

U22

U23

U24

U25

Function

Pin Number

Function

VCCI

I/O

Pin Number

Function

I/O

Y17

I/O

Y18

I/O

Y19

I/O

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

Y20

I/O

Y21

I/O

Y22

I/O

Y23

I/O

V_CCA

I/O

Y24

GND

I/O

Y25

I/O

AA1

GND

I/O

GND

V_CCI

AA2

AA3

V_CCI

I/O

AA4

I/O

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

AA5

GND

I/O

AA6

I/O

AA7

I/O

AA8

I/O

AA9

I/O

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AB1

I/O

V_CCI

I/O

V_CCA

GND

I/O

V_CCA

I/O

Y10

Y11

Y12

Y13

Y14

Y15

Y16

I/O

GND

I/O

GND

I/O

V_CCI

I/O

GND

I/O

GND

I/O

3-26

v2.2

RTSX-SU RadTolerant FPGAs (UMC)

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

624-Pin CCGA

RTSX72SU

Pin Number

Function

V_CCI

I/O

Pin Number

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AD1

Function

PRB, I/O

I/O

Pin Number

AD22

AD23

AD24

AD25

AE1

Function

GND

V_CCI

GND

AB2

AB3

AB4

GND

I/O

HCLK

I/O

AB5

AB6

I/O

AB7

I/O

AE2

AB8

I/O

AE3

AB9

I/O

AE4

GND

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AC1

I/O

AE5

I/O

AE6

I/O

QCLKA, I/O

I/O

AE7

I/O

GND

I/O

AE8

I/O

AE9

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

I/O

AD2

GND

V_CCI

GND

I/O

AD3

I/O

AD4

QCLKB, I/O

I/O

AD5

TDO, I/O

V_CCI

I/O

AD6

I/O

AD7

I/O

AD8

I/O

V_CCI

AD9

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

V_CCI

I/O

AC2

I/O

GND

AC3

GND

I/O

AC4

I/O

AC5

I/O

AC6

I/O

GND

I/O

AC7

I/O

AC8

I/O

AC9

I/O

AC10

AC11

I/O

v2.2

3-27

RTSX-SU RadTolerant FPGAs (UMC)

Datasheet Information

List of Changes

The following table lists critical changes that were made to the current version of the document.

Previous version Changes in current version (v2.2)

Page

2-11

2-14

1-6

2-11

2-14

2-7

2-8

v2.1

The notes in Table 2-10 were updated.

The notes in Table 2-13 were updated.

v2.0

Figure 1-5 was updated and a note was added.

Table 2-10 was updated to include Notes 2 and 3.

Table 2-13 was updated to include Notes 1 and 2.

Footnote 1 in the "Pin Descriptions" section was updated.

Footnote 2 in the "Pin Descriptions" section was updated.

Table 1 was updated to include the CQ84.

Advanced v0.3

The "Ceramic Device Resources" table was updated to include CQ84.

The "Temperature Grade and Application Offering" table was updated to include CQ84.

Table 2-3 was updated. The 0.25V/ms was changed to 0.25V/μs and 0.025V/ms was changed to

0.025V/μs.

2-1

Table 2-7 was updated to include the CQ84.

2-4

2-12

Table 2-11 was updated to include Note 2.

Table 2-12 was updated to include Note 2.

2-13

Table 2-13 was updated to include I_ILand I_IH.

2-35

Table 2-14 was updated to include Note 2.

2-15

Table 2-15 was updated to include Note 2.

2-15

Table 2-18 was updated to include Note 2.

2-18

Table 2-19 was updated to include Note 2.

2-18

Table 2-22 was updated to include Note 2.

2-21

Table 2-23 was updated to include Note 2.

2-21

The headings in Table 2-32 were updated to say Dedicated Test Mode and Flexible Mode.

The "84-Pin CQFP" section, which includes the package figure and the pin table, is new.

2-4

3-1

Advanced v0.2

Advanced v0.1

In Table 2-13, the I_OH= –20μA and I_OL

20μA.

2-14

Table 2-8 was updated.

2-5

Table 2-11 and Table 2-12 were updated.

Table 2-14 and Table 2-15 were updated.

Table 2-18 and Table 2-19 were updated.

Table 2-22 and Table 2-23 were updated.

Table 2-25 was updated.

2-12, 2-13

2-15, 2-15

2-18, 2-18

2-21, 2-21

2-26

Table 2-26 and Table 2-27 were updated.

Table 2-28 and Table 2-29 were updated.

Table 2-30 and Table 2-31 were updated.

2-28, 2-28

2-30, 2-31

2-32, 2-33

v2.2

4-1

RTSX-SU RadTolerant FPGAs (UMC)

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet

Supplement." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advanced or production) containing general product

information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

Export Administration Regulations (EAR) or International Traffic in

Arms Regulations (ITAR)

The product described in this datasheet could be subject to either the Export Administration Regulations (EAR) or in

some cases the International Traffic in Arms Regulations (ITAR). They could require an approved export license prior to

export from the United States. An export includes release of product or disclosure of technology to a foreign national

inside or outside the United States.

4-2

v2.2

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

http://www.actel.com

Actel Corporation

Actel Europe Ltd.

Actel Japan

www.jp.actel.com

Actel Hong Kong

www.actel.com.cn

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Phone +852 2185 6460

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51700053-5/3.06

RTSX72SU-1CC256B [ACTEL]

相关型号：

RTSX72SU-1CC256E

RTSX72SU-1CC256M

RTSX72SU-1CG256B

RTSX72SU-1CG256E

RTSX72SU-1CG256M

RTSX72SU-1CQ256B

RTSX72SU-1CQ256E

RTSX72SU-1CQ256M

RTSX72SU-CC256B

RTSX72SU-CC256E

RTSX72SU-CC256M

RTSX72SU-CG256B