ACT410_14_技术文档

ACT410

Rev 3, 27-Feb-14

ActivePSR^TMQuasi-Resonant PWM Controller

and overload conditions, it would enter auto restart

mode including cycle-by-cycle current limiting.

FEATURES

• Patented Primary Side Regulation

ACT410 is to achieve no overshoot and very short

rise time even with big capacitive load (4000µF)

with the built-in fast and soft start process, .

Technology

• Quasi-Resonant Operation

• Adjustable up to 120kHz Switching

The Quasi-Resonant (QR) operation mode can

effectively improve efficiency, reduce the EMI noise

and further reduce the components in input filter.

Frequency

• +/-5% Output Voltage Regulation

• Accurate OCP/OLP Protection

ACT410 is idea for application up to 36 Watt.

Figure 1:

• Integrated Output Cord Compensation

Simplified Application Circuit

• Integrated Line and Primary Inductance

Compensation

• Built-in Soft-Start Circuit

• Line Under-Voltage, Thermal, Output Over-

voltage, Output Short Protections

• Current Sense Resistor Short Protection

• Transformer Short Winding Protection

• Less than 100mW Standby Power

• Complies with Global Energy Efficiency and

CEC Average Efficiency Standards

• Tiny SOT23-6 Package

APPLICATIONS

• AC/DC Adaptors/Chargers for Smart Phones,

iPADs, ADSL, PDAs, E-books

• Adaptors for Portable Media Player, DSCs,

and Other

GENERAL DESCRIPTION

The ACT410 is a high performance peak current

mode PWM controller which applies ActivePSR^TM

and ActiveQR^TMtechnology. ACT410 achieves

accurate voltage regulation without the need of an

opto-coupler or reference device.

The ACT410 is designed to achieve less than

100mW Standby Power. By applying frequency fold

back and

ActiveQR^TMtechnology, ACT410

exceeds the latest ES2.0 efficiency standard.

ACT410 integrates comprehensive protection. In

case of over temperature, over voltage, short

winding, short current sense resistor, open loop

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ACT410

Rev 3, 27-Feb-14

ORDERING INFORMATION

TEMPERATURE

PART NUMBER

PACKING

METHOD

OPTION (DC

CORD %)

PACKAGE PINS

TOP MARK

RANGE

ACT410US-T

-40°C to 85°C

SOT23-6

6

TUBE & REEL

6

FRYH

PIN CONFIGURATION

SOT23-6

ACT410US

PIN DESCRIPTIONS

NAME

CS

DESCRIPTION

Current Sense Pin. Connect an external resistor (R_CS) between this pin and ground to set peak

current limit for the primary switch.

1

2

3

4

5

6

GND

Ground.

GATE Gate Drive. Gate driver for the external MOSFET transistor.

VDD

FB

Power Supply. This pin provides bias power for the IC during startup and steady state operation.

Feedback Pin. Connect this pin to a resistor divider network from the auxiliary winding.

COMP Compensation Pin.

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ACT410

Rev 3, 27-Feb-14

ABSOLUTE MAXIMUM RATINGS^c

PARAMETER

FB, CS, COMP to GND

VALUE

-0.3 to + 6

-0.3 to + 22

0.45

UNIT

V

VDD, GATE to GND

Maximum Power Dissipation (SOT23-6)

W

Operating Junction Temperature

-40 to 150

˚C

Junction to Ambient Thermal Resistance (θ_JA)

Operating Junction Temperature

Storage Temperature

220

˚C/W

˚C

-40 to 150

-55 to 150

300

˚C

Lead Temperature (Soldering, 10 sec)

˚C

c: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods.

ELECTRICAL CHARACTERISTICS

V_DD= 15V, L_M= 0.37mH, R_CS= 1Ω, V_OUT= 5V, N_P= 76, N_S= 7, N_A= 20, T_A= 25°C, unless otherwise specified,5V2A application.)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN TYP MAX UNIT

Supply

VDD Turn-On Voltage

V_DDON

V_DDOFF

V_DDOVP

I_DDST

V_DDRising from 0V

11.11 12.35 13.58

V

VDD Turn-Off Voltage

V_DDFalling after Turn-on

V_DDRising from 0V

6.1

6.8

20.5

5

7.5

22.55

10

VDD Over Voltage Protection

Start Up Supply Current

18.45

V

V_DD= 11V, before VDD Turn-on

µA

V_DD= 12V, after VDD Turn-on (no

switching)

IDD Supply Current

I_DD

0.55

0.25

1

mA

V_DD= 12V, after VDD Turn-on,

fault = 1

IDD Supply Current at Fault Mode

Feedback

Effective FB Reference Voltage

V_FBREF

T_{FB_BLK}

2.23

0.38

1.1

2.25

0.45

1.3

2.28

0.52

1.5

V

Light load

µs

µA

FB Sampling Blanking Time

Heavy Load

FB sampling

0.5

0.65

0.25

0.75

0.29

1

Time needed for FB Sampling

(After blanking)

T_{FB_SAMP}

I_BVFB

CC and Knee point detecting

V_FB= 3V

0.22

FB Leakage Current

Current Limit

CS Current Limit Threshold

V_CSLIM

V_CSMIN

0.99

1.00

300

1.01

V

CS Minimum Current Limits

Threshold

mV

CS to GATE Propagation Delay

60

ns

Light Load

150

636

Leading Edge Blanking Time

T_CSBLANK

Heavy Load

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ACT410

Rev 3, 27-Feb-14

ELECTRICAL CHARACTERISTICS CONT’D

V_DD= 15V, L_M= 0.37mH, R_CS= 1ꢀ, V_OUT= 5V, N_P= 76, N_S= 7, N_A= 20, T_A= 25°C, unless otherwise specified,5V2A application.)

PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX UNIT

RCORD

Output Cable Resistance

Compensation

ACT410

DV_COMP

6

%

GATE DRIVE

Gate Rise Time

T_RISE

T_FALL

R_ONLO

R_ONHI

VDD = 10V, CL = 1nF

I_SINK= 30mA

150

90

250

ns

ꢀ

Gate Falling Time

Gate Low Level ON-Resistance

Gate High Level ON-Resistance

10

I_SOURCE= 30mA

31

ꢀ

GATE = 18V, before VDD

turn-on

Gate Leakage Current

1

µA

COMPENSATION

Inside Compensate Resistor

Output Sink Current

R_COMP

ACT410

0

kꢀ

I_{COMP_SINK}V_FB= 3V, V_COMP= 2V

15

40

µA

I_{COMP SOUR}

_

Output Source Current

V_FB= 1.5V, V_COMP= 2V

40

µA

CE

Transconductance of Error Amplifier

Maximum Output Voltage

Minimum Output Voltage

CS to COMP Gain

Gm

71

3.5

0.4

2

µA/V

V

V_COMPMAX

V_COMPMIN

V_FB= 1.5V

V_FB= 3V

V

V/V

µA

Pre-Amp Gain

1

COMP Leakage Current

OSCILLATOR

COMP = 2.5V

1

Maximum Switching

f_MAX

108

65

120

75

132

kHz

%

Maximum Duty Cycle

D_MAX

Minimum Switching Frequency

f_MIN

1164

Hz

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ACT410

Rev 3, 27-Feb-14

ELECTRICAL CHARACTERISTICS CONT’D

(V_DD= 15V, L_M= 0.37mH, R_CS= 1ꢀ, V_OUT= 5V, N_P= 76, N_S= 7, N_A= 20, T_A= 25°C, unless otherwise specified,5V2A application.)

PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX UNIT

Protection

CS Short Waiting Time

CS Short Detection Threshold

CS Open Threshold Voltage

Abnormal OCP Blanking Time

Inductance Short CS Threshold Voltage

Thermal Shutdown Temperature

Thermal Hysteresis

2

2.25

0.1

1.75

190

1.75

135

20

3

µs

V

0.15

V

ns

V

˚C

mA

µA

mA

V

Line UVLO

I_FBUVLO

0.2

20

Line UVLO Hysteresis

Line OVP

I_FBOVP

2.4

3

VFB Over Voltage Protection

Valley Detection

Valley Detection Time Window

V_COMP= 0.45V

3.3

µs

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ACT410

Rev 3, 27-Feb-14

FUNCTIONAL BLOCK DIAGRAM

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ACT410

Rev 3, 27-Feb-14

FUNCTIONAL DESCRIPTION

ACT410 is a high performance peak current mode

low-voltage PWM controller IC. The controller

includes the most advance features that are

required in the adaptor applications up to 36 Watt.

Unique fast startup, frequency fold back, QR

switching technique, accurate OLP, low standby

mode operation, external compensation adjustment,

short winding protection, OCP, OTP, OVP and

UVLO are included in the controller.

transformer secondary and auxiliary turns, and V_D

is the rectifier diode forward drop voltage at

approximately 0.1A bias.

Constant Current (CC) Mode Operation

When the secondary output current reaches a level

set by the internal current limiting circuit, the

ACT410 enters current limit condition and causes

the secondary output voltage to drop. As the output

voltage decreases, so does the flyback voltage in a

proportional manner. An internal current shaping

circuitry adjusts the switching frequency based on

the flyback voltage so that the transferred power

remains proportional to the output voltage, resulting

in a constant secondary side output current profile.

The energy transferred to the output during each

switching cycle is ½(LP × ILIM^2) × η, where LP is

the transformer primary inductance, ILIM is the

primary peak current, and η is the conversion

efficiency. From this formula, the constant output

current can be derived:

Startup

Startup current of ACT410 is designed to be very

low so that VDD could be charged to VDDON

threshold level and device starts up quickly. A large

value startup resistor can therefore be used to

minimize the power loss yet reliable startup in

application. For a typical AC/DC adaptor with

universal input range design, two 1Mꢀ, 1/8 W

startup resistors could be used together with a VDD

capacitor(4.7uF) to provide a fast startup and yet

low power dissipation design solution.

During startup period, the IC begins to operate with

minimum Ippk to minimize the switching stresses

for the main switch, output diode and transformers.

And then, the IC operates at maximum power

output to achieve fast rise time. After this, V_OUT

reaches about 90% V_OUT, the IC operates with a

‘soft-landing’ mode (decrease Ippk) to avoid output

overshoot.

1

2

V_CS

R_CS

η × f_SW

V_OUTCV

I_OUTCC

=

× L_p× (

)²× (

)

(2)

where f_SWis the switching frequency and V_OUTCVis

the nominal secondary output voltage. The constant

current operation typically extends down to lower

than 40% of nominal output voltage regulation.

Standby (No Load) Mode

Constant Voltage (CV) Mode Operation

In no load standby mode, the ACT410 oscillator

In constant voltage operation, the ACT410 senses

the output voltage at FB pin through a resistor

divider network R5 and R6 in Figure 2. The signal

at FB pin is pre-amplified against the internal

reference voltage, and the secondary side output

voltage is extracted based on Active-Semi's

proprietary filter architecture.

frequency is further reduced to a minimum

frequency while the current pulse is reduced to a

minimum level to minimize standby power. The

actual minimum switching frequency is

programmable with an output preload resistor.

Loop Compensation

The ACT410 allows external loop compensation by

connecting a capacitor and a resistor to extend its

applications, especially with different V_OUTin a wide

output power range.

This error signal is then amplified by the internal

error amplifier. When the secondary output voltage

is above regulation, the error amplifier output

voltage decreases to reduce the switch current.

When the secondary output voltage is below

regulation, the error amplifier output voltage

increases to ramp up the switch current to bring the

secondary output back to regulation. The output

regulation voltage is determined by the following

relationship:

Primary Inductance Compensation

The ACT410 integrates

a

built-in primary

inductance compensation circuit to maintain

constant OLP despite variations in transformer

manufacturing. The compensated ranges is +/-7%.

R_FB1

R_{FB 2}

N_S

N_A

V_OUTCV= 2.20V × (1 +

) ×

-V_D

(1)

Primary Inductor Current Limit

Compensation

The ACT410 integrates a primary inductor peak

where R_FB1(R5) and R_FB2(R6) are top and bottom

feedback resistor, N_Sand N_Aare numbers of

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ACT410

Rev 3, 27-Feb-14

FUNCTIONAL DESCRIPTION CONT’D

current limit compensation circuit to achieve

constant OLP over wide line and wide load range.

Protection Features

The ACT410 provides full protection functions. The

following table summarizes all protection functions.

Output Cable Resistance Compensation

The ACT410 provides internal programmable

output cable resistance compensation during

constant voltage regulation, monotonically adding

an output voltage correction up to predetermined

percentage at full power.

PROTECTION

FUNCTIONS

FAILURE

CONDITION

PROTECTION

MODE

V_DDOver Voltage

VFB Over Voltage

Over Temperature

V_DD> 20.5V

(4 duty cycle)

Auto Restart

V_FB> 3V

(4 duty cycle)

Auto Restart

The feature allows better output voltage accuracy

by compensating for the output voltage drop due to

the output cable resistance.

T > 135˚C

Auto Restart

Short Winding/

Short Diode

V_CS> 1.75V

Frequency Fold-back

When the load drops to 75% of full load level,

ACT410 starts to decrease the switching frequency,

which is proportional to the load current ,to improve

the efficiency of the converter as show in Functional

Block Diagram.

Over Load

IPK = I_LIMIT

Auto Restart

Output Short

Circuit

V_FB< 0.56V

Open Loop

No switching for

4 cycle

Auto Restart

This enables the application to meet all latest green

energy standards. The actual minimum switching

frequency is programmable with a small dummy

load (while still meeting standby power).

V_CCUnder

Voltage

V_CC< 6.8V

Auto-Restart Operation

Valley Switching

ACT410 will enter auto-restart mode when a fault is

identified. There is a startup phase in the auto-

restart mode. After this startup phase the conditions

are checked whether the failure is still present.

Normal operation proceeds once the failure mode is

removed. Otherwise, new startup phase will be

initiated again.

ACT410 employed valley switching from medium

load to heavy load to reduce switching loss and

EMI. After the switch is turned off, the ringing

voltage from the auxiliary winding is applied to the

VFB pin through feedback network R5, R6.

Internally, the VFB pin is connected to an zero-

crossing detector to generate the switch turn on

signal when the conditions are met. In light load, the

frequency fold back scheme starts to take control to

determine the switch turn on signal, so thus the

switching frequency.

To reduce the power loss during fault mode, the

startup delay control is implemented. The startup

delay time increases over lines.

Over Load Protection (OLP)

Figure 1:

When the secondary output current reaches a level

set by the internal current limiting circuit, the

ACT410 enters current limit condition and causes

the secondary output voltage to drop, the IC enters

fault mode and enter auto restart mode.

Valley Switching at heavy load

Vdrain_gndMosfet

DCvoltage

ACT410 is able to achieve very accurate OLP

(constant I_OUT) independent of input lines and

primary inductor values.

Short Circuit Protection

When the secondary side output is short circuited,

the ACT410 enters hiccup mode operation. This

hiccup behavior continues until the short circuit is

removed.

t

Possible Valley turn on

T

Ton

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ACT410

Rev 3, 27-Feb-14

TYPICAL APPLICATION CONT’D

FB Over Voltage Protection

The ACT410 includes output over-voltage

protection circuitry, which shuts down the IC when

the output voltage is 40% above the normal

regulation voltage 4 consecutive switching cycles.

The ACT410 enters hiccup mode when an output

over voltage fault is detected.

VDD Over Voltage Protection

ACT410 can monitor the converter output voltage.

The voltage generated by the auxiliary winding

tracks converter’s output voltage through VDD,

which is in proportion to the turn ratio (V_OUT+V_DIODE

)

хN_A/N_S. When the V_OUTis abnormally higher than

design value for four consecutive cycles, IC will

enter the restart process. A counter is used to

reduce sensitivity to noise and prevent the auto

start unnecessary.

Open Loop Protection

ACT410 is able to protect itself from damage when

the control loop is open. The typical open loop

condition includes either VFB floating or RFB5

open.

Over Temperature Shutdown

The thermal shutdown circuitry detects the ACT410

die temperature. The threshold is set at typical

135˚C. When the die temperature rises above this

threshold (135˚C) the ACT410 is disabled and

remains disabled until the die temperature falls

below 115˚C, at which point the ACT410 is re-

enabled.

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ACT410

Rev 3, 27-Feb-14

TYPICAL APPLICATION CONT’D

Where ŋ is the estimated circuit efficiency, f_Lis the

line frequency, t_Cis the estimated rectifier

conduction time, C_INis empirically selected to be

2х10µF electrolytic capacitors.

Design Example

The design example below gives the procedure for

a DCM fly back converter using an ACT410. Refer

to Application Circuit Figure 2, the design for an

adapter application starts with the following

specification:

The maximum duty cycle is set to be 35% at low

line voltage 85VAC and the circuit efficiency is

estimated to be 75%. Then the maximum average

input current is:

Input Voltage Range

Output Power, P_O

90VAC - 265VAC, 50/60Hz

10W

5V

V_OUT× I_OUT

_ CC

I_IN

=

_ MAX

Output Voltage, V_OUTCV

Full Load Current, I_OUTFL

CC Current, I_OUTMAX

System Efficiency CV, η

(5)

V _INDC

× η

_ MIN

2A

12 × 2 .3

100 × 0 .75

=

= 153 mA

2-2.6A

0.75

The maximum input primary peak current:

2 × L_I

D_MAX

2 ×153

0.35

N

I_LIM

=

= 874 mA

(6)

The operation for the circuit shown in Figure 1 is as

follows: the rectifier bridge BD1 and the capacitor

C1/C2 convert the AC line voltage to DC. This

voltage supplies the primary winding of the

transformer T1 and the startup resistor R7/R8 to

VDD pin of ACT410 and C4. The primary power

current path is formed by the transformer’s primary

winding, the mosfet, and the current sense resistor

R9. The resistors R3, R2, diode D2 and capacitor

C3 create a snubber clamping network that protects

Q1 from voltage spike from the transformer primary

winding leakage inductance. The network

consisting of capacitor C4, diode D3 and resistor

R4 provides a VDD supply voltage for ACT410 from

the auxiliary winding of the transformer. The resistor

R4 is optional, which filters out spikes and noise to

makes VDD more stable. C4 is the decoupling

capacitor of the supply voltage and energy storage

component for startup. During power startup, the

current charges C4 through startup resistor R7/R8

from the rectified high voltage. The diode D4 and

the capacitor C7/L2/C6 rectify filter the output

voltage. The resistor divider consists of R5 and R6

programs the output voltage.

The primary inductance of the transformer:

V_{INDC _ MIN}D_max

L_p

=

I_LIM× f_s

(7)

(8)

100 × 0.35

874 mA ×110 k

=

= 0.37 mH

The maximum primary turns on time:

I_LIM

T_ON

= L_p

_ MAX

V_INDC

_ MIN

0.37 mH × 874 mA

=

= 3.23 μs

100

The ringing periods from primary inductance with

mosfet Drain-Source capacitor:

T_{RINGING_MAX}= 2π L_{p _MAX}C_{DS _MAX}

(9)

= 2×3.14× 0.37mH×(1+7%)×100PF =1.25μs

Design only an half ringing cycle at maximum load

in minimum low line, so secondly reset time:

T_RST=T_SW-T_{ON_MAX}-0.5T_{RINGING_MAX}

(10)

=1/ 110kHz-3.23μs-0.5×1.25μs = 5.24μs

Since a bridge rectifier and bulk input capacitors are

used, the resulting minimum and maximum DC

input voltages can be calculated:

Base on conservation of energy and transformer

transform identity, the primary to secondary turns

ratio N_P/N_S:

1

V_IN

N_P

N_S

T_ON

_ MIN

2P_OUT

(

- t_C)

=

×

2f_L

η × C_IN

V_INDC

=

2V_IN²_AC

_ MIN

T_RSTV_OUT+ V_D

100

5.24 5 + 0.45

(11)

_ MIN

3.23

(3)

=

×

= 11 .31

1

2 ×10 .5 × (

- 3.5ms )

2 × 85 ²

-

2 × 47

0.75 × 2 ×10 μF

=

≈100 V

The auxiliary to secondary turns ratio N_A/N_S:

N _A

N _S

V_DD+ V_D'

V_OUT+ V_D

12 + 0.45

5 + 0.45

=

= 2.28

V_{IN ( MAX}

=

2 ×V_{IN ( MAX}

)AC

(12)

)DC

(4)

=

2 ×(265 V_AC) = 375 V

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ACT410

Rev 3, 27-Feb-14

TYPICAL APPLICATION CONT’D

An EFD15 core is selected for the transformer.

Two 820µF electrolytic capacitors are used to keep

the ripple small.

From

the

manufacture’s

catalogue

recommendation, the gapped core with an effective

inductance A_LEof 64 nH/T²is selected. The turn of

the primary winding is:

PCB Layout Guideline

Good PCB layout is critical to have optimal

performance. Decoupling capacitor (C4) and

feedback resistor (R5/R6) should be placed close to

VDD and FB pin respectively. There are two main

power path loops. One is formed by C1/C2, primary

winding, Mosfet transistor and current sense

resistor (R9). The other is secondary winding,

rectifier D4 and output capacitors (C7/C6). Keep

these loop areas as small as possible. Connecting

high current ground returns, the input capacitor

ground lead, and the ACT410 GND pin to a single

point (star ground configuration).

L_P

0.37mH

64nH / T²

(13)

N_P=

=

= 76T

A_LE

The turns of secondary and auxiliary winding can

be derived accordingly:

N_s

1

N_S=

×N_p=

×76 ≈ 7T

(14)

(15)

N_p

11.32

N_A

N_S

N_A=

×N_s= 2.28 ×7 ≈ 20T

Determining the value of the current sense resistor

(R9) uses the peak current in the design. Since the

ACT410 internal current limit is set to 1V, the

design of the current sense resistor is given by:

V_CS

R_CS

=

2×I_{OUT _OCP}×V_OUT

L_P×F_SW×η_system

(16)

1

=

≈1.07.Ω

2×2.6×5

0.37mH×100kHz×0.75

Where Fsw is the frequency at 4.75V CC mode.

The voltage feedback resistors are selected

according to the Ioccmax and Vo. The design

Io_cc max is given by:

N_p

R_fb1× R_{fb 2}

V_O+ V_D

f_s=

×

(17)

V_cs

N_sR_fb1+ R_{fb 2}

L_p×

× K_{f _ sw}

R_cs

The design Vo is given by:

R_fb1

R_fb2

N_s

N_a

(18)

V_o= (1 +

)×

×V_FB−V_D

Where k is IC constant and K=0.000075, then we

can get the value:

(19)

R_fb1= 68K,R_fb2=11.5K

When selecting the output capacitor, a low ESR

electrolytic capacitor is recommended to minimize

ripple from the current ripple. The approximate

equation for the output capacitance value is given

by:

I_OUT

2

C_OUT

=

= 364μF

(20)

f_sw×V

110k ×50mV

RIPPLE

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ACT410

Rev 3, 27-Feb-14

Figure 2:

ACT410, Universal VAC Input, 5V/2A Output Charger

ACT410 Bill of Materials

Table 1:

ITEM

1

REFERENCE

DESCRIPTION

QTY

1

MANUFACTURER

Active-Semi.

KSC

U1

C1,C2

C3

IC, ACT410,SOT23-6

2

Capacitor, Electrolytic, 10µF/400V, 10x15mm

Capacitor, Ceramic, 1000pF/500V, 0805,SMD

Capacitor, Electrolytic,10µF/35V,5x11mm

Capacitor, Electrolytic, 820µF/6.3V, 6.3 × 16mm

Capacitor, Ceramic, 0.1µF/25V, 0805,SMD

Capacitor, Ceramic, 1000pF/100V, 0805,SMD

Capacitor, Ceramic, 200pF/50V, 0805,SMD

Safety Y1,Capacitor,1000pF/400V,Dip

Bridge Rectifier,D1010S,1000V/1.0A,SDIP

Fast Recovery Rectifier, RS1M,1000V/1.0A, RMA

Diode, Schottky, 45V/10A, S10U45S, SMD

Diode, 1N4148 SMD

2

3

1

POE

4

C4

1

KSC

5

C6,C7

C8

2

KSC

6

1

POE

7

C9

1

POE

8

C10

CY1

BD1

D2,D3

D4

1

POE

9

1

UXT

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

1

PANJIT

Vishay

2

1

D5

1

PANJIT

SoKa

L1

Axial Inductor, 1.5mH, 5*7,Dip

1

L2

Axial Inductor, 0.55*5T, 5*7,Dip

1

SoKa

Q1

Mosfet Transistor, 2N60,TO-251

PCB, L*W*T=40x28x1.6mm,Cem-1,Rev:A

Fuse,1A/250V

1

Infineon

Jintong

TY-OHM

PCB1

FR1

R2

1

Carbon Resistor, 200Kꢀ, 1206, 5%

Chip Resistor, 100ꢀ, 0805, 5%

1

R3

1

R1

Chip Resistor, 51ꢀ, 0805, 5%

1

R4,R13

R5

Chip Resistor, 22ꢀ, 0805, 5%

2

Chip Resistor, 68Kꢀ, 0805,1%

1

R6

Chip Resistor, 11.5Kꢀ, 0805, 1%

Chip Resistor, 1Mꢀ, 0805 , 5%

1

R7

1

R8

Chip Resistor, 1Mꢀ, 0805 , 5%

1

R9

Chip Resistor, 1.1ꢀ, 1206,1%

1

R10,R15

R11,R12

R14

T1

Chip Resistor, 240ꢀ, 0805 , 5%

2

Chip Resistor, 3Kꢀ, 0805 , 5%

2

Chip Resistor, 100Kꢀ, 0805, 5%

Transformer, Lp=0.37mH, EFD15

1

Innovative Power^TM

- 12 -

www.active-semi.com

Active-Semi Proprietary―For Authorized Recipients and Customers

ActivePSR^TMis a trademark of Active-Semi.

ACT410

Rev 3, 27-Feb-14

TYPICAL PERFORMANCE CHARACTERISTICS

Startup Supply Current vs. Temperature

VDD ON/OFF Voltage vs. Temperature

13.5

12.5

11.5

10.5

9.5

8

7

6

V_DDON

5

4

3

8.5

V_DDOFF

7.5

6.5

-40

0

40

80

120

-40

0

40

80

120

Temperature (°C)

Supply Current at Operation/Fault Mode

vs. Temperature

Maximum/Minimum Switching Frequency vs.

Temperature

0.6

0.5

0.4

0.3

0.2

150

Operation Mode

F_MAX

100

50

0

Fault Mode

F_MIN

-40

0

40

80

120

-40

0

40

80

120

Temperature (°C)

V_FBThreshold Voltage vs. Temperature

V_CSVoltage vs. Temperature

2

1.5

1

2.5

V_REF

V_{CS_Open}

V_CSVoltage

2

0.5

0

V_{CS_Short}

1.5

-40

0

40

80

120

-40

0

40

80

120

Temperature (°C)

Innovative Power^TM

- 13 -

www.active-semi.com

Active-Semi Proprietary―For Authorized Recipients and Customers

ActivePSR^TMis a trademark of Active-Semi.

ACT410

Rev 3, 27-Feb-14

TYPICAL PERFORMANCE CHARACTERISTICS

V_COMPVoltage vs. Temperature

V_MAX

4

3

2

1

0

V_MIN

-40

0

40

80

120

Temperature (°C)

Innovative Power^TM

- 14 -

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Active-Semi Proprietary―For Authorized Recipients and Customers

ActivePSR^TMis a trademark of Active-Semi.

ACT410

Rev 3, 27-Feb-14

PACKAGE OUTLINE

SOT23-6 PACKAGE OUTLINE AND DIMENSIONS

Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each

product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use

as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of

the use of any product or circuit described in this datasheet, nor does it convey any patent license.

Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact

sales@active-semi.com or visit http://www.active-semi.com.

is a registered trademark of Active-Semi.

Innovative Power^TM

- 15 -

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Active-Semi Proprietary―For Authorized Recipients and Customers

ActivePSR^TMis a trademark of Active-Semi.

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Active-Semi:

ACT410US-T


型号：	ACT410_14
厂家：	ACTIVE-SEMI, INC
描述：	ActivePSRTM Quasi-Resonant PWM Controller
文件：	总16页 (文件大小：301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ACT410_14 [ACTIVE-SEMI]

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