ACT8810QJ1C1-T [ACTIVE-SEMI]
Eight Channel ActivePathTM Power Management IC; 八通道ActivePathTM电源管理IC
| 型号： | ACT8810QJ1C1-T |
| 厂家： | 
ACTIVE-SEMI, INC |
| 描述： | Eight Channel ActivePathTM Power Management IC |
| 文件： | 总52页 (文件大小：884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Active- Semi
ACT8810
Rev 4, 01-Oct-09
Eight Channel ActivePathTM Power Management IC
FEATURES
GENERAL DESCRIPTION
• ActivePathTM Li+ Charger with System Power
The patent-pending ACT8810 is a complete, cost effect
tive, highly-efficient ActivePMUTM power management
solution that is ideal for a wide range of high
performance portable handheld applications such as
personal navigation devices (PNDs). This device
integrates the ActivePathTM complete battery charging
and management system with six power supply
channels.
Selection
• Six Integrated Regulators
− 1.3A High Efficiency Step-Down DC/DC
− 1.0A High Efficiency Step-Down DC/DC
− 0.55A High Efficiency Step-Down DC/DC
− 2×360mA Low Noise, High PSRR LDOs
− 30mA RTC LDO / Backup Battery Charger
The ActivePath architecture automatically selects the
best available input supply for the system. If the
external input source is not present or the system load
current is more than the input source can provide, the
ActivePath supplies additional current from the battery
to the system. The charger is a complete, thermally-
regulated, stand-alone single-cell linear Li+ charger
that incorporates an internal power MOSFET.
• I2CTM Serial Interface
• Minimal External Components
• Compatible with USB or AC-Adapter
Charging
• 5mm × 5mm, Thin-QFN (TQFN55-40) Package
− Only 0.75mm Height
− RoHS Compliant
REG1, REG2, and REG3 are three independent,
fixed-frequency, current-mode step-down DC/DC
converters that output 1.3A, 1.0A, and 0.55A,
respectively. REG4 and REG5 are high performance,
low-noise, low-dropout linear regulators that output
up to 360mA each. REG6 is a RTC LDO that
outputs up to 30mA for a real time clock. Finally, an
I2C serial interface provides programmability for the
DC/DC converters and LDOs.
APPLICATIONS
• Personal Navigation Devices
• Portable Media Players
• Smart Phones
The ACT8810 is available in a tiny 5mm x 5mm 40-
pin Thin-QFN package that is just 0.75mm thin.
SYSTEM BLOCK DIAGRAM
Battery
CHG_IN
Programmable
Up to 1A
VSYS
CHGLEV
ActivePathTM
DCCC
&
ISET
ACIN
nSTAT
TH
REG1
Step-Down
DC/DC
Single-Cell Li+
Battery Charger
OUT1
Adjustable, or
0.8V to 4.4V
Up to 1.3A
REG2
Step-Down
DC/DC
BTR
OUT2
Adjustable, or
0.8V to 4.4V
Up to 1.0A
nPBIN
nIRQ
nRSTO
SCL
SDA
ON1
ON2
ON3
VSEL
REG3
Step-Down
DC/DC
OUT3
Adjustable, or
0.8V to 4.4V
Up to 0.55A
System
Control
REG4
LDO
OUT4
0.9V to 3.3V
Up to 360mA
REG5
LDO
OUT5
0.9V to 3.3V
Up to 360mA
REG6
RTC_LDO
ACT8810
OUT6
0.9V to 3.3V
Up to 30mA
TM
PMU
Active
Innovative PowerTM
- 1 -
www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
TABLE OF CONTENTS
GENERAL INFORMATION ..........................................................................................P. 01
Functional Block Diagram ......................................................................................................p. 03
Ordering Information ..............................................................................................................p. 04
Pin Configuration....................................................................................................................p. 04
Pin Descriptions .....................................................................................................................p. 05
Absolute Maximum Ratings....................................................................................................p. 07
SYSTEM MANAGEMENT ...........................................................................................P. 08
Register Descriptions .............................................................................................................p. 08
I2C Interface Electrical Characteristics...................................................................................p. 09
Electrical Characteristics........................................................................................................p. 10
Register Descriptions .............................................................................................................p. 11
Typical Performance Characteristics......................................................................................p. 12
Functional Description............................................................................................................p. 13
STEP-DOWN DC/DC CONVERTERS..........................................................................P. 17
Electrical Characteristics........................................................................................................p. 17
Typical Performance Characteristics......................................................................................p. 20
Register Descriptions .............................................................................................................p. 22
Functional Description............................................................................................................p. 28
LOW-DROPOUT LINEAR REGULATORS ..................................................................P. 31
Electrical Characteristics........................................................................................................p. 31
Typical Performance Characteristics......................................................................................p. 33
Register Descriptions .............................................................................................................p. 34
Functional Description............................................................................................................p. 36
RTC LOW-DROPOUT LINEAR REGULATOR ............................................................P. 37
Electrical Characteristics........................................................................................................p. 37
Register Descriptions .............................................................................................................p. 38
Functional Description............................................................................................................p. 39
ActivePathTM CHARGER.............................................................................................P. 40
Electrical Characteristics........................................................................................................p. 40
Typical Performance Characteristics......................................................................................p. 42
Functional Description............................................................................................................p. 44
PACKAGE INFORMATION..........................................................................................P. 52
Innovative PowerTM
- 2 -
www.active-semi.com
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
FUNCTIONAL BLOCK DIAGRAM
BODY
SWITCH
Active- Semi
(Optional)
CHG_IN
VSYS System Supply
Up to 12V
ACT8810
AC Adaptor
BODY
SWITCH
USB
DCCC
ACIN
BAT
Li+ Battery
+
ActivePath
Control
100µA
VSYS
CURRENT SENSE
VOLTAGE SENSE
nSTAT
ISET
TH
PRE-
CONDITION
CHARGE STATUS
2.9V
BTR
THERMAL
REGULATION
Charge
Control
110°C
VSYS
VP1
CHGLEV
To VSYS
OUT1
SW1
OUT1
nRSTO
OUT1
GP1
VSYS
VP2
nPBIN
nIRQ
To VSYS
PUSH BUTTON
OUT1
SW2
OUT2
GP2
OUT2
VP3
To VSYS
SCL
SDA
SW3
OUT3
GP3
OUT3
System
Control
ON1
ON2
INL
To VSYS
OUT4
OUT4
ON3
REG4
LDO
OUT5
OUT6
REG5
LDO
VSEL
OUT5
REG6
RTC_LDO
REFBP
OUT6
Reference
GA
EP
Innovative PowerTM
- 3 -
www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
ORDERING INFORMATIONꢀ
PART
NUMBER
ꢁ
V
OUT1/VSTBY1 VOUT2/VSTBY2 VOUT3/VSTBY3 VOUT4 VOUT5 VOUT6 CONTROL SEQUENCEꢂ
ACT8810QJ1C1-T
ACT8810QJ213-T
ACT8810QJ3EB-T
ACT8810QJ45D-T
ACT8810QJ50F-T
3.3V/3.3V
1.2V/1.2V
3.3V/3.3V
3.3V/3.3V
1.2V/1.2V
1.1V/1.2V
1.8V/1.8V
1.2V/1.2V
1.8V/1.8V
3.3V/3.3V
1.2V/1.2V
1.0V/1.0V
1.8V/1.8V
1.3V/1.3V
1.8V/1.8V
1.2V 2.8V 3.3V
3.3V 1.2V 3.0V
1.5V 2.8V 3.3V
1.2V 3.3V 3.3V
3.3V 1.8V 3.0V
Sequence A
Sequence B
Sequence C
Sequence D
Sequence E
TEMPERATURE
PACKAGING DETAILS
PACKAGE
PINS
PACKING
RANGE
ACT8810QJ###-T
TQFN55-40
40
-40°C to +85°C
TAPE & REEL
ꢀ: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means
semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
ꢁ: To select VSTBYx as a output regulation voltage of REGx, tie VSEL to VSYS or a logic high.
ꢂ: Refer to the Control Sequence section for more information.
PIN CONFIGURATION
TOP VIEW
OUT5
OUT6
VP3
TH
DCCC
BTR
SW3
GP3
ACIN
BAT
Active- Semi
OUT3
nPBIN
SDA
BAT
ACT8810
VSYS
VSYS
CHG_IN
ISET
SCL
EP
ON3
Thin - QFN (TQFN55-40)
Innovative PowerTM
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www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 100µA current internally.
See the Battery Temperature Monitoring section for more information.
1
2
TH
Dynamic Charging Current Control. Connect a resistor to set the dynamic charging current control point.
A internal 100µA current source sets up a voltage that is used to compare with VSYS and dynamically
scale the charging current to maintain VSYS regulation. See the Dynamic Charge Current Control
section for more information.
DCCC
Safety Timer Program Pin. The resistance between this pin and GA determines the timers timeout
values. See the Charging Safety Timers section for more information.
3
4
BTR
AC Adaptor Detect. Detects presence of a wall adaptor and automatically adjusts the charge current
to the maximum charge current level. Do not leave ACIN floating.
ACIN
5, 6
7, 8
BAT
Battery Charger Output. Connect this pin directly to the battery anode (+ terminal)
System Output Pin. Bypass to GA with a 10µF or larger ceramic capacitor.
VSYS
Power Input for the Battery Charger. Bypass CHG_IN to GA with a capacitor placed as close to the
9
CHG_IN IC as possible. The battery charger are automatically enabled when a valid voltage is present on
CHG_IN. See the CHG_IN Bypass Capacitor Selection section for more information.
Charge Current Set. Program the maximum charge current by connecting a resistor (RISET) between
ISET and GA. See the Charger Current Programming section for more information.
10
11
ISET
Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage. See the Output Voltage Selection Pin section
VSEL
for more information.
Independent Enable Control Input for REG1. Drive ON1 to VSYS or to a logic high for normal
operation, drive to GA or a logic low to disable REG1. Do not leave ON1 floating.
12
13
ON1
Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
OUT2
Power Input for REG2. Bypass to GP2 with a high quality ceramic capacitor placed as close as
possible to the IC.
14
15
16
VP2
SW2
GP2
Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
Power Ground for REG2. Connect GA, GP1, GP2 and GP3 together at a single point as close to the
IC as possible.
Power Ground for REG1. Connect GA, GP1, GP2 and GP3 together at a single point as close to the
IC as possible.
17
18
19
GP1
SW1
VP1
Switching Node Output for REG1. Connect this pin to the switching end of the inductor.
Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close as
possible to the IC.
Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
20
21
OUT1
ON3
Enable Control Input for REG3. Drive ON3 to a logic high for normal operation, drive to GA or a logic
low to disable REG3. Do not leave ON3 floating.
22
23
SCL
SDA
Clock Input for I2C Serial Interface.
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
Innovative PowerTM
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www.active-semi.com
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
PIN DESCRIPTIONS CONT’D
PIN NAME
DESCRIPTION
Master Enable Input. Drive nPBIN to GA through a 100kΩ resistor to enable the IC, drive nPBIN
directly to GA to assert a Hard-Reset condition. Refer to the System Startup & Shutdown and
Control Sequence sections for more information. nPBIN is internally pulled up to VSYS through a
50kΩ resistor.
24
25
nPBIN
OUT3
Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to
the IC as possible.
26
27
28
29
30
GP3
SW3
VP3
Switching Node Output for REG3. Connect this pin to the switching end of the inductor.
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as
possible to the IC.
OUT6 RTC LDO Output Voltage. Capable of delivering up to 30mA of output current.
Output Voltage for REG5. Capable of delivering up to 360mA of output current. The output is
discharged to GA with 1kΩ when disabled.
OUT5
Power Input for REG4, REG5, and REG6. Bypass to GA with a high quality ceramic capacitor
placed as close as possible to the IC.
31
32
INL
Output Voltage for REG4. Capable of delivering up to 360mA of output current. The output is
discharged to GA with 1kΩ when disabled.
OUT4
Active-Low Open-Drain Charger Status Output. nSTAT has a 5mA (typ) current limit, allowing it to
directly drive an indicator LED without additional external components. To generate a logic-level
output, connect nSTAT to an appropriate supply voltage (typically VSYS) through a 10kΩ or
33
nSTAT
greater pull-up resistor. See the Charge Status Indication section for more information.
Independent Enable Control Input for REG2. Drive ON2 to a logic high for normal operation, drive to
GA or a logic low to disable REG2. Do not leave ON2 floating.
34
35, 37
36
ON2
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1, GP2, and GP3
together at a single point as close to the IC as possible.
GA
Reference Noise Bypass. Connect a 0.01μF ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
REFBP
Open-Drain Reset Output. nRSTO asserts low whenever REG1 is out of regulation, and remains low
for 260ms (typ) after REG1 reaches regulation.
38
nRSTO
Open-Drain Interrupt Output. nIRQ asserts any time nPBIN is asserted or an unmasked fault
condition exists. See the nIRQ Output section for more information.
39
nIRQ
Charging State Select Input.
When ACIN = 0 charge current is internally set; Drive CHGLEV to a logic-high for high-current USB
charging mode (maximum charge current is 500mA), drive CHGLEV to a logic-low for low-current
40 CHGLEV USB charging mode (maximum charge current is 100mA).
When ACIN = 1 charge current is externally set by RISET; Drive CHGLEV to a logic-high to for high-
current charging mode (ICHG = K × 1000/RISET (mA) where K = 640), drive CHGLEV to a logic-low for
low-current charging mode (ICHG = K × 500/RISET (mA) where K = 640). Do not leave CHGLEV floating.
EP
EP
Exposed Pad. Must be soldered to ground on the PCB.
Innovative PowerTM
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www.active-semi.com
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
ABSOLUTE MAXIMUM RATINGSꢀ
PARAMETER
VALUE
UNIT
CHG_IN to GA
t < 1ms and duty cycle <1%
Steady State
-0.3 to +18
-0.3 to +14
V
V
VP1 to GP1, VP2 to GP2, VP3 to GP3
BAT, VSYS, INL to GA
SW1, OUT1 to GP1
-0.3 to +6
V
V
V
V
V
-0.3 to +6
-0.3 to (VVP1 +0.3)
-0.3 to (VVP2 +0.3)
-0.3 to (VVP3 +0.3)
SW2, OUT2 to GP2
SW3, OUT3 to GP3
ON1, ON2, ON3, ISET, ACIN, VSEL, DCCC, CHGLEV, TH, SCL, SDA, REFBP, nIRQ,
nRSTO, nSTAT, BTR, nPBIN to GA
-0.3 to +6
V
OUT4, OUT5, OUT6 to GA
-0.3 to (VINL +0.3)
-40 to 85
V
Operating Ambient Temperature
Maximum Junction Temperature
°C
°C
125
Maximum Power Dissipation
2.7
W
TQFN55-40 (Thermal Resistance θJA = 30oC/W)
Storage Temperature
-65 to 150
300
°C
°C
Lead Temperature (Soldering, 10 sec)
ꢀ: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
Innovative PowerTM
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www.active-semi.com
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
REGISTER DESCRIPTIONS
Table 1:
Global Register Map
ADDRESS
DATA (DEFAULT VALUE)
OUTPUT
HEX A7 A6
A5
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
A4
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
A0 D7 D6 D5 D4 D3 D2 D1 D0
SYS
06h
10h
11h
12h
13h
20h
21h
22h
23h
30h
31h
32h
33h
40h
43h
41h
42h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
1
R
R
R
R
V
R
R
R
V
R
R
R
V
R
R
R
R
R
V
R
R
V
V
R
R
V
V
R
R
V
1
0
V
R
R
V
V
R
R
V
V
R
R
V
V
R
V
V
R
V
R
R
V
V
R
R
V
V
R
R
V
V
R
V
V
R
V
R
0
1
V
R
R
V
V
R
R
V
V
R
R
V
V
0
R
V
R
1
REG1
REG1
REG1
REG1
REG2
REG2
REG2
REG2
REG3
REG3
REG3
REG3
REG4
REG4
REG5
REG6
V
V
R
0
V
V
R
1
V
V
R
0
V
V
R
1
V
V
R
V
V
V
V
R
V
V
R
1
R
1
V
V
R
R
KEY:
R: Read-Only bits. No Default Assigned.
V: Default Values Depend on Voltage Option. Default Values May Vary.
Note: Addresses other than those specified in Table 1 may be used for factory settings. Do not access any registers other than those
specified in Table 1.
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
SCL, SDA Low Input Voltage
TEST CONDITIONS
MIN TYP MAX UNIT
VVSYS = 2.6V to 5.5V, TA = -40ºC to 85ºC
0.35
V
V
SCL, SDA High Input Voltage
VVSYS = 2.6V to 5.5V, TA = -40ºC to 85ºC 1.55
SCL, SDA Leakage Current
1
µA
V
SDA Low Output Voltage
I
OL = 5mA
0.3
SCL Clock Period, tSCL
2.5
100
300
100
100
µs
ns
ns
ns
ns
SDA Data In Setup Time to SCL High, tSU
SDA Data Out Hold Time after SCL Low, tHD
SDA Data Low Setup Time to SCL Low, tST
Start Condition
SDA Data High Hold Time after Clock High, tSP Stop Condition
Figure 1:
I2C Serial Bus Timing
tSCL
SCL
tST
tSU
tSP
SDA IN
tHD
SDA OUT
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Copyright © 2009 Active-Semi, Inc.
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
WLED BIAS DC/DC CONVERTER (REG3)
ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Input Voltage Range
2.6
5.5
2.6
V
V
UVLO Threshold Voltage
UVLO Hysteresis
VSYS Rising
2.35
2.5
100
70
VSYS Falling
mV
µA
µA
V
VSYS Supply Current
VSYS Shutdown Current
Voltage Reference
ONx = VSYS
ONx = GA, Not Charging
30
1.24
1.35
1.4
1.25
1.6
1.26
1.85
Oscillator Frequency
MHz
V
Logic High Input Voltage
Logic Low Input Voltage
Leakage Current
ON1, ON2, ON3, VSEL
ON1, ON2, ON3, VSEL
0.4
1
V
V
ON1 = VON2 = VON3 = VVSEL = VnIRQ = VnRSTO = 4V
µA
kΩ
V
nPBIN Internal Pull-up Resistance
Low Level Output Voltage
nRSTO Delay
50
0.3
260
160
20
nIRQ, nRSTO. Sinking 10mA
ms
°C
°C
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Temperature rising
Temperature decreasing
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Copyright © 2009 Active-Semi, Inc.
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 2:
Control Register Map
DATA
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
06h
R
R
R
W/E
R
R
nPBMASK PBSTAT
R: Read-Only bits. Default Values May Vary.
W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 3:
Control Register Bit Descriptions
ADDRESS
NAME
BIT ACCESS
FUNCTION
DESCRIPTION
De-assert
0
1
0
1
06h
PBSTAT
[0]
[1]
R/W
R/W
Push Button Status
Asserted
Masked
06h
nPBMASK
Push Button Interrupt Mask Option
Not Mask
06h
06h
06h
[3:2]
[4]
R
W/E
R
READ ONLY
WRITE-EXACT
READ ONLY
[7:5]
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
TYPICAL PERFORMANCE CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
Oscillator Frequency vs. Temperature
1.71
1.68
1.65
1.62
1.59
1.56
1.53
1.50
-40
-20
0
20
40
60
85
Temperature (°C)
Shutdown Current vs. Temperature
26
ON1 = ON2 = ON3 = GA
VVSYS = 4.2V
VVSYS = 3.6V
24
22
20
VVSYS = 3.2V
-40
-20
0
20
40
60
85
Temperature (°C)
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ACT8810
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Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
FUNCTIONAL DESCRIPTION
process is completely software-controlled, a typical
shutdown sequence proceeds as follows: The
second assertion of nPBIN asserts nPBIN and
interrupts the microprocessor, which then initiates
an interrupt service routine to reveal that nPBIN has
been asserted. If there is no input to the charger,
then the microprocessor disables each regulator
according to the sequencing requirements of the
system, then the system will finally be disabled
when each of ON1, ON2, and ON3 have been de-
asserted.
General Description
The ACT8810 offers a wide array of system
management functions that allow it to be configured
for optimal performance in a wide range of
applications.
I2C Serial Interface
At the core of the ACT8810’s flexible architecture is
an I2C interface that permits optional programming
capability to enhance overall system performance.
To ensure compatibility with a wide range of system
processors, the ACT8810 uses standard I2C
commands; I2C write-byte commands are used to
program the ACT8810, and I2C read-byte
commands are used to read the ACT8810’s internal
registers. The ACT8810 always operates as a slave
device, and is addressed using a 7-bit slave
address followed by an eighth bit, which indicates
whether the transaction is a read-operation or a
write-operation, [1011010x].
nPBIN Input
ACT8810's nPBIN pin is a dual-function pin,
combining system enable/disable control with a
hardware reset function. Refering to Figure 2, the
two pin functions are obtained by asserting this pin
low, either through a direct connection or through a
100kΩ resistor, as described below.
In most applications, nPBIN will be driven through a
100kΩ resistor. When driven in this way, nPBIN
initiates system startup or shutdown, as described
in the System Startup and Shutdown section.
SDA is a bi-directional data line and SCL is a clock
input. The master initiates a transaction by issuing a
START condition, defined by SDA transitioning from
high to low while SCL is high. Data is transferred in
8-bit packets, beginning with the MSB, and is
clocked-in on the rising edge of SCL. Each packet
of data is followed by an “Acknowledge” (ACK) bit,
used to confirm that the data was transmitted
successfully.
When a hardware-reset function is desired, nPBIN
may also be driven directly to GA. In this case,
nRSTO is immediately asserted low and remains
low until nPBIN is de-asserted and the reset timeout
period expires. This provides a hardware-reset
function, allowing the system to be manually reset if
the system processor locks up.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com
Although a typical application will use momentary
switches to drive nPBIN, as shown in Figure 2,
nPBIN may also be driven by other sources, such
as a GPIO or other logic output.
System Startup and Shutdown
Figure 2:
Startup Sequence
nPBIN Input
The ACT8810 features
a
flexible enable
architecture that allows it to support a variety of
push-button enable/disable schemes. Although
other startup routines are possible, ACT8810
provides three typical startup and shutdown
processes proceed as shown in Control Sequence
section.
Shutdown Sequence
Once a successful power-up routine is completed, a
shutdown process may be initiated by asserting
nPBIN a second time, typically as the result of
pressing the push-button. Although the shutdown
Enable/Disable Inputs (ON1, ON2 and ON3)
The ACT8810 provides three manual
enable/disable inputs, ON1, ON2 and ON3, which
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ACT8810
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Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
FUNCTIONAL DESCRIPTION CONT’D
enable and disable REG1, REG2, and REG3,
respectively. Once the system is enabled, the
system will remain enabled until all of ON1, ON2,
and ON3 have been de-asserted. See the Control
Sequence section for more information.
ACT8810QJ1## begins its system startup
procedure by enabling REG1. When REG1 reaches
94% of its final regulation voltage, ACT8810QJ1##
automatically turns on REG4 and REG5 and
nRSTO is asserted low, holding the microprocessor
in reset for a user-selectable reset period of 260ms.
If VOUT1 is within 6% of its regulation voltage when
the reset timer expires, the nRSTO is de-asserted,
and the microprocessor can begin its power-up
sequence. Once the power-up routine is
successfully completed, the system remains
enabled after the push-button is released as long as
the microprocessor asserts any one of ON1, ON2
or ON3, and REG4, REG5 may be enabled or
disabled via the I2C interface.
Power-On Reset Output
nRSTO is an open-drain output which asserts low
upon startup or when nPBIN is driven directly to
GA, and remains asserted low until the 260ms
(default) power-on reset timer has expired. Connect
a 10kΩ or greater pull-up resistor from nRSTO to an
appropriate voltage supply.
nIRQ Output
This start-up procedure requires that the
pushbutton be held until the microprocessor
assumes control (by asserting any one of ON1,
ON2, and ON3), providing protection against
inadvertent momentary assertions of the
pushbutton. If desired, longer “push-and-hold” times
can be easily implemented by simply adding an
additional time delay before asserting ON1, ON2, or
ON3. If the microprocessor is unable to complete its
power-up routine successfully before the user lets
go of the push-button, the ACT8810QJ1##
automatically shuts itself down.
nIRQ is an open-drain output that asserts low any
time startup or an unmasked fault condition exists.
When asserted, nIRQ remains low until the
microprocessor polls the ACT8810's I2C interface.
The ACT8810 supports a variety of other fault
conditions, which may each be optionally unmasked
via the I2C interface. For more information about the
available fault conditions, refer to the appropriate
sections of this datasheet.
Connect a pull-up resistor from nIRQ to an
appropriate voltage supply. nIRQ is typically used to
drive the interrupt input of the system processor,
and is useful in a variety of software-controlled
enable/disable control routines.
Figure 3:
Sequence A
Thermal Shutdown
First Push
Button
Assert
Power-Hold
Release
Button
Second Push System
Button Shutdown
The ACT8810 integrates thermal shutdown
protection circuitry to prevent damage resulting
from excessive thermal stress, as may be
encountered under fault conditions. This circuitry
disables all regulators if the ACT8810 die
temperature exceeds 160°C, and prevents the
regulators from being enabled until the IC
temperature drops by 20°C (typ).
nPBIN
System Enable
94% of VOUT1
OUT1
ON1, ON2, ON3
OUT2, OUT3
OUT4, OUT5
Reset time Enable
nRSTO
Control Sequence
260ms
Sequence A
The ACT8810QJ1## which is set with “sequence
A“, has a system startup is initiated whenever the
following conditions occurs:
nIRQ
1) nPBIN is pushed low via 100kΩ resistance,
When ever this condition exists, the
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
Sequence B
Sequence C
The ACT8810QJ2## which is set with “sequence
B“, has a system startup is initiated whenever the
following conditions occurs:
The ACT8810QJ3## which is set with “sequence
C“, has a system startup is initiated whenever the
following conditions occurs:
1) nPBIN is pushed low via 100kΩ resistance,
1) nPBIN is pushed low via 100kΩ resistance,
When ever this condition exists, the
ACT8810QJ2## begins its system startup
procedure by enabling REG1. When REG1 reaches
94% of its final regulation voltage, ACT8810QJ2##
automatically turns on REG2 and REG3 and
nRSTO is asserted low, holding the microprocessor
in reset for a user-selectable reset period of 260ms.
If VOUT1 is within 6% of its regulation voltage when
the reset timer expires, the nRSTO is de-asserted,
and the microprocessor can begin its power-up
sequence. Once the power-up routine is
successfully completed, the system remains
enabled after the push-button is released as long as
the microprocessor asserts any one of ON1, ON2
or ON3. REG4 and REG5 may be enabled if the
microprocessor sets REG4.ON[] and REG5.ON[] to
1 via the I2C interface. In other case, REG4 and
REG5 are disable.
This start-up procedure requires that the
pushbutton be held until the microprocessor
assumes control (by asserting any one of ON1,
ON2, and ON3), providing protection against
inadvertent momentary assertions of the
pushbutton. If desired, longer “push-and-hold” times
can be easily implemented by simply adding an
additional time delay before asserting ON1, ON2, or
ON3. If the microprocessor is unable to complete its
power-up routine successfully before the user lets
go of the push-button, the ACT8810QJ2##
automatically shuts itself down.
When ever this condition exists, the
ACT8810QJ3## begins its system startup
procedure by enabling REG1. When REG1 reaches
94% of its final regulation voltage, ACT8810QJ3##
automatically turns on REG2, REG3, REG4, REG5
and nRSTO is asserted low, holding the
microprocessor in reset for a user-selectable reset
period of 260ms. If VOUT1 is within 6% of its
regulation voltage when the reset timer expires, the
nRSTO is de-asserted, and the microprocessor can
begin its power-up sequence. Once the power-up
routine is successfully completed, the system
remains enabled after the push-button is released
as long as the microprocessor asserts any one of
ON1, ON2 or ON3, and REG4, REG5 may be
enabled or disabled via the I2C interface.
This start-up procedure requires that the
pushbutton be held until the microprocessor
assumes control (by asserting any one of ON1,
ON2, and ON3), providing protection against
inadvertent momentary assertions of the
pushbutton. If desired, longer “push-and-hold” times
can be easily implemented by simply adding an
additional time delay before asserting ON1, ON2, or
ON3. If the microprocessor is unable to complete its
power-up routine successfully before the user lets
go of the push-button, the ACT8810QJ3##
automatically shuts itself down.
Figure 5:
Figure 4:
Sequence C
Sequence B
First Push
Button
Assert
Power-Hold
Release
Button
Second Push System
Button Shutdown
First Push
Button
Assert
Power-Hold
Release
Button
Second Push System
Button Shutdown
nPBIN
nPBIN
System Enable
OUT1
System Enable
94% of VOUT1
~100ms
94% of VOUT1
~100ms
OUT1
Enable Qualification
ON1, ON2, ON3
Enable Qualification
ON1, ON2, ON3
OUT2, OUT3
OUT2, OUT3
OUT4, OUT5
REG4.ON[ ],
REG5.ON[ ]
Reset time Enable
nRSTO
260ms
OUT4, OUT5
Reset time Enable
nRSTO
260ms
nIRQ
nIRQ
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Rev 4, 01-Oct-09
SYSTEM MANAGEMENT
Sequence D
Sequence E
The ACT8810QJ4## which is set with “sequence
D“, has a system startup is initiated whenever the
following conditions occurs:
The ACT8810QJ5## which is set with “sequence
E“, has a system startup is initiated whenever the
following conditions occurs:
1) nPBIN is pushed low via 100kΩ resistance,
1) A valid input voltage is present at VIN, or
When ever this condition exists, the
ACT8810QJ4## begins its system startup
procedure by enabling REG1, REG2, REG4, and
REG5. When ACT8810QJ4## in the first enable,
nRSTO is asserted low, holding the microprocessor
in reset for a user-selectable reset period of 260ms.
when the reset timer expires, the nRSTO is de-
asserted, and the microprocessor can begin its
power-up sequence. Once the power-up routine is
successfully completed, the system remains
enabled after the push-button is released as long as
the microprocessor asserts any one of ON1, ON2
or ON3, holding REG1, REG2, REG4, REG5, and
enabling REG3. And any regulators could be
enabled or disabled via the I2C interface.
2) nPBIN is pushed low via 100kΩ resistance,
When ever this condition exists, the
ACT8810QJ5## begins its system startup
procedure by enabling REG1. When REG1 reaches
94% of its final regulation voltage, ACT8810QJ5##
automatically turns on REG2, REG3, REG4, REG5
and nRSTO is asserted low, holding the
microprocessor in reset for a user-selectable reset
period of 260ms. If VOUT1 is within 6% of its
regulation voltage when the reset timer expires, the
nRSTO is de-asserted, and the microprocessor can
begin its power-up sequence. Once the power-up
routine is successfully completed, the system
remains enabled after the push-button is released
as long as the microprocessor asserts any one of
ON1, ON2 or ON3, and REG4, REG5 may be
enabled or disabled via the I2C interface.
This start-up procedure requires that the
pushbutton be held until the microprocessor
assumes control (by asserting any one of ON1,
ON2, and ON3), providing protection against
inadvertent momentary assertions of the
pushbutton. If desired, longer “push-and-hold” times
can be easily implemented by simply adding an
additional time delay before asserting ON1, ON2, or
ON3. If the microprocessor is unable to complete its
power-up routine successfully before the user lets
go of the push-button, the ACT8810QJ4##
automatically shuts itself down.
This start-up procedure requires that the
pushbutton be held until the microprocessor
assumes control (by asserting any one of ON1,
ON2, and ON3), providing protection against
inadvertent momentary assertions of the
pushbutton. If desired, longer “push-and-hold” times
can be easily implemented by simply adding an
additional time delay before asserting ON1, ON2, or
ON3. If the microprocessor is unable to complete its
power-up routine successfully before the user lets
go of the push-button or un-plug charger input, the
ACT8810QJ5## automatically shuts itself down.
Figure 6:
Sequence D
Figure 7:
First Push
Button
Assert
Power-Hold
Release
Button
Second Push
Button
System
Shutdown
Sequence E
nPBIN
First Push
Button
Assert
Power-Hold
Release
Button
Second Push System
Button Shutdown
CHG_IN
OR
System Enable
OUT1, OUT2
nPBIN
System Enable
OUT4, OUT5
94% of VOUT1
~100ms
OUT1
ON1, ON2, ON3
OUT3
Enable Qualification
ON1, ON2, ON3
OUT2, OUT3
Reset time Enable
260ms
OUT4, OUT5
nRSTO
nIRQ
Reset time Enable
260ms
nRSTO
nIRQ
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
ELECTRICAL CHARACTERISTICS (REG1)
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
VP1 Operating Voltage Range
VP1 UVLO Threshold
TEST CONDITIONS
MIN
2.9
TYP
MAX
5.5
UNIT
V
Input Voltage Rising
2.7
2.8
85
2.9
V
VP1 UVLO Hysteresis
Input Voltage Falling
mV
µA
µA
Quiescent Supply Current
Shutdown Supply Current
130
0.1
200
1
REG1 is disabled, VVP1 = 4.2V
ꢀ
V
NOM1 < 1.5V, IOUT1 = 10mA
-2.1%
-1.5%
VNOM1
VNOM1
0.15
0.0017
1.8
+2.1%
+1.5%
Output Voltage Accuracy
V
VNOM1 ≥ 1.5V, IOUT1 = 10mA
Line Regulation
Load Regulation
Current Limit
VVP1 = Max(VNOM1 + 1V, 3.2V) to 5.5V
OUT1 = 10mA to 1.3A
%/V
%/mA
A
I
1.4
V
OUT1 ≥ 20% of VNOM1
1.35
1.6
1.85
MHz
kHz
Ω
Oscillator Frequency
VOUT1 = 0V
540
PMOS On-Resistance
NMOS On-Resistance
SW1 Leakage Current
Power Good Threshold
Minimum On-Time
I
SW1 = -100mA
SW1 = 100mA
0.16
0.16
0.24
0.24
1
I
Ω
VVP1 = 5.5V, VSW1 = 5.5V or 0V
µA
94
60
%VNOM1
ns
ꢀ: VNOM1 refers to the nominal output voltage level for VOUT1 as defined by the Ordering Information section.
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Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
ELECTRICAL CHARACTERISTICS (REG2)
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
VP2 Operating Voltage Range
VP2 UVLO Threshold
TEST CONDITIONS
MIN
2.9
TYP
MAX
5.5
UNIT
V
Input Voltage Rising
2.7
2.8
85
2.9
V
VP2 UVLO Hysteresis
Input Voltage Falling
mV
µA
µA
Quiescent Supply Current
Shutdown Supply Current
130
0.1
200
1
REG2 Disabled, VVP2 = 4.2V
ꢀ
V
NOM2 < 1.5V, IOUT2 = 10mA
-2.1%
-1.5%
VNOM2
VNOM2
0.15
0.0017
1.45
1.6
+2.1%
+1.5%
Output Voltage Regulation Accuracy
V
VNOM2 ≥ 1.5V, IOUT2 = 10mA
Line Regulation
Load Regulation
Current Limit
VVP2 = Max(VNOM2 + 1V, 3.2V) to 5.5V
OUT2 = 10mA to 1.0A
%/V
%/mA
A
I
1.15
1.35
VOUT2 ≥ 20% of VNOM2
1.85
MHz
kHz
Ω
Oscillator Frequency
V
OUT2 = 0V
540
PMOS On-Resistance
NMOS On-Resistance
SW2 Leakage Current
Power Good Threshold
Minimum On-Time
I
SW2 = -100mA
SW2 = 100mA
0.25
0.17
0.38
0.26
1
I
Ω
VVP2 = 5.5V, VSW2 = 5.5V or 0V
µA
94
60
%VNOM2
ns
ꢀ: VNOM2 refers to the nominal output voltage level for VOUT2 as defined by the Ordering Information section.
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Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
ELECTRICAL CHARACTERISTICS (REG3)
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
VP3 Operating Voltage Range
VP3 UVLO Threshold
TEST CONDITIONS
MIN
2.9
TYP
MAX
5.5
UNIT
V
Input Voltage Rising
2.7
2.8
85
2.9
V
VP3 UVLO Hysteresis
Input Voltage Falling
mV
µA
µA
Quiescent Supply Current
Shutdown Supply Current
130
0.1
200
1
REG3 Disabled, VVP3 = 4.2V
ꢀ
V
NOM3 < 1.5V, IOUT3 = 10mA
-2.1%
-1.5%
VNOM3
VNOM3
0.15
0.0017
0.7
+2.1%
+1.5%
Output Voltage Regulation Accuracy
V
VNOM3 ≥ 1.5V, IOUT3 = 10mA
Line Regulation
Load Regulation
Current Limit
VVP3 = Max(VNOM3 + 1V, 3.2V) to 5.5V
OUT3 = 10mA to 550mA
%/V
%/mA
A
I
0.55
1.35
VOUT3 ≥ 20% of VNOM3
1.6
1.85
MHz
kHz
Ω
Oscillator Frequency
V
OUT3 = 0V
540
PMOS On-Resistance
NMOS On-Resistance
SW3 Leakage Current
Power Good Threshold
Minimum On-Time
I
SW3 = -100mA
SW3 = 100mA
0.46
0.3
0.69
0.45
1
I
Ω
VVP3 = 5.5V, VSW3 = 5.5V or 0V
µA
94
60
%VNOM3
ns
ꢀ: VNOM3 refers to the nominal output voltage level for VOUT3 as defined by the Ordering Information section.
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8810QJ343, VVP1 = VVP2 = 3.6V, L = 3.3µH, CVP1 = CVP2 = 4.7μF, COUT1 = 22µF, COUT2 = 10μF, TA = 25°C, unless otherwise specified.)
REG1 Efficiency vs. Load Current
REG2 Efficiency vs. Load Current
100
80
100
80
VVSYS = 3.6V
VVSYS = 3.6V
VVSYS = 5.2V
VVSYS = 4.6V
VVSYS = 5.2V
VVSYS = 4.2V
60
60
VVSYS = 4.6V
VVSYS = 4.2V
40
40
20
0
20
VOUT1 = 3.3V
VOUT2 = 1.2V
1000
0
200
1
10
100
2
20
2000
Load Current (mA)
Load Current (mA)
OUT2 Regulation Voltage vs. Temperature
OUT1 Regulation Voltage vs. Temperature
3.318
3.315
3.312
3.309
3.306
3.303
3.300
3.297
3.294
3.291
3.288
1.212
1.208
1.204
1.200
1.196
IOUT1 = 35mA
IOUT2 = 35mA
1.192
1.188
3.285
3.282
85
-40
-20
0
20
40
60
85
-40
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
REG1 RDSON vs. VP1 Input Voltage
REG2 RDSON vs. VP2 Input Voltage
0.18
0.16
0.14
0.12
0.10
0.5
0.4
0.3
PMOS
NMOS
PMOS
0.08
0.06
0.2
0.1
0
NMOS
0.04
0.02
0
3.5
4.0
4.5
5.0
5.5
6.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VP2 Input Voltage (V)
VP1 Input Voltage (V)
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Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(ACT8810QJ343, VVP3 = 3.6V, L = 3.3µH, CVP3 = 4.7μF, COUT3 = 10μF, TA = 25°C, unless otherwise specified.)
REG3 Efficiency vs. Load Current
100
VOUT3 = 1.2V
VVSYS = 3.6V
80
VVSYS = 4.2V
VVSYS = 4.6V
60
40
20
0
10
100
1
1000
Load Current (mA)
OUT3 Regulation Voltage vs. Tempera-
1.812
1.808
1.804
1.800
1.796
IOUT3 = 35mA
1.792
1.788
-40
-20
0
20
40
60
85
Temperature (°C)
REG3 RDSON vs. VP3 Input Voltage
0.50
0.45
0.40
0.35
0.30
0.25
0.20
PMOS
NMOS
0.15
0.1
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VP3 Input Voltage (V)
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 4:
REG1 Control Register Map
DATA
ADDRESS
D7
R
D6
D5
D4
D3
D2
D1
D0
10h
11h
12h
13h
R
VSET1
R
R
R
R
R
R
R
R
R
R
R
R
R
nFLTMSK
VSET0
OK
ON
R
VRANGE
R: Read-Only bits. Default Values May Vary.
Table 5:
REG1 Control Register Bit Descriptions
ADDRESS NAME BIT ACCESS
FUNCTION
DESCRIPTION
See Table 4
10h
10h
11h
VSET1
[5:0]
[7:6]
[7:0]
R/W
R
REG1 Standby Output Voltage Selection
READ ONLY
READ ONLY
REG1 Disable
REG1 Enable
Output is not OK
Output is OK
Masked
R
0
1
0
1
0
1
12h
12h
12h
ON
OK
[0]
[1]
[2]
R/W
R
REG1 Enable
REG1 Power-OK
nFLTMSK
R/W
REG1 Output Voltage Fault Mask Option
Not Mask
12h
13h
[7:3]
[5:0]
R
READ ONLY
See Table 4
VSET0
R/W
REG1 Output Voltage Selection
REG1 Voltage Range
0
1
Min VOUT = 0.8V
Min VOUT = 1.25V
READ ONLY
13h
13h
VRANGE
[6]
[7]
R/W
R
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ACT8810
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Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS CONT’D
Table 6:
REG1/VSETx[ ] Output Voltage Setting
REG1/VSETx[5:4]
REG1/VSETx[3:0]
REG1/VRANGE[ ] = [0]ꢀ
REG1/VRANGE[ ] = [1]
00
Adjustableꢁ
0.800
0.800
0.800
0.800
0.800
0.800
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
01
10
11
00
Adjustable
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.480
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
2.025
2.050
2.075
2.100
2.125
2.150
2.175
2.200
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
3.400
3.450
3.500
3.550
3.600
3.650
3.700
3.750
3.800
3.850
3.900
3.950
4.000
4.050
4.100
4.150
4.200
4.250
4.300
4.350
4.400
ꢀ: Care must be taken when adjusting the VRANGE[ ] selection at address 13h bit-6 to avoid undesired output voltage selections. The
VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 – VOUT range 0.8V
to 2.2V, VRANGE = 1 – VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the
current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit.
ꢁ: Refer to the Output Voltage Programming section for more information.
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 7:
REG2 Control Register Map
DATA
ADDRESS
D7
R
D6
D5
D4
D3
D2
D1
D0
20h
21h
22h
23h
R
VSET1
R
R
R
R
R
R
R
R
R
R
R
R
R
nFLTMSK
VSET0
OK
ON
R
VRANGE
R: Read-Only bits. Default Values May Vary.
Table 8:
REG2 Control Register Bit Descriptions
ADDRESS NAME BIT ACCESS
FUNCTION
DESCRIPTION
See Table 7
20h
20h
21h
VSET1
[5:0]
[7:6]
[7:0]
R/W
R
REG2 Standby Output Voltage Selection
READ ONLY
READ ONLY
REG2 Disable
REG2 Enable
Output is not OK
Output is OK
Masked
R
0
1
0
1
0
1
22h
22h
22h
ON
OK
[0]
[1]
[2]
R/W
R
REG2 Enable
REG2 Power-OK
nFLTMSK
R/W
REG2 Output Voltage Fault Mask Option
Not Mask
22h
23h
[7:3]
[5:0]
R
READ ONLY
See Table 7
VSET0
R/W
REG2 Output Voltage Selection
REG2 Voltage Range
0
1
Min VOUT = 0.8V
Min VOUT = 1.25V
READ ONLY
23h
23h
VRANGE
[6]
[7]
R/W
R
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS CONT’D
Table 9:
REG2/VSETx[ ] Output Voltage Setting
REG2/VSETx[5:4]
REG2/VSETx[3:0]
REG2/VRANGE[ ] = [0]ꢀ
REG2/VRANGE[ ] = [1]
00
Adjustableꢁ
0.800
0.800
0.800
0.800
0.800
0.800
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
01
10
11
00
Adjustable
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.480
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
2.025
2.050
2.075
2.100
2.125
2.150
2.175
2.200
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
3.400
3.450
3.500
3.550
3.600
3.650
3.700
3.750
3.800
3.850
3.900
3.950
4.000
4.050
4.100
4.150
4.200
4.250
4.300
4.350
4.400
ꢀ: Care must be taken when adjusting the VRANGE[ ] selection at address 23h bit-6 to avoid undesired output voltage selections. The
VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 – VOUT range 0.8V
to 2.2V, VRANGE = 1 – VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the
current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit.
ꢁ: Refer to the Output Voltage Programming section for more information.
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 10:
REG3 Control Register Map
DATA
ADDRESS
D7
R
D6
D5
D4
D3
D2
D1
D0
30h
31h
32h
33h
R
VSET1
R
R
R
R
R
R
R
R
R
R
R
R
R
nFLTMSK
VSET0
OK
ON
R
VRANGE
R: Read-Only bits. Default Values May Vary.
W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1
Table 11:
REG3 Control Register Bit Descriptions
ADDRESS NAME
BIT ACCESS
FUNCTION
DESCRIPTION
See Table 10
READ ONLY
READ ONLY
REG3 Disable
REG3 Enable
Output is not OK
Output is OK
Masked
30h
30h
31h
VSET1
[5:0]
[7:6]
[7:0]
R/W
R
REG3 Standby Output Voltage Selection
R
0
1
0
1
0
1
32h
32h
32h
ON
OK
[0]
[1]
[2]
R/W
R
REG3 Enable
REG3 Power-OK
nFLTMSK
R/W
REG3 Output Voltage Fault Mask Option
Not Mask
32h
33h
[7:3]
[5:0]
R
READ ONLY
See Table 10
Min VOUT = 0.8V
Min VOUT = 1.25V
READ ONLY
VSET0
R/W
REG3 Output Voltage Selection
REG3 Voltage Range
0
1
33h
33h
VRANGE
[6]
[7]
R/W
R
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
REGISTER DESCRIPTIONS CONT’D
Table 12:
REG3/VSETx[ ] Output Voltage Setting
REG3/VSETx[5:4]
REG3/VSETx[3:0]
REG3/VRANGE[ ] = [0]ꢀ
REG3/VRANGE[ ] = [1]
00
Adjustableꢁ
0.800
0.800
0.800
0.800
0.800
0.800
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
01
10
11
00
Adjustable
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.480
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
2.025
2.050
2.075
2.100
2.125
2.150
2.175
2.200
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.450
2.500
2.550
2.600
2.650
2.700
2.750
2.800
2.850
2.900
2.950
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
3.400
3.450
3.500
3.550
3.600
3.650
3.700
3.750
3.800
3.850
3.900
3.950
4.000
4.050
4.100
4.150
4.200
4.250
4.300
4.350
4.400
ꢀ: Care must be taken when adjusting the VRANGE[ ] selection at address 33h bit-6 to avoid undesired output voltage selections. The
VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 – VOUT range 0.8V
to 2.2V, VRANGE = 1 – VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the
current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit.
ꢁ: Refer to the Output Voltage Programming section for more information.
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
FUNCTIONAL DESCRIPTION
General Description
1) ONx is asserted high to enable REGx,
2) REGx/ONx[ ] is set to 1 when ONx is high
In addition REG1, REG2, or REG3 may be enabled
when nPBIN is pushed low via 100kΩ resistance. It
depends on sequence is set. See the Control
Sequence section for more information.
When none of these conditions are true, REG1,
REG2 and REG3 are disabled, and each regulator’s
quiescent supply current drops to less than 1μA.
REG1, REG2, and REG3 are fixed-frequency,
current-mode, synchronous PWM step-down
converters that are capable of supplying up to 1.3A,
1.0A, and 0.55A of output current, respectively.
These regulators operate with a fixed frequency of
1.6MHz, minimizing noise in sensitive applications
and allowing the use of small external components,
and achieve peak efficiencies of up to 97%.
Each step-down DC/DC is available with a variety of
standard and custom output voltages, which may be
software-controlled by systems requiring advanced
power management functions, via the I2C interface.
Power-OK
REG1, REG2 and REG3 each feature a variety of
status bits that can be read by the system
microprocessor. If any output falls below its power-
OK threshold, typically 6% below the programmed
regulation voltage, REGx/OK[ ] is cleared to 0.
Buck Regulator PFM/PWM Operating
Modes
The buck converters offer PFM/PWM operating
modes to maximize efficiency under both light and
full load conditions. The device will automatically
transition from fixed frequency PWM mode to PFM
mode when the output current is approximately
100mA. In PFM mode, the device maintains output
voltage regulation by adjusting the switching
frequency. The device transitions into fixed
frequency PWM mode when the output current
reaches approximately 100mA.
Soft-Start
REG1, REG2 and REG3 each include matched
soft-start circuitry. When enabled, the output
voltages track the internal 80μs soft-start ramp and
both power up in a monotonic manner that is
independent of loading on either output. This
circuitry ensures that each output powers up in a
controlled manner, greatly simplifying power
sequencing design considerations.
Compensation
100% Duty Cycle Operation
REG1, REG2 and REG3 utilize current-mode control
and a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over their full
operating range. No compensation design is required;
simply follow a few simple guide lines described
below when choosing external components.
REG1, REG2 and REG3 are each capable of
operating at up to 100% duty cycle. During 100%
duty-cycle operation, the high-side power MOSFET
is held on continuously, providing
a
direct
connection from the input to the output (through the
inductor), ensuring the lowest possible dropout
voltage in battery powered applications.
Input Capacitor Selection
Synchronous Rectification
The input capacitor reduces peak currents and
noise induced upon the voltage source. A 4.7μF
ceramic capacitor for each of REG1, REG2 and
REG3 is recommended for most applications.
REG1, REG2 and REG3 each feature integrated
channel synchronous rectifiers, maximizing
efficiency and minimizing the total solution size and
cost by eliminating the need for external rectifiers.
Output Capacitor Selection
Enabling and Disabling REG1, REG2
and REG3
REG1, REG2, and REG3 are typically enabled and
disabled using the ACT8810's closed-loop
enable/disable control scheme, including the nPBIN
input. Refer to the System Startup and Shutdown
section for more information about this function.
For most applications, 22μF ceramic output
capacitors are recommended for REG1 and 10μF
ceramic output capacitors are recommended for
REG2, REG3. Although the these regulators were
designed to take advantage of the benefits of
ceramic capacitors, namely small size and very-low
ESR, low-ESR tantalum capacitors can provide
acceptable results as well.
Each regulator is enabled when the following
conditions are met:
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
FUNCTIONAL DESCRIPTION CONT’D
Figure 8:
Output Voltage Programming
Inductor Selection
REG1, REG2 and REG3 utilize current-mode control
and a proprietary internal compensation scheme to
simultaneously simplify external component
selection and optimize transient performance over
their full operating range.
OUTx
CFF
RFB1
ACT8810
FBx
REG1, REG2 and REG3 of the device were optimized
for operation with and 3.3μH inductor, although inductors
in the 2.2μH to 4.7μH range can be used.
RFB2
Finally choose CFF using the following equation:
Choose an inductor with a low DC-resistance, and
avoid inductor saturation by choosing inductors with
DC ratings that exceed the maximum output current
of the application by at least 30%.
2.2 ×10 −6
CFF
=
(2)
RFB1
Where RFB1 = 47kꢀ, use 47pF.
Output Voltage Programming
When using Adjustable Option, OUTx pins works as
FBx function.
By default, REG1, REG2 and REG3 each power up
and regulate to their default output voltage, as
defined in the Ordering Information section. Once
the system is enabled, each regulator’s output
voltage may be modified through either the I2C
interface or the Voltage Selection (VSEL) pin.
Output Voltage Selection Pin (VSEL)
ACT8810's VSEL pin provides a simple means of
alternating between two preset output voltage
settings, such as may be needed for dynamic
voltage selection (DVS). The operation of this pin is
as follows: when VSEL is driven to GA or a logic
low, the output voltages of REG1, REG2, and
REG3 are each defined by their VSET0[ ] register.
when VSEL is driven to VSYS or a logic high, the
output voltages of REG1, REG2, and REG3 are
each defined by their VSET1[ ] register.
Programming via the I2C Interface
Following startup, REG1, REG2, and REG3 may be
independently programmed to different values by
writing to the REGx/VSETx[_] and REGx/VRANGE[_]
registers via the I2C interface. To program each
regulator, first select the desired output voltage range
via the REGx/VRANGE[ ] bit. Each regulator
supports two overlapping ranges; set
REGx/VRANGE[_] to 0 for voltages below 2.245V,
set REGx/VRANGE[_] to 1 for voltages above 1.25V.
By default, each regulator's VSET0[ ] and VSET1[ ]
registers are both programmed to the same voltage,
as defined in the Ordering Information section. As a
result, toggling VSET under default conditions has
no affect. However, by re-programming one or more
regulator's VSET0[ ] and/or VSET1[ ] registers, one
can easily toggle these regulators' output voltages
between two sets of voltages, such as to implement
'normal' and 'standby' modes in a system utilizing
the ACT8810 to implement an advanced power
management architecture.
Once the desired range has been selected, program
the output to a voltage within that range by setting the
REGx/VSETx bits. For more information about the
output voltage setting options, refer to Tables 4, 7,
and 10, for REG1, REG2, and REG3, respectively.
Programming with Adjustable Option
Figure 8 shows the feedback network necessary to
set the output voltage when using the adjustable
output voltage option. Select components as
follows: Set RFB2 = 51kꢀ, then calculate RFB1 using
the following equation:
PCB Layout Considerations
High switching frequencies and large peak currents
make PC board layout an important part of step-
down DC/DC converter design. A good design
minimizes excessive EMI on the feedback paths
and voltage gradients in the ground plane, both of
which can result in instability or regulation errors.
⎛
⎞
VOUTx
VFBx
(1)
⎜
⎜
⎟
⎟
RFB1 = RFB 2
−1
⎝
⎠
Where VFBx is 0.625V when REGx × VRANGE[ ] = 0
and 1.25V when REGx × VRANGE[ ] = 1
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
STEP-DOWN DC/DC CONVERTERS
FUNCTIONAL DESCRIPTION CONT’D
close as possible to the IC, and avoiding the use of
vias if possible. The inductor, input filter capacitor, and
output filter capacitor should be connected as close
together as possible, with short, direct, and wide
traces. The ground nodes for each regulator’s power
loop should be connected at a single point in a star-
ground configuration, and this point should be
connected to the backside ground plane with multiple
vias. The output node for each regulator should be
connected to its corresponding OUTx pin through the
shortest possible route, while keeping sufficient
distance from switching nodes to prevent noise
injection. Finally, the exposed pad should be directly
connected to the backside ground plane using multiple
vias to achieve low electrical and thermal resistance.
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
LOW-DROPOUT LINEAR REGULATORS
ELECTRICAL CHARACTERISTICS (REG4)
(VINL = 3.6V, COUT4 = 1µF, TA = 25°C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range
INL UVLO Threshold
TEST CONDITIONS
MIN
2.6
TYP MAX UNIT
5.5
2.6
V
V
V
V
INL Input Rising
INL Input Falling
2.4
2.5
0.1
UVLO Hysteresis
V
ꢀ
TA = 25°C
-2% VNOM4 +2%
Output Voltage Accuracy
V
TA = -40°C to 85°C
-3%
VNOM4 +3%
Line Regulation Error
Load Regulation Error
V
INL = Max(VOUT5 + 0.5V, 3.6V) to 5.5V
OUT5 = 1mA to 360mA
0
-0.006
70
%/V
I
%/mA
f = 1kHz, IOUT4 = 360mA, COUT4 = 1µF
f = 10kHz, IOUT4 = 360mA, COUT4 = 1µF
Regulator Enabled
Power Supply Rejection Ratioꢁ
dB
60
35
Supply Current per Output
µA
mV
mA
Regulator Disabled
0
Dropout Voltage3
Output Current
Current Limitꢃ
IOUT4 = 160mA, VOUT4 > 3.1V
100
200
360
VOUT4 = 95% of regulation voltage
400
Internal Soft-Start
100
88
µs
%
Power Good Flag High Threshold VOUT4, hysteresis = -2%
Output Noise
COUT4 = 10µF, f = 10Hz to 100kHz
40
µVRMS
µF
Stable COUT4 Range
1
20
Discharge Resistor in Shutdown LDO Disabled, DIS4[ ] = [1]
1000
ꢀ
ꢀ: VNOM4 refers to the nominal output voltage level for VOUT4 as defined by the Ordering Information section.
ꢁ: PSRR is lower with VSET < 1.25V
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage at 1V differential voltage (for 2.8V output voltage or higher)
ꢃ: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Un-
der heavy overload conditions the output current limit folds back by 40% (typ)
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
LOW-DROPOUT LINEAR REGULATORS
ELECTRICAL CHARACTERISTICS (REG5)
(VINL = 3.6V, COUT5 = 1µF, TA = 25°C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range
INL UVLO Threshold
TEST CONDITIONS
MIN
2.6
TYP MAX UNIT
5.5
2.6
V
V
V
V
INL Input Rising
INL Input Falling
2.4
2.5
0.1
UVLO Hysteresis
V
ꢀ
TA = 25°C
-2%
-3%
VNOM5
+2%
+3%
Output Voltage Accuracy
V
TA = -40°C to 85°C
VNOM5
0
Line Regulation Error
Load Regulation Error
V
INL = Max(VOUT5 + 0.5V, 3.6V) to 5.5V
OUT5 = 1mA to 360mA
%/V
I
-0.006
70
%/mA
f = 1kHz, IOUT5 = 360mA, COUT5 = 1µF
f = 10kHz, IOUT5 = 360mA, COUT5 = 1µF
Regulator Enabled
Power Supply Rejection Ratioꢁ
dB
µA
60
35
Supply Current per Output
Regulator Disabled
0
Dropout Voltage3
Output Current
Current Limitꢃ
IOUT5 = 160mA, VOUT5 > 3.1V
100
200
360
mV
mA
mA
µs
VOUT5 = 95% of regulation voltage
400
1
Internal Soft-Start
Output Noise
100
40
COUT5 = 10µF, f = 10Hz to 100kHz
µVRMS
µF
Stable COUT5 Range
20
Discharge Resistor in Shutdown LDO Disabled, DIS5[ ] = [1]
1000
ꢀ
ꢀ: VNOM5 refers to the nominal output voltage level for VOUT5 as defined by the Ordering Information section.
ꢁ: PSRR is lower with VSET < 1.25V
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage at 1V differential voltage (for 2.8V output voltage or higher)
ꢃ: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Un-
der heavy overload conditions the output current limit folds back by 40% (typ)
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
LOW-DROPOUT LINEAR REGULATORS
TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8810QJ343, VVSYS = 5V, TA = 25°C, unless otherwise specified.)
Output Regulation Voltage vs. Load Current
Dropout Voltage vs. Output Current
225
200
175
150
125
100
1.5
1.0
0.5
REG4, REG5
0.0
-0.5
-1.0
-1.5
75
50
3.1V
3.3V
3.6V
25
0
0
50
100
150
200
250
300
360
0
40
80 120 160 200 240 280 320 360
Output Current (mA)
Load Current (mA)
LDO Output Voltage Noise
Output Voltage Deviation vs. Temperature
2.00
1.50
ILOAD = 0mA
CH1
1.00
0.50
0.00
-0.5
CREF = 10nF
-15
10
35
60
85
-40
CH1: VOUTx, 200µV/div (AC COUPLED)
TIME: 200ms/div
Temperature (°C)
Region of Stable COUT ESR vs. Output Current
1
0.1
Stable ESR
0.01
0
50
100
150
200
250
300
360
Output Current (mA)
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
LOW-DROPOUT LINEAR REGULATORS
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 13:
REG45 Control Register Map
DATA
ADDRESS
D7
DIS4
DIS5
R
D6
R
D5
ON4
ON5
R
D4
D3
D2
VSET4
VSET5
R
D1
D0
40h
41h
43h
R
R
R
R
nFLTMSK
OK
R: Read-Only bits. Default Values May Vary.
Table 14:
REG45 Control Register Bit Descriptions
ADDRESS
NAME
BIT ACCESS
FUNCTION
DESCRIPTION
REG4 Output Voltage
Selection
40h
VSET4
[4:0]
R/W
See Table 15
0
1
REG4 Disable
REG4 Enable
40h
40h
40h
ON4
[5]
[6]
[7]
R/W
R
REG4 Enable
READ ONLY
0
1
Discharge Disable
Discharge Enable
DIS4
VSET5
ON5
R/W
REG4 Discharge Enable
REG5 Output Voltage
Selection
41h
[4:0]
R/W
See Table 15
0
1
REG5 Disable
REG5 Enable
READ ONLY
Discharge Disable
Discharge Enable
Output is not OK
Output is OK
Masked
41h
41h
41h
[5]
[6]
[7]
R/W
R
REG5 Enable
0
1
0
1
0
1
DIS5
OK
R/W
REG5 Discharge Enable
REG4 Power-OK
43h
[0]
R
REG4 Output Voltage Fault
Mask Option
nFLTMSK
[1]
R/W
R
43h
43h
Not Mask
[7:2]
READ ONLY
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
LOW-DROPOUT LINEAR REGULATORS
REGISTER DESCRIPTIONS CONT’D
Table 15:
REG45/VSETx[ ] Output Voltage Setting
REG45CFG/VSETx[4:3]
REG45CFG/VSETx[2:0]
00
01
10
11
000
001
010
011
100
101
110
111
0.90
1.00
1.10
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.70
1.75
1.80
1.85
1.90
2.00
2.10
2.20
2.40
2.50
2.60
2.70
2.75
2.80
2.85
2.90
3.00
3.10
3.20
3.30
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
LOW-DROPOUT LINEAR REGULATORS
FUNCTIONAL DESCRIPTION
which filters noise from the reference, providing a
low noise voltage reference to the LDOs. Bypass
General Description
REG4 and REG5 are low-noise, low-dropout linear
regulators (LDOs) that are optimized for low noise
and high-PSRR operation, achieving more than
60dB PSRR at frequencies up to 10kHz.
REFBP to GA with a 0.01μF ceramic capacitor.
Optional LDO Output Discharge
Each of the ACT8810’s LDOs features an optional,
independent output voltage discharge feature.
When this feature is enabled, the LDO output is
discharged to ground through a 1kꢀ resistance
when the LDO is shutdown. This feature may be
enabled or disabled via the I2C interface by writing
to the REG45CFG/DISx[ ] bits.
LDO Output Voltage Programming
All LDOs feature independently-programmable
output voltages that are set via the I2C serial
interface, increasing the ACT8810’s flexibility while
reducing total solution size and cost. Set the output
voltage by writing to the REG45CFG/VSETx[ ]
registers.
Output Capacitor Selection
REG4 and REG5 each require only a small ceramic
capacitor for stability. For best performance, each
output capacitor should be connected directly
between the OUTx and GA pins as possible, with a
short and direct connection. To ensure best
performance for the device, the output capacitor
should have a minimum capacitance of 1μF, and
ESR value between 10mꢀ and 200mꢀ. High quality
ceramic capacitors such as X7R and X5R dielectric
types are strongly recommended.
Output Current Capability
REG4 and REG5 each supply an output current of
360mA. Excellent performance is achieved over this
load current range.
Output Current Limit
In order to ensure safe operation under over-load
conditions, each LDO features current-limit circuitry
with current fold-back. The current-limit circuitry
limits the current that can be drawn from the output,
providing protection in over-load conditions. For
additional protection under extreme over current
conditions, current-fold-back protection reduces the
current-limit by approximately 40% under extreme
overload conditions.
PCB Layout Considerations
The ACT8810’s LDOs provide good DC, AC, and
noise performance over a wide range of operating
conditions, and are relatively insensitive to layout
considerations. When designing a PCB, however,
careful layout is necessary to prevent other circuitry
from degrading LDO performance. A good design
places input and output capacitors as close to the
LDO inputs and output as possible, and utilizes a
star-ground configuration for all regulators to
prevent noise-coupling through ground. Output
traces should be routed to avoid close proximity to
noisy nodes, particularly the SW nodes of the
DC/DCs. REFBP is a filtered reference noise, and
internally has a direct connection to the linear
regulator controller. Any noise injected onto REFBP
will directly affect the outputs of the linear
regulators, and therefore special care should be
taken to ensure that no noise is injected to the
outputs via REFBP. As with the LDO output
capacitors, the REFBP bypass capacitor should be
placed as close to the IC as possible, with short,
direct connections to the star-ground. Avoid the use
of vias whenever possible. Noisy nodes, such as
from the DC/DCs, should be routed as far away
from REFBP as possible.
Enabling and Disabling the LDOs
All LDOs feature independent enable/disable
control via the I2C serial interface. Independently
enable or disable each output by writing to the
appropriate REG45CFG/ONx[ ] bit.
In addition REG4 or REG5 may be enable when
nPBIN is pushed low via 100kꢀ resistance. It
depends on sequence is set. See the Control
Sequence section for more information.
Power-OK
REG4 features power-OK status bit that can be
read by the system microprocessor via the I2C
interface. If an output voltage is lower than the
power-OK threshold, typically 12% below the
programmed regulation voltage, the corresponding
REG45CFG/OK[ ] will clear to 0.
Reference Bypass Pin
The ACT8810 contains a reference bypass pin
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
RTC LOW-DROPOUT LINEAR REGULATOR
ELECTRICAL CHARACTERISTICS (REG6)
(TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
2.6
TYP
MAX UNIT
Input Supply Range
5.5
V
ꢀ
TA = 25°C
TA = -40°C to 85°C
INL = VOUT6 + 0.5V to VINL = 5.5V
OUT6 = 0mA to 30mA
-2%
-3%
VNOM6
VNOM6
0.1
+2%
+3%
Output Voltage Accuracy
V
Line Regulation Error
Load Regulation Error
Input Supply Current
Dropout Voltageꢁ
Output Current
V
%/V
%/mA
µA
I
-0.01
6
ON1 = ON2 = ON3 = GA
IOUT6 = 10mA
12
70
30
35
mV
mA
Current Limit3
VOUT6 = 95% of regulation voltage
45
1
mA
Stable COUT6 Range
20
µF
ꢀ: VNOM6 refers to the nominal output voltage level for VOUT6 as defined by the Ordering Information section.
ꢁ: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage at 1V differential voltage (for 2.8V output voltage or higher)
3: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
RTC LOW-DROPOUT LINEAR REGULATOR
REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 16:
REG6 Control Register Map
DATA
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
42h
R
R
R
VSET6
R: Read-Only bits. Default Values May Vary.
Table 17:
REG6 Control Register Bit Descriptions
ADDRESS
42h
NAME
BIT ACCESS
FUNCTION
DESCRIPTION
See Table 18
READ ONLY
REG6 Output Voltage
Selection
VSET6
[4:0]
[7:5]
R/W
R
42h
Table 18:
REG6/VSETx[ ] Output Voltage Setting
REG6CFG/VSETx[4:3]
REG6CFG/VSETx[2:0]
00
01
10
11
000
001
010
011
100
101
110
111
0.90
1.00
1.10
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.70
1.75
1.80
1.85
1.90
2.00
2.10
2.20
2.40
2.50
2.60
2.70
2.75
2.80
2.85
2.90
3.00
3.10
3.20
3.30
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
RTC LOW-DROPOUT LINEAR REGULATOR
FUNCTIONAL DESCRIPTION
Backup Battery Charging
General Description
REG6 features a constant current-limit, which
REG6 is an always-on, low-dropout linear regulator
(LDO) that is optimized for RTC and backup-battery
applications. REG6 features low-quiescent supply
current, current-limit protection, and reverse-current
protection, and is ideally suited for always-on power
supply applications, such as for a real-time clock, or
as a backup-battery or super-cap charger.
protects the IC under output short-circuit conditions
as well as provides a constant charge current, when
operating as a backup battery charger.
As shown in Figure 10, REG6 features a CC/CV
output characteristic, regulating its output voltage
for load currents up to 30mA, and regulating output
current when the load exceeds (typically) 60mA.
Output Voltage
Figure 10:
By default, REG6's output voltage is as defined in
the Ordering Information section. However, this
voltage may be programmed by writing to the
REG6CFG/VSETx[ ] register via the I2C interface.
REG6 Output Voltage
REG6 Output Voltage vs. Load Current
4
Reverse-Current Protection
REG6 features internal circuitry that limits the
reverse supply current to less than 1µA when the
input voltage falls below the output voltage, as can
be encountered in backup-battery charging
applications. REG6's internal circuitry monitors the
input and the output, and disconnects internal
circuitry and parasitic diodes when the input voltage
falls below the output voltage, greatly minimizing
backup battery discharge.
3
2
Constant Voltage Region
Constant Current Region
1
0
0
20
40
60
80
100
Typical Application
Load Current (mA)
Voltage Regulators
REG6 is ideally suited for always-on voltage-
regulation applications, such as for real-time clock
and memory keep-alive applications. This regulator
requires only a small ceramic capacitor with a
minimum capacitance of 1μF for stability. For best
performance, the output capacitor should be
connected directly between the output and GA, with
a short and direct connection.
Figure 9:
Typical Application of RTC LDO
OUT6
ACT8810
RTC
Supper cap or
Back-up battery
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
ELECTRICAL CHARACTERISTICS
(VCHG_IN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
ActivePath
TEST CONDITIONS
MIN
TYP MAX UNIT
CHG_IN Operating Voltage Range
CHG_IN UVLO Threshold
CHG_IN UVLO Hysteresis
CHG_IN OVP Threshold
4.35
3.6
12
V
V
CHG_IN Voltage Rising
CHG_IN Voltage Falling
CHG_IN Voltage Rising
CHG_IN Voltage Falling
VCHG_IN < VUVLO
3.8
0.8
6.8
350
20
4.0
V
V
CHG_IN OVP Hysteresis
mV
µA
µA
VCHG_IN < VBAT + 120mV , VCHG_IN > VUVLO
50
120
200
CHG_IN Supply Current
V
CHG_IN > VBAT + 120mV , VCHG_IN > VUVLO
1.8
mA
Charger disabled, ISYS = 0mA
IVSYS = 100mA
CHG_IN to VSYS On-Resistance
CHG_IN to VSYS Current Limit
0.4
2
0.6
3
ꢀ
ACIN = VSYS
1.5
85
A
ACIN = GA, CHGLEV = GA
ACIN = GA, CHGLEV = VSYS
95
450
105
500
mA
400
VSYS AND DCCC REGULATION
VSYS Regulated Voltage
IVSYS = 10mA
4.4
92
4.6
4.8
V
DCCC Pull-Up Current
VCHG_IN > VBAT + 120mV, Hysteresis = 50mV
100
108
µA
nSTAT OUTPUT
nSTAT Sink current
VnSTAT = 2V
InSTAT = 1mA
3
5
7
0.4
1
mA
V
nSTAT Output Low Voltage
nSTAT Leakage Current
VnSTAT = 4.2V
µA
ACIN AND CHGLEV INPUTS
CHGLEV Logic High Input Voltage
CHGLEV Logic Low Input Voltage
CHGLEV Leakage Current
ACIN Logic High Input Voltage
ACIN Logic Low Input Voltage
ACIN Leakage Current
1.4
1.4
V
V
0.4
1
V
V
CHGLEV = 4.2V
µA
V
0.4
1
V
ACIN = 4.2V
µA
TEMPERATURE SENSE COMPARATOR
TH Pull-Up Current
VCHG_IN > VBAT + 120mV, Hysteresis = 50mV
92
100
108
µA
V
VTH Upper Temperature Voltage
Hot Detect NTC Thermistor
0.485 0.500 0.525
Threshold (VTHH
)
VTH Lower Temperature Voltage
Cold Detect NTC Thermistor
Upper and Lower
2.47
2.52
30
2.57
V
Threshold (VTHL
VTH Hysteresis
)
mV
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
ELECTRICAL CHARACTERISTICS CONT’D
(VCHG_IN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER
CHARGER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BAT Reverse Leakage Current
BAT to VSYS On-Resistance
VCHG_IN = 0V, VBAT = 4.2V, IVSYS = 0mA
5
µA
80
mꢀ
Fast Charge
1.02
0.12
4.2
ISET Pin Voltage
V
Precondition
TA = -20°C to 70°C
TA = -40°C to 85°C
4.179
4.170
4.221
V
Battery Regulation Voltage
4.230
ACIN = VSYS, CHGLEV = VSYS -10%
ISET1
+10%
ACIN = VSYS, CHGLEV = GA
-16% 50%ISET +16%
Smallest
-10% (450mA or +10%
ISET)
ACIN = GA, CHGLEV = VSYS
Charge Current
VBAT = 3.5V
mA
Smallest
-10% (90mA or +10%
ISET)
ACIN = GA, CHGLEV = GA
ACIN = VSYS, CHGLEV = VSYS
ACIN = VSYS, CHGLEV = GA
ACIN = GA, CHGLEV = VSYS
12%ISET
12%ISET
12%ISET
Precondition Charge Current
Precondition Threshold Voltage
VBAT = 2.5V
mA
Smallest
(90mA or
12%ISET)
ACIN = GA, CHGLEV = GA
VBAT Voltage Rising
2.75
2.85
100
2.95
V
Precondition Threshold Hysteresis VBAT Voltage Falling
mV
ACIN = VSYS, CHGLEV = VSYS -10% 10%ISET +10%
ACIN = VSYS, CHGLEV = GA
ACIN = GA, CHGLEV = VSYS
ACIN = GA, CHGLEV = GA
-10% 10%ISET +10%
End-of-Charge Current Threshold VBAT = 4.2V
mA
-10%
-10%
150
5%ISET +10%
5%ISET +10%
Charge Restart Threshold
BTR Scale Factor
VSET - VBAT, VBAT Falling
170
0.24
1
190
mV
s/ꢀ
hr
Precondition Safety Timer
Fast Charge Safety Timer
THERMAL REGULATION
Thermal Regulation Threshold
RBTR = 47kꢀ, tPRCHG = 0.24 × RBTR(ꢀ)/180(min)
RBTR = 47kꢀ, tCHG = 0.24 × RBTR(ꢀ)/60(min)
3
hr
100
145
°C
ꢀ: ISET = 640 × (1V/RISET
)
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
TYPICAL PERFORMANCE CHARACTERISTICS
(VCHG_IN = 5V, RDCCC = 20k, RISET = 680ꢀ, TA = 25°C, unless otherwise specified.)
SYS Output Voltage vs. DC Voltage
SYS Voltage vs. SYS Current
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
4.25
4.15
4.05
3.95
3.85
3.75
ISYS = 10mA
12
VBAT = 4.2V
0
2
4
6
8
10
14
0
1000
2000
3000
CHG_IN Voltage (V)
SYS Current (mA)
Charger Current vs. Battery Voltage (USB Mode)
500
Charger Current vs. Battery Voltage (USB Mode)
100
450
Battery Voltage Falling
400
80
350
Battery Voltage Rising
VBAT Falling
300
60
250
200
150
VBAT Rising
40
20
100
CHG_IN = 5V
CHG_IN = 5V
ISYS = 0mA
500mA USB
I
SYS = 0mA
50
0
100mA USB
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Battery Voltage (V)
0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Battery Voltage (V)
Fast Charge Current vs. Ambient Temperature
Charger Current vs. Battery Voltage (AC Mode)
1200
1200
ISYS = 0mA
1000
800
600
400
200
0
1000
800
600
400
200
0
Battery Voltage Falling
ACIN, CHGLEV = 11
ACIN, CHGLEV = 10
Battery Voltage Rising
ACIN, CHGLEV = 01
ACIN, CHGLEV = 00
-40 -20
0
20
40
60
80 100 120 140
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Ambient Temperature (°C)
Battery Voltage (V)
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(VCHG_IN = 5V, RDCCC = 20k, RISET = 680ꢀ, TA = 25°C, unless otherwise specified.)
VAC Applied, CHGLEV = LOW
VAC Applied, CHGLEV = HIGH
CH1
CH2
CH1
CH2
CH3
CH3
450mA
100mA
CH4
CH4
CH1: VUSB, 2.00V/div
CH1: VUSB, 2.00V/div
CH2: VCHG_IN, 2.00V/div
CH3: IBAT, 500mA/div
CH4: VVAC, 2.00V/div
TIME: 400µs/div
CH2: VCHG_IN, 2.00V/div
CH3: IBAT, 500mA/div
CH4: VVAC, 2.00V/div
TIME: 400µs/div
VAC Removed, CHGLEV = HIGH
VAC Removed, CHGLEV = LOW
CH1
CH2
CH1
CH2
CH3
CH3
450mA
100mA
CH4
CH4
CH1: VUSB, 2.00V/div
CH2: VCHG_IN, 2.00V/div
CH3: IBAT, 500mA/div
CH4: VVAC, 2.00V/div
TIME: 400µs/div
CH1: VUSB, 2.00V/div
CH2: VCHG_IN, 2.00V/div
CH3: IBAT, 500mA/div
CH4: VVAC, 2.00V/div
TIME: 400µs/div
Battery Leakage Current vs. Battery Voltage
10
8
6
4
2
0
No CHG_IN
CHGLEV = 0
0
1
2
3
4
5
Battery Voltage (V)
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
FUNCTIONAL DESCRIPTION
System Configuration Optimization
General Description
ActivePath circuitry automatically detects the state
of the input supply, the battery, and the system, and
automatically reconfigures itself to optimize the
power system. If the input supply is present,
ActivePath powers the system in parallel with
charging the battery, so that system power and
charge current can be independently managed to
satisfy all system power requirements. This allows
the battery to charge as quickly as possible, while
ensuring that the total system current does not
exceed the capability of the input supply. If the input
supply is not present, however, then ActivePath
automatically configures the system to draw power
from the battery. Finally, if the input is present and
the system current requirement exceeds the
capability of the input supply, such as under
momentary peak-power consumption conditions,
ActivePath automatically configures itself for
maximum power capability by drawing system
power from both the battery and the input supply.
The ACT8810 incorporates Active-Semi's patent-
pending ActivePath architecture. ActivePath is a
complete battery-charging and system power-
management solution for portable hand-held
equipment. This circuitry performs a variety of
advanced battery-management functions, including
automatic selection of the best available input
supply, current-management to ensure system
power availability, and a complete, high-accuracy
(±0.5%), thermally regulated, full-featured single-
cell linear Li+ charger with an integrated 12V power
MOSFET.
ActivePath Architecture
Active-semi's patent-pending ActivePath
architecture performs three important functions:
1) Input Protection,
2) System Configuration Optimization, and
3) Battery-Management
Battery Management
ActivePath includes a full-featured battery charger
for single-cell Li-based batteries. This charger is a
full-featured, intelligent, linear-mode, single-cell
charger for Lithium-based cells, and was designed
specifically to provide a complete charging solution
with minimum system design effort.
Input Protection
At the input of the ACT8810's ActivePath circuit is
an internal, low-dropout linear regulator (LDO) that
regulates the system voltage (VSYS). This LDO
features a 12V power MOSFET, allowing the
ActivePath system to withstand input voltages of up
to 12V, and additionally includes a variety of other
protection features, including current limit protection
and input over-voltage protection.
The core of the ActivePath's charger is a CC/CV
(Constant-Current/Constant-Voltage), linear-mode
charge controller. This controller incorporates
current and voltage sense circuitry, an internal
80mꢀ power MOSFET, a full-featured state-
machine that implements charge control and safety
features, and circuitry that eliminates the reverse-
blocking diode required by conventional charger
designs.
The ActivePath circuitry provides a very simple
means of implementing a solution that safely
operates within the current-capability limitations of a
USB port while taking advantage of the high output-
current capability of an AC adapter, when available.
ActivePath limits the total current drawn from the
input supply to a value set by the ACIN input; when
ACIN is driven to a logic-low ActivePath operates in
“USB Mode” and limits the current to either 500mA
(when CHGLEV is driven to a logic-high) or to
100mA (when CHGLEV is driven to a logic-low),
and when ACIN is driven to a logic-high ActivePath
operates in “AC-Mode” and limits the input current
to 2A. In either case, ActivePath's DCCC circuitry,
described below, allows the input overload
protection to be adjusted to accommodate a wide
range of input supplies.
This charger also features thermal-regulation
circuitry that protects it against excessive junction
temperature, allowing the fastest possible charging
times, as well as proprietary input protection
circuitry that makes the charger robust against input
voltage transients that can damage other chargers.
The charge termination voltage is highly accurate
(±0.5%), and features a selection of charge safety
timeout periods that protect the system from
operation with damaged cells. Other features
include pin-programmable fast-charge current and
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I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
FUNCTIONAL DESCRIPTION CONT’D
two current-limited nSTAT outputs that can directly
drive LED indicators or provide a logic-level status
When ACIN is driven to a logic-low, the ActivePath
circuitry operates in “USB-Mode”, which enforces a
maximum charge current setting of 500mA, if
CHGLEV is driven to a logic-high, or 100mA, if
CHGLEV is driven to a logic-low.
signal to the host microprocessor.
Dynamic Charge Current Control (DCCC)
The ACT8810's charge current settings are
summarized in the table below:
The ACT8810's ActivePath charger features
Dynamic Charge Current Control (DCCC) circuitry,
which continuously monitors the input supply and
prevents input overload conditions by dynamically
adjusting the charge current to keep the input voltage
from dropping below the DCCC voltage threshold.
Table 19:
ACIN and CHGLEV Inputs Table
CHARGE
CURRENT
ICHG (mA)
PRECONDITION
CHARGE CURRENT
ICHG (mA)
ACIN CHGLEV
By default, the DCCC voltage threshold is set to
4.4V, but it may also be programmed by connecting
a resistor from DCCC to GA, where the resistor has
value given by the following equation:
90mA or ISET
(Smallest one)
90mA or 12%ISET
(Smallest one)
0
0
0
1
VDCCC = 2 × (IDCCC × RDCCC
)
(2)
450mA or ISET
(Smallest one)
12% × ISET
Where RDCCC is the value of the external resistor,
and IDCCC is the value of the current sourced from
DCCC, typically 100μA.
1
1
0
1
50% × ISET
ISET
12% × ISET
12% × ISET
Charger Current Programming
Note that the actual charging current may be limited
to a current that is lower than the programmed fast
charge current due to the ACT8810’s internal
thermal regulation loop. See the Thermal
Regulation and Protection section for more
information.
The ACT8810's ActivePath charger features a
flexible charge current-programming scheme that
combines the convenience of internal charge
current programming with the flexibility of resistor
based charge current programming. Current limits
and charge current programming are managed as a
function of the ACIN and CHGLEV pins, in
combination with RISET, the resistance connected to
the ISET pin.
Battery Temperature Monitoring
The ACT8810 continuously monitors the
temperature of the battery pack by sensing the
resistance of its thermistor, and suspends charging
if the temperature of the battery pack exceeds the
safety limits.
ACIN and CHGLEV Inputs
ACIN is a logic input that configures the current-limit
of ActivePath's linear regulator as well as that of the
battery charger. ACIN features a precise 1.25V
logic threshold, so that the input voltage detection
threshold may be adjusted with a simple resistive
voltage divider. This input also allows a simple, low-
cost dual-input charger switch to be implemented
with just a few, low-cost components.
In a typical application, shown in Figure 11, the TH
pin is connected to the battery pack's thermistor
input. The ACT8810 injects a 100µA current out of the
TH pin into the thermistor, so that the thermistor
resistance is monitored by comparing the voltage at
TH to the internal VTHH and VTHL thresholds of 0.5V
and 2.5V, respectively. When VTH > VTHL or VTH < VTHH
charging and the charge timers are suspended. When
VTH returns to the normal range, charging and the
charge timers resume.
When ACIN is driven to a logic high, the ActivePath
operates in “AC-Mode” and the charger charges at
the current programmed by RISET
,
ICHG = 1V/RISET × KISET
(3)
The net resistance from TH to G required to cross
the threshold is given by:
where KISET = 640 when CHGLEV is driven to a
logic high, and K = 320 when CHGLEV is driven to
a logic low.
100µA × RNOM × kHOT = 0.5V → RNOM × kHOT = 5kꢀ
100µA × RNOM × kCOLD = 2.5V → RNOM × kCOLD = 25kꢀ
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Copyright © 2009 Active-Semi, Inc.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
FUNCTIONAL DESCRIPTION CONT’D
where RNOM is the nominal thermistor resistance at
room temperature, and kHOT and kCOLD are the ratios
of the thermistor's resistance at the desired hot and
cold thresholds, respectively.
Simple Solution
The ACT8810 was designed to accommodate most
requirements with very little design effort, but also
provides flexibility when additional control over a
design is required. Initial thermistor selection is
accomplished by choosing one that best meets the
following requirements:
Figure 11:
Simple Configuration
R
R
NOM = 5kꢀ/kHOT, and
NOM = 25kꢀ/kCOLD
ACT8810
100µA
where kHOT and kCOLD for a given thermistor can be
found on its characteristic tables.
+
VTHH
Li+ Battery
+
Pack
Taking a 0°C to 40°C application using a "curve 2"
NTC for this example, from the characteristic tables
one finds that kHOT and kCOLD are 0.5758 and 2.816,
respectively, and the RNOM that most closely
satisfies these requirements is therefore around
8.8kꢀ. Selecting 10kꢀ as the nearest standard
value, calculate kCOLD and kHOT as:
–
TH
+
NTC
–
VTHL
–
k
COLD = VTHL/(ITH × RNOM) = 2.5V/(100µA × 10kꢀ) = 2.5
HOT = VTHH/(ITH × RNOM) = 0.5V/(100µA × 10kꢀ) = 0.5
Design Procedure
k
When designing with thermistors it is important to
keep in mind that their nonlinear behavior typically
allows one to directly control no more than one
threshold at a time. As a result, the design
procedure can change depending on which
threshold is most critical for a given application.
Identifying these values on the curve
2
characteristic tables indicates that the resulting
operating temperature range is 2°C to 44°C, vs. the
design goal of 0°C to 40°C. This example
demonstrates that one can satisfy common
operating temperature ranges with very little design
effort.
Most application requirements can be solved using
one of three cases,
Fix VTHH
1) Simple solution
For demonstration purposes, supposing that we
had selected the next closest standard thermistor
value of 6.8kꢀ in the example above, we would
have obtained the following results:
2) Fix VTHH, accept the resulting VTHL
3) Fix VTHL, accept the resulting VTHH
The ACT8810 was designed to achieve an
operating temperature range that is suitable for
most applications with very little design effort. The
simple solution is often found to provide reasonable
results and should always be used first, then the
design procedure may proceed to one of the other
solutions if necessary.
k
COLD = VTHL/(ITH × RNOM) = 2.5V/(100µA × 6.8kꢀ) = 3.67
kHOT = VTHH/(ITH × RNOM) = 0.5V/(100µA × 6.8kꢀ) = 0.74
which, according to the characteristic tables would
have resulted in an operating temperature range of
-6°C to 33°C vs. the design goal of 0°C to 40°C.
In this case, one can add resistance in series with
the thermistor to shift the range upwards, using the
following equation:
In each design example, we refer to the Vishay
NTHS series of NTCs, and more specifically those
which follow a "curve 2" characteristic. For more
information on these NTCs, as well as access to the
resistance/temperature characteristic tables referred
to in the example, please refer to the Vishay
website at http://www.vishay.com/thermistors.
(VTHH/ITH) = kHOT(@40°C) × RNOM + R
R = (VTHH/ITH) - kHOT(@40°C) × RNOM
R = (2.5V/100µA) - 0.5758 × 6.8kꢀ
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
FUNCTIONAL DESCRIPTION CONT’D
Finally,
at low temperatures by connecting a resistor in
parallel with ITH. The desired resistance can be
found using the following equation:
R = 5kꢀ - 3.9kꢀ = 1.1kꢀ
This result shows that adding 1.1kꢀ in series with
the thermistor sets the net resistance from TH to G
to be 0.5V at 40°C, satisfying VTHH at the correct
temperature. Adding this resistance, however, also
impacts the lower temperature limit as follows:
(ITH + (VCHG_IN - VTHL)/R) × kCOLD(@0°C) × RNOM = VTHL
Rearranging yields
R = (VCHG_IN - VTHL)/(VTHL/(kCOLD(@0°C) × RNOM) - ITH)
R = (5V - 2.5V)/(2.5V/(2.816 × 6.8kꢀ) - 100µA)
R = 82kꢀ
VTHL/ITH = kCOLD(@TC) × RNOM + R
k
COLD(@TC) = (VTHL/ITH) - R)/RNOM
Finally,
COLD(@TC) = (25kꢀ - 1.1kꢀ)/6.8kꢀ = 3.51
Adding 82kꢀ in parallel with the current source
increases the net
current flowing into the
k
thermistor, thus increasing the voltage at TH.
Adding this resistance, however, also impacts the
upper temperature limit:
Reviewing the characteristic curves, the lower
threshold is found to move to -5°C, a change of only
1°C. As a result, the system satisfies the upper
threshold of 40°C with an operating temperature
range of -5°C to 40°C, vs. our design target of 0°C
to 40°C. It is informative to highlight that due to the
NTC behavior of the thermistor, the relative impact
on the lower threshold is significantly smaller than
the impact on the upper threshold.
V
THH = (ITH + (VCHG_IN - VTHH)/R) × kHOT(@40°C) × RNOM
Rearranging yields,
HOT(@TC) = VTHH/(RNOM × (ITH + (VCHG_IN - VTHH)/R))
HOT(@TC) = 0.5V/(6.8kꢀ × (100µA + (5V - 0.5V)/82kꢀ))
k
k
= 0.4748
Reviewing the characteristic curves, the upper
threshold is found to move to 45°C, a change of
about 14°C. Adding the parallel resistance has
allowed us to achieve our desired lower threshold of
0°C with an operating temperature range of 0°C to
45°C, vs. our design target of 0°C to 40°C.
Fix VTHL
Following the same example as above, the
"unadjusted" results yield an operating temperature
range of -6°C to 33°C vs. the design goal of 0°C to
40°C. In applications that favor VTHL over VTHH
,
however, one can control the voltage present at TH
Figure 12:
Figure 13:
Fix VTHL Configuration
Fix VTHH Configuration
ACT8810
CHG_IN
100µA
ACT8810
100µA
+
+
VTHH
VTHH
Li+ Battery
Pack
Li+ Battery
+
+
–
R
Pack
R
–
TH
TH
+
+
–
NTC
NTC
–
VTHL
VTHL
–
–
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
Copyright © 2009 Active-Semi, Inc.
I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
FUNCTIONAL DESCRIPTION CONT’D
Table 20:
Thermal Regulation
Charging Status Indication Table
The ACT8810's ActivePath charger features an
internal thermal regulation loop that reduces the
charging current as necessary to ensure that the
die temperature does not rise beyond the thermal
regulation threshold of 110°C. This feature protects
the against excessive junction temperature and
makes the device more accommodating to
aggressive thermal designs. Note, however, that
attention to good thermal designs is required to
achieve the fastest possible charge time by
maximizing charge current.
STATE
Charging
nSTAT
ON
Discharging
Charging Complete
Input Floating
Fault
OFF
OFF
OFF
OFF
In order to account for the reduced charge current
resulting from operation in thermal regulation mode,
the charge timeout periods are extended
proportionally to the reduction in charge current.
Input Supply Detection
The ACT8810's ActivePath charger is capable of
withstanding voltages of up to 12V, protecting the
system from fault conditions such as input voltage
transients or application of an incorrect input
supply. Although the ACT8810 can withstand a
wide range of input voltages, valid input voltages for
charging must be greater than the under-voltage
lockout voltage (UVLO) and the over-voltage
protection (OVP) thresholds, as described below.
Charging Safety Timers
The ACT8810 features a safety timer that is
programmable via an external resistor (RBTR
)
connected from BTR to GA. The timeout period is
calculated as a function of this resistor by the
following equation:
Under Voltage Lock Output (UVLO)
tCHG = KBTR × RBTR, where KBTR = 0.24s/ꢀ.
Whenever the input voltage applied to CHG_IN falls
below 3.0V (typ), an input under-voltage condition is
detected and the charger is disabled. Once an input
under-voltage condition is detected, the input must
exceed the under-voltage threshold by at least
800mV for charging to resume.
If the timeout period expires prior to charge
termination, the charger is disabled and the nSTAT
pin signal a fault condition. If the ACT8810 detects
that the charger remains in precondition for longer
than the precondition time out period (which
determined as tCHG/3), the ACT8810 turns off the
charger and generate a FAULT to ensure prevent
charging a bad cell.
Over Voltage Protection (OVP)
If the charger detects that the voltage applied to
CHG_IN exceeds 6.8V (typ), an over-voltage
condition is detected and the charger is disabled.
Once an input over-voltage condition is detected,
the input must fall below the OVP threshold by at
least 350mV for charging to resume.
Charging Status Indication
The ACT8810 provides one charge-status output,
nSTAT which indicates charge status as defined in
Table 20. nSTAT is open-drain output with internal
5mA current limits, which sinks current when
asserted and are high-Z otherwise, and is capable
of directly driving LED without the need of current-
limiting resistor or other external circuitry. To drive
an LED, simply connect the LED between nSTAT
pin and an appropriate supply (typically VSYS). For
a logic level indication, simply connect a resistor
from nSTAT to a appropriate voltage supply.
Reverse Leakage Current
The ACT8810's ActivePath charger includes
internal circuitry that eliminates the need for
blocking diodes, reducing solution size and cost as
well as dropout voltage relative to conventional
battery chargers. When the voltage at CHG_IN falls
below VBAT, the charger automatically reconfigures
its power switch to minimize current drain from the
battery.
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I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
Figure 14:
Typical Li+ charge profile and ACT8810 charge states
VSET
RECHARGE
ISET
Current
Voltage
VPRECHARGE
12% ISET
STATE
A
B
C
D
E
B
A: PRECONDITION State
B: FAST-CHARGE State
C: TOP-OFF State
D: SLEEP State
E: DISCHARGE State
Figure 15:
Charger State Diagram
ANY STATE
BATTERY REMOVED OR
V
V
CHG_IN < VBAT + 120mV OR
CHG_IN < UVLO
SUSPEND
BATTERY REPLACED AND
VCHG_IN > VBAT + 120mV AND
VCHG_IN > UVLO
T > TPRECONDITION AND
VBAT < 2.85V
TIMEOUT-FAULT
PRECONDITION
VBAT > 2.85V
T > TNORMAL AND
BAT < VTERM
V
FAST-CHARGE
VBAT = VTERM
TOP-OFF
IBAT < ITERM
IBAT > ITERM
DELAY
SLEEP
VBAT < VTERM – 175mV
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I2CTM is a trademark of Philips Electronics.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
FUNCTIONAL DESCRIPTION CONT’D
End of Charge State
Charger State-Machine
In the End-of-Charge (EOC) state, the ACT8810
presents a high-impedance to the battery, allowing
the cell to “relax” and minimizes battery leakage
current. The ACT8810 continues to monitor the cell
voltage, however, so that it can re-initiate charging
cycles as necessary to ensure that the cell remains
fully charged.
PRECONDITION State
A
new charging cycle begins with the
PRECONDITION state, and operation continues in
this state until VBAT exceeds the Precondition
Threshold Voltage of 2.85V (typ). When operating
in PRECONDITION state, the cell is charged at a
reduced current, 12% of the programmed maximum
fast-charge constant current, ISET. Once VBAT
reaches the Precondition Threshold Voltage the
state machine jumps to the NORMAL state. If VBAT
does not reach the Precondition Threshold Voltage
before the Precondition Timeout period tPRECONDITION
expires, then a damaged cell is detected and the
state machine jumps to the TIMEOUT-FAULT State.
For the Precondition Timeout period, see the
Charging Safety Timers section for more information.
SUSPEND State
The ACT8810 features an user-selectable suspend-
charge mode, which disables the charger but keeps
other circuiting functional. The charger can be put
into suspend mode by driving EN to logic low. Upon
exiting the SUSPEND State, the charge timer is
reset and the state machine jumps to
PRECONDITION state.
SLEEP State
FAST CHARGE State
In SLEEP mode the ACT8810 presents a high-
impedance to the battery, allowing the cell to “relax”
and minimizes battery leakage current. The
ACT8810 continues to monitor the cell voltage,
however, so that it can re-initiate charging as
necessary to ensure that the cell remains fully
charged. Under normal operation, the state
machine initiates a new charging cycle by jumping
to the FAST-CHARGE state when VBAT drops below
the Charge Termination Threshold.
Normal state is made up of two operating modes,
fast charge Constant-Current (CC) and Constant-
Voltage (CV). In CC mode, the ACT8810 charges at
the current programmed by RISET (see the Current
Limits and Charge Current Programming section for
more information). During a normal charge cycle
fast-charge continues in CC mode until VBAT
reaches the charge termination voltage (VTERM), at
which point the ACT8810 charges in CV mode.
Charging continues in CV mode until the charge
current drops to 10% (ACIN = 1) or 5% (ACIN = 0)
of the programmed maximum charge current, at
which point the state machine jumps to the TOP-
OFF state. If VBAT does not proceed out of the
NORMAL state before the Normal Timeout period
(TNORMAL) expires, then a damaged cell is detected
and the state machine jumps to the TIMEOUT-
FAULT State. See the Charging Safety Times
section for more information.
CHG_IN Bypass Capacitor Selection
CHG_IN is the power input for the ACT8810 battery
charger. The battery charger is automatically
enabled whenever a valid voltage is present on
CHG_IN. In most applications, CHG_IN is
connected to either a wall adapter or USB port.
Under normal operation, the input of the charger will
often be “hot-plugged” directly to a powered USB or
wall adapter cable, and supply voltage ringing and
overshoot may appear at the CHG_IN pin.
TOP-OFF State
In most applications a high quality capacitor
connected from CHG_IN to GA, placed as close as
possible to the IC, is sufficient to absorb the energy.
Wall-adapter powered applications provide flexibility
in input capacitor selection, but the USB
specification presents limitations to input
capacitance selection. In order to meet both the
USB 2.0 and USB OTG (On The Go) specifications
while avoiding USB supply under-voltage conditions
In the TOP-OFF state, the cell is charged in
constant-voltage (CV) mode. Charge current
decreases as charging continues. During a normal
charging cycle charging proceeds until the charge
current decreases below the End-Of-Charge (EOC)
threshold, defined as 10% of ISET (ACIN = 1) or
5% of ISET (ACIN = 0) . When this happens, the
state machine terminates the charge cycle and
jumps to the SLEEP state.
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ACT8810
Active- Semi
Rev 4, 01-Oct-09
ActivePathTM CHARGER
FUNCTIONAL DESCRIPTION CONT’D
resulting from the current limit slew rate
(100mA/µS) limitations of the USB bus, the
CHG_IN bypass capacitance value must to be
between 4.7µF and 10µF for the ACT8810.
robustness and an absolute maximum voltage
rating of 14V for transients, attention must be given
to bypass techniques to ensure safe operation.
As a result, design of the CHG_IN bypass must
take care to “de-Q” the filter. This can be
accomplished by connecting a 1ꢀ resistor in series
with a ceramic capacitor (as shown in Figure 16), or
by using a tantalum or electrolytic capacitor to
utilize it’s higher ESR to dampen the ringing. For
additional protection in extreme situations, Zener
diodes with 12V clamp voltages may also be used.
In any case, it is always critical to evaluate voltage
transients at the ACT8810 CHG_IN pin with an
oscilloscope to ensure safe operation.
Ceramic capacitors are often preferred for
bypassing applications due to their small size and
good surge current ratings, but care must be taken
in applications that can encounter hot plug
conditions as their very low ESR, in combination
with the inductance of the cable, can create a high-
Q filter that induces excessive ringing at the
CHG_IN pin. This ringing can couple to the output
and be mistaken as loop instability, or the ringing
may be large enough to damage the input itself.
Although the CHG_IN pin is designed for maximum
Figure 16:
CHG_IN Bypass Options for USB or Wall Adaptor Supplies
Innovative PowerTM
- 51 -
www.active-semi.com
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
ACT8810
Active- Semi
Rev 4, 01-Oct-09
PACKAGE OUTLINE AND DIMENSIONS
PACKAGE OUTLINE
TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS
D
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
D/2
SYMBOL
MIN
MAX
MIN
MAX
A
A1
A2
b
0.700
0.800
0.028
0.031
E/2
0.200 REF
0.008 REF
0.000
0.150
4.900
4.900
3.450
3.450
0.050
0.250
5.100
5.100
3.750
3.750
0.000
0.006
0.193
0.193
0.136
0.136
0.002
0.010
0.201
0.201
0.148
0.148
E
D
E
D2
E2
e
A
0.400 BSC
0.016 BSC
L
0.300
0.500
0.012
0.020
A2
A1
D2
R
0.300
0.012
b
L
e
E2
R
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
sales@active-semi.com or visit http://www.active-semi.com. For other inquiries, please send to:
2728 Orchard Parkway, San Jose, CA 95134-2012, USA
Innovative PowerTM
- 52 -
www.active-semi.com
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of Philips Electronics.
Copyright © 2009 Active-Semi, Inc.
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