ACT8941AQJ465-T [ACTIVE-SEMI]
Advanced PMU for Rockchip RK2906/RK2918 Processor;型号: | ACT8941AQJ465-T |
厂家: | ACTIVE-SEMI, INC |
描述: | Advanced PMU for Rockchip RK2906/RK2918 Processor |
文件: | 总42页 (文件大小:757K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ACT8941A
Rev 0, 12-Mar-13
Advanced PMU for Rockchip RK2906/RK2918 Processor
Rockchip RK2906/RK2918 processor. It is ideal for a
wide range of high performance portable handheld
applications such as tablet or pad devices. This device
FEATURES
• Three Step-Down DC/DC Converters
• Four Low-Dropout Linear Regulators
• Integrated ActivePathTM Charger
• I2CTM Serial Interface
• Advanced Enable/Disable Sequencing Controller
• Minimal External Components
• Tiny 5×5mm TQFN55-40 Package
− 0.75mm Package Height
− Pb-Free and RoHS Compliant
integrates the ActivePathTM complete battery charging
and management system with seven power supply
channels.
This device features three step-down DC/DC
converters and four low-noise, low-dropout linear
regulators, along with a complete battery charging
solution featuring the advanced ActivePathTM
system-power selection function.
The three DC/DC converters utilize
a high-
efficiency, fixed-frequency (2MHz), current-mode
PWM control architecture that requires a minimum
number of external components. Two DC/DCs are
capable of supplying up to 1100mA of output
current, while the third supports up to 1200mA. All
four low-dropout linear regulators are high-
performance, low-noise regulators that supply up to
320mA of output current.
GENERAL DESCRIPTION
The ACT8941A is a complete, cost effective, highly-
efficient ActivePMUTM power management solution,
optimized for the unique power, voltage-
sequencing, and control requirements of the
The ACT8941A is available in a compact, Pb-Free
and RoHS-compliant TQFN55-40 package.
TYPICAL APPLICATION DIAGRAM
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2013 Active-Semi, Inc.
ACT8941A
Rev 0, 12-Mar-13
TABLE OF CONTENTS
General Information.....................................................................................................................................p. 01
Functional Block Diagram............................................................................................................................p. 03
Ordering Information....................................................................................................................................p. 04
Pin Configuration .........................................................................................................................................p. 04
Pin Descriptions...........................................................................................................................................p. 05
Absolute Maximum Ratings.........................................................................................................................p. 07
I2C Interface Electrical Characteristics ........................................................................................................p. 08
Global Register Map....................................................................................................................................p. 09
Register and Bit Descriptions ......................................................................................................................p. 10
System Control Electrical Characteristics....................................................................................................p. 15
Step-Down DC/DC Electrical Characteristics..............................................................................................p. 16
Low-Noise LDO Electrical Characteristics...................................................................................................p. 17
ActivePathTM Charger Electrical Characteristics..........................................................................................p. 18
Typical Performance Characteristics...........................................................................................................p. 20
System control information ..........................................................................................................................p. 26
Control Signals.................................................................................................................................p. 27
Push-Button Control.........................................................................................................................p. 27
Control Sequences...........................................................................................................................p. 28
Functional Description .................................................................................................................................p. 29
I2C Interface .....................................................................................................................................p. 29
Voltage Monitor and Interrupt...........................................................................................................p. 29
Thermal Shutdown ...........................................................................................................................p. 30
Step-Down DC/DC Regulators ....................................................................................................................p. 31
General Description..........................................................................................................................p. 31
100% Duty Cycle Operation.............................................................................................................p. 31
Synchronous Rectification................................................................................................................p. 31
Soft-Start ..........................................................................................................................................p. 31
Compensation ..................................................................................................................................p. 31
Configuration Options.......................................................................................................................p. 31
OK[ ] and Output Fault Interrupt.......................................................................................................p. 32
PCB Layout Considerations.............................................................................................................p. 32
Low-Noise, Low-Dropout Linear Regulators................................................................................................p. 33
General Description..........................................................................................................................p. 33
Output Current Limit.........................................................................................................................p. 33
Compensation ..................................................................................................................................p. 33
Configuration Options.......................................................................................................................p. 33
OK[ ] and Output Fault Interrupt.......................................................................................................p. 33
PCB Layout Considerations.............................................................................................................p. 33
ActivePathTM Charger ..................................................................................................................................p. 35
General Description..........................................................................................................................p. 35
ActivePath Architecture....................................................................................................................p. 35
System Configuration Optimization..................................................................................................p. 35
Input Protection ................................................................................................................................p. 35
Battery Management........................................................................................................................p. 35
Charge Current Programming..........................................................................................................p. 36
Charger Input Interrupts ...................................................................................................................p. 36
Charge-Control State Machine.........................................................................................................p. 38
State Machine Interrupts..................................................................................................................p. 38
Thermal Regulation..........................................................................................................................p. 39
Charge Safety Timers ......................................................................................................................p. 39
Charger Timer Interrupts..................................................................................................................p. 39
Charge Status Indicator....................................................................................................................p. 39
Reverse-Current Protection .............................................................................................................p. 39
Battery Temperature Monitoring ......................................................................................................p. 39
Battery Temperature Interrupts........................................................................................................p. 40
TQFN55-40 Package Outline and Dimensions ...........................................................................................p. 41
Revision History...........................................................................................................................................p. 42
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
Copyright © 2013 Active-Semi, Inc.
I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
FUNCTIONAL BLOCK DIAGRAM
BODY
SWITCH
ACT8941A
CHGIN
ACIN
AC Adap
USB
4.35V to 6V
System Supply
VSYS
BODY
SWITCH
Li+ Battery
BAT
VSYS
+
nSTAT
102µA
CURRENT SENSE
CHARGE STATUS
TH
VOLTAGE SENSE
PRE-
CONDITION
CHGLEV
ISET
2.85V
VP1
To VSYS
THERMAL
REGULATION
OUT1
110°C
SW1
OUT1
GP12
OUT1
nRSTO
VSYS
nPBIN
PUSH BUTTON
VP2
To VSYS
OUT1
nPBSTAT
SW2
OUT2
GP12
OUT2
OUT1
nIRQ
VP3
To VSYS
SW3
OUT3
GP3
OUT3
PWRHLD
VSEL
SCL
INL
To VSYS
OUT4
OUT4
SDA
BAT
LDO
OUT5
OUT6
OUT7
LBI
-
OUT5
OUT6
OUT7
LDO
LDO
LDO
1.2V
VSYS
+
nLBO
REFBP
Reference
GA
EP
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I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
ORDERING INFORMATIONꢀꢁ
TEMPERATURE
RANGE
PART NUMBER
ꢂVOUT2/VSTBY2 VOUT3/VSTBY3 VOUT4 VOUT5 VOUT6 VOUT7 PACKAGE PINS
VOUT1/VSTBY1
ACT8941AQJ465-T 3.0V/3.0V
1.5V/1.5V 1.2V/1.2V 2.5V 1.8V 3.0V 3.0V TQFN55-40 40 -40°C to +85°C
ꢀ: All Active-Semi components are RoHS Compliant and with Pb-free plating otherwise specified.
ꢁ: Standard product options are listed in this table. Contact factory for custom options. Minimum order quantity is 12,000 units.
ꢂ: To select VSTBYx as the output regulation voltage for REGx, drive VSEL to logic high. VSTBYx can be set by software via I2C interface.
Refer to appropriate sections of this datasheet for VSTBYx setting.
PIN CONFIGURATION
TOP VIEW
ACTIVE
A33KY25
DATE CODE
Thin - QFN (TQFN55-40)
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I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
1
REFBP
2
3
4
5
6
7
8
OUT1
GA
Output Feedback Sense for REG1.
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12 and GP3
together at a single point as close to the IC as possible.
REG4 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
OUT4
OUT5
INL
REG5 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
Power Input for REG4, REG5, REG6, and REG7. Bypass to GA with a high quality ceramic
capacitor placed as close to the IC as possible.
REG7 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
OUT7
OUT6
REG6 output. Capable of delivering up to 320mA of output current. Connect a 3.3µF ceramic
capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive nPBIN
directly to GA to assert a manual reset condition. Refer to the nPBIN Multi-Function Input section
for more information. nPBIN is internally pulled up to VSYS through a 35kꢀ resistor.
9
nPBIN
Power Hold Input. Enable input for all regulators. PWRHLD is internally pulled down to GA through
a 500kꢀ resistor. Refer to the Control Sequences section for more information.
10
11
12
PWRHLD
nRSTO
nIRQ
Active Low Reset Output. See the nRSTO Output section for more information.
Open-Drain Interrupt Output. nIRQ is asserted any time an unmasked fault condition exists or a
charger interrupt occurs. See the nIRQ Output section for more information.
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the
nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information.
13
nPBSTAT
Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the
IC as possible.
14
15
16
GP3
SW3
VP3
Switching Node Output for REG3.
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the
IC as possible.
17
18
19
OUT3
NC1
Output Feedback Sense for REG3.
No Connect. Not internally connected.
Low Battery Indicator Output. nLBO is asserted low whenever the voltage at LBI is lower than
1.2V, and is high-Z otherwise. See the Precision Voltage Detector section for more information.
nLBO
Low Battery Input. The input voltage is compared to 1.2V and the output of this comparison drives
nLBO. See the Precision Voltage Detector section for more information.
20
LBI
21
22
ACIN
AC Input Supply Detection. See the Charge Current Programming section for more information.
CHGLEV Charge Current Selection Input. See the Charge Current Programming section for more information.
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I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
PIN DESCRIPTIONS CONT’D
PIN
NAME
DESCRIPTION
Charge Current Set. Program the charge current by connecting a resistor (RISET) between ISET
and GA. See the Charge Current Programming section for more information.
23
ISET
Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 102µA (typ) current
internally. See the Battery Temperature Monitoring section for more information.
24
25
TH
Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage. See the Output Voltage Programming
section for more information.
VSEL
26
27
SCL
SDA
Clock Input for I2C Serial Interface.
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
Active-Low Open-Drain Charger Status Output. nSTAT has a 8mA (typ) current limit, allowing it
to directly drive an indicator LED without additional external components. See the Charge Status
Indicator section for more information.
28
nSTAT
29, 30
31, 32
BAT
Battery Charger Output. Connect this pin directly to the battery anode (+ terminal)
System Output Pin. Bypass to GA with a 10µF or larger ceramic capacitor.
VSYS
Power Input for the Battery Charger. Bypass CHGIN to GA with a capacitor placed as close to
the IC as possible.
33
34
CHGIN
OUT2
Output Feedback Sense for REG2.
Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close to
the IC as possible.
35
36
37
38
39
VP2
SW2
GP12
SW1
VP1
Switching Node Output for REG2.
Power Ground for REG1 and REG2. Connect GA, GP12 and GP3 together at a single point as
close to the IC as possible.
Switching Node Output for REG1.
Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close to
the IC as possible.
40
NC2
EP
No Connect. Not internally connected.
EP
Exposed Pad. Must be soldered to ground on PCB.
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I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
ABSOLUTE MAXIMUM RATINGSꢀ
PARAMETER
VALUE
-0.3 to + 6
-0.3 to + 6
-0.3 to + 14
UNIT
V
VP1, VP2 to GP12
VP3 to GP3
BAT, VSYS, INL to GA
CHGIN to GA
V
V
V
V
V
SW1, OUT1 to GP12
SW2, OUT2 to GP12
SW3, OUT3 to GP3
-0.3 to (VVP1 + 0.3)
-0.3 to (VVP2 + 0.3)
-0.3 to (VVP3 + 0.3)
nPBIN, ACIN, CHGLEV, ISET, LBI, PWRHLD, REFBP, SCL, SDA, TH, VSEL, nIRQ,
nLBO, nPBSTAT, nRSTO, nSTAT to GA
-0.3 to + 6
V
OUT4, OUT5, OUT6, OUT7 to GA
GP12, GP3 to GA
-0.3 to (VINL + 0.3)
-0.3 to + 0.3
-40 to 85
V
V
Operating Ambient Temperature
Maximum Junction Temperature
°C
°C
125
Maximum Power Dissipation
2.7
W
TQFN55-40 (Thermal Resistance θJA = 30oC/W)
Storage Temperature
-65 to 150
300
°C
°C
Lead Temperature (Soldering, 10 sec)
ꢀ: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
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I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
SCL, SDA Input Low
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VVSYS = 3.1V to 5.5V, TA = -40ºC to 85ºC
0.35
SCL, SDA Input High
SDA Leakage Current
SCL Leakage Current
SDA Output Low
V
VSYS = 3.1V to 5.5V, TA = -40ºC to 85ºC
1.55
V
1
2
µA
µA
V
I
OL = 5mA
0.35
SCL Clock Period, tSCL
SDA Data Setup Time, tSU
SDA Data Hold Time, tHD
Start Setup Time, tST
Stop Setup Time, tSP
1.5
100
300
100
100
µs
ns
ns
ns
ns
For Start Condition
For Stop Condition
Figure 1:
I2C Compatible Serial Bus Timing
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
condition
Stop
condition
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I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
GLOBAL REGISTER MAP
BITS
OUTPUT ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
NAME
DEFAULTꢀ
NAME
TRST nSYSMODE nSYSLEVMSK nSYSSTAT SYSLEV[3] SYSLEV[2] SYSLEV[1] SYSLEV[0]
SYS
0x00
0x01
0x20
0x21
0x22
0x30
0x31
0x32
0x40
0x41
0x42
0x50
0x51
0x54
0x55
0x60
0x61
0x64
0x65
0x70
0x71
0x78
0x79
0x7A
0
1
0
R
0
1
1
1
Reserved Reserved
MSTROFF
Reserved
SCRATCH SCRATCH SCRATCH
SCRATCH
SYS
DEFAULTꢀ
0
0
0
0
0
0
0
0
NAME
Reserved Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
REG1
REG1
REG1
REG2
REG2
REG2
REG3
REG3
REG3
REG4
REG4
REG5
REG5
REG6
REG6
REG7
REG7
APCH
APCH
APCH
APCH
APCH
DEFAULTꢀ
NAME
DEFAULTꢀ
0
0
1
1
VSET2[4]
1
0
VSET2[3]
0
1
VSET2[2]
1
1
VSET2[1]
1
0
Reserved Reserved
VSET2[5]
VSET2[0]
0
ON
1
0
PHASE
0
1
0
NAME
MODE
DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK
OK
DEFAULTꢀ
NAME
DEFAULTꢀ
0
0
0
0
0
R
Reserved Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
0
0
0
1
VSET2[4]
1
1
VSET2[3]
1
1
VSET2[2]
1
1
VSET2[1]
1
0
NAME
Reserved Reserved
VSET2[5]
VSET2[0]
DEFAULTꢀ
NAME
DEFAULTꢀ
0
ON
1
0
PHASE
0
0
0
MODE
DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK
OK
0
0
1
0
0
R
NAME
Reserved Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
DEFAULTꢀ
NAME
DEFAULTꢀ
0
0
0
1
VSET2[4]
1
1
VSET2[3]
1
0
VSET2[2]
0
0
VSET2[1]
0
0
Reserved Reserved
VSET2[5]
VSET2[0]
0
ON
1
0
PWRSTAT
0
0
0
NAME
MODE
DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK
OK
DEFAULTꢀ
NAME
DEFAULTꢀ
0
0
VSET[4]
1
1
VSET[3]
0
0
VSET[2]
0
0
VSET[1]
0
R
Reserved Reserved
VSET[5]
VSET[0]
0
ON
1
0
DIS
1
1
1
NAME
LOWIQ
DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK
OK
DEFAULTꢀ
NAME
DEFAULTꢀ
0
0
VSET[4]
0
0
VSET[3]
0
1
VSET[2]
1
0
VSET[1]
0
R
Reserved Reserved
VSET[5]
VSET[0]
0
ON
1
0
DIS
1
1
0
NAME
LOWIQ
DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK
OK
DEFAULTꢀ
NAME
DEFAULTꢀ
0
0
VSET[4]
1
0
VSET[3]
0
1
VSET[2]
1
0
VSET[1]
1
R
Reserved Reserved
VSET[5]
VSET[0]
0
ON
0
0
DIS
1
1
0
NAME
LOWIQ
DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK
OK
DEFAULTꢀ
NAME
DEFAULTꢀ
0
0
VSET[4]
1
0
VSET[3]
0
0
VSET[2]
1
0
VSET[1]
1
R
Reserved Reserved
VSET[5]
VSET[0]
0
ON
0
0
DIS
1
1
0
NAME
LOWIQ
DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK
OK
DEFAULTꢀ
NAME
DEFAULTꢀ
0
Reserved
0
0
Reserved
1
0
Reserved
0
0
Reserved
0
0
Reserved
0
R
Reserved
0
Reserved Reserved
0
1
NAME
SUSCHG Reserved TOTTIMO[1] TOTTIMO[0] PRETIMO[1] PRETIMO[0] OVPSET[1] OVPSET[0]
DEFAULTꢀ
NAME
DEFAULTꢀ
0
1
1
0
CHGSTAT
0
1
TIMRDAT
R
0
0
INDAT
R
0
TIMRSTAT TEMPSTAT
INSTAT
TEMPDAT
CHGDAT
0
0
0
R
TEMPOUT
0
R
NAME
TIMRTOT TEMPIN
INCON
CHGEOCIN TIMRPRE
INDIS
0
CHGEOCOUT
DEFAULTꢀ
NAME
DEFAULTꢀ
0
0
0
CSTATE[0]
R
0
CSTATE[1]
R
0
Reserved
0
0
Reserved
R
Reserved Reserved
Reserved ACINSTAT
0
0
R
R
ꢀ: Default values of ACT8941AQJ465.
2: All bits are automatically cleared to default values when the input power is removed or falls below the system UVLO.
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I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Reset Timer Setting. Defines the reset time-out threshold. Reset
time-out is 65ms when value is 1, reset time-out is 260ms when
value is 0. See nRSTO Output section for more information.
SYS
SYS
0x00
0x00
[7]
TRST
R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Generate an interrupt when VVSYS falls below
the programmed SYSLEV threshold, 0: automatic shutdown
when VVSYS falls below the programmed SYSLEV threshold.
[6] nSYSMODE
R/W
System Voltage Level Interrupt Mask. SYSLEV interrupt is
masked by default, set to 1 to unmask this interrupt. See the
Programmable System Voltage Monitor section for more
information
SYS
SYS
0x00
0x00
[5] nSYSLEVMSK R/W
System Voltage Status. Value is 1 when VVSYS is lower than the
SYSLEV voltage threshold, value is 0 when VVSYS is higher than
the system voltage detection threshold.
[4]
nSYSSTAT
R
System Voltage Detect Threshold. Defines the SYSLEV voltage
threshold. See the Programmable System Voltage Monitor
section for more information.
SYS
SYS
0x00
0x01
[3:0]
[7:6]
SYSLEV
-
R/W
R/W
Reserved.
Master Off Control. Set bit to 1 to turn off all regulators. The bit
will be automatically cleared to 0 when nPBIN is asserted or a
valid CHGIN voltage is detected (for ACT8941AQJ4## only).
SYS
0x01
[5]
[4]
MSTROFF
-
R/W
SYS
SYS
0x01
0x01
0x20
0x20
0x21
0x21
R/W
R/W
R
Reserved.
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
when system voltage falls below UVLO threshold.
[3:0] SCRATCH
REG1
REG1
REG1
REG1
[7:6]
[5:0]
[7:6]
[5:0]
Reserved.
-
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information.
VSET1
-
R/W
R
Reserved.
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
VSET2
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1
REG1
0x22
0x22
[7]
[6]
ON
R/W
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
PHASE
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-savings
mode under light-load conditions.
REG1
0x22
[5]
MODE
R/W
Regulator Turn-On Delay Control. See the REG1, REG2, REG3
Turn-on Delay section for more information.
REG1
REG1
REG1
0x22
0x22
0x22
[4:2]
[1]
DELAY
nFLTMSK
OK
R/W
R/W
R
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
[0]
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ACT8941A
Rev 0, 12-Mar-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
0x30
0x30
0x31
0x31
[7:6]
[5:0]
[7:6]
[5:0]
R
Reserved.
REG2
REG2
REG2
REG2
-
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information.
VSET1
-
R/W
R
Reserved.
Secondary Output Voltage Selection. Valid when VSEL is
driven high. See the Output Voltage Programming section for
more information.
VSET2
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG2
REG2
0x32
0x32
[7]
[6]
ON
R/W
R/W
Regulator Phase Control. Set bit to 1 for the regulator to
operate 180° out of phase with the oscillator, clear bit to 0 for
the regulator to operate in phase with the oscillator.
PHASE
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-
savings mode under light-load conditions.
REG2
0x32
[5]
MODE
R/W
Regulator Turn-On Delay Control. See the REG1, REG2,
REG3 Turn-on Delay section for more information.
REG2
REG2
0x32
0x32
[4:2]
[1]
DELAY
R/W
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG2
REG3
0x32
0x40
[0]
OK
-
R
R
[7:6]
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information.
REG3
REG3
REG3
0x40
0x41
0x41
[5:0]
[7:6]
[5:0]
VSET1
-
R/W
R
Reserved.
Secondary Output Voltage Selection. Valid when VSEL is
driven high. See the Output Voltage Programming section for
more information.
VSET2
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG3
REG3
0x42
0x42
[7]
[6]
ON
-
R/W
R/W
Reserved.
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-
savings mode under light-load conditions.
REG3
0x42
[5]
MODE
R/W
Regulator Turn-On Delay Control. See the REG1, REG2,
REG3 Turn-on Delay section for more information.
REG3
REG3
REG3
0x42
0x42
0x42
[4:2]
[1]
DELAY
nFLTMSK
OK
R/W
R/W
R
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
[0]
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ACT8941A
Rev 0, 12-Mar-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
REG4
REG4
0x50
0x50
[7:6]
[5:0]
-
R
Reserved.
Output Voltage Selection. See the Output Voltage
Programming section for more information.
VSET
ON
R/W
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG4
REG4
0x51
0x51
[7]
[6]
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kꢀ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
DIS
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG4
REG4
REG4
0x51
0x51
0x51
[5]
[4:2]
[1]
LOWIQ
DELAY
R/W
R/W
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG4
REG5
REG5
0x51
0x54
0x54
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage
Programming section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG5
REG5
0x55
0x55
[7]
[6]
ON
R/W
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kꢀ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
DIS
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG5
REG5
REG5
0x55
0x55
0x55
[5]
[4:2]
[1]
LOWIQ
DELAY
R/W
R/W
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6 , REG7 Turn-on Delay section for more information.
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG5
REG6
REG6
0x55
0x60
0x60
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage
Programming section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG6
REG6
0x61
0x61
[7]
[6]
ON
R/W
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kꢀ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
DIS
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG6
REG6
REG6
0x61
0x61
0x61
[5]
[4:2]
[1]
LOWIQ
DELAY
R/W
R/W
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
nFLTMSK
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ACT8941A
Rev 0, 12-Mar-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG6
REG7
REG7
0x61
0x64
0x64
[0]
OK
-
R
R
[7:6]
[5:0]
Reserved.
Output Voltage Selection. See the Output Voltage
Programming section for more information.
VSET
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG7
REG7
0x65
0x65
[7]
[6]
ON
R/W
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kꢀ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
DIS
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG7
REG7
REG7
0x65
0x65
0x65
[5]
[4:2]
[1]
LOWIQ
DELAY
R/W
R/W
R/W
R
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
nFLTMSK
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG7
APCH
APCH
APCH
APCH
0x65
0x70
0x71
0x71
0x71
[0]
[7:0]
[7]
OK
-
R/W Reserved.
Charge Suspend Control Input. Set bit to 1 to suspend
charging, clear bit to 0 to allow charging to resume.
SUSCHG
-
R/W
[6]
R/W Reserved.
Total Charge Time-out Selection. See the Charge Safety
Timers section for more information.
[5:4]
TOTTIMO
R/W
R/W
R/W
Precondition Charge Time-out Selection. See the Charge
Safety Timers section for more information.
APCH
APCH
0x71
0x71
[3:2]
[1:0]
PRETIMO
OVPSET
Input Over-Voltage Protection Threshold Selection. See the
Input Over-Voltage Protection section for more information.
Charge Time-out Interrupt Status. Set this bit with
TIMRPRE[ ] and/or TIMRTOT[ ] to 1 to generate an interrupt
APCH
APCH
APCH
0x78
0x78
0x78
[7]
[6]
[5]
TIMRSTAT1
TEMPSTAT1
INSTAT
R/W when charge safety timers expire, read this bit to get charge
time-out interrupt status. See the Charge Safety Timers
section for more information.
Battery Temperature Interrupt Status. Set this bit with
TEMPIN[ ] and/or TEMPOUT[ ] to 1 to generate an interrupt
R/W when a battery temperature event occurs, read this bit to get
the battery temperature interrupt status. See the Battery
Temperature Monitoring section for more information.
Input Voltage Interrupt Status. Set this bit with INCON[ ] and/or
INDIS[ ] to generate an interrupt when UVLO or OVP condition
R/W occurs, read this bit to get the input voltage interrupt status.
See the Charge Current Programming section for more
information.
Charge State Interrupt Status. Set this bit with
CHGEOCIN[ ] and/or CHGEOCOUT[ ] to 1 to generate an
R/W interrupt when the state machine gets in or out of EOC state,
read this bit to get the charger state interrupt status. See the
State Machine Interrupts section for more information.
APCH
APCH
0x78
0x78
[4]
[3]
CHGSTAT1
TIMRDAT1
Charge Timer Status. Value is 1 when precondition time-out or
R
total charge time-out occurs. Value is 0 in other case.
ꢀ: Valid only when CHGIN UVLO Threshold<VCHGIN<CHGIN OVP Threshold.
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ACT8941A
Rev 0, 12-Mar-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Temperature Status. Value is 0 when battery temperature is
outside of valid range. Value is 1 when battery temperature
is inside of valid range.
APCH
APCH
APCH
0x78
0x78
0x78
[2]
[1]
[0]
TEMPDAT1
R
Input Voltage Status. Value is 1 when a valid input at
CHGIN is present. Value is 0 when a valid input at CHGIN
is not present.
INDAT
R
R
Charge State Machine Status. Value is 1 indicates the
charger state machine is in EOC state, value is 0 indicates
the charger state machine is in other states.
CHGDAT1
Total Charge Time-out Interrupt Control. Set both this bit
and TIMRSTAT[ ] to 1 to generate an interrupt when a total
charge time-out occurs. See the Charge Safety Timers
section for more information.
APCH
APCH
APCH
APCH
APCH
APCH
APCH
APCH
0x79
0x79
0x79
0x79
0x79
0x79
0x79
0x79
[7]
[6]
[5]
[4]
[3]
[2]
[1]
TIMRTOT
TEMPIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Battery Temperature Interrupt Control. Set both this bit and
TEMPSTAT[ ] to 1 to generate an interrupt when the battery
temperature goes into the valid range. See the Battery
Temperature Monitoring section for more information.
Input Voltage Interrupt Control. Set both this bit and
INSTAT[ ] to 1 to generate an interrupt when CHGIN input
voltage goes into the valid range. See the Charge Current
Programming section for more information.
INCON
Charge State Interrupt Control. Set both this bit and
CHGSTAT[ ] to 1 to generate an interrupt when the state
machine goes into the EOC state. See the State Machine
Interrupts section for more information.
CHGEOCIN
TIMRPRE
TEMPOUT
INDIS
PRECHARGE Time-out Interrupt Control. Set both this bit
and TIMRSTAT[ ] to 1 to generate an interrupt when a
PRECHARGE time-out occurs. See the Charge Safety
Timers section for more information.
Battery Temperature Interrupt Control. Set both this bit and
TEMPSTAT[ ] to 1 to generate an interrupt when the battery
temperature goes out of the valid range. See the Battery
Temperature Monitoring section for more information.
Input Voltage Interrupt Control. Set both this bit and
INSTAT[ ] to 1 to generate an interrupt when CHGIN input
voltage goes out of the valid range. See the Charge Current
Programming section for more information.
Charge State Interrupt Control. Set both this bit and
CHGSTAT[ ] to 1 to generate an interrupt when the state
machines jumps out of the EOC state. See the State
Machine Interrupts section for more information.
[0] CHGEOCOUT
APCH
APCH
APCH
0x7A
0x7A
0x7A
[7:6]
[5:4]
[3:2]
-
R
R
R
Reserved.
Charge State. Values indicate the current charging state.
See the State Machine Interrupts section for more
information.
CSTATE
-
Reserved.
ACIN Status. Indicates the state of the ACIN input, typically
in order to identify the type of input supply connected. Value
is 1 when ACIN is above the 1.2V precision threshold, value
is 0 when ACIN is below this threshold.
APCH
APCH
0x7A
0x7A
[1]
[0]
ACINSTAT
-
R
R
Reserved.
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ACT8941A
Rev 0, 12-Mar-13
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
Input Voltage Range
TEST CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNIT
V
UVLO Threshold Voltage
UVLO Hysteresis
VVSYS Rising
2.2
2.45
200
420
8
2.65
V
VVSYS Falling
mV
Supply Current
All Regulators Enabled
All Regulators Disabled
µA
Shutdown Supply Current
Oscillator Frequency
Logic High Input Voltage1
Logic Low Input Voltage
Leakage Current
18
1.8
1.4
2
2.2
MHz
V
0.4
1
V
VnIRQ = VnRSTO = 4.2V
µA
V
LBI Threshold Voltage
LBI Hysteresis Threshold
Low Level Output Voltage2
nRSTO Delay
V
BAT Falling
1.03
1.2
1.31
VBAT Rising
ISINK = 5mA
200
mV
V
0.35
130ꢂ
500
ms
PWRHLD Pull Down Resistor
kꢀ
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Temperature rising
160
20
°C
°C
ꢀ: PWRHLD, VSEL are logic inputs.
2: nLBO, nPBSTAT, nIRQ, nRSTO are open drain outputs.
3: Typical value shown. Actual value may vary from (T-1ms) x 88% to T x 112%, where T = 130ms.
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ACT8941A
Rev 0, 12-Mar-13
STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
Operating Voltage Range
UVLO Threshold
CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNIT
V
Input Voltage Rising
2.5
2.6
100
65
0
2.7
V
UVLO Hysteresis
Input Voltage Falling
Regulator Enabled
mV
µA
µA
Quiescent Supply Current
Shutdown Current
90
1
V
V
V
V
VP = 5.5V, Regulator Disabled
ꢀ
OUT ≥ 1.2V, IOUT = 10mA
-1%
-2%
VNOM
VNOM
1%
2%
Output Voltage Accuracy
V
ꢀ
OUT < 1.2V, IOUT = 10mA
VP = Max (VNOM1 +1, 3.2V) to 5.5V
I
OUT = 10mA to IMAX2
Line Regulation
0.15
0.0017
93
%/V
%/mA
%VNOM
%VNOM
MHz
kHz
Load Regulation
Power Good Threshold
Power Good Hysteresis
V
V
V
V
OUT Rising
OUT Falling
2
OUT ≥ 20% of VNOM
OUT = 0V
1.8
2
2.2
Oscillator Frequency
500
400
75
Soft-Start Period
Minimum On-Time
REG1
µs
ns
Maximum Output Current
Current Limit
1.1
A
A
1.55
1.80
0.16
0.16
0
2.05
1
PMOS On-Resistance
NMOS On-Resistance
SW1 Leakage Current
REG2
I
SW1 = -100mA
SW1 = 100mA
ꢀ
I
ꢀ
V
VP1 = 5.5V, VSW1 = 0 or 5.5V
µA
Maximum Output Current
Current Limit
1.1
A
A
1.55
1.80
0.16
0.16
0
2.05
1
PMOS On-Resistance
NMOS On-Resistance
SW2 Leakage Current
REG3
I
SW2 = -100mA
SW2 = 100mA
ꢀ
I
ꢀ
V
VP2 = 5.5V, VSW2 = 0 or 5.5V
µA
Maximum Output Current
Current Limit
1.2
A
A
1.55
1.80
0.16
0.16
0
2.05
PMOS On-Resistance
I
SW3 = -100mA
ISW3 = 100mA
VP3 = 5.5V, VSW3 = 0 or 5.5V
ꢀ
NMOS On-Resistance
SW3 Leakage Current
ꢀ
V
1
µA
ꢀ: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
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ACT8941A
Rev 0, 12-Mar-13
LOW-NOISE LDO ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, COUT4 = COUT5 = COUT6 = COUT7 = 3.3µF, LOWIQ[ ] = [0], TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
2.5
TYP
MAX
5.5
UNIT
Operating Voltage Range
V
ꢀ
V
OUT ≥ 1.2V, TA = 25°C, IOUT = 10mA
-1%
-2%
VNOM
VNOM
2%
Output Voltage Accuracy
Line Regulation
V
ꢀ
VOUT < 1.2V, TA = 25°C, IOUT = 10mA
INL = Max (VOUT + 0.5V, 3.6V) to 5.5V
4%
V
0.05
0.5
LOWIQ[ ] = [0]
mV/V
VINL = Max (VOUT + 0.5V, 3.6V) to 5.5V
LOWIQ[ ] = [1]
Load Regulation
IOUT = 1mA to IMAX2
0.08
75
65
37
31
0
V/A
dB
f = 1kHz, IOUT = 20mA, VOUT =1.2V
f = 10kHz, IOUT = 20mA, VOUT =1.2V
Regulator Enabled, LOWIQ[ ] = [0]
Regulator Enabled, LOWIQ[ ] = [1]
Regulator Disabled
Power Supply Rejection Ratio
60
52
1
Supply Current per Output
µA
Soft-Start Period
VOUT = 2.9V
VOUT Rising
VOUT Falling
140
89
3
µs
%
%
Power Good Threshold
Power Good Hysteresis
I
OUT = 20mA, f = 10Hz to 100kHz, VOUT =
Output Noise
50
µVRMS
1.2V
Discharge Resistance
REG4
LDO Disabled, DIS[ ] = 1
1.5
kꢀ
Dropout Voltageꢂ
Maximum Output Current
Current Limitꢃ
IOUT = 80mA, VOUT > 3.1V
90
140
90
180
mV
mA
mA
µF
320
400
3.3
VOUT = 95% of regulation voltage
Stable COUT4 Range
REG5
20
Dropout Voltage
Maximum Output Current
Current Limit
IOUT = 80mA, VOUT > 3.1V
280
mV
mA
mA
µF
320
400
3.3
VOUT = 95% of regulation voltage
Stable COUT5 Range
REG6
20
Dropout Voltage
Maximum Output Current
Current Limit
IOUT = 80mA, VOUT > 3.1V
180
mV
mA
mA
µF
320
400
3.3
VOUT = 95% of regulation voltage
Stable COUT6 Range
REG7
20
Dropout Voltage
Maximum Output Current
Current Limit
IOUT = 80mA, VOUT > 3.1V
140
280
mV
mA
mA
µF
320
400
3.3
VOUT = 95% of regulation voltage
Stable COUT7 Range
20
ꢀ: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher)
ꢃ: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
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Copyright © 2013 Active-Semi, Inc.
I2CTM is a trademark of NXP.
ACT8941A
Rev 0, 12-Mar-13
ActivePathTM CHARGER ELECTRICAL CHARACTERISTICS
(VCHGIN = 5.0V, TA = 25°C, unless otherwise specified.)
PARAMETER
ActivePath
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHGIN Operating Voltage Range
4.35
3.1
6.0
3.9
V
V
CHGIN UVLO Threshold
CHGIN UVLO Hysteresis
CHGIN OVP Threshold
CHGIN OVP Hysteresis
CHGIN Voltage Rising
CHGIN Voltage Falling
3.5
0.5
6.6
0.4
35
V
CHGIN Voltage Rising
CHGIN Voltage Falling
VCHGIN < VUVLO
6.0
7.2
V
V
70
µA
µA
VCHGIN < VBAT + 50mV, VCHGIN > VUVLO
100
200
CHGIN Supply Current
V
CHGIN > VBAT + 150mV, VCHGIN > VUVLO
1.3
2.0
mA
Charger disabled, IVSYS = 0mA
IVSYS = 100mA
CHGIN to VSYS On-Resistance
CHGIN to VSYS Current Limit
0.3
2
ꢀ
ACIN = VSYS
1.5
80
A
ACIN = GA, CHGLEV = GA
ACIN = GA, CHGLEV = VSYS
90
450
100
500
mA
400
VSYS REGULATION
VSYS Regulated Voltage
nSTAT OUTPUT
IVSYS = 10mA
VnSTAT = 2V
4.45
4
4.6
8
4.8
V
nSTAT Sink current
12
1
mA
µA
nSTAT Leakage Current
ACIN AND CHGLEV INPUTS
CHGLEV Logic High Input Voltage
CHGLEV Logic Low Input Voltage
CHGLEV Leakage Current
ACIN Voltage Thresholds
ACIN Hysteresis Voltage
ACIN Leakage Current
TH INPUT
VnSTAT = 4.2V
1.4
V
V
0.4
1
VCHGLEV = 4.2V
µA
V
ACIN voltage rising
ACIN voltage falling
1.03
1.2
1.31
200
mV
µA
V
ACIN = 4.2V
1
TH Pull-Up Current
VCHGIN > VBAT + 100mV, Hysteresis = 50mV
Hot Detect NTC Thermistor
91
102
110
µA
V
VTH Upper Temperature Voltage
0.47
0.50
0.53
Threshold (VTHH
)
VTH Lower Temperature Voltage
Cold Detect NTC Thermistor
Upper and Lower Thresholds
2.44
2.51
30
2.58
V
Threshold (VTHL
)
VTH Hysteresis
mV
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ACT8941A
Rev 0, 12-Mar-13
ActivePathTM CHARGER ELECTRICAL CHARACTERISTICS CONT’D
(VCHGIN = 5.0V, TA = 25°C, unless otherwise specified.)
PARAMETER
CHARGER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BAT Reverse Leakage Current VCHGIN = 0V, VBAT = 4.2V, IVSYS = 0mA
BAT to VSYS On-Resistance
8
µA
70
mꢀ
Fast Charge
ISET Pin Voltage
1.2
0.13
4.2
4.2
V
Precondition
TA = -20°C to 70°C
4.179
4.170
4.221
V
Charge Termination Voltage
VTERM
TA = -40°C to 85°C
4.230
1
ACIN = VSYS, CHGLEV = VSYS -10%
ICHG
ICHG/5
450
+10%
ACIN = VSYS, CHGLEV = GA
ACIN = GA, CHGLEV = VSYS
-10%
400
80
+10%
mA
VBAT = 3.8V
RISET = 6.8K
Charge Current
500
ACIN = GA, CHGLEV = GA
ACIN = VSYS, CHGLEV = VSYS
ACIN = VSYS, CHGLEV = GA
ACIN = GA, CHGLEV = VSYS
ACIN = GA, CHGLEV = GA
90
10% ICHG
10% ICHG
45
100
VBAT = 2.7V
Precondition Charge Current
mA
RISET = 6.8K
45
Precondition Threshold Voltage VBAT Voltage Rising
Precondition Threshold
2.75
2.85
3.0
V
V
BAT Voltage Falling
150
mV
Hysteresis
ACIN = VSYS, CHGLEV = VSYS
10% ICHG
ACIN = VSYS, CHGLEV = GA
ACIN = GA, CHGLEV = VSYS
ACIN = GA, CHGLEV = GA
10% ICHG
45
END-OF-CHARGE Current
Threshold
VBAT = 4.15V,
mA
45
Charge Restart Threshold
Precondition Safety Timer
Total Safety Timer
VTERM - VBAT, VBAT Falling
PRETIMO[ ] = 10
190
205
80
220
mV
min
hr
TOTTIMO[ ] = 10
5
Thermal Regulation Threshold
100
°C
ꢀ: RISET (kꢀ) = 2336 × (1V/ICHG (mA)) - 0.205
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ACT8941A
Rev 0, 12-Mar-13
TYPICAL PERFORMANCE CHARACTERISTICS
(VVSYS = 3.6V, TA = 25°C, unless otherwise specified.)
Frequency vs. Temperature
VREF vs. Temperature
2.5
2
0.84
0.42
0
1.5
1
0.5
0
-0.42
-0.84
-0.5
-1
Typical VREF=1.2V
Typical Oscillator Frequency=2MHz
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80 85
Temperature (°C)
Temperature (°C)
nPBIN Startup Sequence
PWRHLD Startup Sequence
CH1
CH1
CH2
CH3
CH4
CH2
CH3
CH4
CH5
CH5
CH6
CH6
CH1: VnPBIN, 2V/div
CH2: VOUT1, 2V/div
CH3: VOUT2, 1V/div
CH4: VOUT3, 1V/div
CH5: VOUT4, 2V/div
CH6: VOUT5, 1V/div
TIME: 5ms/div
CH1: VPWRHLD, 5V/div
CH2: VOUT1, 2V/div
CH3: VOUT2, 1V/div
CH4: VOUT3, 1V/div
CH5: VOUT4, 2V/div
CH6: VOUT5, 1V/div
TIME: 5ms/div
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ACT8941A
Rev 0, 12-Mar-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Warm Reset
(Reset button pressed less than 130ms)
Push-Button Response (First Power-Up)
CH1
CH2
CH1
CH2
CH3
CH3
CH1: VnPBIN, 2V/div
CH1: VnPBIN, 2V/div
CH2: OUT5, 1V/div
CH3:VnRSTO , 5V/div
TIME: 100ms/div
nPBIN Resistor = 50kꢀ
CH2: VnPBSTAT, 2V/div
nPBIN Resistor = 0ꢀ
CH3: VnRSTO, 2V/div
TIME: 50ms/div
Cold Reset
(Reset button pressed longer than 260ms)
Cold Reset
(Reset button pressed longer than 130ms, less than 260ms)
CH1
CH1
CH2
CH3
CH2
CH3
CH1: VnPBIN, 2V/div
nPBIN Resistor = 0ꢀ
nPBIN Resistor = 0ꢀ
CH2: OUT5, 1V/div
CH3:VnRSTO , 5V/div
TIME: 100ms/div
CH1: VnPBIN, 2V/div
CH2: OUT5, 1V/div
CH3:VnRSTO , 5V/div
TIME: 100ms/div
REG1 Efficiency vs. Output Current
REG2 Efficiency vs. Output Current
100
80
60
40
20
0
100
80
60
40
20
0
VOUT = 1.3V
VOUT = 3.3V
VIN = 5.0V
VIN=5.0V
VIN = 3.6V
VIN = 4.2V
VIN = 3.6V
VIN = 4.2V
1
10
100
1000
1
10
100
1000
Output Current (mA)
Output Current (mA)
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ACT8941A
Rev 0, 12-Mar-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG1, 2, 3 Output Voltage vs. Temperature
REG3 Efficiency vs. Output Current
100
80
60
40
20
0
VOUT = 1.3V
0.02
0.01
0
ILOAD = 100mA
VIN=5.0V
VOUT ≤ 1.2V
VIN = 3.6V
VIN = 4.2V
VOUT > 1.2V
-0.01
-0.02
-40
-20
0
20
40
60
80
1
10
100
1000
Temperature (°C)
Output Current (mA)
REG1, 2, 3 MOSFET Resistance
REG4, 5, 6, 7 Output Voltage vs. Output Current
350
300
250
200
150
100
50
ILOAD = 100mA
4%
2%
VOUT > 1.2V
PMOS
NMOS
0%
-2%
VOUT ≤ 1.2V
-4%
-6%
0
3.0
3.5
4.0
4.5
5.0
5.5
0
50
100
150
200
250
300
350
400
Input Voltage (V)
Output Current (mA)
Dropout Voltage vs. Output Current
Dropout Voltage vs. Output Current
350
300
250
200
150
100
50
250
200
150
REG5, REG7
REG4, REG6
100
50
0
VIN = 3.3V
150 200 250 300 350 400
VIN = 3.3V
0
0
50
100
0
50
100
150 200 250 300 350 400
Output Current (mA)
Output Current (mA)
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ACT8941A
Rev 0, 12-Mar-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG4, 5, 6, 7 Output Voltage vs. Temperature
Region of Stable COUT ESR vs. Output Current
1
4%
2%
VOUT ≤ 1.2V
0.1
0%
-2%
-4%
Stable ESR
VOUT > 1.2V
0.01
-40
-20
0
20
40
60
80
0
50
100
150
200
250
Temperature (°C)
Output Current (mA)
LDO Output Voltage Noise
CH1
CH1: VOUTx, 200µV/div (AC COUPLED)
TIME: 200ms/div
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ACT8941A
Rev 0, 12-Mar-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
VSYS Voltage vs. CHGIN Voltage
VSYS Voltage vs. VSYS Current
6.0
5.0
4.0
3.0
2.0
1.0
0
5.2
5.0
4.8
4.6
4.4
4.2
4.0
ACIN/CHGLEV = 01
ACIN/CHGLEV = 11
VSYS = 4.6V
0
2
4
6
8
10
0
500
1000
1500
2000
2500
CHGIN Voltage (V)
VSYS Current (mA)
Charger Current vs. Battery Voltage
Charger Current vs. Battery Voltage
500
450
400
350
300
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
VCHGIN = 5V
ACIN = 0
CHGLEV = 1
450mA USB
VBAT Falling
VBAT Rising
VCHGIN = 5V
ACIN = 0
VBAT Falling
CHGLEV = 0
VBAT Rising
90mA USB
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Battery Voltage (V)
Battery Voltage (V)
Charger Current vs. Battery Voltage
DCCC and Battery Supplement Modes
1200
1000
800
600
400
200
0
RISET = 2.4kꢀ
VCHGIN = 5V
CH4
CH3
CH2
ACIN/CHGLEV = 11
VBAT = 3.5V
VVSYS = 4.6V
VSYS = 0-1.8A
ICHARGE = 1000mA
CHGIN = 5.1V-3A
I
VBAT Falling
VBAT Rising
CH1
V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
CH1: IVSYS, 1.00A/div
CH2: IBAT, 1.00A/div
CH3: VBAT, 1.00V/div
CH4: VVSYS, 1V/div
TIME: 200ms/div
Battery Voltage (V)
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ACT8941A
Rev 0, 12-Mar-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
VAC Applied
VAC Removed
CH4
CH4
CH3
CH2
CH3
CH2
CH1
CH1
VCHGIN = 5V
VBAT = 3.5V
RVSYS = 100ꢀ
ACIN/CHGLEV = 01
VCHGIN = 5V
VBAT = 3.5V
RVSYS = 100ꢀ
ACIN/CHGLEV = 01
CH1: IBAT, 400mA/div
CH2: VBAT, 1V/div
CH3: VVSYS, 2V/div
CH4: VCHGIN, 5V/div
TIME: 40ms/div
CH1: IBAT, 200mA/div
CH2: VVSYS, 2V/div
CH3: VBAT, 1V/div
CH4: VCHGIN, 5V/div
TIME: 100ms/div
VAC Applied
VAC Removed
CH4
CH4
CH3
CH2
CH3
CH2
CH1
CH1
VCHGIN = 5V
VBAT = 3.97V
VCHGIN = 5V
VBAT = 3.97V
CH1: IBAT, 1A/div
CH2: VBAT, 2V/div
CH3: VVSYS, 2V/div
CH4: VCHGIN, 5V/div
TIME: 40ms/div
CH1: IBAT, 1A/div
CH2: VVSYS, 2V/div
CH3: VBAT, 2V/div
CH4: VCHGIN, 5V/div
TIME: 40ms/div
RVSYS = 47ꢀ
RVSYS = 47ꢀ
ACIN/CHGLEV = 11
ACIN/CHGLEV = 11
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ACT8941A
Rev 0, 12-Mar-13
SYSTEM CONTROL INFORMATION
Interfacing with the Rockchip RK2906/RK2918 Processor
The ACT8941A is optimized for use in applications
using the Rockchip RK2906/RK2918 processors,
supporting both the power domains as well as the
signal interface for these processors.
the ACT8941A pin names and the Rockchip
RK2906/RK2918 processor pin names are
provided. When this is done, the Rockchip
RK2906/RK2918 pin names are located after the
ACT8941A pin names, and are italicized and
located inside parentheses. For example, OUT1
(IO) refers to ACT8941A's OUT1 pin, identifying
that it is connected to the Rockchip
RK2906/RK2918’s IO power domain.
While the ACT8941A supports many possible
configurations for powering a processors, one of the
most common configurations is detailed in this
datasheet. In general, this document refers to the
ACT8941A pin names and functions. However, in
cases where the description of interconnections
between these devices benefits by doing so, both
Table 2:
ACT8941A and Rockchip RK2906/RK2918 Power Domains
POWER DOMAIN
ACT8941A CHANNEL TYPE DEFAULT VOLTAGE CURRENT CAPABILITY
IO, GSensor, NandFlash, USB_Host11,
TP VCC, CODEC_3.0V, Camera IO
etc.
REG1
DC/DC
3.0V
1100mA
DDR3
Core
REG2
REG3
DC/DC
DC/DC
1.5V
1.2V
1100mA
1200mA
ARM_PLL_2.5V, USB_PHY_2.5V,
RK2918_SAR-ADC_2.5V
REG4
REG5
LDO
LDO
2.5V
1.8V
320mA
320mA
Camera_1.8V
VCC_SD
REG6
REG7
LDO
LDO
3.0V
3.0V
320mA
320mA
LCD_VCC
Table 3:
ACT8941A and Rockchip RK2906/RK2918 Power Modes
POWER
QUIESCENT
CURRENT
CONTROL STATE
MODE
POWER DOMAIN STATE
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are on.
NORMAL
PWRHLD is asserted
420µA
SYSTEM
OFF
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are all off.
PWRHLD is de-asserted.
<18µA
Table 4:
ACT8941A and RK2906/RK2918 Signal Interface
ACT8941A
SCL
DIRECTION
RK2906/RK2918
I2C3_SCL
I2C3_SDA
GPIO4_D0
NPOR
SDA
VSEL
nRSTO
nIRQ
BAT_LOW
Power_KEY
Power_ON
nPBSTAT
PWRHLD
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ACT8941A
Rev 0, 12-Mar-13
SYSTEM CONTROL INFORMATION
Control Signals
automatically shuts down.
nPBSTAT Output
Enable Inputs
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage
(typically OUT1) through a 10kꢀ or greater resistor.
The ACT8941A features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWRHLD is a logic input, while nPBIN is a unique,
multi-function input.
nPBIN Multi-Function Input
ACT8941A features the nPBIN multi-function pin,
which combines system enable/disable control with
a hardware reset function. Select either of the two
pin functions by asserting this pin, either through a
direct connection to GA, or through a 50kꢀ resistor
to GA, as shown in Figure 2.
nRSTO Output
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires after
OUT1 reaches its power-OK threshold. When
asserted due to manual-reset, nRSTO immediately
asserts low, then remains asserted low until the
nPBIN input is de-asserted and the reset time-out
period expires.
Figure 2:
nPBIN Input
Connect a 10kꢀ or greater pull-up resistor from
nRSTO to an appropriate voltage supply (typically
OUT1).
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kꢀ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
ACT8941A
Warm/Cold Manual Reset Function
The second major function of the nPBIN input is to
provide warm and cold manual reset function. To
manually reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kꢀ).
An internal timer detects the duration of the manual
reset event.
Many of the ACT8941A's functions support
interrupt-generation as
a
result of various
conditions. These are typically masked by default,
but may be unmasked via the I2C interface. For
more information about the available fault
conditions, refer to the appropriate sections of this
datasheet.
Short Press/Warm Reset
When the manual reset button is pressed for less
than 130ms, ACT8941A commences a warm reset
operation where nRSTO immediately asserts low,
then remains asserted low until the manual reset
button is released for 130ms.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
Long Press / Cold Reset (Power Cycle)
When the manual reset button is pressed for more
than 130ms, ACT8941A commences a power cycle
routine in which case all regulators are turned off
and then turned back on after reset button is
released with all the registers reloaded to default
values. When the ACT8941A turns on again, it
stays enabled for 260ms, the PWRHLD need to be
asserted during this time so that the system
remains powered, otherwise the ACT8941A
Push-Button Control
The ACT8941A is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
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ACT8941A
Rev 0, 12-Mar-13
PWRHLD) before nPBIN is de-asserted. If the
microprocessor is unable to complete its power-up
routine successfully before the user releases the
push-button, the ACT8941A automatically shuts the
system down. This provides protection against
accidental or momentary assertions of the push-
button. If desired, longer “push-and-hold” times can
be implemented by simply adding an additional time
delay before asserting PWRHLD.
When the first regulator (REG1) reaches its power-
OK threshold, nRSTO is asserted low, resetting the
microprocessor. When REG1 reaches its power-OK
threshold for 2msꢀ, REG4 and REG5 are enabled.
When REG1 reaches its power-OK threshold for
4msꢀ, REG2 and REG3 are enabled. If REG1 is
above its power-OK threshold when the reset timer
expires, nRSTO is de-asserted, allowing the
microprocessor to begin its boot sequence. REG6
and REG7 can be enabled or disabled by I2C after
system powers up.
Control Sequences
The ACT8941A features a variety of control
sequences that are optimized for supporting system
During the boot sequence, the microprocessor must
assert PWRHLD, holding the regulators to ensure
that the system remains powered after nPBIN is
released.
enable and disable sequences of
RK2906/RK2918 application processor.
Rockchip
Enabling/Disabling Sequence
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes
before finally set MSTROFF[ ] bit to 1 to shut the
system down.
A typical enable sequence is initiated whenever the
following conditions occurs:
1) nPBIN is asserted low via 50Kꢀ resistance, or
2) A valid input voltage is present at CHGIN2
The enable sequence begins by enabling REG1.
Figure 3:
Enable/Disable Sequence
2
ꢀ: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.
2: Applicable only for ACT8941AQJ4##.
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ACT8941A
Rev 0, 12-Mar-13
FUNCTIONAL DESCRIPTION
I2C Interface
below the SYSLEV[-] voltage threshold:
1) If nSYSMODE[-] = 1 (default case), when system
The ACT8941A features an I2C interface that allows
advanced programming capability to enhance overall
system performance. To ensure compatibility with a
wide range of system processors, the I2C interface
supports clock speeds of up to 400kHz (“Fast-Mode”
operation) and uses standard I2C commands. I2C
write-byte commands are used to program the
ACT8941A, and I2C read-byte commands are used
to read the ACT8941A’s internal registers. The
ACT8941A always operates as a slave device, and
is addressed using a 7-bit slave address followed by
an eighth bit, which indicates whether the transaction
is a read-operation or a write-operation, [1011011x].
voltage level interrupt is unmasked
(nSYSLEVMSK[ ]=1) and VVSYS falls below the
programmable threshold, the ACT8941A asserts
nIRQ, providing a software “under-voltage alarm”.
The response to this interrupt is controlled by the
CPU, but will typically initiate a controlled shutdown
sequence either or alert the user that the battery is
low. In this case the interrupt is cleared when VVSYS
rises up again above the SYSLEV rising threshold
and nSYSSTAT[-] is read via I2C.
2) If nSYSMODE[-] = 0, when VVSYS falls below the
programmable threshold the ACT8941A shuts down,
immediately disabling all regulators. This option is
useful for implementing a programmable “under-
voltage lockout” function that forces the system off
when the battery voltage falls below the SYSLEV
threshold voltage. Since this option does not support
a controlled shutdown sequence, it is generally used
as a "fail-safe" to shut the system down when the
battery voltage is too low.
SDA is a bi-directional data line and SCL is a clock
input. The master device initiates a transaction by
issuing a START condition, defined by SDA
transitioning from high to low while SCL is high. Data
is transferred in 8-bit packets, beginning with the
MSB, and is clocked-in on the rising edge of SCL.
Each packet of data is followed by an “Acknowledge”
(ACK) bit, used to confirm that the data was
transmitted successfully.
Table 5:
For more information regarding the I2C 2-wire serial
SYSLEV Falling Threshold
interface,
go
to
the
NXP
website:
SYSLEV Falling Threshold
SYSLEV[3:0]
http://www.nxp.com.
(Hysteresis = 200mV)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Voltage Monitor and Interrupt
Programmable System Voltage Monitor
The ACT8941A features a programmable system-
voltage monitor, which monitors the voltage at VSYS
and compares it to a programmable threshold
voltage. The programmable voltage threshold is
programmed by SYSLEV[3:0], as shown in Table 5.
SYSLEV[ ] is set to 3.0V by default. There is a
200mV rising hysteresis on SYSLEV[ ] threshold
such that VVSYS needs to be 3.2V(typ) or higher in
order to power up the IC.
The nSYSSTAT[-] bit reflects the output of an
internal voltage comparator that monitors VVSYS
relative to the SYSLEV[-] voltage threshold, the
value of nSYSTAT[-] = 1 when VVSYS is lower than
the SYSLEV[-] voltage threshold, and nSYSTAT[-] =
0 when VVSYS is higher than the SYSLEV[-] voltage
threshold. Note that the SYSLEV[-] voltage threshold
is defined for falling voltages, and that the
comparator produces about 200mV of hysteresis at
VSYS. As a result, once VVSYS falls below the
SYSLEV threshold, its voltage must increase by
more than about 200mV to clear that condition.
Precision Voltage Detector
The LBI input connects to one input of a precision
voltage comparator, which can be used to monitor a
system voltage such as the battery voltage. An
external resistive-divider network can be used to set
voltage monitoring thresholds, as shown in
Functional Block Diagram. The output of the
comparator is present at the nLBO open-drain
output.
After the IC is powered up, the ACT8941A responds
in one of two ways when the voltage at VSYS falls
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ACT8941A
Rev 0, 12-Mar-13
Thermal Shutdown
The ACT8941A integrates thermal shutdown
protection circuitry to prevent damage resulting from
excessive thermal stress, as may be encountered
under fault conditions. This circuitry disables all
regulators if the ACT8941A die temperature exceeds
160°C, and prevents the regulators from being
enabled until the IC temperature drops by 20°C (typ).
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ACT8941A
Rev 0, 12-Mar-13
STEP-DOWN DC/DC REGULATORS
Despite the advantages of ceramic capacitors, care
must be taken during the design process to ensure
stable operation over the full operating voltage and
temperature range. Ceramic capacitors are
available in a variety of dielectrics, each of which
exhibits different characteristics that can greatly
affect performance over their temperature and
voltage ranges.
General Description
The ACT8941A features three synchronous, fixed-
frequency, current-mode PWM step down
converters that achieve peak efficiencies of up to
97%. REG1 and REG2 are capable of supplying up
to 1100mA of output current, while REG3 supports
up to 1200mA. These regulators operate with a
fixed frequency of 2MHz, minimizing noise in
sensitive applications and allowing the use of small
external components.
Two of the most common dielectrics are Y5V and
X5R. Whereas Y5V dielectrics are inexpensive and
can provide high capacitance in small packages,
their capacitance varies greatly over their voltage
and temperature ranges and are not recommended
for DC/DC applications. X5R and X7R dielectrics
are more suitable for output capacitor applications,
as their characteristics are more stable over their
operating ranges, and are highly recommended.
100% Duty Cycle Operation
Each regulator is capable of operating at up to
100% duty cycle. During 100% duty-cycle
operation, the high-side power MOSFET is held on
continuously, providing a direct connection from the
input to the output (through the inductor), ensuring
the lowest possible dropout voltage in battery
powered applications.
Inductor Selection
REG1, REG2, and REG3 utilize current-mode
control and a proprietary internal compensation
scheme to simultaneously simplify external
component selection and optimize transient
performance over their full operating range. These
devices were optimized for operation with 2.2μH
inductors, although inductors in the 1.5μH to 3.3μH
range can be used. Choose an inductor with a low
DC-resistance, and avoid inductor saturation by
choosing inductors with DC ratings that exceed the
maximum output current by at least 30%.
Synchronous Rectification
REG1, REG2, and REG3 each feature integrated n-
channel synchronous rectifiers, maximizing
efficiency and minimizing the total solution size and
cost by eliminating the need for external rectifiers.
Soft-Start
When enabled, each output voltages tracks an
internal 400μs soft-start ramp, minimizing input
current during startup and allowing each regulator
to power up in a smooth, monotonic manner that is
independent of output load conditions.
Configuration Options
Output Voltage Programming
Compensation
By default, each regulator powers up and regulates
to its default output voltage. Output voltage is
selectable by setting VSEL pin that when VSEL is
low, output voltage is programmed by VSET1[-]
bits, and when VSEL is high, output voltage is
programmed by VSET2[-] bits. However, once the
system is enabled, each regulator's output voltage
may be independently programmed to a different
value, typically in order to minimize the power
consumption of the microprocessor during some
operating modes. Program the output voltages via
the I2C serial interface by writing to the regulator's
VSET1[-] register if VSEL is low or VSET2[-]
register if VSEL is high as shown in Table 6.
Each buck regulator utilizes current-mode control
and a proprietary internal compensation scheme to
simultaneously simplify external component
selection and optimize transient performance over
its full operating range. No compensation design is
required; simply follow a few simple guidelines
described below when choosing external
components.
Input Capacitor Selection
The input capacitor reduces peak currents and
noise induced upon the voltage source. A 4.7μF
ceramic capacitor is recommended for each
regulator in most applications.
Enable / Disable Control
During normal operation, each buck may be
enabled or disabled via the I2C interface by writing
to that regulator's ON[ ] bit. The regulator accept
rising or falling edge of ON[ ] bit as on/off signal. To
enable the regulator, clear ON[ ] to 0 first then set to
Output Capacitor Selection
For most applications, 22μF ceramic output
capacitors are recommended for REG1, REG2 and
REG3.
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ACT8941A
Rev 0, 12-Mar-13
1. To disable the regulator, set ON[ ] to 1 first then
clear it to 0.
I2C interface. If an output voltage is lower than the
power-OK threshold, typically 7% below the
programmed regulation voltage, that regulator's
OK[ ] bit will be 0.
REG1, REG2, REG3 Turn-on Delay
Each of REG1, REG2 and REG3 features a
programmable Turn-on Delay which help ensure a
reliable qualification. This delay is programmed by
DELAY[2:0], as shown in Table 7.
If a DC/DC's nFLTMSK[-] bit is set to 1, the
ACT8941A will interrupt the processor if that
DC/DC's output voltage falls below the power-OK
threshold. In this case, nIRQ will assert low and
remain asserted until either the regulator is turned
off or back in regulation, and the OK[ ] bit has been
read via I2C.
Table 7:
REGx/DELAY[ ] Turn-On Delay
DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY
PCB Layout Considerations
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 ms
2 ms
High switching frequencies and large peak currents
make PC board layout an important part of step-
down DC/DC converter design. A good design
minimizes excessive EMI on the feedback paths
and voltage gradients in the ground plane, both of
which can result in instability or regulation errors.
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
close as possible to the IC, and avoiding the use of
via if possible. The inductor, input filter capacitor,
and output filter capacitor should be connected as
close together as possible, with short, direct, and
wide traces. The ground nodes for each regulator's
power loop should be connected at a single point in
a star-ground configuration, and this point should
be connected to the backside ground plane with
multiple via. The output node for each regulator
should be connected to its corresponding OUTx pin
through the shortest possible route, while keeping
sufficient distance from switching nodes to prevent
noise injection. Finally, the exposed pad should be
directly connected to the backside ground plane
using multiple via to achieve low electrical and
thermal resistance.
Operating Mode
By default, REG1, REG2, and REG3 each operate
in fixed-frequency PWM mode at medium to heavy
loads, while automatically transitioning to
a
proprietary power-saving mode at light loads in
order to maximize standby battery life. In
applications where low noise is critical, force fixed-
frequency PWM operation across the entire load
current range, at the expense of light-load
efficiency, by setting the MODE[ ] bit to 1.
OK[ ] and Output Fault Interrupt
Each DC/DC features a power-OK status bit that
can be read by the system microprocessor via the
Table 6:
REGx/VSET[ ] Output Voltage Setting
REGx/VSET[5:3]
REGx/VSET[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.100
2.150
2.200
2.250
2.300
2.350
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
3.600
3.700
3.800
3.900
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ACT8941A
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LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS
or falling edge of ON[ ] bit as on/off signal. To
enable the regulator, clear ON[ ] to 0 first then set to
1. To disable the regulator, set ON[ ] to 1 first then
clear it to 0.
General Description
REG4, REG5, REG6, and REG7 are low-noise,
low-dropout linear regulators (LDOs) that supply up
to 320mA. Each LDO has been optimized to
achieve low noise and high-PSRR, achieving more
than 65dB PSRR at frequencies up to 10kHz.
REG4, REG5, REG6, REG7 Turn-on Delay
Each of REG4, REG5, REG6 and REG7 features a
programmable Turn-on Delay which help ensure a
reliable qualification. This delay is programmed by
DELAY[2:0], as shown in Table 7.
Output Current Limit
Each LDO contains current-limit circuitry featuring a
current-limit fold-back function. During normal and
moderate overload conditions, the regulators can
support more than their rated output currents.
During extreme overload conditions, however, the
current limit is reduced by approximately 30%,
reducing power dissipation within the IC.
Output Discharge
Each of the ACT8941A’s LDOs features an optional
output discharge function, which discharges the
output to ground through a 1.5kꢀ resistance when
the LDO is disabled. This feature may be enabled
or disabled by setting DIS[-]; set DIS[-] to 1 to
enable this function, clear DIS[-] to 0 to disable it.
Compensation
The LDOs are internally compensated and require
very little design effort, simply select input and
output capacitors according to the guidelines below.
Low-Power Mode
Each of ACT8941A's LDOs features a LOWIQ[-] bit
which, when set to 1, reduces the LDO's quiescent
current by about 16%, saving power and extending
battery lifetime.
Input Capacitor Selection
Each LDO requires a small ceramic input capacitor
to supply current to support fast transients at the
input of the LDO. Bypassing each INL pin to GA
with 1μF. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
OK[ ] and Output Fault Interrupt
Each LDO features a power-OK status bit that can
be read by the system microprocessor via the
interface. If an output voltage is lower than the
power-OK threshold, typically 11% below the
programmed regulation voltage, the value of that
regulator's OK[-] bit will be 0.
Output Capacitor Selection
Each LDO requires a 3.3μF ceramic output
capacitor for stability. For best performance, each
output capacitor should be connected directly
between the output and GA pins, as close to the
output as possible, and with a short, direct
connection. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
If a LDO's nFLTMSK[-] bit is set to 1, the
ACT8941A will interrupt the processor if that LDO's
output voltage falls below the power-OK threshold.
In this case, nIRQ will assert low and remain
asserted until either the regulator is turned off or
back in regulation, and the OK[-] bit has been read
via I2C.
Configuration Options
PCB Layout Considerations
Output Voltage Programming
The ACT8941A’s LDOs provide good DC, AC, and
noise performance over a wide range of operating
conditions, and are relatively insensitive to layout
considerations. When designing a PCB, however,
careful layout is necessary to prevent other circuitry
from degrading LDO performance.
By default, each LDO powers up and regulates to
its default output voltage. Once the system is
enabled, each output voltage may be independently
programmed to a different value by writing to the
regulator's VSET[-] register via the I2C serial
interface as shown in Table 6.
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
close proximity to noisy nodes, particularly the SW
Enable / Disable Control
During normal operation, each LDO may be
enabled or disabled via the I2C interface by writing
to that LDO's ON[ ] bit. The regulator accept rising
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ACT8941A
Rev 0, 12-Mar-13
nodes of the DC/DCs.
REFBP is a noise-filtered reference, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
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ACT8941A
Rev 0, 12-Mar-13
ActivePathTM CHARGER
General Description
In an input over-voltage condition this circuit limits
VVSYS to 4.6V, protecting any circuitry connected to
VSYS from the over-voltage condition, which may
exceed this circuitry's voltage capability. This circuit
is capable of withstanding input voltages of up to
12V.
The ACT8941A features an advanced battery
charger that incorporates the patent-pending
ActivePath architecture for system power selection.
This combination of circuits provides a complete,
advanced battery-management system that
automatically selects the best available input
supply, manages charge current to ensure system
power availability, and provides a complete, high-
accuracy (±0.5%), thermally regulated, full-featured
single-cell linear Li+ charger that can withstand
input voltages of up to 12V.
Table 8:
Input Over-Voltage Protection Setting
OVPSET[1]
OVPSET[0]
OVP THRESHOLD
0
0
1
1
0
1
0
1
6.6V
7.0V
7.5V
8.0V
ActivePath Architecture
The ActivePath architecture performs three
important functions:
Input Supply Overload Protection
1) System Configuration Optimization
2) Input Protection
The ActivePath circuitry monitors and limits the total
current drawn from the input supply to a value set
by the ACIN and CHGLEV inputs, as well as the
resistor connected to ISET. Drive ACIN to a logic-
low for “USB Mode”, which limits the input current to
either 100mA, when CHGLEV is driven to a logic-
low, or 450mA, when CHGLEV is driven to a logic-
high. Drive ACIN to a logic-high for “AC-Mode”,
which limits the input current to 2A, typically.
3) Battery-Management
System Configuration Optimization
The ActivePath circuitry monitors the state of the
input supply, the battery, and the system, and
automatically reconfigures itself to optimize the
power system. If a valid input supply is present,
ActivePath powers the system from the input while
charging the battery in parallel. This allows the
battery to charge as quickly as possible, while
supplying the system. If a valid input supply is not
present, ActivePath powers the system from the
battery. Finally, if the input is present and the
system current requirement exceeds the capability
of the input supply, ActivePath allows system power
to be drawn from both the battery and the input
supply.
Input Under Voltage Lockout
If the input voltage applied to CHGIN falls below
3.5V (typ), an input under-voltage condition is
detected and the charger is disabled. Once an input
under-voltage condition is detected, a new charge
cycle will initiate when the input exceeds the under-
voltage threshold by at least 500mV.
Battery Management
The ACT8941A features a full-featured, intelligent
charger for Lithium-based cells, and was designed
specifically to provide a complete charging solution
with minimum system design effort.
Input Protection
Input Over-Voltage Protection
The core of the charger is a CC/CV (Constant-
Current/Constant-Voltage), linear-mode charge
controller. This controller incorporates current and
voltage sense circuitry, an internal 70mꢀ power
The ActivePath circuitry features input over-voltage
protection circuitry. This circuitry disables charging
when the input voltage exceeds the voltage set by
OVPSET[-] as shown in Table 8, but stands off the
input voltage in order to protect the system. Note
that the adjustable OVP threshold is intended to
provide the charge cycle with adjustable immunity
against upward voltage transients on the input, and
is not intended to allow continuous charging with
input voltages above the charger's normal operating
voltage range. Independent of the OVPSET[-]
setting, the charge cycle is not allowed to resume
until the input voltage falls back into the charger's
normal operating voltage range (i.e. below 6.0V).
MOSFET, thermal-regulation circuitry,
a
full-
featured state machine that implements charge
control and safety features, and circuitry that
eliminates the reverse blocking diode required by
conventional charger designs.
The charge termination voltage is highly accurate
(±0.5%), and features a selection of charge safety
time-out periods that protect the system from
operation with damaged cells. Other features
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ACT8941A
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include pin-programmable fast-charge current and
one current-limited nSTAT output that can directly
drive LED indicator or provide a logic-level status
logic-low.
The ACT8941A's charge current settings are
summarized in Table 9.
signal to the host microprocessor.
Note that the actual charge current may be limited
to a current lower than the programmed fast charge
current due to the ACT8941A’s internal thermal
regulation loop. See the Thermal Regulation section
for more information.
Dynamic Charge Current Control (DCCC)
The ACT8941A's ActivePath charger features
dynamic charge current control (DCCC) circuitry,
which acts to ensure that the system remains
powered while operating within the maximum output
capability of the power adapter. The DCCC circuitry
continuously monitors VVSYS, and if the voltage at
VSYS drops by more than 200mV, the DCCC
circuitry automatically reduces charge current in
order to prevent VVSYS from continuing to drop.
Charger Input Interrupts
In order to ease input supply detection and
eliminate the size and cost of external detection
circuitry, the charger has the ability to generate
interrupts based upon the status of the input supply.
This function is capable of generating an interrupt
when the input is connected, disconnected, or both.
An interrupt is generated any time the input supply
is connected when INSTAT[ ] bit is set to 1 and the
INCON[-] bit is set to 1, and an interrupt is
generated any time the input supply is disconnected
when INSTAT[ ] bit is set to 1 and the INDIS[ ] bit is
set to 1.
Charge Current Programming
The ACT8941A's ActivePath charger features a
flexible charge current-programming scheme that
combines the convenience of internal charge
current programming with the flexibility of resistor
based charge current programming. Current limits
and charge current programming are managed as a
function of the ACIN and CHGLEV pins, in
combination with RISET, the resistance connected to
the ISET pin.
INDAT[-] indicates the status of the CHGIN input
supply. A value of 1 indicates that a valid CHGIN
input (CHGIN UVLO Threshold<VCHGIN<CHGIN
OVP Threshold) is present, a value of 0 indicates a
valid input is not present.
ACIN is a logic input that configures the current-limit
of ActivePath's linear regulator as well as that of the
battery charger. ACIN features a precise 1.2V logic
threshold, so that the input voltage detection
threshold may be adjusted with a simple resistive
voltage divider. This input also allows a simple, low-
cost dual-input charger switch to be implemented
with just a few, low-cost components.
When an interrupt is generated by the input supply,
reading the INSTAT[ ] returns a value of 1.
INSTAT [ ] is automatically cleared to 0 upon
reading. When no interrupt is generated by the
input supply, reading the INSTAT[ ] returns a value
of 0.
When the voltage at ACIN is above the 1.2V
threshold, the charger operates in “AC-Mode” with a
charge current programmed by RISET, and the RISET
is given by:
When responding to an Input Status Interrupt, it is
often useful to know the state of the ACIN input. For
example, in
a
dual-input charger application
knowing the state of the ACIN input can identify
which type of input supply has been connected. The
state of the ACIN input can be read at any time by
reading the ACINSTAT[-] bit, where a value of 1
indicates that the voltage at ACIN is above the 1.2V
threshold (indicating that a wall-cube has been
attached), and a value of 0 indicates that the
voltage is below this threshold (indicating that ACIN
input is not valid and USB supply input is selected).
R
ISET (kꢀ) = 2336 × (1V/ICHG (mA)) - 0.205
With a given RISET then charge current will reduce 5
times when CHGLEV is driven low.
When ACIN is below the 1.2V threshold, the
charger operates in “USB-Mode”, with a maximum
CHGIN input current and charge current defined by
the CHGLEV input; 450mA, if CHGLEV is driven to
a logic-high, or 100mA, if CHGLEV is driven to a
Table 9:
ACIN and CHGLEV Inputs
CHARGE CURRENT
PRECONDITION CHARGE CURRENT
(mA)
ACIN
CHGLEV
(mA)
0
0
1
1
0
1
0
1
90
45
450
CHG/5
ICHG
45
I
10% × ICHG
10% × ICHG
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ACT8941A
Rev 0, 12-Mar-13
Figure 4:
Typical Li+ charge profile and ACT8941A charge states
A: PRECONDITION State
B: FAST-CHARGE State
C: TOP-OFF State
D: END-OF-CHARGE State
Figure 5:
Charger State Diagram
TEMP NOT OK
ANY STATE
(VCHGIN < VBAT) OR (VCHGIN < VCHGIN UVLO)
OR (VCHGIN > VOVP) OR (SUSCHG[ ] = 1)
SUSPEND
TEMP-FAULT
(VCHGIN > VBAT) AND (VCHGIN > VCHGIN UVLO)
AND (VCHGIN < VOVP) AND (SUSCHG[ ] = 0)
TEMP OK
PRECONDITION
TIME-OUT-FAULT
PRECONDITION
Time-out
(VBAT > 2.85V) AND
(TQUAL = 32ms)
Total Time-out
FAST-CHARGE
(VBAT = VTERM ) AND
(TQUAL = 32ms)
(VBAT < VTERM - 205mV )
AND (TQUAL = 32ms)
TOP-OFF
(IBAT < 10% x ICHG) OR (Total
Time-out) AND (TQUAL = 32ms)
END-OF-CHARGE
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ACT8941A
Rev 0, 12-Mar-13
minimizing battery current drain and allowing the
cell to “relax”. The charger continues to monitor the
cell voltage, and re-initiates a charging sequence if
the cell voltage drops to 205mV (typ) below the
charge termination voltage.
Charge-Control State Machine
PRECONDITION State
new charging cycle begins with the
A
PRECONDITION state, and operation continues in
this state until VBAT exceeds the Precondition
Threshold Voltage. When operating in
PRECONDITION state, the cell is charged at 10%
of the programmed maximum fast-charge constant
SUSPEND State
The state-machine jumps to the SUSPEND state
any time the battery is removed, and any time the
input voltage either falls below the CHGIN UVLO
threshold or exceeds the OVP threshold. Once
none of these conditions are present, a new charge
cycle initiates.
current, ICHG
.
Once VBAT reaches the Precondition Threshold
Voltage, the state machine jumps to the FAST-
CHARGE state. If VBAT does not reach the
Precondition Threshold Voltage before the
Precondition Time-out period expires, then the state
machine jumps to the TIME-OUT-FAULT state in
order to prevent charging a damaged cell. See the
Charge Safety Timers section for more information.
A charging cycle may also be suspended manually
by setting the SUSPEND[ ] bit. In this case, initiate
a new charging sequence by clearing SUSPEND[ ]
to 0.
State Machine Interrupts
FAST-CHARGE State
The charger features the ability to generate
interrupts when the charger state machine
transitions, based upon the status of the CHG_ bits.
Set CHGEOCIN[ ] bit to 1 and CHGSTAT[ ] bit to 1
to generate an interrupt when the charger state
machine goes into the END-OF-CHARGE (EOC)
state. Set CHGEOCOUT[ ] bit to 1 and CHGSTAT[ ]
bit to 1 to generate an interrupt when the charger
state machine exits the EOC state.
In the FAST-CHARGE state, the charger operates
in constant-current (CC) mode and regulates the
charge current to the current set by RISET . Charging
continues in CC mode until VBAT reaches the charge
termination voltage (VTERM), at which point the state-
machine jumps to the TOP-OFF state. If VBAT does
not reach VTERM before the total time out period
expires then the state-machine will jump to the
“EOC” state and will re-initiate a new charge cycle
after 32ms “relax”. See the Current Limits and
Charge Current Programming sections for more
information about setting the maximum charge
current.
CHGDAT[ ] indicates the status of the charger state
machine. A value of 1 indicates that the charger
state machine is in END-OF-CHARGE state, a
value of 0 indicates the charger state machine is in
other states.
When an interrupt is generated by the charger state
machine, reading the CHGSTAT[ ] returns a value
of 1. CHGSTAT[ ] is automatically cleared to 0 upon
reading. When no interrupt is generated by the
charger state machine, reading the CHGSTAT[ ]
returns a value of 0.
TOP-OFF State
In the TOP-OFF state, the cell charges in constant-
voltage (CV) mode. In CV mode operation, the
charger regulates its output voltage to the 4.20V
charge termination voltage, and the charge current
is naturally reduced as the cell approaches full
charge. Charging continues until the charge current
drops to END-OF-CHARGE current threshold, at
which point the state machine jumps to the END-
OF-CHARGE (EOC) state.
For additional information about the charge cycle,
CSTATE[1:0] may be read at any time via I2C to
determine the current charging state.
Table 10:
If the state-machine does not jump out of the TOP-
OFF state before the Total-Charge Time-out period
expires, then the state machine jumps to the EOC
state and will re-initiate a new charge cycle if VBAT
falls below termination voltage 205mV (typ). For
more information about the charge safety timers,
see the Charging Safety Times section.
Charging Status Indication
CSTATE[1] CSTATE[0] STATE MACHINE STATUS
1
1
1
0
PRECONDITION State
FAST-CHARGE/
TOP-OFF State
0
0
1
0
END-OF-CHARGE State
END-OF-CHARGE (EOC) State
In the END-OF-CHARGE (EOC) state, the charger
SUSPEND/DISABLED/
FAULT State
presents
a
high-impedance to the battery,
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ACT8941A
Rev 0, 12-Mar-13
Table 12:
Thermal Regulation
Total Safety Timer Setting
The charger features an internal thermal regulation
loop that monitors die temperature and reduces
charging current as needed to ensure that the die
temperature does not exceed the thermal regulation
threshold of 110°C. This feature protects against
excessive junction temperature and makes the
device more accommodating to aggressive thermal
designs. Note, however, that attention to good
thermal designs is required to achieve the fastest
possible charge time by maximizing charge current.
TOTAL TIME-OUT
PERIOD
TOTTIMO[1] TOTTIMO[0]
0
0
1
1
0
1
0
1
3 hrs
4 hrs
5 hrs
Disabled
Charge Status Indicator
Charge Safety Timers
The charger provides a charge-status indicator
output, nSTAT. nSTAT is an open-drain output
which sinks current when the charger is in an
active-charging state, and is high-Z otherwise.
nSTAT features an internal 8mA current limit, and is
capable of directly driving a LED without the need
of a current-limiting resistor or other external
circuitry. To drive an LED, simply connect the LED
between nSTAT pin and an appropriate supply,
such as VSYS. For a logic-level charge status
indication, simply connect a resistor from nSTAT to
an appropriate voltage supply.
The charger features programmable charge safety
timers which help ensure a safe charge by
detecting potentially damaged cells. These timers
are programmable via the PRETIMO[1:0] and
TOTTIMO[1:0] bits, as shown in Table 11 and Table
12. Note that in order to account for reduced charge
current resulting from DCCC operation in thermal
regulation mode, the charge time-out periods are
extended proportionally to the reduction in charge
current. As a result, the actual safety period may
exceed the nominal timer period.
Charger Timer Interrupts
Table 13:
The charger features the ability to generate
interrupts based upon the status of the charge
Charging Status Indication
STATE
PRECONDITION
FAST-CHARGE
TOP-OFF
nSTAT
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
timers. Set the TIMRPRE[
]
bit to
1
and
TIMRSTAT[ ] bit to 1 to generate an interrupt when
the Precondition Timer expires. Set the TIMRTOT[ ]
bit to 1 and TIMRSTAT[ ] bit to 1 to generate an
interrupt when the Total-Charge Timer expires.
TIMRDAT[ ] indicates the status of the charge
timers. A value of 1 indicates a precondition time-
out or a total charge time-out occurs, a value of 0
indicates other cases.
END-OF-CHARGE
SUSPEND
TEMPERATURE FAULT
TIME-OUT-FAULT
When an interrupt is generated by the charge
timers, reading the TIMRSTAT[ ] returns a value of
1. TIMRSTAT[ ] is automatically cleared to 0 upon
reading. When no interrupt is generated by the
charge timers, reading the TIMRSTAT[ ] returns a
value of 0.
Reverse-Current Protection
The charger includes internal reverse-current
protection circuitry that eliminates the need for
blocking diodes, reducing solution size and cost as
well as dropout voltage relative to conventional
battery chargers. When the voltage at CHGIN falls
below VBAT, the charger automatically reconfigures
its power switch to minimize current drawn from the
battery.
Table 11:
PRECONDITION Safety Timer Setting
PRECONDITION
PRETIMO[1] PRETIMO[0]
TIME-OUT PERIOD
0
0
1
1
0
1
0
1
40 mins
60 mins
80 mins
Disabled
Battery Temperature Monitoring
In a typical application, the TH pin is connected to
the battery pack's thermistor input, as shown in
Figure 6. The charger continuously monitors the
temperature of the battery pack by injecting a
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ACT8941A
Rev 0, 12-Mar-13
102μA (typ) current into the thermistor (via the TH
pin) and sensing the voltage at TH. The voltage at
TH is continuously monitored, and charging is
suspended if the voltage at TH exceeds either of
the internal VTHH and VTHL thresholds of 0.5V and
2.51V, respectively.
Figure 6:
Simple Configuration
ACT8941A
The net resistance (from TH to GA) required to
cross the thresholds are given by:
102μA × RNOM × kHOT = 0.5V → RNOM × kHOT
≈ 5kꢀ
102μA × RNOM × kCOLD = 2.51V → RNOM ×
kCOLD ≈ 25kꢀ
where RNOM is the nominal thermistor resistance
at room temperature, and kHOT and kCOLD
represent the ratios of the thermistor's resistance at
the desired hot and cold thresholds, respectively, to
the resistance at 25°C.
Battery Temperature Interrupts
In order to ease detecting the status of the battery
temperature, the charger features the ability to
generate interrupts based upon the status of the
battery temperature. Set the TEMPOUT[ ] bit to 1
and TEMPSTAT[ ] bit to 1 to generate an interrupt
when battery temperature goes out of the valid
temperature range. Set the TEMPIN[ ] bit to 1 and
TEMPSTAT[ ] bit to 1 to generate an interrupt when
battery temperature returns to the valid range.
TEMPDAT[ ] indicates the status of the battery
temperature. A value of 1 indicates the battery
temperature is inside of the valid range, a value of 0
indicates the battery is outside of the valid range.
When an interrupt is generated by the battery
temperature event, reading the TEMPSTAT[ ]
returns a value of 1. TEMPSTAT[ ] is automatically
cleared to 0 upon reading. When no interrupt is
generated by the battery temperature event,
reading the TEMPSTAT[ ] returns a value of 0.
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ACT8941A
Rev 0, 12-Mar-13
TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
SYMBOL
MIN
MAX
MIN
MAX
A
A1
A2
b
0.700
0.800
0.028
0.031
0.200 REF
0.008 REF
0.000
0.150
4.900
4.900
3.450
3.450
0.050
0.250
5.100
5.100
3.750
3.750
0.000
0.006
0.193
0.193
0.136
0.136
0.002
0.010
0.201
0.201
0.148
0.148
D
E
D2
E2
e
0.400 BSC
0.016 BSC
L
0.300
0.500
0.012
0.020
R
0.300
0.012
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ACT8941A
Rev 0, 12-Mar-13
REVISION HISTORY
REVISION
DATE
12 Mar 2013
DESCRIPTION
Rev 0
Initial release.
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
sales@active-semi.com or visit http://www.active-semi.com.
is a registered trademark of Active-Semi.
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ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
Copyright © 2013 Active-Semi, Inc.
I2CTM is a trademark of NXP.
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