5962-89481022A [ADI]
CMOS 12-Bit Monolithic Multiplying DAC; CMOS 12位单片乘法DAC
| 型号： | 5962-89481022A |
| 厂家： | 
ADI |
| 描述： | CMOS 12-Bit Monolithic Multiplying DAC |
| 文件： | 总8页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS
a
12-Bit Monolithic Multiplying DAC
AD7541A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Improved Version of AD7541
Full Four-Quadrant Multiplication
12-Bit Linearity (Endpoint)
All Parts Guaranteed Monotonic
TTL/CMOS Compatible
10kΩ
10kΩ
10kΩ
V
REF
20kΩ
20kΩ
S2
20kΩ
20kΩ
20kΩ
S1
S3
S12
Low Cost
Protection Schottky Diodes Not Required
Low Logic Input Leakage
OUT2
OUT1
10kΩ
R
FEEDBACK
GENERAL DESCRIPTION
BIT 1 (MSB)
BIT 2
BIT 3
BIT 12 (LSB)
The Analog Devices AD7541A is a low cost, high performance
12-bit monolithic multiplying digital-to-analog converter. It is
fabricated using advanced, low noise, thin film on CMOS
technology and is available in a standard 18-lead DIP and in
20-terminal surface mount packages.
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO I
FOR
OUT1
ITS DIGITAL INPUT IN A "HIGH" STATE.
PRODUCT HIGHLIGHTS
Compatibility: The AD7541A can be used as a direct replace-
ment for any AD7541-type device. As with the Analog Devices
AD7541, the digital inputs are TTL/CMOS compatible and
have been designed to have a ±1 µA maximum input current
requirement so as not to load the driving circuitry.
The AD7541A is functionally and pin compatible with the in-
dustry standard AD7541 device and offers improved specifica-
tions and performance. The improved design ensures that the
device is latch-up free so no output protection Schottky diodes
are required.
Improvements: The AD7541A offers the following improved
specifications over the AD7541:
This new device uses laser wafer trimming to provide full 12-bit
endpoint linearity with several new high performance grades.
1. Gain Error for all grades has been reduced with premium
ORDERING GUIDE1
grade versions having a maximum gain error of ±3 LSB.
2. Gain Error temperature coefficient has been reduced to
Relative
Gain
Error
2 ppm/°C typical and 5 ppm/°C maximum.
Temperature
Range
Accuracy
Package
Model2
TMIN to TMAX TA = +25؇C Options3
3. Digital-to-analog charge injection energy for this new device
is typically 20% less than the standard AD7541 part.
AD7541AJN 0°C to +70°C
AD7541AKN 0°C to +70°C
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1/2 LSB
±1 LSB
±6 LSB
±1 LSB
±6
±1
±1
±6 LSB
±1 LSB
±6 LSB
±1 LSB
±6 LSB
±1 LSB
N-18
N-18
P-20A
P-20A
R-18
Q-18
Q-18
Q-18
Q-18
E-20A
E-20A
4. Latch-up proof.
AD7541AJP
0°C to +70°C
AD7541AKP 0°C to +70°C
AD7541AKR 0°C to +70°C
AD7541AAQ –25°C to +85°C
AD7541ABQ –25°C to +85°C
5. Improvements in laser wafer trimming provides 1/2 LSB max
differential nonlinearity for top grade devices over the operat-
ing temperature range (vs. 1 LSB on older 7541 types).
±1/2 LSB
AD7541ASQ –55°C to +125°C ±1 LSB
AD7541ATQ –55°C to +125°C ±1/2 LSB
AD7541ASE –55°C to +125°C ±1 LSB
AD7541ATE –55°C to +125°C ±1/2 LSB
6. All grades are guaranteed monotonic to 12 bits over the
operating temperature range.
NOTES
1Analog Devices reserves the right to ship either ceramic (D-18) or cerdip (Q-18)
hermetic packages.
2To order MIL-STD-883, Class B process parts, add /883B to part number. Contact
local sales office for military data sheet.
3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = Small Outline IC.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1997
(V = +15 V, VREF = +10 V; OUT 1 = OUT 2 = GND = 0 V unless otherwise noted)
AD7541A–SPECIFICATIONS
DD
TA
=
TA =
TMIN, TMAX
1
Parameter
Version
+25؇C
Units
Test Conditions/Comments
ACCURACY
Resolution
All
12
12
Bits
Relative Accuracy
J, A, S
K, B, T
J, A, S
K, B, T
J, A, S
K, B, T
±1
±1/2
±1
±1/2
±6
±3
±1
±1/2
±1
±1/2
±8
±5
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
±1 LSB = ±0.024% of Full Scale
±1/2 LSB = ±0.012% of Full Scale
All Grades Guaranteed Monotonic
Differential Nonlinearity
Gain Error
to 12 Bits, TMIN to TMAX.
Measured Using Internal RFB and Includes
Effect of Leakage Current and Gain TC.
Gain Error Can Be Trimmed to Zero.
Gain Temperature Coefficient2
⌬Gain/⌬Temperature
Output Leakage Current
OUT1 (Pin 1)
All
5
5
ppm/°C max
Typical Value Is 2 ppm/°C.
J, K
A, B
S, T
J, K
A, B
S, T
±5
±5
±5
±5
±5
±5
±10
±10
±200
±10
±10
nA max
nA max
nA max
nA max
nA max
nA max
All Digital Inputs = 0 V.
OUT2 (Pin 2)
All Digital Inputs = VDD.
±200
REFERENCE INPUT
Input Resistance (Pin 17 to GND)
All
7–18
7–18
kΩ min/max
Typical Input Resistance = 11 kΩ.
Typical Input Resistance Temperature
Coefficient = –300 ppm/°C.
DIGITAL INPUTS
V
IH (Input HIGH Voltage)
All
All
All
All
2.4
0.8
±1
8
2.4
0.8
±1
8
V min
VIL (Input LOW Voltage)
V max
µA max
pF max
I
IN (Input Current)
Logic Inputs Are MOS Gates. IIN typ (25°C) = 1 nA.
VIN = 0 V
CIN (Input Capacitance)2
POWER SUPPLY REJECTION
⌬Gain/⌬VDD
All
±0.01
±0.02
% per % max
⌬VDD = ±5%
POWER SUPPLY
V
IDD
DD Range
All
All
+5 to +16
2
+5 to +16
2
V min/V max
mA max
Accuracy Is Not Guaranteed Over This Range.
All Digital Inputs VIL or VIH
.
100
500
µA max
All Digital Inputs 0 V or VDD.
AC PERFORMANCE CHARACTERISTICS
These Characteristics are included for Design Guidance only and are not subject to test. VDD = +15 V, VIN = +10 V except where noted,
OUT1 = 0UT2 = GND = 0 V, Output Amp is AD544 except where noted.
TA
+25؇C
=
TA
=
Parameter
Version1
TMIN, TMAX
Units
Test Conditions/Comments
1
PROPAGATION DELAY (From Digital Input
Change to 90% of Final Analog Output)
OUT 1 Load = 100 Ω, CEXT = 13 pF.
Digital Inputs = 0 V to VDD or VDD to 0 V.
All
100
—
ns typ
DIGITAL TO ANALOG GLITCH
IMPULSE
VREF = 0 V. All digital inputs 0 V to VDD or
VDD to 0 V.
All
1000
—
nV-sec typ
Measured using Model 50K as output amplifier.
MULTIPLYING FEEDTHROUGH ERROR3
(VREF to OUT1)
All
All
1.0
0.6
—
—
mV p-p typ
VREF = ±10 V, 10 kHz sine wave.
OUTPUT CURRENT SETTLING TIME
µs typ
To 0.01% of full-scale range.
OUT 1 Load = 100 Ω, CEXT = 13 pF.
Digital Inputs = 0 V to VDD or VDD to 0 V.
OUTPUT CAPACITANCE
C
C
OUT1 (Pin 1)
OUT2 (Pin 2)
All
All
All
All
200
70
70
200
70
70
pF max
pF max
pF max
pF max
Digital Inputs
= VIH
Digital Inputs
= VIL
COUT1 (Pin 1)
COUT2 (Pin 2)
200
200
NOTES
1Temperature range as follows: J, K versions, 0°C to +70°C; A, B versions, –25°C to +85°C; S, T versions, –55°C to +125°C.
2Guaranteed by design but not production tested.
3To minimize feedthrough in the ceramic package (Suffix D) the user must ground the metal lid.
Specifications subject to change without notice.
–2–
REV. B
AD7541A
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature Range
(TA = +25°C unless otherwise noted)
Commercial (J, K Versions) . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . –25°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Digital Input Voltage to GND . . . . . . . . –0.3 V, VDD + 0.3 V
OUT 1, OUT 2 to GND . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Power Dissipation (Any Package)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7541A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
OUTPUT LEAKAGE CURRENT
Current which appears at OUTI with the DAC loaded to all 0s
or at OUT2 with the DAC loaded to all 1s.
TERMINOLOGY
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is expressed in % of full-
scale range or (sub)multiples of 1 LSB.
MULTIPLYING FEEDTHROUGH ERROR
AC error due to capacitive feedthrough from VREF terminal to
OUT1 with DAC loaded to all 0s.
OUTPUT CURRENT SETTLING TIME
Time required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, i.e., 0 to full
scale.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal l LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range insures monotonicity.
PROPAGATION DELAY
This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
GAIN ERROR
Gain error is a measure of the output error between an ideal
DAC and the actual device output. For the AD7541A, ideal
maximum output is
DIGITAL-TO-ANALOG CHARGE INJECTION (QDA)
This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with VREF = GND and a Model 50K as the
output op amp, C1 (phase compensation) = 0 pF.
4095
4096
–
(VREF ).
Gain error is adjustable to zero using external trims as shown in
Figures 4, 5 and 6.
PIN CONFIGURATIONS
DIP/SOIC
LCCC
PLCC
1
2
3
4
5
6
7
8
9
18
17
16
R
V
OUT1
OUT2
FEEDBACK
3
2
1
20 19
3
2
1
20 19
IN
REF
V
(+)
GND
DD
PIN 1
IDENTIFIER
GND
BIT 1 (MSB)
BIT 2
4
5
6
18
17
16
V
18
17
16
15
14
4
5
6
V
DD
GND
BIT 1 (MSB)
BIT 2
DD
15 BIT 12 (LSB)
BIT 1 (MSB)
BIT 2
BIT 12 (LSB)
BIT 11
AD7541A
BIT 12 (LSB)
BIT 11
AD7541A
TOP VIEW
AD7541A
TOP VIEW
(Not to Scale)
TOP VIEW 14 BIT 11
(Not to Scale)
(Not to Scale)
BIT 3 7
BIT 4 8
BIT 10
BIT 3
BIT 10
BIT 9
BIT 8
13
12
11
BIT 3
15 BIT 10
BIT 9
7
8
BIT 9
BIT 4
BIT 4
14
BIT 5
9
10 11 12 13
9
10 11 12
13
BIT 6
10 BIT 7
NC = NO CONNECT
NC = NO CONNECT
REV. B
–3–
AD7541A
GENERAL CIRCUIT INFORMATION
APPLICATIONS
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at Pin 17, the circuit is a unipolar D/A converter. With an
ac reference voltage or current, the circuit provides 2-quadrant
multiplication (digitally controlled attenuation). The input/
output relationship is shown in Table II.
10kΩ
10kΩ
10kΩ
V
REF
20kΩ
20kΩ
S2
20kΩ
20kΩ
20kΩ
S1
S3
S12
R1 provides full-scale trim capability [i.e., load the DAC register
to 1111 1111 1111, adjust R1 for VOUT = –VREF (4095/4096)].
Alternatively, Full Scale can be adjusted by omitting R1 and R2
and trimming the reference voltage magnitude.
OUT2
OUT1
10kΩ
R
FEEDBACK
C1 phase compensation (10 pF to 25 pF) may be required for
stability when using high speed amplifiers. (C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT1).
BIT 1 (MSB)
BIT 2
BIT 3
BIT 12 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO I
FOR
OUT1
ITS DIGITAL INPUT IN A "HIGH" STATE.
Amplifier A1 should be selected or trimmed to provide VOS
≤
10% of the voltage resolution at VOUT. Additionally, the ampli-
fier should exhibit a bias current which is low over the tempera-
ture range of interest (bias current causes output offset at VOUT
equal to IB times the DAC feedback resistance, nominally 11kΩ).
The AD544L is a high speed implanted FET input op amp with
Figure 1. Functional Diagram (Inputs HIGH)
The input resistance at VREF (Figure 1) is always equal to RLDR
(RLDR is the R/2R ladder characteristic resistance and is equal to
value “R”). Since RIN at the VREF pin is constant, the reference
terminal can be driven by a reference voltage or a reference
current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external RFB is
recommended to define scale factor.)
low factory-trimmed VOS
.
V
DD
R2*
C1
33pF
16
18
V
R
FB
EQUIVALENT CIRCUIT ANALYSIS
DD
V
IN
1
2
OUT1
V
OUT
17
V
The equivalent circuits for all digital inputs LOW and all digital
inputs HIGH are shown in Figures 2 and 3. In Figure 2 with all
digital inputs LOW, the reference current is switched to OUT2.
The current source ILEAKAGE is composed of surface and junc-
tion leakages to the substrate, while the I/4096 current source
represents a constant 1-bit current drain through the termina-
tion resistor on the R-2R ladder. The ON capacitance of the
output N-channel switch is 200 pF, as shown on the OUT2
terminal. The OFF switch capacitance is 70 pF, as shown on
the OUT1 terminal. Analysis of the circuit for all digital inputs
HIGH, as shown in Figure 3 is similar to Figure 2; however, the
ON switches are now on terminal OUT1, hence the 200 pF at
REF
AD7541A
R1*
OUT2
3
AD544L
(SEE TEXT)
DGND
PINS 4–15
ANALOG
COMMON
DIGITAL
GROUND
BIT 1 – BIT 12
*REFER TO TABLE 1
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades
Trim
that terminal.
Resistor JN/AQ/SD KN/BQ/TD
RFB
R
R1
R2
100 Ω
47 Ω
100 Ω
33 Ω
OUT1
70pF
I
I
LEAKAGE
LEAKAGE
15kΩ
V
OUT2
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC
REF
200pF
I
I
REF
/4096
MSB
LSB
Analog Output, VOUT
Figure 2. DAC Equivalent Circuit All Digital Inputs LOW
4095
4096
1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 1
–VIN
RFB
R
15kΩ
V
OUT1
OUT2
REF
200pF
70pF
2048
4096
I
I
I
I
/4096
LEAKAGE
LEAKAGE
REF
1 0 0 0
0 0 0 0
–VIN
= –1/2 VIN
1
4096
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
–VIN
Figure 3. DAC Equivalent Circuit All Digital Inputs HIGH
0 Volts
–4–
REV. B
AD7541A
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 5 and Table III illustrate the circuitry and code relation-
ship for bipolar operation. With a dc reference (positive or nega-
tive polarity) the circuit provides offset binary operation. With
an ac reference the circuit provides full 4-quadrant multiplication.
Figure 6 and Table IV show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage of giving 12-bit resolution in each
quadrant, compared with 11-bit resolution per quadrant for the
circuit of Figure 5. The AD7592 is a fully protected CMOS
changeover switch with data latches. R4 and R5 should match
each other to 0.01% to maintain the accuracy of the D/A con-
verter. Mismatch between R4 and R5 introduces a gain error.
With the DAC loaded to 1000 0000 0000, adjust R1 for
VOUT = 0 V (alternatively, one can omit R1 and R2 and adjust
the ratio of R3 to R4 for VOUT = 0 V). Full-scale trimming can
be accomplished by adjusting the amplitude of VREF or by vary-
ing the value of R5.
VDD
R2*
R4
20kΩ
R5
20kΩ
C1
33pF
16
18
VDD
RFB
VOUT
1
2
OUT1
R3
10kΩ
As in unipolar operation, A1 must be chosen for low VOS and
low IB. R3, R4 and R5 must be selected for matching and track-
ing. Mismatch of 2R3 to R4 causes both offset and full-scale
error. Mismatch of R5 to R4 or 2R3 causes full-scale error. C1
phase compensation (10 pF to 50 pF) may be required for sta-
bility, depending on amplifier used.
V
17
REF AD7541A
A2
A1
AD544L
VIN
R1*
OUT2
GND
AD544J
10%
PINS 4–15
3
1/2 AD7592JN
ANALOG
COMMON
DIGITAL
GROUND
SIGN BIT
BIT 1 – BIT 12
*FOR VALUES OF R1 AND R2
SEE TABLE 1.
V
DD
R2*
R4
Figure 6. 12-Bit Plus Sign Magnitude Operation
20kΩ
C1
33pF
16
18
R
R5
20kΩ
V
R3
10kΩ
DD
REF
FB
1
2
OUT1
OUT2
Table IV. 12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 6
V
17
A1
AD544L
AD7541A
V
R1*
IN
A2
AD544J
R6
5kΩ
V
GND
OUT
PINS 4–15
3
Sign
Bit
Binary Number in DAC
MSB LSB
10%
Analog Output, VOUT
ANALOG
COMMON
DIGITAL
GROUND
*FOR VALUES OF R1 AND R2
SEE TABLE 1.
BIT 1 – BIT 12
4095
4096
0
1 1 1 1 1 1 1 1 1 1 1 1
+VIN ×
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
0
1
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 Volts
0 Volts
Table III. Bipolar Code Table for Offset Binary Circuit of
Figure 5
4095
4096
1
1 1 1 1 1 1 1 1 1 1 1 1
–VIN ×
Binary Number in DAC
MSB
LSB
Analog Output, VOUT
Note: Sign bit of “0” connects R3 to GND.
2047
2048
1 1 1 1
1 1 1 1
1 1 1 1
+VIN
1
1 0 0 0
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
+VIN
2048
0 Volts
1
0 1 1 1
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
0 0 0 0
–VIN
2048
2048
2048
–VIN
REV. B
–5–
AD7541A
APPLICATIONS HINTS
SINGLE SUPPLY OPERATION
Output Offset: CMOS D/A converters exhibit a code-dependent
output resistance which in turn can cause a code-dependent
error voltage at the output of the amplifier. The maximum am-
plitude of this offset, which adds to the D/A converter nonlin-
earity, is 0.67 VOS where VOS is the amplifier input offset
voltage. To maintain monotonic operation it is recommended
that VOS be no greater than (25 × 10–6) (VREF) over the tempera-
ture range of operation. Suitable op amps are AD517L and
AD544L. The AD517L is best suited for fixed reference appli-
cations with low bandwidth requirements: it has extremely low
offset (50 µV) and in most applications will not require an offset
trim. The AD544L has a much wider bandwidth and higher
slew rate and is recommended for multiplying and other appli-
cations requiring fast settling. An offset trim on the AD544L
may be necessary in some circuits.
Figure 7 shows the AD7541A connected in a voltage switching
mode. OUT1 is connected to the reference voltage and OUT2
is connected to GND. The D/A converter output voltage is
available at the VREF pin (Pin 17) and has a constant output
impedance equal to RLDR. The feedback resistor RFB is not used
in this circuit.
V
= +15V
DD
NOT
USED
18
16
CA3140B
R
V
DD
FB
1
2
OUT1
OUT2
V+
V–
V
AD7541A V
REF
+2.5V
REF 17
V
= 0V TO +10V
OUT
PINS 4–15
15
GND
3
4
R2
30kΩ
R1
10kΩ
Digital Glitches: One cause of digital glitches is capacitive
coupling from the digital lines to the OUT1 and OUT2 termi-
nals. This should be minimized by screening the analog pins of
the AD7541A (Pins 1, 2, 17, 18) from the digital pins by a
ground track run between Pins 2 and 3 and between Pins 16
and 17 of the AD7541A. Note how the analog pins are at one
end of the package and separated from the digital pins by VDD
and GND to aid screening at the board level. On-chip capacitive
coupling can also give rise to crosstalk from the digital-to-analog
sections of the AD7541A, particularly in circuits with high cur-
rents and fast rise and fall times.
BIT 1 – BIT 12
SYSTEM
GROUND
V
±V
D (1 +R2/R1) WHERE 0 ≤ D ≤ 1
REF
OUT
i.e., D IS A FRACTIONAL REPRESENTATION OF THE DIGITAL INPUT
Figure 7. Single Supply Operation Using Voltage Switch-
ing Mode
The reference voltage must always be positive. If OUT1 goes
more than 0.3 V less than GND, an internal diode will be turned
on and a heavy current may flow causing device damage (the
AD7541A is, however, protected from the SCR latch-up
phenomenon prevalent in many CMOS devices). Suitable refer-
ences include the AD580 and AD584.
Temperature Coefficients: The gain temperature coefficient
of the AD7541A has a maximum value of 5 ppm/°C and a typi-
cal value of 2 ppm/°C. This corresponds to worst case gain shifts
of 2 LSBs and 0.8 LSBs, respectively, over a 100°C temperature
range. When trim resistors R1 and R2 are used to adjust full-
scale range, the temperature coefficient of R1 and R2 should
also be taken into account. The reader is referred to Analog
Devices Application Note “Gain Error and Gain Temperature
Coefficient of CMOS Multiplying DACs,” Publication Number
E630c-5-3/86.
The loading on the reference voltage source is code-dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltage at OUT1 should remain within
2.5 V of GND, for a VDD of 15 V. If VDD is reduced from 15 V
or the reference voltage at OUT1 increased to more than 2.5 V,
the differential nonlinearity of the DAC will increase and the
linearity of the DAC will be degraded.
SUPPLEMENTAL APPLICATION MATERIAL
For further information on CMOS multiplying D/A converters,
the reader is referred to the following texts:
CMOS DAC Application Guide, Publication Number
G872b-8-1/89 available from Analog Devices.
Gain Error and Gain Temperature Coefficient of CMOS
Multiplying DACs Application Note, Publication Number
E630c-5-3/86 available from Analog Devices.
Analog-Digital Conversion Handbook—available from Analog
Devices.
–6–
REV. B
AD7541A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Terminal Ceramic Leadless Chip Carrier
(E-20A)
20-Lead Plastic Leadless Chip Carrier
(P-20A)
0.180 (4.57)
0.200 (5.08)
BSC
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.100 (2.54) BSC
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
3
19
0.095 (2.41)
0.075 (1.90)
3
0.021 (0.53)
0.013 (0.33)
MIN
19
4
8
18
PIN 1
20
0.050
(1.27)
BSC
18
4
IDENTIFIER
0.028 (0.71)
0.330 (8.38)
0.290 (7.37)
0.358
1
0.358 (9.09)
0.011 (0.28)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
0.022 (0.56)
(9.09)
MAX
SQ
BOTTOM
VIEW
0.342 (8.69)
SQ
0.007 (0.18)
R TYP
0.075 (1.91)
REF
14
13
0.050 (1.27)
BSC
9
14
13
8
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
9
0.356 (9.04)
0.350 (8.89)
SQ
45° TYP
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.150 (3.81)
BSC
0.110 (2.79)
0.085 (2.16)
0.395 (10.02)
0.385 (9.78)
SQ
18-Lead Plastic DIP
(N-18)
18-Lead Cerdip
(Q-18)
0.925 (23.49)
0.845 (21.47)
0.005 (0.13) MIN
0.098 (2.49) MAX
18
10
18
1
10
9
0.280 (7.11)
0.240 (6.10)
0.310 (7.87)
0.220 (5.59)
0.325 (8.25)
1
9
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
0.320 (8.13)
0.290 (7.37)
PIN 1
PIN 1
0.960 (24.38) MAX
0.060 (1.52)
0.015 (0.38)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.200 (5.08)
MAX
0.130
(3.30)
MIN
0.150
(3.81)
MIN
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
0.125 (3.18)
0.015 (0.381)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
0.015 (0.38)
0.008 (0.20)
0.008 (0.204)
0.023 (0.58)
0.014 (0.36)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
15°
0°
18-Lead SOIC
(R-18)
0.4625 (11.75)
0.4469 (11.35)
18
10
1
9
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
REV. B
–7–
–8–
相关型号：
5962-8948102VB
PARALLEL, WORD INPUT LOADING, 0.6us SETTLING TIME, 12-BIT DAC, CDIP18, 0.960 X 0.310 INCH, CERDIP-18
ADI
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