5962-89657023A [ADI]
Dual 12-Bit CMOS DAC with Parallel Load Input Structure;
| 型号： | 5962-89657023A |
| 厂家： | 
ADI |
| 描述： | Dual 12-Bit CMOS DAC with Parallel Load Input Structure 转换器 |
| 文件： | 总12页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
A
DESCRIPTION
DATE (YR-MO-DA)
92-01-27
APPROVED
Changes in accordance with NOR 5962-R120-92.
Michael A. Frye
B
C
Drawing updated to reflect current requirements. - lgt
01-12-17
13-09-20
Raymond Monnin
Charles F. Saffle
Redrawn. Update paragraphs to MIL-PRF-38535 requirements. - drw
THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
REV
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
C
C
SHEET
10
11
PREPARED BY
Rick C. Officer
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Charles E. Besore
APPROVED BY
Michael A. Frye
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
MICROCIRCUIT, LIINEAR, DUAL, CMOS, 12-BIT,
D/A CONVERTER, MONOLITHIC SILICON
DRAWING APPROVAL DATE
89-12-28
REVISION LEVEL
C
SIZE
A
CAGE CODE
AMSC N/A
5962-89657
67268
SHEET
1 OF 11
DSCC FORM 2233
APR 97
5962-E575-13
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-89657
01
L
A
Drawing number
Device type
(see 1.2.1)
Case outline
(see 1.2.2)
Lead finish
(see 1.2.3)
1.2.1 Device types. The device types identify the circuit function as follows:
Device type
Generic number
Circuit function
Gain error
01
02
03
7547S
7547T
7547U
Dual, CMOS, 12-bit D/A converter
Dual, CMOS, 12-bit D/A converter
Dual, CMOS, 12-bit D/A converter
±6.0 LSB
±3.0 LSB
±2.0 LSB
1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows:
Outline letter
Descriptive designator
Terminals
Package style
L
3
GDIP3-T24 or CDIP4-T24
CQCC1-N28
24
28
Dual-in-line
Square leadless chip carrier
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
V
V
DD to DGND......................................................................................... 0.3 V dc to +17 V dc
REFA, VREFB, to AGND.......................................................................... ±25 V dc
VRFBA, VRFBB, to AGND.......................................................................... ±25 V dc
Digital input voltage to DGND ............................................................... 0.3 V dc to VDD +0.3 V
Voltage at IOUTA, IOUTB to DGND............................................................ -0.3 V dc to VDD +0.3 V
AGND to DGND .................................................................................... -0.3 V dc to VDD +0.3 V
Storage temperature range................................................................... -65°C to +150°C
Lead temperature (soldering, 10 seconds)............................................ +300°C
Power dissipation (PD) .......................................................................... 450 mW 1/
Thermal resistance, junction to case (θJC)............................................. See MIL-STD-1835
Thermal resistance, junction to ambient (θJA) ....................................... 120°C C/W
Junction temperature (TJ)...................................................................... +175°C
1.4 Recommended operating conditions.
Supply voltage range (VDD) ................................................................... 10.8 V dc to 16.5 V dc
Minimum high level input voltage.......................................................... 2.4 V dc
Maximum low level input voltage........................................................... 0.8 V dc
Ambient operating temperature range (TA) ........................................... -55°C to +125°C
Voltage at VREFA, VREFB ......................................................................... 10 V dc
Voltage at AGND, IOUTA......................................................................... 0 V dc
Voltage at AGND, IOUTB......................................................................... 0 V dc
______
1/ Derate above TA = +75°C at 6.0 mW/°C.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
2
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
-
Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to
MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and
qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management
(QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the
device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with
MIL-PRF-38535 is required to identify when the QML flow option is used.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
3
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Conditions 1/
-55°C ≤ TA ≤+125°C
unless otherwise specified
Test
Symbol
Group A
subgroups
Device
type
Limits
Unit
Min
12
Max
Resolution
Relative accuracy
2/
RES
RA
Guaranteed minimum
resolution
1, 2, 3
All
Bits
VDD = 10.8 V and 16.5 V
1, 2, 3
1
01
LSB
±1.0
±1.0
±0.5
±1.0
02, 03
2, 3, 12
1, 2, 3
Differential nonlinearity
Gain error
DNL
AE
Guaranteed monotonic to
12-bits , VDD = 10.8 V and
16.5 V
All
LSB
LSB
Measured using RFBA and
RFBB. Both DAC registers
loaded with all 1’s,
1, 2, 3
1
01
02
03
02
03
All
±6.0
±3.0
±2.0
±3.0
±2.0
±5.0
VDD = 10.8 V.
2, 3, 12
Gain temperature
coefficient
2/
4
1
∆A
E
ppm/°C
∆T
VDD = 10.8 V and 16.5 V
VDD = 10.8 V
Power supply rejection
ratio, VREFB to IOUTB
PSRR
All
All
%/%
±0.01
2, 3
1
±0.02
±10
IOUTA
IOUTB
tSL
Output leakage current
DAC A loaded with all 0’s,
VDD = 16.5 V
nA
nA
µs
2, 3
1
±250
±10
DAC B loaded with all 0’s,
VDD = 16.5 V
All
All
2, 3
9
±250
Output current settling 2/
time to 0.01% of FSR
1.5
IOUT load = 100Ω,
CEXT = 13 pF, DAC output
measured from falling edge
of WR
10, 11
4
1.5
-65
Feedthrough error,
VREFA to IOUTA or VREFB to
IOUTB
2/
FT
All
dB
VREFA = VREFB = ±20 Vpp,
10 kHz sine wave, DAC
register loaded with all 0’s
5, 6
-65
See footnotes at end of table.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
4
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics – continued.
Conditions 1/
-55°C ≤ TA ≤+125°C
unless otherwise specified
Test
Symbol
Group A
subgroups
Device
type
Limits
Unit
Min
9.0
Max
20
RIN
VDD = 10.8 V
VDD = 10.8 V
Reference input
resistance
Reference input
resistance match
1, 2, 3
All
kΩ
RMIN
1, 2, 3
1
01, 02
03
%
±3.0
±3.0
±1.0
(VREFA/VREFB
)
2, 3
1, 2, 3
1, 2, 3
1
VIH
VIL
IIN
VDD = 10.8 V and 16.5 V
VDD = 10.8 V and 16.5 V
VIN = VDD = 16.5 V
Digital input high voltage
Digital input low voltage
Input current
All
All
All
2.4
V
V
0.8
1.0
10
µA
2, 3
4
CIN
Digital input capacitance
2/
Output capacitance 2/
All
All
10
pF
pF
TA = +25°C
COUTA
DAC A = all 0’s,
TA = +25°C
4
70
140
70
DAC A = all 1’s,
TA = +25°C
COUTB
Output capacitance 2/
DAC B = all 0’s,
4
All
pf
TA = +25°C
DAC B = all 1’s,
140
TA = +25°C
Functional test
Data setup time
See 4.3.1c
7
All
All
tDS
See figure 3
9
60
80
25
25
80
ns
ns
ns
10, 11 2/
tDH
Data hold time
See figure 3
See figure 3
9
10, 11 2/
9
All
All
tCWS
Chip select or update to
write setup time
10, 11 2/
9
100
0
tCWH
Chip select or update to
write hold time
See figure 3
All
ns
10, 11 2/
9
0
tWR
IDD
Write pulse width
Supply current
See figure 3
VDD = 16.5 V
All
All
80
ns
10, 11 2/
1, 2, 3
100
2.0
mA
1/ VDD = 10.8 V to 16.5 V, unless otherwise specified. VREFA = VREFB = 10 V, voltage at AGND = 0 V,
voltage at IOUTA = IOUTB = 0 V.
2/ If not tested, shall be guaranteed to the limits specified in table I herein.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
5
DSCC FORM 2234
APR 97
Device type
Case outline
01, 02, 03
L
02
3
Terminal number
1
Terminal symbol
AGND
Terminal symbol
NC
IOUTA
RFBA
VREFA
2
AGND
IOUTA
3
RFBA
4
VREFA
5
CSA
DB0(LSB)
6
CSA
DB1
DB2
DB0(LSB)
7
8
NC
DB1
DB3
9
DB4
DB2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DB5
DB3
DB4
DGND
DB6
DB5
DB7
DGND
NC
DB8
DB9
DB6
DB10
DB11(MSB)
DB7
DB8
DB9
WR
CSB
VDD
DB10
DB11(MSB)
NC
VREFB
RFBB
IOUTB
------
------
------
------
WR
CSB
VDD
VREFB
RFBB
IOUTB
FIGURE 1. Terminal connections.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
6
DSCC FORM 2234
APR 97
Function
CSA
X
CSB
X
WR
1
No data transfer
No data transfer
1
1
X
0
A rising edge on CSA or CSB loads data to the
respective DAC from data bus
0
1
1
0
0
DACA register loaded from data bus
DACB register loaded from data bus
0
DACA and DACB register loaded from data bus
0 = Logic low level
1 = Logic high level
X = Irrelevant
= Rising edge triggered
FIGURE 2. Truth table.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
7
DSCC FORM 2234
APR 97
Notes
1.
All input signal rise and fall times are measured from 10% to 90% of +5.0 V, tr = tf = 20 ns.
V
IH + VIL
2
Timing measurement reference level is
2.
FIGURE 3. Timing diagram.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
8
DSCC FORM 2234
APR 97
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN
listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD
PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance
to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in
accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and
Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the
requirements of MIL-PRF-38535, appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that
affects this drawing.
3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
c. Subgroup 12 test is used for grading and part selection at +25°C and is not included in PDA calculations.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
9
DSCC FORM 2234
APR 97
TABLE II. Electrical test requirements.
Subgroups
(in accordance with
MIL-STD-883, method 5005,
table I)
MIL-STD-883 test requirements
Interim electrical parameters
(method 5004)
- - -
Final electrical test parameters
(method 5004)
1*, 2, 3, 7, 12
Group A test requirements
(method 5005)
1, 2, 3, 4**, 5**, 6**, 7, 9, 10**,
11**, 12**
Groups C and D end-point
electrical parameters
(method 5005)
1
* PDA applies to subgroup 1.
**Subgroups 10 and 11, if not tested, shall be guaranteed
to the limits specified in table I herein.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of
MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroup 8 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroups 7 shall include verification of the truth table.
d. Subgroup 12 test is used for grading and part selection at +25°C.
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1005 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
10
DSCC FORM 2234
APR 97
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform DLA Land and Maritime when a system application requires
configuration control and the applicable SMD to that system. DLA Land and Maritime will maintain a record of users and this
list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.5 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103 and QML-38535. The vendors
listed in MIL-HDBK-103 and QML-38535 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has
been submitted to and accepted by DLA Land and Maritime-VA.
SIZE
STANDARD
5962-89657
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
C
SHEET
COLUMBUS, OHIO 43218-3990
11
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 13-09-20
Approved sources of supply for SMD 5962-89657 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
Vendor
similar
PIN 2/
number
5962-8965701LA
5962-8965702LA
1ES66
1ES66
24355
24355
1ES66
24355
MX7547SQ/883B
MX7547TQ/883B
AD7547TQ/883B
AD7547TE/883B
MX7547UQ/883B
AD7547UQ/883B
5962-89657023A
5962-8965703LA
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
Vendor name
and address
1ES66
Maxim Integrated
160 Rio Robles
San Jose, CA 95134
24355
Analog Devices
Rt 1 Industrial Park
PO Box 9106
Norwood, MA 02062
Point of contact:
Raheen Business Park
Limerick, Ireland
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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