5962-9089401MEA [ADI]
Software Programmable Gain Amplifier; 软件可编程增益放大器
| 型号： | 5962-9089401MEA |
| 厂家： | 
ADI |
| 描述： | Software Programmable Gain Amplifier |
| 文件： | 总14页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Software Programmable
Gain Amplifier
a
AD526
FEATURES
PIN CONFIGURATION
Digitally Programmable Binary Gains from 1 to 16
Two-Chip Cascade Mode Achieves Binary Gain from
1 to 256
DIG GND
NULL
1
2
3
4
5
6
7
8
16 A1
15 A0
Gain Error:
0.01% Max, Gain = 1, 2, 4 (C Grade)
0.02% Max, Gain = 8, 16 (C Grade)
0.5 ppm/؇C Drift Over Temperature
Fast Settling Time
10 V Signal Change:
0.01% in 4.5 s (Gain = 16)
Gain Change:
V
14
CS
IN
NULL
ANALOG GND 2
ANALOG GND 1
AD526
TOP VIEW
(Not to Scale)
13
12
11
10
9
CLK
A2
B
–V
S
+V
S
V
SENSE
V
FORCE
OUT
OUT
0.01% in 5.6 s (Gain = 16)
Low Nonlinearity: ؎0.005% FSR Max (J Grade)
Excellent DC Accuracy:
Offset Voltage: 0.5 mV Max (C Grade)
Offset Voltage Drift: 3 V/؇C (C Grade)
TTL-Compatible Digital Inputs
PRODUCT DESCRIPTION
APPLICATION HIGHLIGHTS
The AD526 is a single-ended, monolithic software program-
mable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8
and 16. It is complete, including amplifier, resistor network
and TTL-compatible latched inputs, and requires no external
components.
1. Dynamic Range Extension for ADC Systems: A single
AD526 in conjunction with a 12-bit ADC can provide
96 dB of dynamic range for ADC systems.
2. Gain Ranging Preamps: The AD526 offers complete digital
gain control with precise gains in binary steps from 1 to 16.
Additional gains of 32, 64, 128 and 256 are possible by cas-
cading two AD526s.
Low gain error and low nonlinearity make the AD526 ideal for
precision instrumentation applications requiring programmable
gain. The small signal bandwidth is 350 kHz at a gain of 16. In
addition, the AD526 provides excellent dc precision. The FET-
input stage results in a low bias current of 50 pA. A guaranteed
maximum input offset voltage of 0.5 mV max (C grade) and low
gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using
Analog Devices’ laser trimming technology.
ORDERING GUIDE
Temperature Package
Range
Package
Options
Model
Descriptions
To provide flexibility to the system designer, the AD526 can be
operated in either latched or transparent mode. The force/sense
configuration preserves accuracy when the output is connected
to remote or low impedance loads.
AD526JN
Commercial
Industrial
Industrial
Industrial
Military
16-Lead Plastic DIP N-16
AD526AD
AD526BD
AD526CD
AD526SD
AD526SD/883B
5962-9089401MEA* Military
16-Lead Cerdip
16-Lead Cerdip
16-Lead Cerdip
16-Lead Cerdip
16-Lead Cerdip
16-Lead Cerdip
D-16
D-16
D-16
D-16
D-16
D-16
The AD526 is offered in one commercial (0°C to +70°C) grade,
J, and three industrial grades, A, B and C, which are specified
from –40°C to +85°C. The S grade is specified from –55°C to
+125°C. The military version is available processed to MIL-
STD 883B, Rev C. The J grade is supplied in a 16-lead plastic
DIP, and the other grades are offered in a 16-lead hermetic
side-brazed ceramic DIP.
Military
*Refer to official DESC drawing for tested specifications.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(@ V = ؎15 V, R = 2 k⍀ and T = +25؇C unless otherwise noted)
AD526–SPECIFICATIONS
S
L
A
AD526J
Typ
AD526A
Typ
AD526B/S
Typ
AD526C
Typ
Model
Min
Max
Min
Max
Min
Max
Min
Max
Units
GAIN
Gain Range
(Digitally Programmable)
Gain Error
Gain = 1
Gain = 2
Gain = 4
1, 2, 4, 8, 16
1, 2, 4, 8, 16
0.02
1, 2, 4, 8, 16
0.01
1, 2, 4, 8, 16
0.05
0.05
0.10
0.15
0.15
0.01
0.01
0.01
0.02
0.02
%
%
%
%
%
0.03
0.03
0.07
0.07
0.02
0.02
0.04
0.04
Gain = 8
Gain = 16
Gain Error Drift
Over Temperature
G = 1
0.5
0.5
0.5
0.5
1.0
2.0
2.0
3.0
5.0
5.0
0.5
0.5
0.5
0.5
1.0
2.0
2.0
3.0
5.0
5.0
0.5
0.5
0.5
0.5
1.0
2.0
2.0
3.0
5.0
5.0
0.5
0.5
0.5
0.5
1.0
2.0
2.0
3.0
5.0
5.0
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
G = 2
G = 4
G = 8
G = 16
Gain Error (TMIN to TMAX
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Nonlinearity
Gain = 1
Gain = 2
Gain = 4
)
0.06
0.06
0.12
0.17
0.17
0.03
0.04
0.04
0.08
0.08
0.02
0.03
0.03
0.05
0.05
0.015
0.015
0.015
0.03
%
%
%
%
%
0.03
0.005
0.001
0.001
0.001
0.001
0.005
0.001
0.001
0.001
0.001
0.005
0.001
0.001
0.001
0.001
0.0035 % FSR
0.001 % FSR
0.001 % FSR
0.001 % FSR
0.001 % FSR
Gain = 8
Gain = 16
Nonlinearity (TMIN to TMAX
Gain = 1
Gain = 2
Gain = 4
Gain = 8
)
0.01
0.01
0.01
0.007 % FSR
0.001 % FSR
0.001 % FSR
0.001 % FSR
0.001 % FSR
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
Gain = 16
VOLTAGE OFFSET, ALL GAINS
Input Offset Voltage
Input Offset Voltage Drift Over
Temperature
Input Offset Voltage
TMIN to TMAX
0.4
5
1.5
20
0.25
3
0.7
10
0.25
3
0.5
10
0.25
3
0.5
10
mV
µV/°C
mV
2.0
1.0
0.8
0.8
Input Offset Voltage vs. Supply
(VS ± 10%)
80
80
84
90
dB
INPUT BIAS CURRENT
Over Input Voltage Range ± 10 V
50
150
50
150
50
150
50
150
pA
ANALOG INPUT
CHARACTERISTICS
Voltage Range
(Linear Operation)
Capacitance
؎10
±12
5
؎10
±12
5
؎10
±12
5
؎10
±12
5
V
pF
RATED OUTPUT
Voltage
؎10
±12
±10
30
؎10
؎5
15
±12
±10
30
؎10
؎5
15
±12
±10
30
؎10
؎5
15
±12
±10
30
V
Current (VOUT = ±10 V)
Short-Circuit Current
DC Output Resistance
Load Capacitance
(For Stable Operation)
mA
mA
Ω
15
0.002
0.002
0.002
0.002
700
700
700
700
pF
–2–
REV. D
AD526
AD526J
Typ
AD526A
Typ
AD526B/S
Typ
AD526C
Typ Max
Model
Min
Max
Min
Max Min
Max
Min
Units
NOISE, ALL GAINS
Voltage Noise, RTI
0.1 Hz to 10 Hz
Voltage Noise Density, RTI
f = 10 Hz
3
3
3
3
µV p-p
70
60
30
25
70
60
30
25
70
60
30
25
70
60
30
35
nV√Hz
nV√Hz
nV√Hz
nV√Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
DYNAMIC RESPONSE
–3 dB Bandwidth (Small Signal)
G = 1
G = 2
G = 4
G = 8
4.0
2.0
1.5
0.65
0.35
4.0
2.0
1.5
0.65
0.35
4.0
2.0
1.5
0.65
0.35
4.0
2.0
1.5
0.65
0.35
MHz
MHz
MHz
MHz
MHz
G = 16
Signal Settling Time to 0.01%
(∆VOUT = ±10 V)
G = 1
2.1
2.5
2.7
3.6
4.1
4
5
5
7
7
2.1
2.5
2.7
3.6
4.1
4
5
5
7
7
2.1
2.5
2.7
3.6
4.1
4
5
5
7
7
2.1
2.5
2.7
3.6
4.1
4
5
5
7
7
µs
µs
µs
µs
µs
G = 2
G = 4
G = 8
G = 16
Full Power Bandwidth
G = 1, 2, 4
G = 8, 16
Slew Rate
G = 1, 2, 4
G = 8, 16
0.10
0.35
0.10
0.35
0.10
0.35
0.10
0.35
MHz
MHz
4
18
6
24
4
18
6
24
4
18
6
24
4
18
6
24
V/µs
V/µs
DIGITAL INPUTS
(TMIN to TMAX
)
Input Current (VH = 5 V)
Logic “1”
60
2
100
140
6
60
2
100
140
6
60
2
100
140
6
60
2
100 140
µA
V
6
Logic “0”
0
0.8
0
0.8
0
0.8
0
0.8
V
TIMING1
(VL = 0.2 V, VH = 3.7 V)
A0, A1, A2
TC
TS
TH
B
50
30
30
50
30
30
50
30
30
50
30
30
ns
ns
ns
TC
TS
TH
50
40
10
50
40
10
50
40
10
50
40
30
ns
ns
ns
TEMPERATURE RANGE
Specified Performance
Storage
0
–65
+70
+125
–40
–65
+85
+150 –65
–40/–55
+85/+125 –40
+85
+150
°C
°C
+150
–65
POWER SUPPLY
Operating Range
Positive Supply Current
Negative Supply Current
؎4.5
؎16.5 ؎4.5
14
13
؎16.5 ؎4.5
14
13
؎16.5
14
13
؎4.5
؎16.5
14
13
V
mA
mA
10
10
10
10
10
10
10
10
PACKAGE OPTIONS
Plastic (N-16)
AD526JN
Ceramic DIP (D-16)
AD526AD
AD526BD AD526SD
AD526SD/883B
AD526CD
NOTES
1Refer to Figure 25 for definitions. FSR = Full Scale Range = 20 V. RTI = Referred to Input.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. All min and max specifications are guaranteed, although only those shown in
boldface are tested on all production units.
–3–
REV. D
AD526–Typical Performance Characteristics
20
15
10
5
20
15
10
5
30
+25؇C
20
R
= 2k⍀
L
@ V = ؎15V
V
= 0
S
IN
10
0
0
0
0
5
10
15
20
0
5
10
15
20
100
1k
LOAD RESISTANCE – ⍀
10k
SUPPLY VOLTAGE – ؎V
SUPPLY VOLTAGE – ؎V
Figure 3. Input Bias Current vs.
Supply Voltage
Figure 1. Output Voltage Swing vs.
Supply Voltage, G = 16
Figure 2. Output Voltage Swing vs.
Load Resistance
75
20
10
100nA
10nA
1nA
16
8
V
= ؎15V
S
50
4
2
1
100pA
10pA
1pA
25
0
1
–60
–20
20
60
100
140
–10
–5
0
5
10
10
100
1k
10k 100k
1M
10M
INPUT VOLTAGE – V
TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 6. Gain vs. Frequency
Figure 4. Input Bias Current vs.
Temperature
Figure 5. Input Bias Current vs. Input
Voltage
1.0002
25
100
؎15V WITH 1V p-p
SINE WAVE
80
20
15
10
5
GAIN = 8, 16
1.0001
1.0000
+SUPPLY
60
GAIN = 1, 2, 4
40
–SUPPLY
0.9999
0.9998
20
10
0
1k
–60
–20
20
60
100
140
1
10
100
1k
10k 100k
1M
10k
100k
1M
10M
TEMPERATURE – ؇C
FREQUENCY – Hz
FREQUENCY – Hz
Figure 9. Normalized Gain vs.
Temperature, Gain = 1
Figure 7. Large Signal Frequency
Response
Figure 8. PSRR vs. Frequency
–4–
REV. D
AD526
0.006
0.004
1000
100
10
0.002
0.000
–0.002
–0.004
–60
–20
20
60
100
140
1k
100
FREQUENCY – Hz
10
10k
100k
TEMPERATURE – ؇C
Figure 11. Nonlinearity vs.
Temperature, Gain = 1
Figure 10. Noise Spectral Density
Figure 12. Wideband Output Noise,
G = 16 (Amplified by 10)
Figure 14. Small Signal Pulse
Response, G = 1
Figure 13. Large Signal Pulse
Response and Settling Time,*
G = 1
Figure 15. Large Signal Pulse
Response and Settling Time,*
G = 2
Figure 16. Small Signal Pulse
Response, G = 2
Figure 17. Large Signal Pulse
Response and Settling Time,*
G = 4
Figure 18. Small Signal Pulse
Response, G = 4
*For Settling Time Traces, 0.01% = 1/2 Vertical Division
–5–
REV. D
AD526
Figure 19. Large Signal Pulse
Response and Settling Time,* G = 8
Figure 20. Small Signal Pulse
Response, G = 8
Figure 21. Large Signal Pulse
Response and Settling Time,* G = 16
–60
10
5
–70
–80
–90
0
–5
–100
–10
10
10
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 22. Small Signal Pulse
Response, Gain = 16
Figure 23. Total Harmonic Distortion
vs. Frequency Gain = 16
Figure 24. Phase Distortion vs.
Frequency, Gain = 16
100
G = 2, 8
G = 4, 16
G = 1
10
1
10k
100k
1M
10M
FREQUENCY – Hz
Figure 25. Output Impedance vs.
Frequency
Figure 26. Gain Change Settling
Time,** Gain Change: 1 to 2
Figure 27. Gain Change Settling
Time,** Gain Change 1 to 4
*For Settling Time Traces, 0.01% = 1/2 Vertical Division
**Scope Traces are: Top: Output Transition; Middle: Output Settling; Bottom: Digital Input.
REV. D
–6–
AD526
Figure 28. Gain Change Settling
Time,* Gain Change 1 to 8
Figure 29. Gain Change Settling
Time,* Gain Change 1 to 16
+15V –15V
+15V –15V
10F
10F
+
+
10F
10F
TEKTRONIX
7000 SERIES
SCOPE
+
+
7A13
PREAMP
5MHz BW
AD526
G = 16
OP37
900⍀
G = 10
V
= 160
؋
e p-p
100⍀
o
10F
+
+5V
SHIELD
NOTE: COAX CABLE 1 FT. OR LESS
Figure 30. Wideband Noise Test Circuit
+15V –15V
10F 10F
+
+
DATA
DYNAMICS
5109
+15V –15V
(OR EQUIVALENT
FLAT-TOP PULSE
GENERATOR)
10F
10F
+
5k⍀
+
AD526
TEKTRONIX
1pF
7000 SERIES
SCOPE
V
ERROR
2k⍀
POT.
+
7A13
PREAMP
5MHz BW
V
؋
5 ERROR
–
AD711
5k⍀
AD3554
–
1pF
5pF
+
R
G
5k⍀
IN
5.6k⍀
IN6263
1
2
5.6k⍀
2.8k⍀
1.4k⍀
715⍀
348⍀
R
2
2
10F
10F
IN
T
=
TMEAS – T
4
SET
X
+
+
–
IN6263
8
16
5k⍀
1.25k⍀
G
T
X
AD3554
50⍀
–15V +15V
+
1
2
1.2s
1.2s
1.2s
1.4s
1.8s
4
10F
+
10F
+
8
16
–15V +15V
Figure 31. Settling Time Test Circuit
*Scope Traces are:
Top: Output Transition
Middle: Output Settling
Bottom: Digital Input
–7–
REV. D
AD526
THEORY OF OPERATION
TRANSPARENT MODE OF OPERATION
The AD526 is a complete software programmable gain amplifier
(SPGA) implemented monolithically with a drift-trimmed
BiFET amplifier, a laser wafer trimmed resistor network, JFET
analog switches and TTL compatible gain code latches.
In the transparent mode of operation, the AD526 will respond
directly to level changes at the gain code inputs (A0, A1, A2) if
B is tied high and both CS and CLK are allowed to float low.
After the gain codes are changed, the AD526’s output voltage
typically requires 5.5 µs to settle to within 0.01% of the final
value. Figures 26 to 29 show the performance of the AD526 for
positive gain code changes.
A particular gain is selected by applying the appropriate gain
code (see Table I) to the control logic. The control logic turns
on the JFET switch that connects the correct tap on the gain
network to the inverting input of the amplifier; all unselected
JFET gain switches are off (open). The “on” resistance of the
gain switches causes negligible gain error since only the
amplifier’s input bias current, which is less than 150 pA, actu-
ally flows through these switches.
A2
A1
A0
+V
S
0.1F
+5V
The AD526 is capable of storing the gain code, (latched mode),
B, A0, A1, A2, under the direction of control inputs CLK and
CS. Alternatively, the AD526 can respond directly to gain code
changes if the control inputs are tied low (transparent mode).
OUT
FORCE
9
16
15
14
13
12
11
B
10
A1 A0
CS CLK A2
LOGIC AND LATCHES
For gains of 8 and 16, a fraction of the frequency compensation
capacitance (C1 in Figure 32) is automatically switched out of
the circuit. This increases the amplifier’s bandwidth and im-
proves its signal settling time and slew rate.
16
8
4
2
1
V
OUT
GAIN NETWORK
–
+
AD526
1
2
3
4
5
6
7
8
OUT
SENSE
AMPLIFIER
+V
S
0.1F
V
C1
C2
IN
–V
S
V
IN
OUT
FORCE
Figure 33. Transparent Mode
LATCHED MODE OF OPERATION
N1
N2
The latched mode of operation is shown in Figure 34. When
either CS or CLK go to a Logic “1,” the gain code (A0, A1, A2,
B) signals are latched into the registers and held until both CS
and CLK return to “0.” Unused CS or CLK inputs should be tied
to ground . The CS and CLK inputs are functionally and electri-
cally equivalent.
–V
OUT
S
SENSE
A0
A1
A2
B
C
O
N
T
R
O
L
14k⍀
L
G = 8
A
T
3.4k⍀
RESISTOR
NETWORK
C
H
E
S
TIMING SIGNAL
G = 2
A2
A1
L
O
G
I
1k⍀
CLK
CS
A0
G = 16
+V
S
C
1.7k⍀
0.1F
+5V
G = 4
DIGITAL
GND
OUT
FORCE
9
1k⍀
1.7k⍀
16
15
14
13
12
11
B
10
ANALOG
GND2
ANALOG
GND1
A1 A0
CS CLK A2
LOGIC AND LATCHES
Figure 32. Simplified Schematic of the AD526
16
8
4
2
1
V
OUT
GAIN NETWORK
–
+
AD526
1
2
3
4
5
6
7
8
OUT
SENSE
0.1F
V
IN
–V
S
Figure 34. Latched Mode
REV. D
–8–
AD526
TIMING AND CONTROL
Table I. Logic Input Truth Table
DIGITAL FEEDTHROUGH
With either CS or CLK or both held high, the AD526 gain state
will remain constant regardless of the transitions at the A0, A1,
A2 or B inputs. However, high speed logic transitions will un-
avoidably feed through to the analog circuitry within the AD526
causing spikes to occur at the signal output.
Gain Code
Control
Condition
Gain
A2 A1 A0 B CLK (CS = 0)
Condition
X
0
0
0
0
1
X
X
0
0
0
0
1
X
0
0
1
1
X
X
X
0
0
1
X
0
1
0
1
X
X
X
0
1
0
X
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Previous State Latched
This feedthrough effect can be completely eliminated by operat-
ing the AD526 in the transparent mode and latching the gain
code in an external bank of latches (Figure 36).
1
2
4
8
16
1
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Latched
To operate the AD526 using serial inputs, the configuration
shown in Figure 36 can be used with the 74LS174 replaced by a
serial-in/parallel-out latch, such as the 54LS594.
1
A1
A0
A2
B
+5V
1
Latched
2
4
Latched
Latched
1F
TIMING
SIGNAL
74LS174
1
X
1
X
8
Latched
16
Latched
+V
S
NOTE: X = Don’t Care.
0.1F
The specifications on page 3, in combination with Figure 35,
give the timing requirements for loading new gain codes.
OUT
FORCE
9
16
15
14
13
12
11
B
10
A1 A0
CS CLK A2
LOGIC AND LATCHES
GAIN CODE
VALID DATA
INPUTS
16
8
4
2
1
T
C
V
OUT
GAIN NETWORK
CLK OR CS
–
+
T
T
H
S
AD526
T
T
T
= MINIMUM CLOCK CYCLE NOTE: THRESHOLD LEVEL FOR
C
S
H
1
2
3
4
5
6
7
8
OUT
SENSE
GAIN CODE, CS, AND CLK IS 1.4V.
= DATA SETUP TIME
= DATA HOLD TIME
0.1F
V
IN
Figure 35. AD526 Timing
–V
S
Figure 36. Using an External Latch to Minimize Digital
Feedthrough
–9–
REV. D
AD526
GROUNDING AND BYPASSING
Utilizing the force and sense outputs of the AD526, as shown in
Figure 38, avoids signal drops along etch runs to low impedance
loads.
Proper signal and grounding techniques must be applied in
board layout so that specified performance levels of precision
data acquisition components, such as the AD526, are not
degraded.
Table II. Logic Table for Figure 38
VOUT/VIN
A2
A1
A0
As is shown in Figure 37, logic and signal grounds should be
separate. By connecting the signal source ground locally to the
AD526 analog ground Pins 5 and 6, gain accuracy of the
AD526 is maintained. This ground connection should not be
corrupted by currents associated with other elements within the
system.
1
2
4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
16
32
64
128
+15V
–15V
0.1F
0.1F
AD574
12-BIT
V
IN
A/D
0.1F 0.1F
–V
CONVERTER
ANALOG ANALOG +V
GROUND 1 GROUND 2
S
S
V
OUT
FORCE
AMP
AD526
V
OUT
SENSE
GAIN
NETWORK
DIGITAL
GROUND
1F
LATCHES AND LOGIC
+5V
Figure 37. Grounding and Bypassing
CLK
A2
A1
A0
+V
+V
S
S
0.1F
0.1F
+5V
+5V
OUT
FORCE
OUT
FORCE
9
16
15
14
13
12
11
B
10
9
16
15
14
13
12
11
B
10
A1 A0
CS CLK A2
A1 A0
CS CLK A2
LOGIC AND LATCHES
LOGIC AND LATCHES
16
8
4
2
1
16
8
4
2
1
V
OUT
GAIN NETWORK
GAIN NETWORK
–
+
–
+
AD526
AD526
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
OUT
SENSE
OUT
SENSE
0.1F
V
IN
0.1F
–V
S
–V
S
Figure 38. Cascaded Operation
REV. D
–10–
AD526
OFFSET NULLING
CASCADED OPERATION
Input voltage offset nulling of the AD526 is best accomplished
at a gain of 16, since the referred-to-input (RTI) offset is ampli-
fied the most at this gain and therefore is most easily trimmed.
The resulting trimmed value of RTI voltage offset typically
varies less than 3 µV across all gain ranges.
A cascade of two AD526s can be used to achieve binarily
weighted gains from 1 to 256. If gains from 1 to 128 are needed,
no additional components are required. This is accomplished by
using the B pin as shown in Figure 38. When the B pin is low,
the AD526 is held in a unity gain stage independent of the other
gain code values.
Note that the low input current of the AD526 minimizes RTI
voltage offsets due to source resistance.
OFFSET NULLING WITH A D/A CONVERTER
Figure 41 shows the AD526 with offset nulling accomplished
with an 8-bit D/A converter (AD7524) circuit instead of the
potentiometer shown in Figure 39. The calibration procedure is
the same as before except that instead of adjusting the potenti-
ometer, the D/A converter corrects for the offset error. This
calibration circuit has a number of benefits in addition to elimi-
nating the trimpot. The most significant benefit is that calibra-
tion can be under the control of a microprocessor and therefore
can be implemented as part of an autocalibration scheme. Sec-
ondly, dip switches or RAM can be used to hold the 8-bit word
after its value has been determined. In Figure 42 the offset null
sensitivity, at a gain of 16, is 80 µV per LSB of adjustment,
which guarantees dc accuracy to the 16-bit performance level.
+V
S
0.1F
OUT
FORCE
9
16
15
14
13
12
11
B
10
A1 A0
CS CLK A2
LOGIC AND LATCHES
16
8
4
2
1
V
OUT
GAIN NETWORK
–
+
AD526
1
2
3
4
5
6
7
8
OUT
SENSE
V
IN
+V
S
0.1F
20k⍀
0.1F
–V
S
Figure 39. Offset Voltage Null Circuit
OUTPUT CURRENT BOOSTER
OUT
FORCE
9
16
15
14
13
12
11
B
10
A1
A0
CS CLK A2
LOGIC AND LATCHES
The AD526 is rated for a full ±10 V output voltage swing into
2 kΩ. In some applications, the need exists to drive more cur-
rent into heavier loads. As shown in Figure 40, a high current
booster may be connected “inside the loop” of the SPGA to
provide the required current boost without significantly degrad-
ing overall performance. Nonlinearities, offset and gain inaccu-
racies of the buffer are minimized by the loop gain of the
AD526 output amplifier.
16
8
4
2
1
V
OUT
GAIN NETWORK
–
+
AD526
1
2
3
4
5
6
7
8
OUT
SENSE
V
IN
+V
S
0.1F
AD581 OR
AD587
3.3M⍀
7.5M⍀
–V
S
+10V
+V
S
V
REF
ALL BYPASS CAPACITORS ARE 0.1F
0.1F
+V
S
1k⍀
0.01F
MSB
10F
LSB
CS
OUT 1
OUT 2
OUT
FORCE
9
–
AD7524
0.01F
16
15
14
13
12
11
B
10
AD548
+
WR
A1 A0
CS CLK A2
0.01F
LOGIC AND LATCHES
16
8
4
2
1
HOS-100
–V
GND
S
GAIN NETWORK
Figure 41. Offset Nulling Using a DAC
0.01F
–
+
AD526
1
2
3
4
5
6
7
8
OUT
SENSE
0.1F
V
IN
R
L
–V
S
Figure 40. Current Output Boosting
–11–
REV. D
AD526
FLOATING-POINT CONVERSION
the input falls within, relative to full scale. Once the AD526 has
settled to the appropriate level, then the second sample/hold
amplifier can be put into hold which holds the amplified signal
while the AD7572 perform its conversion routine. The acquisi-
tion time for the AD585 is 3 µs, and the conversion time for the
AD7572 is 5 µs for a total of 8 µs, or 125 kHz. This performance
relies on the fast settling characteristics of the AD526 after the
flash autoranging (comparator) circuit quantizes the input sig-
nal. A 16-bit register holds the 3-bit output from the flash autor-
anger and the 12-bit output of the AD7572.
High resolution converters are used in systems to obtain high
accuracy, improve system resolution or increase dynamic range.
There are a number of high resolution converters available with
throughput rates of 66.6 kHz that can be purchased as a single
component solution; however in order to achieve higher through-
put rates, alternative conversion techniques must be employed.
A floating point A/D converter can improve both throughput
rate and dynamic range of a system.
In a floating point A/D converter (Figure 42), the output data is
presented as a 16-bit word, the lower 12 bits from the A/D
converter form the mantissa and the upper 4 bits from the digi-
tal signal used to set the gain form the exponent. The AD526
programmable gain amplifier in conjunction with the compara-
tor circuit scales the input signal to a range between half scale
and full scale for the maximum usable resolution.
The A/D converter in Figure 42 has a dynamic range of 96 dB.
The dynamic range of a converter is the ratio of the full-scale
input range to the LSB value. With a floating-point A/D con-
verter the smallest value LSB corresponds to the LSB of the
monolithic converter divided by the maximum gain of the PGA.
The floating point A/D converter has a full-scale range of 5 V, a
maximum gain of 16 V/V from the AD526 and a 12-bit A/D
converter; this produces:
LSB = ([FSR/2N]/Gain) = ([5 V/4096]/16) = 76 µV. The
dynamic range in dBs is based on the log of the ratio of the
full-scale input range to the LSB; dynamic range = 20 log
(5 V/76 µV) = 96 dB.
The A/D converter diagrammed in Figure 42 consists of a pair
of AD585 sample/hold amplifiers, a flash converter, a five-range
programmable gain amplifier (the AD526) and a fast 12-bit A/D
converter (the AD7572). The floating-point A/D converter
achieves its high throughput rate of 125 kHz by overlapping the
acquisition time of the first sample/hold amplifier and the set-
tling time of the AD526 with the conversion time of the A/D
converter. The first sample/hold amplifier holds the signal for
the flash autoranger, which determines which binary quantum
–15V +15V
+
10F
10F
+5V
+5V
–15V +15V
+
5
6
+
1/6
+5V
10F
10F
+
BUSY
30pF
D12
D11
D10
D9
50k⍀
MSB
+5V
74-
123
1/2
CLOCK
125MHz
V
IN
74–
LS174
1
3
1/6
1/6
1s
–15V +15V
S/H
AD585
2
4
68pF
2.5MHz
68pF
D8
+
AD7572
10F
10F
–15V +15V
D7
+
+
10F
10F
10k⍀
+
F
AD526S
D6
D5
D4
D3
D2
D1
47F
V
IN
+5V
B
74–
LS174
S/H
AD585
LSB
V
A0 A1 A2
IN
10k⍀
–15V +15V
+5V
+
A0
A1
A2
10F
+
10F
E1
E2
E3
10k⍀
74ALS86
1
74–
LS174
+5V
3
12
13
REF
11
2
1/4
1/4
1/4
10k⍀
5k⍀
10k⍀
10k⍀
10k⍀
4
5
AD588
6
8
NOTE: ALL BYPASS CAPACITORS ARE 0.1F
1/4
1/4
2.5k⍀
1
2
3
9
10
1.25k⍀
1.25k⍀
1F
11
10
1/6
LM339A
Figure 42. Floating-Point A/D Converter
–12–
REV. D
AD526
HIGH ACCURACY A/D CONVERTERS
hunting during the calibration process, the reference offset and
gain codes should be different from the endpoint codes. A cali-
bration cycle consists of selecting whether gain or offset is to be
calibrated then selecting the appropriate multiplexer channel to
apply the reference voltage to the signal channel. Once the op-
eration has been initiated, the counter, a 74ALS869, drives the
D/A converter in a linear fashion providing a small correction
voltage to either the gain or offset trim point of the AD574. The
output of the A/D converter is then compared to the value pre-
set in the 74ALS528 to determine a match. Once a match is
detected, the 74ALS528 produces a low going pulse which stops
the counter. The code at the D/A converter is latched until the
next calibration cycle. Calibration cycles are under the control
of the microprocessor in this application and should be imple-
mented only during periods of converter inactivity.
Very high accuracy and high resolution floating-point A/D con-
verters can be achieved by the incorporation of offset and gain
calibration routines. There are two techniques commonly used
for calibration, a hardware circuit as shown in Figure 43 and/or
a software routine. In this application the microprocessor is
functioning as the autoranging circuit, requiring software over-
head; therefore, a hardware calibration technique was applied
which reduces the software burden. The software is used to set
the gain of the AD526. In operation the signal is converted, and
if the MSB of the AD574 is not equal to a Logical 1, the gain is
increased by binary steps, up to the maximum gain. This maxi-
mizes the full-scale range of the conversion process and insures
a wide dynamic range.
The calibration technique uses two point correction, offset and
gain. The hardware is simplified by the use of programmable
magnitude comparators, the 74ALS528s, which can be “burned”
for a particular code. In order to prevent under or over range
+5V
+
+15V
–15V
10F
200pF
10F
+
–15V +15V
MSB
NOISE
REDUCTION
1F
AD585
7404
2
1
+15V
DATA
BUS
AD574
+5V
F
S
A3
A4
R8
–15V +15V
10k⍀
AD588
R4
A1
AD7501
AD526
V
V
V
V
IN1
IN2
IN3
IN4
R1
V
REF
OP27
1k⍀
–5V
R2
R5
WR
LSB
+V
+15V
S
50k⍀
0.1F
0.1F
R6
R3
A2
SYS
GND
–15V
–V
S
DE-
CODED
ADD
+5V
DECODED
ADDRESS
DECODED
ADDRESS
–15V
WR
WR
ADDRESS BUS
12
12
+5V
CALIBRATION
PRESET
VALUE
R5
20k⍀
+5V
PIN 15
AD588
+5V
MSB
2
R6
5k⍀
PIN 28
AD574
V
REF
20k⍀
74ALS
2
528
A2
R7
1
GAIN
R2
10k⍀
RFB A
R11
5k⍀
P = Q
AD7628
AD712
MSB
1
2
2
3
C1
7400
INPUT
BUFFER
7475
1/2
OUT A
A1
LATCH DAC A
GAIN
AGND
74ALS
869
AD712
ADG221
1
R4
RFB B
7475
LSB
2
WR
C2
CONTROL
LOGIC
A3
OUT B
4
5
LATCH DAC B
LSB
6
MSB
74ALS
R8
20k⍀
7400
7475
1/2
AD712
2
R9
AGND
10k⍀
528
WR
A/B
+5V
A2
2
R10
20k⍀
V
REF
P = Q
OFFSET
AD712
R12
5k⍀
PIN 15
AD588
OFFSET
+5V
AGND
NOTE: ALL BYPASS CAPACITORS ARE 0.1F
LSB
+5V
Figure 43. High Accuracy A/D Converter
–13–
REV. D
AD526
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic
DIP Package (N-16)
16-Lead Sided-Brazed
Ceramic Package (D-16)
0.87 (22.1) MAX
0.430
(10.922)
16
9
8
0.25
0.31
16
9
(6.25)
(7.87)
0.040R
0.310 ؎0.01
(7.874 ؎0.254)
1
0.290 ؎0.010
(7.37 ؎0.254)
0.265
(6.73)
0.3 (7.62)
PIN 1
0.035
(0.89)
1
8
0.18
(4.57)
MAX
PIN 1
0.800 ؎0.010
(20.32 ؎0.254)
0.18
(4.57)
0.125 (3.18)
MIN
0.011
(0.28)
0.300
SEATING
PLANE
(7.62)
REF
0.035 ؎0.01
(0.889 ؎0.254)
0.018
(0.46)
0.100
(2.54)
0.033
(0.84)
0.095 (2.41)
0.085 (2.159)
0.125
(3.175)
MIN
0.180 ؎0.03
(4.57 ؎0.762)
0.010 ؎0.002
(0.254 ؎0.05)
0.100
(2.54)
BSC
0.047 ؎0.007
(1.19 ؎0.18)
SEATING
PLANE
+0.003
0.017
–0.002
+0.076
(0.43
)
–0.05
0.700 (17.78) BSC
REV. D
–14–
相关型号：
©2020 ICPDF网 联系我们和版权申明