5962-9316401MXA [ADI]
12-Bit 100 kSPS A/D Converter; 12位100 kSPS的A / D转换器
| 型号： | 5962-9316401MXA |
| 厂家： | 
ADI |
| 描述： | 12-Bit 100 kSPS A/D Converter |
| 文件： | 总12页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit 100 kSPS
A/D Converter
a
AD1674*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Com plete Monolithic 12-Bit 10 s Sam pling ADC
On-Board Sam ple-and-Hold Am plifier
Industry Standard Pinout
12/8
CS
STS
A
CONTROL
0
CE
8- and 16-Bit Microprocessor Interface
AC and DC Specified and Tested
Unipolar and Bipolar Inputs
R/C
10V
REF
CLOCK
SAR
REF OUT
12
؎5 V, ؎10 V, 0 V–10 V, 0 V–20 V Input Ranges
Com m ercial, Industrial and Military Tem perature
Range Grades
DB11 (MSB)
DB0 (LSB)
AGND
COMP
12
20k
REF IN
12
5k
10k
10k
MIL-STD-883 and SMD Com pliant Versions Available
BIP OFF
20V
IN
DAC
5k
2.5k
2.5k
10V
IN
IDAC
5k
SHA
AD1674
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD1674 is a complete, multipurpose, 12-bit analog-to-
digital converter, consisting of a user-transparent onboard
sample-and-hold amplifier (SHA), 10 volt reference, clock and
three-state output buffers for microprocessor interface.
1. Industry Standard Pinout: T he AD1674 utilizes the pinout
established by the industry standard AD574A and AD674A.
2. Integrated SHA: T he AD1674 has an integrated SHA which
supports the full Nyquist bandwidth of the converter. T he
SHA function is transparent to the user; no wait-states are
needed for SHA acquisition.
T he AD1674 is pin compatible with the industry standard
AD574A and AD674A, but includes a sampling function while
delivering a faster conversion rate. T he on-chip SHA has a wide
input bandwidth supporting 12-bit accuracy over the full
Nyquist bandwidth of the converter.
3. DC and AC Specified: In addition to traditional dc specifica-
tions, the AD1674 is also fully specified for frequency do-
main ac parameters such as total harmonic distortion,
signal-to-noise ratio and input bandwidth. T hese parameters
can be tested and guaranteed as a result of the onboard
SHA.
T he AD1674 is fully specified for ac parameters (such as S/(N+D)
ratio, T H D, and IMD) and dc parameters (offset, full-scale
error, etc.). With both ac and dc specifications, the AD1674 is
ideal for use in signal processing and traditional dc measure-
ment applications.
4. Analog Operation: T he precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges:
0 V to +10 V and 0 V to +20 V unipolar, –5 V to +5 V and
–10 V to +10 V bipolar. T he AD1674 operates on +5 V and
±12 V or ±15 V power supplies.
T he AD1674 design is implemented using Analog Devices’
BiMOS II process allowing high performance bipolar analog cir-
cuitry to be combined on the same die with digital CMOS logic.
Five different temperature grades are available. T he AD1674J
and K grades are specified for operation over the 0°C to +70°C
temperature range. T he A and B grades are specified from
–40°C to +85°C; the AD1674T grade is specified from –55°C
to +125°C. T he J and K grades are available in both 28-lead
plastic DIP and SOIC. T he A and B grade devices are available
in 28-lead hermetically sealed ceramic DIP and 28-lead SOIC.
T he T grade is available in 28-lead hermetically sealed ceramic
DIP.
5. Flexible Digital Interface: On-chip multiple-mode
three-state output buffers and interface logic allow direct
connection to most microprocessors.
*P r otected by U. S. P atent Nos. 4,962,325; 4,250,445; 4,808,908; RE 30586 .
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD1674–SPECIFICATIONS
(TMIN to T , V = +15 V ؎ 10% or +12 V ؎ 5%, VLOGIC = +5 V ؎ 10%, V = –15 V ؎ 10% or
MAX CC
EE
DC SPECIFICATIONS
–12 V ؎ 5% unless otherwise noted)
AD 1674J
Typ
AD 1674K
P aram eter
Min
Max
Min
Typ
Max
Unit
Bits
RESOLUT ION
12
12
12
INT EGRAL NONLINEARIT Y (INL)
±1
±1/2
LSB
DIFFERENT IAL NONLINEARIT Y (DNL)
(No Missing Codes)
12
Bits
LSB
LSB
UNIPOLAR OFFSET 1 @ +25°C
BIPOLAR OFFSET 1 @ +25°C
±3
±6
±2
±4
FULL-SCALE ERROR1, 2 @ +25°C
(with Fixed 50 Ω Resistor from REF OUT to REF IN)
0.1
0.25
+70
0.1
0.25
+70
% of FSR
T EMPERAT URE RANGE
0
0
°C
T EMPERAT URE DRIFT 3
Unipolar Offset2
±2
±2
±6
±1
±1
±3
LSB
LSB
LSB
Bipolar Offset2
Full-Scale Error2
POWER SUPPLY REJECT ION
VCC = 15 V ± 1.5 V or 12 V ± 0.6 V
VLOGIC = 5 V ± 0.5 V
±2
±1/2
±2
±1
±1/2
±1
LSB
LSB
LSB
VEE = –15 V ± 1.5 V or –12 V ± 0.6 V
ANALOG INPUT
Input Ranges
Bipolar
–5
–10
0
+5
–5
–10
0
+5
Volts
Volts
Volts
Volts
+10
+10
+20
+10
+10
+20
Unipolar
0
0
Input Impedance
10 Volt Span
20 Volt Span
3
6
5
10
7
14
3
6
5
10
7
14
kΩ
kΩ
POWER SUPPLIES
Operating Voltages
VLOGIC
VCC
VEE
+4.5
+11.4
–16.5
+5.5
+16.5
–11.4
+4.5
+11.4
–16.5
+5.5
+16.5
–11.4
Volts
Volts
Volts
Operating Current
ILOGIC
ICC
IEE
5
10
14
8
14
18
5
10
14
8
14
18
mA
mA
mA
POWER DISSIPAT ION
385
575
385
575
mW
INT ERNAL REFERENCE VOLT AGE
9.9
10.0
10.1
2.0
9.9
10.0
10.1
2.0
Volts
mA
Output Current (Available for External Loads)4
(External Load Should Not Change During Conversion
NOT ES
1Adjustable to zero.
2Includes internal voltage reference error.
3Maximum change from 25°C value to the value at T MIN or T MAX
4Reference should be buffered for ±12 V operation.
.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. C
AD1674
AD 1674A
AD 1674B
AD 1674T
P aram eter
Min Typ Max Min Typ Max Min Typ Max
Unit
RESOLUT ION
12
12
12
12
12
12
Bits
INT EGRAL NONLINEARIT Y (INL)
±1
±1
±1/2
±1/2
±1/2
±1
LSB
LSB
DIFFERENT IAL NONLINEARIT Y (DNL)
(No Missing Codes)
Bits
LSB
LSB
UNIPOLAR OFFSET 1 @ +25°C
BIPOLAR OFFSET 1 @ +25°C
±2
±6
±2
±3
±2
±3
FULL-SCALE ERROR1, 2 @ +25°C
(with Fixed 50 Ω Resistor from REF OUT to REF IN)
0.1
0.25
0.1
0.125
0.1
0.125 % of FSR
T EMPERAT URE RANGE
–40
+85 –40
+85 –55
+125
°C
T EMPERAT URE DRIFT 3
Unipolar Offset2
±2
±2
±8
±1
±1
±5
±1
±2
±7
LSB
LSB
LSB
Bipolar Offset2
Full-Scale Error2
POWER SUPPLY REJECT ION
VCC = 15 V ± 1.5 V or 12 V ± 0.6 V
VLOGIC = 5 V ± 0.5 V
±2
±1/2
±2
±1
±1/2
±1
±1
±1/2
±1
LSB
LSB
LSB
VEE = –15 V ± 1.5 V or –12 V ± 0.6 V
ANALOG INPUT
Input Ranges
Bipolar
–5
–10
0
+5
–5
+5
–5
+5
Volts
Volts
Volts
Volts
+10 –10
+10
+20
+10 –10
+10
+20
+10
+10
+20
Unipolar
0
0
0
0
0
Input Impedance
10 Volt Span
20 Volt Span
3
6
5
10
7
14
3
6
5
10
7
14
3
6
5
10
7
14
kΩ
kΩ
POWER SUPPLIES
Operating Voltages
VLOGIC
VCC
VEE
+4.5
+11.4
–16.5
+5.5 +4.5
+16.5 +11.4
–11.4 –16.5
+5.5 +4.5
+16.5 +11.4
–11.4 –16.5
+5.5
+16.5 Volts
–11.4
Volts
Volts
Operating Current
ILOGIC
ICC
IEE
5
10
14
8
14
18
5
10
14
8
14
18
5
10
14
8
14
18
mA
mA
mA
POWER DISSIPAT ION
385
575
385
575
385
575
mW
INT ERNAL REFERENCE VOLT AGE
9.9
10.0 10.1 9.9
2.0
10.0 10.1 9.9
2.0
10.0 10.1
2.0
Volts
mA
Output Current (Available for External Loads)4
(External Load Should Not Change During Conversion
REV. C
–3–
AD1674–SPECIFICATIONS
AC SPECIFICATIONS
(TMIN to T , with V = +15 V ؎ 10% or +12 V ؎ 5%, VLOGIC = +5 V ؎ 10%, V = –15 V ؎10% or
MAX
CC
EE
–12 V ؎ 5%, fSAMPLE = 100 kSPS, fIN = 10 kHz, stand-alone mode unless otherwise noted)1
AD 1674J/A
Typ
AD 1674K/B/T
Typ
P aram eter
Min
Max
Min
Max
Units
Signal to Noise and Distortion (S/N+D) Ratio2, 3
T otal Harmonic Distortion (T HD)4
69
70
70
71
dB
–90
–82
0.008
–90
–82
0.008
dB
%
Peak Spurious or Peak Harmonic Component
–92
–82
–92
–82
dB
Full Power Bandwidth
Full Linear Bandwidth
1
500
1
500
MHz
kHz
Intermodulation Distortion (IMD)5
Second Order Products
T hird Order Products
–90
–90
–80
–80
–90
–90
–80
–80
dB
dB
SHA (Specifications are Included in Overall Timing Specifications)
Aperture Delay
Aperture Jitter
Acquisition T ime
50
250
1
50
250
1
ns
ps
µs
MIN to T , with V = +15 V ؎ 10% or +12 V ؎ 5%, VLOGIC = +5 V ؎ 10%,
V = –15 V ؎ 10% or –12 V ؎ 5%)
EE
DIGITAL SPECIFICATIONS (for all grades T
MAX
CC
P aram eter
Test Conditions
Min
Max
Units
LOGIC INPUT S
VIH
VIL
IIH
IIL
CIN
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 5 V)
Low Level Input Current (VIN = 0 V)
Input Capacitance
+2.0
–0.5
–10
VLOGIC +0.5 V
V
V
µA
µA
pF
+0.8
+10
+10
10
VIN = VLOGIC
VIN = 0 V
–10
LOGIC OUT PUT S
VOH
VOL
IOZ
High Level Output Voltage
IOH = 0.5 mA
IOL = 1.6 mA
VIN = 0 to VLOGIC
+2.4
–10
V
V
µA
pF
Low Level Output Voltage
High-Z Leakage Current
High-Z Output Capacitance
+0.4
+10
10
COZ
NOT ES
1fIN amplitude = –0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to –0 dB (9.997 V p-p) input signal unless
otherwise noted.
2Specified at worst case temperatures and supplies after one minute warm-up.
3See Figures 12 and 13 for other input frequencies and amplitudes.
4See Figure 11.
5fa = 9.08 kHz, fb = 9.58 kHz with fSAMPLE = 100 kHz. See Definition of Specifications section and Figure 15.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
REV. C
–4–
AD1674
(for all grades TMIN to TMAX with V = +15 V ؎ 10% or +12 V ؎ 5%,
CC
V
LOGIC = +5 V ؎10%, V = –15 V ؎ 10% or –12 V ؎ 5%; V = 0.4 V,
EE IL
V = 2.4 V unless otherwise noted)
IH
SWITCHING SPECIFICATIONS
CO NVERTER START TIMING (Figur e 1)
J, K, A, B, Grades
T Grade
P aram eter
Sym bol Min Typ Max Min Typ Max Units
tHEC
tHSC
CE
Conversion T ime
8-Bit Cycle
12-Bit Cycle
__
CS
tC
tC
tDSC
tHEC
tSSC
7
9
8
10
200
7
9
8
10
225 ns
µs
µs
tSSC
ST S Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High tHSC
R/C to CE Setup tSRC
R/C Low During CE High tHRC
A0 to CE Setup tSAC
A0 Valid During CE High tHAC
_
R/C
tSRC tHRC
50
50
50
50
50
0
50
50
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
tSAC
tHAC
A
0
tC
50
50
STS
tDSC
DB11 – DB0
HIGH IMPEDANCE
READ TIMING—FULL CO NTRO L MO D E ( Figur e 2)
J, K, A, B, Grades
T Grade
Figure 1. Converter Start Tim ing
P aram eter
Sym bol Min Typ Max Min Typ Max Units
1
Access T ime
Data Valid After CE Low tHD
tDD
75
150
150
75 150 ns
252
203
252
154
ns
ns
150 ns
CE
__
CS
5
tHSR
Output Float Delay
CS to CE Setup
R/C to CE Setup
A0 to CE Setup
tHL
tSSR
tSSR
tSRR
tSAR
50
0
50
0
50
0
50
0
ns
ns
ns
ns
ns
_
R/C
tSSR
tHRR
CS Valid After CE Low tHSR
R/C High After CE Low tHRR
0
0
A0 Valid After CE Low
tHAR
50
50
ns
A
0
tSAR
tHAR
NOT ES
1tDD is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
tHS
STS
20°C to T MAX
3At –40°C.
4At –55°C.
.
tHD
HIGH
IMPEDANCE
HIGH
IMP.
5tHL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
DATA
VALID
DB11 – DB0
tDD
tHL
All min and max specifications are guaranteed.
Specifications subject to change without notice.
Figure 2. Read Tim ing
Test
VCP
CO UT
Access T ime High Z to Logic Low
Float T ime Logic High to High Z
Access T ime High Z to Logic High
Float T ime Logic Low to High Z
5 V
0 V
0 V
5 V
100 pF
10 pF
100 pF
10 pF
I
OL
D
OUT
V
CP
C
OUT
I
OH
Figure 3. Load Circuit for Bus Tim ing Specifications
REV. C
–5–
AD1674
TIMING—STAND -ALO NE MO D E (F igur es 4a and 4b)
J, K, A, B Grades
Typ
T Grade
Typ
P aram eter
Sym bol
Min
Max
Min
Max
Units
Data Access T ime
tDDR
tHRL
tDS
tHDR
tHS
150
150
ns
ns
ns
ns
µs
ns
Low R/C Pulse Width
ST S Delay from R/C
Data Valid After R/C Low
ST S Delay After Data Valid
High R/C Pulse Width
50
50
200
1.2
225
1.2
25
0.6
150
25
0.6
150
0.8
0.8
tHRH
NOT E
All min and max specifications are guaranteed.
Specifications subject to change without notice.
tHRL
_
R/C
_
R/C
tHRH
tDS
tDS
STS
STS
tC
tDDR
tHDR
tC
tHS
tHDR
HIGH-Z
HIGH-Z
DATA
VALID
DB11 – DB0
HIGH-Z
DATA
VALID
DB11 – DB0
DATA VALID
tHL
Figure 4a. Stand-Alone Mode Tim ing Low Pulse for R/C
Figure 4b. Stand-Alone Mode Tim ing High Pulse for R/C
. . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead T emperature, Soldering (10 sec) . . . . . . . +300°C, 10 sec
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
ABSO LUTE MAXIMUM RATINGS*
VCC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to + 16.5 V
VEE to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V
VLOGIC to Digital Common . . . . . . . . . . . . . . . . . . 0 V to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V
Digital Inputs to Digital Common . . . –0.5 V to VLOGIC +0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . VEE to VCC
20 VIN to Analog Common . . . . . . . . . . . . . . . . . VEE to +24 V
REF OUT . . . . . . . . . . . . . . . . . Indefinite Short to Common
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1674 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. T herefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
O RD ERING GUID E
INL
(TMIN to TMAX
S/(N+D )
(TMIN to TMAX
P ackage
D escription
P ackage
O ption2
Model1
Tem perature Range
)
)
AD1674JN
AD1674KN
AD1674JR
AD1674KR
AD1674AR
AD1674BR
AD1674AD
AD1674BD
AD1674T D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
69 dB
70 dB
69 dB
70 dB
69 dB
70 dB
69 dB
70 dB
70 dB
Plastic DIP
Plastic DIP
N-28
N-28
R-28
R-28
R-28
R-28
D-28
D-28
D-28
Plastic SOIC
Plastic SOIC
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
±1/2 LSB
±1 LSB
NOT ES
1For details on grade and package offerings screened in accordance with MIL-ST D-883, refer to the Analog Devices Military Products Databook or current
AD1674/883B data sheet. SMD is also available.
2N = Plastic DIP; D = Hermetic Ceramic DIP; R = Plastic SOIC.
–6–
REV. C
AD1674
P IN D ESCRIP TIO N
Sym bol
P in No. Type
Nam e and Function
Analog Ground (Common).
AGND
A0
9
4
P
DI
Byte Address/Short Cycle. If a conversion is started with A0 Active LOW, a full 12-bit conversion
cycle is initiated. If A0 is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/C = 1) with 12/8 LOW, A0 = LOW enables the 8 most significant bits
(DB4–DB11), and A0 = HIGH enables DB3–DB0 and sets DB7–DB4 = 0.
BIP OFF
12
AI
Bipolar Offset. Connect through a 50 Ω resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
CE
6
3
DI
DI
Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
Chip Select. Chip Select is Active LOW.
CS
DB11–DB8 27–24
DO
Data Bits 11 through 8. In the 12-bit format (see 12/8 and A0 pins), these pins provide the up-
per 4 bits of data. In the 8-bit format, they provide the upper 4 bits when A0 is LOW and are
disabled when A0 is HIGH.
DB7–DB4
DB3–DB0
23–20
19–16
DO
DO
Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when Ao is LOW and all zeroes when A0 is HIGH.
Data Bits 3 through 0. In the 12-bit format these pins provide the lower 4 bits of data. In the
8-bit format these pins provide the lower 4 bits of data when A0 is HIGH, they are disabled
when A0 is LOW.
DGND
REF OUT
R/C
15
8
P
Digital Ground (Common).
+10 V Reference Output.
AO
DI
5
Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW
for a convert operation. In the stand-alone mode, the falling edge of R/C initiates a conversion.
REF IN
ST S
10
28
AI
Reference Input is connected through a 50 Ω resistor to +10 V Reference for normal operation.
DO
Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
VCC
7
P
+12 V/+15 V Analog Supply.
–12 V/–15 V Analog Supply.
+5 V Logic Supply.
VEE
11
1
P
VLOGIC
10 VIN
P
13
AI
10 V Span Input, 0 V to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the
AD1674 in the 20 V Span 10 VIN should not be connected.
20 VIN
14
2
AI
20 V Span Input, 0 V to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using
the AD1674 in the 10 V Span 20 VIN should not be connected.
12/8
DI
T he 12/8 pin determines whether the digital output data is to be organized as two 8-bit words
(12/8 LOW) or a single 12-bit word (12/8 HIGH).
T YPE: AI
=
=
=
Analog Input
Analog Output
Digital Input
AO
DI
FUNCTIO NAL BLO CK D IAGRAM
P IN CO NFIGURATIO N
DO = Digital Output
12/8
CS
P
=
Power
V
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
STS
LOGIC
12/8
STS
DB11(MSB)
DB10
A
CONTROL
0
CS
CE
A
0
DB9
R/C
R/C
CE
DB8
DB7
10V
CLOCK
SAR
REF OUT
AD1674
REF
DB6
V
12
CC
TOP VIEW
REF OUT
AGND
DB5
DB4
(Not to Scale)
DB11 (MSB)
DB0 (LSB)
AGND
COMP
12
20k
REF IN 10
DB3
REF IN
12
V
11
12
13
14
DB2
DB1
5k
10k
10k
EE
BIP OFF
BIP OFF
20V
IN
DAC
16 DB0(LSB)
10V
IN
5k
2.5k
2.5k
20V
IN
15
DGND
10V
IN
IDAC
5k
SHA
AD1674
REV. C
–7–
AD1674
D EFINITIO N O F SP ECIFICATIO NS
are present in a sample sequence. T he result, called Prime
Coherent Sampling, is a highly accurate and repeatable measure
of the actual frequency-domain response of the converter.
INTEGRAL NO NLINEARITY (INL)
T he ideal transfer function for an ADC is a straight line drawn
between “zero” and “full scale.” T he point used as “zero”
occurs 1/2 LSB before the first code transition. “Full scale” is
defined as a level 1 1/2 LSB beyond the last code transition.
Integral nonlinearity is the worst-case deviation of a code from
the straight line. T he deviation of each code is measured from
the middle of that code.
NYQ UIST FREQ UENCY
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
SIGNAL-TO -NO ISE AND D ISTO RTIO N (S/N+D ) RATIO
S/(N+D) is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. T he
value for S/(N+D) is expressed in decibels.
D IFFERENTIAL NO NLINEARITY (D NL)
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing
sequence as the analog input level is increased. T hus every code
must have a finite width. T he AD1674 guarantees no missing
codes to 12-bit resolution; all 4096 codes are present over the
entire operating range.
TO TAL H ARMO NIC D ISTO RTIO N (TH D )
T HD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
UNIP O LAR O FFSET
T he first transition should occur at a level 1/2 LSB above ana-
log common. Unipolar offset is defined as the deviation of the
actual transition from that point at 25°C. T his offset can be
adjusted as shown in Figure 11.
INTERMO D ULATIO N D ISTO RTIO N (IMD )
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for
which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb) and the third order terms
are (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). T he IMD
products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
T he two signals are of equal amplitude and the peak value of
their sums is –0.5 dB from full scale. T he IMD products are
normalized to a 0 dB input signal.
BIP O LAR O FFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. T he bipolar offset error specifies the
deviation of the actual transition from that point at 25°C. T his
offset can be adjusted as shown in Figure 12.
FULL-SCALE ERRO R
T he last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10 volts full scale). T he full-scale
error is the deviation of the actual level of the last transition
from the ideal level at 25°C. The full-scale error can be adjusted
to zero as shown in Figures 11 and 12.
FULL-P O WER BAND WID TH
T he full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
TEMP ERATURE D RIFT
T he temperature drifts for full-scale error, unipolar offset and
bipolar offset specify the maximum change from the initial
FULL-LINEAR BAND WID TH
T he full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than –0.1 dB. Beyond this frequency, dis-
tortion of the sampled input signal increases significantly.
(25°C) value to the value at TMIN or T MAX
.
P O WER SUP P LY REJECTIO N
T he effect of power supply error on the performance of the
device will be a small change in full scale. T he specifications
show the maximum full-scale change from the initial value with
the supplies at various limits.
AP ERTURE D ELAY
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Read/Convert (R/C) to when
the input signal is held for conversion.
FREQ UENCY-D O MAIN TESTING
T he AD1674 is tested dynamically using a sine wave input and
a 2048 point Fast Fourier T ransform (FFT ) to analyze the
resulting output. Coherent sampling is used, wherein the ADC
sampling frequency and the analog input frequency are related
to each other by a ratio of integers. T his ensures that an integral
multiple of input cycles is captured, allowing direct FFT pro-
cessing without windowing or digital filtering which could mask
some of the dynamic characteristics of the device. In addition,
the frequencies are chosen to he “relatively prime” (no common
factors) to maximize the number of different ADC codes that
AP ERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
–8–
REV. C
Typical Dynamic Performance–AD1674
80
70
fSAMPLE = 100kSPS
FULL-SCALE = +10V
0dB INPUT
0
60
–20dB INPUT
–20
50
40
THD
–40
–60
30
20
–80
RD
3
–60dB INPUT
HARMONIC
–100
–120
10
0
ND
2
HARMONIC
1
10
100
1000 10000
1
10
100
1000
10000
INPUT FREQUENCY – kHz
INPUT FREQUENCY – kHz
Figure 5. Harm onic Distortion vs.
Input Frequency
Figure 6. S/(N+D) vs. Input Frequency
and Am plitude
Figure 7. S/(N+D) vs. Input Am plitude
0
0
–10
–20
–20
–30
–40
–40
–50
–60
–60
–70
–80
–80
–100
–120
–140
–90
–100
–110
–120
–130
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY – kHz
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY – kHz
Figure 8. Nonaveraged 2048 Point FFT
at 100 kSPS, fIN = 25.049 kHz
Figure 9. IMD Plot for fIN = 9.08 kHz (fa), 9.58 kHz (fb)
DAC current sum to be greater than or less than the input cur-
rent. If the sum is less, the bit is left on; if more, the bit is
turned off. After testing all the bits, the SAR contains a 12-bit
binary code which accurately represents the input signal to
within ±1/2 LSB.
GENERAL CIRCUIT O P ERATIO N
T he AD1674 is a complete 12-bit, 10 µs sampling analog-to-
digital converter. A block diagram of the AD1674 is shown on
page 7.
When the control section is commanded to initiate a conversion
(as described later), it places the sample-and-hold amplifier
(SHA) in the hold mode, enables the clock, and resets the suc-
cessive approximation register (SAR). Once a conversion cycle
has begun, it cannot be stopped or restarted and data is not
available from the output buffers. T he SAR, timed by the inter-
nal clock, will sequence through the conversion cycle and return
an end-of-convert flag to the control section when the conver-
sion has been completed. T he control section will then disable
the clock, switch the SHA to sample mode, and delay the ST S
LOW going edge to allow for acquisition to 12-bit accuracy.
T he control section will allow data read functions by external
command anytime during the SHA acquisition interval.
CO NTRO L LO GIC
T he AD1674 may be operated in one of two modes, the full-
control mode and the stand-alone mode. T he full-control mode
utilizes all the AD1674 control signals and is useful in systems
that address decode multiple devices on a single data bus. T he
stand-alone mode is useful in systems with dedicated input ports
available and thus not requiring full bus interface capability.
T able I is a truth table for the AD1674, and Figure 10 illus-
trates the internal logic circuitry.
Table I. AD 1674A Truth Table
CE CS R/C 12/8 A0 O peration
During the conversion cycle, the internal 12-bit, 1 mA full-scale
current output DAC is sequenced by the SAR from the most
significant bit (MSB) to the least significant bit (LSB) to pro-
vide an output that accurately balances the current through the
5 kΩ resistor from the input signal voltage held by the SHA.
T he SHA’s input scaling resistors divide the input voltage by 2
for the 10 V input span and by 4 V for the 20 V input span,
maintaining a 1 mA full-scale output current through the 5 kΩ
resistor for both ranges. T he comparator determines whether
the addition of each successively weighted bit current causes the
0
X
X
1
X
X
X
X
X
X
None
None
1
1
0
0
0
0
X
X
0
1
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
1
0
1
1
X
Enable 12-Bit Parallel Output
1
1
0
0
1
1
0
0
0
1
Enable 8 Most Significant Bits
Enable 4 LSBs +4 T railing Zeroes
–9–
REV. C
AD1674
VALUE OF A AT LAST
0
CONVERT COMMAND
Q
D
Q
D
QB
EOC 12
EOC 8
EN
EN
R
S
Q
SAR RESET
S
R
Q
QB
1µs DELAY-HOLD SETTLING
CE
CLK ENABLE
STATUS
CS
R/C
1µs DELAY-ACQUISITION
HOLD/SAMPLE
A
0
NYBBLE A
NYBBLE B
READ
12/8
TO OUTPUT
BUFFERS
NYBBLE C
NYBBLE B = 0
Figure 10. Equivalent Internal Logic Circuitry
FULL-CO NTRO L MO D E
T he register control inputs, A0 and 12/8, control conversion
length and data format. If a conversion is started with A0 LOW,
a full 12-bit conversion cycle is initiated. If A0 is HIGH during a
convert start, a shorter 8-bit conversion cycle results.
Chip Enable (CE), Chip Select (CS) and Read/ Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or CS may be used to initiate a conversion. T he state of R/C
when CE and CS are both asserted determines whether a data
Read (R/C = 1) or a Convert (R/C = 0) is in progress. R/C
should be LOW before both CE and CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly
resulting in system bus contention.
During data read operations, A0 determines whether the three-
state buffers containing the 8 MSBs of the conversion result (A0
= 0) or the 4 LSBs (A0 = 1) are enabled. T he 12/8 pin deter-
mines whether the output data is to be organized as two 8-bit
words (12/8 tied LOW) or a single 12-bit word (12/8 tied
HIGH). In the 8-bit mode, the byte addressed when A0 is high
contains the 4 LSBs from the conversion followed by four trail-
ing zeroes. T his organization allows the data lines to be over-
lapped for direct interface to 8-bit buses without the need for
external three-state buffers.
STAND -ALO NE MO D E
T he AD1674 can be used in a “stand-alone” mode, which is
useful in systems with dedicated input ports available and thus
not requiring full bus interface capability. Stand-alone mode
applications are generally able to issue conversion start com-
mands more precisely than full-control mode. T his improves ac
performance by reducing the amount of control-induced aper-
ture jitter.
INP UT CO NNECTIO NS AND CALIBRATIO N
T he 10 V p-p and 20 V p-p full-scale input ranges of the
AD1674 accept the majority of signal voltages without the need
for external voltage divider networks which could deteriorate the
accuracy of the ADC.
In stand-alone mode, the control interface for the AD1674 and
AD674A are identical. CE and 12/8 are wired HIGH, CS and
A0 are wired LOW, and conversion is controlled by R/C. T he
three-state buffers are enabled when R/C is HIGH and a con-
version starts when R/C goes LOW. T his gives rise to two pos-
sible control signals—a high pulse or a low pulse. Operation
with a low pulse is shown in Figure 4a. In this case, the outputs
are forced into the high impedance state in response to the fall-
ing edge of R/C and return to valid logic levels after the conver-
sion cycle is completed. T he ST S line goes HIGH 200 ns after
R/C goes LOW and returns low 1 µs after data is valid.
T he AD1674 is factory trimmed to minimize offset, linearity,
and full-scale errors. In many applications, no calibration trim-
ming will be required and the AD1674 will exhibit the accuracy
limits listed in the specification tables.
In some applications, offset and full-scale errors need to be
trimmed out completely. T he following sections describe the
correct procedure for these various situations.
UNIP O LAR RANGE INP UTS
If conversion is initiated by a high pulse as shown in Figure 4b,
the data lines are enabled during the time when R/C is HIGH.
T he falling edge of R/C starts the next conversion and the data
lines return to three-state (and remain three-state) until the next
high pulse of R/C.
Figure 11 illustrates the external connections for the AD1674 in
unipolar-input mode. T he first output-code transition (from
0000 0000 0000 to 0000 0000 0001) should nominally occur
for an input level of +1/2 LSB (1.22 mV above ground for a 10 V
range; 2.44 mV for a 20 V range). T o trim unipolar offset to this
nominal value, apply a +1/2 LSB signal between Pin 13 and
ground (10 V range) or Pin 14 and ground (20 V range) and ad-
just R1 until the first transition is located. If the offset trim is
not required, Pin 12 can be connected directly to Pin 9; the two
resistors and trimmer for Pin 12 are then not needed.
CO NVERSIO N TIMING
Once a conversion is started, the ST S line goes HIGH. Convert
start commands will be ignored until the conversion cycle is
complete. T he output data buffers will be enabled a minimum
of 0.6 µs prior to ST S going LOW. T he ST S line will return
LOW at the end of the conversion cycle.
–10–
REV. C
AD1674
R1
100k
REFERENCE D ECO UP LING
2
12/8
CS
STS 28
It is recommended that a 10 µF tantalum capacitor be con-
nected between REF IN (Pin 10) and ground. T his has the
effect of improving the S/(N+D) ratio through filtering possible
broad-band noise contributions from the voltage reference.
3
4
HIGH BITS
24-27
+15V
–15V
A
0
5
6
R/C
CE
MIDDLE BITS
20-23
R2
100Ω
100k
100Ω
10 REF IN
LOW BITS
16-19
8
REF OUT
BO ARD LAYO UT
12 BIP OFF
Designing with high resolution data converters requires careful
attention to board layout. T race impedance is a significant issue.
At the 12-bit level, a 5 mA current through a 0.5 Ω trace will
develop a voltage drop of 2.5 mV, which is 1 LSB for a 10 V
full-scale range. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies should be decoupled in order to
filter out ac noise.
AD1674
+5V
+15V
1
7
0 TO +10V
ANALOG
INPUTS
13 10V
14 20V
IN
–15V 11
IN
0 TO +20V
9
ANA COM DIG COM 15
Figure 11. Unipolar Input Connections with Gain and
Offset Trim s
T he full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 V for a 10 V range) and adjusting
R2 until the last transition is located (1111 1111 1110 to 1111
1111 1111). If full-scale adjustment is not required, R2 should
be replaced with a fixed 50 Ω ±1% metal film resistor. If REF
OUT is connected directly to REF IN, the additional full-scale
error will be approximately 1%.
T he AD1674 has a wide bandwidth sampling front end. T his
means that the AD1674 will “see” high frequency noise at the
input, which nonsampling (or limited-bandwidth sampling)
ADCs would ignore. T herefore, it’s important to make an effort
to eliminate such high frequency noise through decoupling or by
using an anti-aliasing filter at the analog input of the AD1674.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single inter-
connection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them (if necessary) only at right angles.
BIP O LAR RANGE INP UTS
T he connections for the bipolar-input mode are shown in Figure
12. Either or both of the trimming potentiometers can be
replaced with 50 Ω ± 1% fixed resistors if the specified AD1674
accuracy limits are sufficient for the application. If the pins are
shorted together, the additional offset and gain errors will be
approximately 1%.
T o trim bipolar offset to its nominal value, apply a signal 1/2
LSB below midrange (–1.22 mV for a ±5 V range) and adjust
R1 until the major carry transition is located (0111 1111 1111
to 1000 0000 0000). T o trim the full-scale error, apply a signal
1 1/2 LSB below full scale (+4.9963 V for a ±5 V range) and
adjust R2 to give the last positive transition (1111 1111 1110 to
1111 1111 1111). T hese trims are interactive so several itera-
tions may be necessary for convergence.
T he AD1674 incorporates several features to help the user’s lay-
out. Analog pins are adjacent to help isolate analog from digital
signals. Ground currents have been minimized by careful circuit
architecture. Current through AGND is 2.2 mA, with little
code-dependent variation. T he current through DGND is domi-
nated by the return current for DB11–DB0.
A single-pass calibration can be done by substituting a negative
full-scale trim for the bipolar offset trim (error at midscale),
using the same circuit. First, apply a signal 1/2 LSB above minus
full scale (–4.9988 V for a ±5 V range) and adjust R1 until the
minus full-scale transition is located (0000 0000 0001 to 0000
0000 0000). Then perform the gain error trim as outlined above.
SUP P LY D ECO UP LING
T he AD1674 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and ground. A 10 µF tanta-
lum capacitor in parallel with a 0.1 µF disc ceramic capacitor
provides adequate decoupling over a wide range of frequencies.
2
12/8
CS
STS 28
3
4
HIGH BITS
24-27
A
0
5
6
R/C
CE
MIDDLE BITS
20-23
R2
100Ω
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. T he circuit layout should attempt to locate
the AD1674, associated analog input circuitry, and interconnec-
tions as far as possible from logic circuitry. A solid analog
ground plane around the AD1674 will isolate large switching
ground currents. For these reasons, the use of wire-wrap circuit
construction is not recommended; careful printed-circuit con-
struction is preferred.
10 REF IN
LOW BITS
16-19
8
REF OUT
12 BIP OFF
R1
100Ω
AD1674
+5V
+15V
1
7
±5V
13 10V
14 20V
IN
ANALOG
INPUTS
±10V
–15V 11
IN
9
ANA COM DIG COM 15
Figure 12. Bipolar Input Connections with Gain and Offset
Trim s
REV. C
–11–
AD1674
GRO UND ING
P ACKAGE INFO RMATIO N
If a single AD1674 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. T hen connect AGND and DGND together at the
AD1674. If multiple AD1674s are used or the AD1674 shares
analog supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. T his prevents large ground loops which inductively
couple noise and allow digital currents to flow through the ana-
log system.
D imensions shown in inches and (mm).
28-P in Ceram ic D IP P ackage (D -28)
0.505 (12.83)
28
15
0.59 ±0.01
(14.98 ±0.254)
PIN 1
14
1
GENERAL MICRO P RO CESSO R INTERFACE
CO NSID ERATIO NS
0.050 ±0.010
(1.27 ±0.254)
0.095
(2.41)
1.42 (36.07)
1.40 (35.56)
A typical A/D converter interface routine involves several opera-
tions. First, a write to the ADC address initiates a conversion.
T he processor must then wait for the conversion cycle to com-
plete, since most ADCs take longer than one instruction cycle to
complete a conversion. Valid data can, of course, only be read
after the conversion is complete. T he AD1674 provides an out-
put signal (ST S) which indicates when a conversion is in
progress. T his signal can be polled by the processor by reading
it through an external three-state buffer (or other input port).
T he ST S signal can also be used to generate an interrupt upon
completion of a conversion, if the system timing requirements
are critical (bear in mind that the maximum conversion time of
the AD1674 is only 10 microseconds) and the processor has
other tasks to perform during the ADC conversion cycle. An-
other possible time-out method is to assume that the ADC will
take 10 microseconds to convert, and insert a sufficient number
of “no-op” instructions to ensure that 10 microseconds of pro-
cessor time is consumed.
0.145 ±0.02
(3.68 ±0.51)
0.125
(3.17)
MIN
0.010 ±0.002
(0.254 ±0.05)
0.085
(2.16)
0.6 (15.24)
SEATING
PLANE
0.047 ±0.007
(1.19 ±0.178)
0.1 (2.54)
0.017 ±0.003
(0.43 ±0.076)
28-Lead P lastic D IP P ackage (N-28)
28
1
15
0.550 (13.97)
0.530 (13.462)
PIN 1
14
0.606 (15.39)
0.594 (15.09)
1.450 (38.83)
1.440 (35.576)
0.160 (4.06)
0.140 (3.56)
0.200
(5.080)
MAX
15
°
0.012 (0.305)
0.008 (0.203)
0°
0.175 (4.45)
0.105 (2.67)
0.065 (1.65)
0.045 (1.14)
0.020 (0.508)
0.015 (0.381)
0.120 (3.05)
SEATING
PLANE
0.095 (2.41)
Once it is established that the conversion is finished, the data
can be read. In the case of an ADC of 8-bit resolution (or less),
a single data read operation is sufficient. In the case of convert-
ers with more data bits than are available on the bus, a choice of
data formats is required, and multiple read operations are
needed. T he AD1674 includes internal logic to permit direct in-
terface to 8-bit or 16-bit data buses, selected by the 12/8 input.
In 16-bit bus applications (12/8 HIGH) the data lines (DB11
through DB0) may be connected to either the 12 most signifi-
cant or 12 least significant hits of the data bus. T he remaining
four bits should be masked in software. T he interface to an 8-bit
data bus (12/8 LOW) contains the 8 MSBs (DB11 through
DB4). T he odd address (A0 HIGH) contains the 4 LSBs (DB3
through DB0) in the upper half of the byte, followed by four
trailing zeroes, thus eliminating bit masking instructions.
28-Lead Wide-Body SO P ackage (R-28)
28
15
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
PIN 1
0.3937 (10.00)
14
1
0.1043 (2.65)
0.7125 (18.10)
0.0926 (2.35)
0.6969 (17.70)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500 (1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
AD1674 Data Form at for 8-Bit Bus
–12–
REV. C
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