5962-9581501HXX [ADI]
IC DUAL 3-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68, CERAMIC, LCC-68, Analog to Digital Converter;
| 型号： | 5962-9581501HXX |
| 厂家： | 
ADI |
| 描述： | IC DUAL 3-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68, CERAMIC, LCC-68, Analog to Digital Converter 转换器 模数转换器 |
| 文件： | 总16页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, 12-Bit, 40 MSPS MCM A/D Converter
with Analog Input Signal Conditioning
a
AD10242
FEATURES
T he AD10242 operates with ±5.0 V for the analog signal condi-
Tw o Matched ADCs w ith Input Signal Conditioning
Selectable Bipolar Input Voltage Range
(؎0.5 V, ؎1.0 V, ؎2.0 V)
Full MIL-STD-883B Com pliant
80 dB Spurious-Free Dynam ic Range
Trim m ed Channel-Channel Matching
tioning with a separate +5.0 V supply for the analog-to-digital
conversion. Each channel is completely independent allowing
operation with independent encode or analog inputs. T he
AD10242 also offers the user a choice of analog input signal
ranges to minimize additional signal conditioning required for
multiple functions within a single system. T he heart of the
AD10242 is the AD9042 which is designed specifically for appli-
cations requiring wide dynamic range.
APPLICATIONS
Radar Processing
T he AD10242 is manufactured by Analog Devices on our
MIL-PRF-38534 MCM line and is completely qualified. Units
are packaged in a custom cofired ceramic 68-lead gull wing
package and specified for operation from –55°C to +125°C.
Contact the factory for additional custom options including
those which allow the user to ac couple the ADC directly, by-
passing the front end amplifier section. Also see the AD9042
data sheet for additional details on ADC performance.
Com m unications Receivers
FLIR Processing
Secure Com m unications
Any I/ Q Signal Processing Application
P RO D UCT D ESCRIP TIO N
T he AD10242 is a complete dual signal chain solution including
onboard amplifiers, references, ADCs, and output buffering pro-
viding unsurpassed total system performance. Each channel is
laser trimmed for gain and offset matching and provides channel-
to-channel crosstalk performance better than 80 dB. The AD10242
utilizes two each of the AD9631, OP279, and the AD9042 in a
custom MCM to gain space, performance, and cost advantages
over solutions previously available.
P RO D UCT H IGH LIGH TS
1. Guaranteed sample rate of 40 MSPS.
2. Dynamic performance specified over entire Nyquist band;
spurious signals @ 80 dBc for –1 dBFS input signals.
3. Low power dissipation: <2 W off ±5.0 V supplies.
4. User defined input amplitude.
5. Packaged in 68-lead ceramic leaded chip carrier.
FUNCTIO NAL BLO CK D IAGRAM
A
1
A
2
A
1
A
2
A
3
A
3
UNEG UCOM UPOS
IN
62
IN
7
IN
6
IN
63
IN
64
IN
8
56
55
57
12
UPOS
OP279
OP279
AD9631
AD9631
AD9042
4
3
UCOM
UNEG
OP279
OP279
AD9042
52
51
ENC
(LSB) D0A 17
D1A 18
TIMING
ENC
V
V
REF
REF
D2A 19
49
48
47
46
45
D11B (MSB)
D10B
20
21
22
23
24
25
D3A
D4A
D5A
D6A
D7A
D8A
AD10242
12
OUTPUT BUFFERING
12
9
5
D9B
OUTPUT BUFFERING
7
D8B
D7B
TIMING
32
D10A
29
ENC
28
ENC
31
37
40
42
D6B
33
36
38
39
41
D11A
(MSB)
D9A
D0B D1B
(LSB)
D2B
D3B
D4B
D5B
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD10242–SPECIFICATIONS
(AV = +5 V; AV = –5.0 V; DV = +5 V; applies to each ADC unless otherwise noted)
Electrical Characteristics
CC
EE
CC
Test
Mil
Subgroup
AD 10242BZ/TZ
Typ
P aram eter
Tem p
Level
Min
Max
Units
RESOLUT ION
12
Bits
DC ACCURACY
No Missing Codes
Offset Error
Full
+25°C
Full
Full
+25°C
Full
VI
I
VI
V
I
1, 2, 3
1
2, 3
Guaranteed
±0.05
±1.0
±0.1
±0.5
–0.5
–2.0
+0.5
+2.0
% FS
% FS
%
% FS
% FS
%
Offset Error Channel Match
Gain Error1
1
2, 3
–1.0
–1.5
+1.0
+1.5
VI
V
±0.8
±0.1
Gain Error Channel Match
Full
ANALOG INPUT (AIN
Input Voltage Range
)
AIN
IN2
AIN
Input Resistance
1
Full
Full
Full
I
I
I
±0.5
±1.0
±2
V
V
V
A
3
AIN
AIN
AIN
1
2
3
Full
Full
Full
+25°C
Full
IV
IV
IV
IV
V
12
12
12
12
99
100
200
400
4.0
60
101
202
404
7.0
Ω
Ω
Ω
pF
MHz
198
396
0
Input Capacitance2
Analog Input Bandwidth3
ENCODE INPUT 4, 5
Logic Compatibility
T T L/CMOS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V)
Logic “0” Current (VINL = 0 V)
Input Capacitance
Full
Full
Full
Full
I
I
I
I
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
12
2.0
0
5.0
0.8
800
V
V
µA
µA
pF
625
–300
–400
+25°C
V
7.0
SWIT CHING PERFORMANCE
Maximum Conversion Rate6
Minimum Conversion Rate6
Aperture Delay (tA)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
ENCODE Pulse Width High
ENCODE Pulse Width Low
Full
Full
VI
V
V
V
V
IV
IV
IV
4, 5, 6
12
40
50
MSPS
MSPS
ns
ns
ps rms
ns
5
+25°C
+25°C
+25°C
+25°C
+25°C
Full
1.0
±2.0
1
10
10
12
12
12
12
10
41
14
ns
ns
Output Delay (tOD
)
12
SNR7
Analog Input @ 1.2 MHz
@ 4.85 MHz
+25°C
+25°C
Full
+25°C
Full
V
I
II
I
II
I
II
68
66
66
65
65
63
62
dB
dB
dB
dB
dB
dB
dB
4
5, 6
4
5, 6
4
5, 6
63
62
63
62
60
59
@ 9.9 MHz
@ 19.5 MHz
+25°C
Full
SINAD8
Analog Input @ 1.2 MHz
@ 4.85 MHz
+25°C
+25°C
Full
+25°C
Full
V
I
II
I
II
I
II
67
65
64
64
63
61
60
dB
dB
dB
dB
dB
dB
dB
4
5, 6
4
5, 6
4
5, 6
62
61
60
60
58
58
@ 9.9 MHz
@ 19.5 MHz
+25°C
Full
–2–
REV. A
AD10242
Test
Level
Mil
Subgroup
AD 10242BZ/TZ
Typ
P aram eter
Tem p
Min
Max
Units
SPURIOUS-FREE DYNAMIC RANGE9
Analog Input @ 1.2 MHz
@ 4.85 MHz
+25°C
+25°C
Full
+25°C
Full
I
I
II
I
II
I
81
80
79
70
69
67
66
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
4
5, 6
4
5, 6
4
5, 6
70
70
63
63
60
60
@ 9.9 MHz
@ 19.5 MHz
+25°C
Full
II
T WO-T ONE IMD REJECT ION 10
F1, F2 @ –7 dBFS
Full
II
4, 5, 6
12
70
75
76
80
10
dBc
dB
ns
CHANNEL-TO-CHANNEL ISOLAT ION11
T RANSIENT RESPONSE
+25°C
+25°C
IV
V
LINEARIT Y
Differential Nonlinearity
(Encode = 20 MHz)
Integral Nonlinearity
+25°C
Full
+25°C
Full
IV
IV
V
12
12
0.3
0.5
0.3
0.5
1.0
1.25
LSB
LSB
LSB
LSB
(
Encode = 20 MHz)
V
OVERVOLT AGE RECOVERY T IME12
VIN = 2.0 × FS
VIN = 4.0 × FS
Full
Full
IV
IV
12
12
50
75
100
200
ns
ns
DIGIT AL OUT PUT S
Logic Compatibility
Logic “1” Voltage13
Logic “0” Voltage14
Output Coding
CMOS
4.2
0.45
Full
Full
I
I
1, 2, 3
1, 2, 3
3.5
V
V
0.65
T wos Complement
POWER SUPPLY
AVCC Supply Voltage
I (AVCC) Current
AVEE Supply Voltage
I (AVEE) Current
DVCC Supply Voltage
I (DVCC) Current
ICC (T otal) Supply Current
Power Dissipation (T otal)
Power Supply Rejection Ratio (PSRR)
Pass Band Ripple to 10 MHz
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
V
VI
V
VI
V
I
I
I
IV
+5.0
260
–5.0
55
+5.0
25
350
1.75
0.01
V
mA
V
mA
V
mA
mA
W
1, 2, 3
1, 2, 3
7, 8
400
2.0
0.02
0.2
% FSR/% VS
dB
12
NOT ES
1 Gain tests are performed on AIN3 over specified input voltage range.
2 Input capacitance specifications combines AD9631 die capacitance + ceramic package capacitance.
3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4 ENCODE (Pin 4) driven by single-ended source; ENCODE (Pin 5) bypassed to ground through 0.01 µF capacitor.
5 ENCODE (Pin 4) may also be driven differentially in conjunction with ENCODE (Pin 5); see “Encoding the AD10242” for details.
6 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
7 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 40.0 MSPS.
8 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS.
9 Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10 Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 10.0 MHz
± 100 kHz, 50 kHz ≤ f1 – f2 ≤ 300 kHz.
11 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (AIN1).
12 Input driven to 2× and 4× AIN1 range for >4 clock cycles. Output recovers inband in specified time with Encode = 40 MSPS. No foldover guaranteed.
13 Outputs are sourcing 10 µA.
14 Outputs are sinking 10 µA.
All specifications guaranteed within 100 ms of initial power up regardless of sequencing.
Specifications subject to change without notice.
REV. A
–3–
AD10242
ABSO LUTE MAXIMUM RATINGS1
Table I. O utput Coding
Base 10
P aram eter
Min
Max Units
MSB
LSB
Input
ELECT RICAL
VCC Voltage
VEE Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage (ENCODE)
ENCODE, ENCODE Differential Voltage
Digital Output Current
0111111111111
0000000000001
0000000000000
1111111111111
1000000000000
2047
+1
0
–1
2048
+FS
0
7
0
VCC
+10
VCC
4
V
V
V
mA
V
–7
VEE
–10
0
0.0 V
–FS
V
mA
–40
–55
+40
EXP LANATIO N O F TEST LEVELS
Test Level
ENVIRONMENT AL2
I
–
100% Production T ested.
Operating T emperature (Case)
Maximum Junction T emperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
+125 °C
+175 °C
+300 °C
+150 °C
II
–
100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
–65
III – Sample T ested Only.
NOT ES
IV – Parameter is guaranteed by design and characterization
testing.
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
V
– Parameter is a typical value only.
T ypical thermal impedances for “Z” package: θJC = 11oC/W; θJA = 30oC/W.
2
VI – All devices are 100% production tested at +25°C; sample
tested at temperature extremes.
O RD ERING GUID E
M
odel
Tem perature Range
P ackage D escription
P ackage O ption
AD10242BZ
AD10242T Z
AD10242T Z/883B
5962-9581501HXA –55°C to +125°C (Case) 68-Pin Ceramic
AD10242/PCB
–40°C to +85°C (Case)
68-Pin Ceramic Leaded Chip Carrier Z-68A
–55°C to +125°C (Case) 68-Pin Ceramic
Carrier Z-68A
Leaded Chip
–55°C to +125°C (Case) 68-Pin Ceramic Leaded Chip Carrier Z-68A
Carrier Z-68A
Leaded Chip
Evaluation Board with AD10242BZ
+25°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD10242 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–4–
AD10242
P IN FUNCTIO N D ESCRIP TIO NS
P in No.
Nam e
Function
Internal Ground Shield between channels.
A Channel Ground. A and B grounds should be connected as close to the device as possible.
Unipolar Negative.
1
SHIELD
GNDA
UNEGA
UCOMA
2, 5, 9–11, 26–27
3
4
Unipolar Common.
6
7
8
12
13
14
15–16
A
A
A
INA1
INA2
INA3
Analog Input for A side ADC (nominally ±0.5 V).
Analog Input for A side ADC (nominally ±1.0 V).
Analog Input for A side ADC (nominally ±2.0 V).
Unipolar Positive.
Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V).
Analog Positive Supply Voltage (nominally +5.0 V).
No Connect.
UPOSA
AVEE
AVCC
NC
17–25, 31–33
28
29
30
D0A–D11A
ENCODEA
ENCODEA
DVCC
Digital Outputs for ADC A. D0 (LSB).
ENCODE is complement of ENCODE.
Data conversion initiated on rising edge of ENCODE input.
Digital positive supply voltage (nominally +5.0 V).
No Connect.
34–35
NC
36–42, 45–49
43–44, 53–54
58–61, 65, 68
D0B–D11B
GNDB
Digital Outputs for ADC B. D0 (LSB).
B Channel Ground. A and B grounds should be connected as close to the device
as possible.
50
51
52
55
56
57
62
63
64
66
67
DVCC
Digital Positive Supply Voltage (nominally +5.0 V).
Data conversion initiated on rising edge of ENCODE input.
ENCODE is complement of ENCODE.
Unipolar Common.
Unipolar Negative.
Unipolar Positive.
Analog Input for B side ADC (nominally ±0.5 V).
Analog Input for B side ADC (nominally ±1.0 V).
Analog Input for B side ADC (nominally ±2.0 V).
Analog Positive Supply Voltage (nominally +5.0 V).
Analog Negative Supply Voltage (nominally –5.0 V or –5.2 V).
ENCODEB
ENCODEB
UCOMB
UNEGB
UPOSB
A
A
A
INB1
INB2
INB3
AVCC
AVEE
P IN CO NFIGURATIO N
68-Lead Ceram ic Leaded Chip Carrier
4
9
8
7
6
5
3
2
1 68 67 66 65 64 63 62 61
10
11
12
13
14
GNDA
GNDA
60
59
GNDB
GNDB
PIN 1
UPOSA
58
57
56
55
54
53
52
51
50
49
48
GNDB
AV
EE
UPOSB
UNEGB
AV
CC
15
16
17
18
19
20
NC
NC
UCOMB
GNDB
AD10242
(LSB) D0A
D1A
GNDB
TOP VIEW
(Not to Scale)
ENCODEB
D2A
ENCODEB
D3A
DV
CC
21
22
23
24
25
26
D4A
D11B (MSB)
D10B
D5A
D6A
47
46
45
44
D9B
D7A
D8B
D8A
D7B
GNDA
GNDB
28 29 30 31
42
43
27
32 33 34 35 36 37 38 39 40 41
NC = NO CONNECT
REV. A
–5–
AD10242
O ver voltage Recover y Tim e
D EFINITIO N O F SP ECIFICATIO NS
Analog Bandwidth
T he analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
T he amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified per-
centage of full scale is reduced to midscale.
P ower Supply Rejection Ratio
T he ratio of a change in input offset voltage to a change in
power supply voltage.
Aper tur e D elay
T he delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Signal-to-Noise-and-D istor tion (SINAD )
T he ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Aper tur e Uncer tainty (Jitter )
T he sample-to-sample variation in aperture delay.
Signal-to-Noise Ratio (without H ar m onics)
D iffer ential Nonlinear ity
T he ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
T he deviation of any code from an ideal 1 LSB step.
Encode P ulse Width/D uty Cycle
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Spur ious-Fr ee D ynam ic Range
T he ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. T he peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered) or in dBFS (always re-
lated back to converter full scale).
H ar m onic D istor tion
T he ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Tr ansient Response
T he time required for the converter to achieve 0.02% accuracy
when a one-half full-scale step function is applied to the analog
input.
Integr al Nonlinear ity
T he deviation of the transfer function from a reference line mea-
sured in fractions of 1 LSB using a “best straight line” deter-
mined by a least square curve fit.
Two-Tone Inter m odulation D istor tion Rejection
T he ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in
dBc.
Minim um Conver sion Rate
T he encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Two-Tone SFD R
T he ratio of the rms value of either input tone to the rms value
of the peak spurious component. T he peak spurious compo-
nent may or may not be an IMD product. May be reported
in dBc (i.e., degrades as signal levels is lowered) or in dBFS
(always related back to converter full scale).
Maxim um Conver sion Rate
T he encode rate at which parametric testing is performed.
O utput P r opagation D elay
The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.
REV. A
–6–
AD10242
N + 4
N + 5
N
N + 1
N + 2
N + 3
ENC
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TTL CLOCK
10MHz
f
≈
ENC
A
IN
1/2
AD10242
SHOWN
3
2
A
A
IN
tA = 1.0ns TYP
tOD = 12ns TYP
IN
ENCODE
1
A
IN
DIGITAL
OUTPUTS
N – 2
N – 1
N
N + 1
N + 2
NOTE: ALL ±5V SUPPLY PINS BYPASSED
TO GND WITH A 0.1µF CAPACITOR
Figure 2. Equivalent Burn-In Circuit
Figure 1. Tim ing Diagram
DV
CC
EQ UIVALENT CIRCUITS
A
3
CURRENT
MIRROR
IN
IN
R4
200Ω
A
2
R3
100Ω
A
1
IN
R2
21Ω
DV
CC
TO AD9631
R1
79Ω
V
REF
D0 – D11
Figure 3. Analog Input Stage
AV
CC
AV
AV
CC
CC
R1
17k⍀
R1
17k⍀
CURRENT
MIRROR
ENCODE
ENCODE
TIMING
CIRCUITS
R2
8k⍀
R2
8k⍀
Figure 5. Digital Output Stage
Figure 4. Encode Inputs
REV. A
–7–
AD10242–Typical Performance Characteristics
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ENCODE = 40.0 MSPS
ENCODE = 40.0 MSPS
A
A
A
A
1 = 9.8 MHz
1 = –7 dBFs
2 = 10.1 MHz
2 = –7 dBFs
IN
IN
IN
IN
A
A
= 4.85 MHz
= –1 dBFs
IN
IN
SNR = 66.4 dB
SFDR = 72.8 dBc
SFDR = 76.0 dBc
0
2
4
6
8
10
12
14
16
18
20
0
0
0
2
4
6
8
10
12
14
16
18
20
20
20
FREQUENCY – MHz
FREQUENCY – MHz
Figure 9. Two Tone FFT @ 9.8/10.1 MHz
Figure 6. Single Tone @ 4.85 MHz
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ENCODE = 40.0 MSPS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
A
A
A
A
1 = 19.5 MHz
1 = –7 dBFs
2 = 19.7 MHz
2 = –7 dBFs
IN
IN
IN
IN
ENCODE = 40.0 MSPS
A
A
= 9.9 MHz
= –1 dBFs
IN
IN
SNR = 66.0 dB
SFDR = 65.7 dBc
SFDR = 70.6 dBc
0
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
FREQUENCY – MHz
FREQUENCY – MHz
Figure 10. Two Tone FFT @ 19.5/19.7 MHz
Figure 7. Single Tone @ 9.9 MHz
76
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
74
ENCODE = 40.0 MSPS
ENCODE = 40.0 MSPS
A
= –1 dBFs
IN
A
A
= 19.5 MHz
= –1 dBFs
72
70
68
66
64
62
60
58
IN
IN
SNR = 64.3 dB
SFDR = 63.3 dBc
T = +125؇C
T = +25؇C
T = –55؇C
10
5
20
2
4
6
8
10
12
14
16
18
ANALOG INPUT FREQUENCY – MHz
FREQUENCY – MHz
Figure 11. Harm onics vs. AIN
Figure 8. Single Tone @ 19.5 MHz
REV. A
–8–
AD10242
67
66.5
66
–90
–80
–70
–60
–50
–40
–30
–20
IN A1
IN B1
T = –55؇C
65.5
65
IN B3
T = +25؇C
IN A3
64.5
64
T = +125؇C
63.5
63
ENCODE = 40.0 MSPS
A = –1 dBFs
IN
ENCODE = 40.0 MSPS
A
= –1 dBFs
IN
62.5
62
–10
0
61.5
10
5
20
20
25
30
35
40
10
15
ANALOG INPUT FREQUENCY – MHz
ANALOG INPUT FREQUENCY – MHz
Figure 12. SNR vs. AIN
Figure 15. Isolation vs. Frequency
90
80
70
60
70
68
66
64
62
60
58
A
A
= 9.9 MHz
= –1 dBFs
IN
IN
SFDR (dBFs)
SFDR
SFDR (dBc)
50
40
SNR
SFDR = 75dB
30
20
ENCODE = 40 MSPS
= 9.98 MHz
10
0
A
IN
–60
–50
–40
–30
–20
–10
0
–70
5
10
15
20
25
30
35
40
45
50
ANALOG INPUT POWER LEVEL – dBFs
SAMPLE RATE – MSPS
Figure 13. SNR and Harm onics vs. Encode Rate
Figure 16. Single Tone SFDR (AIN @ 9.98) vs. Power Level
100
90
2.0
1.5
80
SFDR (dBFs)
1.0
70
60
GAIN
0.5
0
SFDR (dBc)
50
40
OFFSET
–0.5
–1.5
SFDR = 75dB
30
20
ENCODE = 40 MSPS
–1.5
–2.0
10
0
A
= 19.9 MHz
IN
–60
–50
–40
–30
–20
–10
0
–70
5
25
45
65
85
105
125
–55 –35
–15
ANALOG INPUT POWER LEVEL – dBFs
TEMPERATURE – ؇C
Figure 14. Offset and Gain Error vs. Tem perature
Figure 17. Single Tone SFDR (AIN @ 19.9) vs. Power Level
REV. A
–9–
AD10242–Typical Performance Characteristics
80
–0.5
0
70
SNR (dB)
ENCODE = 40 MSPS
60
0.5
1
50
40
30
20
10
0
SFDR (dBFS)
1.5
2
ENCODE = 40 MSPS
2.5
3
A
= 1dBFs
IN
5
10
20
29.2
34.5
52.5
60.95
0
5
10
15
20
25
30
35
40
45
50
55
ANALOG INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 18. SNR/Harm onics to AIN > Nyquist MSPS
Figure 19. Gain Flatness vs. Input Frequency
TH EO RY O F O P ERATIO N
AP P LYING TH E AD 10242
Encoding the AD 10242
T he AD10242 is designed to interface with T T L and CMOS
logic families. T he source used to drive the ENCODE pin(s)
must be clean and free from jitter. Sources with excessive jitter
will limit SNR and overall performance.
Refer to the block diagram. T he AD10242 employs three
monolithic ADI components per channel (AD9631, OP279, and
AD9042), along with multiple passive resistor networks and de-
coupling capacitors to fully integrate a complete 12-bit analog-
to-digital converter.
T he input signal is first passed through a precision laser
trimmed resistor divider allowing the user to externally select
operation with a full scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by
choosing the proper input terminal for the application. The result
of the resistor divider is to apply a full-scale input of approxi-
mately 0.4 V to the noninverting input of the internal AD9631
amplifier.
AD10242
TTL OR CMOS
ENCODE
SOURCE
ENCODE
0.01µF
Figure 20. Single-Ended TTL/CMOS Encode
T he AD9631 provides the dc coupled level shift circuit required
for operation with the AD9042 ADC. Configuring the amplifier
in a noninverting mode the ac signal gain can be trimmed to
provide a constant input to the ADC centered around the inter-
nal reference voltage of the AD9042. T his allows the converter
to be used in multiple system applications without the need for
external gain and level shift circuitry normally requiring trim.
T he AD9631 was chosen for its superior ac performance and in-
put drive capabilities which have limited the ability of many am-
plifiers to drive high performance ADCs. As new amplifiers are
developed, pin compatible improvements are planned to incor-
porate the latest operational amplifier technology.
T he AD10242 encode inputs are connected to a differential in-
put stage (see Figure 4 under EQUIVALENT CIRCUIT S).
With no input connected to either the ENCODE or input, the
voltage divider bias the inputs to 1.6 volts. For T T L or CMOS
usage, the encode source should be connected to ENCODE
(Pins 29 and/or 51). ENCODE (Pins 28 and/or 52) should be
decoupled using a low inductance or microwave chip capacitor
to ground. Devices such as AVX 05085C103MA15, a
0.01 µF capacitor, work well.
P er for m ance Im pr ovem ents
It is possible to improve the performance of the AD10242
slightly by taking advantage of the internal characteristics of the
amplifier and converter combination. By increasing the +5 V
supply slightly, the user may be able to gain up to a 5 dB improve-
ment in SFDR over the entire frequency range of the converter.
It is not recommended to exceed +5.5 V on the analog supplies
as there are no performance benefits beyond that range and care
should be taken to avoid the absolute maximum ratings.
T he OP279 provides the buffer and inversion of the internal ref-
erence of the AD9042 in order to supply the summing node of
the AD9631 input amplifier. T his dc voltage is then summed
with the input voltage and applied to the input of the AD9042
ADC. T he reference voltage of the AD9042 is designed to track
internal offsets and drifts of the ADC and is used to ensure
matching over an extended temperature range of operation.
REV. A
–10–
AD10242
If a logic threshold other than the nominal 1.6 V is required,
the following equations show how to use an external resistor,
RX, to raise or lower the trip point (see Figure 4, R1 = 17 kΩ,
R2 = 8 kΩ).
If no T T L source is available, a clean sine wave may be substi-
tuted. In the case of the sine source, the matching network is
shown below. Since the matching transformer specified is a 1:1
impedance ratio, R, the load resistor should be selected to
match the source impedance. T he input impedance of the
AD9042 is negligible in most cases.
5R2RX
V1
=
to lower logic threshold.
R1R2 + R1RX + R2RX
T1-1T
SINE
SOURCE
ENCODE
+5V
ENCODE
SOURCE
ENCODE
R
AD10242
R1
V
l
ENCODE
ENCODE
0.01µF
R2
R
X
AD10242
Figure 24. Sine Source—Differential Encode
If a low jitter ECL clock is available, another option is to ac-
couple a differential ECL signal to the encode input pins as
shown below. T he capacitors shown here should be chip capaci-
tors but do not need to be of the low inductance variety.
Figure 21. Lower Threshold for Encode
5R2
V1
=
R1RX
to raise logic threshold.
R2 +
R1 + RX
AV
CC
0.1µF
R
X
ENCODE
+5V
R1
ECL
GATE
ENCODE
SOURCE
AD10242
0.1µF
ENCODE
ENCODE
ENCODE
V
l
510Ω
510Ω
R2
0.01µF
AD10242
–V
S
Figure 25. Differential ECL for Encode
Figure 22. Raise Logic Threshold for Encode
As a final alternative, the ECL gate may be replaced by an ECL
comparator. T he input to the comparator could then be a logic
signal or a sine signal.
While the single ended encode will work well for many applica-
tions, driving the encode differentially will provide increased
performance. Depending on circuit layout and system noise, a
1 dB to 3 dB improvement in SNR can be realized. It is recom-
mended that the encode signal be ac-coupled into the ENCODE
and ENCODE pins.
AD96687 (1/2)
0.1µF
ENCODE
AD10242
0.1µF
50Ω
ENCODE
T he simplest option is shown below. T he low jitter T T L signal
is coupled with a limiting resistor, typically 100 Ω, to the pri-
mary side of an RF transformer (these transformers are inexpen-
sive and readily available; Part No. in figure is from Mini-
Circuits). T he secondary side is connected to the ENCODE
and ENCODE pins of the converter. Since both encode inputs
are self-biased, no additional components are required.
510Ω
510Ω
–V
S
Figure 26. ECL Com parator for Encode
Care should be taken not to overdrive the encode input pin
when ac coupled. Although the input circuitry is electrically pro-
tected from over or under voltage conditions, improper circuit
operations may result from overdriving the encode input pin.
100Ω
T1-1T
ENCODE
TTL
AD10242
ENCODE
Figure 23. TTL Source—Differential Encode
REV. A
–11–
AD10242
USING TH E FLEXIBLE INP UT
A
A
A
1
2
3
IN
IN
IN
T he AD10242 has been designed with the user’s ease of opera-
tion in mind. Multiple input configurations have been included
on board to allow the user to have a choice of input signal levels
and input impedance. While the standard inputs are ±0.5 V,
±1.0 V, and ±2.0 V, the user can select the input impedance of
the AD10242 on any input by using the other inputs as alternate
locations for GND or an external resistor. T he following
chart summarizes the impedance options available at each
input location:
AD10242
UNEG
2.67kΩ
UCOM
Figure 28. Unipolar Negative
GRO UND ING AND D ECO UP LING
Analog and D igital Gr ounding
A
A
A
IN1 = 100 Ω when AIN2 and AIN3 Are Open.
IN1 = 75 Ω when AIN3 Is Shorted to GND.
IN1 = 50 Ω when AIN2 Is Shorted to GND.
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. T he
use of ground and power planes offers distinct advantages:
AIN2 = 200 Ω when AIN3 Is Open.
A
A
A
A
A
IN2 = 100 Ω when AIN3 Is Shorted to GND.
IN2 = 75 Ω when AIN2 to AIN3 Has an External Resistor of
IN2 = 300 Ω, with AIN 3 Shorted to GND.
IN2 = 50 Ω when AIN2 to AIN3 Has an External Resistor of
IN2 = 100 Ω, with AIN3 Shorted to GND.
1. T he minimization of the loop area encompassed by a signal
and its return path.
2. T he minimization of the impedance associated with ground
and power paths.
3. T he inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
AIN3 = 400 Ω.
AIN3 = 100 Ω when AIN3 Has an External Resistor of 133 Ω to GND.
AIN3 = 75 Ω when AIN3 Has an External Resistor of 92 Ω to GND.
AIN3 = 50 Ω when AIN3 Has an External Resistor of 57 Ω to GND.
T hese characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
While the Analog inputs of the AD10242 are designed for dc
coupled bipolar inputs, the AD10242 has the ability to use uni-
polar inputs in a user selectable mode through the addition of a
external resistor. T his allows for 1 V, 2 V, and 4 V full-scale
unipolar signals to be applied to the various inputs (AIN1, AIN2,
and AIN3 respectively). Placing a 2.43 kΩ resistor (typical, off-
set calibration required) between UPOS and UCOM shifts the
reference voltage setpoint to allow a unipolar positive voltage
to be applied at the inputs of the device. T o calibrate offset a
midscale dc voltage should be applied to the converter while
adjusting the unipolar resistor for a midscale output transition.
It is important to design a layout that prevents noise from cou-
pling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. T he AD10242 does not distinguish between
analog and digital ground pins as the AD10242 should always
be treated like an analog component. All ground pins should be
connected together directly under the AD10242. T he PCB
should have a ground plane covering all unused portions of the
component side of the board to provide a low impedance path
and manage the power and ground currents. T he ground plane
should be removed from the area near the input pins to reduce
stray capacitance.
A
A
A
1
2
3
IN
IN
IN
LAYO UT INFO RMATIO N
T he schematic of the evaluation board (Figure 29) represents a
typical implementation of the AD10242. T he pinout of the
AD10242 is very straightforward and facilitates ease of use
and the implementation of high frequency/high resolution
design practices. It is recommended that high quality ceramic
chip capacitors be used to decouple each supply pin to
ground directly at the device. All capacitors except the one
placed on ENCODE can be standard high quality ceramic chip
capacitors. T he capacitor used on ENCODE pin must be a low
inductance chip capacitor as referenced previously in the data
sheet.
AD10242
UPOS
2.43kΩ
UCOM
Figure 27. Unipolar Positive
T o operate with –1 V, –2 V, or –4 V full-scale unipolar signals
place a 2.67 kΩ resistor (typical, offset calibration required)
between UNEG and UCOM. T his again shifts the reference
voltage setpoint to allow a unipolar negative voltage to be
applied at the inputs of the device. T o calibrate offset a mid-
scale dc voltage should be applied to the converter while adjust-
ing the unipolar resistor for a midscale output transition.
REV. A
–12–
AD10242
+5VA
C2
0.1µF
SMA SMA
J8 JB
SMA
JD
+5VA
C1
0.1µF
SMA SMA
J1 JA
SMA
JC
14
VCC
14
VCC
H2DM
J16
H2DM
J15
8
8
OUT
VEE
7
OUT
VEE
7
U2
K1115
U1
K1115
1
2
1
2
U5
AD9696KN
8
2
U5
AD9696KN
8
2
+5VA
R11
+5VA
51⍀
51⍀
H2DM
J18
H2DM
J17
R9
470⍀
E5
E5
470⍀
3
3
1
2
1
2
BUFLATB
BUFLATA
7
5
7
5
R12
470⍀
C5
0.1µF
R10
470⍀
C14
0.1µF
T2
T1 – 1T
T1
T1 – 1T
4
4
3
3
GND
GND
ENCBB
2
ENCAB
ENCA
2
R2
100⍀
R1
100⍀
B SECTION
A SECTION
1
6
1
6
ENCB
1 : 1
1 : 1
PULSE A
IN
PULSE A
OUT
PULSE B
IN
PULSE B
OUT
H40DM
U3
AD8036Q
U4
AD8036Q
B JACKS
E4
J9
VHIGH
8
VHIGH
SMA
J11
SMA
J13
SMA
J12
SMA
J14
E1
E3
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
3
3
8
+5VD
(MSB) D11A
D10A
D9A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
6
6
+5VA
GND
+5VA
GND
2
2
3
R7
49.9⍀
R8
49.9⍀
5
5
4
E2
VLOW
VHIGH
VLOW
VHIGH
5
VLOW
VLOW
–5.2V
–5.2V
D8A
6
D7A
7
R5
470⍀
R6
470⍀
R3
470⍀
R4
470⍀
D6A
8
D5A
9
D4A
10
11
12
13
14
15
16
17
18
19
20
VHIGH
+5V
BUFLATA
U4
C22
0.1µF
U3
C21
0.1µF
U4
C17
0.1µF
U3
C18
0.1µF
DUT
C8
0.1µF
DUT
C9
0.1µF
U5
C12
0.1µF
U6
C3
0.1µF
C23
D3A
D2A
10µF
D1A
–5.2V
VLOW
(LSB) D0A
GND
U3
C15
0.1µF
U4
C16
0.1µF
DUT
C10
0.1µF
U5
C13
0.1µF
DUT
C11
0.1µF
U6
C4
0.1µF
U3
C19
0.1µF
U4
C20
0.1µF
C24
10µF
GND
GND
+5VD
GND
DUT
C7
0.1µF
DUT
C6
0.1µF
C25
10µF
GND
SMA
J2
SMA
J3
SMA
J4
SMA
J5
SMA
J6
SMA
J7
AINA1
AINA2
AINA3
AINB1
AINB2
AINB3
H40DM
J10
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
+5VD
(MSB) D11B
D10B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
3
4
D9B
5
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
D8B
6
NOTES;
D7B
7
1) UNIPOLAR OPERATION
D6B
8
A SIDE + CONNECT 2.43kΩ RES. FROM TP1 TO TP5.
A SIDE – CONNECT 2.67kΩ RES. FROM TP5 TO TP6.
B SIDE + CONNECT 2.43kΩ RES. FROM TP2 TO TP4.
B SIDE – CONNECT 2.67kΩ RES. FROM TP4 TO TP3.
D5B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
GND
GNDA
GNDA
GNDB
GNDB
GNDB
GND
D4B
10
11
12
59
GND
TP1
GND
BUFLATB
58
UNIPOSA
–5.2VAA
+5VAA
NCA
GND
57
–5.2V
+5VA
GND
GND
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
GND
UNIPOSB
UNINEGB
UNICOMB
GNDB
TP2
2) ABOVE UNIPOLAR RESISTOR VALUES ARE
NOMINAL & MAY HAVE TO BE ADJUSTED
DEPENDING ON OFFSET OF DUT.
D3B
D2B
56
13
14
15
16
17
18
19
20
TP3
55
TP4
D1B
54
NCA
GND
(LSB) D0B
GND
3) ENCODE SOURCES
53
D0A (LSBA)
D1A
GNDB
GND
DUT
AD10242
A)FOR NORMAL OPERATION, A 40MHz TTL CLOCK
OSCILLATOR IS INSTALLED IN U1 & U2. THERE
IS A 51Ω RESISTOR BETWEEN J15 & J16.
J17 & J18 ARE OPEN.
B)FOR EXTERNAL SQUAREWARE ENCODE, INPUT
SIGNAL AT J1 & J8, REMOVE U1, U2, JUMPERS
J15 & J16. CONNECT JUMPERS J17 & J18.
C)FOR EXTERNAL SINEWAVE ENCODE, INPUT
SIGNAL AT J1 & J8, REMOVE U1, U2, R9, R11,
JUMPERS J15 & J16.
52
ENCBB
ENCB
ENCBB
GND
51
50
49
48
47
46
45
44
D2A
ENCB
GND
+5VDB
(MSBB) D11B
D10B
+5VD
D11B
D10B
D9B
D3A
GND
D4A
GND
D5A
D6A
D9B
D7A
D8B
D8B
D8A
D7B
D7B
TEST POINTS
TP1 TP6
TP2 TP7
TP3 TP8
TP4 TP9
TP5 TP10
GNDA
GNDB
GND
CONNECT JUMPERS J17 & J18.
TP1
TP2
TP3
TP4
TP5
TP6
ENCAB
ENCA
4) POWER (+5VD) FOR DIGITAL OUTPUTS OF THE
AD10242 IS SUPPLIED VIA PIN 1 OF EITHER J9 OR J10
(THE DIGITAL INTERFACES). TO POWER THE EVAL.
BOARD WITH ONE +5V SUPPLY, JUMPER A WIRE
FROM E1 TO E4 (CONNECTED AT FACTORY).
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
ENCBB
ENCB
Figure 29. Evaluation Board Schem atic
–13–
REV. A
AD10242
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the AD9042 ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
analog-to-digital converter. T he board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10242.
Power to the analog supply pins is connected via banana jacks.
T he analog supply powers the crystal oscillator, the associated
components and amplifiers, and the analog section of the
AD10242. T he Digital outputs of the AD10242 are powered
via Pin 1 of either J9 or J10 found on the digital interface con-
nector. T o power the evaluation board with one +5 V supply a
jumper wire is required from test point E1 to E4. Contact the
factory if additional layout or applications assistance is required.
EVALUATIO N BO ARD
T he AD10242 evaluation board (see Figure 30) is designed to
provide optimal performance for evaluation of the AD10242
Figure 30. Evaluation Board Mechanical Layout
REV. A
–14–
AD10242
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
68-Lead Ceram ic Leaded Chip Carrier
(Z-68A)
1.180 (29.97) SQ
0.950 (24.13) SQ
0.060 (1.52)
9
61
10
60
PIN 1
0.800
(20.32)
TOP VIEW
(PINS DOWN)
26
44
27
43
0.050 (1.27)
0.018 (0.457)
0.240 (6.096)
REV. A
–15–
–16–
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