5962-9684601QJA_技术文档

LC²MOS Single Supply,

12-Bit 600 kSPS ADC

a

AD7892

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Fast 12-Bit ADC with 1.47 ␮s Conversion Time

600 kSPS Throughput Rate (AD7892-3)

500 kSPS Throughput Rate (AD7892-1, AD7892-2)

Single Supply Operation

On-Chip Track/Hold Amplifier

Selection of Input Ranges:

REF OUT/REF IN

V

DD

2k⍀

+2.5V

MODE

AD7892

REFERENCE

DB0

؎10 V or ؎5 V for AD7892-1

0 V to +2.5 V for AD7892-2

؎2.5 V for AD7892-3

High Speed Serial and Parallel Interface

Low Power, 60 mW typ

DB2

DB3/RFS

12-BIT

ADC

DB4/SCLK

DB5/SDATA

DB10/LOW

DB11/LOW

V

IN1

SIGNAL

SCALING

IN2

Overvoltage Protection on Analog Inputs (AD7892-1

and AD7892-3)

TRACK/HOLD

CLOCK

CONTROL LOGIC

CS

RD EOC CONVST AGND DGND STANDBY

The AD7892 is fabricated in Analog Devices’ Linear Compat-

ible CMOS (LC²MOS) process, a mixed technology process

that combines precision bipolar circuits with low power CMOS

logic. It is available in a 24-lead, 0.3" wide, plastic or hermetic

DIP or in a 24-lead SOIC.

GENERAL DESCRIPTION

The AD7892 is a high speed, low power, 12-bit A/D converter

that operates from a single +5 V supply. The part contains a

1.47 µs successive approximation ADC, an on-chip track/hold

amplifier, an internal +2.5 V reference and on-chip versatile

interface structures that allow both serial and parallel connec-

tion to a microprocessor. The part accepts an analog input range

of 10 V or 5 V (AD7892-1), 0 V to +2.5 V (AD7892-2) and

2.5 V (AD7892-3). Overvoltage protection on the analog inputs

for the AD7892-1 and AD7892-3 allows the input voltage to go

to 17 V or 7 V respectively without damaging the ports.

PRODUCT HIGHLIGHTS

1. The AD7892-3 features a conversion time of 1.47 µs and a

track/hold acquisition time of 200 ns. This allows a through-

put rate for the part up to 600 kSPS. The AD7892-1 and

AD7892-2 operate with throughput rates of 500 kSPS.

2. The AD7892 operates from a single +5 V supply and con-

sumes 60 mW typ making it ideal for low power and portable

applications.

The AD7892 offers a choice of two data output formats: a

single, parallel, 12-bit word or serial data. Fast bus access times

and standard control inputs ensure easy parallel interface to

microprocessors and digital signal processors. A high speed

serial interface allows direct connection to the serial ports of

microcontrollers and digital signal processors.

3. The part offers a high speed, flexible interface arrangement

with parallel and serial interfaces for easy connection to

microprocessors, microcontrollers and digital signal

processors.

In addition to the traditional dc accuracy specifications such as

linearity, full-scale and offset errors, the part is also specified for

dynamic performance parameters including harmonic distortion

and signal-to-noise ratio.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(V_DD= +5 V ؎ 5%, AGND = DGND = 0 V, REF IN = +2.5 V. All specifications T_MINto T_MAX

AD7892–SPECIFICATIONS ^{unless otherwise noted.)}

Parameter

A Versions¹B Versions S Version²

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

AD7892-1, AD7892-2

f_IN= 100 kHz. f_SAMPLE= 500 kSPS

typ –84 dB

Signal to (Noise + Distortion) Ratio³

Total Harmonic Distortion³

Peak Harmonic or Spurious Noise³

Intermodulation Distortion³

2nd Order Terms

70

–78

–79

70

–78

–79

70

–78

–79

dB min

dB max

fa = 49 kHz, fb = 50 kHz

typ –84 dB

–78

dB max

3rd Order Terms

AD7892-3

f_IN= 100 kHz. f_SAMPLE= 600 kSPS

Signal to (Noise + Distortion) Ratio³

Total Harmonic Distortion³

Peak Harmonic or Spurious Noise³

Intermodulation Distortion³

2nd Order Terms

70

–78

–79

70

–78

–79

dB min

dB max

fa = 49 kHz, fb = 50 kHz

–78

dB max

3rd Order Terms

DC ACCURACY

Resolution

12

1.5

1

12

Bits

Minimum Resolution for Which No

Missing Codes Are Guaranteed

Relative Accuracy³

12

1

12

1

Bits

LSB max

Differential Nonlinearity³

AD7892-1

Positive Full-Scale Error³

Negative Full-Scale Error³

Bipolar Zero Error³

AD7892-3

4

3

4

2

5

3

LSB max

Positive Full-Scale Error³

Negative Full-Scale Error³

Bipolar Zero Error³

AD7892-2

4

3

LSB max

Positive Full-Scale Error³

Unipolar Offset Error³

5

4

5

3

5

4

LSB max

ANALOG INPUT

AD7892-1

Input Voltage Range

Input Resistance

10

5

10

5

10

5

Volts

kΩ min

Input Applied to V_IN1with V_IN2Grounded

Input Applied to V_IN1and V_IN2

Input Applied to V_IN1with V_IN2Grounded

8

AD7892-2

Input Voltage Range on V_IN1

Input Current

Input Voltage Range on V_IN2

AD7892-3

Input Voltage Range on V_IN1

Input Resistance

0 to +2.5

10

50

0 to +2.5

10

50

0 to +2.5

50

Volts

nA max

mV max

Input Applied to V_IN1

2.5

2

2.5

2

Volts

kΩ min

REFERENCE OUTPUT/INPUT

REF IN Input Voltage Range

Input Impedance

2.375/2.625 2.375/2.625 2.375/2.625

V min/V max 2.5 V 5%

1.6

10

1.6

10

1.6

10

kΩ min

Resistor Connected to Internal Reference Node

Input Capacitance⁴

pF max

V nom

mV max

ppm/°C typ

kΩ nom

REF OUT Output Voltage

REF OUT Error @ +25°C

T_MINto T_MAX

REF OUT Temperature Coefficient

REF OUT Output Impedance

2.5

10

20

25

10

20

25

10

25

5.5

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

10

2.4

0.8

10

2.4

0.8

10

V min

V_DD= 5 V 5%

V_IN= 0 V to V_DD

V max

µA max

pF max

4

Input Capacitance, C_IN

–2–

REV. C

AD7892

Parameter

A Versions¹B Versions S Version²

Unit

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

DB11–DB0

4.0

0.4

4.0

0.4

4.0

0.4

V min

V max

I_SOURCE= 200 µA

I_SINK= 1.6 mA

Floating-State Leakage Current

Floating-State Capacitance⁴

Output Coding

10

15

10

15

10

15

µA max

pF max

AD7892-1 and AD7892-3

AD7892-2

Two’s Complement

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

1.47

0.2

1.6

1.47

0.2

1.6

µs max

AD7892-3

AD7892-1 and AD7892-2

Track/Hold Acquisition Time³

Conversion Time

1.68

0.32

Track/Hold Acquisition Time³

0.4

POWER REQUIREMENTS

V_DD

I_DD

+5

18

+5

18

+5

19

V nom

5% for Specified Performance

5

Normal Operation

mA max

Standby Mode⁶

AD7892-2

250

80

250

80

µA typ

µA max

AD7892-3, AD7892-1

Power Dissipation⁵

Normal Operation

Standby Mode⁶

100

95

typ 15 µA

90

mW max

V_DD= +5 V. Typically 60 mW

AD7892-2

AD7892-3, AD7892-1

1.25

400

1.25

400

mW typ

µW max

500

V_DD= +5 V. Typically 75 µW

NOTES

¹Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.

²S Version available on AD7892-1 and AD7892-2 only.

³See Terminology.

⁴Sample tested @ +25°C to ensure compliance.

⁵These normal mode and standby mode currents are achieved with resistors (in the range 10 kΩ to 100 kΩ) to either DGND or V_DDon Pins 8, 9, 16 and 17.

⁶A conversion should not be initiated on the part within 30 µs of exiting standby mode.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

(T_A= +25°C unless otherwise noted)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

V_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C

V

_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

Analog Input Voltage to AGND

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W

AD7892-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V

AD7892-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_DD

AD7892-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Reference Input Voltage to AGND . . . –0.3 V to V_DD+ 0.3 V

Digital Input Voltage to DGND . . . . . –0.3 V to V_DD+ 0.3 V

Digital Output Voltage to DGND . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

REV. C

–3–

AD7892

TIMING CHARACTERISTICS^{1, 2}

(V_DD= +5 V ؎ 5%, AGND = DGND = 0 V, REF IN = +2.5 V)

A, B

S

Parameter

Versions

Version

Unit

Test Conditions/Comments

t_CONV

1.47

1.6

200

400

µs max

ns min

Conversion Time for AD7892-3

Conversion Time for AD7892-1, AD7892-2

Acquisition Time for AD7892-3

Acquisition Time for AD7892-1, AD7892-2

1.68

320

t_ACQ

Parallel Interface

t₁

t₂

t₃

t₄

t₅₃

t₆₄

t₇

35

60

0

45

60

0

ns min

ns max

ns min

ns max

ns min

CONVST Pulsewidth

EOC Pulsewidth

EOC Falling Edge to CS Falling Edge Setup Time

CS to RD Setup Time

Read Pulsewidth

Data Access Time After Falling Edge of RD

Bus Relinquish Time After Rising Edge of RD

0

35

5

30

0

45

40

5

40

0

t₈

t₉

CS to RD Hold Time

RD to CONVST Setup Time

200

Serial Interface

t₁₀

t₁₁

30

25

5

25

20

0

35

30

25

5

30

0

ns min

ns max

ns min

ns max

ns min

ns max

ns min

ns max

RFS Low to SCLK Falling Edge Setup Time

RFS Low to Data Valid Delay

SCLK High Pulsewidth

3

t₁₂

t₁₃

t₁₄

t₁₅

SCLK Low Pulsewidth

3

SCLK Rising Edge to Data Valid Hold Time

SCLK Rising Edge to Data Valid Delay

RFS to SCLK Falling Edge Hold Time

Bus Relinquish Time after Rising Edge of RFS

3

t₁₆

t₁₇

4

30

0

30

0

30

4

t_17A

Bus Relinquish Time after Rising Edge of SCLK

NOTES

¹Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.

²See Figures 2 and 3.

³Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

⁴These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

⁵Assumes CMOS loads on the data bits. With TTL loads, more current is drawn from the data lines and the RD to CONVST time needs to be extended to 400 ns min.

Specifications subject to change without notice.

1.6mA

TO

+1.6V

OUTPUT

PIN 50pF

200␮A

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7892 features proprietary ESD protection circuitry, permanent damage may

WARNING!

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

ESD SENSITIVE DEVICE

–4–

REV. C

AD7892

ORDERING GUIDE

Input

Range

Sample

Rate

Relative

Accuracy

Temperature

Range

Package

Model

Option¹

AD7892AN-1

AD7892BN-1

AD7892AR-1

AD7892BR-1

AD7892SQ-1

AD7892AN-2

AD7892BN-2

AD7892AR-2

AD7892BR-2

AD7892AN-3

AD7892BN-3

AD7892AR-3

5 V or 10 V

0 V to +2.5 V

2.5 V

Evaluation Board

Controller Board

500 kSPS

600 kSPS

–40°C to +85°C

–55°C to +125°C

–40°C to +85°C

N-24

R-24

Q-24

N-24

R-24

N-24

R-24

1 LSB

AD7892BR-3

EVAL-AD7892-2CB²

EVAL-AD7892-3CB²

EVAL-CONTROL BOARD³

NOTES

¹N = Plastic DIP; Q = Cerdip; R = SOIC.

²These boards can be used as stand-alone evaluation boards or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.

³This board is a complete unit allowing a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB designators.

–5–

REV. C

AD7892

PIN FUNCTION DESCRIPTION

No.

Mnemonic

Description

1

2

V_DD

Positive Supply Voltage, +5 V 5%.

STANDBY

Standby Input. Logic Input. With this input at a logic high, the part is in its normal operating

mode; with this input at a logic low, the part is placed in its standby or power-down mode, which

reduces power consumption to 5 mW typical.

3

V_IN2

Analog Input 2. For the AD7892-1, this input either connects to AGND or to V_IN1to determine

the analog input voltage range. With V_IN2connected to AGND on the AD7892-1, the analog input

range at the V_IN1input is 10 V. With V_IN2connected to V_IN1on the AD7892-1, the analog input

range to the part is 5 V.

For the AD7892-2 and AD7892-3, this input can be left unconnected but must not be connected

to a potential other than AGND.

4

5

V_IN1

Analog Input 1. The analog input voltage to be converted by the AD7892 is applied to this input.

For the AD7892-1, the input voltage range is either 5 V or 10 V depending on where the V_IN2

input is connected. For the AD7892-2, the voltage range on the V_IN1input is 0 V to +2.5 V with

respect to the voltage appearing at the V_IN2input. For the AD7892-3, the voltage range on the V_IN1

input is 2.5 V.

REF OUT/REF IN

Voltage Reference Output/Input. The part can be used with either its own internal reference or with

an external reference source. The on-chip +2.5 V reference is provided at this pin. When using this

internal reference as the reference source for the part, REF OUT should be decoupled to AGND

with a 0.1 µF disc ceramic capacitor. The output impedance of this reference source is typically

5.5 kΩ. When using an external reference source as the reference voltage for the part, the reference

source should be connected to this pin. This overdrives the internal reference and provides the

reference source for the part. The REF IN input is buffered on-chip but must be able to sink or

source current through the resistor to the output of the on-chip reference. The nominal reference

voltage for correct operation of the AD7892 is +2.5 V.

6

7

AGND

MODE

Analog Ground. Ground reference for track/hold, comparator and DAC.

Mode. Control input which determines the interface mode for the AD7892. With this pin at a logic

low, the device is in its serial interface mode; with this pin at a logic high, the device is in its parallel

interface mode.

8

9

DB11/LOW

DB10/LOW

Data Bit 11/Test Pin. When the device is in its parallel mode, this pin is Data Bit 11 (MSB), a

three-state TTL-compatible output. When the device is in its serial mode, this is used as a test pin

which must be tied to a logic low for correct operation of the AD7892.

Data Bit 10/Test Pin. When the device is in its parallel mode, this pin is Data Bit 10, a three-state

TTL-compatible output. When the device is in its serial mode, this is used as a test pin which must

be tied to a logic low for correct operation of the AD7892.

10

11

12

13

DB9

DB8

DB7

DB6

Data Bit 9. Three-state TTL-compatible output. This output should be left unconnected when the

device is in its serial mode.

Data Bit 8. Three-state TTL-compatible output. This output should be left unconnected when the

device is in its serial mode.

Data Bit 7. Three-state TTL-compatible output. This output should be left unconnected when the

device is in its serial mode.

Data Bit 6. Three-state TTL-compatible output. This output should be left unconnected when the

device is in its serial mode.

14

15

DGND

Digital Ground. Ground reference for digital circuitry.

DB5/SDATA

Data Bit 5/Serial Data. When the device is in its parallel mode, this pin is Data Bit 5, a three-state

TTL-compatible output. When the device is in its serial mode, this becomes the serial data output

line. Sixteen bits of serial data are provided with four leading zeros preceding the 12 bits of valid

data. Serial data is valid on the falling edge of SCLK for sixteen edges after RFS goes low. Output

coding is two’s complement for AD7892-1 and AD7892-3 and straight (natural) binary for

AD7892-2.

–6–

REV. C

AD7892

No.

Mnemonic

Description

16

DB4/SCLK

Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state

TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin,

SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial

data from the AD7892. Serial data is clocked out from the output shift register on the rising edges

of SCLK after RFS goes low.

17

DB3/RFS

Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data

Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the

receive frame synchronization input with RFS provided externally to obtain serial data from the

AD7892.

18

19

20

DB2

DB1

DB0

Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the

device is in its serial mode.

Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the

device is in its serial mode.

Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for

AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left

unconnected when the device is in its serial mode.

21

22

23

RD

Read. Active low logic input which is used in conjunction with CS low to enable the data outputs.

Chip Select. Active low logic input which is used in conjunction with RD to enable the data outputs.

CS

EOC

End-of-Conversion. Active low logic output indicating converter status. The end of conversion is

signified by a low going pulse on this line. The duration of this EOC pulse is nominally 100 ns.

24

CONVST

Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold

mode and starts conversion.

PIN CONFIGURATION

DIP and SOIC

V

1

2

3

4

5

6

7

8

9

24 CONVST

23 EOC

DD

STANDBY

V

22 CS

IN2

IN1

21 RD

REF OUT/REF IN

AGND

20 DB0 (LSB)

19 DB1

AD7892

TOP VIEW

(Not to Scale)

MODE

18 DB2

DB11/LOW

DB10/LOW

17 DB3/RFS

DB4/SCLK

16

15 DB5/SDATA

14

DB9 10

DB8 11

DB7 12

DGND

13 DB6

–7–

REV. C

AD7892

TERMINOLOGY

Relative Accuracy

Signal to (Noise + Distortion) Ratio

Relative accuracy or endpoint nonlinearity is the maximum

deviation from a straight line passing through the endpoints of

the ADC transfer function.

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f_S/2), excluding dc.

The ratio is dependent upon the number of quantization levels

in the digitization process; the more levels, the smaller the quan-

tization noise. The theoretical signal to (noise + distortion)

ratio for an ideal N-bit converter with a sine wave input is given

by:

Differential Nonlinearity

This is the difference between the measured and the ideal

1 LSB change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7892-1)

This is the deviation of the last code transition (01 . . . 110 to

01 . . . 111) from the ideal 4 × REF IN – 3/2 LSB ( 10 V range)

or 2 × REF IN – 3/2 LSB ( 5 V range) after the bipolar zero

error has been adjusted out.

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Positive Full-Scale Error (AD7892-2)

Total Harmonic Distortion

This is the deviation of the last code transition (11 . . . 110 to

11 . . . 111) from the ideal (REF IN – 3/2 LSB) after the unipo-

lar offset error has been adjusted out.

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7892, it is defined

as:

Positive Full-Scale Error (AD7892-3)

This is the deviation of the last code transition (01 . . . 110 to

01 . . . 111) from the ideal (REF IN – 3/2 LSB) after the bipolar

zero error has been adjusted out.

2

V₂+V₃+V₄+V₅+V₆

THD (dB) = 20 log

V₁

Bipolar Zero Error (AD7892-1, AD7892-3)

This is the deviation of the midscale transition (all 1s to all 0s)

from the ideal (AGND – 1/2 LSB).

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅and V₆are the rms amplitudes of the second through the

sixth harmonics.

Unipolar Offset Error (AD7892-2)

This is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal (AGND + 1/2 LSB).

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

Negative Full-Scale Error (AD7892-1)

This is the deviation of the first code transition (10 . . . 000 to

10 . . . 001) from the ideal –4 × REF IN + 1/2 LSB ( 10 V

range) or –2 × REF IN + 1/2 LSB ( 5 V range) after bipolar

zero error has been adjusted out.

Negative Full-Scale Error (AD7892-3)

Intermodulation Distortion

This is the deviation of the first code transition (10 . . . 000 to

10 . . . 001) from the ideal – REF IN + 1/2 LSB after bipolar

zero error has been adjusted out.

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for

which neither m nor n are equal to zero. For example, the sec-

ond order terms include (fa + fb) and (fa – fb), while the third

order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and

(fa – 2fb).

Track/Hold Acquisition Time

Track/Hold acquisition time is the time required for the output

of the track/hold amplifier to reach its final value, within 1/2 LSB,

after the end of conversion (the point at which the track/hold

returns to track mode). It also applies to situations where there

is a step input change on the input voltage applied to the V_IN

input of the AD7892. It means that the user must wait for the

duration of the track/hold acquisition time after the end of con-

version or after a step input change to V_INbefore starting another

conversion, to ensure that the part operates to specification.

The AD7892 is tested using two input frequencies away from

the bottom end of the input bandwidth. In this case, the second

and third order terms are of different significance. The second

order terms are usually distanced in frequency from the original

sine waves while the third order terms are usually at a frequency

close to the input frequencies. As a result, the second and third

order terms are specified separately. The calculation of the

intermodulation distortion is as per the THD specification where it

is the ratio of the rms sum of the individual distortion products to

the rms amplitude of the fundamental expressed in dBs.

–8–

REV. C

AD7892

specified with a +2.5 V reference voltage. Errors in the refer-

ence source will result in gain errors in the AD7892’s transfer

function and will add to the specified full-scale errors on the

part. On the AD7892-1 and AD7892-3, it will also result in an

offset error injected in the attenuator stage.

CIRCUIT DESCRIPTION

The AD7892 is a fast, 12-bit single supply A/D converter. It

provides the user with signal scaling, track/hold, reference, A/D

converter and versatile interface logic functions on a single chip.

The signal scaling on the AD7892-1 allows the part to handle

either 5 V or 10 V input signals while operating from a single

+5 V supply. The AD7892-2 handles a 0 V to +2.5 V analog

input range, while signal scaling on the AD7892-3 allows it to

handle 2.5 V input signals when operating from a single supply.

The part requires a +2.5 V reference which can be provided from

the part’s own internal reference or from an external reference

source.

The AD7892 contains an on-chip +2.5 V reference. To use this

reference as the reference source for the AD7892, simply con-

nect a 0.1 µF disc ceramic capacitor from the REF OUT/

REF IN pin to AGND. The voltage that appears at this pin is

internally buffered before being applied to the ADC. If this

reference is required for use external to the AD7892, it should

be buffered as the part has a FET switch in series with the refer-

ence output resulting in a source impedance for this output of

5.5 kΩ nominal. The tolerance on the internal reference is

10 mV at 25°C with a typical temperature coefficient of

25 ppm/°C and a maximum error over temperature of 25 mV.

Conversion is initiated on the AD7892 by pulsing the CONVST

input. On the rising edge of CONVST, the track/hold goes

from track mode to hold mode and the conversion sequence is

started. At the end of conversion (falling edge of EOC), the

track/hold returns to tracking mode and the acquisition time

begins. Conversion time for the part is 1.47 µs (AD7892-3) and

the track/hold acquisition time is 200 ns (AD7892-3). This allows

the AD7892-3 to operate at throughput rates up to 600 kSPS.

The AD7892-1 and AD7892-2 are specified with a 1.6 µs con-

version and 400 ns acquisition time allowing a throughput rate

of 500 kSPS.

If the application requires a reference with a tighter tolerance or

the AD7892 needs to be used with a system reference, then the

user has the option of connecting an external reference to this

REF OUT/REF IN pin. The external reference will effectively

overdrive the internal reference and thus provide the reference

source for the ADC. The reference input is buffered before

being applied to the ADC with the maximum input current is

100 µA. Suitable reference sources for the AD7892 include the

AD680, AD780 and REF43 precision +2.5 V references.

Track/Hold Section

The track/hold amplifier on the AD7892 allows the ADC to

accurately convert an input sine wave of full-scale amplitude to

12-bit accuracy. The input bandwidth of the track/hold is greater

than the Nyquist rate of the ADC even when the ADC is oper-

ated at its maximum throughput rate of 600 kHz (i.e., the track/

hold can handle input frequencies in excess of 300 kHz).

INTERFACING

The part provides two interface options, a 12-bit parallel inter-

face and a three-wire serial interface. The required interface

mode is selected via the MODE pin. The two interface modes

are discussed in the following sections.

The track/hold amplifier acquires an input signal to 12-bit accu-

racy in less than 200 ns. The operation of the track/hold is

essentially transparent to the user. The track/hold amplifier

goes from its tracking mode to its hold mode on the rising edge

of CONVST. The aperture time for the track/hold (i.e., the

delay time between the external CONVST signal and the track/

hold actually going into hold) is typically 15 ns. At the end of

conversion, the part returns to its tracking mode. The acquisi-

tion time of the track/hold amplifier begins at this point.

Parallel Interface Mode

The parallel interface mode is selected by tying the MODE

input to a logic high. Figure 2 shows a timing diagram illustrat-

ing the operational sequence of the AD7892. The on-chip

track/hold goes into hold mode, and conversion is initiated on

the rising edge of the CONVST signal. When conversion is

complete, the end of conversion line (EOC) pulses low to indi-

cate that new data is available in the AD7892’s output register.

This EOC line can be used to drive an edge-triggered interrupt

of a microprocessor. The falling edge of the RD signal should

occur 200 ns prior to the next rising edge of CONVST. CS and

RD going low accesses the 12-bit conversion result. In systems

where the part is interfaced to a gate array or ASIC, this EOC

Reference Section

The AD7892 contains a single reference pin, labelled REF OUT/

REF IN, which either provides access to the part’s own +2.5 V

reference or to which an external +2.5 V reference can be con-

nected to provide the reference source for the part. The part is

CONVST (I)

t_ACQ

t₁

t₂

EOC (O)

t_CONV

t₉

t₃

CS (I)

RD (I)

t₄

t₈

t₅

t₇

t₆

THREE-STATE

DB0–DB11 (O)

THREE-STATE

VALID

DATA

NOTE:

I = INPUT; O = OUTPUT

Figure 2. Parallel Mode Timing Diagram

–9–

REV. C

AD7892

pulse can be applied to the CS and RD inputs to latch data out

of the AD7892 and into the gate array or ASIC. This eliminates

the logic required in the gate array or ASIC to recognize the end

of conversion and generate the read signal for the AD7892. To

obtain optimum performance from the AD7892, it is not recom-

mended to tie CS and RD permanently low as this keeps the

three-state active during conversion.

CONVST. For the AD7892-1 and AD7892-2, a serial read

should also be avoided within 400 ns of the rising edge of

CONVST. This limits the maximum achievable throughput

rate in serial mode (assuming 20 MHz serial clock) to 400 kSPS

for the AD7892-3 and 357 kSPS for the AD7892-1 and

AD7892-2.

Analog Input Section

Serial Interface Mode

The AD7892 is offered as three part types allowing for four

different analog input voltage ranges. The AD7892-1 handles

either 5 V or 10 V input voltage ranges. The AD7892-2

handles a 0 V to +2.5 V input voltage range while the AD7892-3

handles an input range of 2.5 V.

The AD7892 is configured for serial mode interfacing by tying

the MODE input low. It provides for a three-wire, serial link

between the AD7892 and industry-standard microprocessors,

microcontrollers and digital signal processors. SCLK and RFS

of the AD7892 are inputs, and the AD7892’s serial interface is

designed for direct interface to systems that provide a serial

clock input that is synchronized to the serial data output includ-

ing microcontrollers such as the 80C51, 87C51, 68HC11 and

68HC05 and most digital signal processors.

AD7892-1

Figure 4 shows the analog input section for the AD7892-1. The

analog input range is pin-strappable (using V_IN2) for either 5 V

or 10 V on the V_IN1input. With V_IN2connected to AGND, the

input range on V_IN1is 10 V, and the input resistance on V_IN1is

15 kΩ nominal. With V_IN2connected to V_IN1, the input range on

Figure 3 shows the timing diagram for reading from the AD7892

in the serial interface mode. RFS goes low to access data from

the AD7892. The serial clock input does not have to be con-

tinuous. The serial data can be accessed in a number of bytes.

However, RFS must remain low for the duration of the data

transfer operation. Sixteen bits of data are transmitted with four

leading zeros followed by the 12-bit conversion result starting

with the MSB. Serial data is clocked out of the device on the

rising edge of SCLK. Old data is guaranteed to be valid for 5 ns

after this edge. This is useful for high speed serial clocks where

the access time of the part would not allow sufficient set-up time

for the data to be accepted on the falling edge of the clock. In

this case, care must be taken that RFS does not go just prior to

a rising edge of SCLK. For slower serial clocks data is valid on

the falling edge of SCLK. At the end of the read operation, the

SDATA line is three-stated by a rising edge on either the SCLK

or RFS inputs, whichever occurs first. Serial data cannot be

read during conversion to avoid feedthrough problems from the

serial clock to the conversion process. For optimum perfor-

mance of the AD7892-3, a serial read should also be avoided

within 200 ns of the rising edge of CONVST to avoid feedthrough

into the track/hold during its acquisition time. The serial read

should, therefore, occur between the end of conversion (EOC

falling edge) and 200 ns prior to the next rising edge of

V_IN1is 5 V, and the input resistance on V_IN1is 8 kΩ nominal.

As a result, the V_IN1and V_IN2inputs should be driven from a

low impedance source. The resistor attenuator stage is followed

by the high input impedance stage of the track/hold amplifier.

This resistor attenuator stage allows the input voltage to go to

17 V without damaging the AD7892-1.

+2.5

REFERENCE

2k⍀

REF OUT/

REF IN

TO ADC

REFERENCE

3.25k⍀

6.5k⍀

CIRCUITRY

13k⍀

TO HIGH

IMPEDANCE

SHA INPUT

V

IN1

IN2

AGND

Figure 4. AD7892-1 Analog Input Structure

RFS (I)

t₁₀

t₁₂

t₁₆

SCLK (I)

t₁₇

t₁₃

t₁₄

t₁₁

t_17A

t₁₅

FOUR LEADING ZEROS

DB11

DB10

DB0

SDATA (O)

THREE-

STATE

NOTE:

I = INPUT; O = OUTPUT

Figure 3. Serial Mode Timing Diagram

–10–

REV. C

AD7892

The designed code transitions occur midway between successive

integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs). Output

coding is two’s complement binary with 1 LSB = FSR/4096 =

20 V/4096 = 4.88 mV for the 10 V range and 1 LSB = FSR/

4096 = 10 V/4096 = 2.44 mV for the 5 V range. The ideal

input/output transfer function for the AD7892-1 is shown in

Table I.

AD7892-3

Figure 5 shows the analog input section for the AD7892-3. The

analog input range is 2.5 V on the V_IN1input. The V_IN2input

can be left unconnected but if it is connected to a potential then

that potential must be AGND. The input resistance on the V_IN1

is 1.8 kΩ nominal. As a result, the V_IN1input should be driven

from a low impedance source. The resistor attenuator stage is

followed by the high input impedance stage of the track/hold

amplifier. This resistor attenuator stage allows the input voltage

to go to 7 V without damaging the AD7892-3.

AD7892-2

The analog input section for the AD7892-2 contains no biasing

resistors. The analog input looks directly into the track/hold

input stage. The analog input range on the V_IN1input is 0 V to

+2.5 V. The V_IN2input can be left unconnected but if it is

connected to a potential then that potential must be AGND.

The V_IN1input connects directly to the input sampling capacitor

of the AD7892-2’s track/hold. The value of this input sampling

capacitor is nominally 10 pF.

The designed code transitions occur midway between succes-

sive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs).

Output coding is two’s complement binary with 1 LSB = FSR/

4096 = 5 V/4096 = 1.22 mV with REF IN = +2.5 V. The ideal

input/output transfer function for the AD7892-3 is shown in

Table III.

Once again, the designed code transitions occur midway be-

tween successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,

5/2 LSBs). Output coding is straight (natural) binary with

1 LSB = FSR/4096 = 2.5 V/4096 = 0.61 mV. The ideal input/

output transfer function for the AD7892-2 is shown in Table II.

+2.5

REFERENCE

2k⍀

REF OUT/

REF IN

TO ADC

REFERENCE

CIRCUITRY

Table I. Ideal Input/Output Code Table for the AD7892-1

Digital Output

3.25k⍀

TO HIGH

IMPEDANCE

SHA INPUT

Analog Input

Code Transition

V

IN1

+FSR/2 – 3/2 LSB^{1, 2}(9.99268 or 4.99634)³

+FSR/2 – 5/2 LSBs (9.98779 or 4.99390)

+FSR/2 – 7/2 LSBs (9.98291 or 4.99146)

011 . . . 110 to 011 . . . 111

011 . . . 101 to 011 . . . 110

011 . . . 100 to 011 . . . 101

V

*

IN2

AGND

AGND + 3/2 LSB (0.00732 or 0.00366)

AGND + 1/2 LSB (0.00244 or 0.00122)

AGND – 1/2 LSB (–0.00244 or –0.00122)

AGND – 3/2 LSB (–0.00732 or –0.00366)

000 . . . 001 to 000 . . . 010

000 . . . 000 to 000 . . . 001

111 . . . 111 to 000 . . . 000

111 . . . 110 to 111 . . . 111

* UNCONNECTED INTERNALLY ON THE AD7892-3

Figure 5. AD7892-3 Analog Input Structure

–FSR/2 + 5/2 LSB (–9.98779 or –4.99390)

–FSR/2 + 3/2 LSB (–9.99268 or –4.99634)

–FSR/2 + 1/2 LSB (–9.99756 or –4.99878)

100 . . . 010 to 100 . . . 011

100 . . . 001 to 100 . . . 010

100 . . . 000 to 100 . . . 001

Table III. Ideal Input/Output Code Table for the AD7892-3

Digital Output

NOTES

¹FSR is full-scale range and REF IN = +2.5 V, is 20 V for the 10 V range and 10 V

Analog Input

Code Transition

for the 5 V range.

+FSR/2 – 3/2 LSB^{1, 2}(2.49817)

+FSR/2 – 5/2 LSBs (2.49695)

+FSR/2 – 7/2 LSBs (2.49573)

011 . . . 110 to 011 . . . 111

011 . . . 110 to 011 . . . 110

011 . . . 110 to 011 . . . 101

²1 LSB = FSR/4096 = 4.88 mV ( 10 V range) and 2.44 mV ( 5 V range) with REF

IN = +2.5 V.

3

10 V range or 5 V range.

AGND + 3/2 LSB (0.00183)

AGND + 1/2 LSB (0.00061)

AGND – 1/2 LSB (–0.00061)

AGND – 3/2 LSB (–0.00183)

000 . . . 001 to 000 . . . 010

000 . . . 000 to 000 . . . 001

111 . . . 111 to 000 . . . 000

111 . . . 110 to 111 . . . 111

Table II. Ideal Input/Output Code Table for the AD7892-2

Digital Output

–FSR/2 + 5/2 LSB (–2.49695)

–FSR/2 + 3/2 LSB (–2.49817)

–FSR/2 + 1/2 LSB (–2.49939)

100 . . . 010 to 100 . . . 011

100 . . . 001 to 100 . . . 010

100 . . . 000 to 100 . . . 001

Analog Input

Code Transition

+FSR – 3/2 LSB^{1, 2}(2.499084 V)

+FSR – 5/2 LSBs (2.498474 V)

+FSR – 7/2 LSBs (2.497864 V)

111 . . . 110 to 111 . . . 111

111 . . . 110 to 111 . . . 110

111 . . . 100 to 111 . . . 101

NOTES

¹FSR is full-scale range and is 5 V with REF IN = +2.5 V.

²1 LSB = FSR/4096 = 1.22 mV with REF IN = +2.5 V.

AGND + 5/2 LSB (0.001526 V)

AGND + 3/2 LSB (0.00916 V)

AGND + 1/2 LSB (0.000305 V)

000 . . . 010 to 010 . . . 011

000 . . . 001 to 001 . . . 010

000 . . . 000 to 000 . . . 001

NOTES

¹FSR is full-scale range and is 2.5 V with REF IN = +2.5 V.

²1 LSB = FSR/4096 = 0.61 mV with REF IN = +2.5 V.

–11–

REV. C

AD7892

MICROPROCESSOR INTERFACING

EOC Pulse Provides CS and RD

The AD7892 features both high speed parallel and serial inter-

faces, allowing considerable flexibility in interfacing to micro-

processor systems. To obtain optimum performance from the

part, data should not be read during conversion and this limits

the achievable throughput rate in serial mode to 400 kSPS for

the AD7892-3.

Figure 8 shows a parallel interface between the AD7892 and a

gate array or ASIC. CONVST starts conversion and at the end

of conversion the falling edge of the EOC output provides the

CS and RD pulse to latch data out of the AD7892 and into the

gate array/ASIC. This scheme allows for the fastest possible

throughput rate with the part as no time is lost in interrupt

service routines and as soon as data is available from the part it

is transferred out of it.

Figures 6, 7 and 9 show some typical interface circuits between

the AD7892 and popular DSP processors. Figure 8 shows an

interface between the part and a gate array or ASIC where data

is clocked into the ASIC by the AD7892 itself at the end of

conversion. In all cases, the CONVST signal is generated from

an external timer to ensure equidistant sampling.

TIMER

AD7892

AD7892 to ADSP-2101 Interface

GATE

Figure 6 shows a parallel interface between the AD7892 and the

ADSP-2101 DSP processor. CONVST starts conversion and at

the end of conversion the falling edge of the EOC output pro-

vides an interrupt request to the ADSP-2101.

ARRAY/ASIC

CONVST

EOC

RD

ENABLE

CS

TIMER

ADDRESS BUS

DMA13–DMA0

DB11–DB0

DATA BUS

DB11–DB0

ADSP-2101

ADDRESS DECODE

LOGIC

AD7892

DMS

EN

Figure 8. AD7892 to Gate Array/ASIC Interface

CONVST

CS

AD7892 to DSP56000 Interface

Figure 9 shows a serial interface between the AD7892 and the

DSP56000 DSP processor. CONVST starts conversion and at

the end of conversion the falling edge of the EOC output pro-

vides an interrupt request to the DSP56000.

IRQn

RD

EOC

RD

DATA BUS

DMD15–DMD0

DB11–DB0

TIMER

AD7892

DSP56000

Figure 6. AD7892 to ADSP-2101

AD7892 to TMS320C25 Interface

Figure 7 shows a parallel interface between the AD7892 and the

TMS320C25 DSP processor. CONVST starts conversion and

at the end of conversion the falling edge of the EOC output

provides an interrupt request to the TMS320C25.

CONVST

IRQA

SCK

SRD

SC1

EOC

SCLK

SDATA

RFS

TIMER

Figure 9. AD7892 to DSP56000 Interface

A15–A0

ADDRESS BUS

TMS320C25

ADDRESS DECODE

LOGIC

CS

IS

EN

CONVST

G2

READY

AD7892

RD

MSC

STRB

R/W

EOC

INT

DATA BUS

D15–D0

DB11–DB0

Figure 7. AD7892 to TMS320C25 Interface

–12–

REV. C

AD7892

Good decoupling is important when using high resolution ADCs.

All analog supplies should be decoupled with 10 µF tantalum in

parallel with 0.1 µF capacitors to AGND. To achieve the best

from these decoupling components, they have to be placed as

close as possible to the device, ideally right up against the device.

All logic chips should be decoupled with 0.1 µF disc ceramic

capacitors to DGND. It is recommended that the system’s

AV_DDsupply is used to supply the V_DDfor the AD7892. This

supply should have the recommended analog supply decoupling

capacitors between the V_DDpin of the AD7892 and AGND and

the recommended digital supply decoupling capacitor between

the V_DDpin of the AD7892 and DGND.

Grounding and Layout

The AD7892 has a single supply voltage pin, V_DD, which sup-

plies both the analog and digital circuitry on the part. For opti-

mum performance from the part, it is recommended that this

+5 V is taken from the +5 V analog supply in the system. The

analog and digital grounds to the AD7892 are independent and

separately pinned out to minimize coupling between the analog

and digital sections of the device. The part exhibits good immu-

nity to noise on the supplies but care must still be taken with

regard to grounding and layout especially when using switching

mode supplies.

The printed circuit board which houses the AD7892 should be

designed such that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes which can be separated easily. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should only be

joined in one place. If the AD7892 is the only device requiring

an AGND to DGND connection, then the ground planes

should be connected at the AGND and DGND pins of the

AD7892. If the AD7892 is in a system where multiple devices

require AGND to DGND connections, the connection should

still be made at one point only, a star ground point which

should be established as close as possible to the AD7892.

Evaluating the AD7892 Performance

The recommended layout for the AD7892 is outlined in the

evaluation board for the AD7892. The evaluation board package

includes a fully assembled and tested evaluation board, docu-

mentation and software for controlling the board from a PC

using the EVAL-CONTROL BOARD. The EVAL-CONTROL

BOARD can be used in conjunction with the AD7892 evalua-

tion board, as well as many other Analog Devices evaluation

boards ending in the CB designator. Using the EVAL-CONTROL

BOARD with the AD7892 evaluation board allows the user to

evaluate the ac and dc performance of the AD7892 on a PC.

The software provided with the evaluation board allows the user

to perform ac (Fast Fourier Transform) and dc (histogram of

codes) tests on the AD7892. The evaluation board can also

be used in a stand-alone fashion without the EVAL-CONTROL

BOARD but in this case, the user has to write their own software

to evaluate the part. There are two versions of the evaluation

board available, one for the AD7892-2 and one for the AD7892-3.

To order the AD7892-2 evaluation board, the order number is

EVAL-AD7892-2CB and to order the AD7892-3 evaluation

board, the order number is EVAL-AD7892-3CB.

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7892 to avoid noise coupling. The power

supply lines to the AD7892 should use as large a trace as pos-

sible to provide low impedance paths and reduce the effects of

glitches on the power supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board and clock signals should

never be run near the analog inputs. Avoid crossover of digital

and analog signals. Traces on opposite sides of the board should

run at right angles to each other. This will reduce the effects of

feedthrough through the board. A microstrip technique is by far

the best but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

–13–

REV. C

AD7892

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic DIP (N-24)

1.228 (31.19)

1.226 (31.14)

24

1

13

0.260 0.001

(6.61 0.03)

12

0.32 (8.128)

0.30 (7.62)

PIN 1

0.130 (3.30)

0.128 (3.25)

0.011 (0.28)

0.009 (0.23)

SEATING

PLANE

0.07 (1.78)

0.05 (1.27)

0.02 (0.5)

0.11 (2.79)

15؇

0

0.016 (0.41) 0.09 (2.28)

Cerdip (Q-24)

0.005 (0.13) MIN

24

0.098 (2.49) MAX

13

12

0.310 (7.87)

0.220 (5.59)

1

0.320 (8.13)

0.290 (7.37)

PIN 1

0.060 (1.52)

0.015 (0.38)

1.280 (32.51) MAX

0.200 (5.08)

MAX

0.150

(3.81)

MIN

0.200 (5.08)

0.125 (3.18)

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

0.023 (0.58)

0.014 (0.36)

0.070 (1.78)

0.030 (0.76)

0.100 (2.54)

BSC

15°

0°

SOIC (R-24)

0.614 (15.6)

0.598 (15.2)

24

1

13

12

0.1043 (2.65)

0.0926 (2.35)

PIN 1

0.0291 (0.74)

0.0098 (0.25)

؋

45؇

0.050 (1.27)

0.015 (0.40)

8؇

0؇

0.050

(1.27)

BSC

0.019 (0.49)

0.012 (0.30)

0.004 (0.10)

SEATING

0.014 (0.35)

PLANE

0.013 (0.32)

0.009 (0.23)

–14–

REV. C


型号：	5962-9684601QJA
厂家：	ADI
描述：	LC2MOS Single Supply, 12-Bit 600 kSPS ADC LC2MOS单电源， 12位600 kSPS的ADC 转换器模数转换器
文件：	总14页 (文件大小：145K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5962-9684601QJA [ADI]

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