AD10201/PCB_技术文档

Dual-Channel, 12-Bit 105 MSPS

IF Sampling A/D Converter

a

AD10201

FEATURES

PRODUCT DESCRIPTION

Two Independent 12-Bit, 105 MSPS ADCs

Channel-to-Channel Isolation, > 90 dB

AC-Coupled Signal Conditioning Included

Gain Flatness up to Nyquist, < 0.1 dB

Input VSWR 1.05:1 to Nyquist

80 dB Spurious-Free Dynamic Range

Two’s Complement Output Format

3.3 V or 5 V CMOS-Compatible Output Levels

900 mW Per Channel

The AD10201 offers two complete ADC channels with on-module

signal conditioning for improved dynamic performance. Each wide

dynamic range ADC has a transformer coupled front end optimized

for direct IF sampling. The AD10201 has on-chip track-and-hold

circuitry, and uses an innovative architecture to achieve 12-bit,

105 MSPS performance. The AD10201 uses innovative high

density circuit design to achieve exceptional performance while still

maintaining excellent isolation and providing for board area savings.

The AD10201 operates with 5.0 V supply for the analog-to-digital

conversion. Each channel is completely independent, allowing

operation with independent ENCODE and analog inputs. The

AD10201 is available as a 35 mm square 385-lead BGA package.

Single-Ended or Differential Input

250 MHz Input Bandwidth

APPLICATIONS

Wireless and Wired Broadband Communications

Base Stations and “Zero-IF” or Direct IF Sampling

Subsystems

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 105 MSPS

Wireless Local Loop (WLL)

Local Multipoint Distribution Service (LMDS)

Radar and Satellite Subsystems

2. Input signal conditioning included with full-power bandwidth

to 250 MHz

3. Industry-leading IF sampling performance

FUNCTIONAL BLOCK DIAGRAM

A

A1 A A2

IN

A B1 A B2

IN IN

IN

D0B

(LSB)

D0A

(LSB)

D1A

D2A

D1B

D2B

T1A

T1B

D3A

D4A

D5A

D6A

D7A

D8A

D9A

D10A

D3B

D4B

50⍀

T/H

D5B

D6B

D7B

D8B

AD10201

ADC

12

D9B

D10B

OUTPUT

RESISTORS

D11B

(MSB)

D11A

(MSB)

TIMING

REF

TIMING

ENCODEA

REF_A_OUT

REF_B_OUT

ENCODEB

ENCODEA

ENCODEB

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD10201–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS¹

(V_DD= 3.3 V, V_CC= 5.0 V; ENCODE = 105 MSPS, unless otherwise noted.)

Test

Parameter

Temp

Level

Min

Typ

Max

Unit

RESOLUTION

12

Bits

DC ACCURACY

Differential Nonlinearity

Integral Nonlinearity

No Missing Codes

Gain Error²

Output Offset

Gain Tempco

Full

25°C

Full

IV

I

V

–0.99

1.5

0.5

0.1

Guaranteed

2

60

–12

+0.99

+1.5

LSB

–9

–8

+9

+8

% FS

LSB

ppm/°C

Offset Tempco

ANALOG INPUT

Input Voltage Range

Input Impedance

25°C

Full

V

1.75

50

1.05:1

250

300

V p-p

Ω

Ratio

MHz

kHz

Input VSWR³

Analog Input Bandwidth, High

Analog Input Bandwidth, Low

ANALOG REFERENCE

Output Voltage

Load Current

25°C

Full

V

2.5

5

50

V

mA

ppm/°C

Tempco

SWITCHING PERFORMANCE⁴

Maximum Conversion Rate

Minimum Conversion Rate

Duty Cycle

Full

25°C

Full

25°C

VI

IV

V

105

45

MSPS

%

ns

ps rms

ns

10

55

50

Aperture Delay (t_A)

2.0

0.25

6.3

6.5

3.5

3.3

Aperture Uncertainty (Jitter)

V

Output Valid Time (t_V)⁵

Output Propagation Delay (t_PD

Output Rise Time (t_R)

IV

V

3.0

5

)

9.0

Output Fall Time (t_F)

V

DIGITAL INPUTS

ENCODE Input Common-Mode

Differential Input (ENC, ENC)

Logic “1” Voltage

Logic “0” Voltage

Input Resistance

Full

25°C

IV

V

1.2

0.4

2.0

1.6

2.0

5.0

V

kΩ

pF

0.8

8.0

3

5

4.5

Input Capacitance

DIGITAL OUTPUTS

Logic “1” Voltage⁵

Logic “0” Voltage⁵

Output Coding

Full

IV

3.1

3.3

0

V

0.2

Two’s Complement

POWER SUPPLY⁶

Power Dissipation⁷

Power Supply Rejection Ratio

Total I (DV_DD) Current

Total I (AV_CC) Current

Full

VI

IV

VI

1800

0.5

32

2200

+5.0

40

mW

mV/V

mA

–5.0

340

410

mA

–2–

REV. 0

AD10201

Test

Level

Parameter

Temp

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)⁸(Without Harmonics)

f_IN= 10 MHz

f_IN= 41 MHz

f_IN= 71 MHz

f_IN= 121 MHz

25°C

I

V

I

V

66

68

67

66.5

63

dBFS

63.5

Signal-to-Noise Ratio (SINAD)⁹(With Harmonics)

f_IN= 10 MHz

f_IN= 41 MHz

f_IN= 71 MHz

f_IN= 121 MHz

25°C

I

V

I

65.5

63

67.5

67.2

65

dBFS

V

59

Spurious-Free Dynamic Range¹⁰

f_IN= 10 MHz

25°C

I

V

I

75.5

71

81

76

74

63

dBFS

f_IN= 41 MHz

f_IN= 71 MHz

f_IN= 121 MHz

V

Two-Tone Intermodulation

Distortion¹¹(IMD)

f

_IN= 10 MHz; f_IN= 12 MHz

25°C

V

81

66

61

dBc

f_IN= 71 MHz; f_IN= 72 MHz

f

_IN= 121 MHz; f_IN= 122 MHz

Channel-to-Channel Isolation¹²

f_IN= 121 MHz

Full

IV

90

dBc

NOTES

¹All specifications tested by driving ENCODE and ENCODE differentially, with the analog input applied to A_INX1 and A_INX2 tied to ground.

²Gain error measured at 10.3 MHz.

³Input VSWR, see TPC 12.

⁴See Figure 1, Timing Diagram.

⁵t_Vand t_PDare measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is

not to exceed an ac load of 10 pF or a dc current of 40 ꢀA.

⁶Supply voltages should remain stable within 5% for normal operation.

⁷Power dissipation measures with encode at rated speed.

⁸Analog input signal power at –1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first six harmonics removed).

ENCODE = 105 MSPS. SNR is reported in dBFS, related back to converter full scale.

⁹Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. ENCODE = 105 MSPS.

SINAD is reported in dBFS, related back to converter full scale.

¹⁰Analog input signal equals –1 dBFS; SFDR is ratio of converter full scale to worst spur.

¹¹Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.

¹²Channel-to-channel isolation tested with A channel/50 Ω terminated (A_INA2 grounded) and a full-scale signal applied to B channel (A_INB2).

Specifications subject to change without notice.

–3–

REV. 0

AD10201

ABSOLUTE MAXIMUM RATINGS*

EXPLANATION OF TEST LEVELS

Test Level

V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . 5 V p-p (18 dBm)

Digital Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+0.5 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature (Ambient) . . . . . . . –55°C to +125°C

Storage Temperature (Ambient) . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

* Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions outside of those indicated in the operation sections

of this specification is not implied. Exposure to absolute maximum ratings for

extended periods may affect device reliability.

I

100% production tested

II 100% production tested at 25°C and sample tested at specific

temperatures

III Sample tested only

IV Parameter is guaranteed by design and characterization

testing

V

Parameter is a typical value only

VI 100% production tested at 25°C; guaranteed by design and

characterization testing for industrial temperature range

Table I. Output Coding (V_REF= 2.5 V) (Two’s Complement)

Code

A_IN(V)

Digital Output

THERMAL CHARACTERISTICS

385-Lead BGA Package:

The typical θ_JAof the module as determined by an IR scan is

25.33°C/W.

+2047

·

+0.875

·

0111 1111 1111

·

0

0000 0000 0000

–1

·

–0.000427

·

1111 1111 1111

·

–2048

–0.875

1000 0000 0000

SAMPLE N؊1

SAMPLE N

SAMPLE N؉10

SAMPLE N؉11

AIN

SAMPLE N؉1

SAMPLE N؉9

1/f_S

ENCODE

t_PD

t_V

D11؊D0

DATA N؊11

DATA N؊10

N؊9

N؊2

DATA N؊1

DATA N

DATA N؉1

Figure 1. Timing Diagram

ORDERING GUIDE

Package Description

Model

Temperature Range

Package Option

AD10201AB

AD10201/PCB

–25°C to +85°C (Ambient)

+25°C

385-Lead BGA (35 mm ꢁ 35 mm)

Evaluation Board with AD10201AB

B-385

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD10201 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. 0

AD10201

PIN CONFIGURATION

25

23

21

19

17

15

13

11

9

7

5

3

1

24

22

20

18

16

14

12

10

8

6

4

2

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

35 mm square

BOTTOMVIEW

PIN FUNCTION DESCRIPTIONS

Mnemonic

Function

AGNDA

REF_A_OUT

NC

A Channel Analog Ground. A and B grounds should be connected as close to the device as possible

A Channel Internal Voltage Reference

No connection

A_INA1

Analog Input for A side ADC (؊ input)

A_INA2

Analog Input for A side ADC (+ input)

AV_CC

A

Analog Positive Supply Voltage (nominally 5.0 V)

A Channel Digital Ground

DGNDA

D11A–D0A

ENCODEA

Digital Outputs for ADC A. D0 (LSB)

Complement of ENCODE

Data conversion initiated on the rising edge of ENCODE input

Digital Positive Supply Voltage (nominally 3.3 V)

B Channel Digital Ground

DV_CC

A

DGNDB

D11B–D0B

AGNDB

Digital Outputs for ADC B. D0 (LSB)

B Channel Analog Ground. A and B grounds should be connected as close to the device as possible.

Digital Positive Supply Voltage (nominally 3.3 V)

Complement of ENCODE

DV_CC

B

ENCODEB

REF_B_OUT

A_INB1

Data conversion initiated on rising edge of ENCODE input

B Channel Internal Voltage Reference

Analog Input for B side ADC (؊ input)

A_INB2

Analog Input for B side ADC (+ input)

AV_CC

B

Analog Positive Supply Voltage (nominally 5.0 V)

REV. 0

–5–

AD10201

385-LEAD BGA PINOUT

Ball Signal Ball Signal

No. Name

Ball Signal

No. Name

Ball Signal

No. Name

Ball Signal

No. Name

No.

Name

No. Name

A1

A2

A3

A4

A5

A6

A7

A8

AGNDA

DNC

AGNDA

AV_CCA

REF_A_OUT

AGNDA

DNC

AGNDB

AV_CCB

AGNDB

AV_CCB

DNC

C16 AV_CCB

C17 AGNDB

C18 AV_CCB

C19 DNC

H24 AGNDB

H25 AGNDB

N16 AGNDB

N22 AGNDB

N23 AGNDB

N24 AGNDB

N25 AGNDB

V24

V25

W1

W2

W3

W4

W22 DB4

W23 DB4

W24 DB4

W25 DB4

Y1

Y2

Y3

Y4

Y22

Y23

Y24

Y25

AA1 DGNDA

AA2 DGNDA

AA3 DGNDA

AA4 DGNDA

AA22 DGNDB

AA23 DGNDB

AA24 DGNDB

AA25 DGNDB

AB1 OVRA

AB2 OVRA

AB3 OVRA

AB4 OVRA

AB5 DGNDA

AB6 DA6

AB7 DA5

AB8 DA4

AB9 DA3

AB10 DA2

AB11 DA1

AB12 DA0

AB13 DGNDA

AB14 DGNDB

AB15 DB11

AB16 DB10

AB17 DB9

AB18 DB8

AB19 DB7

AB20 DB6

AB21 DGNDB

AB22 OVRB

AB23 OVRB

AB24 OVRB

AB25 OVRB

AC1 DGNDA

AC2 DGNDA

AC3 DGNDA

AC4 DGNDA

AC5 DGNDA

AC6 DA6

DB3

DA8

AC13 DGNDA

AC14 DGNDB

AC15 DB11

AC16 DB10

AC17 DB9

AC18 DB8

AC19 DB7

AC20 DB6

AC21 DGNDB

AC22 DGNDB

AC23 DGNDB

AC24 DGNDB

AC25 DGNDB

AD1 DGNDA

AD2 DGNDA

AD3 DGNDA

AD4 DGNDA

AD5 DGNDA

AD6 DA6

AD7 DA5

AD8 DA4

AD9 DA3

AD10 DA2

AD11 DA1

AD12 DA0

AD13 DGNDA

AD14 DGNDB

AD15 DB11

AD16 DB10

AD17 DB9

AD18 DB8

AD19 DB7

AD20 DB6

AD21 DGNDB

AD22 DGNDB

AD23 DGNDB

AD24 DGNDB

AD25 DGNDB

AE1 DGNDA

AE2 DGNDA

AE3 DGNDA

AE4 DGNDA

AE5 DGNDA

AE6 DA6

AE7 DA5

AE8 DA4

AE9 DA3

AE10 DA2

AE11 DA1

AE12 DA0

AE13 DGNDA

AE14 DGNDB

AE15 DB11

AE16 DB10

AE17 DB9

AE18 DB8

AE19 DB7

AE20 DB6

AE21 DGNDB

AE22 DGNDB

AE23 DGNDB

AE24 DGNDB

AE25 DGNDB

J1

J2

J3

AV_CCA

C20 DNC

C21 AGNDB

C22 AGNDB

C23 AGNDB

C24 AGNDB

C25 AGNDB

J4

AV_CCA

P1

P2

P3

P4

AGNDA

DNC

AGNDB

DV_CCB

J22

J23

J24

J25

K1

K2

K3

K4

REF_B_OUT

AGNDA

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

C1

C2

C3

C4

C5

C6

C7

C8

C9

P10

P11

P12

P13

P14

P15

P16

P22

P23

P24

P25

R1

D1

D2

D3

D4

D5

D6

D7

D8

D9

AGNDA

A_INA2

A_INA1

AGNDA

DA7

DB5

K10 AV_CCA

K11 AGNDA

K12 AGNDA

K13 DNC

K14 AGNDB

K15 AGNDB

K16 AV_CCB

K22 AGNDB

K23 AGNDB

K24 AGNDB

K25 AGNDB

DV_CCB

DV_CC

B

DNC

D10 AV_CCA

D11 REF_A_OUT

D12 AGNDA

D13 DNC

D14 AGNDB

D15 AGNDB

D16 AV_CCB

D17 AGNDB

D18 AV_CCB

DV_CCB

AGNDB

AGNDA

DNC

AGNDA

AV_CCA

REF_A_OUT

AGNDA

DNC

AGNDB

AV_CCB

DV_CC

A

R2

DV_CCA

R3

DV_CCA

R4

DV_CC

A

L1

L2

L3

L4

AGNDA

DNC

AGNDA

DNC

R10

R11

R12

R13

R14

R15

R16

R22

R23

R24

R25

T1

AGNDA

DNC

AGNDB

DB0

DA11

D19

A

_INB2

D20 A_INB1

L10

L11

L12

L13

L14

L15

L16

L22

L23

L24

L25

M1

M2

M3

M4

D21 AGNDB

D22 AGNDB

D23 AGNDB

D24 AGNDB

D25 AGNDB

AGNDB

DNC

E1

E2

E3

E4

E22

E23

E24

E25

F1

AGNDA

AGNDB

AGNDA

AGNDB

AGNDA

ENCBB

ENCAB

T2

DA11

T3

DA11

T4

DA11

T10 AV_CCA

T11 AGNDA

T12 AGNDA

T13 DNC

T14 AV_CCB

T15 AGNDB

T16 AGNDB

T22 DB1

AGNDB

AV_CCB

DNC

F2

F3

F4

M10 AGNDA

M11 AGNDA

M12 AGNDA

M13 DNC

M14 AGNDB

M15 AGNDB

M16 AGNDB

M22 ENCB

M23 ENCB

M24 ENCB

M25 ENCB

AGNDB

AGNDA

DNC

F22

F23

F24

F25

G1

G2

G3

G4

T23 DB1

T24 DB1

T25 DB1

U1

U2

U3

U4

DA10

G22 AGNDB

G23 AGNDB

G24 AGNDB

G25 AGNDB

N1

N2

N3

N4

ENCA

U22 DB2

U23 DB2

U24 DB2

U25 DB2

DNC

AGNDA

AC7 DA5

AC8 DA4

AC9 DA3

AC10 DA2

AC11 DA1

AC12 DA0

C10 AV_CCA

H1

H2

H3

H4

AGNDA

N10 AGNDA

N11 AGNDA

N12 AGNDA

N13 DNC

N14 AGNDB

N15 AGNDB

V1

V2

V3

V4

V22

V23

DA9

DB3

C11 REF_A_OUT

C12 AGNDA

C13 DNC

C14 AGNDB

C15 AGNDB

H22 AGNDB

H23 AGNDB

–6–

REV. 0

AD10201

385-LEAD BGA PINOUT (Top View, PCB Footprint)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DNC

DNC AGNDA AV

A

REF_A_OUT AGNDA DNC AGNDB AGNDB AV B AGNDB AV

B

DNC DNC AGNDB AGNDB AGNDB AGNDB AGNDB

B DNC DNC AGNDB AGNDB AGNDB AGNDB AGNDB

CC

A

B

C

D

CC

DNC AGNDA AV

A

REF_A_OUT AGNDA DNC AGNDB AGNDB AV B AGNDB AV

CC

AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA DNC

DNC AGNDA AV

A

REF_A_OUT AGNDA DNC AGNDB AGNDB AV B AGNDB AV

CC

B

DNC DNC AGNDB AGNDB AGNDB AGNDB AGNDB

CC

AGNDA AGNDA AGNDA AGNDA AGNDA AGNDA

AGNDA AGNDA AGNDA AGNDA

A

A2

A

A1 AGNDA AV

A

REF_A_OUT AGNDA DNC AGNCB AGNCB AV B AGNCB AV

CC CC

B

A

B2

A

B1 AGNDB AGNDB AGNDB AGNDB AGNDB

CC

IN

AGNDB AGNDB AGNDB AGNDB

E

F

G

H

J

K

L

REF_B_OUTREF_B_OUT REF_B_OUTREF_B_OUT

AGNDB AGNDB AGNDB AGNDB

AV

A

AGNDA AGNDA DNC AGNDB AGNDB AV B

CC

AGNDA AGNDA AGNDA AGNDA

CC

DNC

AGNDA AGNDA DNC AGNDB AGNDB DNC

ENCBB ENCBB ENCBB ENCBB

M

N

AGNDA AGNDA AGNDA DNC AGNDB AGNDB AGNDB

ENCB

AGNDB AGNDB AGNDB AGNDB

DV DV DV DV

ENCB

ENCB ENCB

ENCAB ENCAB ENCAB ENCAB

ENCA ENCA ENCA ENCA

AGNDA AGNDA AGNDA DNC AGNDB AGNDB AGNDB

DNC

P

R

T

AGNDA AGNDA AGNDA AGNDA

AGNDA AGNDA AGNDA

AGNDB AGNDB AGNDB

B

CC

DV

A

DV A DV A DV

CC CC

A

CC

AGNDA AGNDA AGNDA DNC AGNDB AGNDB AGNDB

DB0

CC

DA11 DA11 DA11 DA11

DA10 DA10 DA10 DA10

AV

A

AGNDA AGNDA DNC AV B AGNDB AGNDB

CC

DB1

DB2

DB1

DB2

DB1

DB2

DB1

DB2

CC

U

V

DB3

DB4

DB5

DB3

DB4

DB5

DB3

DB4

DB5

DB3

DB4

DB5

DA9

DA8

DA7

DA9

DA8

DA7

DA9

DA8

DA7

DA9

DA8

DA7

W

Y

DGNDA DGNDA DGNDA DGNDA

OVRA OVRA OVRA OVRA

DGNDA DGNDA DGNDA DGNDA

AA

DGNDB DGNDB DGNDB DGNDB

DB6 DGNDB OVRB OVRB OVRB OVRB

DGNDA DA6

DA5

DA4

DA3

DA2

DA1

DA0 DGNDA DGNDB DB11 DB10 DB9 DB8

DB7

AB

AC

AD

AE

DA4

DB6 DGNDB DGNDB DGNDB DGNDB DGNDB

DGNDA DGNDA DGNDA DGNDA

DNC = DO NOT CONNECT

REV. 0

–7–

– Typical Performance Characteristics

AD10201

0

؊10

؊20

؊30

؊40

؊50

؊60

؊70

؊80

؊90

؊100

؊110

؊120

0

ENCODE = 105MSPS

IN

SNR = 67.65dBFS

SFDR = 88.14dBFS

ENCODE = 105MSPS

IN = 121MHz (–1dBFS)

SNR = 64.4dBFS

SFDR = 65.4dBFS

؊10

؊20

A

= 10MHz (–1dBFS)

A

؊30

؊40

؊50

؊60

؊70

؊80

؊90

؊100

؊110

؊120

؊130

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

FREQUENCY – MHz

TPC 1. Single Tone @ 10 MHz

TPC 4. Single Tone @ 121 MHz

0

؊10

؊20

؊30

؊40

؊50

؊60

0

ENCODE = 105MSPS

؊10

ENCODE = 105MSPS

= 10.3MHz AND 12MHz

A

= 49MHz (–1dBFS)

IN

A

IN

SFDR = 87.82dBFS

؊20

؊30

؊40

؊50

؊60

؊70

؊80

؊90

؊100

؊110

SNR = 66.97dBFS

SFDR = 82.66dBFS

؊70

؊80

؊90

؊100

؊110

؊120

؊130

؊120

؊130

0

5

10

15

20

25

30

35

40

5

10

15

20

25

30

35

40

45

50

FREQUENCY – MHz

TPC 2. Single Tone @ 49 MHz

TPC 5. Two Tone @ 10/12 MHz

0

؊10

0

؊10

؊20

؊30

؊40

؊50

؊60

ENCODE = 105MSPS

ENCODE = 105 MSPS

= 71 AND 72 MHz

SFDR = 83.03dBFS

A

= 71MHz (–1dBFS)

IN

A

؊20

SNR = 66.1dBFS

SFDR = 81.3dBFS

IN

؊30

؊40

؊50

2 2

F F

2 1

2

F

؊60

2

F

2

•

F

•

1

•

؊70

؊80

F

1

•

F F

1 2

F

1

+

F

2

F

2

؊80

؊90

؊100

؊110

؊120

؊130

؊100

؊110

؊120

؊130

0

5

10

15

20

25

30

35

40

5

10

15

20

25

30

35

40

45

50

FREQUENCY – MHz

TPC 3. Single Tone @ 71 MHz

TPC 6. Two Tone @ 71/72 MHz

–8–

REV. 0

AD10201

0

؊10

3.0

2.0

1.0

ENCODE = 105MSPS

INL MIN = 0.586

INL MAX = 0.472

ENCODE = 105MSPS

= 121MHz AND 122MHz

SFDR = 69.05dBFS

A

IN

؊20

؊30

؊40

؊50

؊60

0.0

؊70

؊80

؊1.0

؊90

؊100

؊110

؊120

؊130

؊2.0

؊3.0

0

1

0

5

10

15

20

25

30

35

40

45

50

0

512

1024

1536

2048

2560 3072 3584

4096

FREQUENCY – MHz

OUTPUT CODES

TPC 7. Two Tone @ 121/122 MHz

TPC 10. Integral Nonlinearity

0

1MHz = 1.007

10MHz = 1.030

50MHz = 1.028

100MHz = 1.042

140MHz = 1.095

160MHz = 1.134

200MHz = 1.254

؊

1

2

3

؊

4

5

؊

؊6

10

100

1000

FREQUENCY – MHz

TPC 8. Gain Flatness*

TPC 11. Input Impedance S11

3.0

2.5

10

9

10MHz = 51.45 ؉ j 0.09

50MHz = 50.34 ؉ j 1.21

100MHz = 47.91 ؉ j 0.05

150MHz = 46.57 ؉ j 4.13

200MHz = 48.92 ؉ j 10.0

ENCODE = 105MSPS

DNL MIN = 0.244

DNL MAX = 0.306

8

2.0

1.5

1.0

0.5

0.0

7

6

5

4

3

2

؊0.5

؊1.0

1

0

0.1

1

10

100

1000

512

1024

1536

2048

2560 3072 3584 4096

FREQUENCY – MHz

OUTPUT CODES

TPC 9. Differential Nonlinearity

TPC 12. Voltage Standing Wave Ratio (VSWR)

*Gain flatness measurement is performed by

applying a constant voltage at the device input.

REV. 0

–9–

– Equivalent Circuits

AD10201

V

CC

V

CC

V

CC

17k⍀

8k⍀

Q1

NPN

ENCODE

100⍀

8k⍀

V

OUTPUT

REF

Test Circuit 1. Equivalent ENCODE Input

Test Circuit 3. Equivalent Voltage Reference Output

V

CC

V

CC

5k⍀

7k⍀

A

2

IN

50⍀

100⍀

DIGITAL

OUTPUT

A

1

IN

7k⍀

Test Circuit 2. Equivalent Digital Output

Test Circuit 4. Equivalent Analog Input

DEFINITION OF TERMS

Analog Bandwidth

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Output Propagation Delay

The delay between the 50% point of the rising edge of ENCODE

command and the time when all output data bits are within valid

logic levels.

Power Supply Rejection Ratio

Aperture Delay

The delay between the 50% point on the rising edge of the ENCODE

command and the instant at which the analog input is sampled.

The ratio of a change in output offset voltage to a change in

power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

The ratio of the rms signal amplitude (set at 1 dB below full-scale)

to the rms value of the sum of all other spectral components,

excluding the first six harmonics and dc. [May be reported in dBc

(i.e., degrades as signal levels are lowered) or in dBFS (always

related back to converter full-scale).]

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

ENCODE Pulsewidth/Duty Cycle

Signal-to-Noise Ratio (without Harmonics)

Pulsewidth high is the minimum amount of time that the

ENCODE pulse should be left in logic “1” state to achieve rated

performance; pulsewidth low is the minimum time ENCODE

pulse should be left in low state. At a given clock rate, these specs

define an acceptable ENCODE duty cycle.

The ratio of the rms signal amplitude (set at 1 dB below full-scale)

to the rms value of the sum of all other spectral components,

excluding the first six harmonics and dc. [May be reported in

dBc (i.e., degrades as signal levels are lowered) or in dBFS (always

related back to converter full-scale).]

Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the

worst harmonic component.

Spurious-Free Dynamic Range

The ratio of the rms signal amplitude to the rms value of the peak

spurious spectral component. The peak spurious component may

or may not be a harmonic. [May be reported in dBc (i.e., degrades

as signal levels is lowered) or in dBFS (always related back to

converter full-scale).]

Integral Nonlinearity

The deviation of the transfer function from a reference line measured

in fractions of 1 LSB using a “best straight line” determined by

a least square curve fit.

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value

of the worst third order intermodulation product; reported in dBc.

Minimum Conversion Rate

The ENCODE rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed limit.

Voltage Standing Wave Ratio (VSWR)

The ratio of the amplitude of the electric field at a voltage maximum

to that at an adjacent voltage minimum.

Maximum Conversion Rate

The ENCODE rate at which parametric testing is performed.

–10–

REV. 0

AD10201

APPLICATION NOTES

Theory of Operation

Often, the cleanest clock source is a crystal oscillator producing

a pure sine wave. In this configuration, or with any roughly sym-

metrical clock input, the input can be ac-coupled and biased to a

reference voltage that also provides the ENCODE. This ensures

that the reference voltage is centered on the encode signal.

The AD10201 is a high-dynamic-range dual 12-bit, 105 MHz sub-

range pipeline converter that uses switched capacitor architecture.

The analog input section uses A_INA2/B2 at 1.75 V p-p with an input

impedance of 50 Ω. The analog input includes an ac-coupled

wideband 1:1 transformer, which provides high dynamic range and

SNR while maintaining VSWR and gain flatness. The ADC includes

a high bandwidth linear track/hold that gives excellent spurious

performance up to and beyond the Nyquist rate. The high bandwidth

track/hold has a low jitter of 0.25 ps rms, leading to excellent SNR

and SFDR performance. AC-coupled differential PECL/ECL

encode inputs are recommended for optimum performance.

Digital Outputs

The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL/CMOS-

compatible for lower power consumption.

Analog Input

The analog input is a single-ended ac-coupled high performance

1:1 transformer with an input impedance of 50 Ω to 250 MHz.

The nominal full-scale input is 1.75 V p-p.

Special care was taken in the design of the analog input section

of the AD10201 to prevent damage and corruption of data when

the input is overdriven.

USING THE AD10201

ENCODE Input

Any high speed A/D converter is extremely sensitive to the quality

of the sampling clock provided by the user. A track/hold circuit

is essentially a mixer, and any noise, distortion, or timing jitter

on the clock will be combined with the desired signal at the A/D

output. For that reason, considerable care has been taken in the

design of the ENCODE input of the AD10201, and the user is

advised to give commensurate thought to the clock source. The

ENCODE inputs are fully TTL/CMOS compatible. For optimum

performance, the AD10201 must be clocked differentially. Note

that the ENCODE inputs cannot be driven directly from PECL

level signals (V_IHDis 3.5 V max). PECL level signals can easily

be accommodated by ac-coupling as shown in Figure 2. Good

performance is obtained using an MC10EL16 in the circuit to

drive the encode inputs.

Voltage Reference

A stable and accurate 2.5 V voltage reference is designed into the

AD10201 (V_REFOUT). An external voltage reference is not required.

Timing

The AD10201 provides latched data outputs, with 10 pipeline

delays. Data outputs are available one propagation delay (t_PD) after

the rising edge of the ENCODE command (see Figure 1). The

length of the output data lines and loads placed on them should

be minimized to reduce transients within the AD10201; these

transients can detract from the converter’s dynamic performance.

The minimum guaranteed conversion rate of the AD10201 is

10 MSPS. At internal clock rates below 10 MSPS dynamic perfor-

mance may degrade. Therefore, input clock rates below 10 MHz

should be avoided.

AD10201

0.1␮F

ENCODE

GROUNDING AND DECOUPLING

Analog and Digital Grounding

PECL

GATE

ENCODE

Proper grounding is essential in any high speed, high resolution

system. Multilayer printed circuit boards (PCBs) are recommended

to provide optimal grounding and power schemes. The use of

ground and power planes offers distinct advantages:

0.1␮F

510⍀

GND

Figure 2. AC-Coupling to ENCODE Inputs

ENCODE Voltage Level Definition

1. The minimization of the loop area encompassed by a signal

and its return path.

The voltage level definitions for driving ENCODE and ENCODE

in differential mode are shown in Figure 3 and Table II.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the powerplane,

PCB insulation, and ground plane.

ENCODE

V

IHD

V

ID

ICM

These characteristics result in both a reduction of electromagnetic

interference (EMI) and an overall improvement in performance.

ENCODE

V

ILD

It is important to design a layout that prevents noise from coupling

to the input signal. Digital signals should not be run in parallel

with input signal traces and should be routed away from the input

circuitry. The PCB should have a ground plane covering all unused

portions of the component side of the board to provide a low

impedance path and manage the power and ground currents. The

ground plane should be removed from the area near the input

pins to reduce stray capacitance.

Figure 3. Differential Input Levels

Table II. ENCODE Inputs

Description

Min

Nom

Max

Differential Signal

Amplitude (V_ID)

500 mV

750 mV

Differential Signal

Amplitude (V_ID)

5 V

Low Differential Input

Voltage (V_ILD

Common-Mode

Input (V_ICN

)

0 V

)

1.25 V

1.6 V

REV. 0

–11–

AD10201

Solder Reflow Profile

The solder reflow profile provided in Figure 4 is recommended.

It is recommended that high quality ceramic chip capacitors be used

to decouple each supply pin to ground directly at the device. All

capacitors can be standard high quality ceramic chip capacitors.

250

200

Care should be taken when placing the digital output runs. Because

the digital outputs have such a high slew rate, the capacitive loading

on the digital outputs should be minimized. Circuit traces for the

digital outputs should be kept short and connect directly to the

receiving gate. Internal circuitry buffers the outputs of the AD9432

ADC through a resistor network to eliminate the need to exter-

nally buffer the device from the receiving gate.

150

100

EVALUATION BOARD

The AD10201 evaluation board (Figures 6a–6f) is designed to

provide optimal performance for evaluation of the AD10201

analog-to-digital converter. The board encompasses everything

needed to ensure the highest level of performance for evaluating

the AD10201. The board requires an analog input signal, encode

clock, and power supply inputs. The clock is buffered on-board

to provide clocks for the latches. The digital outputs and out

clocks are available at the standard 40-pin connectors J1 and J2.

50

0

50

100

150

200

250

300

350

400

TIME – Seconds

Figure 4. Typical Solder Reflow Profile

LAYOUT INFORMATION

The schematic of the evaluation board (Figures 5a–5d) represents

a typical implementation of the AD10201. The pinout of the

AD10201 is very straightforward and facilitates ease of use and the

implementation of high-frequency/high resolution design practices.

Power to the analog supply pins is connected via banana jacks.

The analog supply powers the associated components and the

analog section of the AD10201. The digital outputs of the

AD10201 are powered via banana jacks with 3.3 V. Contact the

factory if additional layout or applications assistance is required.

BILL OF MATERIALS LIST FOR AD10201 EVALUATION BOARD

Quantity Reference Designator

Value

Description

Part Number

2

U16, U17

IC, Low Voltage 16-Bit D-Type Flip-Flop

with 5 V Tolerant Inputs and Outputs

IC, BGA 35 ꢁ 35 385

IC, Precision Low Dropout any CAP

Voltage Regulator

74LCX16374MTD

(Fairchild)

AD10201AB

ADP3330ART-3.3-RL7

(Analog)

1

2

U1

U14, U15

4

8

32

R38, R39, R56, R58

R1, R7, R8, R41, R60, R61, R71, R72 51 Ω

R3, R4, R9–R18, R23–R30, R35,

R36, R40, R42–R46, R63–R66

C1, C2, C5–C10, C12, C16–C18,

C20–C26, C28, C33–C35

C13, C27

J1, J2

L1, L2, L3, L4

U2, U3, U9, U11

33 kΩ

RES 33 kΩ 1/10W 0.1% 0805 SMD

RES 51 Ω 1/10W 5% 0805 SMD

RES 100 Ω 1/10W 1% 0805 SMD

ERA-6YEB333V (Panasonic)

ERJ-6GEYJ510V (Panasonic)

ERJ-6ENF1000V

(Panasonic)

ECJ-2VF1H104Z

(Panasonic)

100 Ω

23

0.1 µF CAP 0.1 µF 50 V Ceramic Y5V 0805

0.47 µF CAP 0.47 µF 25 V Ceramic Y5V 0805

2

4

ECJ-2YF1E474Z (Panasonic)

2 ꢁ 20 Male Connector Strip, 100 Centers TSW-120-08G-D (Samtec)

SMT Ferrite Bead

IC, 3.3 V/5 V ECL Differential

Receiver/Driver

47 Ω

2743019447 (Fair Rite)

MC10EP16D

(Motorola)

8

2

E3–E6, E25, E26, E33, E34

U4, U10

Power Jack, Banana Plug

3.3 V Dual Differential

108-0740-001 (Johnson Company)

SY100ELT23L

LVPECL-to-LVTTL Translator

Solid Tantalum Chip Capacitor,

10 µF, 16 V, 20%

(Micrel-Synergy)

T491C106M016AS

(KEMET)

10

8

C3, C4, C11, C14, C15, C19,

C29, C30–C32

J3–J7, J10–J12

10 µF

SMA PLUG 200Mil STR GOLD

142-0801-201

(Johnson Components Inc.)

4

1

2

4

Spacer Aluminum, Hex M–F (Standoff)

Nut Hex Stl #4-40 UNC-2B

GS03983 Rev. A (PCB)

CAP 0.047 µF 25 V Ceramic Y5V 0603

RES 0 Ω 1/16 W 5% 0402

AD10201/AD10226 Evaluation Board

C36, C37

JP3, JP6, JP8, JP12

ECJ-1VB1C473K

ER J-2GEOR00

0 Ω

–12–

REV. 0

AD10201

R18

100⍀

B11A MSB

B10A

B9A

DUT_3.3VDA

42

R17

U16

100⍀

VCC

R7

31

7

VCC

O15

O14

O13

O12

O11

O10

O9

R16

100⍀

3.3VDA

51⍀

25

24

26

27

29

30

32

33

35

36

48

1

37

38

40

41

43

44

46

47

28

34

39

45

J1

40

LATCHA

CP2

OE2

18

23

22

20

19

17

16

14

13

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

40

39

38

37

36

35

34

33

R40

100⍀

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

MSB D11A

D10A

D9A

I15

I14

I13

I12

I11

I10

I9

MSB B11A

B10A

B9A

2

3

4

5

6

7

8

B8A

C15

+

10␮F

R44

100⍀

D8A

D7A

D6A

D5A

16V

B8A

B7A

B6A

B7A

R45

100⍀

DGNDA

B5A

B4A

B6A

R71

51⍀

D4A

I8

O8

9

32

31

30

29

28

27

26

25

24

23

22

21

R46

100⍀

CP1

BUFLATA

10

11

12

13

14

15

16

17

18

19

20

OE1

I7

I6

I5

I4

I3

I2

I1

I0

GND

B5A

12

11

9

8

6

5

3

2

21

15

10

4

O7

O6

O5

O4

O3

O2

O1

O0

GND

D3A

D2A

D1A

R15

100⍀

B3A

B2A

B1A

B4A

R14

100⍀

LSB D0A

LSB B0A

B3A

R13

100⍀

B2A

R24

100⍀

B1A

R23

100⍀

DGNDA

B0A LSB

74LCX16374MTD

DGNDA

R11

100⍀

B11B MSB

B10B

B9B

DUT_3.3VDB

42

R10

100⍀

U17

VCC

R8

31

7

VCC

O15

O14

O13

O12

O11

O10

O9

R30

100⍀

3.3VDB

51⍀

25

24

26

27

29

30

32

33

35

36

48

1

37

38

40

41

43

44

46

47

28

34

39

45

J2

LATCHB

CP2

OE2

18

23

22

20

19

17

16

14

13

1

2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

R29

MSB D11B

D10B

D9B

I15

I14

I13

I12

I11

I10

I9

MSB B11B

100⍀

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

B10B

B9B

B8B

B7B

B6B

B5B

B4B

B8B

C14

10␮F

16V

+

R28

100⍀

D8B

D7B

D6B

D5B

B7B

R27

100⍀

DGNDB

B6B

R72

51⍀

D4B

I8

O8

9

R26

100⍀

CP1

BUFLATB

10

11

12

13

14

15

16

17

18

19

20

OE1

I7

I6

I5

I4

I3

I2

I1

I0

GND

B5B

12

11

9

8

6

5

3

2

21

15

10

4

O7

O6

O5

O4

O3

O2

O1

O0

GND

D3B

D2B

D1B

R12

100⍀

B3B

B2B

B1B

B4B

R9

100⍀

LSB D0B

LSB B0B

B3B

R25

100⍀

B2B

R36

100⍀

B1B

R35

100⍀

DGNDB

B0B LSB

74LCX16374MTD

DGNDB

Figure 5a. Evaluation Board Schematic

REV. 0

–13–

AD10201

E4

AGNDA

5VAA

L3

E6

1

2

J3

5VAA

A

A1

AINA1

IN

47⍀ @ 100MHz

C3

10␮F

16V

C11

+

JP1

C20

0.1␮F

10␮F

16V

STITCHESTOTIE GROUNDSTOGETHER

AGNDA

DGNDA

AGNDA

DGNDB

E78

E7

E10

E8

E77

E12

E9

E11

E2

DGNDB

AGNDA

AGNDB

E3

E5

E1

AGNDB

J4

L4

5VAB

A

A2

AINA2

AINB2

IN

1

2

5VAB

E42

E44

E48

E66

E67

E70

E72

E73

E76

E81

E41

E43

E47

E65

E68

E69

E71

E74

E75

E82

47⍀ @ 100MHz

AGNDA

J7

C4

C19

+

C21

0.1␮F

10␮F

16V

10␮F

16V

A

B2

IN

AGNDB

E34

E25

DGNDA

AGNDA

DGNDA

3.3VDA

L1

E29

E36

E38

E40

E45

E79

E84

E30

E35

E37

E39

E46

E80

E83

1

2

J6

DUT_3.3VDA

A

B1

AINB1

IN

47⍀ @ 100MHz

C29

C31

+

JP2

C12

10␮F

0.1␮F

16V

AGNDB

DGNDB

AGNDB

DGNDA

E33

E26

DGNDB

3.3VDB

L2

1

2

DUT_3.3VDB

47⍀ @ 100MHz

DUT_3.3VDA

DUT_3.3VDB

C18

5VAA

C30

C32

+

C16

0.1␮F

10␮F

C34

0.1␮F

C10

0.1␮F

C9

0.1␮F

C17

0.1␮F

16V

0.1␮F

DGNDB

AGNDA

DGNDA

DGNDB

Figure 5b. Evaluation Board Schematic

–14–

REV. 0

AD10201

3.3VA

U14

OUT

2

6

1

5

3

IN

5VAA

NR

SD

ERR

GND

4

AGNDA

C1

0.1␮F

C7

0.1␮F

J5

U2

ENCODE

ENCAB

ENCA

1

8

R56

33k⍀

R1

51⍀

NC

VCC

2

3

4

7

6

5

3.3VA

D

Q

AGNDA

D

Q

C8

0.1␮F

AGNDA

C13

VBB VEE

R42

100⍀

R43

100⍀

0.1␮F

MC10EP16D

25V

AGNDA

3.3VDA

U3

1

2

3

4

8

7

6

5

R58

33k⍀

NC

D

VCC

Q

3.3VDA

U4

3.3VDA

1

2

3

4

8

7

6

5

LATCHA

E23

D0

D1

VCC

Q

D

Q

C2

0.1␮F

VBB VEE

C6

0.1␮F

J12

E19

Q

R3

100⍀

R4

100⍀

MC10EP16D

ENCA

GND

BUFLATA

C5

0.1␮F

R41

51⍀

SY100EPT23L

DGNDA

AGNDA

DGNDA

AGNDA

DGNDA

3.3VB

U15

2

1

5

3

IN

OUT

NR

5VAB

6

SD

ERR

GND

4

AGNDB

C22

0.1␮F

C24

0.1␮F

J10

U11

ENCODE

ENCBB

ENCB

1

8

R38

33k⍀

R60

51⍀

NC

VCC

2

3

4

7

6

5

3.3VB

D

Q

AGNDB

D

Q

C28

0.1␮F

AGNDB

C27

0.47␮F

25V

VBB VEE

R63

100⍀

R64

100⍀

MC10EP16D

AGNDB

3.3VDB

U9

1

2

3

4

8

7

6

5

R39

33k⍀

NC

D

VCC

Q

3.3VDB

U10

VCC

3.3VDB

1

2

3

4

8

7

6

5

LATCHB

E24

D0

D1

D

Q

C23

0.1␮F

Q

VBB VEE

C25

0.1␮F

J11

E22

Q

R65

100⍀

R66

100⍀

MC10EP16D

ENCB

GND

BUFLATB

C26

0.1␮F

R61

51⍀

SY100EPT23L

DGNDB

AGNDB

DGNDB

AGNDB

DGNDB

Figure 5c. Evaluation Board Schematic

REV. 0

–15–

AD10201

C33

0.1␮F

E49

AGNDA

A1

A2

AGNDA

A3

A4

A5

AGNDA

A6

J1

J2

J3

J4

A10

B10

C10

D10

A9

5VAA

+5VAA

A12

B1

B2

B3

B4

B5

B6

B9

R1

R2

R3

R4

B12

C1

3.3VDA

DUT_3.3VDA

C2

C3

C4

A13

B13

C13

D13

K13

L13

M13

N13

P13

R13

T13

C5

SHEILD

C6

C9

C12

D1

D2

D3

D4

D5

D6

D9

D12

E1

P22

P23

P24

P25

3.3VDB

DUT_3.3VDB

+5VAB

E2

E3

E4

F1

A16

B16

C16

D16

A18

B18

C18

D18

F2

5VAB

F3

F4

G1

G2

G3

G4

H1

H2

A14

A15

A17

A21

A22

A23

A24

A25

B14

B15

B17

B21

B22

B23

B24

B25

C14

C15

C17

C21

C22

C23

C24

C25

D14

D15

D17

D21

D22

D23

D24

D25

E22

E23

E24

E25

F22

F23

F24

F25

G22

G23

G24

G25

H22

H23

H24

H25

K14

K15

K16

K22

K23

K24

K25

L14

L15

L16

M14

M15

M16

N14

N15

N16

N22

N23

N24

N25

P14

P15

P16

R14

R15

R16

T14

T15

T16

H3

AGNDB

H4

K1

+5VAA

K2

C36

K3

0.047␮F

K4

K10

K11

K12

L1

JP3

AGNDA

+5VAA

JP4

AGNDA

L2

L3

L4

AGNDA

+5VAA

L10

L11

L12

M10

M11

M12

N10

N11

N12

P1

AGNDA

AD10201

AGNDA

JP6

AGNDA

P2

P3

P4

AGNDA

P10

P11

P12

R10

R11

R12

T10

T11

T12

+5VAA

AGNDA

AA1

AA2

AA3

AA4

AB5

AB13

AC1

AC2

AC3

AC4

AC5

AC13

AD1

AD2

AD3

AD4

AD5

AD13

AE1

AE2

AE3

AE4

AE5

AE13

DGNDA

+5VAB

JP8

AGNDB

+5VAB

JP9

C37

0.047␮F

AGNDB

AA22

AA23

AA24

AA25

AB14

AB21

AC14

AC21

AC22

AC23

AC24

AC25

AD14

AD21

AD22

AD23

AD24

AD25

AE14

AE21

AE22

AE23

AE24

AE25

DGNDB

AGNDB

DGNDB

+5VAB

JP12

+5VAB

AGNDB

C35

0.1␮F

AGNDB

E50

Figure 5d. Evaluation Board Schematic

–16–

REV. 0

AD10201

J2

E5 +5VAB

E3

AGNDB

E33 DGNDB

C16

E26 +3.3VDB

E37

E30

E38

E29

C30

+

C4

L4

E1

E2

E35

E80

E46

E83

L2

+

E36

E79

E45

E84

C32

C19

+

J10

ENCB

E22

BUFLATB

LATCHB

E24

J11

E50

REF_B

J6

JP2

A

B2

IN

A

B1

E11

E39

IN

J7

E12

E77

GNDTIE

A

A1

GNDTIE

IN

E78

E7

J3

E49

E8

E47

REF_A

J1

JP1

J4

U1

GS03983 REV: A

AD10201/ AD10206

EVALUATION BOARD

A

A2

IN

BUFLATA

E19

E23

ENCA

J12

LATCHA

E82

E81

E66

E10

E42

E44

E67

E73

E72

E70

E76

ENCA

E65

E9

J5

C31

L3

+

C11

E41

E43

E68

E74

E71

E69

E75

+

L1

C29

+

C3

+

C12

DGNDA

AGNDA

+5V

AA

E4

E6

E34

E25

+3.3VDA

Figure 6a. Mechanical Layout Top View

Figure 6c. Top View

C14

R72

R61

U10

C23

U11

R60

C22

R39

C26

R38

C27

C17

R8

R66

R65

C25

U17

U9

U15

C18C28 C24

C21

C33

C37

C36

JP8

JP3

GNDTIE

+5V

GNDTIE

U16

C20

C8

C10

C7

R42

C15

C34

U3

C9

R7

R4

R3

U14

C1

R1

U2

C6

U4

R71

C5

Figure 6b. Mechanical Layout Bottom View

Figure 6d. Layer 2

REV. 0

–17–

AD10201

Figure 6f. Bottom View

Figure 6e. Layer 3

–18–

REV. 0

AD10201

OUTLINE DIMENSIONS

Dimensions shown in millimeters (mm).

385-Lead Ball Grid Array (BGA)

(B-385)

37.00

35.00 BSC SQ

33.00

24 22 20 18 16 14 12 10

25 23 21 19 17 15 13 11

8 6 4 2

7 5 3 1

DETAIL C

9

A

C

E

B

D

F

H

K

M

P

T

G

J

L

30.48 BSC

SQ

N

R

U

W

V

Y

AA

AC

AE

AB

AD

DETAIL A

1.27 TYP

DETAIL B

3.20

MAX

COMPONENT

VOLUME

1.15

1.02

0.89

0.90

0.75

0.60

0.75

0.60

0.50

DETAIL A

DETAIL B

DETAIL C

REV. 0

–19–

–20–


型号：	AD10201/PCB
厂家：	ADI
描述：	DUAL-CHANNEL, 12-BIT 105MSPS IF SAMPLING A/D CONVERTER 双通道， 12位105MSPS中频采样A / D转换器转换器
文件：	总20页 (文件大小：759K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD10201/PCB [ADI]

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