AD13280BF [ADI]
Dual-Channel, 12-Bit, 80 MSPS ADC with Analog Input Signal Conditioning; 双通道， 12位， 80 MSPS ADC模拟输入信号调理
| 型号： | AD13280BF |
| 厂家： | 
ADI |
| 描述： | Dual-Channel, 12-Bit, 80 MSPS ADC with Analog Input Signal Conditioning |
| 文件： | 总28页 (文件大小：1264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual-Channel, 12-Bit, 80 MSPS ADC
with Analog Input Signal Conditioning
AD13280
FEATURES
APPLICATIONS
Dual 80 MSPS, minimum sample rate
Channel-to-channel matching, 1ꢀ gain error
90 dB channel-to-channel isolation
DC-coupled signal conditioning
Radar processing (optimized for I/Q baseband operation)
Phased array receivers
Multichannel, multimode receivers
GPS antijamming receivers
80 dB spurious-free dynamic range
Selectable bipolar inputs ( 1 V and 0.ꢁ V ranges)
Integral single-pole, low-pass Nyquist filter
Twos complement output format
3.3 V compatible outputs
Communications receivers
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 80 MSPS.
2. Input signal conditioning; gain and impedance match.
3. Single-ended, differential, or off-module filter option.
4. Fully tested/characterized full channel performance.
1.8ꢁ W per channel
FUNCTIONAL BLOCK DIAGRAM
AMP-IN-B-2
AMP-IN-B-1
AMP-IN-A-1
AMP-IN-A-2
AMP-OUT-B
AMP-OUT-A
A–IN
B+IN
B–IN
A+IN
AD13280
DROUTA
D0A (LSB)
D1A
DROUTB
ENCODEB
ENCODEB
D2A
TIMING
D3A
VREF
DROUT
VREF
DROUT
D4A
D11B (MSB)
D10B
D5A
12
12
9
5
100Ω OUTPUT TERMINATORS
D6A
D7A
D8A
100Ω OUTPUT TERMINATORS
D9B
D8B
7
3
TIMING
D7B
D0B
(LSB)
ENCODEA ENCODEA
D1B D2B D3B D4B D5B D6B
D9A D10A D11A
(MSB)
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
AD13280
TABLE OF CONTENTS
Features .............................................................................................. 1
Input and Output Stages................................................................ 13
Theory of Operation ...................................................................... 14
Using the Single-Ended Input .................................................. 14
Using the Differential Input...................................................... 14
Applications Information.............................................................. 15
Encoding the AD13280 ............................................................. 15
Jitter Consideration.................................................................... 15
Power Supplies............................................................................ 16
Output Loading .......................................................................... 16
Evaluation Board ............................................................................ 17
Layout Information.................................................................... 17
Bill of Materials List for Evaluation Board.............................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Timing Diagram ........................................................................... 6
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels........................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 12
REVISION HISTORY
4/08—Rev. B to Rev. C
8/02—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 25
Edits to Specifications.......................................................................2
Changes to the Ordering Guide.................................................... 26
Packages Updated........................................................................... 19
11/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features and Product Highlights ............................... 1
Changes to General Description .................................................... 3
Changes to Table 1............................................................................ 4
Changes to Figure 3.......................................................................... 8
Changes to Theory of Operation.................................................. 14
Changes to Equation 1 ................................................................... 15
Changes to Table 5.......................................................................... 18
Changes to Figure 21...................................................................... 19
Changes to Figure 22...................................................................... 20
Changes to Figure 23...................................................................... 21
Changes to Figure 28 and Figure 29............................................. 24
Updated Outline Dimensions....................................................... 25
Changes to the Ordering Guide.................................................... 26
Rev. C | Page 2 of 28
AD13280
GENERAL DESCRIPTION
The AD13280 is a complete, dual-channel, signal processing
solution that includes on-board amplifiers, references, ADCs, and
output termination components to provide optimized system
performance. The AD13280 has on-chip track-and-hold circuitry
and uses an innovative multipass architecture to achieve 12-bit, 80
MSPS performance. The AD13280 uses innovative high density
circuit design and laser-trimmed thin-film resistor networks to
achieve exceptional channel matching, impedance control, and
performance while maintaining excellent isolation and
providing for significant board area savings.
signal ranges to further minimize additional external signal
conditioning, while remaining general purpose.
The AD13280 operates with 5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion and 3.3 V digital supply for the output stage. Each
channel is completely independent, allowing operation with
independent encode and analog inputs and maintaining
minimal crosstalk and interference.
The AD13280 is available in a 68-lead, ceramic gull wing package.
The components are manufactured using the Analog Devices, Inc.,
high speed complementary bipolar process (XFCB).
Multiple options are provided for driving the analog input,
including single-ended, differential, and optional series fil-
tering. The AD13280 also offers users a choice of analog input
Rev. C | Page 3 of 28
AD13280
SPECIFICATIONS
AVCC = +5 V, AVEE = −5 V, DVCC = +3.3 V; applies to each ADC with front-end amplifier, unless otherwise noted.
Table 1.
AD13280AZ
Parameter
Temperature
Test Level
Min
Typ
Max
Unit
RESOLUTION
DC ACCURACY1
No Missing Codes
Offset Error
12
Bits
Full
25°C
Full
Full
25°C
Full
25°C
Max
Min
IV
I
VI
VI
I
VI
I
VI
VI
Guaranteed
1.ꢀ
1.ꢀ
ꢀ.1
−1.ꢀ
2.ꢀ
ꢀ.5
1.ꢀ
1.ꢀ
−2.2
−2.2
−1.ꢀ
−3
−5.ꢀ
−1.5
−3.ꢀ
−5
+2.2
+2.2
+1.ꢀ
+1
+5.ꢀ
+1.5
+3.ꢀ
+5
% FS
% FS
%
% FS
% FS
%
Offset Error Channel Match
Gain Error2
Gain Error Channel Match
%
%
SINGLE-ENDED ANALOG INPUT
Input Voltage Range
AMP-IN-X-1
AMP-IN-X-2
Full
Full
V
V
ꢀ.5
1.ꢀ
V
V
Input Resistance
AMP-IN-X-1
AMP-IN-X-2
Capacitance
Analog Input Bandwidth3
DIFFERENTIAL ANALOG INPUT
Analog Signal Input Range
A+IN to A–IN and B+IN to B−IN4
Input Impedance
Analog Input Bandwidth
ENCODE INPUT (ENCODE, ENCODE)1
Differential Input Voltage
Differential Input Resistance
Differential Input Capacitance
SWITCHING PERFORMANCE
Maximum Conversion Rate5
Minimum Conversion Rate5
Aperture Delay (tA)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
ENCODE Pulse Width High at Max Conversion Rate
ENCODE Pulse Width Low at Max Conversion Rate
Output Delay (tOD)
Full
Full
25°C
Full
IV
IV
V
99
198
1ꢀꢀ
2ꢀꢀ
4.ꢀ
1ꢀ1
2ꢀ2
7.ꢀ
Ω
Ω
pF
MHz
V
143
Full
25°C
Full
V
V
V
1
618
5ꢀ
V
Ω
MHz
Full
25°C
25°C
IV
V
V
ꢀ.4
8ꢀ
V p-p
kΩ
pF
1ꢀ
2.5
Full
Full
VI
IV
V
IV
V
IV
IV
V
MSPS
MSPS
ns
ps
ps rms
ns
3ꢀ
25°C
25°C
25°C
25°C
25°C
Full
ꢀ.9
25ꢀ
ꢀ.3
6.25
6.25
5
5ꢀꢀ
4.75
4.75
8
8
ns
ns
Encode, Rising to Data Ready, Rising Delay
SNR1, 6
Full
V
8.5
ns
Analog Input @ 1ꢀ MHz
25°C
Min
Max
25°C
Min
Max
I
66.5
64.5
66.3
66.5
64
7ꢀ
7ꢀ
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
II
II
I
II
II
Analog Input @ 21 MHz
66.3
Rev. C | Page 4 of 28
AD13280
AD13280AZ
Parameter
Temperature
25°C
Min
Test Level
Min
63
61.5
63
Typ
Max
Unit
dBFS
dBFS
dBFS
Analog Input @ 37 MHz
I
II
II
65
Max
SINAD1, 7
Analog Input @ 10 MHz
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
I
66
63.5
66
64
63
64
54
53
54
69
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
II
II
I
II
II
I
Analog Input @ 21 MHz
Analog Input @ 37 MHz
68.5
59
II
II
SPURIOUS-FREE DYNAMIC RANGE1, 8
Analog Input @ 10 MHz
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
I
75
70
75
68
67
67
56
55
55
80
75
62
dBFS
dBFS
dBFS
II
II
I
II
II
I
Analog Input @ 21 MHz
Analog Input @ 37 MHz
II
II
SINGLE-ENDED ANALOG INPUT
Pass-Band Ripple to 10 MHz
Pass-Band Ripple to 25 MHz
25°C
25°C
V
V
0.07
0.12
dB
dB
DIFFERENTIAL ANALOG INPUT
Pass-Band Ripple to 10 MHz
Pass-Band Ripple to 25 MHz
25°C
25°C
V
V
0.3
0.82
dB
dB
TWO-TONE IMD REJECTION9
fIN = 9.1 MHz and 10.1 MHz (f1 and f2 are −7 dBFS)
25°C
Min
I
75
71
74
80
dBc
II
II
V
V
IV
V
Max
25°C
25°C
25°C
25°C
fIN = 19.1 MHz and 20.7 MHz (f1 and f2 are −7 dBFS)
fIN = 36 MHz and 37 MHz (f1 and f2 are −7 dBFS)
CHANNEL-TO-CHANNEL ISOLATION10
TRANSIENT RESPONSE
DIGITAL OUTPUTS11
Logic Compatibility
DVCC = 3.3 V
77
60
dBc
dBc
dB
90
25
ns
CMOS
Logic 1 Voltage
Logic 0 Voltage
Full
Full
I
I
2.5
DVCC − 0.2
0.2
V
V
0.5
DVCC = 5 V
Logic 1 Voltage
Logic 0 Voltage
Full
Full
V
V
DVCC − 0.3
0.35
V
V
Output Coding
Twos complement
POWER SUPPLY
AVCC Supply Voltage12
I (AVCC) Current
AVEE Supply Voltage12
I (AVEE) Current
DVCC Supply Voltage12
Full
Full
Full
Full
Full
IV
I
IV
I
4.85
5.0
5.25
364
−4.75
49
V
mA
V
mA
V
313
−5.0
38
−5.25
3.135
IV
3.3
3.465
Rev. C | Page 5 of 28
AD13280
AD13280AZ
Parameter
Temperature
Test Level
Min
Typ
34
375
3.7
Max
46
459
4.3
Unit
I (DVCC) Current
Full
Full
Full
Full
I
I
I
V
mA
mA
W
ICC (Total) Supply Current per Channel
Power Dissipation (Total)
Power Supply Rejection Ratio (PSRR)
0.01
% FSR/% VS
1
ENCODE
All ac specifications tested by driving ENCODE and
differentially. Single-ended input: AMP-IN-x-1 = 1 V p-p, AMP-IN-x-2 = GND.
2 Gain tests are performed on the AMP-IN-x-1 input voltage range.
3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4 For differential input: +IN = 1 V p-p and −IN = 1 V p-p (signals are 180 Ω out of phase). For single-ended input: +IN = 2 V p-p and –IN = GND.
5 Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% 5%.
6 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is
reported in dBFS, related back to converter full scale.
7 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is
reported in dBFS, related back to converter full scale.
8 Analog input signal at –1 dBFS; SFDR is the ratio of converter full scale to worst spur.
9 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product.
10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.
11 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrades performance.
12 Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AVCC = 5.0 V to 5.25 V.
TIMING DIAGRAM
tA
N + 3
N
A
IN
N + 1
N + 2
N + 4
tENC
tENCH
N+1
tENCL
ENCODE,
ENCODE
N
N+2
N+3
N + 4
tOD
tE_DR
D[11:0]
DRY
N – 3
N – 2
N – 1
N
Figure 2.
Rev. C | Page 6 of 28
AD13280
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
ELECTRICAL1
EXPLANATION OF TEST LEVELS
Ratings
I.
100% production tested.
AVCC Voltage
AVEE Voltage
DVCC Voltage
Analog Input Voltage
ꢀ V to 7 V
−7 V to ꢀ V
ꢀ V to 7 V
II.
100% production tested at 25°C, and sample tested
at specified temperatures. AC testing done on a
sample basis.
VEE to VCC
III.
IV.
Sample tested only.
Analog Input Current
−1ꢀ mA to +1ꢀ mA
ꢀ to VCC
4 V max
Digital Input Voltage (ENCODE)
ENCODE, ENCODE Differential Voltage
Digital Output Current
ENVIRONMENTAL1
Operating Temperature Range (Case)
Maximum Junction Temperature
Lead Temperature (Soldering, 1ꢀ sec)
Storage Temperature Range (Ambient)
Parameter guaranteed by design and characterization
testing.
−1ꢀ mA to +1ꢀ mA
V.
Parameter is a typical value only.
−4ꢀ°C to +85°C
175°C
3ꢀꢀ°C
VI.
100% production tested with temperature at 25°C, and
sample tested at temperature extremes.
−65°C to +15ꢀ°C
1 Typical thermal impedance for ES package: θJC 2.2°C/W; θJA 24.3°C/W.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 7 of 28
AD13280
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
61
AGNDB
43
42
41
40
39
DGNDB
D3B
62
63
AMP-IN-B-2
AMP-IN-B-1
D2B
AMP-OUT-B 64
B+IN 65
D1B
D0B (LSB)
66
67
68
1
B–IN
AGNDB
AGNDB
SHIELD
AGNDA
AGNDA
A–IN
38 NC
37
36
35
34
33
32
31
30
NC
DROUTB
SHIELD
DROUTA
D11A (MSB)
D10A
AD13280
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
2
3
4
5
A+IN
D9A
6
AMP-OUT-A
D8A
7
AMP-IN-A-1
AMP-IN-A-2
AGNDA
29 D7A
28 D6A
8
9
27
DGNDA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
NC = NO CONNECT
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 35
2, 3, 9, 1ꢀ, 13, 16
4
SHIELD
AGNDA
A−IN
Internal Ground Shield Between Channels.
A Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
Inverting Differential Input (Gain = +1).
5
A+IN
Noninverting Differential Input (Gain = +1).
6
7
8
AMP-OUT-A Single-Ended Amplifier Output (Gain = +2).
AMP-IN-A-1 Analog Input for A Side ADC (Nominally ꢀ.5 V).
AMP-IN-A-2 Analog Input for A Side ADC (Nominally 1.ꢀ V).
11
12
14
AVEEA
A Channel Analog Negative Supply Voltage (Nominally −5.ꢀ V or −5.2 V).
A Channel Analog Positive Supply Voltage (Nominally +5.ꢀ V).
Complement of ENCODEA. Differential input.
Encode Input. Conversion initiated on rising edge.
A Channel Digital Positive Supply Voltage (Nominally +5.ꢀ V/+3.3 V).
No Connect.
AVCCA
ENCODEA
ENCODEA
DVCCA
NC
15
17
18, 19, 37, 38
2ꢀ to 25, 28 to 33
DꢀA to
D11A
Digital Outputs for ADC A. Dꢀ (LSB).
26, 27
34
36
DGNDA
DROUTA
DROUTB
A Channel Digital Ground.
Data Ready A Output.
Data Ready B Output.
39 to 42, 45 to 52
DꢀB to
D11B
Digital Outputs for ADC B. Dꢀ (LSB).
43, 44
53
DGNDB
DVCCB
B Channel Digital Ground.
B Channel Digital Positive Supply Voltage (Nominally +5.ꢀ V/+3.3 V).
Rev. C | Page 8 of 28
AD13280
Pin No.
Mnemonic Description
B Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
54, 57, 6ꢀ, 61, 67, 68 AGNDB
55
56
58
59
62
63
64
65
66
ENCODEB
ENCODEB
AVCCB
Encode Input. Conversion initiated on rising edge.
Complement of ENCODEB. Differential input.
B Channel Analog Positive Supply Voltage (Nominally +5.ꢀ V).
B Channel Analog Negative Supply Voltage (Nominally −5.ꢀ V or −5.2 V).
AVEEB
AMP-IN-B-2 Analog Input for B Side ADC (Nominally 1.ꢀ V).
AMP-IN-B-1 Analog Input for B Side ADC (Nominally ꢀ.5 V).
AMP-OUT-B Single-Ended Amplifier Output (Gain = +2).
B+IN
B−IN
Noninverting Differential Input (Gain = +1).
Inverting Differential Input (Gain = +1).
Rev. C | Page 9 of 28
AD13280
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–10
–20
–30
–40
–50
–60
–70
–80
ENCODE = 80MSPS
ENCODE = 80MSPS
= 10MHz (–1dBFS)
–10
A
= 5MHz (–1dBFS)
A
IN
IN
–20
–30
–40
–50
–60
–70
–80
SNR = 69.4dBFS
SFDR = 81.9dBc
SNR = 69.19dBFS
SFDR = 79.55dBc
3
5
3
2
5
2
4
–90
–100
–110
–120
–130
6
–90
–100
–110
–120
–130
6
4
0
0
0
5
5
5
10
15
20
25
30
35
40
40
40
0
0
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Single Tone @ 5 MHz
Figure 7. Single Tone @ 10 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
ENCODE = 80MSPS
= 18MHz (–1dBFS)
ENCODE = 80MSPS
A = 37MHz (–1dBFS)
IN
SNR = 68.38dBFS
SFDR = 57.81dBc
A
IN
SNR = 69.79dBFS
SFDR = 76.81dBc
2
3
–70
–80
5
6
–90
–100
–110
–120
–130
–90
–100
–110
–120
–130
4
10
15
20
25
30
35
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Single Tone @ 18 MHz
Figure 8. Single Tone @ 37 MHz
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
ENCODE = 80MSPS
= 19MHz AND
ENCODE = 80MSPS
= 9MHz AND
A
A
IN
20MHz (–7dBFS)
SFDR = 74.41dBc
IN
10MHz (–7dBFS)
SFDR = 82.77dBc
–70
–80
–70
–80
–90
–100
–110
–120
–130
–90
–100
–110
–120
–130
5
10
15
20
25
30
35
40
10
15
20
25
30
35
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Two Tone @ 9 MHz and 10 MHz
Figure 9. Two Tone @ 19 MHz and 20 MHz
Rev. C | Page 1ꢀ of 28
AD13280
3
3.0
2.5
2.0
1.5
1.0
ENCODE = 80MSPS
DNL MAX = 0.688 CODES
DNL MIN = 0.385 CODES
ENCODE = 80MSPS
INL MAX = 0.562 CODES
INL MIN = 0.703 CODES
2
1
0
0.5
0
–1
–2
–3
–0.5
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Figure 10. Differential Nonlinearity
Figure 12. Integral Nonlinearity
0
–1
–2
–3
ENCODE = 80MSPS
ROLL-OFF = 0.0459dB
–4
–5
–6
–7
–8
–9
–10
1.0
3.5
6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0
FREQUENCY (MHz)
Figure 11. Pass-Band Ripple to 25 MHz
Rev. C | Page 11 of 28
AD13280
TERMINOLOGY
Analog Bandwidth
Minimum Conversion Rate
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Aperture Delay
The delay between a differential crossing of the ENCODEA
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
ENCODEA
signal and the
analog input is sampled.
signal and the instant at which the
Output Propagation Delay
The delay between a differential crossing of the ENCODEA
ENCODEA
signal and the
signal and the time at which all
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
output data bits are within valid logic levels.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically, and the
capacitance and differential input impedances are measured
with a network analyzer.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
Differential Analog Input Voltage Range
power supply voltage.
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage from the other
pin, which is 180 degrees out of phase. Peak-to-peak differential
is computed by rotating the input phase 180 degrees and taking
the peak measurement again. The difference is then computed
between both peak measurements.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc. SINAD can be
reported in dB (that is, degrades as signal level is lowered) or
in dBFS (always related back to converter full scale).
Signal-to-Noise Ratio (SNR) (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral com-
ponents, excluding the first five harmonics and dc. SNR can be
reported in dB (that is, degrades as signal level is lowered) or
in dBFS (always related back to converter full scale).
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
ENCODE Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in a Logic 1 state to achieve the
rated performance. Pulse width low is the minimum time the
ENCODE pulse should be left in a low state. At a given clock
rate, these specifications define an acceptable encode duty cycle.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of
the peak spurious spectral component. The peak spurious
component may or may not be a harmonic.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Transient Response
The time required for the converter to achieve 0.02% accuracy
when a one-half full-scale step function is applied to the analog
input.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product; reported in
dBc.
Rev. C | Page 12 of 28
AD13280
INPUT AND OUTPUT STAGES
LOADS
AV
AV
CC
AV
AV
CC
CC
CC
10kΩ
10kΩ
ENCODE
ENCODE
10kΩ
10kΩ
AMP-IN-X-2
100
Ω
AMP-IN-X-1
TOAD8045
100Ω
LOADS
Figure 15. ENCODE Inputs
Figure 13. Single-Ended Input Stage
DV
CC
DV
CC
CURRENT MIRROR
CURRENT MIRROR
DV
CC
DV
CC
V
V
REF
REF
100Ω
DROUT
D0–D11
CURRENT MIRROR
CURRENT MIRROR
Figure 14. DR Digital Output Stage
Figure 16. Digital Output Stage
Rev. C | Page 13 of 28
AD13280
THEORY OF OPERATION
The AD13280 is a high dynamic range 12-bit, 80 MHz pipeline
delay (three pipelines) analog-to-digital converter (ADC). The
custom analog input section provides input ranges of 1 V p-p
and 2 V p-p and input impedance configurations of 50 Ω, 100 Ω,
and 200 Ω.
USING THE SINGLE-ENDED INPUT
The AD13280 has been designed with user ease of operation in
mind. Multiple input configurations have been included on-
board to allow the user a choice of input signal levels and input
impedance. The standard inputs are 0.5 V and 1.0 V. The
user can select the input impedance of the AD13280 on any
input by using the other inputs as alternate locations for the
GND. The following is a summary of the impedance options
available at each input location:
The AD13280 employs four monolithic Analog Devices com-
ponents per channel (AD8045, AD8138, AD8031, and a custom
ADC IC), along with multiple passive resistor networks and
decoupling capacitors to fully integrate a complete 12-bit
analog-to-digital converter (ADC).
AMP-IN-x-1 = 100 Ω when AMP-IN-x-2 is open.
AMP-IN-x-1 = 50 Ω when AMP-IN-x-2 is shorted to GND.
AMP-IN-x-2 = 200 Ω when AMP-IN-x-1 is open.
In the single-ended input configuration, the input signal is passed
through a precision laser-trimmed resistor divider, allowing the
user to externally select operation with a full-scale signal of 0.5 V
or 1.0 V by choosing the proper input terminal for the applica-
tion. The result of the resistor divider is to apply a full-scale
input of approximately 0.4 V to the noninverting input of the
internal AD8045 amplifier.
Each channel has two analog inputs: AMP-IN-A-1 and
AMP-IN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use
AMP-IN-A-1 or AMP-IN-B-1 when an input of 0.5 V full
scale is desired. Use AMP-IN-A-2 or AMP-IN-B-2 when 1 V
full scale is desired. Each channel has an AMP-OUT that must
be tied to either a noninverting or inverting input of a
differential amplifier with the remaining input grounded. For
example, Side A, AMP-OUT-A (Pin 6) must be tied to A+IN
(Pin 5) with A−IN (Pin 4) tied to ground for noninverting
operation or AMP-OUT-A (Pin 6) tied to A−IN (Pin 4) with
A+IN (Pin 5) tied to ground for inverting operation.
The AD13280 analog input includes an AD8045 amplifier
featuring an innovative architecture that maximizes the dynamic
range capability on the amplifier inputs and outputs. The AD8045
amplifier provides a high input impedance and gain for driving the
AD8138 in a single-ended to differential amplifier configuration.
The AD8138 has a −3 dB bandwidth at 300 MHz and delivers a
differential signal with the lowest harmonic distortion available in
a differential amplifier. The AD8138 differential outputs help
balance the differential inputs to the custom ADC, maximizing
the performance of the device.
USING THE DIFFERENTIAL INPUT
Each channel of the AD13280 is designed with two optional
differential inputs, A+IN, A−IN and B+IN, B−IN. The inputs
provide system designers with the ability to bypass the AD8045
amplifier and drive the AD8138 directly. The AD8138 differen-
tial ADC driver can be deployed in either a single-ended or
differential input configuration. The differential analog inputs
have a nominal input impedance of 620 Ω and nominal full-
scale input range of 1.2 V p-p. The AD8138 amplifier drives a
differential filter and the custom analog-to-digital converter.
The differential input configuration provides the lowest even-
order harmonics and signal-to-noise (SNR) performance
improvement of up to 3 dB (SNR = 73 dBFS). Exceptional care
was taken in the layout of the differential input signal paths.
The differential input transmission line characteristics are
matched and balanced. Equal attention to system level signal
paths must be provided in order to realize significant perform-
ance improvements.
The AD8031 provides the buffer for the internal reference
analog-to-digital converter. The internal reference voltage of
the custom ADC is designed to track the offsets and drifts and
is used to ensure matching over an extended temperature range
of operation. The reference voltage is connected to the output
common-mode input on the AD8138. This reference voltage
sets the output common mode on the AD8138 at 2.4 V, which
is the midsupply level for the ADC.
AIN
The custom ADC has complementary analog input pins,
and AIN. Each analog input is centered at 2.4 V and should
AIN
swing 0.55 V around this reference. Because AIN and
are
180 degrees out of phase, the differential analog input signal is
2.2 V peak-to-peak. Both analog inputs are buffered prior to
the first track-and-hold.
The custom ADC digital outputs drive 100 Ω series resistors
(see Figure 16). The result is a 12-bit, parallel digital CMOS-
compatible word, coded as a twos complement.
Rev. C | Page 14 of 28
AD13280
APPLICATIONS INFORMATION
ENCODING THE AD13280
JITTER CONSIDERATION
The AD13280 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 12-bit accuracy at 80 MSPS places a premium on
encode clock phase noise. SNR performance can easily degrade
3 dB to 4 dB with 37 MHz input signals when using a high jitter
clock source. See Analog Devices Application Note AN-501,
Aperture Uncertainty and ADC System Performance, for com-
plete details. For optimum performance, the AD13280 must be
clocked differentially. The encode signal is usually ac-coupled
The signal-to-noise ratio for any ADC can be predicted. When
normalized to ADC codes, Equation 1 accurately predicts the
SNR based on three terms. These are jitter, average DNL error,
and thermal noise. Each of these terms contributes to the noise
within the converter.
1/2
2
2
⎡
⎢
⎣
⎤
⎥
V
⎛
⎞
1+ ε
⎡
⎤
NOISE rms
2
⎜
⎜
⎟
⎟
SNR = − 20× log
+
(
2×π × fANALOG × tJ rms
)
+
2N
2N
⎢
⎥
⎦
⎢⎣
⎥
⎦
⎝
⎠
(1)
ENCODE
into the ENCODE and
pins via a transformer or
where:
capacitors. These pins are biased internally and require no
additional bias.
f
ANALOG is the analog input frequency.
t
J rms is the rms jitter of the encode (rms sum of encode source
Figure 17 shows one preferred method for clocking the AD13280.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD13280 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD13280 and limits the
noise presented to the ENCODE inputs. A crystal clock
oscillator can also be used to drive the RF transformer if an
appropriate limited resistor (typically 100 Ω) is placed in series
with the primary.
and internal encode circuitry).
ε is the average DNL of the ADC (typically 0.50 LSB).
N is the number of bits in the ADC.
V
NOISE rms is the analog input of the ADC (typically 5 LSB).
For a 12-bit analog-to-digital converter like the AD13280,
aperture jitter can greatly affect the SNR performance as the
analog frequency is increased. The chart below shows a family
of curves that demonstrates the expected SNR performance of
the AD13280 as jitter increases. The chart is derived from
Equation 1.
For a complete discussion of aperture jitter, consult Analog
Devices Application Note AN-501, Aperture Uncertainty and
ADC System Performance.
0.1µF
T1-4T
100
Ω
CLOCK
SOURCE
ENCODE
AD13280
ENCODE
71
HSMS2812
DIODES
A
= 5MHz
IN
70
69
68
Figure 17. Crystal Clock Oscillator—Differential Encode
A
= 10MHz
IN
67
66
65
64
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter per-
formance is the MC100LVEL16 (or within the same family)
from Motorola.
A
= 20MHz
= 37MHz
IN
63
62
61
VT
60
59
58
A
IN
0.1µF
ENCODE
AD13280
ECL/PECL
CLOCK JITTER (ps)
ENCODE
0.1µF
Figure 19. SNR vs. Jitter
VT
Figure 18. Differential ECL for Encode
Rev. C | Page 15 of 28
AD13280
POWER SUPPLIES
OUTPUT LOADING
Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend
to have radiated components that may be received by the
AD13280. Each of the power supply pins should be decoupled
as close as possible to the package using 0.1 μF chip capacitors.
Care must be taken when designing the data receivers for the
AD13280. The digital outputs drive an internal series resistor
(for example, 100 Ω) followed by a gate like 75LCX574. To
minimize capacitive loading, there should be only one gate on
each output pin. An example of this is shown in the evaluation
board schematic (see Figure 20). The digital outputs of the
AD13280 have a constant output slew rate of 1 V/ns.
The AD13280 has separate digital and analog power supply
pins. The analog supplies are denoted AVCC, and the digital
supply pins are denoted DVCC. AVCC and DVCC should be
separate power supplies because the fast digital output swings
can couple switching current back into the analog supplies.
A typical CMOS gate combined with a PCB trace has a load of
approximately 10 pF. Therefore, as each bit switches, 10 mA
(10 pF × 1 V ÷ 1 ns) of dynamic current per bit flows in or out
of the device. A full-scale transition can cause up to 120 mA
(12 bits × 10 mA/bit) of transient current through the output
stages. These switching currents are confined between ground
and the DVCC pin. Standard TTL gates should be avoided
because they can appreciably add to the dynamic switching
currents of the AD13280. It should also be noted that extra
capacitive loading increases output timing and invalidates
timing specifications. Digital output timing is guaranteed with
10 pF loads.
Note that AVCC must be held within 5% of 5 V. The AD13280 is
specified for DVCC = 3.3 V because this is a common supply for
digital ASICs.
Rev. C | Page 16 of 28
AD13280
EVALUATION BOARD
The AD13280 evaluation board (see Figure 20) is designed to
provide optimal performance for evaluation of the AD13280
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD13280. The board requires an analog input signal, encode
clock, and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
LAYOUT INFORMATION
The schematics of the evaluation board (Figure 21, Figure 22,
and Figure 23) represent a typical implementation of the
AD13280. The pinout of the AD13280 is very straightforward
and facilitates ease of use and the implementation of high
frequency/high resolution design practices. It is recommended
that high quality ceramic chip capacitors be used to decouple
each supply pin to ground directly at the device. All capacitors
can be standard, high quality ceramic chip capacitors.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD13280. The digital outputs of the
AD13280 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
should connect directly to the receiving gate. Internal circuitry
buffers the outputs of the ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
Figure 20. Evaluation Board Mechanical Layout
Rev. C | Page 17 of 28
AD13280
J13
SMA
J6
SMA
E68
AGNDA
E67
AGNDB
E66
LIDA
J9
SMA
J8
SMA
J3
SMA
J14
SMA
AGNDB
AGNDA
E50
J4
E53
J7
SMA
SMA
E51
E54
AGNDB
AGNDB
AGNDA
E49
E70
E52
E85
E69
AGNDA
E86
AGNDB
AGNDA
AGNDA
10
AGNDB
–5VAB
C33
0.1µF
–5VAA
C9
0.1µF
60
AGNDB
AGNDA
AGNDB
AGNDA
11
12
59
58
AV
AV
A
A
AV
AV
B
B
EE
EE
AGNDB
AGENDA
+5VAA
+5VAB
C38
0.1µF
CC
CC
13
14
57
56
C17
0.1µF
C34
0.1µF
C35
0.1µF
AGNDB
AGNDA
AGNDB
ENCODEB
ENCODEB
AGNDB
AGNDA
ENCODEA
ENCODEA
AGNDA
ENCODEA
ENCODEA
AGNDA
ENCODEB
ENCODEB
AGNDB
15
16
17
18
19
20
21
22
23
24
25
26
55
54
53
52
51
50
49
48
47
46
45
44
AGNDA
OUT_3.3VDA
AGNDB
OUT_3.3VDB
U1
DV
CC
B
DV
CC
A
C18
0.1µF
C37
0.1µF
C36
0.1µF
C10
0.1µF
AD13280AZ
D11B(MSB)
D10B
D9B
D11B
D10B
D9B
D8B
D7B
D6B
D5B
NC0A
NC1A
NC
NC
D0A(LSB)
D1A
D0A
D1A
DGNDB
DGNDA
D8B
D2A
D2A
D7B
D3A
D3A
D6B
D4A
D4A
D5B
D5A
D5A
D4B
D4B
DGNDA
DGNDA
DGNDB
DGNDB
NC = NO CONNECT
DRAOUT
DRBOUT
E56
E55
LIDB
E48
E65
E40
DGNDB
DGNDA
47Ω
±20%
@100MHz
47Ω
±20%
@100MHz
47Ω
±20%
@100MHz
+3VDA
1
+3VAA
BJ6
–5VAA
BJ2
BJ10
+5VAA
DUT_3.3VDA
–5VAA
U7
L1
L3
1
C3
10µF
U1
C20
L5
1
C11
10µF
U1
C32
C12
C29
10µF
0.1µF
0.1µF
0.1µF
AGNDA
AGNDA
AGNDA
AGNDA
DGNDA
47Ω
±20%
@100MHz
47Ω
±20%
@100MHz
47Ω
±20%
@100MHz
+3VDB
+5VAB
BJ5
–5VAB
BJ1
BJ9
DUT_3.3VDB
+5VAB
–5VAB
1
U8
L2
L4
1
C4
10µF
U1
L6
1
C19
10µF
U1
C30
C16
C21
C31
10µF 0.1µF
0.1µF
0.1µF
AGNDB
AGNDB
AGNDB
AGNDB
DGNDB
Figure 21. Evaluation Board
Rev. C | Page 18 of 28
AD13280
U8
R47
0Ω
LE2 OE2
DGNDA
R18, DNI
R17, DNI
J1
H40DM
24
23
22
21
25
26
27
28
115
114
O15
O14
F0A
F1A
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
3.3VDA
R48
0Ω
DGNDA
DGNDA
GND GND
(MSB) B11A
B10A
R16, DNI
R40, DNI
3
F2A
F3A
NC0A
NC1A
C15
10µF
113
112
VCC
111
110
O13
O12
VCC
O11
O10
20
19
18
17
16
15
14
29
30
31
32
33
34
35
DGNDA
4
B9A
5
DUT_3.3VDA
DGNDA
DUT_3.3VDA
(LSB) D0A
D1A
B8A
DGNDA
R44, 100Ω
R45, 100Ω
6
B0A (LSB)
B1A
B7A
7
B6A
B5A
8
DGNDA
D2A
GND GND
9
R5
R46, 100Ω
R15, 100Ω
R14, 100Ω
R13, 100Ω
B4A
50Ω
B2A
B3A
B4A
B5A
19
O9
E61
E60
10
11
12
13
14
15
16
17
18
19
20
D3A
18
17
16
O8
O7
O6
E59
13
12
11
36
37
38
39
D4A
B3A
B2A
D5A
GND GND
DGNDA
D6A
DGNDA
B1A
R24, 100Ω
R23, 100Ω
10
9
B6A
B7A
15
14
O5
O4
(LSB) B0A
F3A
40
41
42
43
D7A
8
F2A
DUT_3.3VDA
DGNDA
DUT_3.3VDA
D8A
VCC VCC
R22, 100Ω
R21, 100Ω
7
F1A
F0A
13
12
O3
O2
B8A
B9A
6
D9A
DGNDA
5
4
3
44
45
46
DGNDA
GND GND
R20, 100Ω
R19, 100Ω
11
10
O1
O0
B10A
D10A
DGNDA
(MSB) D11A
B11A (MSB)
2
1
47
48
LE1 OE1
DGNDA
R7
74LCX16374
50Ω
LATCHB
E58
U7
R49
0Ω
LE2 OE2
DGNDB
DGNDB
R11, DNI
R10, DNI
J2
H40DN
24
23
22
21
25
26
27
115
114
O15
O14
F0B
F1B
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
3.3VDB
R50
0Ω
DGNDB
GND GND
(MSB) B11B
B10B
R30, DNI
R29, DNI
28
3
F2B
F3B
NC0B
NC1B
C14
10µF
113
112
O13
O12
20
19
18
17
16
15
14
29
30
31
32
33
34
35
DGNDB
4
B9B
5
DUT_3.3VDB
(LSB) D0B
D1B
VCC VCC
DUT_3.3VDB
DGNDB
B8B
DGNDB
R28, 100Ω
R27, 100Ω
6
B0B (LSB)
B1B
B7B
111
110
O11
O10
7
B6B
B5B
8
DGNDB
D2B
GND GND
9
R2
R26, 100Ω
R12, 100Ω
R9, 100Ω
R25, 100Ω
B4B
50Ω
B2B
B3B
B4B
B5B
19
O9
E64
E63
10
11
12
13
14
15
16
17
18
19
20
D3B
18
17
16
O8
O7
O6
E62
13
12
11
36
37
38
39
D4B
B3B
B2B
D5B
GND GND
DGNDB
D6B
DGNDB
B1B
R36, 100Ω
R35, 100Ω
10
9
B6B
B7B
15
14
O5
O4
(LSB) B0B
F3B
40
41
42
43
D7B
8
F2B
DUT_3.3VDB
D8B
VCC VCC
DUT_3.3VDB
DGNDB
R34, 100Ω
R33, 100Ω
7
F1B
F0B
13
12
O3
O2
B8B
B9B
6
D9B
DGNDB
5
4
3
44
45
46
DGNDB
GND GND
R32, 100Ω
R31, 100Ω
11
10
O1
O0
B10B
D10B
DGNDB
(MSB) D11B
B11B (MSB)
2
1
47
48
LE1 OE1
DGNDB
R8
50Ω
LATCHB
E57
74LCX16374
Figure 22. Evaluation Board
Rev. C | Page 19 of 28
AD13280
5
NR
3
1
OUT
ADP3330
ERR
2
6
U5
IN
+5VAA
SD
GND
4
AGNDA
+3.3VA
AGNDA
R42
100Ω
C13
J5
ENCODE
SMA
0.47µF
8
7
C7
0.1µF
C1
0.1µF
1
NC
VCC
BJ3
AGNDB
2
3
ENCODEA
ENCODEA
1
D
Q
QB
U2
6
5
DB
BJ4
R1
50Ω
4
AGNDA
DGNDB
C8
0.1µF
AGNDA
R43
100Ω
1
VBB
VEE
AGNDA
BJ7
AGNDA
MC10EP16
NC = NO CONNECT
1
AGNDA
DGNDB
BJ8
R56
33kΩ
DGNDA
R55
DGNDA
J12
DGNDA
C2
C6
1
SMA
33kΩ
0.1µF
0.1µF
DGND
C5
0.1µF
DGNDA
1
8
R3
100Ω
+3.3VDA
R41
25Ω
NC
VCC
Q
1
8
2
3
4
7
6
E15 E16
E7 E12
+3.3VDA
D
D0
D0
D1
VCC
U3
LATCHA
E23
2
3
4
7
6
5
QB
DB
Q0
Q1
U4
5
AGNDA
R4
100Ω
DGNDA
AGNDB
DGNDB
E19
BUFLATA
VBB
VEE
DGNDA
D1
GND
MC10EP16
NC = NO CONNECT
E11
E39 E47
E8
DGNDA
DGNDA
MC100EPT23
NC = NO CONNECT
AGNDA
5
E17 E18
E27 E28
E25 E26
E21 E20
E32 E31
E44 E43
E42 E41
NR
3
1
OUT
ERR
ADP3330
2
6
U6
IN
+5VAB
SD
GND
4
E10
E9
E33 E34
AGNDB
AGNDB
E6
E5
R52
100Ω
C27
J10
0.47µF
DGNDA
AGNDA
8
7
C24
0.1µF
1
ENCODE
SMA
C22
0.1µF
+3.3VB
NC
VCC
2
3
ENCODEB
D
Q
QB
U11
E38 E37
E29 E30
6
5
DB
ENCODEB
R54
4
50Ω
C28
0.1µF
AGNDB
E1
E2
R51
100Ω
VBB
VEE
E36 E35
E14 E13
E45 E46
AGNDB
AGNDB
MC10EP16
NC = NO CONNECT
AGNDB
E3
E4
AGNDB
SO1 SO4
R38
33kΩ
DGNDB
R39
DGNDB
J11
DGNDB
C23
C25
SMA
33kΩ
0.1µF
0.1µF
DGNDB
C26
0.1µF
SO5
SO6
SO2
SO3
1
8
R37
100Ω
+3.3VDB
R53
25Ω
NC
VCC
Q
1
8
2
3
4
7
6
+3.3VDA
D
D0
D0
D1
VCC
U9
LATCHB
2
3
4
7
6
QB
DB
Q0
Q1
E24
U10
5
AGNDB
R6
100Ω
E22
BUFLATB
VBB
VEE
5
DGNDB
D1
GND
MC10EP16
NC = NO CONNECT
DGNDB
DGNDB
MC100EPT23
NC = NO CONNECT
Figure 23. Evaluation Board
Rev. C | Page 2ꢀ of 28
AD13280
Figure 24. Top Silk
Figure 25. Top Layer
Rev. C | Page 21 of 28
AD13280
Figure 26. GND1
Figure 27. GND2
Rev. C | Page 22 of 28
AD13280
Figure 28. Bottom Silk
Figure 29. Bottom Layer
Rev. C | Page 23 of 28
AD13280
BILL OF MATERIALS LIST FOR EVALUATION BOARD
Table 4.
Component
Qty Name
Reference
Value
Description
Latch
AD1328ꢀ
Manufacturing Part Number
74LCX16374MTD (Fairchild)
AD1328ꢀAZ
2
1
2
1ꢀ
2
74LCX16374MTD
U7, U8
U1
U5, U6
BJ1 to BJ1ꢀ
R41, R53
R38, R39, R55, R56
C1, C2, C5 to C1ꢀ,
C12, C16 to C18,
C2ꢀ to C26, C28,
C31 to C38
C13, C27
AD1328ꢀAZ
ADP333ꢀ
BJACK
BRESꢀ8ꢀ5
BRESꢀ8ꢀ5
CAP2
Regulator
ADP333ꢀART-3.3RL7
Banana jacks
ꢀ8ꢀ5 SM resistor
ꢀ8ꢀ5 SM resistor
ꢀ8ꢀ5 SM capacitor
1ꢀ8-ꢀ74ꢀ-ꢀꢀ1 (Johnson Components)
ERJ-6GEYJ 24ꢀV (Panasonic)
ERJ-6GEYJ 333V (Panasonic)
GRM 4ꢀX7R1ꢀ4Kꢀ25BL
25 Ω
33 kΩ
ꢀ.1 μF
4
28
2
2
6
4
2
8
CAP2
H4ꢀDM
IND2
MC1ꢀEP16
MC1ꢀꢀEPT23
POLCAP2
ꢀ.47 μF
47 Ω
ꢀ8ꢀ5 SM capacitor
2 × 2ꢀ, 4ꢀ-pin male connector TSW-12ꢀ-ꢀ8-G-D
SM inductor
Clock drivers
ECL/TTL clock drivers
Tantalum polar capacitor
VJ12ꢀ6U474MFXMB (Vishay)
J1, J2
L1 to L6
2743ꢀ19447
U2, U3, U9, U11
U4, U1ꢀ
C3, C4, C11, C14,
C15, C19, C29, C3ꢀ
R47 to R5ꢀ
MC1ꢀEP16D (ON Semiconductor)
SY1ꢀꢀEP23L (ON Semiconductor)
T491C1ꢀ6Mꢀ16AT (Kemet)
1ꢀ μF
4
6
32
RES2
RES2
RES2
ꢀ Ω
5ꢀ Ω
1ꢀꢀ Ω
ꢀ8ꢀ5 SM resistor
ꢀ8ꢀ5 SM resistor
ꢀ8ꢀ5 SM resistor
ERJ-6GEY OR ꢀꢀV (Panasonic)
ERJ-6GEYJ 51ꢀV (Panasonic)
ERJ-6GEYJ 1ꢀ1V (Panasonic)
R1, R2, R5, R7, R8, R54
R3, R4, R6, R9, R12 to
R15, R19 to R28, R31
to R37, R42, R43, R44
to R46, R51, R52
12
4
4
SMA
J3 to J14
SMA connectors
Standoff
Screws (standoff)
AD1328ꢀ evaluation board
142-ꢀ7ꢀ1-2ꢀ1
Standoff
Screws
PCB
313-2477-ꢀ16 (Johnson Components)
MPMS ꢀꢀ4 ꢀꢀꢀ5 PH (Building Fasteners)
GSꢀ3361
1
Rev. C | Page 24 of 28
AD13280
OUTLINE DIMENSIONS
2.00 (50.80)
TYP
0.035 (0.889)
MAX
0.350
(8.89)
TYP
0.040 (1.02)
× 45°
DETAIL A
PIN 1
TOE DOWN
ANGLE
0–8 DEGREES
0.960 (24.38)
0.800 (20.32)
BSC
0.010 (0.254)
0.950 (24.13) SQ
0.940 (23.88)
TOP VIEW
(PINS DOWN)
30°
0.050 (1.27)
0.020 (0.508)
DETAIL A
ROTATED 90° CCW
0.040
(1.02) R
TYP
0.015 (0.30)
× 45°
3 PLS
0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
0.235 (5.97)
MAX
0.020 (0.508)
0.017 (0.432)
0.014 (0.356)
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 30. 68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar [CLCC]
(ES-68-1)
Dimensions shown in inches and (millimeters)
0.235 (5.97)
0.960 (24.38)
MAX
0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
0.950 (24.13) SQ
0.940 (23.88)
9
61
10
60
PIN 1
TOP VIEW
(PINS DOWN)
1.190 (30.23)
1.180 (29.97) SQ
1.170 (29.72)
1.070
(27.18)
MIN
0.800
(20.32)
BSC
TOE DOWN
ANGLE
0–8 DEGREES
0.010 (0.254)
26
44
30°
27
43
0.050 (1.27)
0.020 (0.508)
DETAIL A
0.060 (1.52)
0.050 (1.27)
0.040 (1.02)
DETAIL A
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.020 (0.508)
0.017 (0.432)
0.014 (0.356)
0.175 (4.45)
MAX
ROTATED 90° CCW
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 31. 68-Lead Ceramic Leaded Chip Carrier [CLCC]
(ES-68-C)
Dimensions shown in inches and (millimeters)
Rev. C | Page 25 of 28
AD13280
ORDERING GUIDE
Model
Temperature Range1 Package Description
Package Option
ES-68-C
ES-68-1
AD1328ꢀAZ2
AD1328ꢀAF
AD1328ꢀ/PCB
−25°C to +85°C
−25°C to +85°C
68-Lead Ceramic Leaded Chip Carrier [CLCC]
68-Lead Ceramic Leaded Chip Carrier with Nonconductive Tie-Bar [CLCC]
Evaluation Board with AD1328ꢀAZ
1 Referenced temperature is case temperature.
2 Z is a package indicator; the part is not RoHS compliant.
Rev. C | Page 26 of 28
AD13280
NOTES
Rev. C | Page 27 of 28
AD13280
NOTES
©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02386–0–4/08(C)
Rev. C | Page 28 of 28
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