AD1854 [ADI]
Stereo, 96 kHz, Multibit DAC; 立体声， 96千赫，多位DAC
| 型号： | AD1854 |
| 厂家： | 
ADI |
| 描述： | Stereo, 96 kHz, Multibit DAC |
| 文件： | 总12页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Stereo, 96 kHz, Multibit ꢀꢁ DAC
AD1854
PRODUCT OVERVIEW
FEATURES
The AD1854 is a high performance, single-chip stereo, audio
DAC delivering 113 dB Dynamic Range and 112 dB SNR
(A-weighted—not muted) at 48 kHz sample rate. It is comprised
of a multibit sigma-delta modulator with dither, continuous
time analog filters and analog output drive circuitry. Other features
include an on-chip stereo attenuator and mute, programmed
through an SPI-compatible serial control port. The AD1854
is fully compatible with current DVD formats, including 96 kHz
sample frequency and 24 bits. It is also backwards compatible
by supporting 50 µs/15 µs digital de-emphasis intended for
“redbook” 44.1 kHz sample frequency playback from com-
pact discs.
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Differential Output for Optimum Performance
113 dB Dynamic Range at 48 kHz Sample Rate
(AD1854KRS)
112 dB Signal-to-Noise at 48 kHz Sample Rate
(AD1854KRS)
–101 THD+N (AD1854KRS)
The AD1854 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The AD1854 can be configured in left-justified, I2S, and right-
justified. The AD1854 accepts serial audio data in MSB first,
twos-complement format. A power-down mode is offered to mini-
mize power consumption when the device is inactive. The AD1854
operates from a single 5 V power supply. It is fabricated on a single
monolithic integrated circuit and housed in a 28-lead SSOP
package for operation over the temperature range 0°C to 70°C.
On-Chip Volume Control with 1024 Steps
Hardware and Software Controllable Clickless Mute
Zero Input Flag Outputs for Left and Right Channels
Digital De-Emphasis Processing
Supports 256 ꢂ FS or 384 ꢂ FS Master Mode Clock
Switchable Clock Doubler
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, and I2S-Compatible
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Set-Top Boxes, Home Theater Systems,
Automotive Audio Systems, Sampling Musical
Keyboards, Digital Mixing Consoles, Digital Audio
Effects Processors
FUNCTIONAL BLOCK DIAGRAM
96/48F
CLOCK
DIGITAL CLOCK
CONTROL DATA
INPUT
S
SUPPLY
IN
VOLUME
MUTE
2
3
CLOCK
CIRCUIT
SERIAL CONTROL
INTERFACE
VOLTAGE
REFERENCE
AD1854
8 ꢂ F
INTERPOLATOR
MULTIBIT SIGMA-
S
OUTPUT
BUFFER
ATTEN/
MUTE
DAC
DAC
DELTA MODULATOR
SERIAL
DATA
INTERFACE
16-/18-/20-/24-BIT
DIGITAL
ANALOG
OUTPUTS
8 ꢂ F
DATA INPUT
OUTPUT
BUFFER
MULTIBIT SIGMA-
DELTA MODULATOR
S
ATTEN/
MUTE
INTERPOLATOR
2
SERIAL
MODE
2
2
PD/RST
MUTE
DE-EMPHASIS
ANALOG
SUPPLY
ZERO
FLAG
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD1854–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD
Ambient Temperature
Input Clock
)
5.0 V
25°C
12.288 MHz (256 × FS Mode)
Input Signal
1.0013 kHz
–0.5 dB Full Scale
48 kHz
Input Sample Rate
Measurement Bandwidth
Word Width
20 Hz to 20 kHz
20 Bits
Load Capacitance
Load Impedance
Input Voltage HI
Input Voltage LO
100 pF
47 kΩ
2.4 V
0.8 V
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ANALOG PERFORMANCE
Min
Typ
Max
Unit
Resolution
20
Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (AD1854JRS)
No Filter (AD1854KRS)
With A-Weighted Filter (AD1854JRS)
With A-Weighted Filter (AD1854KRS)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (AD1854JRS)
105
110
108
112
dB
dB
dB
dB
105
110
108
113
–97
–101
–89
dB
dB
dB
dB
dB
dB
dB
No Filter (AD1854KRS)
106
With A-Weighted Filter (AD1854JRS)
With A-Weighted Filter (AD1854KRS)
Total Harmonic Distortion + Noise (AD1854JRS) VO = 0 dB
Total Harmonic Distortion + Noise (AD1854KRS) VO = 0 dB
Total Harmonic Distortion + Noise (AD1854JRS and
AD1854KRS) VO = –20 dB
108
–88
–94
Total Harmonic Distortion + Noise (AD1854JRS and
AD1854KRS) VO = –60 dB
–49
dB
Analog Outputs
Differential Output Range ( Full Scale)
Output Impedance at Each Output Pin
Output Capacitance at Each Output Pin
Out-of-Band Energy (0.5 × FS to 100 kHz)
CMOUT
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
5.6
<200
V p-p
Ω
pF
dB
V
20
–72.5
2.25
3.0
–11.0
–0.15
+11.0
+0.15
300
%
dB
ppm/°C
dB
Degrees
dB
200
–120
0.1
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Mute Attenuation
–100
De-Emphasis Gain Error
0.1
dB
DIGITAL I/O (0ꢃC to 70ꢃC)
Min
Typ
Max
Unit
Input Voltage HI (VIH)
Input Voltage LO (VIL)
2.2
V
V
0.8
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 1 mA
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
Input Capacitance
2.0
V
V
µA
µA
pF
0.4
10
10
20
–2–
REV. A
AD1854
POWER
Min
Typ
Max
Unit
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current—Power-Down
Digital Current
Digital Current—Power-Down
Dissipation
4.5
26
26
14
1.5
5
5.5
35
33.5
20
V
30
29
17
2.5
mA
mA
mA
mA
5.5
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
Power-Down—Both Supplies
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
250
150
100
mW
mW
mW
mW
190
–60
–50
dB
dB
TEMPERATURE RANGE
Min
Typ
Max
Unit
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
0
–55
70
+125
DIGITAL TIMING (Guaranteed over 0ꢃC to 70ꢃC, AVDD = DVDD = 5.0 V ꢄ 10%)
Min
Max
Unit
tDMP
tDMP
tDMP
tDML
tDMH
tDBH
tDBL
tDBP
tDLS
tDLH
tDDS
tDDH
tPDRP
MCLK Period (512 FS Mode)
MCLK Period (384 FS Mode)
MCLK Period (256 FS Mode)
MCLK LO Pulsewidth (All Mode)
MCLK HI Pulsewidth (All Mode)
BCLK HI Pulsewidth
BCLK LO Pulsewidth
BCLK Period
L/RCLK Setup
L/RCLK Hold (DSP Serial Port Mode Only)
SDATA Setup
35
48
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.4 × tDMP
0.4 × tDMP
20
20
140
20
5
5
10
SDATA Hold
PD/RST LO Pulsewidth
4 MCLK Periods
DIGITAL FILTER CHARACTERISTICS
Min
Typ
Max
Unit
Passband Ripple
Stopband Attenuation
Passband
Stopband
Group Delay
0.04
47
0.448
0.552
106/FS
0
dB
dB
FS
FS
sec
µs
Group Delay Variation
Specifications subject to change without notice.
REV. A
–3–
AD1854
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Min
Max
Unit
DVDD to DGND
AVDD to AGND
Digital Inputs
Analog Outputs
AGND to DGND
Reference Voltage
Soldering
–0.3
–0.3
DGND – 0.3
AGND – 0.3
–0.3
+6
+6
V
V
V
V
V
1
2
DGND
MCLK
28 DVDD
27
26
SDATA
BCLK
DVDD + 0.3
AVDD + 0.3
+0.3
(AVDD + 0.3)/2
300
CLATCH
CCLK
3
4
25 L/RCLK
CDATA
5
24
23
22
21
PD/RST
MUTE
6
384/256
X2MCLK
ZEROR
DEEMP
96/48
AD1854
TOP VIEW
(Not to Scale)
°C
sec
7
ZEROL
IDPM0
10
8
9
20 IDPM1
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
10
FILTB
AVDD
OUTL+
OUTL–
AGND
19
18
17
16
15
AGND 11
12
OUTR+
13
OUTR–
14
FILTR
PACKAGE CHARACTERISTICS
Min
Typ
Max
Unit
θ
θ
JA (Thermal Resistance
[Junction-to-Ambient])
JC (Thermal Resistance
[Junction-to-Case])
109
°C/W
39
°C/W
ORDERING GUIDE
Model
Temperature
Package Description
Package Option
AD1854JRS
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
28-Lead Shrink Small Outline
28-Lead Shrink Small Outline
28-Lead Shrink Small Outline
28-Lead Shrink Small Outline
RS-28
RS-28 on 13" Reels
RS-28
AD1854JRSRL
AD1854KRS
AD1854KRSRL
RS-28 on 13" Reels
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1854 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD1854
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Pin Name
Description
1
2
I
I
DGND
MCLK
Digital Ground.
Master Clock Input. Connect to an external clock source at either 256, 384
or 512 FS.
3
4
I
I
CLATCH
CCLK
Latch input for control data. This input is rising-edge sensitive.
Control clock input for control data. Control input data must be valid on the
rising edge of CCLK. CCLK may be continuous or gated.
5
6
I
I
CDATA
Serial control input, MSB first, containing 16 bits of unsigned data per
channel. Used for specifying channel-specific attenuation and mute.
Selects the master clock mode as either 384 times the intended sample
frequency (HI) or 256 times the intended sample frequency (LO). The state
of this input should be hardwired to logic HI or logic LO, or may be changed
while the AD1854 is in power-down/reset. It must not be changed while the
AD1854 is operational.
384/256
7
8
I
O
X2MCLK
ZEROR
Selects internal clock doubler (LO) or internal clock = MCLK (HI).
Right Channel Zero Flag Output. This pin goes HI when Right Channel has
no signal input for more than 1024 LR Clock Cycles.
9
I
DEEMP
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.
This is used to impose a 50 µs/15 µs response characteristic on the output
audio spectrum at an assumed 44.1 kHz sample rate.
10
11, 15
12
13
14
I
I
O
O
O
96/48
Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
Analog Ground.
Right Channel Positive line level analog output.
Right Channel Negative line level analog output.
AGND
OUTR+
OUTR–
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 µF and 0.1 µF capacitors to the AGND.
16
17
18
19
20
O
O
I
O
I
OUTL–
OUTL+
AVDD
FILTB
IDPM1
Left Channel Negative line level analog output.
Left Channel Positive line level analog output.
Analog Power Supply. Connect to analog 5 V supply.
Filter Capacitor connection, connect 10 µF capacitor to AGND.
Input serial data port mode control one. With IDPM0, defines one of four
serial modes.
21
22
23
24
I
IDPM0
ZEROL
MUTE
PD/RST
Input serial data port mode control zero. With IDPM1, defines one of four
serial modes.
Left Channel Zero Flag Output. This pin goes HI when Left Channel has no
signal input for more than 1024 LR Clock Cycles.
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-
mal operation.
Power-Down/Reset. The AD1854 is placed in a low power consumption
mode when this pin is held LO. The AD1854 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values.
Connect HI for normal operation.
O
I
I
25
26
I
I
L/RCLK
BCLK
Left/Right clock input for input data. Must run continuously.
Bit clock input for input data. Need not run continuously; may be gated or
used in a burst fashion.
27
28
I
I
SDATA
DVDD
Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of
twos complement data per channel.
Digital Power Supply Connect to digital 5 V supply.
REV. A
–5–
AD1854
OPERATING FEATURES
Serial Data Input Port
Figure 1 shows the right-justified mode (16-bit mode). L/RCLK
is HI for the left channel, LO for the right channel. Data is valid
on the rising edge of BCLK. The MSB is delayed 16-bit clock
periods from an L/RCLK transition, so that when there are 64
BCLK periods per L/RCLK period, the LSB of the data will be
right justified to the next L/RCLK transition. The right-justified
mode can also be used with 20-bit or 24-bit inputs as selected
in Table I.
Figure 2 shows the I2S-justified mode. L/RCLK is LO for the
left channel and HI for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an L/RCLK
transition but with a single BCLK period delay. The I2S-justified
mode can be used with 16-/18-/20- or 24-bit inputs.
The AD1854’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The input data
consists of either 16, 18, 20, or 24 bits, as established by the
mode select pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the
mode select bits (Bits 15 and 14) in the control register through
the SPI (Serial Peripheral Interface) control port. Neither the
pins nor the SPI controls has preference; to ensure proper control,
the selection not being used should be tied LO. Therefore,
when the SPI bits are used to control Serial Data Input Format,
Pins 20 and 21 should be tied LO. Similarly, when the pins are
to be used to select the Data Format, the SPI bits should be set
to zeros. When the SPI Control Port is not being used, the SPI
Pins (3, 4, and 5) should be tied LO.
Figure 3 shows the left-justified mode. Note: Left-justified mode
is selected by pulsing IDPM1 (Pin 20) with bit clock, that is, tying
bit clock to IDPM1 while IDPM0 (Pin 21) is tied LO. Left-
justified can only be selected this way, it cannot be selected through
SPI Control Port.
Serial Data Input Mode
The AD1854 uses two multiplexed input pins to control the
mode configuration of the input data port mode as follows:
L/RCLK is HI for the left channel, and LO for the right channel.
Data is valid on the rising edge of BCLK. The MSB is left-
justified to an L/RCLK transition, with no MSB delay. The
left-justified mode can be used with 16-/18-/20- or 24-bit inputs.
Table I. Serial Data Input Modes
IDPM1
(Pin 20)
IDPM0
(Pin 21)
Serial Data Input Format
Note that the AD1854 is capable of a 32 × FS BCLK frequency
“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to an L/RCLK transi-
tion. L/RCLK is HI for the left channel, and LO for the right
channel. Data is valid on the rising edge of BCLK. Packed
mode can be used when the AD1854 is programmed in right-
justified mode. Packed mode is shown is Figure 4.
0
0
1
1
0
1
0
1
0
Right Justified (16 Bits)
I2S-Compatible
Right Justified (20 Bits)
Right Justified (24 Bits)
Left Justified
Bit Clock
Table II. Frequency Mode Settings
FS
96/48
MCLK
X2MCLK
384/256
Note
Normal, 32 kHz–48 kHz
Normal, 32 kHz–48 kHz
Normal, 32 kHz–48 kHz
Normal, 32 kHz–48 kHz
Double FS (96 kHz)
Double FS (96 kHz)
Double FS (96 kHz)
0
0
0
0
1
1
1
1
256 × FS
384 × FS
512 × FS
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Not Allowed
Not Allowed
128 × FS
(384/2) × FS
256 × FS
Double FS (96 kHz)
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB–1
LSB+1
LSB+2
MSB
MSB–2
LSB
Figure 1. Right-Justified Mode
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB
Figure 2. I2S-Justified Mode
–6–
REV. A
AD1854
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
MSB
MSB–1
Figure 3. Left-Justified Mode
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB
MSB–1 MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1 MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
Figure 4. 32 × FS Packed Mode
tCHD
tCCP
D15
CDATA
CCLK
D14
D0
tCCH
tCLH
tCSU
tCLL
tCCL
CLATCH
Figure 5. Serial Control Port Timing
Serial Control Port
The serial control port is byte oriented. The data is MSB first,
and is unsigned. There is one control register for the left
channel or the right channel, as distinguished by Bit Data 10.
For power-up and reset, the default settings are: Data 11 the
mute control bit, reset default state is LO, which is the normal
(nonmuted) setting. Data 10 is LO, the Volume 9 through
Volume 0 control bits have a reset default value of 11 1111 1111,
which is an attenuation of 0.0 dB (i.e., full scale, no attenuation).
The intent with these reset defaults is to enable AD1854 applica-
tions without requiring the use of the serial control port. For those
users who do not use the serial control port, it is still possible to
mute the AD1854 output by using the MUTE (Pin 23) signal.
The AD1854 serial control port is SPI-compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft power-down control, soft de-emphasis, channel-
specific attenuation and mute (both channels at once). The
AD1854 serial control port consists of three signals, control
clock CCLK (Pin 4), control data CDATA (Pin 5), and control
latch CLATCH (Pin 3). The control data input must be valid
on the control clock rising edge, and the control clock must make a
LO to HI transition when there is valid data. The control latch
must make a LO-to-HI transition after the LSB has been clocked
into the AD1854, while the control clock is inactive. The timing
relation between these signals is shown in Figure 5. The control
bits are assigned as in Table IV.
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the L/RCLK after the
CLATCH write pulse as shown in Figure 8.
Table III. Digital Timing
The SPI port can be used in either of two modes, Burst Mode,
or Continuous CCLK Mode, as described below.
Min
Unit
tCCH CCLK HI Pulsewidth
tCCL CCLK LO Pulsewidth
tCCP CCLK Period
tCSU CDATA Setup Time
tCHD CDATA Hold Time
tCLL CLATCH LO Pulsewidth
tCLH CLATCH HI Pulsewidth
40 (Burst Mode)
40 (Burst Mode)
80 (Burst Mode)
10
10
10
ns
ns
ns
ns
ns
ns
ns
Continuous CCLK Mode
In this mode, the maximum CCLK frequency is 3 MHz. The
CCLK can run continuously between transactions. Please note
that the LO-to-HI transition of the CLATCH with respect to
the rising edge of CCLK must be at least 130 ns, as shown in
Figure 6.
130 (Burst Mode)
Table IV. Serial Control Bit Definitions
MSB
LSB
Data 15 Data 14 Data 13 Data 12 Data 11
Data 10 Data 9 Data 8 Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1 Data 0
IDPM1 IDPM0 Soft
Input Input Power- De-
Mode1 Mode0 Down Emphasis (Nonmute)
Soft
1/Mute
0/Normal 0/Left
1/Right Volume Volume Volume Volume Volume Volume Volume Volume Volume Volume
Control Control Control Control Control Control Control Control Control Control
Data Data Data Data Data Data Data Data Data Data
Select
Select
REV. A
–7–
AD1854
CLATCH
>130ns
CCLK
CDATA
20
40
60
80
100
120
140
160
180
TIME – ns
Figure 6. SPI Port Continuous CCLK Mode
CLATCH
CCLK
CDATA
200
400
600
800
1000
1200
1400
1600
1800
TIME – ns
Figure 7. SPI Port Burst Mode
Burst Mode
Output Drive, Buffering and Loading
To operate with SPI CCLK frequencies up to 12.288 MHz, the
SPI port can be operated in Burst Mode. This means that when
CLATCH is high, CCLK cannot be HI, as shown in Figure 7.
The AD1854 analog output stage is able to drive a 1 kΩ (in
series with 2 nF) load.
Power-Down Reset
Mute
The AD1854 offers two methods for power-down and reset.
When the PD/RST input (Pin 24) is asserted LO, the AD1854
is reset. As an alternative, the user can assert the soft power-
down bit (Data 13) HI. All the registers in the AD1854 digital
engine (serial data port, interpolation filter and modulator) are
zeroed. The two 8-bit registers in the serial control port are
initialized back to their default values. The user should wait
100 ms after bringing PD/RST HI before using the serial data
input port and the serial control input. The AD1854 is designed
to minimize pops and clicks when entering and exiting the power-
down state.
The AD1854 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Data 11) HI. The
AD1854 has been designed to minimize pops and clicks when
muting and unmuting the device.
Smooth Volume Control with Auto Ramp Up/Down
The AD1854 incorporates ADI’s 1024 step “Smooth Volume
Control” with auto ramp up/down. Once per L/RCLK cycle, the
AD1854 compares current volume level register to the volume
level request register Data 9:0. If different, volume is adjusted
one step/sample. Therefore, a change from max to min volume
takes 1024 samples or about 20 ms as shown in Figure 8.
De-Emphasis
The AD1854 offers digital de-emphasis, supporting 50 µs/15 µs
digital de-emphasis intended for “Redbook” 44.1 kHz sample
frequency playback from Compact Discs. The AD1854 offers
control of de-emphasis by asserting the DEEMP input (Pin 9)
HI or by asserting the de-emphasis register bit (Data 12) HI.
The AD1854’s de-emphasis is optimized for 44.1 kHz but will
scale to the other sample frequencies.
0
VOLUME REQUEST REGISTER
Control Signals
–60
The IDPM0, IDPM1, and DEEMP control inputs are normally
connected HI or LO to establish the operating state of the
AD1854. They can be changed dynamically (and asynchronously
to L/RCLK and the master clock) as long as they are stable
before the first serial data input bit (i.e., MSB) is presented to
the AD1854.
0
ACTUAL VOLUME REGISTER
–60
TIME
20ms
Figure 8. Smooth Volume Control
–8–
REV. A
AD1854
Timing Diagrams
minimum setup time is tDDS and the minimum serial data hold
The serial data port timing is shown in Figures 9 and 10. The
minimum bit clock HI pulsewidth is tDBH and the minimum bit
clock LO pulsewidth is tDBL. The minimum bit clock period is
tDBP. The left/right clock minimum setup time is tDLS and the
left/right clock minimum hold time is tDLH. The serial data
time is tDDH
.
The power-down/reset timing is shown in Figure 11. The mini-
mum reset LO pulse width is tPDRP (four MCLK periods) to
accomplish a successful AD1854 reset operation.
tDBH
tDBP
BCLK
tDBL
tDLS
L/RCLK
tDDS
SDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB-1
tDDS
MSB
tDDH
SDATA
2
I S-JUSTIFIED
MODE
tDDS
LSB
tDDH
tDDS
MSB
tDDH
SDATA
RIGHT-JUSTIFIED
MODE
Figure 9. Serial Data Port Timing
tDBH
tDBP
BCLK
tDBL
tDLS
tDLH
L/RCLK
tDDS
MSB
tDDH
SDATA
LEFT-JUSTIFIED
DSP SERIAL
MSB-1
PORT STYLE MODE
Figure 10. Serial Data Port Timing–DSP Serial Port Style Mode
tDMH
tDMP
MCLK
tDML
PD/RST
tPDRP
Figure 11. Power-Down/Reset Timing
REV. A
–9–
AD1854
MCLK/SR SELECT
SELECT RATE X2MCLK
MCLK
384/256 96/48
DVDD
R2
SPDIF
DIRECT 48.0
DIRECT 96.0
44.1
0
0
0
0
0
0
0
0
1
11.2896
12.2880
12.2880
MCLK/SR
SEL
R3
10kꢅ
R1
10kꢅ 10kꢅ
JP1
AD1854 STEREO DAC
DVDD
AVDD
C3
100nF
C2
100nF
SDATA
LRCLK
SCLK
OUTPUT BUFFERS AND LP FILTERS
AUDIO
DATA
C9
R9
R8
953ꢅ
R16
390pF
NP0
DVDD
AVDD
2.15kꢅ
MCLK
1.96kꢅ
OUTL–
96/48
C14
R20
I/F MODE
IDPM1 IDPM0
1nF, NP0
J1
384/256
X2MCLK
SDATA
L/RCLK
BCLK
549ꢅ
1
LEFT
OUT
RJ, 16-BIT
0
0
1
1
0
1
0
1
0
U3B
C13
1nF, NP0
2
I S
C15
2.2nF
NP0
53.6kꢅ
R17
1.96kꢅ
R10
953ꢅ
RJ, 20-BIT
RJ, 24-BIT
LJ
SSM2135
OUTL+
BCLK
C10
390pF
NP0
R11
2.15kꢅ
DVDD
3RD ORDER LP BESSEL FILTER
CORNER FREQUENCY: 92kHz
GROUP DELAY: ~2.8ꢆs
I/F
U1
AD1854JRS
MODE
R4
R5
MCLK
IDPM0
IDPM1
DEEMP
MUTE
JP2
10kꢅ 10kꢅ
+AV
C11
390pF
NP0
CC
R13
2.15kꢅ
R18
1.96kꢅ
R12
953ꢅ
C5
DE-EMPHASIS
100nF
OUTR–
C17
MUTE
1nF, NP0
R21
J2
549ꢅ
1
CLATCH
CCLK
CDATA
ZR
RIGHT
OUT
C16
1nF, NP0
U3A
CLATCH
CCLK
C18
2.2nF
NP0
R19
1.96kꢅ
R14
953ꢅ
53.6kꢅ
SSM2135
OUTR+
C12
C6
100nF
CDATA
ZEROR
ZEROL
R15
2.15kꢅ
390pF
NP0
ZL
FILTR
FITLB
–AV
EE
RST
C1
PD/RST
100nF
DGND
AGND AGND
+
–
+
–
C8
10ꢆF
C7
10ꢆF
DGND
FB1
600Z
CDATA
CCLK
CONTROL
PORT
DVDD
CLATCH
C4
100nF
CR1
ZERO LEFT
CR2
ZERO RIGHT
U2A
R6
221ꢅ
R7
221ꢅ
NOTE:
HC04
1
ZL
ZR
2
= DGND
= AGND
U2B
HC04
3
4
Figure 12. Evaluation Board Circuit
–10–
REV. A
AD1854
TYPICAL PERFORMANCE
performance of the AD1854. Figure 15 shows the noise floor of
the AD1854. The digital filter transfer function is shown in
Figure 16. The two-tone test in Figure 17 is per the SMPTE
Standard for Measuring Intermodulation Distortion.
Figures 13 through 20 illustrate the typical analog performance
of the AD1854 as measured by an Audio Precision System Two.
Signal-to-Noise and THD+N performance are shown under a
range of conditions. Figure 14 shows the power supply rejection
0
0
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–20
–40
–60
–80
–20
–40
–60
–80
–140
–145
–150
–155
–160
–140
–145
–150
–155
–160
–100
–120
–100
–120
–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
0
2
4
6
8
10
12
14
16
18
20
AMPLITUDE – dBFS
FREQUENCY – kHz
Figure 13. THD+N at 1 kHz, –0.5 dBFS (8K-Point FFT)
Figure 16. THD+N vs. Level at 1 kHz
–40
–45
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–40
–45
–50
–55
–60
–65
–70
–75
–80
–40
–45
–50
–55
–60
–65
–70
–75
–80
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–85
–90
–85
–90
10
12
14
16
18
20
0
2
4
6
8
1k
2k
5k
10k 20k
20
50
100 200
500
FREQUENCY – kHz
FREQUENCY – Hz
Figure 17. Power Supply Rejection to 300 mV p-p on AVDD
Figure 14. THD+N vs. Frequency at –0.5 dBFS
0
–10
–20
–30
0
–10
0
0
–10
–20
–30
–40
–10
–20
–30
–40
–20
–30
–40
–50
–60
–70
–40
–50
–50
–60
–50
–60
–60
–70
–70
–80
–70
–80
–80
–90
–80
–90
–90
–90
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–100
–100
–110
–120
–110
–120
–130
–130
–140
–150
–160
–140
–150
–160
–140
–150
–160
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY – kHz
FREQUENCY – kHz
Figure 18. Noise Floor, A-Weighted (8K-Point FFT)
Figure 15. Dynamic Range: 1 kHz at –60 dBFS
(8K Point FFT)
REV. A
–11–
AD1854
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–100
0
0
2
4
6
8
10
12
14
16
18
20
20
40
60
80
100
120
140
160
FREQUENCY – kHz
FREQUENCY – kHz
Figure 19. Digital Filter Response
Figure 20. Two-Tone Test
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (SSOP)
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
0.32 (8.20)
0.29 (7.40)
0.22 (5.60)
0.20 (5.00)
1
0.073 (1.85)
0.065 (1.65)
PIN 1
0.079 (2.0)
MAX
0.037 (0.95)
0.022 (0.55)
8°
0°
0.026
(0.65)
BSC
0.015 (0.38)
0.009 (0.22)
0.002
(0.05)
MIN
SEATING
PLANE
0.01 (0.25)
0.004 (0.09)
–12–
REV. A
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