AD1866NZ [ADI]
IC SERIAL INPUT LOADING, 16-BIT DAC, PDIP16, PLASTIC, DIP-16, Digital to Analog Converter;
| 型号： | AD1866NZ |
| 厂家： | 
ADI |
| 描述： | IC SERIAL INPUT LOADING, 16-BIT DAC, PDIP16, PLASTIC, DIP-16, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply
Dual 16-Bit Audio DAC
a
AD1866*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Dual Serial Input, Voltage Output DACs
Single +5 Volt Supply
0.005% THD+N
AD1866
16-BIT
DAC
V
1
2
V
L
16
B
L
Low Pow er –50 m W
115 dB Channel Separation
Operates at 8
؋
Oversam pling 16-Pin Plastic DIP or SOIC Package
V
V
LL
15
14
13
12
11
10
16-BIT
SERIAL
REGISTER
S
L
DL
3
4
O
CLK
V
V
NRL
APPLICATIONS
REF
Multim edia Workstations
PC Audio Add-In Boards
Portable CD and DAT Players
Autom otive CD and DAT Players
Noise Cancellation
AGND
NRR
5
6
7
8
DR
LR
16-BIT
SERIAL
REGISTER
REF
DGND
V
R
O
16-BIT
DAC
V
R
V
B
9
S
P RO D UCT D ESCRIP TIO N
T he AD1866 operates on +5 V power supplies. T he digital
supply, VL, can be separated from the analog supply, VS, for re-
duced digital feedthrough. Separate analog and digital ground
pins are also provided. In systems employing a single +5 volt
power supply, VL and VS should be connected together. In bat-
tery operated systems, operation will continue even with re-
duced supply voltage. Typically, the AD1866 dissipates 50 mW.
T he AD1866 is a complete dual 16-bit DAC offering excellent
performance while requiring a single +5 V power supply. It is
fabricated on Analog Devices’ ABCMOS wafer fabrication
process. T he monolithic chip includes CMOS logic elements,
bipolar and MOS linear elements and laser trimmed, thin-
film resistor elements. Careful design and layout techniques
have resulted in low distortion, low noise, high channel separa-
tion and low power dissipation.
T he AD1866 is packaged in either a 16-pin plastic DIP or a
16-pin plastic SOIC package. Operation is guaranteed over the
temperature range of –35°C to +85°C and over the voltage
supply range of 4.75 V to 5.25 V.
T he DACs on the AD1866 chip employ a partially segmented
architecture. T he first three MSBs of each DAC are segmented
into 7 elements. T he 13 LSBs are produced using standard
R-2R techniques. T he segments and R-2R resistors are laser
trimmed to provide extremely low total harmonic distortion.
T he AD1866 requires no deglitcher or trimming circuitry.
P RO D UCT H IGH LIGH TS
1. Single supply operation @ +5 V.
2. 50 mW power dissipation.
Each DAC is equipped with a high performance output ampli-
fier. T hese amplifiers achieve fast settling and high slew rate,
producing ±1 V signals at load currents up to ±1 mA. T he buff-
ered output signal range is 1.5 V to 3.5 V. T he 2.5 V reference
voltages eliminate the need for “false ground” networks.
3. T HD+N is 0.005% (typical).
4. Signal-to-Noise Ratio is 95 dB (typical).
5. 115 dB channel separation (typical).
6. Compatible with all digital filter chips.
7. 16-pin DIP and 16-pin SOIC packages.
8. No deglitcher required.
A versatile digital interface allows the AD1866 to be directly
connected to all digital filter chips. Fast CMOS logic elements
allow for an input clock rate of up to 16 MHz. T his allows for
operation at 2×, 4×, 8×, or 16× the sampling frequency (where
FS = 44.1 kHz) for each channel. T he digital input pins of the
AD1866 are T T L and +5 V CMOS compatible.
9. No external adjustments required.
*P r otected by U.S. P atent Nos: 3,961,326; 4,141,004; 4,349,811; 4,857,862;
and patents pending.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD1866–SPECIFICATIONS(T = +25؇C and +5 V supplies unless otherwise noted)
A
Min
Typ
Max
0.8
Unit
RESOLUT ION
16
Bits
DIGIT AL INPUT S
VIH
VIL
2.4
V
V
I
IH, VIH = VL
1.0
–10.0
µA
µA
MHz
IIL, VIL = DGND
Maximum Clock Input Frequency
13.5
ACCURACY
Gain Error
Gain Matching
Midscale Error
Midscale Error Matching
Gain Linearity Error
±3
±3
±30
±10
±3
% of FSR
% of FSR
mV
mV
dB
DRIFT (0°C to +70°C)
Gain Drift
Midscale Drift
±100
–130
ppm/°C
µV/°C
T OT AL HARMONIC DIST ORT ION + NOISE
0 dB, 990.5 Hz
AD1866N
AD1866R
AD1866N
AD1866R
AD1866N
AD1866R
0.005
0.005
0.02
0.02
2.0
0.01
0.01
%
%
%
%
%
%
–20 dB, 990.5 Hz
–60 dB, 990.5 Hz
2.0
CHANNEL SEPARAT ION (1 kHz, 0 dB)
SIGNAL-T O-NOISE RAT IO (With A-Weight Filter)
D-RANGE (With A-Weight Filter)
OUT PUT
108
115
95
dB
dB
dB
90
Voltage Output Pins (VOL, VOR
Output Range (±3%)
Output Impedance
)
±1
0.1
±1
V
Ω
mA
Load Current
Bias Voltage Pins (VBL, VBR
Output Range
)
+2.5
350
V
Ω
Output Impedance
POWER SUPPLY
Specification, VL and VS
Operation, VL and VS
+I, VL and VS = 5 V
4.75
3.5
5
5.25
5.25
14
V
V
mA
10
50
POWER DISSIPAT ION
70
mW
T EMPERAT URE RANGE
Operation
Storage
–35
–60
85
100
°C
°C
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical
–2–
REV. 0
Typical Performance–AD1866
6
–30
–35°C
4
2
–40
–50
–60
–60dB
0°C
25°C
0
–2
–70
–80
70°C
–4
–6
–20dB
–90
0dB
125°C
–8
–100
–100
–80
–60
–40
–20
20
0
500
5500
10500
15500
20500
INPUT AMPLITUDE – dB
FREQUENCY – Hz
Figure 4. Gain Linearity Error vs. Input Am plitude
Figure 1. THD+N vs. Frequency
–30
125
–60dB
–40
124
123
122
–50
–60
–70
–20dB
–80
121
120
–90
0dB
–100
–75
–50
–25
25
50
75
100
125
0
2
3
4
5
10
10
10
FREQUENCY – Hz
10
TEMPERATURE – °C
Figure 5. THD+N vs. Tem perature
Figure 2. Channel Separation vs. Frequency
80
70
–30
–40
–60dB
–50
–60
60
50
–70
–20dB
–80
–90
0dB
40
3
4
5
–100
10
10
10
4.4
4.6
4.8
5.0
5.2
5.4
5.6
FREQUENCY – Hz
SUPPLY VOLTAGE
Figure 6. Power Supply Rejection Ratio vs. Frequency
(Supply Modulation Am plitude at 500 m V p-p)
Figure 3. THD+N vs. Supply Voltage
REV. 0
–3–
AD1866
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ABSO LUTE MAXIMUM RATINGS*
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VL
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1866 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO N
P IN D ESIGNATIO NS
P in
Mnem onic
D escription
AD1866
16-BIT
DAC
V
1
2
V
L
L
16
B
L
11
12
13
14
15
16
17
18
19
10
11
12
13
14
15
16
VL
Digital Supply (+5 V)
V
V
LL
16-BIT
SERIAL
REGISTER
15
14
13
12
11
10
LL
Left Channel Latch Enable Pin
Left Channel Data Input Pin
Clock Input Pin
S
DL
DL
3
4
O
CLK
DR
CLK
V
NRL
REF
Right Channel Data Input Pin
Right Channel Latch Enable Pin
Digital Common Pin
AGND
NRR
DR
LR
5
6
7
8
16-BIT
SERIAL
REGISTER
LR
V
REF
DGND
VBR
VS
DGND
V
R
O
16-BIT
DAC
Right Channel Bias Pin
V
R
V
S
B
9
Analog Supply (+5 V)
VOR
NRR
AGND
NRL
VOL
VS
Right Channel Output Pin
Right Channel Noise Reduction Pin
Analog Common Pin
Left Channel Noise Reduction Pin
Left Channel Output Pin
Analog Supply (+5 V)
VBL
Left Channel Bias Pin
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
AD1866N
AD1866R
AD1866R-REEL
–35°C to +85°C
–35°C to +85°C
–35°C to +85°C
Plastic DIP
SOIC
SOIC
N-16
R-16
R-16
–4–
REV. 0
Definition of Specifications–AD1866
TO TAL H ARMO NIC D ISTO RTIO N + NO ISE
T otal harmonic distortion plus noise (T HD+N) is defined as
the ratio of the square root of the sum of the squares of the am-
plitudes of the harmonics and noise to the amplitude of the fun-
damental input frequency. It is usually expressed in percent (%)
or decibels (dB).
FUNCTIO NAL D ESCRIP TIO N
T he AD1866 is a complete, monolithic dual 16-bit digital audio
DAC which runs off a single +5 volt supply. As shown in the
block diagram, each channel contains a voltage reference, a
16-bit serial-to-parallel input register, a 16-bit input latch, a
16-bit DAC, and an output amplifier.
T he voltage reference section provides a reference voltage and a
false ground voltage for each channel. T he low noise bandgap
circuits produce reference voltages that are unaffected by
changes in temperature, time, and power supply.
D -RANGE D ISTO RTIO N (EIAJ SP ECIFICATIO N)
D-Range distortion is the ratio of the amplitude of the signal at
an amplitude of –60 dB to the amplitude of the distortion plus
noise. In this case, an A-weight filter is used. T he value speci-
fied for D-range performance is the ratio measured plus 60 dB.
T he input registers are fabricated with CMOS logic gates.
T hese gates allow high switching speeds and low power con-
sumption, contributing to the fast digital timing, the low glitch
and low power dissipation of the AD1866.
SIGNAL-TO -NO ISE RATIO
T he signal-to-noise ratio is defined as the ratio of the amplitude
of the output when a full-scale output is present to the ampli-
tude of the output with no signal present. It is expressed in
decibels (dB) and measured using an A-weight filter.
AD1866
16-BIT
DAC
V
V
L
16
15
14
1
2
V
B
L
LL
GAIN LINEARITY
16-BIT
SERIAL
REGISTER
S
Gain linearity is a measure of the deviation of the actual output
amplitude from the ideal output amplitude. It is determined by
measuring the amplitude of the output signal as the amplitude
of that output signal is digitally reduced to a lower level. A per-
fect D/A converter exhibits no difference between the ideal and
actual amplitudes. Gain linearity is expressed in decibels (dB).
V
L
DL
CLK
DR
3
O
V
13
12
NRL
4
5
REF
AGND
16-BIT
SERIAL
REGISTER
V
LR
6
7
8
11 NRR
REF
MID SCALE ERRO R
V
R
DGND
10
9
O
Midscale error, or bipolar zero error, is the deviation of the ac-
tual analog output from a voltage at the bias pin when the twos
complement input code representing midscale is loaded in the
DAC. Midscale error is expressed in mV.
16-BIT
DAC
V
V
R
S
B
AD1866 Functional Block Diagram
T he 16-bit DAC uses a combination of segmentation and R-2R
architecture to achieve good integral and differential linearity.
T he resistors which form the ladder structure are fabricated
with silicon-chromium thin film. Laser trimming of these resis-
tors further reduces linearity error, resulting in low output
distortion.
T he output amplifier uses both MOS and bipolar devices and
incorporates an NPN class A output stage. It is designed to pro-
duce high slew rate, low noise, low distortion, and optimal fre-
quency response.
REV. 0
–5–
AD1866–Analog Circuit Considerations
GRO UND ING RECO MMEND ATIO NS
POWER
SUPPLY
T he AD1866 has two ground pins, designated as AGND (Pin
12) and DGND (Pin 7). T he analog ground, AGND, serves as
the “high quality” reference ground for analog signals and as a
return path for the supply current from the analog portion of
the device. T he system analog common should be located as
close as possible to Pin 12 to minimize any voltage drop which
may develop between these two points, although the internal
circuit is designed to minimize signal dependence of the analog
return current.
AD1866
V
V
V
L
1
2
3
L
16
15
14
13
12
11
10
9
B
V
LL
S
L
O
DL
4.7µF
T he digital ground, DGND, returns ground current from the
digital logic portion of the device. T his pin should be connected
to the digital common node in the system. As shown in Figure
7, the analog and digital grounds should be joined at one point
in a system. When these two grounds are connected such as at
the power supply ground, care should be taken to minimize the
voltage difference between the DGND and AGND pins in or-
der to ensure the specified performance.
+
–
CLK
DR
NRL
4
5
6
7
8
AGND
NRR
4.7µF
+
–
LR
DGND
V
R
O
V
V
R
S
B
P O WER SUP P LIES AND D ECO UP LING
T he AD1866 has three power supply input pins. VS (Pins 9 and
15) provide the supply voltages which operate the analog por-
tion of the device including the 16-bit DACs, the voltage refer-
ences, and the output amplifiers. T he VS supplies are designed
to operate from a +5 V supply. T hese pins should be decoupled
to the analog ground using a 0.1 µF capacitor. Good engineer-
ing practice suggests that the bypass capacitor be placed as
close as possible to the package pins. T his minimizes the inher-
ent inductive effects of printed circuit board traces.
(CAPACITOR VALUES ARE 0.1 µF UNLESS OTHERWISE
INDICATED)
Figure 7. Recom m ended Circuit Schem atic
NO ISE RED UCTIO N CAP ACITO RS
T he AD1866 has two noise reduction pins, designated as NRL
(Pin 13) and NRR (Pin 11). In order to meet specifications, it
is required that external noise reduction capacitors be con-
nected from these pins to AGND to reduce the output noise
contributed by the voltage reference circuitry. As shown in Fig-
ure 7, each of these pins should be bypassed to AGND with a
4.7 µF or larger capacitor. T he connections between the ca-
pacitors, package pins and AGND should be as short as pos-
sible to achieve the lowest noise.
VL (Pin 1) operates the digital portions of the chip including the
input shift registers and the input latching circuitry. VL is also
designed to operate from a +5 V supply. T his pin should be by-
passed to digital common using a 0.1 µF capacitor, again placed
as close as possible to the package pins. Figure 7 illustrates the
correct connection of the digital and analog supply bypass
capacitors.
An important feature of the AD1866 audio DAC is its ability to
operate at diminished power supply voltages. T his feature is
very important in portable battery operated systems. As the bat-
teries discharge, the supply voltage drops. Unlike any other au-
dio DAC, the AD1866 can continue to function at supply
voltages as low as 3.5 V. Because of its unique design, the
power requirements of the AD1866 diminish as the battery volt-
age drops, further extending the operating time of the system.
USING VBL AND VBR
T he AD1866 has two bias voltage reference pins, designated as
VBR (Pin 8) and VBL (Pin 16). Each of these pins supplies a dc
reference voltage equal to the center of the output voltage swing.
These bias voltages replace “false ground” networks previously
required in single supply audio systems. At the same time, they
allow dc coupled systems, improving audio performance.
–6–
REV. 0
Analog Circuit Considerations–AD1866
AD1866
16
V
V L
B
1
L
+
5V
LL
V
S
V
R
2
15
14
13
O
+5V
V
L
O
+
5V
V L
O
3
DL
V L
O
CLK
NRL
4
5
6
7
AGND
FALSE GROUND
(2.5V)
DR
LR
12
11
+5V
NRR
V R
O
+
5V
DGND
V R 10
O
V
R
V
R
V
S
8
9
O
B
V
L
O
Figure 8b. Circuitry Using Voltage Biases
D ISTO RTIO N P ERFO RMANCE AND TESTING
Figure 8a. Schem atic Using False Ground
T he T HD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and play-
back of an audio waveform. T herefore, the T HD+N specifica-
tion provides a direct measure to classify and choose an audio
DAC for a desired level of performance. Figure 1 illustrates the
typical T HD+N versus frequency performance of the AD1866.
It is evident that the T HD+N performance of the AD1866 re-
mains stable at all three amplitude levels through a wide range
of frequencies. A load impedance of at least 2 kΩ is recom-
mended for best T HD+N performance.
Figure 8a illustrates the traditional approach used to generate
false ground voltages in single supply audio systems. T his cir-
cuit requires additional power and circuit board space.
T he AD1866 eliminates the need for “false ground” circuitry.
VBR and VBL generate the required bias voltages previously
generated by the “false ground.” As shown in Figure 8b, VBR
and VBL may be used as the reference point in each output
channel. T his permits a dc coupled output signal path. T his
eliminates ac coupling capacitors and improves low frequency
performance. It should be noted that these bias outputs have
relatively high output impedance and will not drive output cur-
rents larger than 100 µA without degrading the specified
performance.
Analog Devices tests all AD1866s on the basis of T HD+N per-
formance. During the distortion test, a high speed digital pat-
tern generator transmits digital data to each channel of the
device under test. Sixteen-bit data is latched into the DAC at
352.8 kHz (8 × FS). T he test input code is a digitally encoded
990.5 Hz sine wave with 0 dB, –20 dB, and –60 dB amplitudes.
A 4096 point FFT calculates total harmonic distortion + noise,
signal-to-noise ratio, and D-range. No deglitchers or external
adjustments are used.
REV. 0
–7–
AD1866–Digital Circuit Considerations
CLK
M
S
B
L
S
B
DL
L
S
B
M
S
B
DR
LL
LR
Figure 9. AD1866 Control Signals
>30ns
INP UT D ATA
T he digital input port of the AD1866 employs five signals: Data
Left (DL), Data Right (DR), Latch Left (LL), Latch Right
(LR), and Clock (CLK). DL and DR are the serial inputs for
the left and right DACs, respectively. Input data bits are clocked
into the input register on the rising edge of CLK. T he falling
edges of LL and LR cause the last 16 bits which were clocked
into the serial registers to be shifted into the DACs, thereby up-
dating the respective DAC outputs. For systems using only a
single latch signal, LL and LR may be connected together. For
systems using only one DAT A signal, DR and DL may be con-
nected together. Data is transmitted to the AD1866 in a bit
stream composed of 16-bit words with a serial, twos comple-
ment, MSB first format. Left and right channels share the Clock
(CLK) signal.
DR/DL
CLK
>10ns
>40ns
>10ns
>30ns
>67ns
>30ns
>15ns
LR/LL
>40ns
>40ns
Figure 9 illustrates the general signal requirements for data
transfer for the AD1866.
Figure 10. AD1866 Input Signal Tim ing
T he maximum clock rate of the AD1866 is specified to be at
least 13.5 MHz. T his clock rate allows data transfer rates of 2×,
4×, 8×, and 16× FS (where FS equals 44.1 kHz). T he applica-
tions section of this data sheet contains additional guidelines for
using the AD1866.
TIMING
Figure 10 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. T he input pins of the AD1866 are both T T L and +5 V
CMOS compatible.
–8–
REV. 0
Applications of the AD1866
AP P LICATIO NS O F TH E AD 1866
In summary, the AD1866 is an excellent choice for multimedia,
battery operated portable or automotive digital audio systems.
In the following sections, some examples of high performance
audio applications featuring the AD1866 are described.
T he AD1866 is a high performance audio DAC specifically de-
signed for portable and automotive digital audio applications.
T hese market segments have technical requirements fundamen-
tally different than those found in the high-end or home use
market segment. Portable equipment must rely on components
which require low amounts of power to offer reasonable play-
back times. Also, battery voltage tends to diminish as the end of
the discharge cycle is approached. T he AD1866’s ability to op-
erate from a single +5 V supply makes it a good choice for bat-
tery operated gear. And, as the battery voltage drops, the power
dissipation of the AD1866 drops. T his extends the usable bat-
tery life. Finally, as the battery supply voltage drops, the bias
voltages and signal swings also drop, preventing signal clipping
and abrupt degradation of distortion. Figure 3 illustrates how
the T HD+N performance of the AD1866 remains constant
through a wide supply voltage range.
AD 1866 with the Sony CXD 2550P D igital Filter
Figure 11 illustrates a 16-bit CD player design incorporating an
AD1866 DAC, a Sony CXD2550P digital filter, and 2-pole
antialias filters. T his high performance, single supply design op-
erates at 8× FS and is suitable for portable and automotive ap-
plications. In this design, the CXD2550P filter transmits left
and right channel digital data to the AD1866. T he left and right
latch signals, LL and LR, are both provided by the word clock
signal (LRCKO) of the digital filter. T he digital data is con-
verted to low distortion output voltages by the output amplifiers
on the AD1866. Also, no deglitching circuitry or external ad-
justments are required. Bypass capacitors, noise reduction
capacitors and the antialias filter details are omitted for clarity.
Automotive equipment relies on components which are able to
consistently perform over a wide range of temperatures. In addi-
tion, due to the limited space available in automotive applica-
tions, small size is essential. T he AD1866 has guaranteed
operation between –35°C and +85°C, and the 16-pin DIP or
16-pin SOIC package is particularly attractive where overall size
is important.
AD D ITIO NAL AP P LICATIO NS
In addition to CD player designs, the AD1866 is suited for
similar applications such as DAT , portable musical instruments,
laptop and notebook personal computers, and PC audio I/O
boards. T he circuit techniques illustrated here are directly ap-
plicable in those applications. Figures 12, 13, 14, and 15 show
connection diagrams for the AD1866 and several popular digital
filter chips from NPC and Yamaha. Each application operates
at 8× FS operation. Please refer to the appropriate sections of
this data sheet for additional information.
Since the AD1866 provides dc bias voltages, the entire signal
chain can be dc coupled. T his eliminates ac coupling capacitors
from the signal path, improving low frequency performance and
lowering system cost and size.
+5V POWER
SUPPLY
LEFT
CHANNEL
OUTPUT
CXD2550P
AD1866
V
1
2
3
1
18
17
TEST
SLOT
16
15
V
L
L
B
NJM2100
1
2
3
8
7
+V
2
V
S
LRCKO
LL
S
330
pF
6.8kΩ
RIGHT
CHANNEL
OUTPUT
6.8kΩ
3
4
5
16
15
14
DL
V
L
DATAL
DATAR
14
13
O
6.8kΩ
6.8kΩ
330 pF
1000 pF
4
5
6
7
8
CLK
DR
NRL
6
5
V
6.8kΩ
V
DD
AGND 12
SS
4
6
7
8
13
12
BCKO
LR
NRR
11
10
9
6.8kΩ
V
SS
DGND
V
R
O
11
10
LRCK
V
R
V
S
1000 pF
B
9
LATCH
Figure 11. AD1866 with Sony CXD2550P Digital Filter
REV. 0
–9–
AD1866
+5V POWER
SUPPLY
1
2
3
28
27
SM5813
AD1866
L
BCKO
26
25
V L
1
V
16
15
B
4
5
WCKO
V
O
2
3
LL
S
LOW-
PASS
FILTER
DOL 24
DOR 23
LEFT
CHANNEL
OUTPUT
V
L
14
13
12
11
DL
6
7
V
22
4
5
NRL
DD
CLK
V
1
V
2
21
20
19
18
17
8
9
SS
SS
DR
AGND
NRR
6
7
8
LR
LOW-
PASS
FILTER
RIGHT
CHANNEL
OUTPUT
10
11
12
V
R
10
9
DGND
O
V R
B
V
OW18
S
13
14
16
15
OW20
COB
Figure 12. AD1866 with NPC SM5813 Digital Filter
+5V POWER
SUPPLY
SM5818AP
AD1866
1
V
16
DD
1
V
16
15
V L
L
B
2
BCKO
WDCO
15
14
2
3
4
5
V
S
LL
DL
LOW
PASS
FILTER
LEFT
CHANNEL
OUTPUT
3
V L
O
14
13
12
11
4
5
13
12
CLK
DR
NRL
AGND
NRR
DOR
DOL
6
7
8
6
7
11
10
9
LR
LOW
PASS
FILTER
RIGHT
CHANNEL
OUTPUT
DGND
10
9
V R
O
V R
B
V
S
OMOD1
V
8
SS
Figure 13. AD1866 with NPC SM5818AP Digital Filter
–10–
REV. 0
Applications–AD1866
+5V POWER
SUPPLY
YM3434
1
16
AD1866
V
16
1
2
V L
L
B
2
3
16/18 15
V
15
14
13
LL
DL
S
LOW-
LEFT
ST 14
3
PASS
V
L
CHANNEL
OUTPUT
O
FILTER
4
13
V
V
2
SS
DD
4
5
6
7
8
CLK
DR
NRL
AGND
NRR
5
6
7
8
BCO 12
WCO 11
12
11
10
LR
LOW-
PASS
FILTER
RIGHT
CHANNEL
OUTPUT
V
R
DGND
10
9
DRO
DLO
O
V
V R
B
9
V
1
S
DD
Figure 14. AD1866 with Yam aha YM3434 Digital Filter
+5V POWER
SUPPLY
AD1866
1
18
17
V
1
2
3
V L 16
L
B
2
3
4
5
V
LL
15
S
LOW-
PASS
FILTER
LEFT
CHANNEL
OUTPUT
SM5840A/B
16
V
L
DL
14
13
O
BCKO 15
CLK
4
5
NRL
AGND
NRR
V
12
11
10
9
14
DR
V
SS
DD
6
7
8
WCKO 13
OW20
LR
6
7
8
RIGHT
CHANNEL
OUTPUT
LOW-
PASS
FILTER
V
R
DGND
DOL
O
12
11
V R
B
V
S
DOR
10
9
Figure 15. AD1866 with NPC SM5840C Digital Filter
REV. 0
–11–
AD1866
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic D IP (N) P ackage
P lastic SO IC (R) P ackage
9
16
1
0.25
0.31
16
9
(6.35)
(7.87)
8
0.419
(10.65)
0.299
(7.60)
0.87 (22.1) MAX
0.035
(0.89)
0.18 (4.57)
MAX
1
8
0.125
(3.18)
MIN
0.18
(4.57)
0.011
(0.28)
0.413
(10.50)
0.3 (7.62)
0.033 (0.84)
0.1 (2.54)
0.018 (0.46)
0.104
(2.65)
0.012
(0.3)
0.019 (0.49)
0.05 (1.27)
REF
0.030
(0.75)
0.042 (1.07)
0.013
(0.32)
–12–
REV. 0
相关型号：
AD1868NZ
IC DUAL, SERIAL INPUT LOADING, 18-BIT DAC, PDIP16, PLASTIC, DIP-16, Digital to Analog Converter
ADI
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