AD1876 [ADI]
16-Bit 100 kSPS Sampling ADC; 16位100 kSPS的采样ADC
| 型号： | AD1876 |
| 厂家： | 
ADI |
| 描述： | 16-Bit 100 kSPS Sampling ADC |
| 文件： | 总12页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit 100 kSPS
Sampling ADC
a
AD1876
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Autocalibrating
0.002% THD
90 dB S/ (N+D)
A CHIP
1 MHz Full Pow er Bandw idth
On-Chip Sam ple & Hold Function
2
؋
Oversam pling for Audio Applications 16-Pin DIP Package
Serial Tw os Com plem ent Output Form at
Low Input Capacitance–typ 50 pF
AGND Sense for Im proved Noise Im m unity
V
10
9
IN
16-BIT
DAC
COMP
AGND
SENSE
INPUT
BUFFERS
11
8
V
REF
CAL
DAC
AGND
LOGIC TIMING
LEVEL TRANSLATORS
15 BUSY
14
3
D
D
CLK
OUT
OUT
CAL
CLK
16
2
SAR
P RO D UCT D ESCRIP TIO N
MICROCODED
CONTROLLER
T he AD1876 is a 16-bit serial output sampling A/D converter
which uses a switched capacitor/charge redistribution architecture
to achieve a 100 kSPS conversion rate (10 µs total conversion
time). Overall performance is optimized by digitally correcting
internal nonlinearities through on-chip autocalibration.
ALU
SAMPLE
1
RAM
D CHIP
AD1876
T he circuitry of the AD1876 is partitioned onto two monolithic
chips, a digital control chip fabricated with Analog Devices’
DSP CMOS process and an analog ADC chip fabricated with
the BiMOS II process. Both chips are contained in a single
package.
T he serial output interface requires an external clock and
sample command signal. T he output data rate may be as high
as 2.08 MHz, and is controlled by the external clock. T he twos
complement format of the output data is MSB first and is di-
rectly compatible with the NPC SM5805 digital decimation fil-
ter used in consumer audio products. T he AD1876 is also
compatible with a variety of DSP processors.
T he AD1876 is packaged in a space saving 16-pin plastic DIP
and operates from +5 V and ±12 V supplies; typical power con-
sumption is 235 mW. T he digital supply (VDD) is isolated from
the linear supplies (VEE and VCC) for reduced digital crosstalk.
Separate analog and digital grounds are also provided.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
MIN to T , V = +12 V ؎ 5%, V = –12 V ؎ 5%, V = +5 V ؎ 10%)1
AD1876–SPECIFICATIONS (T
MAX CC
EE
DD
AD 1876J
Typ
P aram eter
Min
Max
Units
T EMPERAT URE RANGE
0
70
°C
T OT AL HARMONIC DIST ORT ION (T HD)2
–0.05 dB Input
–95
0.002
–78
0.01
–40
1.0
–88
0.004
dB
%
dB
%
dB
%
–20 dB Input
–60 dB Input
D-RANGE, –60 dB, A-WEIGHT ED
92
dB
SIGNAL-T O-NOISE AND DIST ORT ION (S/(N+D)) RAT IO3
–0.05 dB Input, A-Weighted
–0.05 dB Input, 48 kHz Bandwidth
–20 dB Input, A-Weighted
–20 dB Input, 48 kHz Bandwidth
–60 dB Input, A-Weighted
–60 dB Input, 48 kHz Bandwidth
92
90
73
70
34
31
dB
dB
dB
dB
dB
dB
83
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
–99
–89
dB
INT ERMODULAT ION DIST ORT ION (IMD)4
2nd Order Products
3rd Order Products
–102
–98
dB
dB
FULL POWER BANDWIDT H
1
MHz
V
VOLT AGE REFERENCE INPUT RANGE5 (VREF
ANALOG INPUT6
)
3
5
10.0
Input Range (VIN
Input Impedance
)
±VREF
V
*
Input Capacitance During Sample
Aperture Delay
Aperture Jitter
50*
6
100
pF
ns
ps
POWER SUPPLIES
Operating Current
ICC
IEE
IDD
9
9
3
235
12
12
12
350
mA
mA
mA
mW
Power Consumption
NOT ES
1VREF = 5.00 V; conversion rate = 96 kSPS; fIN = 1.06 kHz; VIN = –0.05 dB unless otherwise noted. All measurements referred to a 0 dB (10 V p-p) input signal.
Values are post calibration.
2Includes first 19 harmonics.
3Minimum value of S/(N+D) corresponds to 5.0 V reference; typical values of S/(N+D) correspond to 10.0 V reference.
4fa = 1008 Hz; fb = 1055 Hz. See Definition of Specifications section and Figure 14.
5See Applications section for recommended voltage reference circuit and Figure 11 for performance with other reference voltage values.
6See Applications section for recommended input buffer circuit.
*For explanation of input characteristics, see “Analog Input” section.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
O RD ERING GUID E
Tem perature TH D P ackage
P ackage
O ption*
Model
Range
dB
D escription
AD1876JN
0°C to +70°C
–95
Plastic 16-Pin DIP N-16
*N = Narrow Plastic DIP.
–2–
REV. A
AD1876
(TMIN to T , V = +12 V ؎ 5%, V = –12 V ؎ 5%, V = +5 V ؎ 10%)
DIGITAL SPECIFICATIONS
P aram eter
MAX CC
EE
DD
Test Conditions
Min
Typ
Max
Units
LOGIC INPUT S
VIH
VIL
IIH
IIL
CIN
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
2.4
V
V
µA
µA
pF
–0.3
–10
–10
0.8
+10
+10
10
VIH = VDD
VIL = 0 V
LOGIC OUT PUT S
VOH
High Level Output Voltage
IOH = 0.1 mA
IOH = 0.5 mA
IOL = 1.6 mA
VDD – 1 V
2.4
V
V
V
VOL
Low Level Output Voltage
0.4
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing qual-
ity levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
ABSO LUTE MAXIMUM RATINGS*
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +26.4 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . –18 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . 0 V to 5.5 V
Analog Inputs, VREF to AGND . . . . . . . . . . . (VCC + 0.3 V) to
(VEE – 0.3 V)
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage T emperature . . . . . . . . . . . . . . . . . . –60°C to +100°C
*Stresses greater than those listed under “Absolute M aximum Ratings” may
cause permanent damage to the device. T his is
a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1876 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
1
TIMING SPECIFICATIONS (TMIN to T , V = +12 V ؎ 5%, V = –12 V ؎ 5%, V = +5 V ؎ 10%, V = 5.00 V)
MAX CC
EE
DD
REF
P aram eter
Sym bol
Min
Typ
Max
Units
Sampling Rate2
fS = 1/tS
tS = l/fS
tA
tCT
tC
tCALB
tCB
tCD
tCH
tCL
tDCL
tSC
tCALH
tCDH
tSL
1
10
2
100
1000
kSPS
µs
µs
Sampling Period2
Acquisition T ime (Included in tS)
Calibration T ime
CLK Period
CAL to BUSY Delay
CLK to BUSY Delay
CLK to DOUT Hold T ime
CLK HIGH
CLK LOW
DOUT CLK LOW
SAMPLE LOW to 1st CLK Delay
CAL HIGH T ime
CLK to DOUT CLK
SAMPLE LOW
5000
175
tC
480
0
ns
ns
ns
ns
ns
ns
ns
ns
tC
50
10
160
50
30
50
4
120
80
200
275
150
50
200
ns
ns
NOT ES
1See Figure 1 and Figure 2 and the Conversion Control and Autocalibration sections for detailed explanations of the above timing.
2Depends upon external clock frequency; includes acquisition time and conversion time. T he minimum sampling rate/maximum sampling period is specified to
account for droop of the internal sample/hold. Operation at slower rates than specified may degrade performance.
REV. A
–3–
AD1876
CAL
t
CT
t
CALB
t
BUSY
CLK
C
t
t
CL
CH
t
CB
Figure 1. AD1876 Calibration Tim ing
t
(=1/fs)
S
t
SL
SAMPLE
t
A
t
A
t
C
BUSY
CLK
t
t
t
CL
CB
CH
t
CB
t
SC
2
17
1
16
3
t
CD
D
PREVIOUS LSB
X
OUT
MSB
LSB
t
CDH
t
DCL
D
CLK
OUT
Figure 2. Recom m ended AD1876 Conversion Tim ing
Definition of Specifications
BAND WID TH
NYQ UIST FREQ UENCY
T he full power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
INTERMO D ULATIO N D ISTO RTIO N (IMD )
TO TAL H ARMO NIC D ISTO RTIO N
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, l, 2, 3. . . . Intermodulation terms are those for
which m or n is not equal to zero. For example, the second or-
der terms are (fa + fb) and (fa – fb), and the third order terms are
(2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). T he IMD products
are expressed as the decibel ratio of the rms sum of the mea-
sured input signals to the rms sum of the distortion terms. T he
two signals applied to the converter are of equal amplitude, and
the peak value of their sum is –0.05 dB from full scale. T he
IMD products are normalized to a 0 dB input signal.
T otal harmonic distortion (T HD) is measured as the ratio of the
rms sum of the first nineteen harmonic components to the rms
value of a 1 kHz full-scale sine wave input signal and is ex-
pressed in percent (%) or decibels (dB). For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
SIGNAL-TO -NO ISE P LUS D ISTO RTIO N RATIO
Signal-to-noise plus distortion (S/N+D) is defined to be the ra-
tio of the rms value of the measured input signal to the rms sum
of all other spectral components below the Nyquist frequency,
including harmonics but excluding dc.
AP ERTURE D ELAY
D -RANGE D ISTO RTIO N
Aperture delay is the time required after SAMPLE is taken
LOW for the internal sample-hold of the AD1876 to open, thus
D-range distortion is the ratio of the distortion plus noise to the
signal at a signal amplitude of –60 dB. In this case, an A-weight
filter is used. T he value specified for D-range performance is the
ratio measured plus 60 dB.
holding the value of VIN
.
AP ERTURE JITTER
Aperture jitter is the variation in the aperture delay from sample
to sample.
–4–
REV. A
AD1876
P IN D ESCRIP TIO N
P in
No.
Nam e
Type
D escription
1
SAMPLE
DI
VIN Acquisition Control Pin. During conversion, SAMPLE controls the state of the internal
Sample-Hold Amplifier and initiates conversion (see “Conversion Control” paragraph). Dur-
ing calibration, SAMPLE is active HIGH, forcing DOUT (Pin 3) LOW. If SAMPLE is LOW
during calibration, DOUT will output diagnostic information (See “Autocalibration” paragraph.)
2
CLK
DI
Master Clock Input. T he AD1876 requires 17 clock pulses to execute a conversion. CLK is
also used to derive DOUT CLK (Pin 14). During calibration, 5000 clock pulses are applied.
3
DOUT
DO
P
Serial Output Data, T wos Complement format.
Digital Ground.
4
DGND
VCC
5
P
+12 V Analog Supply Voltage.
No Connection.
6
N/C
–
7
N/C
–
No Connection.
8
AGND
AGND SENSE
VIN
P/AI
AI
AI
AI
P
Analog Ground.
9
Analog Ground Sense.
10
11
12
13
14
Analog Input Voltage, referred the AGND SENSE.
External Voltage Reference Input, referred to AGND.
–12 V Analog Supply Voltage.
+5 V Logic Supply Voltage.
VREF
VEE
VDD
P
DOUT CLK
DO
T he rising edge of DOUT CLK may be used to latch DOUT (Pin 3). DOUT CLK is derived from
CLK.
15
16
BUSY
CAL
DO
DI
Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress.
Calibration Control Pin (asynchronous).
T ype: AI = Analog Input.
DI = Digital Input.
DO = Digital Output.
P = Power.
A CHIP
V
10
9
IN
16-BIT
DAC
COMP
AGND
SENSE
INPUT
BUFFERS
11
8
V
REF
CAL
DAC
AGND
LOGIC TIMING
LEVEL TRANSLATORS
1
16
15
14
13
12
11
10
9
SAMPLE
CLK
CAL
2
3
4
5
6
7
8
BUSY
15 BUSY
D
D CLK
OUT
OUT
14
3
D
D
CLK
OUT
OUT
AD1876
TOP VIEW
DGND
V
DD
EE
REF
IN
CAL
CLK
16
2
SAR
MICROCODED
CONTROLLER
V
V
V
V
(Not to Scale)
CC
ALU
NC
NC
SAMPLE
1
RAM
AGND SENSE
AGND
D CHIP
AD1876
NC = NO CONNECT
Functional Block Diagram
Package Pinout
REV. A
–5–
AD1876
FUNCTIO NAL D ESCRIP TIO N
held HIGH, DOUT will be forced LOW. In either case, DOUT
CLK will continue pulsing. Since the SAMPLE pin has no con-
trol over the actual calibration process, normal conversion tim-
ing may also be used for calibration. In this case, however, the
DOUT pin will output test information during those periods that
SAMPLE is LOW. BUSY going LOW will always indicate the
end of calibration.
T he AD1876 is a 16-bit analog-to-digital converter including a
sample/hold input circuit, successive approximation register,
ground sensing circuitry, serial output port and a micro-
controller based autocalibration circuit. T hese functions are seg-
mented onto two monolithic chips, an analog signal processor
and a digital controller. Both chips are contained within the
AD1876 package.
A calibration sequence should be followed by one “dummy”
conversion to clear the internal circuitry of the AD1876 in order
to guarantee subsequent conversion accuracy.
T he AD1876 employs a successive-approximation technique to
determine the value of the analog input voltage. However, in-
stead of the traditional laser-trimmed resistor-ladder approach,
the AD1876 uses a capacitor-array, charge-redistribution tech-
nique. An array of binary-weighted capacitors subdivides the
input value to perform the actual analog to digital conversion.
T his capacitor array also serves a sample/hold function without
the need for additional external circuitry.
In most applications, it is sufficient to calibrate the AD1876
only upon power-up, in which case care should be taken that the
power supplies and voltage reference have stabilized first.
CO NVERSIO N CO NTRO L
T he AD1876 is controlled by two signals: SAMPLE and CLK,
as shown in Figure 2. It is assumed that the part has been cali-
brated and the digital I/O pins have the levels shown at the start
of the timing diagram.
T he autocalibration circuit within the AD1876 employs a
microcontroller and calibration DAC to measure and compen-
sate capacitor mismatch errors. As each error is determined, its
value is stored in on-chip memory (RAM). Subsequent conver-
sions use these RAM values to improve conversion accuracy.
T he autocalibration routine may be invoked at any time. Auto-
calibration insures high performance while eliminating the need
for any user adjustments, and is described in detail below.
A conversion consists of an input acquisition followed by 17
clock pulses which are required to run the 16-bit internal suc-
cessive approximation routine. T he analog input is acquired by
taking the SAMPLE line HIGH for a minimum acquisition time
of tA. T he actual sample taken is the voltage present on VIN at
the instant the SAMPLE pin is brought LOW. Care should be
taken to ensure that this negative edge is well defined and jitter
free to reduce the uncertainty (noise) in ac signal acquisition.
On that edge the AD1876 commits itself to the initiated conver-
sion—the input at VIN is disconnected from the internal capaci-
tor array and the SAMPLE input will be ignored until the
conversion is completed (i.e., BUSY goes LOW). After a delay
of at least tSC (SAMPLE to CLK setup) the 17 CLK cycles are
applied. BUSY is asserted after the first positive edge on CLK
and reset after the 17th. Both the DOUT and the DOUT CLK out-
puts are generated in response to the rising edges of valid CLK
pulses. As indicated in the timing diagram, the 2s complement
output data is presented MSB first. T his data may be captured
with the rising edge of DOUT CLK or the falling edge of CLK
provided tCH ≥ tCDH. T he AD1876 will ignore CLK after BUSY
has gone LOW and not change DOUT or DOUT CLK until a new
sample is acquired. SAMPLE will no longer be ignored after
BUSY goes LOW, and so an acquisition may be initiated even
during the HIGH time of the 17th CLK pulse for maximum
throughput rate while enabling full settling of the sample/hold
circuitry. Note that if SAMPLE is already HIGH when BUSY
goes LOW, then an acquisition is immediately initiated and tA
starts from that time.
T he microcontroller controls all of the various functions within
the AD1876. T hese include the actual successive approximation
routine, the autocalibration routine, the sample/hold operation,
and the serial data transmission.
AUTO CALIBRATIO N
T he AD1876 achieves rated performance without the need for
user trims or adjustments. T his is accomplished through the use
of on-chip autocalibration.
In the autocalibration sequence, sample/hold offset is nulled by
internally connecting the input circuit to the ground sense cir-
cuit. T he resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. T his
charge is then inverted and shared between the MSB capacitor
and one of equal size composed of all the least significant bits.
T he difference in the summation of the charges in each of the
equally sized capacitors represents the amount of capacitor mis-
match. A calibration D/A converter (DAC) adds an appropriate
value of error correction voltage to cancel the mismatch. T his
correction factor is also stored in RAM. T his process is repeated
for each of the capacitors representing the remaining bits. T he
accumulated values in RAM are then used during subsequent
conversions to adjust conversion results.
During signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is not
recommended that CLK be running during VIN sampling. If a
continuous CLK is used, then the user must avoid CLK edges
at the instant of disconnecting VIN, i.e., the falling edge of
SAMPLE (see the tSC specifications). T he LOW level time of
CLK (tCL) should be at least 100 ns to avoid the negative edge
transition disturbing the internal comparator’s settling (whose
decision is latched on the positive edge of each valid CLK). For
the same reason, it is also not recommended that the SAMPLE
pin change state during conversion (i.e., until after BUSY re-
turns LOW).
As shown in Figure 1, when CAL is taken HIGH the AD1876
internal circuitry is reset, the BUSY pin is driven HIGH and the
part prepares for calibration. T his is a ‘hard’ reset and will inter-
rupt any conversion or calibration currently in progress. In order
to guarantee that all internal undefined states are cleared, the
CAL pin should he held HIGH for at least 4 CLK cycles. Ac-
tual calibration begins when the CAL pin is taken LOW and
completes in less than 5000 clock cycles or about 2.5 msec with
a continuous 500 nsec clock.
During calibration the SAMPLE pin adopts an alternative func-
tion. If it is held LOW, DOUT provides diagnostic test informa-
tion (not intended to be used by the customer). If SAMPLE is
–6–
REV. A
AD1876
Internal dc error terms such as comparator voltage offset are
sampled, stored on internal capacitors and used to correct for
their corresponding errors when needed. Because these voltages
are stored on capacitors, they are subject to leakage decay and
so require refreshing. For this reason the part is required to be
run continuously—i.e., there is a minimum tS specification. If
the part has been idle for too long (i.e., tS has expired) then a
dummy conversion cycle is required to refresh these correction
voltages.
Decoupling capacitors should he used on all power supply pins.
T hese capacitors should be placed as close as possible to the
package pins as well as the ground connections. T he logic sup-
ply (VDD) should be decoupled to digital common (DGND)
with a 0.1 µF ceramic capacitor, and the analog supplies (VEE
and VCC) should be decoupled to analog common (AGND)
with 4.7 µF and 0.1 µF tantalum capacitors in parallel, repre-
sented by C1. An effort should be made to minimize the trace
length between the capacitor leads and the respective converter
power supply and common pins. T he recommended decoupling
scheme is illustrated in Figure 3.
BUSY is HIGH during a conversion and goes LOW when the
conversion is completed. T he twos complement output data is
presented MSB first, with MSB data valid on the rising edge of
the second DOUT CLK pulse. Subsequent data is valid on rising
edges of subsequent DOUT CLK pulses. T able I illustrates the
AD1876 output coding.
As with most high performance linear circuits, changes in the
power supplies can produce undesired changes in the perfor-
mance of the circuit. Analog Devices recommends that well
regulated power supplies with less than 1% ripple be incorpo-
rated into the design of any system using these devices.
Table I. Serial O utput Coding Form at (Twos Com plem ent)
BO ARD LAYO UT
VIN
O utput Code
Designing with high resolution data converters requires careful
attention to board layout. T race impedance is a significant issue.
A 1.22 mA current through a 0.5 Ω trace will develop a voltage
drop of 0.6 mV, which is 4 LSBs at the 16 bit level for a 10 V
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies need to be decoupled in order to
filter ac noise.
–Full Scale
100 . . . 00
100 . . . 01
111 . . . 11
000 . . . 00
000 . . . 01
011 . . . 10
011 . . . 11
–Full Scale + 1 LSB
Midscale – 1 LSB
Midscale
Midscale + 1 LSB
Full Scale – 1 LSB
Full Scale
Analog and digital signals should not share a common return
path. Each signal should have an appropriate analog or digital
return routed close to it. Using this approach, signal loops en-
close a small area, minimizing the inductive coupling of noise.
Wide PC tracks, large gauge wire, and ground planes are highly
recommended to provide low impedance signal paths. Separate
analog and digital ground planes are also desirable, with a single
interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them, if at all, only at right angles. A solid analog
ground plane around the AD1876 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit con-
struction is preferred.
A simple method for generating the required signals for the
AD1876 is to connect one or more AD1876s to an NPC
SM5805 digital filter. T his device supplies all signals required to
operate the AD1876 at a 96 kHz sample rate, which is 2 × FS for
audio applications. This is more fully discussed in the applications
section of this data sheet, accompanied by Figures 9 and 10.
AP P LICATIO NS
P O WER SUP P LIES AND D ECO UP LING
T he AD1876 has three power supply input pins. VEE and VCC
provide the supply voltages to operate the analog portions of the
AD1876 including the ADC and SHA. VDD provides the supply
voltage which operates the digital portions of the AD1876 in-
cluding the serial output port and the autocalibration controller.
GRO UND ING
V
T he AD1876 has three grounding pins, designated ANALOG
GROUND (AGND), DIGIT AL GROUND (DGND) and
ANALOG GROUND SENSE (AGND SENSE). T he analog
ground pin is the “high quality” ground reference point for the
device. T he analog ground pin should be connected to the ana-
log common point in the system.
11
REF
13
5V
V
DD
V
10
9
IN
AD1876
AGND SENSE
0.1µF
V
V
EE
CC
DGND
AGND
8
AGND SENSE is intended to be connected to the input signal
ground reference point. T his allows for slight differences in level
between the analog ground point in the system and the input
signal ground point. However, no more than 100 mV is recom-
mended between the analog ground pin and the analog ground
sense pin for specified performance.
4
12
5
C1
C1
SYSTEM
ANALOG
COMMON
SYSTEM
DIGITAL
COMMON
12V –12V
T he digital ground pin is the reference point for all of the digital
signals that operate the AD1876. T his pin should be connected
to the digital common point in the system. As illustrated in Fig-
ure 3, the analog and digital grounds should be connected to-
gether at one point in the system.
Figure 3. Grounding and Decoupling the AD1876
REV. A
–7–
AD1876
VO LTAGE REFERENCE
+70°C range, the AD586L grade exhibits less than a 2.25 mV
output change from its initial value at +25°C. A noise-reduction
capacitor, CN, reduces the broadband noise of the AD586 out-
put, thereby optimizing the overall performance of the AD1876.
T he AD1876 requires the use of an external voltage reference.
T he input voltage range is determined by the value of the refer-
ence voltage; in general, a reference voltage of n volts produces
an input range of ±n volts. Signal-to-noise performance is in-
creased proportionately with input signal range. T he AD1876 is
specified with a 5.0 V reference and an analog input of ±5 V. In
the presence of a fixed amount of system noise, increasing the
LSB size (which results from increasing the reference voltage)
will increase the effective S/(N+D) performance for input values
below the point where input distortion occurs. Figure 11 illus-
trates S/(N+D) as a function of input amplitude and reference
voltage.
+12V
2
V
8
6
11
AD586
REF
4
+
C
N
47µF
AD1876
1µF
During a conversion, the switched capacitor array of the
AD1876 presents a dynamically changing current load at the
voltage reference as the successive-approximation algorithm
cycles through various choices of capacitor weighting. T he out-
put impedance of the reference circuitry must be low so that the
output voltage will remain sufficiently constant as the current
drive changes. In most applications, this requires that the output
of the voltage reference be buffered by an amplifier with low im-
pedance at relatively high frequencies. A (10 µF or larger) ca-
pacitor connected between VREF and AGND will reduce the
demands on the reference by decreasing the magnitude of high
frequency components.
AGND
8
AGND
Figure 5.
For higher performance needs, the AD588 reference provides
improved drift, low noise, and excellent initial accuracy. T he
AD588 uses a proprietary ion-implanted buried Zener diode in
conjunction with laser-trimmed thin-film resistors for low offset
and gain. T he AD588 output is accurate to 0.65 mV from its
value at +25°C over the 0°C to +70°C range. T he circuit shown
in Figure 6 includes a noise-reduction network on Pins 4, 6 and
7. T he 1 µF capacitors form low-pass filters with the internal re-
sistance of the AD588 and external 3.9 kΩ resistor. T his re-
duces the wide-band (to 1 MHz) noise of the AD588, providing
optimum performance of the AD1876.
T he following two sections represent typical design approaches.
VO LTAGE REFERENCE—AUD IO AP P LICATIO NS
Audio applications require optimal ac performance over a rela-
tively narrow temperature range, with low cost being important.
Figure 4 shows one such approach towards attaining these goals.
A voltage reference, consisting of a Zener diode, capacitor, resis-
tor and op amp with typical component values, is shown. T his
simple circuit has the advantage of low cost, but the reference
voltage value is sensitive to changes in the +12 V supply. Addi-
tionally, changes in the Zener value due to temperature varia-
tions will also be reflected in the reference voltage. ROPT ION may
be required for other component selections if the Zener requires
more current than the op amp can supply.
+12V
1µF
3.9kΩ
1µF
NOISE
REDUCTION
7
6
4
3
V
REF
1
9
2
11
8
47µF
0.1µF
AGND
AD588
10
11
AGND
0.1µF
16
AD1876
+
5
8
13 12
NC
1kΩ
–12V
R
OPTION
NC NC
Figure 6.
V
REF
11
AD711
ANALO G INP UT
3kΩ
1kΩ
As previously discussed, the analog input voltage range for the
AD1876 is ±VREF. For purposes of ground drop and common-
mode rejection, the VIN and VREF inputs each have their own
ground. VREF is referred to the local analog system ground
(AGND), and VIN is referred to the analog ground sense pin
(AGND SENSE) which allows a remote ground sense for the
input signal. If AGND SENSE is not used, it should be con-
nected to the AGND pin at the package. T he AGND SENSE
pin is intended to be tied to potentials within 100 mV of AGND
to maintain specified performance.
AD589
0.1µF
AD1876
Figure 4. Low Cost Voltage Reference Circuit
VO LTAGE REFERENCE—P RECISIO N MEASUREMENT
AP P LICATIO NS
In applications other than audio, parameters such as low drift
over temperature and static accuracy are important. Figure 5
shows a voltage reference circuit featuring the 5 V AD586. T he
AD586 is a low cost reference which utilizes a buried Zener ar-
chitecture to provide low noise and drift. Over the 0°C to
T he AD1876 analog inputs (VIN, VREF and AGND SENSE)
exhibit dynamic characteristics. When a conversion cycle begins,
each analog input is connected to an internal, discharged 50 pF
capacitor which then charges to the voltage present at the
–8–
REV. A
AD1876
corresponding pin. The capacitor is disconnected when SAMPLE
is taken LOW and the stored charge is used in the subsequent
A/D conversion. In order to limit the demands placed on the
external source by this high initial charging current, an internal
buffer amplifier is employed between the input and this capaci-
tance for a few hundred nanoseconds. During this time the
input pin exhibits typically 20 kΩ input resistance, 10 pF input
capacitance and ±40 µA bias current. Next, the input is switched
directly to the now precharged capacitor and allowed to fully
settle, after which SAMPLE is taken LOW. During this time
the input sees only a 50 pF capacitor. Once the sample is taken,
the input is internally floated so that the external input source
sees a very high input resistance and a parasitic input capaci-
tance of typically only 2 pF. As a result, the only dominant input
characteristic which must be considered is the high current steps
which occur when the internal buffers are switched in and out.
T he test procedure consists of the following steps. First, the
device is calibrated by its on-board controller. Next, the device
under test digitizes the input waveform. T his conversion is
performed at a 96 kSPS rate and transmits the resulting serial
data to the tester. T he tester performs an FFT on the test data
and determines the actual performance of the device.
AC P ERFO RMANCE
Using the aforementioned test methodology, ac performance
of the AD1876 is measured. AC parameters, which include
S/(N+D), T HD, etc., reflect the AD1876’s effect on the spec-
tral content of the analog input signal. Figures 11 through 15
provide information on the AD1876’s ac performance under a
variety of conditions.
As a general rule, averaging the results from several conversions
reduces the effects of noise and, therefore, improves such pa-
rameters as S/(N+D) and T HD. AD1876 performance is opti-
mized by operating the device at its maximum sample rate of
100 kSPS and digitally filtering the resulting bit stream to the
desired signal bandwidth. T his succeeds in distributing noise
over a wider frequency range, thus reducing the noise density in
the frequency band of interest. T his subject is discussed in the
following section.
In most cases, it is desirable to use external op amps to drive the
AD1876. For ac applications where low cost and low distortion
are desired, the AD711 may be used as shown in Figure 7. An-
other option is the 5532/5534 series. Care should always be
taken with op amp selection—many available op amps do not
meet the necessary low distortion requirements with even mod-
erate loading conditions.
1kΩ
O VERSAMP LING AND NO ISE FILTERING
T he Nyquist rate for a converter is defined as one-half its sam-
pling rate. T his is established by the Nyquist theorem, which
requires that a signal be sampled at a rate corresponding to at
least twice its widest bandwidth of interest in order to preserve
the information content. Oversampling is a conversion tech-
nique in which the sampling frequency is an integral (2 or more)
multiple of twice the frequency bandwidth of interest. In audio
applications, the AD1876 can operate at a 2× oversampling rate.
+12V
0.1µF
V
IN
1kΩ
2
7
6
10
V
AD711
IN
499Ω
4
3
0.1µF
In quantized systems, the information content of the analog in-
put is represented in the frequency spectrum from dc to the
Nyquist rate of the converter. Within this same spectrum are
higher frequency aliased noise components. Antialias, or low-
pass, filters are used at the input to the ADC to remove the por-
tion of these noise components attributed to high frequency
analog input noise. However, wideband noise contributed by the
AD1876 will not be reduced by the antialias filter. T he AD1876
contributed noise is evenly distributed from dc to the Nyquist
rate, and this fact can be used to minimize its overall effect.
AD1876
–12V
8
9
AGND
AGND SENSE
Figure 7.
T he AD1876 contributed noise effects can be reduced by
oversampling—sampling at a rate higher than defined by the
Nyquist theorem. T his spreads the noise energy over a distribu-
tion of frequencies wider than the frequency band of interest,
and by judicious selection of a digital filter, noise frequencies
outside the bandwidth of interest may be eliminated. T he pro-
cess of quantization inherently produces noise, known as quanti-
zation noise. T he magnitude of this noise is a function of the
resolution of the converter, and manifests itself as a limit to the
theoretical signal-to-noise ratio achievable. T his limit is de-
scribed by S/(N+D) = (6.02 n + 1.76 + 10 log FS/2 Fa) dB,
where n is the resolution of the converter in bits, FS is the sam-
pling frequency, and Fa is the signal bandwidth of interest. For
audio bandwidth applications, the AD1876 is capable of operat-
ing at a 2× oversample rate (96 kSPS), which typically produces
an improvement in S/(N+D) of 3 dB compared with operating
at the Nyquist conversion rate of 48 kSPS. Oversampling has
another advantage as well; the demands on the antialias filter are
TESTING TH E AD 1876
Analog Devices employs a high performance mixed signal VLSI
tester to verify the electrical performance of every AD1876. T he
test system consists of two main sections, an input signal gen-
erator and a digital data and control section.
T he stimulus section is responsible for providing a high purity,
noise-free, band limited tone to the input of the device. T his in-
put frequency is 1.06 kHz. T he test tone is passed through a
bandpass filter to remove distortion products and then buffered
by a high performance op amp. An external 5.000 V reference
voltage is also supplied by this section.
T he control section of the test equipment provides an external
clock and the control signals for calibration, conversion and data
transmission. T his section of the tester also contains the pro-
cessing unit that calculates the actual performance of the device
under test.
REV. A
–9–
AD1876
can be programmed to generate an interrupt after the last data
bit is received. T o maximize the conversion rate, SAMPLE
should be brought HIGH immediately after the last data bit is
received.
lessened. In summary, system performance is optimized by run-
ning the AD1876 at or near its maximum sampling rate of
100 kHz and digitally filtering the resulting spectrum to elimi-
nate undesired frequencies.
SIGNAL P RO CESSING
D SP INTERFACE
An audio spectrum analyzer can be produced by combining an
AD1876 and an ADSP-2101 signal processing microcomputer.
T his system can analyze signals from dc to 50 kHz depending
on the sample rate. T his is ideal for applications such as audio
analysis, but could also be applied to vibration analysis as well.
Figure 8 illustrates the use of the Analog Devices ADSP-2101
digital signal processor with the AD1876. T he ADSP-2101 FO
(flag out) pin of serial port 1 (SPORT 1) is connected to the
SAMPLE line and is used to control acquisition of data. T he
ADSP-2101 timer is used to provide precise timing of the FO
pin.
AUD IO D ELAY LINE
A high performance, 16-bit stereo delay line can be constructed
from two AD1876 audio ADCs, a signal processing microcom-
puter and two AD1856 audio DACs. Depending on the length
of the internal buffer which produces the delay, a variable delay
is possible. Other applications are also possible with only a
change in software. For example, a reverb or echo effect could
be generated as well.
ADSP-2101
AD1876
SAMPLE
FO
CLK
D
SCLK0
SERIAL
PORT Ø
DR0
RFS0
DT0
OUT
BUSY
TFS0
AD 1876 AND SM5805 D IGITAL FILTER @ 2 F S
A simple method for generating the required signals for the
AD1876 is to connect one or more AD1876s to an NPC
SM5805 digital filter. T his device supplies all signals required to
operate the AD1876 at a 96 kHz sample rate, which is 2 × FS for
audio applications.
Figure 8. ADSP-2101 Interface
T he SCLK pin of the ADSP-2101 SPORT 0 provides the CLK
input for the AD1876. T he clock should be programmed to be
approximately 2 MHz to comply with AD1876 specifications.
T o minimize digital feedthrough, the clock should be disabled
(by setting Bit 14 in SPORT 0 control register to 0) during data
acquisition. Since the clock floats when disabled, a pull-down
resistor of 12 k–15 kΩ should be connected to SCLK to ensure
it will be LOW at the falling edge of SAMPLE. T o maximize
the conversion rate, the serial clock should be enabled immedi-
ately after SAMPLE is brought LOW (hold mode).
T o minimize group delay distortion, the input to the AD1876 is
filtered only by a low order analog filter. T he AD1876 samples
the output of the filter at 2 FS (96 kHz). T o prevent aliasing, the
SM5805 filters the data with a sharp, linear phase filter rolling
off at 0.5 FS. T he resulting data is decimated to a sample rate of
48 kSPS.
Interfacing the two chips is straightforward, as shown in Figure
9. T he start signal for the AD1876 (for 96 kSPS operation) is
provided by the S/H pin of the SM5805, and CLK is derived
from the BCC pin. Figure 10 illustrates the corresponding tim-
ing diagram.
T he AD1876 BUSY signal is connected to RF0 to notify
SPORT 0 when a new data word is coming. SPORT 0 should be
configured in normal, external, noninverting framing mode and
AD1876*
LEFT
CHANNEL
INPUT
V
10
D
3
IN
OUT
1F (48kHz)
S
CLOCK
CLK SAMPLE
6
12
4
2
2
1
1
DINL
IPARA
LRCK
16
SH
18 BBC
IBLK
DECIMATED
DATA, LEFT
25
24
DOL
DOR
SM5805*
DECIMATED
DATA, RIGHT
8
U/O
11
DINR ISLB IBPOL
OFB
15
CLK SAMPLE
7
10
5
RIGHT
CHANNEL
INPUT
D
V
3
10
IN
OUT
LEFT OPEN OR TIED
TO +5V
AD1876*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD1876 and SM5805 Digital Filter
1/f (f = 48kHz)
s
s
SH
OUTPUT
BBC
1
17
OUTPUT
Lm + 1
Lm
MSB
MSB
MSB
MSB
14
12 13
10 11
10 11
15
15
14
14
6
8
8
9
9
LSB
LSB
12 13
12 13
2
2
3
3
4
4
5
5
7
DINL
DINR
9
9
10 11
15 LSB
6
6
8
8
2
2
3
3
4
4
5
5
7
7
Rm + 1
Rm
12 13 14
LSB
6
10 11
15
7
Figure 10. SM5805 Tim ing Diagram
–10–
REV. A
Typical Dynamic Performance–AD1876
90
80
–0dB INPUT
90
70
60
50
40
80
V
= 10V
REF
–20dB INPUT
70
60
V
= 5V
REF
50
40
30
30
20
10
0
V
= 7V
REF
–60dB INPUT
100
20
0
1k
10k
100k
1M
–80 –70
–60
–50
–40
–30
–20 –10
0
INPUT FREQUENCY – Hz
INPUT AMPLITUDE, REFERRED TO FULL-SCALE – dB
Figure 12. S/(N+D) vs. Input Frequency and Am plitude
Figure 11. S/(N+D) vs. VREF vs. Input Am plitude
Figure 14. IMD Plot for fIN = 1008 Hz (fa), 1055 Hz (fb) at
96 kSPS
Figure 13. 4096 Point FFT at 96 kSPS, fIN = 1.06 kHz
+5V
90
80
70
60
50
40
30
20
+12V
–12V
0
1M
100
1k
10k
100k
RIPPLE FREQUENCY – Hz
Figure 15. Power Supply Rejection (fIN = 1.06 kHz,
fSAMPLE = 96 kSPS, VRIPPLE = 0.3 V p-p)
REV. A
–11–
AD1876
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic D IP (N) P ackage
–12–
REV. A
相关型号：
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