AD1890JN [ADI]
SamplePort Stereo Asynchronous Sample Rate Converters; SamplePort立体声异步采样速率转换器
| 型号： | AD1890JN |
| 厂家： | 
ADI |
| 描述： | SamplePort Stereo Asynchronous Sample Rate Converters |
| 文件： | 总20页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SamplePort Stereo Asynchronous
Sample Rate Converters
a
AD1890/AD1891
SYSTEM D IAGRAM
FEATURES
Autom atically Sense Sam ple Frequencies—No
Program m ing Required
Tolerant of Sam ple Clock J itter
Sm ooth Transition When Sam ple Clock Frequencies
Cross
EXAMPLE
FREQUENCIES:
DAT 48kHz OR
CD 44.1kHz OR
BROADCAST 32kHz
EXAMPLE
FREQUENCIES:
DAT 48kHz OR
CD 44.1kHz OR
BROADCAST 32kHz
AD1890/
AD1891
Accom m odate Dynam ically Changing Asynchronous
Sam ple Clocks
INPUT SAMPLE CLOCK
OUTPUT SAMPLE CLOCK
8 kHz to 56 kHz Sam ple Clock Frequency Range
1:2 to 2:1 Ratio Betw een Sam ple Clocks
–106 dB THD+N at 1 kHz (AD1890)
120 dB Dynam ic Range (AD1890)
Optim al Clock Tracking Control
–Short/ Long Group Delay Modes
–Slow / Fast Settling Modes
OUTPUT SERIAL DATA
INPUT SERIAL DATA
the two clocks. The input and output sample clock frequencies
can nominally range from 8 kHz to 56 kHz, and the ratio
between them can vary from 1:2 to 2:1.
Linear Phase in All Modes
Equivalent of 4 Million 22-Bit FIR Filter Coefficients
Stored On-Chip
Autom atic Output Mute
Flexible Four Wire Serial Interfaces
Low Pow er
T he AD1890/AD1891 use multirate digital signal processing
techniques to construct an output sample stream from the input
sample stream. T he input word width is 4 to 20 bits for the
AD1890 or 4 to 16 bits for the AD1891. Shorter input words
are automatically zero-filled in the LSBs. T he output word
width for both devices is 24 bits. T he user can receive as many
of the output bits as desired. Internal arithmetic is performed
with 22-bit coefficients and 27-bit accumulation. T he digital
samples are processed with unity gain.
APPLICATIONS
Digital Mixing Consoles and Digital Audio Workstations
CD-R, DAT, DCC and MD Recorders
Multitrack Digital Audio and Video Tape Recorders
Studio to Transm itter Links
Digital Audio Signal Routers/ Sw itches
Digital Audio Broadcast Equipm ent
High Quality D/ A Converters
T he input and output control signals allow for considerable flex-
ibility for interfacing to a variety of DSP chips, AES/EBU
receivers and transmitters and for I2S compatible devices. Input
and output data can be independently justified to the left/right
clock edge, or delayed by one bit clock from the left/right clock
edge. Input and output data can also be independently justified
to the word clock rising edge or delayed by one bit clock from
the word clock rising edge. T he bit clocks can also be indepen-
dently configured for rising edge active or falling edge active
operation.
Digital Tape Recorder Varispeed Applications
Com puter Com m unication and Multim edia System s
P RO D UCT O VERVIEW
The AD1890 and AD1891 SamplePorts™ are fully digital, stereo
Asynchronous Sample Rate Converters (ASRCs) that solve sample
rate interfacing and compatibility problems in digital audio equip-
ment. Conceptually, these converters interpolate the input data up
to a very high internal sample rate with a time resolution of 300 ps,
then decimate down to the desired output sample rate. T he
AD1890 is intended for 18- and 20-bit professional applications,
and the AD1891 is intended for 16-bit lower cost applications
where large dynamic sample-rate changes are not encountered.
These devices are asynchronous because the frequency and phase
relationships between the input and output sample clocks (both are
inputs to the AD1890/AD1891 ASRCs) are arbitrary and need not
be related by a simple integer ratio. There is no need to explicitly
select or program the input and output sample clock frequencies, as
the AD1890/AD1891 automatically sense the relationship between
T he AD1890/AD1891 SamplePort™ ASRCs have on-chip digi-
tal coefficients that correspond to a highly oversampled 0 kHz to
20 kHz low-pass filter with a flat passband, a very narrow tran-
sition band, and a high degree of stopband attenuation. A subset
of these filter coefficients are dynamically chosen on the basis of
the filtered instantaneous ratio between the input sample clock
(LR_I) and the output sample clock (LR_O), and these coeffi-
cients are used in an FIR convolver to perform the sample rate
conversion. Refer to the “T heory of Operation” section of this
data sheet for a more thorough functional description. T he low-
pass filter has been designed so that full 20 kHz bandwidth is
maintained when the input and output sample clock frequencies
are as low as 44.1 kHz. If the output sample rate drops below
the input sample rate, the bandwidth of the input signal is
SamplePort and SamplePorts are trademarks of Analog Devices, Inc.
(continued on Page 4)
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD1890/AD1891–SPECIFICATIONS
TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED
Supply Voltage
Ambient T emperature
MCLK
+5.0
25
20
V
°C
MHz
pF
Load Capacitance
100
All minimums and maximums tested except as noted.
P ERFO RMANCE (Guaranteed over 0°C ≤ T A ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
Min
Max
Units
AD1890 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)†
AD1891 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)†
T otal Harmonic Distortion + Noise†
120
96
dB
dB
dB
AD1890 and AD1891 (20 Hz to 20 kHz, Full-Scale Input,
F
SOUT /FSIN Between 0.5 and 2.0)
–94
–106
–100
–96
–95
0
dB
dB
dB
dB
dB
Degrees
ns
AD1890 (1 kHz Full-Scale Input, FSOUT /FSIN Between 0.7 and 1.4)
AD1890 (10 kHz Full-Scale Input, FSOUT /FSIN Between 0.7 and 1.4)
AD1891 (1 kHz Full-Scale Input, FSOUT /FSIN Between 0.7 and 1.4)
AD1891 (10 kHz Full-Scale Input, FSOUT /FSIN Between 0.7 and 1.4)
Interchannel Phase Deviation†
Input and Output Sample Clock Jitter†
10
(For
≤ 1 dB Degradation in T HD+N with 10 kHz Full-Scale Input, Slow-Settling Mode)
D IGITAL INP UTS (Guaranteed over 0°C ≤ TA ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
Min
Max
Units
VIH
2.2
V
VIL
0. 8
4
4
V
IIH @ VIH = +5 V
IIL @ VIL = 0 V
VOH @ IOH = –4 mA
VOL @ IOL = 4 mA
Input Capacitance†
µA
µA
V
V
pF
3.6
0.4
15
D IGITAL TIMING (Guaranteed over 0°C ≤ TA ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
Min
50
Max
Units
tMCLK
fMCLK
tMPWL
tMPWH
fLRI
MCLK Period
125
20
ns
MHz
ns
ns
kHz
ns
ns
ns
MHz
ns
ns
MCLK Frequency (1/tMCLK
MCLK LO Pulse Width
MCLK HI Pulse Width
LR_I Frequency with 20 MHz MCLK†
RESET LO Pulse Width
)
8
20
20
10
100
15
80
70
tRPWL
tRS
RESET Setup to MCLK Falling
BCLK_I/O Period†
tBCLK
fBCLK
tBPWL
tBPWH
tWSI
tWSO
tLRSI
tLRSO
tDS
BCLK_I/O Frequency (l/tBCLK)†
BCLK_I/O LO Pulse Width
BCLK_I/O HI Pulse Width
WCLK_I Setup to BCLK_I
WCLK_O Setup to BCLK_O
LR_I Setup to BCLK_I
12.5
40
40
15
30
15
30
0
ns
ns
ns
ns
LR_O Setup to BCLK_O
Data Setup to BCLK_I
ns
tDH
Data Hold from BCLK_I
25
ns
tDPD
tDOH
Data Propagation Delay from BCLK_O
Data Output Hold from BCLK_O
40
ns
ns
5
REV. 0
–2–
AD1890/AD1891
P O WER (0°C ≤ T A ≤ 70°C, MCLK = 16 MH z, FSIN = 48 kHz, FSOUT = 44.1 kHz)
Min
Typ
Max
Units
Supplies
Voltage, VDD
2.7
5.5
40
V
mA
mA
Current, IDD (VDD = 5.0 V)
Current, IDD (VDD = 3.0 V)
Dissipation
35
19
Operation (VDD = 5.0 V)
Operation (VDD = 3.0 V)
175
57
200
mW
mW
TEMP ERATURE RANGE
Min
Max
Units
Specifications Guaranteed
Operation Guaranteed
Storage
0
–40
–60
+70
+85
+100
°C
°C
°C
ABSO LUTE MAXIMUM RATINGS*
Min
Max
Units
VDD to GND
–0.3
7.0
V
DC Input Voltage
Latch-Up T rigger Current
Soldering
–0.3
–1000
VDD + 0.3
+1000
+300
10
V
mA
°C
sec
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. T his is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
D IGITAL FILTER CH ARACTERISTICS†
Min
Max
Units
Passband Ripple (0 to 20 kHz)
T ransition Band1
Stopband Attenuation
0.01
4. 1
dB
kHz
dB
µs
110
700
Group Delay (LR–I = 50 kHz)
3000
†Guaranteed. Not T ested
1Valid only when FSOUT ≥ FSIN (i.e., upsampling), FSIN = 44.1 kHz.
Specifications subject to change without notice.
O RD ERING GUID E
Tem perature Range P ackage D escription P ackage O ption
Model
AD1890JN
AD1890JP
AD1891JN
AD1891JP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Plastic DIP
PLCC
Plastic DIP
PLCC
N-28
P-28A
N-28
P-28A
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD 1890/AD 1891 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD1890/AD1891
(continued from Page 1)
GPDLYS (AD1890)
N/C (AD1891)
1
2
28 SETSLW
27 GND
SERIAL IN
P RO D UCT O VERVIEW (Continued)
MCLK
DATA_I
BCLK_I
WCLK_I
LR_I
automatically limited to avoid alias distortion on the output sig-
nal. T he AD1890/AD1891 dynamically alter the low-pass filter
cutoff frequency smoothly and slowly, so that real-time varia-
tions in the sample rate ratio are possible without degradation of
the audio quality.
3
BCLK_O
WCLK_O
LR_O
26
25
24
23
22
SERIAL OUT
4
5
ACCUM
6
DATA_O
T he AD1890/AD1891 have a pin selectable slow- or fast-settling
mode. T his mode determines how quickly the ASRCs adapt to a
change in either the input sample clock frequency (FSIN) or the
output sample clock frequency (FSOUT ). In the slow-settling
mode, the control loop which computes the ratio between FSIN
and FSOUT settles in approximately 800 ms and begins to reject
jitter above 3 Hz. T he slow-settling mode offers the best signal
quality and the greatest jitter rejection. In the fast-settling mode,
the control loop settles in approximately 200 ms and begins to
reject jitter above 12 Hz. T he fast-settling mode allows rapid,
real time sample rate changes to be tracked without error, at the
expense of some narrow-band noise modulation products on the
output signal.
7
V
V
DD
DD
MULT
8
21 GND
GND
N/C
9
20 N/C
10
11
12
13
14
19 BKPOL_O
18 TRGLR_O
BKPOL_I
TRGLR_I
MSBDLY_I
RESET
COEF ROM
FIFO
17
16
15
MSBDLY_O
MUTE_O
MUTE_I
CLOCK
TRACKING
GND
AD1890/AD1891
N/C = NO CONNECT
T he AD1890 also has a pin selectable, short or long group delay
mode. T his pin determines the depth of the First-In, First-Out
(FIFO) memory which buffers the input data samples before
they are processed by the FIR convolver. In the short mode, the
group delay is approximately 700 µs. T he ASRC is more sensi-
tive to sample rate changes in this mode (i.e., the pointers which
manage the FIFO are more likely to cross and become momen-
tarily invalid during a sample rate step change), but the group
delay is minimized. In the long mode, the group delay is ap-
proximately 3 ms. T he ASRC is tolerant of large dynamic
sample rate changes in this mode, and it should be used when
the device is required to track fast sample rate changes, such as
in varispeed applications. T he AD1891 features the short group
delay mode only. In either device, if the read and write pointers
that manage the FIFO cross (indicating underflow or overflow),
the ASRC asserts the mute output (MUT E_O) pin HI for 128
output clock cycles. If MUT E_O is connected to the mute input
(MUT E_I) pin, as it normally should be, the serial output will
be muted (i.e., all bits zero) during this transient event.
AD1890/AD1891 DIP Pinout
4
3
2
1
28
27
26
SERIAL IN
SERIAL OUT
5
25
24
23
22
WCLK_I
WCLK_O
LR_O
6
LR_I
ACCUM
MULT
7
V
DATA_O
DD
8
GND
V
DD
9
21 GND
20
19 BKPOL_O
N/C
COEF ROM
FIFO
10
N/C
BKPOL_I
CLOCK
TRACKING
11
TRGLR_I
T he AD1890/AD1891 are fabricated in a 0.8 µm single poly,
double metal CMOS process and are packaged in a 0.6" wide
28-pin plastic DIP and a 28-pin PLCC. T he AD1890/AD1891
operate from a +5 V power supply over the temperature range of
0°C to +70°C.
AD1890/AD1891
12
13
14
15
16
17
18
N/C = NO CONNECT
AD1890/AD1891 PLCC Pinout
REV. 0
–4–
AD1890/AD1891
D EFINITIO NS
Gr oup D elay
D ynam ic Range
Intuitively, the time interval required for a full-level input pulse
to appear at the converter’s output, at full level, expressed in
milliseconds (ms). More precisely, the derivative of radian phase
with respect to radian frequency at a given frequency.
T he ratio of a near full-scale input signal to the integrated noise
in the passband (0 to ≈20 kHz), expressed in decibels (dB). Dy-
namic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result.
Tr anspor t D elay
Total H ar m onic D istor tion + Noise
T he time interval between when an impulse is applied to the
converters input and when the output starts to be affected by
this impulse, expressed in milliseconds (ms). T ransport delay is
independent of frequency.
T otal Harmonic Distortion plus Noise (T HD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the harmonics and noise to the rms value of a sinusoidal
input signal. It is usually expressed in percent (%) or decibels.
Inter channel P hase D eviation
Difference in input sampling times between stereo channels, ex-
pressed as a phase difference in degrees between 1 kHz inputs.
AD 1890/AD 1891 P IN LIST
Ser ial Input Inter face
P in Nam e Num ber
I/O D escription
DAT A_I
3
I
Serial input, MSB first, containing two channels of 4- to 20-bits of twos-complement data per
channel. AD1891 ONLY: Maximum of 16 data bits per channel; additional bits ignored.
Bit clock input for input data.
Word clock input for input data. T his input is rising edge sensitive. (Not required in LR input data
clock triggered mode [T RGLR_I = HI].)
BCLK_I
WCLK_I
4
5
I
I
LR_I
6
I
Left/right clock input for input data. Must run continuously.
Ser ial O utput Inter face
P in Nam e Num ber
I/O D escription
DAT A_O 23
O
Serial output, MSB first, containing two channels of 4- to 24-bits of twos-complement data per
channel.
BCLK_O
WCLK_O 25
26
I
I
Bit clock input for output data.
Word clock input for output data. T his input is rising edge sensitive. (Not required in LR output
data clock triggered mode [T RGLR_O = HI].)
Left/right clock input for output data. Must run continuously.
LR_O
24
I
Input Contr ol Signals
P in Nam e Num ber
I/O D escription
BKPOL_I 10
T RGLR_I 11
MSBDLY_I 12
I
I
I
Bit clock polarity. LO: Normal mode. Input data is sampled on rising edges of BCLK_I. HI:
Inverted mode. Input data is sampled on falling edges of BCLK_I.
T rigger on LR_I. HI: Changes in LR_I indicate beginning1 of valid input data. LO: Rising edge of
WCLK_I indicates beginning of valid input data.
MSB delay. HI: Input data is delayed one BCLK_I after either LR_I (T RGLR_I = HI) or WCLK_I
(T RGLR_I = LO) indicates the beginning of valid input data. Included for I2S data format
compatibility. LO: No delay.
NOT E
1T he beginning of valid data will be delayed by one BLCK_I if MSBDEL_I is selected (HI).
REV. 0
–5–
AD1890/AD1891
O utput Contr ol Signals
P in Nam e
Num ber
I/O
D escription
BKPOL_O
19
I
Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed
on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on rising.
T RGLR_O 18
MSBDLY_O 17
I
I
T rigger on LR_O. HI: Changes in LR_O indicate beginning1 of valid output data. LO: Rising
edge of WCLK_O indicates beginning of valid output data.
MSB delay. HI: Output data is delayed one BCLK_O after either LR_O (T RGLR_O = HI) or
WCLK_O (T RGLR_O = LO) indicates the beginning of valid output data. Included for I2S data
format compatibility. LO: No delay.
Miscellaneous
P in Nam e
Num ber
I/O
D escription
GPDLYS
1
I
AD1890 ONLY: Group delay—short. HI: Short group delay mode (≈700 µs). More sensitive to
changes in sample rates (LR clocks). LO: Long group delay mode (≈3 ms). More tolerant of
sample rate changes. T his signal may be asynchronous with respect to MCLK, and dynamically
changed, but is normally pulled up or pulled down on a static basis. AD1891: Short group delay
mode only; this pin is a N/C.
MCLK
2
I
Master clock input. Nominally 16 MHz for sampling frequencies (FS, word rates) from 8 kHz to
56 kHz. Exact frequency is not critical, and does not need to be synchronized to any other clock
or possess low jitter.
RESET
13
16
I
Active LO reset. Set HI for normal chip operation.
MUT E_O
O
Mute output. HI indicates that data is not currently valid due to read and write FIFO memory
pointer overlap. LO indicates normal operation.
MUT E_I
15
I
I
Mute input. HI mutes the serial output to zeros (midscale). Normally connected to MUT E_O.
Reset LO for normal operation.
SET LSLW 28
Settle slowly to changes in sample rates. HI: Slow-settling mode (≈800 ms). Less sensitive to
sample clock jitter. LO: Fast-settling mode (≈200 ms). Some narrow-band noise modulation may
result from jitter on LR clocks. T his signal may be asynchronous with respect to MCLK, and
dynamically changed, but is normally pulled up or pulled down on a static basis.
N/C
9, 20
No connect. Reserved. Do not connect.
P ower Supply Connections
P in Nam e Num ber
I/O D escription
VDD
7, 22
I
I
Positive digital voltage supply.
GND
8, 14, 21, 27
Digital ground. Pins 14 and 27 need not be decoupled.
NOT E
1T he beginning of valid data will be delayed by one BCLK_O if MSBDEL _O is selected (Hl).
REV. 0
–6–
AD1890/AD1891
TH EO RY O F O P ERATIO N
implemented as a register, Plot D in Figure 1) and then asyn-
chronously resampled at the output sample frequency (Plot E in
Figure 1). T his resampling can be thought of as a decimation
operation since only a very few samples out of the great many
interpolated samples are retained. T he output values represent
the “nearest” values, in a temporal sense, produced by the inter-
polation operation. T here is always some error in the output
sample amplitude due to the fact that the output sampling
switch does not close at a time that exactly corresponds to a
point on the fine time scale of the interpolated sequence. How-
ever, this error can be made arbitrarily small by using a very
large interpolation ratio. T he AD1890/AD1891 SamplePort
ASRCs use an equivalent IRAT IO of 65,536 to provide 16-bit
accuracy (≈ –96 dB T HD+N) across the 0 to 20 kHz audio
band.
T here are at least two logically equivalent methods of explaining
the concept of asynchronous sample rate conversion: the high
speed interpolation/decimation model and the polyphase filter
bank model. Using the AD1890 and AD1891 SamplePorts does
not require understanding either model. T his section is included
for those who wish a deeper understanding of their operation.
Inter polation/D ecim ation Model
In the high speed interpolation/decimation model, illustrated in
Figure 1, the sampled data input signal (Plot A in Figure 1) is
interpolated at some ratio (IRAT IO) by inserting IRAT IO-1
zero valued samples between each of the original input signal
samples (Plot B in Figure 1). T he frequency domain characteris-
tics of the input signal are unaltered by this operation, except
that the zero-padded sequence is considered to be sampled at a
frequency which is the product of original sampling frequency
multiplied by IRAT IO.
T he number of FIR filter taps and associated coefficients is
approximately 4 million. T he equivalent FIR filter convolution
frequency (or “upsample” frequency) is 3.2768 GHz, and the
fine time scale has resolution of about 300 ps. Various propri-
etary efficiencies are exploited in the AD1890/AD1891 ASRCs
to reduce the complexity and throughput requirements of the
hardware implied by this interpolation/decimation model.
T he zero-padded values are fed into a digital FIR low-pass filter
(Plot C in Figure 1) to smooth or integrate the sequence, and
limit the bandwidth of the filter output to 20 kHz. T he interpo-
lated output signal has been quantized to a much finer time
scale than the original sequence. T he interpolated sequence is
then passed to a zero-order hold functional block (physically
D
E
A
B
C
FIR LOW
PASS
FILTER
ZERO ORDER
HOLD
REGISTER
OUTPUT
SIGNAL
INPUT
SIGNAL
RESAMPLING
DECIMATION
ZERO STUFF
INTERPOLATION
AMP
A
TIME
B
C
D
E
Figure 1. Interpolation/Decim ation Model—Tim e Dom ain View
REV. 0
–7–
AD1890/AD1891
are adequately sampled). T he baseband magnitude and phase
responses of the subfilters are identical. T he out-of-band (i.e.,
alias) regions of the subfilters however have phase responses
which are shifted relative to one another, in a manner that
causes them to cancel when they are summed.
P olyphase Filter Bank Model
Although less intuitively understandable than the interpolation/
decimation model, the polyphase filter bank model is useful to
explore because it more accurately portrays the operation of the
actual AD1890/AD1891 SamplePort hardware. In the polyphase
filter bank model, the stored FIR filter coefficients are thought
of as the impulse response of a highly oversampled 0 to 20 kHz
low-pass prototype filter, as shown in Figure 2. If this low-pass
filter is oversampled by a factor of N, then it can be conceptu-
ally decomposed into N different “subfilters,” each filter consist-
ing of a different subset of the original set of impulse response
samples. If the temporal position of each of the subfilters is
maintained, then they can be summed to recreate the original
oversampled impulse response. Since the original impulse
response is highly oversampled, the more sparsely sampled
subfilters still individually meet the Nyquist criterion (i.e., they
T he subfilter coefficients are then aligned to the left, as shown
in Figure 3, so that the first coefficient of each subfilter is
aligned to the first point on a coarse time scale. (T his concep-
tual step accounts for how the hardware implementation is able
to operate at the slower rate corresponding to the coarse time
scale.) Each subfilter has been shifted in time by a different
amount, and though they still share identical magnitude
responses, they now have in-band phase responses which have
fractionally different slopes (i.e., group delays).
PHASE
90
OVERSAMPLED
LOW PASS FILTER
IMPULSE RESPONSE
AMP
180
0 Deg
270
AMP
TIME
FREQ
1/4Fs
1/4Fs
1/4Fs
1/4Fs
1/4Fs
1/2Fs
3/4Fs
3/4Fs
3/4Fs
3/4Fs
3/4Fs
Fs
Fs
Fs
Fs
Fs
DECOMPOSED INTO
FOUR SUBFILTERS
1/2Fs
1/2Fs
1/2Fs
1/2Fs
Figure 2. Four Polyphase Subfilters in the Tim e and Frequency Dom ains
REV. 0
–8–
AD1890/AD1891
AMP
PHASE
F
/2
sin
FREQ
TIME
DELAY = NOMINAL
SUBFILTER COEFFICIENTS
ALIGNED TO THE LEFT
F
/2
T
= 1/F
sin
sin
sin
DELAY = NOMINAL
F
/2
sin
DELAY = NOMINAL – .25/F
sin
F
/2
sin
DELAY = NOMINAL – .5/F
sin
F
/2
sin
DELAY = NOMINAL – .75/F
sin
Figure 3. Four Polyphase Subfilters Realigned to Coarse Tim e Grid
PARALLEL POLYPHASE
FILTER BANK
T he full set of subfilters can be considered to form a parallel
bank of “polyphase” filters which have decrementing, linear
phase group delays. All of the polyphase filters conceptually pro-
cess the input signal simultaneously, as illustrated in Figure 4, at
the input sample rate.
POLYPHASE FILTER 1
POLYPHASE FILTER 2
POLYPHASE FILTER 3
POLYPHASE FILTER 4
POLYPHASE FILTER 5
POLYPHASE FILTER 6
POLYPHASE FILTER 7
N TO 1
MUX
INPUT
SIGNAL
OUTPUT
SIGNAL
POLYPHASE FILTER N-1
POLYPHASE FILTER N
SELECT
SAMPLE
CLOCK
TRACKING
CIRCUIT
Figure 4. Polyphase Filter Bank Model—Conceptual Block
Diagram
REV. 0
–9–
AD1890/AD1891
Asynchronous sample rate conversion under the polyphase filter
bank model is accomplished by selecting the output of a particu-
lar polyphase filter on the basis of the temporal relationship be-
tween the input sample clock and the output sample clock
events. Figure 5 shows the desired filter group delay as a func-
tion of the relative time difference between the current output
sample clock and the last input sample clock. If an output
sample is requested late in the input sample period, then a short
filter delay is required, and if an output sample is requested
early in the input sample period, then a long filter delay is re-
quired. T his nonintuitive result arises from the fact that FIR fil-
ters always produce some delay, so that selecting a filter with
shorter delay moves the interpolated sample closer to the newest
input sample.
LARGE
OFFSET
SMALL
OFFSET
OFFSET INTO DENSE FIR FILTER COEFFICIENT ARRAY
TO ACCESS REQUIRED POLYPHASE FILTER
LONG
DELAY
SHORT
DELAY
REQUIRED FILTER GROUP DELAY TO
COMPUTE REQUESTED OUTPUT SAMPLE
A
B
AMPLITUDE
AMPLITUDE
INPUT SEQUENCE
A short delay corresponds to a large offset into the dense FIR
filter coefficient array, and a long delay corresponds to a small
offset. Note that because the output sample clock can arrive at
any arbitrary time with respect to the input sample clock, the
selection of a polyphase filter with which to convolve the input
sequence occurs on every output sample clock event. Occasion-
ally the FIFO which holds the input sequence in the FIR con-
volver is either not incremented, or incremented by two between
output sample clocks (see periods A and B in Figure 5); this
happens more often when the input and output sample clock
frequencies are dissimilar than when they are close together.
However, in this situation, an appropriate polyphase filter is
selected to process the input signal, and thus an accurate output
sample is computed. Input and output samples are not skipped
or repeated (unless the input FIFO underflows or overflows), as
is the case in some other sample rate converter implementations.
T o obtain an accurate conversion, a large number of polyphase
filters are needed. T he AD1890/AD1891 SamplePorts use the
equivalent of 65,536 polyphase filters to achieve their profes-
sional audio quality distortion and dynamic range specifications.
PAST
OUTPUT SEQUENCE
FUTURE
Figure 5. Input and Output Clock Event Relationship
T he AD1890/AD1891 SamplePorts solve this problem by
embedding the ratio computation circuit within a digital servo
control loop, as shown in Figure 6. T his control loop includes
special provisions, to allow for the accurate tracking of dynami-
cally changing sample rates. T he outputs of the control loop are
the starting read addresses for the input data FIFO and the filter
coefficient ROM. T hese start addresses are used by the FIFO
and ROM address generators, as shown in Figure 6.
T he input data FIFO write address is generated by a counter
which is clocked by the input sample clock (i.e., LR_I). It is very
important that the FIFO read address and the FIFO write ad-
dress do not cross, as this means that the FIFO has either
underflowed or overflowed. T his consideration affects the
choice of settling time of the control loop. When a step change
in the sample rate occurs, the relative positions of the read and
write addresses will change while the loop is settling. A fast set-
tling loop will act to keep the FIFO read and write addresses
separated better than a slow settling loop. T he AD1890/
AD1891 include a user selectable pin (SET LSLW) to set the
loop settling time that essentially changes the coefficients of the
digital servo control loop filter. T he state of the SET LSLW pin
can be changed on-the-fly but is normally set and forgotten.
Sam ple Clock Tr acking
It should be clear that, in either model, the correct computation
of the ratio between the input sample rate (as determined from
the left/right input clock, LR_I) and the output sample rate (as
determined from the left/right output clock, LR_O) is critical to
the quality of the output data stream. It is straightforward to
compute this ratio if the sample rates are fixed and synchronous;
the challenge is to accurately track dynamically varying and
asynchronous sample rates, as well as to account for jitter.
WCLK_I
LR_I
BCLK_I
LR_I
FIFO WRITE
ADDRESS
GENERATOR
SERIAL DATA
INPUT UNIT
DATA_I
FIFO READ
ADDRESS
GENERATOR
WCLK_O
FIFO
BCLK_O
LR_O
SAMPLE CLOCK RATIO
SERVO CONTROL LOOP
START
ADDRESS
SERIAL DATA
OUTPUT UNIT
ACCUMULATOR
DATA_O
POLYPHASE FILTER
SELECTOR
LR_O
(F
LR_I
(F
POLYPHASE
COEFFICIENT
ROM
ROM ADDRESS
GENERATOR
)
)
SOUT
SIN
F
< F
SIN
SOUT
FIR CONVOLVER
FREQUENCY
RESPONSE
COMPRESSION
LR_I
LR_O
Figure 6. AD1890/AD1891 Functional Block Diagram
–10–
REV. 0
AD1890/AD1891
Sam ple Clock Jitter Rejection
5 kHz digital sinusoid is applied to the ASRC, depending on the
settling mode selected, the ASRC will attenuate sample clock
jitter at either 3 Hz above and below 5 kHz (slow settling) or
12 Hz above and below 5 kHz (fast settling). T he rolloff is 6 dB
per octave. As an example, suppose there was correlated jitter
present on the input sample clock with a 1 kHz component,
associated with the same 5 kHz sinusoidal input data. T his
would produce sidebands at 4 kHz and 6 kHz, 3 kHz and
7 kHz, etc., with amplitudes that decrease as they move away
from the input signal frequency. For the slow settling mode
case, 1 kHz represents more than nine octaves (relative to
3 Hz), so the first two sideband pairs would be attenuated by
more than 54 dB. For the fast settling mode case, 1 kHz repre-
sents more than seven octaves (relative to 12 Hz), so that the
first two sideband pairs would be attenuated by more than
42 dB. T he second and higher sideband pairs are attenuated
even more because they are spaced further from the input signal
frequency.
T he loop filter settling time also affects the ability of the
AD1890/AD1891 ASRCs to reject sample clock jitter, since the
control loop effectively computes a time weighted average or
“estimated” new output of many past input and output clock
events. T his first order low pass filtering of the sample clock
ratio provide the AD1890/AD1891 with their jitter rejection
characteristic. In the slow settling mode, the AD1890/AD1891
attenuate jitter frequencies higher than 3 Hz (≈800 ms for the
control loop to settle to an 18-bit “pure” sine wave), and thus
reject all but the most severe sample clock jitter; performance is
essentially limited only by the FIR filter. In the fast settling
mode, the ASRCs attenuate jitter components above 12 Hz
(≈200 ms for the control loop to settle). Due to the effects of
on-chip synchronization of the sample clocks to the 16 MHz
(62.5 ns) MCLK master clock, sample clock jitter must be a
large percentage of the MCLK period (>10 ns) before perfor-
mance degrades in either the slow or fast settling modes. Note
that since both past input and past output clocks are used to
compute the filtered “current” internal output clock request, jit-
ter on both the input sample clock and the output sample clock
is rejected equally. In summary: the fast settling mode is best for
applications when the sample rates will be dynamically altered
(e.g., varispeed situations) while the slow settling mode provides
the most sample clock jitter rejection.
Gr oup D elay Modes
T he other parameter that determines the likelihood of FIFO in-
put overflow or output underflow is the FIFO depth. T his is the
parameter that is selected by the GPDLYS pin (AD1890 only;
this pin is a No Connect for the AD1891). T he drawback with
increasing the FIFO depth is increasing the device’s overall
group delay, but most applications are insensitive to a small in-
crease in group delay. [T his FIFO-induced group delay is better
termed transport delay, since it is frequency independent, and
should be kept conceptually distinct from the notion of group
delay as used in the polyphase filter bank model. T he total
group delay of the AD1890/AD1891 equals the FIFO transport
delay plus the FIR (polyphase) filter group delay.]
Clock jitter can be modeled as a frequency modulation process.
Figure 7 shows one such model, where a noise source combined
with a sine wave source modulates the “carrier” frequency gen-
erated by a voltage controlled oscillator.
NOISE SOURCE
NOISE
In the short group delay mode, the FIFO read and write point-
ers are separated by five memory locations (≈100 µs equivalent
transport delay at a 50 kHz sample rate). T his is added to the
FIR filter delay (64 taps divided by 2) for a total nominal group
delay in short mode of ≈700 µs. T he short group delay mode is
useful when the input and output sample clocks are asynchro-
nous but either do not vary or change very slowly.
WAVEFORM
SINE
WAVE
VCO
Σ
In the long group delay mode (AD1890 only, the AD1891 is
always in the short group delay mode), the FIFO read and write
pointers are separated by 96 memory locations (≈2 ms equiva-
lent transport delay). T his is added to the FIR filter delay
(64 taps divided by 2) for a total nominal group delay in long
mode of ≈3 ms. T he long group delay mode is useful when the
input and output sample clocks are asynchronous and changing
relative to one another, such as during varispeed effects.
VOLTAGE
SOURCE
DIGITAL
OUT
ADC
ANALOG IN
Figure 7. Clock J itter Modeled as a Modulated VCO
If the jittered output of the VCO is used to clock an analog-to-
digital converter, the digital output of the ADC will be contami-
nated by the presence of jitter. If the noise source is spectrally
flat (i.e., “white” jitter), then an FFT of the ADC digital output
would show a spectrum with a uniform noise floor which is el-
evated compared to the spectrum with the noise source turned
off. If the noise source has distinct frequency components (i.e.,
“correlated” jitter), then an FFT of the ADC digital output
would show symmetrical sidebands around the ADC input sig-
nal, at amplitudes and frequencies determined by frequency
modulation theory. One notable result is that the level of the
noise or the sidebands is proportional to the slope of the input
signal, i.e., the worst case occurs at the highest frequency full-
scale input (a full-scale 20 kHz sinusoid).
T hese delays are deterministic and constant except when FSOUT
drops below FSIN which causes the number of FIR filter taps to
increase (see “Cutoff Frequency Modification” below). In either
mode, if the FIFO read and write addresses cross, the MUTE_O
signal will be asserted. Note that in all modes and under all con-
ditions, both the highly oversampled low-pass prototype and the
polyphase subfilters of the AD1890/AD1891 ASRCs possess a
linear phase response.
T he AD1890 has been designed so that when it is in long group
delay mode and fast settling mode, a full 2:1 step change (i.e.,
occurring between two samples) in sample frequency ratio can
be tolerated without output mute.
T he AD1890/AD1891 apply rejection to these jitter frequency
components referenced to the input signal. In other words, if a
REV. 0
–11–
AD1890/AD1891
When the AD1890/AD1891 output sample frequency is higher
than the input sample frequency (i.e., upsampling operation),
the cutoff frequency of the FIR polyphase filter can be greater
than 20 kHz. T he cutoff frequency of the FIR filter during
upsampling is given by the following relation:
Cutoff Fr equency Modification
The final important operating concept of the ASRCs is the mod-
ification of the filter cutoff frequency when the output sample
rate (FSOUT ) drops below the input sample rate (FSIN), i.e.,
during downsampling operation. T he AD1890/AD1891 auto-
matically reduces the polyphase filter cutoff frequency under
this condition. T his lowering of the cutoff frequency (i.e., the
reduction of the input signal bandwidth) is required to avoid
alias distortion. T he AD1890/AD1891 SoundPorts take advan-
tage of the scaling property of the Fourier transform which can
be stated as follows: if the Fourier transform of f(t) is F(w), then
the Fourier transform of f(k × t) is F(w/k). T his property can be
used to linearly compress the frequency response of the filter,
simply by multiplying the coefficient ROM addresses (shown in
Figure 6) by the ratio of FSOUT to FSIN whenever FSOUT is less
than FSIN. T his scaling property works without spectral distor-
tion because the time scale of the interpolated signal is so dense
(300 ps resolution) with respect to the cutoff frequency that the
discrete-time representation is a close approximation to the con-
tinuous time function.
Upsampling Cutoff Frequency = (FSIN/44.1 kHz) × 20 kHz
Noise and D istor tion P henom ena
T here are three noise/distortion phenomena that limit the per-
formance of the AD1890/AD1891 ASRCs. First, there is
DOWN-
SAMPLING
UPSAMPLING
128
64
0.5
1.0
1.5
2.0
FSOUT /FSIN
T he cutoff frequency (–3 dB down) of the FIR filter during
downsampling is given by the following relation:
Figure 8. Num ber of Filter Taps as a Function of
SOUT/FSlN
Downsampling Cutoff Frequency = (FSOUT /44.1 kHz) × 20 kHz
F
T he AD1890/AD1891 frequency response compression circuit
includes a first order low-pass filter to smooth the filter cutoff
frequency selection during dynamic sample rate conditions.
T his allows the ASRC to avoid objectionable clicking sounds
that would otherwise be imposed on the output while the loop
settles to a new sample rate ratio. Hysteresis is also applied to
the filter selection with approximately 300 Hz of cutoff fre-
quency “noise margin,” which limits the available selection of
cutoff frequencies to those falling on an approximately 300 Hz
frequency grid. T hus if a particular sample frequency ratio was
reached by sliding the output sample frequency up, it is possible
that a filter will be chosen with a cutoff frequency that could dif-
fer by as much as 300 Hz from the filter chosen when the same
sample frequency ratio was reached by sliding the output sample
frequency down. T his is necessary to ensure that the filter selec-
tion is stable even with severely jittered input sample clocks.
broadband, Gaussian noise which results from polyphase filter
selection quantization. Even though the AD1890/AD1891 have
a large number of polyphase filters (the equivalent of 65,536) to
choose from, the selection is not infinite. Second, there is
narrow-band noise which results from the non-ideal synchroni-
zation of the sample clocks to the system clock MCLK, which
leads to a non-ideal computation of the sample clock ratio,
which leads to a non-ideal polyphase filter selection. T his noise
source is narrowband because the digital servo control loop
averages the polyphase filter selection, leading to a strong corre-
lation between selections from output to output. In slow mode,
the selection of polyphase filters is completely unaffected by the
clock synchronization. In fast mode, some narrowband noise
modulation may be observed with very long FFT measure-
ments. T his situation is analogous to the behavior of a phase
locked loop when presented with a noisy or jittered input.
T hird, there are distortion components that are due to the
non-infinite stopband rejection of the low-pass filter response.
Non-infinite stopband rejection means that some amount of
out-of-band spectral energy will alias into the baseband. T he
AD1890/AD1891 performance specifications include the effects
of these phenomena.
Note that when the filter cutoff frequency is reduced, the transi-
tion band of the filter becomes narrower since the scaling prop-
erty affects all filter characteristics. T he number of FIR filter
taps necessarily increases because there are now a smaller num-
ber of longer length polyphase filters. Nominally, when FSOUT is
greater than FSIN, the number of taps is 64. When FSOUT is less
than FSIN, the number of taps linearly increase to a maximum of
128 when the ratio of FSOUT , to FSIN equals 1:2. T he number of
filter taps as a function of sample clock ratio is illustrated in Fig-
ure 8. T he natural consequence of this increase in filter taps is
an increase in group delay.
Note that Figures 15 through 17 are shown with full-scale input
signals. T he distortion and noise components will scale with the
input signal amplitude. In other words, if the input signal is at-
tenuated by –20 dB, the distortion and noise components will
also be attenuated by –20 dB. T his dependency holds until the
effects of the 20-bit input quantization are reached.
REV. 0
–12–
AD1890/AD1891
O P ERATING FEATURES
Ser ial Input/O utput P or ts
appearance of the MSB of data is synchronous with the rising
edge of the left/right clock for the left channel and the falling
edge of left/right clock for the right channel. T he MSB is
delayed by one bit clock after the left/right clock if the MSB
delay mode is selected. T he word clock is not required in the
left/right clock triggered mode, and should be tied either HI or
LO. Figure 23 shows the bit clock in the optional gated or burst
mode; the bit clock is inactive between data fields, and can take
either the HI state or the LO state while inactive.
T he AD1890/AD1891 use the frequency of the left/right input
clock (LR_I) and the left/right output clock (LR_O) signals to
determine the sample rate ratio, and therefore these signals must
run continuously and transition twice per sample period. (T he
LR_I clock frequency is equivalent to FSIN and the LR_O clock
frequency is equivalent to FSOUT .) T he other clocks (WCLK_I,
WCLK_O, BCLK_I, BCLK_O) are edge sensitive and may be
used in a gated or burst mode (i.e., a stream of pulses during
data transmission or reception followed by periods of inactivity).
T he word clocks and bit clocks are used only to write data into
or read data out of the serial ports; only the left/right clocks are
used in the internal DSP blocks. It is important that the left/
right clocks are “clean” with monotonic rising and falling edge
transitions and no excessive overshoot or undershoot which
could cause false triggering on the AD1890/AD1891.
Note that there is no requirement for a delay between the left
channel data and the right channel data. T he left/right clocks
and the word clocks can transition immediately after the LSB of
the data, so that the MSB of the subsequent channel appears
without any timing delay. T he AD1891 is therefore capable of a
32-bit frame mode, in which both 16-bit channels are packed
into a 32-bit clock period. More generally, there is no particular
requirement for when the left/right clock falls (i.e., there is no
left/right clock duty cycle or pulse width specification), provided
that the left/right clock frequency equals the intended sample
frequency, and there are sufficient bit clock periods to clock in
or out the intended number of data bits.
T he AD1890/AD1891’s flexible serial input and output ports
consume and produce data in twos-complement, MSB-first
format. T he left channel data field always precedes the right
channel data field; the current channel being consumed or pro-
duced is indicated by the state of the left/right clock (LR_I and
LR_O). A left channel field, right channel field pair is called a
frame. T he input data field consists of 4 to 20 bits for the
AD1890, and 4 to 16 bits for the AD1891. T he output data
field consists of 4 to 24 bits for both devices. T he input signals
are specified to T T L logic levels, and the outputs swing to full
CMOS logic levels. T he ports are configured by pin selections.
Contr ol Signals
T he GPDLYS, SET LSLW, BKPOL_I, BKPOL_O, T RGLR_I,
T RGLR_O, MSBDLY_I, and MSBDLY_O inputs are asyn-
chronous signals in that they need obey no particular timing
relation to MCLK or the sample clocks. Ordinarily, these pins
are hardwired or connected to an I/O register for microprocessor
control. T he only timing requirement on these pins is that the
control signals are stable and valid before the first serial input
data bit (i.e., the MSB) is presented to the AD1890/AD1891.
Ser ial I/O P or t Modes
T he AD1890/AD1891 has pin-selectable bit clock polarity for
the input and output ports. In “normal” mode (BKPOL_I or
BKPOL_O LO) the data is valid on the rising edge. In the
“inverted” mode (BKPOL_I or BKPOL_O HI) the data is
valid on the falling edge. Both modes are shown in Figures 22
and 23.
Reset
Figure 25 shows the reset timing for the AD1890/AD1891
SamplePorts. MCLK must be running when RESET is
asserted, and the bit clocks, the word clocks and the left/right
clocks may also be running. When the AD1890/AD1891 come
out of reset, they default to a FSIN to FSOUT ratio of 1:1. T he fil-
ter pipeline is not cleared. However, the mute output goes HI
for at least 128 cycles, adequate to allow the pipeline to clear. If
FSIN differs significantly from FSOUT , then the AD1890/AD1891
sample clock servo control loop also has to settle. While settling,
the mute output will be HI. After the external system resets the
AD1890/AD1891, it should wait until the mute output goes LO
before clocking in serial data.
In the pin selectable MSB delay mode, which can be set inde-
pendently for the input and output ports, the MSB is delayed by
one bit clock. T his is useful for I2S format compatibility and for
ease of interfacing to some DSP processors. Both the MSB de-
lay mode (MSBDLY_I or MSBDLY_O HI) and the MSB
non-delay mode (MSBDLY_I or MSBDLY_O LO) are shown
in Figures 22 and 23.
T he AD1890/AD1891 SamplePort serial ports operate in either
the word clock (WCLK_I, WCLK_O) triggered mode or left/
right clock (LR_I, LR_O) triggered mode. T hese modes can be
utilized independently for the input and output ports, by reset-
ting or setting the T RGLR_I and T RGLR_O control lines
respectively. In the word clock triggered mode, as shown in Fig-
ure 22, after the left/right clock is valid, the appearance of the
MSB of data is synchronous with the rising edge of the word
clock (or delayed by one bit clock if the MSB delay mode is
selected). Note that the word clock is rising edge sensitive, and
can fall anytime after it is sampled HI by the bit clock. In the
left/right clock triggered mode, as shown in Figure 23, the
T here is no requirement for using the RESET pin at power-up
or when the input or output sample rate changes. If it is not
used, the AD1890/AD1891 will settle to the sample clocks sup-
plied within ≈200 ms in fast-settling mode or within ≈800 ms in
slow-settling mode.
REV. 0
–13–
AD1890/AD1891
F
/F
= 1/2
F
/F
= 1/1
10kHz
sin sout
sin sout
AP P LICATIO N ISSUES
80
72
64
56
48
40
32
24
16
8
D ither
Due to the large output word length, no redithering of the
AD1890/AD1891 output is necessary. T his assumes that the
input is properly dithered and the user retains the same or
greater number of output bits as there are input bits. T he
AD1890/AD1891 output bit stream may thus be used directly
as the input to downstream digital audio processors, storage
media or output devices.
70kHz
UPSAMPLING
F
/F
= 2/1
sin sout
DOWNSAMPLING
If the AD1890/AD1891 is to be used to dramatically down-
sample (i.e., output sample frequency is much lower than input
sample frequency), the input should be sufficiently dithered to
account for the limiting of the input signal bandwidth (which
reduces the RMS level of the input dither). No dither is inter-
nally used or applied to the audio data in the AD1890/AD1891
SamplePorts.
70kHz
0
0
8
16
24
32
40
– kHz
48
56
64
72
80
F
sin
D ecoupling and P CB Layout
Figure 9. Allowable Input and Output Sam ple Frequencies
MCLK = 20 MHz Case
T he AD1890/AD1891 ASRCs have two power (Pins 7 and 22)
and two ground (Pins 8 and 21) connections to minimize output
switching noise and ground bounce. [Pins 14 and 27 are actu-
ally control inputs, and should be tied LO, but need not be
decoupled.] T he DIP version places these pins at the center of
the device to optimize switching performance. T he AD1890/
AD1891 should be decoupled with two high quality 0.1 µF or
0.01 µF ceramic capacitors (preferably surface mount chip
capacitors, due to their low inductance), one between each VDD
GND pair. Best practice PCB layout and interconnect guide-
lines should be followed. T his may include terminating MCLK
or the bit clocks if excessive overshoot or undershoot is evident
and avoiding parallel PCB traces to minimize digital crosstalk
between clocks and control lines. Note that DIP and PLCC
sockets reduce electrical performance due to the additional in-
ductance they impose; sockets should therefore be used only
when required.
F
/F
sin sout
= 1/2
F
/F
= 1/1
8kHz
sin sout
80
72
64
56
48
40
32
24
16
8
56kHz
UPSAMPLING
/
F
/F
= 2/1
sin sout
DOWNSAMPLING
56kHz
64
0
0
8
16
24
32
40
– kHz
48
56
72
80
F
sin
Master Clock
Using a 16 MHz MCLK, the nominal range of sample frequen-
cies that the AD1890/AD1891 accept is from 8 kHz to 56 kHz.
Other sample frequency ranges are possible by linearly scaling
the MCLK frequency. For example, a 12 MHz MCLK would
yield a sample frequency range of 6 kHz to 42 kHz, and a
20 MHz MCLK would yield a sample frequency range of
10 kHz to 70 kHz. T he approximate relative upper bound
sample frequency is the MCLK frequency divided by 286; the
approximate relative lower bound sample frequency is the
MCLK frequency divided by 2000. T he audio performance will
not degrade if the sample frequencies are kept within these
bounds. T he AD1890/AD1891 SamplePorts are production
tested with a 20 MHz MCLK. Note that due to MCLK-driven
finite register length constraints, there is a minimum input
sample frequency (LR_I). T he allowable input and output
sample frequency ranges for MCLK frequencies of 20 MHz,
16 MHz and 12 MHz are shown in Figures 9, 10 and 11.
Figure 10. Allowable Input and Output Sam ple Frequencies
MCLK = 16 MHz Case
F
/F
= 1/2
F
/F
= 1/1
6kHz
sin sout
sin sout
80
72
64
56
48
40
32
24
16
8
F
/F
= 2/1
sin sout
UP-
SAMPLING
42kHz
DOWN-
SAMPLING
42kHz
0
0
8
16
24
32
40
– kHz
48
56
64
72
80
F
sin
Figure 11. Allowable Input and Output Sam ple Frequencies
MCLK = 12 MHz Case
REV. 0
–14–
AD1890/AD1891
Var ispeed
Multiple ASRC Synchr onization and P er for m ance
D egr adation
It is also envisioned that the AD1890 will be used in varispeed
applications. T he AD1890 and AD1891 SamplePorts are very
useful for converting an input data stream with a variable
sample rate (and therefore pitch characteristic) into an output
data stream with a constant sample rate.
Multiple parallel AD1890/AD1891 ASRCs may be used in a
single system. Multiple AD1890/AD1891s can be “synchro-
nized” by simply sharing the same reset and MCLK lines, and
ensuring that all the ASRCs leave the reset state on the same
MCLK falling edge. No other provision is necessary since the
different AD1890/AD1891s will process samples identically if
they are presented with the same input and output clocks
(neglecting the effect of excessive clock skew on the PCB, as
well process variations between ASRCs which could cause dif-
ferent devices to trigger at slightly different times on excessively
slow rising or falling clock edges).
O ptions for Sam ple Rate Conver sion over a Wider Range
T here are systems which require sample rate conversion over a
range which is wider than the 1:2 or 2:1 range provided by a
single AD1890 or AD1891, such as for “scrubbing” in digital
audio editors. T here are at least two options in this situation.
T he first is to use a programmable DSP chip to perform simple
integer ratio interpolation or decimation, and then use the
AD1890/AD1891 when this intermediate output sample fre-
quency is within the 1:2 or 2:1 range of the final desired output
sample frequency. T he second is to use multiple AD1890/
AD1891 devices cascaded in series to achieve the required
sample rate range.
It is also likely that several AD1890/AD1891s could end up in a
serial cascade arrangement, either in a single systems design or
as the result of two or more systems, each using a single AD1890/
AD1891 in the signal path. T he audio signal quality will be
degraded with each pass through an ASRC, though to a very
minor degree. T he T HD+N performance will degrade by 3 dB
with every doubling of the number of passes through an ASRC.
For example, the AD1890 T HD+N specification of –106 dB (at
1 kHz) will rise to –103 dB if the signal makes two passes
through an ASRC. T he overall system T HD+N specification
will rise to –100 dB with four passes, and so on.
“ Alm ost Synchr onous” O per ation
It is possible to apply input and output sample frequencies
which are very close (within a few Hz) or in fact synchronous
(LR_I and LR_O tied together). T here is no performance pen-
alty when using the AD1890/AD1891 in “almost synchronous”
applications. Indeed, there is a very slight performance benefit
when the input and output sample clocks are synchronous since
the alias distortion components which arise from the non-infinite
stopband attenuation of the FIR filter will pile up exactly on top
of the sinusoidal frequency components of the input signal, and
will thus be masked.
Clipping
Under certain rare input conditions, it is possible for the
AD1890/AD1891 ASRC to produce a clipped output sample.
T his situation is best comprehended by employing the interpola-
tion/decimation model. If two consecutive samples happened to
have full-scale amplitudes (representing the peak of a full-scale
sine wave, for example), the interpolated sample (or samples)
between these two samples might have an amplitude greater
than full scale. As this is not possible, the AD1890/AD1891 will
compute a full-scale amplitude for the interpolated sample or
samples (see Figure 12). Clipping can also arise due to the
pre-echo and post-echo Gibbs phenomena of the FIR filter,
when presented with a full-scale step input. T he result of this
erroneous or clipped output sample may be measured as an
extremely small decrease in headroom for transient signals.
System Mute
T he mute function applies to both right and left channels on the
AD1890/AD1891. T he user can include a system specific out-
put mute signal, while retaining the automatic mute feature of
the AD1890/AD1891 by using the circuit shown in Figure 13.
EXTERNAL SYSTEM MUTE
ACTIVE HI
15
16
CORRECTLY INTERPOLATED SAMPLE
MUTE_O
MUTE_I
AD1890/AD1891
Figure 13. External Mute Circuit
FULL SCALE
AMPLITUDE
CLIPPED INTERPOLATED SAMPLE
TIME
Figure 12. Clipped Output Sam ple
REV. 0
–15–
AD1890/AD1891
Performance Graphs
–60.00
–70.00
–80.00
–90.00
–100.0
–110.0
–120.0
–130.0
–140.0
–150.0
–160.0
–60.00
–70.00
–80.00
–90.00
–100.0
–110.0
–120.0
–130.0
–140.0
–150.0
–160.0
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 14b. AD1891—Dynam ic Range from 20 Hz to
20 kHz, –60 dBFS, 48 kHz Input Sam ple Frequency,
44.1 kHz Output Sam ple Frequency, 16k-Point FFT,
BH4 Window
Figure 14a. AD1890—Dynam ic Range from 20 Hz to
20 kHz, –60 dBFS, 48 kHz Input Sam ple Frequency,
44.1 kHz Output Sam ple Frequency, 16k-Point FFT,
BH4 Window
0.0
0.0
–20.00
–20.00
–40.00
–60.00
–40.00
–60.00
–80.00
–80.00
–100.00
–100.00
–120.00
–140.00
–120.00
–140.00
100
1k
10k 20k
20
100
1k
10k 20k
20
FREQUENCY – Hz
FREQUENCY – Hz
Figure 15b. AD1891—1 kHz Tone at 0 dBFS, 48 kHz Input
Sam ple Frequency, 44.1 kHz Output Sam ple Frequency,
16k-Point FFT, BH4 Window
Figure 15a. AD1890—1 kHz Tone at 0 dBFS, 48 kHz Input
Sam ple Frequency, 44.1 kHz Output Sam ple Frequency,
16k-Point FFT, BH4 Window
0.0
0.0
–20.00
–20.00
–40.00
–60.00
–40.00
–60.00
–80.00
–80.00
–100.00
–100.00
–120.00
–140.00
–120.00
–140.00
100
1k
10k 20k
20
100
1k
10k 20k
20
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16b. AD1891—15 kHz Tone at 0 dBFS, 48 kHz Input
Sam ple Frequency, 44.1 kHz Output Sam ple Frequency,
16k-Point FFT, BH4 Window
Figure 16a. AD1890—15 kHz Tone at 0 dBFS, 48 kHz Input
Sam ple Frequency, 44.1 kHz Output Sam ple Frequency,
16k-Point FFT, BH4 Window
REV. 0
–16–
AD1890/AD1891
–80.00
–85.00
–90.00
–95.00
–100.0
–105.0
–110.0
–80.00
–85.00
–90.00
–95.00
–100.0
–105.0
–110.0
–115.0
–120.0
–115.0
–120.0
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 17a. AD1890—THD+N vs. Frequency, 48 kHz Input
Sam ple Frequency, 44.1 kHz Output Sam ple Frequency,
Full-Scale Input Signal
Figure 17b. AD1891—THD+N vs. Frequency, 48 kHz Input
Sam ple Frequency, 44.1 kHz Output Sam ple Frequency,
Full-Scale Input Signal
–90.00
–95.00
–100.0
–90.00
–91.00
20kHz
–92.00
–93.00
–94.00
20kHz
–105.0
–110.0
–115.0
–95.00
1kHz
–96.00
–97.00
–98.00
–99.00
1kHz
–120.0
–125.0
–130.0
–100.00
–100 –90.0 –80.0 –70.0 –60.0 –50.0 –40.0 –30.0 –20.0 –10.0 0.0
AMPLITUDE – dBFS
–100 –90.0 –80.0 –70.0 –60.0 –50.0 –40.0 –30.0 –20.0 –10.0 0.0
AMPLITUDE – dBFS
Figure 18a. AD1890—THD+N vs. Input Am plitude,
44.1 kHz Input Sam ple Frequency, 48 kHz Output Sam ple
Frequency, 1 kHz and 20 kHz Tones
Figure 18b. AD1891—THD+N vs. Input Am plitude,
44.1 kHz Input Sam ple Frequency, 48 kHz Output Sam ple
Frequency, 1 kHz and 20 kHz Tones
10.000
8.0000
6.0000
4.0000
2.0000
0.0
44.1k
–2.000
–4.000
30k
35k
–6.000
–8.000
–10.00
25k
40k
10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0
FREQUENCY – Hz
Figure 19. AD1890/AD1891 Digital Filter Signal Transfer Function, 10 kHz to
20 kHz, 44.1 kHz Input Sam ple Frequency, 44.1, 40, 35, 30 and 25 kHz
Output Sam ple Frequencies
REV. 0
–17–
AD1890/AD1891
0.0
–20.00
–40.00
–60.00
–80.00
–100.0
–120.0
–140.0
0.0
–20.00
–40.00
–60.00
–80.00
–100.0
–120.0
–140.0
20
2k
4k
6k
8k
10k 12k 14k 16k 18k 20k
20
2k
4k
6k
8k
10k 12k 14k 16k 18k 20k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 20b. AD1891—Twintone, 10 kHz and 11 kHz,
44.1 kHz Input Sam ple Frequency, 48 kHz Output Sam ple
Frequency, 16k-Point FFT, BH4 Window
Figure 20a. AD1890—Twintone, 10 kHz and 11 kHz,
44.1 kHz Input Sam ple Frequency, 48 kHz Output Sam ple
Frequency, 16k-Point FFT, BH4 Window
0.0
–20.00
–40.00
–60.00
–80.00
–100.0
–120.0
–140.0
20
1k
2k
3k
4k
5k
6k
7k
8k
9k
10k
FREQUENCY – Hz
Figure 21. AD1890/AD1891—5 kHz Tone at 0 dBFS with 100 ns p-p Binom ial J itter
on L/R Clocks, Fast Settling Mode, 48 kHz Input Sam ple Frequency, 44.1 kHz Output
Sam ple Frequency, 16k-Point FFT, BH4 Window
BCLK_I, BCLK_O
NORMAL MODE
INPUT
BCLK_I, BCLK_O
INVERTED MODE
LR_I, LR_O
INPUT
WCLK_I, WCLK_O
INPUT
RIGHT DATA
LEFT DATA
DATA IN/OUT
MSB MSB–1 MSB–2 MSB–3
MSB MSB-1 MSB-2 MSB-3
LSB
LSB+1 LSB
NO MSB DELAY MODE
LEFT DATA
RIGHT DATA
DATA IN/OUT
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
LSB+1 LSB
MSB MSB-1 MSB-2
MSB DELAY MODE
Figure 22. AD1890/AD1891 Serial Data Input and Output Tim ing, Word Clock Triggered Mode
REV. 0
–18–
AD1890/AD1891
BCLK_I, BCLK_O
NORMAL MODE
INPUT
BCLK_I, BCLK_O
INVERTED MODE
LR_I, LR_O
INPUT
RIGHT DATA
LEFT DATA
DATA IN/OUT
NO MSB DELAY MODE
MSB MSB-1 MSB–2 MSB–3
LSB+1 LSB
MSB MSB-1 MSB-2 MSB-3
LSB
LEFT DATA
RIGHT DATA
DATA IN/OUT
MSB DELAY MODE
MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB
MSB MSB-1 MSB-2
LSB+1 LSB
Figure 23. AD1890/AD1891 Serial Data Input and Output Tim ing, Left/Right Clock Triggered Mode
tMPWH
MCLK
t
RS
MCLK
RESET
tMCLK
t
tMPWL
RPWL
Figure 25. AD1890/AD1891 Reset Tim ing
Figure 24. AD1890/AD1891 MCLK Tim ing
tBPWH
BCLK_I, BCLK_O
NORMAL MODE
tBPWL
tBPWL
BCLK_I, BCLK_O
INVERTED MODE
tBPWH
tWSI
WCLK_I
tWSO
WCLK_O
tLRSI
tLRSO
tDS
LR_I
LR_O
DATA IN
NO MSB DELAY MODE
MSB-1
MSB
tDH
DATA OUT
NO MSB DELAY MODE
MSB
MSB-1
tDPD
tDOH
tDS
DATA IN
MSB
MSB-1
MSB DELAY MODE
tDH
DATA OUT
MSB DELAY MODE
MSB
MSB-1
tDPD
tDOH
Figure 26. AD1890/AD1891 Bit Clock, Word Clock, Left/Right Clock and Data Tim ing
REV. 0
–19–
AD1890/AD1891
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
N-28
28-Lead P lastic D IP
28
15
0.580 (14.73)
0.485 (12.32)
PIN 1
14
1
1.565 (39.70)
1.380 (35.10)
0.625 (15.87)
0.600 (15.24)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.125 (3.18)
0.250
(6.35)
MAX
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
MAX
P -28A
28-Lead P LCC
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
4
5
26
25
0.042 (1.07)
PIN 1
IDENTIFIER
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
11
12
19
18
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.456 (11.58)
0.450 (11.43)
0.495 (12.57)
0.485 (12.32)
SQ
SQ
0.110 (2.79)
0.085 (2.16)
REV. 0
–20–
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