AD1986AJCPZ-REEL [ADI]
AD1986AJCPZ-REEL;
| 型号： | AD1986AJCPZ-REEL |
| 厂家： | 
ADI |
| 描述： | AD1986AJCPZ-REEL 商用集成电路 |
| 文件： | 总56页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AC ’97 and HD Audio
SoundMAX Codec
AD1986A
FEATURES
ENHANCED FEATURES
Supports both AC ’97 and HD audio interfaces
6 DAC channels for 5.1 surround
S/PDIF output
Integrated parametric speaker equalizer
Stereo microphone with up to 30 dB gain boost
Integrated PLL for system clocking
Integrated headphone amplifiers
Variable rate audio
Variable sample rate: 7 kHz to 96 kHz
7 kHz to 48 kHz in 1 Hz increments
Double rate audio (Fs = 96 kHz)
Greater than 90 dB dynamic range
20-bit resolution on all DACs
20-bit resolution on all ADCs
Line-level mono phone input
High quality differential CD input
Selectable MIC input with preamp
AUX and line-in stereo inputs
External amplifier power down (EAPD)
Power management modes
Jack sensing and device identification
48-lead LQFP package
96 kHz for double rate audio
Jack sense with autotopology switching
Jack presence detection on up to 8 jacks
Three software-controlled microphone bias signals
Software-enabled outputs for jack sharing
Auto-down mix and channel spreading
Microphone-to-mono output for speakerphone
Stereo microphone pass-through to mixer
Built-in microphone/center/LFE/line-in sharing
Built-in SURROUND/LINE_IN sharing
Center/LFE swapping supporting all vendor speakers
Microphone left/right swapping
Reduced support component count
General-purpose digital output pin (GPO)
LINE_OUT and HP_OUT, headphone drive on both
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD1986A
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 4
Surround DAC PCM Rate (Register 0x2E)............................. 34
C/LFE DAC PCM Rate (Register 0x30) .................................. 34
ADC PCM Rate (Register 0x32) .............................................. 34
C/LFE DAC Volume (Register 0x36)....................................... 35
Surround DAC Volume (Register 0x38).................................. 35
SPDIF Control (Register 0x3A)................................................ 36
EQ Control Register (Register 0x60)....................................... 37
EQ Data Register (Register 0x62) ............................................ 38
Misc Control Bits 2 (Register 0x70)......................................... 38
Jack Sense (Register 0x72)......................................................... 39
Serial Configuration (Register 0x74)....................................... 41
Misc Control Bits 1 (Register 0x76)......................................... 43
Advanced Jack Sense (Register 0x78)...................................... 45
Misc Control Bits 3 (Register 0x7A)........................................ 45
Vendor ID Registers (Register 0x7C to 0x7E)........................ 47
Codec Class/Revision Register (Register 0x60) ..................... 47
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 9
Environmental Conditions.......................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration And Function Description ........................... 10
AC’97 Registers............................................................................... 12
HD Audio Widgets ......................................................................... 14
AC ’97 Register Details .................................................................. 21
Reset (Register 0x00).................................................................. 21
Master Volume (Register 0x02) ................................................ 21
Headphone Volume (Register 0x04)........................................ 22
Mono Volume (Register 0x06).................................................. 22
PC Beep (Register 0x0A)........................................................... 23
Phone Volume (Register 0x0C) ................................................ 23
Microphone Volume (Register 0x0E) ...................................... 24
Line_In Volume (Register 0x10)............................................... 25
CD Volume (Register 0x12) ...................................................... 25
AUX Volume (Register 0x16).................................................... 26
Front DAC Volume (Register 0x18)......................................... 26
ADC Select (Register 0x1A)...................................................... 27
ADC Volume (Register 0x1C) .................................................. 28
General-Purpose (Register 0x20)............................................. 29
Audio Int and Paging (Register 0x24) ..................................... 29
Power-Down Ctrl/Stat (Register 0x26).................................... 30
Extended Audio ID (Register 0x28)......................................... 31
Ext’d Audio Stat/Ctrl (Register 0x2A)...................................... 32
Front DAC PCM Rate (Register 0x2C) ................................... 33
PCI Subsystem Vendor ID Register
(Register 0x62, Page 01)............................................................. 48
PCI Subsystem Device ID Register (Register 0x64, Page 01)48
Function Select Register (Register 0x66, Page 01) ................. 49
Information and I/O Register (Register 0x68, Page 01)........ 50
Sense Register (Register 0x6A, Page 01).................................. 51
Jack Presence Detection................................................................. 53
Audio Jack Styles (NC/NO) ...................................................... 53
Microphone Selection/Mixing...................................................... 54
Outline Dimensions....................................................................... 55
Ordering Guide .......................................................................... 55
REVISION HISTORY
4/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 56
AD1986A
NOTES
•
•
Advanced Jack Presence Detection: Using two codec pins,
eight resistors and isolated switch jacks, the AD1986A can
detect jack insertion on eight separate jacks.
Internal Microphone/Line In/C/LFE Sharing: On
systems that share the microphone with the C/LFE jack no
external components are required. The microphone
selector can select the LINE_IN pins when the microphone
and line input devices are swapped.
Internal Line In/Microphone/Surround Sharing: On
systems that share the line in with the surround jack no
external components are required.
Dual Headphone Amplifiers: The AD1986A can drive
headphones out of the HP_OUT or LINE_OUT pins.
REDUCED SUPPORT COMPONENTS
The AD1986A includes many improvements that reduce
external support components for particular applications.
•
Multiple Microphone Sourcing: The MIC_1/2, LINE_IN
and C/LFE pins can all be selected as sources for
microphone input (boost amplifier).
•
Multiple VREF_OUT Pins: Each microphone-capable pin
group (MIC_1/2, LINE_IN and C/LFE) has separate,
software controllable VREF_OUT pins, reducing the need
for external biasing components.
•
•
•
Internal Microphone Mixing: Any combination of the
MIC_1/2, LINE_IN and C/LFE pins can be summed to
produce the microphone input. This removes the need for
external mixing components in applications that externally
mix microphone sources.
Rev. 0 | Page 3 of 56
AD1986A
FUNCTIONAL BLOCK DIAGRAM
SPDIF_OUT
SPDIF TX
AC97CK
PLL
MIC_1
AD1986A
MICROPHONE
SELECTOR/
MIXING AND
GAIN BLOCK
MIC_2
CODEC CORE
PHONE_IN
CD_L
RESET
SYNC
CD
CD_GND
CD_R
DIFF AMP
20-BIT
Σ-∆ ADC
G
G
M
M
ADC
SLOT
LOGIC
AUX_L
AUX_R
LINE_IN_L
20-BIT
Σ-∆ ADC
BITCLK
LINE
IN
SELECT
LINE_IN_R
SDATA_OUT
DAC
SLOT
LOGIC
PCBEEP_IN
SDATA_IN
MZ
MZ
LFE_OUT
CENTER_OUT
MONO_OUT
A
A
24-BIT
GA
M
M
Σ-∆ DAC
AC '97
24-BIT
Σ-∆ DAC
CONTROL
GA
REGISTERS
GA
M
GA
M
GA
M
GA
M
GA
M
M
A
GA
M
GA
M
GA
M
GA
M
M
M
M
M
A
M
JACK_SENSE_A
JACK_SENSE_B
PC BEEP
SURR_OUT_L
SURR_OUT_R
MZ
MZ
A
A
GENERATOR
24-BIT
EQ
GA
GA
M
M
Σ-∆ DAC
24-BIT
EQ
Σ-∆ DAC
A
A
LINE_OUT_L
HP
M
M
EAPD
GPO
GPIO
EAPD
24-BIT
Σ-∆ DAC
Σ
M
M
GA
GA
Σ
Z
Z
Z
G
G
G
LINE_OUT_R
HP_OUT_L
HP
HP
HP
VREF_OUT
(MIC1/2)
24-BIT
Σ-∆ DAC
Σ
M
VREF_OUT
(C/LFE)
A
A
M
M
VOLTAGE
REFERENCE
G = GAIN
A = ATTENUATION
M = MUTE
VREF_OUT
(LINE_IN)
M
HP_OUT_R
Z = HI-Z
VREF_FILT
Figure 1.
Rev. 0 | Page 4 of 56
AD1986A
SPECIFICATIONS
Test conditions, unless otherwise noted.
Table 1.
Parameter
Typ
Unit
°C
Temperature
25
Digital Supply (DVDD)
3.3 ꢀ0ꢁ
V
Analog Supply (AVDD)
5.0 ꢀ0ꢁ
V
Sample Rate (FS)
Input Signal
48
ꢀ.0
kHz
kHz
Analog Output Pass Band
20 Hz–20 kHz
VIH
VIL
VIH
VIL
2.0
0.8
2.4
0.6
V
V
V
V
DAC Test Conditions
Calibrated
ADC Test Conditions
Calibrated
Output −3 dB Relative to Full Scale
10 kΩ Output Load: Line (Surround), Mono
32 Ω Output Load: Headphone
2 kΩ Output Load: Center, LFE
0 dB PGA Gain
Input −3.0 dB Relative to Full Scale
Table 2. Analog Input
Input Voltage
Min
Typ
ꢀ
2.83
0.032
0.089
0.ꢀ
0.283
0.3ꢀ6
0.894
20
Max
Unit
Vrmsꢀ
V p-p
Vrms
V p-p
Vrms
V p-p
Vrms
V p-p
kΩ
MIC_ꢀ/2, LINE_IN, CD, AUX, PHONE_IN (No Preamp)
C/LFE and SURROUND (When Used as Inputs)
MIC_ꢀ/2, LINE_IN, C/LFE With 30 dB Preamp
MIC_ꢀ/2, LINE_IN, C/LFE With 20 dB Preamp
MIC_ꢀ/2, LINE_IN, C/LFE With ꢀ0 dB Preamp
Input Impedance2
Input Capacitance2
5
7.5
pF
ꢀ RMS values assume sine wave input.
2 Guaranteed by design, not production tested.
Table 3. Master Volume
Parameter
Min
Typ
Max
Unit
dB
dB
Step Size (LINE_OUT, HP Out, Mono Out, SURROUND, CENTER, LFE)
Output Attenuation Range (0 dB to –46.5 dB)
Mute Attenuation of 0 dB Fundamental2
−ꢀ.5
−46.5
−80
dB
Table 4. Programmable Gain Amplifier—ADC
Parameter
Step Size
Min
Typ
ꢀ.5
Max
Unit
dB
PGA Gain Range Span (0 dB to 22.5 dB)
22.5
dB
Rev. 0 | Page 5 of 56
AD1986A
Table 5. Analog Mixer—Input Gain/Amplifiers/Attenuators
Parameter
Min
Typ
Max
Unit
Signal-to-Noise Ratio (SNR)
CD to LINE_OUT
LINE, AUX, PHONE to LINE_OUTꢀ
MIC_ꢀ or MIC_2 to LINE_OUTꢀ
Step Size: All Mixer Inputs (Except PC Beep)
Step Size: PC Beep
Input Gain/Attenuation Range: All Mixer Inputs (+ꢀ2 dB to −34.5 dB)
90
88
80
−ꢀ.5
−3.0
−46.5
dB
dB
dB
dB
dB
dB
ꢀ Guaranteed by design, not production tested.
Table 6. Digital Decimation and Interpolation Filters1
Parameter
Min
Typ
Max
Unit
Pass Band
0
0.4 × FS
0.09
0.6 × FS
∞
Hz
dB
Hz
Hz
dB
S
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Rejection
Group Delay
0.4 × FS
0.6 × FS
−74
ꢀ6/FS
0
Group Delay Variation Over Pass Band
µs
Table 7. Analog-to-Digital Converters
Parameter
Min
Typ
Max
Unit
Resolution
Total Harmonic Distortion (THD)
20
Bits
dB
dB
dB
dB
ꢁ
−95
−85
−80
−ꢀ00
ꢀ0
Dynamic Range (−60 dB Input, THD + N Referenced to Full Scale, A-Weighted)
Crosstalk: Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Crosstalk: LINE_IN to Other Inputs
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
−80
0.5
5
dB
mV
Rev. 0 | Page 6 of 56
AD1986A
Table 8. Digital-to-Analog Converters
Parameter
Min
Typ
20/24
−92
−75
9ꢀ
Max
Unit
Bits
dB
dB
dB
ꢁ
Resolution
Total Harmonic Distortion (LINE_OUT Drive)
Total Harmonic Distortion (HP_OUT)
Dynamic Range (−60 dB Input, THD + N Referenced to Full-Scale, A-Weighted)
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalkꢀ (Input L, Zero R, Read R_OUT; Input R, Zero L, Read L_OUT)
ꢀ0
0.7
−80
dB
dB
ꢀ Guaranteed by design, not production tested.
Table 9. Analog Output
Parameter
Min
Typ
Max
Unit
VRMS
V p-p
Ω
kΩ
pF
FULL-SCALE OUTPUT VOLTAGE: SURROUND, CENTER/LFE, MONO_OUT
ꢀ
2.83
300
Output Impedanceꢀ
External Load Impedanceꢀ
ꢀ0
Output Capacitanceꢀ
ꢀ5
External Load Capacitance
ꢀ,000
ꢀ
pF
FULL-SCALE OUTPUT VOLTAGE: HP_OUT, LINE_OUT
ꢀ
2.83
VRMS
V p-p
Ω
Output Impedanceꢀ
External Load Impedanceꢀ
Output Capacitanceꢀ
32
Ω
pF
pF
ꢀ5
External Load Capacitanceꢀ
ꢀ,000
2.450
VREF_FILT
2.050
2.250
2.250
3.700
0.0
V
VREF_OUT(MIC, C/LFE, LIN) (xVREF [2:0] = 00ꢀ)
(xVREF [2:0] = ꢀ00, AVDD = 5.0 V)
(xVREF [2:0] = 0ꢀ0)
V
V
V
Current Drive
5
mA
mV
Mute Click (Muted Output, Unmuted Midscale DAC Output)
5
ꢀ Guaranteed by design, not production tested.
Table 10. Static Digital Specifications—AC ’97
Parameter
Min
Typ
Max
Unit
V
V
V
V
µA
µA
pF
High Level Input Voltage (VIH), Digital Inputs
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH), IOH = 2 mA
Low Level Output Voltage (VOL), IOL = 2 mA
Input Leakage Current
0.65 × DVDD
0.35 × DVDD
0.90 × DVDD
0.ꢀ0 × DVDD
−ꢀ0
−ꢀ0
ꢀ0
ꢀ0
7.5
Output Leakage Current
Input/Output Pin Capacitance
Rev. 0 | Page 7 of 56
AD1986A
Table 11. Power Supply (Quiescent State)
Parameter
Min
4.5
2.97
Typ
Max
5.5
3.63
Unit
V
V
mW
mA
mA
dB
Power Supply Range—Analog (AVDD) ꢀ0ꢁ
Power Supply Range—Digital (DVDD) ꢀ0ꢁ
Power Dissipation—Analog (AVDD)/Digital (DVDD)
Analog Supply Current—Analog (AVDD)
Digital Supply Current—Digital (DVDD)
Power Supply Rejection (ꢀ00 mV p–p Signal @ ꢀ kHz)
365/ꢀ7ꢀ.6
62.0
53.2
40
Table 12. Power-Down States—AC ’97 (Quiescent State)
Parameter
Set Bits
AVDD Typ
DVDD Typ
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ADC
FRONT DAC
PR0
PRꢀ
PRI
PRJ
53.0
53.7
62.0
53.5
62.0
27.0
36.6
27.6
ꢀ2.6
2.4
45.7
47.7
53.2
47.ꢀ
52.8
ꢀ4.5
53.2
45.7
33.0
ꢀ4.5
0.05
53.2
53.2
CENTER DAC
SURROUND DAC
LFE DAC
ADC + ALL DACs
Mixer
PRK
PRꢀ, PR0, PRI, PRJ, PRK
PR2
PR2, PR0
PR2, PRꢀ, PRI, PRJ, PRK
PR2, PRꢀ, PR0, PRI, PRJ, PRK
PR5, PR4, PR3, PR2, PRꢀ(IJK), PR0
PR6
ADC + Mixer
ALL DACs + Mixer
ADC + ALL DACs + Mixer
Standby
Headphone Standby
LINE_OUT HP Standby
0.0
55.0
62.0
LOHPEN = 0
Table 13. Clock Specifications
Parameter
Min
Typ
Max
Unit
Input Clock Frequency (Reference Clock Mode)
ꢀ4.3ꢀ8ꢀ8
48.000
MHz
MHz
Recommended Clock Duty Cycle
40
50
60
ꢁ
Rev. 0 | Page 8 of 56
AD1986A
ABSOLUTE MAXIMUM RATINGS
Table 14.
ENVIRONMENTAL CONDITIONS
Power Supply
Min
−0.3
−0.3
Max
+3.6
+6.0
ꢀ0.0
AVDD + 0.3
DVDD + 0.3
Unit
V
V
mA
V
V
Ambient Temperature Rating
Digital (DVDD)
Analog (AVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins) −0.3
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Commercial
Industrial
Storage Temperature
TAMB = TCASE − (PD × θCA
)
TCASE = case temperature in °C
PD = power dissipation in W
θCA = thermal resistance (case-to-ambient)
θJA = thermal resistance (junction-to-ambient)
θJC = thermal resistance (junction-to-case)
−0.3
°C
0
–40
−65
+70
+85
+ꢀ50
Table 15. Thermal Resistance
°C
Package
θJA
θJC
θCA
LQFP
48°C/W
47°C/W
ꢀ7°C/W
ꢀ5°C/W
3ꢀ°C/W
32°C/W
Stresses greater than those listed under Absolute Maximum
Ratings can cause permanent damage to the device. This is a
stress rating only, functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect
device reliability.
LFCSP
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 56
AD1986A
PIN CONFIGURATION AND FUNCTION DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37
SURR_OUT_R
SURR_OUT_L
1
2
36
35
34
33
32
31
30
29
28
27
26
25
DV
DD
PIN 1
AC97CK
GPO
IDENTIFIER
AV
DD
3
VREF_OUT (C/LFE)
LFE_OUT
4
DV
SS
5
SDATA_OUT
BIT_CLK
AD1986A
TOP VIEW
6
CENTER_OUT
7
AV
SS
DV
SS
(Not to Scale)
8
VREF_OUT (LINE_IN)
VREF_OUT (MIC_1/2)
VREF_FILT
SDATA_IN
9
DV
DD
10
11
12
SYNC
RESET
AV
SS
AV
DD
PCBEEP
13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. Pin Configuration
Table 16. Pin Function Descriptions
Mnemonic
Pin Number
Input/Ouput
Description
AC ’97CK
2
I
External Clock In (ꢀ4.3ꢀ8ꢀ8 MHz) for AC ’97 Operation. Clock or DVSS
must be stable before reset deasserts.
Tied to digital ground for HD audio operation.
SDATA_OUT
BIT_CLK
5
6
I
Link Serial Data Output. Input Stream.
Link Bit Clock, ꢀ2.288 MHz Serial Data Clock Output for AC ‘97, 24
MHz Input for HD Audio.
I/O
SDATA_IN
SYNC
RESET
8
ꢀ0
ꢀꢀ
I/O
I
I
Link Serial Data Input. Output stream.
Link Frame Sync.
Link Reset, Master Hardware Reset.
Table 17. Digital Input/Output
Pin
Number
Input/
Output Description
Mnemonic
S/PDIF_OUT 48
O
O
O
S/PDIF Output.
EAPD
GPO
47
3
External Amplifier Power-Down Output. In HD audio mode this is part of LINE_OUT widget.
General-Purpose Output Pin. A digital signal that can be used to control external circuitry.
Table 18. Jack Sense
Mnemonic
Pin Number
Input/Ouput Description
JACK_SENSE_A
JACK_SENSE_B
ꢀ6
ꢀ7
I
I
JackSense 0–3 Input.
Jack Sense 4–7 Input.
Rev. 0 | Page ꢀ0 of 56
AD1986A
Table 19. Analog Input/Output
Pin
Number
Input/
Ouput Description
Mnemonic
PCBEEP
ꢀ2
I
Analog PC Beep Input. Routed to all output capable pins when RESET is asserted.
PHONE_IN
AUX_L
ꢀ3
ꢀ4
I
I
Mono Line Level Input.
Auxiliary Left Channel Input.
AUX_R
ꢀ5
I
Auxiliary Right Channel Input.
CD_L
ꢀ8
I
CD-Audio-Left Channel.
CD_GND
CD_R
ꢀ9
20
I
I
CD-Audio-Analog-Ground-Reference (for Differential CD Input).
CD-Audio-Right Channel.
MIC_ꢀ
MIC_2
2ꢀ
22
23
24
3ꢀ
32
I
I
I
I
Microphone ꢀ or Line-In-Left Input (See LISEL Bits in Register 0x76).
Microphone 2 or Line-In-Right Input (See LISEL Bits in Register 0x76).
Line-In-Left Channel or Microphone ꢀ Input (See OMS Bits in Register 0x74).
Line-In-Right Channel or Microphone 2 Input (See OMS Bits in Register 0x74).
Center-Channel Output or Microphone ꢀ Input (See OMS Bits in Register 0x74).
Low-Frequency-Enhanced Output or Microphone 2 Input (See OMS Bits in Register 0x74).
Headphone-Out-Left Channel (See HPSEL Bits in Register 0x76).
Headphone-Out-Right Channel (See HPSEL Bits in Register 0x76).
Line-Out (Front)—Left Channel (See LOSEL Bit in Register 0x76) (HP Drive-Capable).
Line-Out (Front)—Right Channel (See LOSEL Bit in Register 0x76) (HP Drive-Capable).
Mono Output to Telephony Subsystem Speakerphone.
Surround-Left Channel Output or Line-In-Left Input (See LISEL and SOSEL Bits in Register 0x76).
Surround-Right Channel Output or Line-In-Right Input (See LISEL and SOSEL Bits in
Register 0x76).
LINE_IN_L
LINE_IN_R
CENTER_OUT
LFE_OUT
HEADPHONE_L 39
HEADPHONE_R 4ꢀ
LINE_OUT_L
LINE_OUT_R
MONO_OUT
SURR_OUT_L
SURR_OUT_R
I/O
I/O
O
O
O
O
O
I/O
I/O
43
45
37
35
36
Table 20. Filter/Reference
Pin
Number
Input/
Ouput Description
Mnemonic
VREF_FILT
VREF_OUT (MIC)
VREF_OUT
(LINE_IN)
27
28
29
O
O
O
Voltage Reference Filter.
Programmable Voltage Reference Output (Intended for MIC Bias on the MIC_ꢀ/2 Channels).
Programmable Voltage Reference Output (Intended for MIC Bias on the LINE_IN Channels).
VREF_OUT (C/LFE)
33
O
Programmable Voltage Reference Output (Intended for MIC Bias on the C/LFE Channels).
Table 21. Power and Ground
Input/
Mnemonic Pin Number Ouput
Description
DVDD
DVSS
AVDD
ꢀ, 9
4, 7
N/A
N/A
Digital Supply Voltage (3.3 V).
Digital Supply Return (Ground).
Analog Supply Voltage (5.0 V). AVDD supplies should be well filtered because supply noise will
degrade performance.
25, 34, 38, 42, N/A
46
AVSS
26, 30, 40, 44 N/A
Analog Supply Return (Ground).
Rev. 0 | Page ꢀꢀ of 56
AD1986A
AC’97 REGISTERS
Table 22. Register Map
Reg Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00 Reset
x
SE4
SE3
SE2
SEꢀ
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
IDꢀ
ID0
0x0290
0x02 Master Volume
LM
x
x
x
x
x
x
LV4
LV4
x
LV3
LV3
x
LV2
LV2
x
LVꢀ
LVꢀ
x
LV0
LV0
x
RM
RM
x
x
x
x
x
x
x
RV4
RV4
V4
RV3
RV3
V2
RV2
RV2
V2
RVꢀ
RVꢀ
Vꢀ
RV0
RV0
V0
0x8080
0x8080
0x8000
0x04 Headphones Volume LM
0x06 Mono Volume
M
0x0A PC Beep
M
M
A/DS
x
x
x
F7
x
F6
x
F5
x
F4
x
F3
x
F2
x
Fꢀ
x
F0
x
V3
V4
V2
V3
Vꢀ
V2
V0
Vꢀ
x
0x8000
0x8008
0x0C Phone Volume
V0
0x0E Microphone Volume LM
x
x
x
x
LV4
LV4
LV3
LV3
LV2
LV2
LVꢀ
LVꢀ
LV0
LV0
RM
RM
M20
x
x
x
RV4
RV4
RV3
RV3
RV2
RV2
RVꢀ
RVꢀ
RV0
RV0
0x8888
0x8888
0xꢀ0 Line In Volume
LM
0xꢀ2 CD Volume
LM
LM
LM
x
x
x
x
x
x
LV4
LV4
LV4
LV3
LV3
LV3
LV2
LV2
LV2
LVꢀ
LVꢀ
LVꢀ
LV0
LV0
LV0
RM
RM
RM
x
x
x
x
x
x
RV4
RV4
RV4
RV3
RV3
RV3
RV2
RV2
RV2
RVꢀ
RVꢀ
RVꢀ
RV0
RV0
RV0
0x8888
0x8888
0x8888
0xꢀ6 AUX Volume
0xꢀ8 Front DAC Volume
0xꢀA ADC Select
x
x
x
x
x
x
x
x
x
x
x
LS2
LV2
LSꢀ
LVꢀ
LS0
LV0
MS
x
x
x
x
x
x
x
x
x
x
x
RS2
RV2
x
RSꢀ
RVꢀ
x
RS0
RV0
x
0x0000
0x8080
0x0000
0xꢀC ADC Volume
0x20 General Purpose
LM
x
LV3
RM
LPBK
RV3
x
DRSSꢀ DRSS0 MIX
0x24 Audio Int. and Paging I4
I3
I2
Iꢀ
I0
x
x
x
x
x
x
x
x
x
x
x
PG3
REF
PG2
ANL
PGꢀ
DAC
PG0
0xxx00
0x26 Power-Down Ctrl/Stat EAPD
PR6
PR5
PR4
PR3
PR2
PRꢀ
PR0
ADC 0x000x
0x28 Ext’d Audio ID
IDꢀꢀ
x
ID0
x
x
x
REVꢀ
PRI
REV0
SPCV
AMAP LDAC SDAC CDAC DSAꢀ DSA0
x
x
SPDF DRA
SPDIF DRA
VRA
VRA
0x0BC7
0x0xx0
0x2A Ext’d Audio Stat/Ctrl
PRK
PRJ
x
LDAC SDAC CDAC SPSAꢀ SPSA0
0x2C Front DAC PCM Rate Rꢀ5
0x2E Surr. DAC PCM Rate Rꢀ5
0x30 C/LFE DAC PCM Rate Rꢀ5
Rꢀ4
Rꢀ4
Rꢀ4
Rꢀ4
x
Rꢀ3
Rꢀ3
Rꢀ3
Rꢀ3
x
Rꢀ2
Rꢀ2
Rꢀ2
Rꢀ2
LFE4
LV4
x
Rꢀꢀ
Rꢀꢀ
Rꢀꢀ
Rꢀꢀ
LFE3
LV3
L
Rꢀ0
Rꢀ0
Rꢀ0
Rꢀ0
LFE2
LV2
CC6
x
R09
R09
R09
R09
LFEꢀ
LVꢀ
CC5
x
R08
R08
R08
R08
LFE0
LV0
CC4
x
R07
R07
R07
R07
CNTM
RM
R06 R05
R06 R05
R06 R05
R06 R05
R04
R04
R04
R04
CNT4
RV4
CC0
R03
R03
R03
R03
R02
R02
R02
R02
R0ꢀ
R0ꢀ
R0ꢀ
R0ꢀ
R00
R00
R00
R00
0xBB80
0xBB80
0xBB80
0xBB80
0x32 ADC PCM Rate
Rꢀ5
0x36 C/LFE DAC Volume
LFEM
x
x
x
x
CNT3 CNT2 CNTꢀ CNT0 0x8888
0x38 Surround DAC Volume LM
x
x
RV3
PRE
RV2
RVꢀ
RV0
0x8888
0x2000
0x3A SPDIF Control
V
VCFG
x
SPSR
x
CC3
CC2 CCꢀ
COPY /AUDIO PRO
0x60 EQ Control
0x62 EQ Data
EQM
x
x
SYM CHS BCA5 BCA4
BCA3 BCA2 BCAꢀ BCA0 0x8080
CFD3 CFD2 CFDꢀ CFD0 0xxxxx
CFDꢀ5 CFDꢀ4 CFDꢀ3 CFDꢀ2 CFDꢀꢀ CFDꢀ0 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4
MVREF2 MVREFꢀ MVREF0 x MMDIS x
0x70 Misc. Control Bits 2
x
x
x
x
JSMAP CVREF2 CVREFꢀ CVREF0 x
x
0x0000
0x72 Jack Sense
JSꢀ SPRD JSꢀ DMX JS0 DMX JS MT2 JS MTꢀ JS MT0 JSꢀ EQB JS0 EQB x
x
JSꢀ MD JS0 MD JSꢀ ST JS0 ST JSꢀ INT JS0 INT 0x0000
0x74 Serial Configuration SLOTꢀ6 REGM2 REGMꢀ REGM0 REGM3 OMS2 OMSꢀ OMS0 SPOVR LBKSꢀ LBKS0 INTS
0x76 Misc. Control Bits ꢀ DACZ DMIXꢀ DMIX0 SPRD 2CMIC SOSEL SRU
AC97NC2 MSPLT SODIS3 CLDIS
0x78 Advanced Jack Sense JS7ST JS7INT JS6ST JS6INT JS5ST JS5INT JS4ST JS4INT JS4-7H x
JSINVB HPSELꢀ HPSEL0 LOSEL JSINVA LVREF2 LVREFꢀ LVREF0
CSWP SPAL SPDZ SPLNK 0xꢀ00ꢀ
x
LISELꢀ LISEL0 MBGꢀ MBG0 0x60ꢀ0
JS3MD JS2MD JS3ST JS2ST JS3INT JS2INT 0xxxxx
0x7A Misc. Control Bits 3
x
x
x
LOHPEN GPO
MMIX
x
x
0x0000
0x7C Vendor IDꢀ
0x7E Vendor ID2
F7
T7
F6
T6
F5
T5
F4
F3
F2
Fꢀ
F0
T0
S7
S6
S5
S4 S3
S2
Sꢀ
S0
0x4ꢀ44
T4
T3
T2
Tꢀ
REV7 REV6 REV5 REV4
REV3 REV2 REVꢀ REV0 0x5378
0x60ꢀ Codec Class/Rev
0x62ꢀ PCI SVID
x
x
x
CL4
CL3
CL2
CLꢀ
CL0
RV7
PVI7 PVI6 PVI5
PI7 PI6 PI5
RV6 RV5
RV4
RV3
RV2
RVꢀ
RV0
PVI0 0xFFFF
PI0 0xFFFF
0x0002
PVIꢀ5
PVIꢀ4
PVIꢀ3
PVIꢀ2 PVIꢀꢀ PVIꢀ0 PVI9
PVI8
PVI4
PVI3
PVI2
PVIꢀ
0x64ꢀ PCI SID
PIꢀ5
PIꢀ4
PIꢀ3
PIꢀ2 PIꢀꢀ PIꢀ0 PI9
PI8
PI4
PI3
PI2
PIꢀ
Rev. 0 | Page ꢀ2 of 56
AD1986A
Reg Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x66ꢀ Function Select
x
x
x
x
x
x
x
x
x
x
x
FC3
FC2
FCꢀ
FC0
T/R
0x0000
0x68ꢀ Function Information G4
0x6Aꢀ Sense Register ST2
G3
G2
Gꢀ
S4
G0
S3
INV
S2
DL4
Sꢀ
DL3
S0
DL2
ORꢀ
DLꢀ DL0
OR0 SR5
IV
x
x
x
FIP
0xXxxx
0xXxxx
STꢀ
ST0
SR4
SR3
SR2
SRꢀ
SR0
ꢀ Codec is always master, ID bits are read-only 0 (zeros).
2 Bits for the ADꢀ98x are backward-compatible only, AC97NC and MSPLT are read-only ꢀ (ones).
3 SODIS/SOSEL were LODIS/LOSEL in the ADꢀ985. Most ADꢀ985 configurations swap LINE_OUT and SURROUND pins; these bits really operate as SO not LO.
Rev. 0 | Page ꢀ3 of 56
AD1986A
HD AUDIO WIDGETS
Table 23. Root Node
NID
Name
TID
Type
Description
0x00
Root
N/A
Root
Device identification.
Table 24. Function Group Node
NID
Name
TID
Type
Description
Designates this device as an audio codec.
0x0ꢀ
Function
N/A
Function
Table 25. ADI Specific Verb Support
Payload
Response
Bit (32 Bits)
Verb
G/S VID
Description
Description
SDI Select
Get 0xF04
N/A (0)
N/A (0)
The ADꢀ986A has only a single SDI line, thus set
SDI verbs are ignored and get SDI verbs always
return a 0.
Set 0x704x N/A (0)
8
N/A (0)
Processing
Coefficient
Get C--0x
N/A (0)
ADI-Specific
Function
Setting
Get/set the vendor specific function at the below
coefficient index address. Address is an 8-bit value
and does not auto-increment.
Set 4--x
ADI-specific function control ꢀ6 N/A (0)
Coefficient
Index
Get D--0x
N/A (0)
ADI Function
Index
Get/set the index of the vendor-specific function.
The index does not auto-increment when writing
the function (processing coefficient) command.
Set 5--0x
Get 0xF03
ADI function index
N/A (0)
8
8
N/A (0)
N/A (0)
Processing
Index
No processing states are supported by this node.
Set operations do nothing, Get operations always
return a 0.
Set 0x703
N/A (0)
N/A (0)
Table 26. S/PDIF Audio Output
NID
Name
TID
0x0
Type
Audio Output
Description
0x02
S/PDIF Audio Output
Designates the codec S/PDIF digital stream interface. Selects
between the HD audio I/F and the record ADC as sources.
Table 27. ADI Specific Verb Support
Payload
Response
Bit (32 Bits)
Verb
G/S VID
Description
Description
SDI Select
Get 0xF04 N/A (0)
Set 0x704 N/A (0)
N/A (0)
N/A (0)
The ADꢀ986 has only a single SDI line, thus set SDI verbs are
ignored and get SDI verbs always return a 0.
8
Table 28. Front DAC Audio Output
NID
Name
TID
Type
Audio Output
Description
0x03
Front DAC Audio Output
0x0
Designates the front channel DACs.
Rev. 0 | Page ꢀ4 of 56
AD1986A
Table 29. ADI Specific Verb Support
Payload
Response
BIt (32 Bits)
Verb
G/S VID
Description
Description
SDI Select
Get 0xF04 N/A (0)
N/A (0)
The ADꢀ986A has only a single SDI line, thus set SDI verbs are
ignored and get SDI verbs always return a 0.
Set 0x704 N/A (0)
8
N/A (0)
Processing
Coefficient
Get C--0x
N/A (0)
Coefficient
Get/set the processing coefficient at the current coefficient index.
Index can be set by the “set coefficient index” verb.
The coefficient indexes and data are identical to the AC’ 97 Registers
0x60 and 0x62 definitions (see the EQ Control Register (Register
0X60) and EQ Data Register (Register 0X62) sections).
Note that the ADꢀ986A does not automatically increment the
coefficient index. The index must be written for each coefficient that
is to be loaded or read.
Set 4--x
Coefficient
ꢀ6 N/A (0)
Coefficient
Coefficient
Index
Get D--0x N/A (0)
Get/set the processing coefficient index for the get/set Processing
Coefficient verb. The coefficient indexes and data are identical to the
AC’ 97 register 0x60 and 0x62 definitions. (see the EQ Control
Register (Register 0X60) and EQ Data Register (Register 0X62)
sections). Note that the ADꢀ986A does not automatically increment
the coefficient index. The index must be written for each coefficient
that is to be loaded or read.
Index
Set 5--0x
Coefficient Index
8
N/A (0)
Processing
State
Get 0xF03 N/A (0)
Processing
State
Processing states supported by the ADꢀ986 Digital EQ:
Processing
(EQM Bit [Inversed])
Value
0x00
0x0ꢀ
0x02
0x80
0x8ꢀ
0x82
Symmetry (SYM Bit)
Off
On
On
On
Off
Off
Off
Benign
Benign
Off
Benign
Benign
Set 0x703 Processing State
8
N/A (0)
Note that the ADꢀ986A considers states on and benign as both
benign. If the on state is set, the ADꢀ986 will set and return the
benign state. States 0x00 or 0x80 must be set when loading
coefficients. Setting state 0x80 will load coefficients with SYM off.
Default state 0x00 is SYM on. When symmetry is on, only ½ of the
coefficients (one channel) need to be loaded.
Table 30. Surround DAC Audio Output
NID
Name
TID
0x0
Type
Description
0x04
Surround DAC Audio Output
Audio Output
Designates the surround channel DACs.
Table 31. ADI Specific Verb Support
Payload
Response
Description Bit (32 Bits)
Verb
G/S VID
Description
SDI
Select
Get 0xF04
N/A (0)
N/A (0)
The ADꢀ986 has a only single SDI line, thus set SDI verbs are ignored
and get SDI verbs always return a 0.
Set 0x704x N/A (0)
8
N/A (0)
Rev. 0 | Page ꢀ5 of 56
AD1986A
Table 32. Center/LFE DAC Audio Output
NID
Name
TID
Type
Description
0x05
Center/LFE DAC Audio Output
0x0
Audio Output
Designates the surround channel DACs.
Table 33. Record ADC Audio Input
NID
Name
TID
Type
Description
0x06
Record ADC Audio Input
0xꢀ
Audio Input
Designates the record channel ADCs.
Table 34. Analog Mixer
NID
Name
TID
Type
Description
0x07
Analog Mixer
0x2
Audio Mixer
Mixes analog input signals into line out audio.
Table 35. Mono Mixer
NID
Name
TID
Type
Description
0x08
Mono Mixer
0x2
Audio Mixer
Mixes the left/right channels from the analog mixer into a
mono signal.
Table 36. Downmix
NID
Name
TID Type
Description
0x09
Surround to Stereo Down Mix
0x2 Audio Mixer
Mixes 5.ꢀ stereo to 4.0 or 2.0 on front channels.
Table 37. ADI Specific Verb Support
Payload
Response
Bits (32 Bits)
Verb
G/S VID
Description
Description
Amplifier
Gain/Mute
Get B--0x Amp/Index
ꢀ6
Amp
settings
This widget contains mute bits for the output and only one input.
Surround DAC (input amp Index 0), has a mute bit. The CLFE DAC
input (input amp Index ꢀ) does not have a mute control.
Writing the CLFE DAC input mute will have no effect and will
always return a 0 when read.
Set 3--0x Amp Set Payload ꢀ6
Table 38. Headphone Selector
N/A (0)
NID
Name
TID Type
Description
0x0A
Headphone Selector
0x3 Audio Selector
Chooses the HP source.
Table 39. Line Out Selector
NID
Name
TID Type
Description
0x0B
Line Out Selector
0x3 Audio Selector
Chooses the line out source.
Table 40. Surround Selector
NID
Name
TID
0x3
Type
Description
0x0C
Surround Selector
Audio Selector
Chooses the surround source.
Table 41. Center/LFE Selector
NID
Name
TID Type
Description
0x0D
Center/LFE Selector
0x3 Audio Selector
Chooses the center/LFE source.
Table 42. Mono Out Selector
NID
Name
TID Type
Description
0x0E
Mono Out Selector
0x3 Audio Selector
Chooses the mono out source.
Rev. 0 | Page ꢀ6 of 56
AD1986A
Table 43. Microphone Selector
NID
Name
TID Type
Description
0x0F
Microphone Selector
0x3 Audio Selector
Chooses the microphone inputs between the MIC_ꢀ/2 and
C/LFE pins. Contains the microphone gain boost amplifier.
Table 44. Line In Selector
NID
Name
TID Type
Description
0xꢀ0
Line In Selector
0x3 Audio Selector
Chooses the line in inputs between the line in, surround and
MIC_ꢀ/2 pins.
Table 45. MIC_1/2 Swap
NID
Name
TID Type
Description
0xꢀꢀ
MIC_ꢀ/2 Swap
0x3 Audio Selector
Swaps the left/right association of MIC_ꢀ/2 on the input pins
only. Allows up mix, spreading one microphone to both left
and right output channels.
Table 46. ADI Specific Verb Support
Payload
Response
BIt (32 bits)
Verb
G/S VID
Get C--0x
Set 4--0x
Description
Description
Processing
Coefficient
Coefficient
Index
N/A (0)
N/A (0)
N/A (0)
ꢀ6 N/A (0)
N/A (0)
Not supported. Writes have no effect, reads always return a 0.
Get D--0x N/A (0)
Set 5--0x N/A (0)
Not supported. Writes have no effect, reads always return a 0.
8
N/A (0)
Processing
State
Get 0xF03 N/A (0)
Processing
State
Controls the up-mix function of the MIC_ꢀ/2 swap widget.
Up-Mix will spread the selected left channel (see the left/right swap
feature of the enable EAPD/BTL verb description) to both the left
and right channel outputs of this stereo widget.
Value
0x00
0x0ꢀ
0x02
Processing State
Off
Benign
Up-Mix Spreading
Off
On
On
Benign
Set 0x703 Processing State
8
N/A (0)
Note that the ADꢀ986 considers both on and benign states as
benign. If the on state is set, the ADꢀ986 will set and return the
benign state.
Table 47. Record Selector
NID
Name
TID Type
Description
0xꢀ2
Record Selector
0x3 Audio Selector
Chooses the analog source to the record ADCs.
Table 48. Microphone MixAmp
NID
Name
TID Type
Description
0xꢀ3
Microphone MixAmp
0x3 Audio Selector
The microphone amplifier input to the analog mixer.
Table 49. Phone MixAmp
NID
Name
TID Type
Description
0xꢀ4
Phone MixAmp
0x3 Audio Selector
The phone amplifier input to the analog mixer.
Table 50. CD MixAmp
NID
Name
TID Type
Description
0xꢀ5
CD MixAmp
0x3 Audio Selector
The CD amplifier input to the analog mixer.
Rev. 0 | Page ꢀ7 of 56
AD1986A
Table 51. Aux MixAmp
NID
Name
TID
Type
Description
0xꢀ6h Aux MixAmp
0x3h Audio Selector
The auxiliary input amplifier to the analog mixer.
Table 52. Line In MixAmp
NID
Name
TID Type
Description
0xꢀ7
Line In MixAmp
0x3 Audio Selector
The line in amplifier input to the analog mixer.
Table 53. PC Beep Selector
NID
Name
TID
Type
Description
0xꢀ8
PC Beep Selector
0x3
Audio Selector
The digital/analog PC beep selector and amplifier input to
the analog mixer.
Table 54. Digital PC Beep
NID
Name
TID Type
Description
0xꢀ9
Digital PC Beep
0x7 Digital Beep
Digital PC beep generator.
Table 55. HP Out
NID
Name
TID
Type
Description
0xꢀA
HP Out
0x4
Pin Complex
HP_OUT pin drivers. Contains the output amplifier for HP
gain control. Supports headphone drive function. See the pin
widget control verb descriptions.
Table 56. Line Out
NID
Name
TID
Type
Description
0xꢀB
Line Out
0x4
Pin Complex
LINE (FRONT)_OUT pin drivers. Contains the output amplifier
for line (front) gain control. Supports headphone drive
function. Supports the EAPD (external amp power-down)
function pin.
Table 57. Surround Out
NID
Name
TID
Type
Description
0xꢀC
Surround Out
0x4
Pin Complex
SURROUND pin drivers. Contains the output amplifier for
surround gain control. Supports multitasking as either the
surround outputs or can be configured as the LINE_IN inputs.
Table 58. C/LFE Out
NID
Name
TID
Type
Description
0xꢀD
C/LFE Out
0x4
Pin Complex
C/LFE pin drivers. Contains the output amplifier for C/LFE
gain control. Supports the left/right channel swap function.
Supports multitasking as either the C/LFE outputs or can be
configured as the MICꢀ/2 inputs. Supports microphone bias
(VREF_OUT).
Table 59. Mono Out
NID
Name
TID
Type
Description
0xꢀE
Mono Out
0x4
Pin Complex
MONO_OUT Pin driver. Contains the output amplifier for
MONO_OUT gain control.
Rev. 0 | Page ꢀ8 of 56
AD1986A
Table 60. MIC_1/2 In
NID
Name
TID
Type
Description
0xꢀF
MIC_ꢀ/2 In
0x4
Pin Complex
MIC_ꢀ/2 IN pin driver. Can be configured as a microphone or
Line_In input.
Table 61. Line In
NID
Name
TID
Type
Description
0x20
Line In
0x4
Pin Complex
LINE_IN pin driver. Can be configured as a Line_In or
microphone input.
Table 62. Aux In
NID
Name
TID
Type
Description
0x2ꢀ
Aux In
0x4
Pin Complex
AUX_IN pin driver. Line level auxiliary input.
Table 63. CD In
NID
Name
TID
Type
Description
0x22
CD In
0x4
Pin Complex
CD_IN pin driver. Differential, low noise, analog CD audio
input.
Table 64. Phone In
NID
Name
TID
Type
Description
0x23
Phone In
0x4
Pin Complex
PHONE_IN pin driver. Mono line level input.
Table 65. PCBeep In
NID
Name
TID
Type
Description
0x24
PCBeep In
0x4
Pin Complex
PCBEEP_IN pin driver. Mono line level input. When the
ADꢀ986A is in reset, the signal on this pin is routed to all
output capable pins. Used for BIOS POST beeps or messages.
Table 66. S/PDIF Out
NID
Name
TID
Type
Description
0x25
S/PDIF Out
0x4
Pin Complex
Digital S/PDIF output drivers. This pin can be hardware-
enabled by connecting an external resistor to DVSS or by
software control.
Table 67. Analog Power-Down
NID
Name
TID
Type
Description
0x26
Analog Power-Down
0x5
Power Widget
Controls power on analog mixer and associated amplifiers.
This will control the power state of all widgets in its
connection list.
Table 68. MIC/C/LFE Mixer
NID
Name
TID
Type
Description
0x27
MIC / C/LFE Mixer
0x2
Audio Mixer
Mixes the MICꢀ/2_IN and C/LFE input signals together to
support simultaneous microphones on front and rear panels.
Multiple microphones do not have individual gain controls.
Table 69. MIC/Line In Mixer
NID
Name
TID
Type
Description
0x28
MIC / Line In Mixer
0x2
Audio Mixer
Mixes the MICꢀ/2_IN and LINE_IN input signals together to
support simultaneous microphones on front and rear panels.
Multiple microphones do not have individual gain controls.
Rev. 0 | Page ꢀ9 of 56
AD1986A
Table 70. C/LFE/Line In Mixer
NID
Name
TID
Type
Description
0x29
C/LFE / Line In Mixer
0x2
Audio Mixer
Mixes the C/LFE and LINE_IN input signals together to
support simultaneous microphones on front and rear panels.
Multiple microphones do not have individual gain controls.
Table 71. MIC/Line In/C/LFE Mixer
NID
Name
TID
Type
Description
0x2A
MIC/Line In/C/LFE Mixer
0x2
Audio Mixer
Mixes the MICꢀ/2_IN, LINE_IN and C/LFE input signals to
support simultaneous microphones on front and rear panels.
Multiple microphones do not have individual gain controls.
Table 72. MIC_1/2 Mixer
NID
Name
TID
Type
Description
0x2B
MIC_ꢀ/2 Mixer
0x2
Audio Mixer
Mixes the left and right channels of the selected microphone
input into a mono stream. This signal drives both the left and
right channels of the following circuitry. Used to mix two
mono microphones on separate jacks. Left and right
microphones can be programmed with separate gain boost
(0 dB, ꢀ0 dB, 20 dB, or 30 dB), but do not have any other gain
or mute controls.
Rev. 0 | Page 20 of 56
AD1986A
AC ’97 REGISTER DETAILS
RESET (REGISTER 0x00)
Writing any value to this register performs a register reset, which causes all registers to revert to their default values. The serial
configuration (0x74) register will not reset the SLOT16, REGM [2:0], SPOVR, SPAL, SPDZ, and SPLNK. These bits are reset on a hard,
hardware, or power-on reset. The REGM and serial configuration bits are reset only by an external hardware reset.
The AC ’97, Revision 2.3, Page 1 registers codec class/rev (0x601), PCI SVID (0x621), PCI SID (0x641), function information (0x681—per
supported function), and sense register ST [3:0] bits (0x6A1 D [15:13]—per supported function) are reset only on a power-on reset. To
satisfy the AC ’97, Revision 2.3 requirements, these registers/bits are sticky across all software and hardware resets.
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
Reg Name D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00 Reset
x
SE4
SE3
SE2
SEꢀ
SE0
ID9 ID8
ID7
ID6
ID5
ID4
ID3
ID2
IDꢀ
ID0
0x0290
Table 73.
Register
Function
The ID decodes the capabilities of the ADꢀ986A based on the functions.
ID [9:0] (RO)
(Identify
Capability)
Bit
Function
AD1986A ID [9:0]
ID0
IDꢀ
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Dedicated MIC PCM In channel
Reserved (per AC ’97, Revision 2.3)
Bass and treble control
Simulated stereo (mono to stereo)
Headphone out support
Loudness (bass boost) support
ꢀ8-bit DAC resolution
20-bit DAC resolution
ꢀ8-bit ADC resolution
20-bit ADC resolution
0
0
0
0
ꢀ
0x290
0
0
ꢀ
0
ꢀ
SE [4:0] (RO)
(Stereo
The ADꢀ986A does not provide hardware 3D stereo enhancement
(all bits are zero).
Default: 0x00
Enhancement)
x
Reserved.
Default: 0
MASTER VOLUME (REGISTER 0x02)
This register controls the LINE_OUT, SURROUND, and CENTER/LFE outputs’ mute and volume controls in unison. Each volume sub-
register contains five bits, generating 32 volume steps of −1.5 dB each for a range of 0 dB to −46.5 dB.
The headphone output (HP_OUT) mute and volume are controlled separately by the headphones volume register (0x04).The mono
output (MONO_OUT) mute and volume are controlled separately by the mono volume register (0x06). To control the LINE_OUT,
SURROUND, and CENTER/LFE volumes separately, use the front DAC volume register (0x18) for LINE_OUT; the surround DAC
Volume register (0x38) for SURROUND; and the C/LFE DAC volume register (0x36) for CENTER/LFE.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1
D0
Default
0x02 Master
Volume
LM
x
x
LV4 LV3 LV2 LVꢀ LV0 RM
x
x
RV4 RV3 RV2 RVꢀ RV0 0x8080
Rev. 0 | Page 2ꢀ of 56
AD1986A
Table 74.
Register
Function
L/RV [4:0]
(Left/Right
Volume)
Left/right volume controls the left/right channel output gains from 0 dB to –46.5 dB.
The least significant bit represents –ꢀ.5 dB.
L/RM
L/RV [4:0]
0 0000
0 ꢀꢀꢀꢀ
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
Default
0
0
0
ꢀ
0 dB
Default
−22.5 dB attenuation
−46.5 dB attenuation
Muted
L/RM
(Left/right mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
HEADPHONE VOLUME (REGISTER 0x04)
This register controls the HP_OUT mute and volume controls. Each volume subregister contains five bits, generating 32 volume steps of
−1.5 dB each for a range of 0 dB to −46.5 dB.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1
D0
Default
0x04 Headphones LM
Volume
x
x
LV4 LV3 LV2 LVꢀ LV0 RM
x
x
RV4 RV3 RV2 RVꢀ RV0 0x8080
Table 75.
Register
Function
L/RV [4:0]
(Left/Right
Volume)
Left/right volume controls the left/right channel output gains from 0 dB to –46.5 dB.
The least significant bit represents –ꢀ.5 dB.
L/RM
L/RV [4:0]
0 0000
0 ꢀꢀꢀꢀ
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
Default
0
0
0
ꢀ
0 dB
Default
−22.5 dB attenuation
−46.5 dB attenuation
Muted
L/RM
(Left/Right Mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
MONO VOLUME (REGISTER 0x06)
This register controls the MONO_OUT mute and volume control. The volume register contains five bits, generating 32 volume steps of
−1.5 dB each for a range of 0 dB to −46.5 dB.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
V4 V3 V2 Vꢀ V0 0x8000
0x06 Mono Volume
M
x
x
x
x
x
x
x
x
x
x
Table 76.
Register
Function
Volume controls the output gain from 0 dB to –46.5 dB. The least significant bit represents –ꢀ.5 dB.
V [4:0]
(Volume)
M
0
0
0
ꢀ
V [4:0]
0 0000
0 ꢀꢀꢀꢀ
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
Default
0 dB
Default
−22.5 dB attenuation
−46.5 dB attenuation
Muted
M (Mute)
x
Mutes the output.
Reserved.
Default: muted (0xꢀ)
Default: 0
Rev. 0 | Page 22 of 56
AD1986A
PC BEEP (REGISTER 0x0A)
This controls the level of the analog PC beep or the level and frequency of the digital PC beep. The volume register contains four bits,
generating 16 volume steps of −3.0 dB each for a range of 0 dB to −45.0 dB. The tone frequency can be set between 47 Hz to 12,000 Hz or
disabled.
Per Intel’s BIOS writer’s guide, the PC beep signal should play via headphone out, line out, and mono out paths. BIOS algorithms should
unmute the PC beep register and the path to each output, and set the volume levels for playback.
When the AD1986A is in reset (the external RESET pin is low), the PCBEEP_IN pin is connected internally to all of the device output
pins (HEADPHONE L/R, LINE_OUT L/R, MONO_OUT, SURROUND L/R, and CENTER/LFE). There are no amplifiers or attenuators
on this path and the external circuitry connected to this pin should anticipate the drive requirements for the multiple output sources.
Headphones connected to output pins will substantially load the signal.
Reg
0x0A PC
Beep
Name
D15 D14
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
F7 F6 F5 F4 F3 F2 Fꢀ F0 V3 V2 Vꢀ V0 0x8000
M
A/DS
x
x
Table 77.
Register
Function
V [3:0]
(Analog or
Digital
Controls the gain into the output mixer from 0 dB to −45.0 dB. The least significant bit represents −3.0 dB. The gain default
is 0 dB and muted.
M
0
V3...V0
0000
Function
0 dB
Default
Volume)
Default
0
ꢀ
ꢀꢀꢀꢀ
xxxx
−45 dB attenuation
Muted
F [7:0]
(PC Beep
Frequency)
The result of dividing the 48 kHz clock by four times this number, allowing tones from 47 Hz to ꢀ2 kHz. A value of 0x00
disables internal PC beep generation. The digitally-generated signal is close to a square wave and is not intended to be a
high quality signal.
F7...F0
0000
Function
Disabled
Default
000ꢀ
ꢀꢀꢀꢀ
ꢀ2,000 Hz tone
47 Hz tone
A/DS
(PC Beep
Source)
Selects either the digital PC beep generator (= 0) or analog PCBEEP pin (= ꢀ). When the
Default: digitally-selected
codec is in reset mode the analog PCBEEP pin is routed to the outputs via a high impedance (0x0)
path. Once out of reset, this bit must be programmed to a ꢀ to pass through any signals on
the analog PCBEEP pin. Designers can choose not to connect the analog PCBEEP pin and
use the digital PC beep generator solely.
M
When this bit is set to ꢀ, the PC beep signal (analog or digital) is muted.
Default: muted (0xꢀ)
(PC Beep
Mute)
x
Reserved.
Default: 0
PHONE VOLUME (REGISTER 0x0C)
This register controls the PHONE_IN mute and gain to the analog mixer section. The volume register contains five bits, generating
32 volume steps of 1.5 dB each for a range of 12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
V4 V3 V2 Vꢀ V0 0x8008
0x0C Phone
Volume
M
x
x
x
x
x
x
x
x
x
x
Rev. 0 | Page 23 of 56
AD1986A
Table 78.
Register
Function
V [4:0]
(Volume)
Controls the gain of this input to the analog mixer from +ꢀ2.0 dB to −34.5 dB. The least significant bit represents −ꢀ.5
dB.
MV
0
0
0
ꢀ
[4:0]
Function
ꢀ2 dB gain
0 dB
−34.5 dB attenuation
Muted
Default
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
Default
M (Mute)
x
Mutes the input to the analog mixer.
Reserved.
Default: muted (0xꢀ)
Default: 0
MICROPHONE VOLUME (REGISTER 0x0E)
This register controls the MIC_1 (left) and MIC_2 (right) channels’ gain, boost, and mute to the analog mixer section. The volume register
contains five bits, generating 32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC
gain (see Register 0x1C).
In typical stereo microphone applications, the signal paths must be identical and should be set to the same gain, boost, and mute values.
With stereo controls, this input is capable of using nonmicrophone sources by disabling the microphone boost (M20 bit = 0).
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
D5 D4
D3
D2
D1
D0
Default
0x0E Microphone LM
Volume
x
x
LV4 LV3 LV2 LVꢀ LV0 RM M20
x RV4 RV3 RV2 RVꢀ RV0 0x8888
Table 79.
Register
Function
Controls the left/right channel gains of this input to the analog mixer from +ꢀ2 dB to −34.5 dB. The least significant bit
L/RV [4:0]
(Left/Right represents −ꢀ.5 dB.
Volume)
L/RM
L/RV [4:0]
Function
ꢀ2 dB gain
0 dB
−34.5 dB attenuation
Mute
Default
0
0
0
ꢀ
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
Default
M20
(MIC_ꢀ/2
Gain
Enables additional gain to increase the microphone sensitivity. This controls the boost of both the MIC_ꢀ and MIC_2 channels.
The nominal gain boost by default is 20 dB; however, MBG0 [ꢀ:0] bits (Register 0x76), allow changing the gain boost to ꢀ0 dB
or 30 dB if necessary.
Boost)
M20
MGB0 [1:0]
Boost Gain
0 dB gain
20 dB gain
ꢀ0 dB gain
Mute
Default
0
ꢀ
ꢀ
ꢀ
xx
00
0ꢀ
x xxxx
Default: disabled
Default
L/RM
(Left/Right
Mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
Rev. 0 | Page 24 of 56
AD1986A
LINE_IN VOLUME (REGISTER 0x10)
This register controls the LINE_IN gain and mute to the analog mixer section. The volume register contains five bits, generating
32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1
D0
Default
0xꢀ0 Line In
Volume
LM
x
x
LV4 LV3 LV2 LVꢀ LV0 RM
x
x
RV4 RV3 RV2 RVꢀ RV0 0x8888
Table 80.
Register
Function
L/RV [4:0]
(Left/Right
Volume)
Controls the left/right channel gains of this input to the analog mixer from +ꢀ2 dB to −34.5 dB. The least significant bit
represents −ꢀ.5 dB.
L/RM
L/RV [4:0]
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
ꢀ2 dB gain
0 dB
Default
0
0
0
ꢀ
Default
−34.5 dB attenuation
Muted
L/RM
(Left/Right
Mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
CD VOLUME (REGISTER 0x12)
This register controls the CD gain and mute to the analog mixer section. The volume register contains five bits, generating 32 volume
steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).
Many operating systems will play CDs directly using the digital data from the CD tracks. This control will only affect CD audio playback
if it is enabled for analog and this input is connected to the CD player analog connection.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1
D0
Default
0xꢀ2 CD Volume LM
x
x
LV4 LV3 LV2 LVꢀ LV0 RM
x
x
RV4 RV3 RV2 RVꢀ RV0 0x8888
Table 81.
Register
Function
L/RV [4:0]
(Left/Right
Volume)
Controls the left/right channel gains of this input to the analog mixer from +ꢀ2 dB to –34.5 dB. The least significant bit
represents –ꢀ.5 dB.
L/RM
L/RV [4:0]
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
ꢀ2 dB gain
0 dB
Default
0
0
0
ꢀ
Default
−34.5 dB attenuation
Muted
L/RM
(Left/Right
Mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
Rev. 0 | Page 25 of 56
AD1986A
AUX VOLUME (REGISTER 0x16)
This register controls the AUX_IN gain and mute to the analog mixer section. The volume register contains five bits, generating
32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1
D0
Default
0xꢀ6 AUX
Volume
LM
x
x
LV4 LV3 LV2 LVꢀ LV0 RM
x
x
RV4 RV3 RV2 RVꢀ RV0 0x8888
Table 82.
Register
Function
L/RV [4:0]
(Left/Right
Volume)
Controls the left/right channel gains of this input to the analog mixer from +ꢀ2 dB to −34.5 dB. The least significant bit
represents −ꢀ.5 dB.
L/RM
L/RV [4:0]
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
ꢀ2 dB gain
0 dB
Default
0
0
0
ꢀ
Default
−34.5 dB attenuation
Mute
L/RM
(Left/Right
Mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
FRONT DAC VOLUME (REGISTER 0x18)
This register controls the front DAC gain and mute to the analog mixer section. The volume register contains five bits, generating
32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1
D0
Default
0xꢀ8 Front DAC
Volume
LM LV4 LV3 LV2 LVꢀ LV0 RM RV4 RV3 RV2 RVꢀ RV0 0x8888
x
x
x
x
Table 83.
Register
Function
L/RV [4:0]
(Left/Right Volume)
Controls the left/right channel gains of this input to the analog mixer from +ꢀ2 dB to −34.5 dB. The least significant
bit represents −ꢀ.5 dB.
L/RM
L/RV [4:0]
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
Default
0
0
0
ꢀ
+ꢀ2 dB gain
0 dB
−34.5 dB attenuation
Mute
Default
L/RM
(Left/Right Mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
Rev. 0 | Page 26 of 56
AD1986A
ADC SELECT (REGISTER 0x1A)
This register selects the record source for the ADC, independently for the right and left channels. The default value is 0x0000, which
corresponds to the MIC_1/2 input for both channels.
Reg
0xꢀA ADC
Select
Name
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2
D1
D0
Default
x
x
x
x
x
LS2
LSꢀ LS0
x
x
x
x
x
RS2 RSꢀ RS0 0x0000
Table 84.
Register
LS [2:0]
000
Left Record Source
Function
Default
Left
LS [2:0]
(Left Record Select)
MIC_ꢀ/2 selector left channel
CD_IN
00ꢀ
0ꢀ0
Muted
–
0ꢀꢀ
AUX_IN
Left
ꢀ00
LINE_IN
Left
ꢀ0ꢀ
Stereo output mix
Mono output mix
PHONE_IN
Left
ꢀꢀ0
Mono
Mono
ꢀꢀꢀ
RS [2:0]
(Right Record Select)
RS [2:0]
000
Right Record Source
MIC_ꢀ/2 selector left channel
CD_IN
Default
Right
–
00ꢀ
0ꢀ0
Muted
0ꢀꢀ
AUX_IN
Right
Right
Right
Mono
Mono
ꢀ00
LINE_IN
ꢀ0ꢀ
Stereo output mix
Mono output mix
PHONE_IN
ꢀꢀ0
ꢀꢀꢀ
Table 85. Microphone Selector
OMS [2:0]1
000
000
000
000
000
00ꢀ
00ꢀ
00ꢀ
00ꢀ
00ꢀ
0ꢀx
MMIX2
2CMIC3
MS4
Left Channel5
Right Channel
0
0
0
0
ꢀ
0
0
0
0
ꢀ
0
0
0
0
ꢀ
0
0
0
0
ꢀ
0
0
ꢀ
ꢀ
x
0
0
ꢀ
ꢀ
x
0
0
ꢀ
ꢀ
x
0
0
ꢀ
ꢀ
x
0
ꢀ
0
ꢀ
x
0
ꢀ
0
ꢀ
x
0
ꢀ
0
ꢀ
x
0
ꢀ
0
ꢀ
x
MIC_ꢀ (default)
MIC_2
MIC_ꢀ
MIC_2
MIC_2
MIC_ꢀ
MIC_ꢀ + MIC_2 (mixed)
LINE_IN left
LINE_IN right
LINE_IN right
LINE_IN left
LINE_IN left
LINE_IN right
Line in—left + right (mixed)
CENTER
0ꢀx
0ꢀx
0ꢀx
0ꢀx
LFE
CENTER
LFE
LFE
CENTER
CENTER + LFE (mixed)
MIC_ꢀ + CENTER (mixed)
MIC_2 + LFE (mixed)
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
MIC_ꢀ + CENTER (mixed)
MIC_2 + LFE (mixed)
MIC_2 + LFE (mixed)
MIC_ꢀ + CENTER (mixed)
MIC_ꢀ + MIC_2 + CENTER + LFE (mixed)
Rev. 0 | Page 27 of 56
AD1986A
OMS [2:0]1
ꢀ0ꢀ
ꢀ0ꢀ
ꢀ0ꢀ
ꢀ0ꢀ
ꢀ0ꢀ
MMIX2
2CMIC3
MS4
0
ꢀ
0
ꢀ
x
Left Channel5
Right Channel
MIC_ꢀ + LINE_IN left (mixed)
MIC_2 + LINE_IN right (mixed)
0
0
0
0
ꢀ
0
0
0
0
ꢀ
0
0
0
0
ꢀ
0
0
ꢀ
ꢀ
x
0
0
ꢀ
ꢀ
x
0
0
ꢀ
ꢀ
x
MIC_ꢀ + LINE_IN left (mixed)
MIC_2 + LINE_IN right (mixed)
MIC_2 + LINE_IN right (mixed)
MIC_ꢀ + LINE_IN left (mixed)
MIC_ꢀ + MIC_2 + LINE_IN left + LINE right (mixed)
LINE_IN left + CENTER (mixed)
ꢀꢀ0
ꢀꢀ0
ꢀꢀ0
ꢀꢀ0
0
ꢀ
0
ꢀ
LINE_IN right + LFE (mixed)
LINE_IN left + CENTER (mixed)
LINE_IN right + LFE (mixed)
LINE_IN right + LFE (mixed)
LINE_IN left + CENTER (mixed)
LINE_IN left + LINE_IN right + CENTER + LFE (mixed)
MIC_ꢀ + LINE_IN left + CENTER (mixed)
MIC_2 + LINE_IN right + LFE (mixed)
ꢀꢀ0
x
ꢀꢀꢀ
ꢀꢀꢀ
ꢀꢀꢀ
ꢀꢀꢀ
0
ꢀ
0
ꢀ
MIC_ꢀ + LINE_IN left + CENTER (mixed)
MIC_2 + LINE_IN right + LFE (mixed)
MIC_2 + LINE_IN right + LFE (mixed)
MIC_ꢀ + LINE_IN left + CENTER (mixed)
ꢀꢀꢀ
x
MIC_ꢀ + MIC_2 + LINE_IN left + LINE_IN right + CENTER + LFE (mixed)
ꢀ To select the alternate pins as a microphone source, see the OMS [2:0] bit (Register 0x74).
2 To mix the left/right MIC channels, see MMIX bit (Register 0x7A).
3 For dual MIC recording, see 2CMIC bit (Register 0x76) to enable simultaneous recording into L/R channels.
4 To swap left/right MIC channels, see the MS bit (Register 0x20) for MIC_ꢀ/2 selection.
5 The MONO_OUT pin can be connected to the left channel of the microphone selector and is affected by these bits.
ADC VOLUME (REGISTER 0x1C)
This register controls the mute and gain of the ADC record path. The volume register contains four bits, generating 16 volume steps of
1.5 dB each for a range of 0 dB to 22.5 dB.
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
D2
D1
D0
Default
0xꢀC ADC Volume LM
x
x
x
LV3 LV2 LVꢀ LV0 RM
x
x
x
RV3 RV2 RVꢀ RV0 0x8080
Table 86.
Register
Function
L/RV [4:0]
(Left/Right
Volume)
Controls the left/right channel gains of this input to the analog mixer from 0 dB to 22.5 dB. The least significant bit
represents ꢀ.5 dB.
L/RM
L/RV [3:0]
0000
Function
0 dB
Default
0
0
0
ꢀ
Default
ꢀ000
ꢀꢀꢀꢀ
xxxx
ꢀ2.0 dB gain
22.5 dB gain
Muted
L/RM
(Left/Right Mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
Rev. 0 | Page 28 of 56
AD1986A
GENERAL-PURPOSE (REGISTER 0x20)
This register should be read before writing to generate a mask for only the bit(s) that need to be changed.
Reg Name
D15 D14 D13 D12 D11
D10
D9
D8 D7
D6 D5 D4 D3 D2 D1 D0 Default
0x20 General-
Purpose
x
x
x
x
DRSSꢀ DRSS0 MIX MS LPBK
x
x
x
x
x
x
x
0x0000
Table 87.
Register
Function
Default
LPBK
(Loop-
Back
This bit enables the digital internal loop back from the ADC to the front DAC. This feature is normally used for
testing and troubleshooting. See LBKS bit in Register 0x74 for changing the loop back path to use the
SURROUND or CENTER/LFE DACs.
Default:
disabled
(0x0)
Control)
MS
(MIC
Select)
Used in conjunction with OMS [2:0] (0x74 Dꢀ0:08]), 2CMIC (0x76 D06) and MMIX (0x7A D02). Selects which MIC
input goes into the ADC0 record selector’s MIC channel inputs. When set, this bit swaps the left and right
channels. Selects mono output audio source.
MIX
MIX
0
ꢀ
Mono Output Connection
(Mono
Output
Select)
MIX—Connected to the mono mixer output.
MIC—Connected to the left channel of the MIC selector and swap.
Default
DRSS [ꢀ:0] The DRSS bits specify the slots for the n+ꢀ sample outputs. PCM L (n+ꢀ) and PCM R (n+ꢀ) data are by default
(Double
Rate Slot
Select)
provided in output Slots ꢀ0 and ꢀꢀ.
DRSS [1:0]
Function
00
0ꢀ
ꢀx
PCM L, R (n+ꢀ) data is on Slots ꢀ0 and ꢀꢀ
PCM L, R (n+ꢀ) data is on Slots 7 and 8
Reserved
Default
x
Reserved.
Default: 0
AUDIO INT AND PAGING (REGISTER 0x24)
This register controls the audio interrupt and register paging mechanisms.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
D2
D1
D0
Default
0x24 Audio Int and I4
Paging
I3 I2 Iꢀ I0 PG3 PG2 PGꢀ PG0 0xxx00
x
x
x
x
x
x
x
Table 88.
Register
Function
PG [3:0]
(Page Selector
(Read/Write))
This register is used to select a descriptor of ꢀ6 word pages between Registers 0x60 to 0x6F. A value of 0x0 is used to
select vendor-specific space to maintain compatibility with AC ’97 Revision 2.2 vendor specific registers. System
software can determine implemented pages by writing the page number and reading the value back. If the value read
back does not match the value written, the page is not implemented. All implemented pages must be in consecutive
order (that is, Page 0x2 cannot be implemented without Page 0xꢀ).
PG [3:0]
Addressing Page Selection
Page 0 (vendor) registers
Page ID 0ꢀ, registers defined in AC ’97, Revision 2.3
Reserved
Default
000 (Page 0)
00ꢀ (Page ꢀ)
Page 0x–0xF
Default
I0
Software should not unmask the interrupt unless the AC ’97 controller ensures that no conflict is possible with modem
Slot ꢀ2—GPI functionality. AC ’97 Revision 2.2-compliant controllers will not likely support audio codec interrupt
infrastructure. In that case, software can poll the interrupt status after initiating a sense cycle and waiting for sense
cycle max delay (defined by software) to determine if an interrupting event has occurred.
(Interrupt Enable
(Read/Write))
I0
0
ꢀ
Interrupt Mask Status
Interrupt generation is masked
Interrupt generation is unmasked
Default
Rev. 0 | Page 29 of 56
AD1986A
Register
Function
Iꢀ
Writing a ꢀ to this bit causes a sense cycle start if supported. If a sense cycle is in progress, writing a 0 to this bit will
abort the sense cycle. The data in the sense result register (0x6A, Page 0ꢀ) can or can not be valid, as determined by
the IV bit.
(Sense Cycle
(Read/Write))
I1
Read
Write
0
Sense cycle completed (or not initiated)
Default
Aborts sense cycle (if in
process)
ꢀ
Sense cycle still in process
Initiate sense cycle
These bits will indicate the cause(s) of an interrupt. This information should be used to service the correct interrupting
event(s). If the Interrupt Status (Bit I4) is set, one or both of these bits must be set to indicate the interrupt cause.
Hardware will reset these bits back to zero when the interrupt status bit is cleared.
I [3:2]
(Interrupt Cause
(RO))
I2
0
Interrupt Status
Sense status has not changed (did not cause interrupt). Default
Sense cycle completed or new sense information is available
ꢀ
I3
0
GPIO status change did not cause interrupt
GPIO status change caused interrupt
ꢀ
I4
Interrupt event is cleared by writing a ꢀ to this bit. The interrupt bit will change regardless of condition of interrupt
enable (I0) status. An interrupt in the GPI in Slot ꢀ2 in the AC link will follow this bit change when interrupt enable (I0)
is unmasked. If this bit is set, one or both of I3 or I2 must be set to indicate the interrupt cause.
(Interrupt Status
(Read/Write))
I4
Read
Write
0
ꢀ
Interrupt clear
Interrupt generated
Default
No operation
Clears interrupt
Default: 0
x
Reserved.
POWER-DOWN CTRL/STAT (REGISTER 0x26)
The ready bits are read only; writing to REF, ANL, DAC, and ADC has no effect. These bits indicate the status for the AD1986A
subsections. If the bit is 1 then that subsection is ready.‘Ready’ is defined as the subsection able to perform in its nominal state.
Reg Name
D15
D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2
D1
D0
Default
0x26 Power-
Down
EAPD PR6 PR5 PR4 PR3 PR2 PRꢀ PR0
x
x
x
x
REF ANL DAC ADC 0x000x
Ctrl/Stat
Table 89.
Register
ADC
ADC Status
0
ꢀ
ADC not ready
ADC (RO)
(ADC Section
Status (RO))
ADC sections ready to transmit data
DAC
Front DAC Status
ADC (RO)
((Front DAC
Status (RO))
0
ꢀ
ADC not ready
ADC sections ready to transmit data
Analog Status
ANL (RO)
ANL
(Analog
0
ꢀ
Analog amplifiers, attenuators, and mixers not ready
Analog amplifiers, attenuators, and mixers ready
Amplifiers,
Attenuators and
Mixers Status
(RO))
Rev. 0 | Page 30 of 56
AD1986A
Register
ADC
ADC Status
REF (RO)
VREF_OUT pin output states controlled by the CVREF, MVREF, and LVREF controls in Register 0x70.
(Voltage
REF
0
VREF Status
References, VREF
and VREF_OUT
status (read
only))
Voltage References, VREF and VREF_OUT not ready.
Voltage References, VREF, and VREF_OUT up to nominal level.
ꢀ
PR0
PRꢀ
PR2
PR3
All ADCs and input selectors’ power down: clearing this bit enables VREF regardless of the state of PR3.
Default: all ADCs and input muxes powered on (0x0).
Front DACs power-down. Also powers down the EQ circuitry. Clearing this bit enables VREF regardless of the state of
PR3. Default: all DACs and EQ powered on (0x0).
Analog mixer power-down. (valid if PR7 = 0).
Default: analog mixer powered on (0x0).
All VREF and VREF_OUT pins power-down. May be used in combination with PR2 or by itself. If all the ADCs and DACs
are not powered down, setting this bit will have no effect on the VREFand will only power down VREF_OUT.
Default: All VREFand VREF_OUT pins powered on (0x0).
PR4
PR5
AC-Link Interface power-down. The reference and the mixer can be either up or down, but all power-up sequences
must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec’s
PR4 bit controls the slave codec. In the slave codec the PR4 bit has no effect except to enable or disable PR5.
Default: AC-link Interface powered on (0x0).
Internal Clocks disabled.
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down (for example, PR0, PRꢀ, PR4). The reference
and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5
and PR4 are both set. In multiple codec systems, the master codec’s PR5 controls the slave codec. PR5 is effective in the
slave codec if the master's PR5 bit is clear. Default: internal clocks enabled (0x0).
PR6
Powers down the headphone amplifiers.
Default: HP amp powered on (0x0).
EAPD
EAPD
EAPD Pin Status
0
ꢀ
Sets the EAPD pin low, enabling an external power amplifier.
Sets the EAPD pin high, shutting the external power amplifier off.
Default
x
Reserved.
Default: 0
EXTENDED AUDIO ID (REGISTER 0x28)
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one
or more of the extended audio features are supported.
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x28
Ext’d Audio ID
IDꢀ
ID0
x
X
REVꢀ
REV0
AMAP
LDAC
SDAC
CDAC
DSAꢀ
DSA0
x
SPDF
DRA
VRA
0x0BC7
Table 90.
Register
VRA (RO)
SPDIF (RO)
DRA (RO)
DSA [ꢀ:0]
Description
Setting
= ꢀ
Function
Variable rate PCM audio: read only
SPDIF support: read only
Variable rate PCM audio supported
SPDIF transmitter supported (IEC958)
= ꢀ
Double rate audio: read only
DAC slot assignment (read/write)
= ꢀ
Double rate audio supported for DAC0 L/R
Front DAC
Surround DAC
C/LFE DAC
Default
DSA [1:0]
Left
3
7
6
ꢀ0
Right
Left
7
6
ꢀ0
3
Right
Left
6
ꢀ0
3
Right
00
0ꢀ
ꢀ0
ꢀꢀ
4
8
9
ꢀꢀ
8
9
ꢀꢀ
4
9
ꢀꢀ
4
Default
7
8
Rev. 0 | Page 3ꢀ of 56
AD1986A
Register
CDAC (RO)
SDAC (RO)
LDAC (RO)
AMAP (RO)
REV [ꢀ:0] (RO)
ID [ꢀ:0] (RO)
x
Description
Setting
= ꢀ
Function
PCM CENTER DAC: read only
PCM Surround DAC: read only
PCM LFE DAC: read only
Slot DAC mappings: read only
AC97 version: read only
Codec configuration: read only
Reserved
PCM center DAC supported
CM Surround DACs supported
PCM LFE DAC supported
Codec ID based slot/DAC mappings
Codec is AC ’97, Revision 2.3-compliant
Primary AC ‘97
= ꢀ
= ꢀ
= ꢀ
= ꢀ0
= 00
Default: 0
EXT’D AUDIO STAT/CTRL (REGISTER 0x2A)
The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x2A
Ext’d Audio Stat/Ctrl
x
x
PRK
PRJ
PRI
SPCV
x
LDAC
SDAC
CDAC
SPSAꢀ
SPSA0
x
SPDIF
DRA
VRA
0x0xx0
Table 91.
Register
Function
Enables variable rate audio mode. Enables sample rate registers and SLOTREQ signaling.
VRA
(Variable Rate
Audio)
VRA
VRA State
Default
0
ꢀ
Disabled, sample rate 48 kHz for all ADCs and DACs
Enabled, ADCs and DACs can be set to variable sample rates
Default
DRA
(Double Rate
Audio)
DRA = ꢀ. Enables double-rate audio mode in which data from PCM L and PCM R in Output Slots 3 and 4 is used in
conjunction with PCM L (n + ꢀ) and PCM R (n + ꢀ) data to provide DAC streams at twice the sample rate designated by the
PCM front sample rate control register. When using the double rate audio, only the front DACs are supported and all other
DACs (surround, center, and LFE) are automatically powered down. The slot that contains the additional data is
determined by the DRSS [ꢀ:0] bits (0x20 D [ꢀꢀ:ꢀ0]). Note that DRA can be used without VRA, in which case the converter
rates are forced to 96 kHz if DRA = ꢀ.
DRA
DRA State
Default
0
ꢀ
Disabled, DACs sample at the programmed rate
Enabled, DACs sample at twice (2×) the programmed rate
Default
SPDIF
SPDIF transmitter subsystem enable/disable bit (read/write).
This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set
high, if the SPDIF pin (48) is pulled down at power-up enabling the codec transmitter logic. If the SPDIF pin is floating or
pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the SPDIF
transmitter is not available. This bit must always be read back, to verify that the SPDIF transmitter is actually enabled.
SPDIF
Function
0
ꢀ
Disables the S/PDIF transmitter
Enables the S/PDIF transmitter
Default
AC '97 Revision 2.2 AMAP-compliant default SPDIF slot assignments.
SPSA [ꢀ:0]
(SPDIF Slot
Assignment
Bits:
SPSA [1:0]
S/PDIF Slot Assignment
3 and 4
00
Default
0ꢀ
7 and 8
ꢀ0
6 and 9
(Read/Write))
ꢀꢀ
ꢀ0 and ꢀꢀ
CDAC (RO)
(Center DAC
Status)
CDAC
Center DAC Status
Center DAC not ready
Center DAC section ready to receive data
Surround DAC not ready
Surround DAC section ready to receive data
LFE DAC Status
0
ꢀ
0
ꢀ
LDAC (RO)
(LFE DAC
Status)
LDAC
0
ꢀ
LFE DAC not ready
LFE DAC section ready to receive data
SPCV (RO)
Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed
Rev. 0 | Page 32 of 56
AD1986A
Register
Function
(SPDIF
SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status.
Configuration
Valid)
SPCV
S/PDIF Configuration Status
0
ꢀ
Invalid SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS)
Valid SPDIF configuration
PRI
Actual status reflected in the CDAC (0x3A D06) bit.
(Center DAC
Power-Down)
PRI
0
CENTER DAC Power Status
Power on center DAC
Default
ꢀ
Power down center DAC
PRJ
Actual status reflected in the SDAC bit.
(Surround
DACs Power-
Down)
PRJ
0
ꢀ
Surround DACs Power Control
Power on surround DACs
Power down surround DACs
Default
PRK
Actual status reflected in the LDAC bit.
(LFE DAC
Power-Down)
PRK
LFE DACs Power Control
0
Power on LFE DAC
Default
ꢀ
Power down LFE DAC
x
Reserved.
Default: 0
FRONT DAC PCM RATE (REGISTER 0x2C)
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register can be programmed with the actual sample rate.
To use 96 kHz in AC ’97 mode set the double rate audio (DRA) bit (0x2A D01). When using DRA in AC ’97, only the front DACs are
supported and all other DACs (surround, center, and LFE) are automatically powered down.
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0x2C Front DAC PCM
Rate
Rꢀ5 Rꢀ4 Rꢀ3 Rꢀ2 Rꢀꢀ Rꢀ0 R9 R8 R7 R6 R5 R4 R3 R2 Rꢀ R0 0xBB80
Table 92.
Register Function
R [ꢀ5:0]
(Sample
Rate)
The sampling frequency range is from 7 kHz (0x0ꢀB58) to 48 kHz (0xBB80) in ꢀ Hz increments. If 0 is written to VRA, then the
sample rates are reset to 48 kHz.
Rev. 0 | Page 33 of 56
AD1986A
SURROUND DAC PCM RATE (REGISTER 0x2E)
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0, this register is forced to 48 kHz (0xBB80). If VRA is 1, this register can be programmed with the actual sample rate.
If the DRA bit (0x2A D01) is set, the surround DAC is inoperative and automatically powered down.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0x2E SURR_ꢀ DAC PCM Rꢀ5 Rꢀ4 Rꢀ3 Rꢀ2 Rꢀꢀ Rꢀ0 R9 R8 R7 R6 R5 R4 R3 R2 Rꢀ R0 0xBB80
Rate
Table 93.
Register Function
R [ꢀ5:0]
(Sample
Rate)
The sampling frequency range is from 7 kHz (0x0ꢀB58) to 48 kHz (0xBB80) in ꢀ Hz increments. If zero is written to VRA then the
sample rates are reset to 48 kHz.
C/LFE DAC PCM RATE (REGISTER 0x30)
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit
(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register can be programmed with the actual sample rate.
If the DRA bit (0x2A D01) is set, the C/LFE DAC is inoperative and automatically powered down.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
Rꢀ5 Rꢀ4 Rꢀ3 Rꢀ2 Rꢀꢀ Rꢀ0 R9 R8 R7 R6 R5 R4 R3 R2 Rꢀ R0 0xBB80
0x30 C/LFE DAC
PCM Rate
Table 94.
Register Function
R [ꢀ5:0]
(Sample
Rate)
The sampling frequency range is from 7 kHz (0x0ꢀB58) to 48 kHz (0xBB80) in ꢀ Hz increments. If 0 is written to VRA then the
sample rates are reset to 48 kHz.
ADC PCM RATE (REGISTER 0x32)
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit (0x2A
D00) is 0 (zero) this register is forced to 48 kHz (0xBB80). If VRA is 1, this register can be programmed with the actual sample rate.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
Rꢀ5 Rꢀ4 Rꢀ3 Rꢀ2 Rꢀꢀ Rꢀ0 R9 R8 R7 R6 R5 R4 R3 R2 Rꢀ R0 0xBB80
0x32 ADC 0 PCM
Rate
Table 95.
Register Function
R [ꢀ5:0]
(Sample
Rate)
The sampling frequency range is from 7 kHz (0x0ꢀB58) to 48 kHz (0xBB80) in ꢀ Hz increments. If 0 is written to VRA then the
sample rates are reset to 48 kHz.
Rev. 0 | Page 34 of 56
AD1986A
C/LFE DAC VOLUME (REGISTER 0x36)
This register controls the CENTER/LFE DAC gain and mute to the output selector section. The volume register contains five bits,
generating 32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.
Note that the left/right association of the center and LFE channels can be swapped at the codec outputs by setting the CSWP bit in
Register 0x74. These controls remain unchanged regardless of the state of CSWP.
Reg
Name
D15
D14 D13 D12
D11
D10
D9
D8
D7
D6 D5 D4
D3
D2
D1
D0
Default
0x36 C/LFE
DAC
LFEM
x
x
LFE4 LFE3 LFE2 LFEꢀ LFE0 CNTM
x
x
CNT4 CNT3 CNT2 CNTꢀ CNT0 0x8888
Volume
Table 96.
Register
CNT [4:0]
Function
Controls the gain of the center channel to the output selector section from +ꢀ2.0 dB to −34.5 dB. The least significant
(Center Volume) bit represents −ꢀ.5 dB.
CNTM
CNT [4:0]
Function
Default
0
0
0
ꢀ
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
+ꢀ2 dB gain
0 dB attenuation
−34.5 dB attenuation
Muted
Default
CNTM
Mutes the center channel.
Default: muted (0xꢀ)
(Center Mute)
LFE [4:0]
(LFE Volume)
Controls the gain of the LFE channel to the output selector section from +ꢀ2.0 dB to −34.5 dB. The least significant bit
represents −ꢀ.5 dB.
LFEM
LFE[4:0]
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
0
0
0
ꢀ
+ꢀ2 dB gain
0 dB attenuation
−34.5 dB attenuation
Muted
Default
LFEM
(LFE Mute)
Mutes the LFE channel.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
SURROUND DAC VOLUME (REGISTER 0x38)
This register controls the surround DAC gain and mute to the output selector section. The volume register contains five bits, generating
32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1
D0
Default
0xꢀ8 Surround
DAC
LM
x
x
LV4 LV3 LV2 LVꢀ LV0 RM
x
x
RV4 RV3 RV2 RVꢀ RV0 0x8888
Volume
Table 97.
Register
Function
L/RV [4:0]
(Left/Right
Volume)
Controls the left/right channel gains of this input to the output selector section from +ꢀ2 dB to -34.5 dB. The least
significant bit represents −ꢀ.5 dB.
L/RM
L/RV [4:0]
0 0000
0 ꢀ000
ꢀ ꢀꢀꢀꢀ
x xxxx
Function
Default
0
0
0
ꢀ
+ꢀ2 dB gain
0 dB
−34.5 dB attenuation
Muted
Default
L/RM
(Left/Right
Mute)
Mutes the left/right channels independently.
Default: muted (0xꢀ)
Default: 0
x
Reserved.
Rev. 0 | Page 35 of 56
AD1986A
SPDIF CONTROL (REGISTER 0x3A)
Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe
in the V-case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in
Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission.
Reg
Name D15 D14
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
/AUDIO
D0
Default
SPDIF
0x3A
V
VCFG SPSR
x
L
CC6 CC5 CC4 CC3 CC2 CCꢀ CC0 PRE COPY
PRO 20000x
Control
Table 98.
Register
Function
Indicates professional use of the audio stream.
PRO
(Professional)
PRO
State
Default
0
ꢀ
Consumer use of channel
Professional use of channel
Default
Default
Default
Default
/AUDIO
(Nonaudio)
Indicates that the data is PCM or another format (such as AC3).
/AUDIO
State
0
ꢀ
Data in PCM format
Data in non-PCM format
COPY
(Copyright)
Allows receivers to make copies of the digital data.
COPY
State
0
ꢀ
Copyright asserted
Copyright not asserted
PRE
(Pre-emphasis)
Disables filter pre-emphasis.
PRE
0
State
Filter pre-emphasis is 50/ꢀ5 µsec
ꢀ
No pre-emphasis
CC [6:0]
(Category Code)
Programmed according to IEC standards, or as appropriate.
Programmed according to IEC standards, or as appropriate.
Chooses between 48.0 kHz and 44.ꢀ kHz S/PDIF transmitter rate.
L
(Generation Level)
SPSR
(SPDIF Transmit
Sample Rate)
SPSR
Transmit Sample Rate
44.ꢀ kHz
48.0 kHz
0
ꢀ
Default
VCFG
(Validity Force Bit)
When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the
validity bit (Dꢀ5) in Register 0x3A (SPDIF control register).
VCFG
V
0
ꢀ
Validity Bit State
Reset Default: 0
Default
0
0
Managed by codec error detection logic
Forced high, indicating subframe data is
invalid
ꢀ
ꢀ
0
ꢀ
Forced low, indicating subframe data is valid
Forced high, indicating subframe data is
invalid
V
This bit affects the validity flag, (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain
connection during error or mute conditions. Note that the VCFG bit (0x3A Dꢀ4) will force the validity flag high (valid) or low
(invalid). See the VCFG bit description.
(Validity)
V
State
0
Each SPDIF subframe (L+R) has Bit 28 set to ꢀ
This tags both samples as invalid
Default
ꢀ
Each SPDIF subframe (L+R) has Bit 28 set to 0 for valid data and ꢀ for invalid data (error condition)
Default: 0
x
Reserved.
Rev. 0 | Page 36 of 56
AD1986A
EQ CONTROL REGISTER (REGISTER 0x60)
Register 0x60 is a read/write register that controls equalizer function and data setup. The register also contains the biquad and coefficient
address pointer, which is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default
disables the equalizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal
coefficients for left and right channels.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7
D6
D5
D4
D3
D2
D1
D0
Default
0x60 EQ
Control
EQM SYM CHS BCA5 BCA4 BCA3 BCA2 BCAꢀ BCA0 0x8080
x
x
x
x
x
x
x
Table 99. Biquad and Coefficient Address Pointer
BCA [5,0]
Biquad 0
Biquad 0
Biquad 0
Biquad 0
Biquad 0
Coef a0
Coef aꢀ
Coef a2
Coef bꢀ
Coef b2
BCA [5,0] = 0ꢀꢀ0ꢀꢀ
BCA [5,0] = 0ꢀꢀ0ꢀ0
BCA [5,0] = 0ꢀꢀ00ꢀ
BCA [5,0] = 0ꢀꢀꢀ0ꢀ
BCA [5,0] = 0ꢀꢀꢀ00
Biquad 3
Biquad 3
Coef bꢀ
Coef b2
BCA [5,0] = ꢀ0ꢀꢀ00
BCA [5,0] = ꢀ0ꢀ0ꢀꢀ
Biquad 4
Biquad 4
Biquad 4
Biquad 4
Biquad 4
Coef a0
Coef aꢀ
Coef a2
Coef bꢀ
Coef b2
BCA [5,0] = ꢀ0ꢀꢀꢀꢀ
BCA [5,0] = ꢀ0ꢀꢀꢀ0
BCA [5,0] = ꢀ0ꢀꢀ0ꢀ
BCA [5,0] = ꢀꢀ000ꢀ
BCA [5,0] = ꢀꢀ0000
Biquad ꢀ
Biquad ꢀ
Biquad ꢀ
Biquad ꢀ
Biquad ꢀ
Coef a0
Coef aꢀ
Coef a2
Coef bꢀ
Coef b2
BCA [5,0] = ꢀ00000
BCA [5,0] = 0ꢀꢀꢀꢀꢀ
BCA [5,0] = 0ꢀꢀꢀꢀ0
BCA [5,0] = ꢀ000ꢀ0
BCA [5,0] = ꢀ0000ꢀ
Biquad 5
Biquad 5
Biquad 5
Biquad 5
Biquad 5
Coef a0
Coef aꢀ
Coef a2
Coef bꢀ
Coef b2
BCA [5,0] = ꢀꢀ0ꢀ00
BCA [5,0] = ꢀꢀ00ꢀꢀ
BCA [5,0] = ꢀꢀ00ꢀ0
BCA [5,0] = ꢀꢀ0ꢀꢀ0
BCA [5,0] = ꢀꢀ0ꢀ0ꢀ
Biquad 2
Biquad 2
Biquad 2
Biquad 2
Biquad 2
Coef a0
Coef aꢀ
Coef a2
Coef bꢀ
Coef b2
BCA [5,0] = ꢀ00ꢀ0ꢀ
BCA [5,0] = ꢀ00ꢀ00
BCA [5,0] = ꢀ000ꢀꢀ
BCA [5,0] = ꢀ00ꢀꢀꢀ
BCA [5,0] = ꢀ00ꢀꢀ0
Biquad 6
Biquad 6
Biquad 6
Biquad 6
Biquad 6
Coef a0
Coef aꢀ
Coef a2
Coef bꢀ
Coef b2
BCA [5,0] = ꢀꢀꢀ00ꢀ
BCA [5,0] = ꢀꢀꢀ000
BCA [5,0] = ꢀꢀ0ꢀꢀꢀ
BCA [5,0] = ꢀꢀꢀ0ꢀꢀ
BCA [5,0] = ꢀꢀꢀ0ꢀ0
Biquad 3
Biquad 3
Biquad 3
Coef a0
Coef aꢀ
Coef a2
BCA [5,0] = ꢀ0ꢀ0ꢀ0
BCA [5,0] = ꢀ0ꢀ00ꢀ
BCA [5,0] = ꢀ0ꢀ000
Table 100.
Register
Function
CHS
Swaps the blocks that are used for symmetry coefficients. Only valid when the SYM bit is set.
(Channel
Select)
CHS
Function
Default
0
ꢀ
Selects left channel coefficients’ data block
Selects right channel coefficients’ data block
Default
SYM
When set to ꢀ this bit indicates that the left and right channel coefficients are equal.
(Symmetry)
This shortens the coefficients setup sequence since only the left channel coefficients need to be addressed and set up. The
right channel coefficients are simultaneously copied into memory.
SYM
Function
0
ꢀ
Left and right channels can use different coefficients
Indicates that the left and right channel coefficients are equal
Default
EQM
(Equalizer
Mute)
When set to ꢀ, this bit disables the equalizer function (allows all data to pass through). The reset default sets this bit to ꢀ,
disabling the equalizer function until the biquad coefficients can be properly set.
EQM
Function
0
EQ is enabled.
ꢀ
EQ is disabled. Data will pass-through without change.
Default
x
Reserved.
Default: 0
Rev. 0 | Page 37 of 56
AD1986A
EQ DATA REGISTER (REGISTER 0x62)
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the
address pointed by the BCA bits in the EQ CNTRL register (0x60). Data will only be written to memory, if the EQM bit (Register 0x60
Bit 15) is asserted.
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x62
EQ
Data
CFDꢀ5
CFDꢀ4
CFDꢀ3
CFDꢀ2
CFDꢀꢀ
CFDꢀ0
CFD9
CFD8
CFD7
CFD6
CFD5
CFD4
CFD3
CFD2
CFDꢀ
CFD0
0xxxxx
Table 101.
Register
Function
The biquad coefficients are fixed point format values with ꢀ6 bits of resolution. The CFDꢀ5 bit is the MSB and the CFD0 bit is
CFD [ꢀ5:0]
(Coefficient the LSB.
Data)
MISC CONTROL BITS 2 (REGISTER 0x70)
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x70
Misc Control
Bits 2
x
x
x
MVREF
2
MVREF
ꢀ
MVREF
0
x
x
MMDIS
x
JSMAP
CVREF
2
CVREF
ꢀ
CVREF
0
x
x
0x0000
Table 102.
Register
Function
CVREF [2:0]
(C/LFE VREF_OUT
Control)
Sets the voltage/state of the C/LFE VREF_OUT signal. VREF_OUT is used to power microphone style devices
plugged into the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right
channels through external resistors to function properly. Selections other than those defined are invalid and
should not be programmed.
C/LFE VREF_OUT Setting
CVREF [2:0]
000
5.0 AVDD
Hi-Z
Default
Default
00ꢀ
0ꢀ0
2.25 V
0 V
ꢀ00
3.70 V
JSMAP
(Jack Sense Mapping)
The ADꢀ986A supports two different methods of mapping the JACK_SENSE_A/B resistor tree to bits JS [7:0]. Use
these bits to change from the default mapping to the alternate method.
JSMAP
Function
0
ꢀ
Default jack sense mapping
Alternate jack sense mapping
Default
MMDIS
(Mono Mute Disable)
Disables the automatic muting of the MONO_OUT pin by jack sense events (see advanced jack sense bits JS [3:0]
(0x76 D [05:04], 0x72 D [05:04]).
MMDIS
Function
0
ꢀ
Automute can occur
Automute disabled
Default
MVREF [2:0]
(MIC VREF_OUT)
Sets the voltage/state of the microphone VREF_OUT signal. VREF_OUT is used to power microphone-style devices
plugged into the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right
channels through external resistors to function properly. Selections other than those defined are invalid and
should not be programmed.
MIC_1/2 VREF_OUT Setting
MVREF [2:0]
000
5.0 AVDD
Hi-Z
Default
00ꢀ
0ꢀ0
2.25 V
0 V
ꢀ00
3.70 V
x
Reserved.
Default: 0
Rev. 0 | Page 38 of 56
AD1986A
JACK SENSE (REGISTER 0x72)
All register bits are read/write except for JS0ST and JS1ST, which are read only. Important: Refer to Table 103 to understand how
JACK_SENSE_A and JACK_SENSE_B codec pins translate to JS1and JS0.
Reg Name D15
0x72 Jack
JSꢀ
D14
D13
D12
D11
D10
D9
D8
D7 D6 D5
JSꢀ JS0 JSꢀ JS0 JSꢀ JS0 0x0000
MD MD ST ST INT INT
D4
D3 D2 D1 D0 Default
JSꢀ
JS0
JSMT JSMT JSMT JSꢀ
2
JS0
x
x
Sense SPRD DMX DMX
ꢀ
0
EQB EQB
Table 103.
Register
Function
JS0INT
(JS0
Indicates JS0 has generated an interrupt. Remains set until the software services JS0 interrupt; that is, JS0 ISR should clear
this bit by writing a 0 to it.
Interrupt
Status)
Interrupts are generated by valid state changes of JS pins.
Interrupt to the system is actually an OR combination of this bit and JS3 JS0 INT.
The interrupt implementation path is selected by the INTS bit (Register 0x74).
It is also possible to generate a software system interrupt by writing a ꢀ to this bit.
JS0INT
Read
Write
0
ꢀ
JS0 did not generate interrupt
JS0 generated interrupt
No operation
Clears JS0INT bit
JSꢀINT
(JSꢀ
Indicates JSꢀ has generated an interrupt. Remains set until the software services JSꢀ interrupt; that is, JSꢀ ISR should clear
this bit by writing a 0 to it. See the JS0INT description above for additional details.
Interrupt
Status)
JS1INT
Read
Write
0
ꢀ
JSꢀ did not generate interrupt
JSꢀ generated interrupt
No operation
Clears JSꢀINT
JS0ST (RO)
(JS0 State)
This bit always reports the logic state of JS0.
On MIC jack sensing, depending on the applications circuit, the logic state for jack sense pins can be the opposite to that on
other jacks. Software needs to be aware that this interprets the JS event as a plug in the out event.
JS0ST
Function
Default
0
ꢀ
JS0 is low (0)
JS0 is high (ꢀ)
JSꢀST (RO)
(JSꢀ State)
This bit always reports the logic state of JSꢀ. MIC jack sensing, depending on the applications circuit, the logic state for JS
pins can be the opposite to the other jacks.
JS1ST
Function
0
ꢀ
JSꢀ is low (0)
JS is high (ꢀ)
JS0MD
This bit selects the operation mode for JS0.
(JS0 Mode)
JS0MD
Function
0
ꢀ
Jack sense mode—JS0INT must be polled by software
Interrupt mode—codec will generate an interrupt on JS0 event
Default
Default
JSꢀMD
(JSꢀ Mode)
This bit selects the operation mode for JSꢀ.
JS1MD
Function
0
ꢀ
Jack sense mode—JSꢀINT must be polled by software
Interrupt mode—codec will generate an interrupt on JSꢀ event
JS0EQB
(JS0 EQ
Bypass
Enable)
This bit enables JS0 to control the EQ bypass. When this bit is set to ꢀ, JS0 = ꢀ will cause the EQ to be bypassed.
JS0EQB
Function
0
ꢀ
JS0 does not affect EQ
JS0 = ꢀ will cause the EQ to be bypassed
Default
JSꢀEQB
(JSꢀ EQ
Bypass
Enable)
This bit enables JSꢀ to control the EQ bypass. When this bit is set to ꢀ, JSꢀ=ꢀ will cause the EQ to be bypassed.
JS1EQB
Function
0
ꢀ
JSꢀ does not affect EQ
JSꢀ = ꢀ will cause the EQ to be bypassed
Default
Rev. 0 | Page 39 of 56
AD1986A
Register
Function
JSMT [2,0]
(JS Mute
Enable
These three bits select and enable the jack sense muting action. See Table ꢀ04.
selector)
JS0DMX
This bit enables JS0 to control the down-mix function. This function allows a digital mix of 6-channel audio into 2-channel
audio. The mix can then be routed to the stereo LINE_OUT or HP_OUT jacks. When this bit is set to ꢀ, JS0 = ꢀ will activate the
down-mix conversion. See the DMIX description in Register 0x76. The DMIX bits select the down-mix implementation type
and can also force the function to be activated.
(JS0 Down-
Mix Control
Enable)
JS0DMX
Function
0
ꢀ
JS0 does not affect down mix
JS0 = ꢀ activates the 6- to 2-channel down mix
Default
JSꢀDMX
This bit enables JSꢀ to control the down-mix function (see the JS0DMx description above). When this bit is set to ꢀ, JSꢀ = ꢀ
will activate the down-mix conversion.
(JSꢀ Down-
Mix Control
Enable)
JS1DMX
Function
0
ꢀ
JSꢀ does not affect down-mix
JSꢀ = ꢀ activates the 6- to 2-channel down-mix
Default
JSSPRD
(JS Spread
control
This bit enables the 2-channel to 6-channel audio spread function when JSs are active (Logic State ꢀ). Note that the SPRD bit
can also force the Spread function without being gated by the jack senses. Please see this bit’s description in Register 0x76
for a better understanding of the Spread function.
enable)
JSSPRD
Function
0
ꢀ
JSꢀ does not affect spread
Jꢀ0 = ꢀ activates spread
Default
x
Reserved.
Default: 0
Table 104. Jack Sense Mute Selections (JSMT)
HP
OUT
LINE
OUT
C/LFE
OUT
SURR
OUT
MONO
OUT
REF JS1
JS0
JSMT2
JSMT1
JSMT0
NOTES
0
ꢀ
2
3
4
5
OUT (0)
OUT (0)
IN (ꢀ)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
JS0 and JSꢀ ignored
OUT (0)
IN (ꢀ)
OUT (0)
IN (ꢀ)
IN (ꢀ)
OUT (0)
OUT (0)
OUT (0)
IN (ꢀ)
JS0 no mute action
JSꢀ mutes mono and enables
LINE_OUT + SURR_OUT +
C/LFE
6
7
8
IN (ꢀ)
OUT (0)
IN (ꢀ)
0
0
0
0
0
ꢀ
ꢀ
ꢀ
0
ACTIVE
ACTIVE
FMUTE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
ACTIVE
ACTIVE
FMUTE
FMUTE
FMUTE
ACTIVE
IN (ꢀ)
STANDARD 6 CHAN CONFIG
OUT (0)
OUT (0)
JS0 no mute action, SWAPPED
HP_OUT and LINE_OUT
9
OUT (0)
IN (ꢀ)
0
ꢀ
0
FMUTE
ACTIVE
FMUTE
FMUTE
ACTIVE
JSꢀ mutes mono and enables
HP_OUT + SURR_OUT + C/LFE
ꢀ0
ꢀꢀ
IN (ꢀ)
IN (ꢀ)
OUT (0)
IN (ꢀ)
0
0
ꢀ
ꢀ
0
0
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
Standard six Channel
Configuration no swap
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
OUT (0)
OUT (0)
IN (ꢀ)
OUT (0)
IN (ꢀ)
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
0
**
**
**
**
**
**Reserved
**
**
**
**
**
OUT (0)
IN (ꢀ)
**
**
**
**
**
IN (ꢀ)
**
**
**
**
**
OUT (0)
OUT (0)
ACTIVE
FMUTE
FMUTE
FMUTE
ACTIVE
JS0 = 0 and JSꢀ = 0
enables MONO
ꢀ7
ꢀ8
ꢀ9
OUT (0)
IN (ꢀ)
IN (ꢀ)
ꢀ
ꢀ
ꢀ
0
0
0
0
0
0
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
ACTIVE
FMUTE
FMUTE
ACTIVE
FMUTE
FMUTE
FMUTE
FMUTE
FMUTE
JSꢀ = ꢀ enabled
FRONT only
OUT (0)
IN (ꢀ)
JS0 = ꢀ and JSꢀ = 0
enables all rear
IN (ꢀ)
6 CHAN CONFIG with front
jack wrap back
Rev. 0 | Page 40 of 56
AD1986A
HP
OUT
LINE
OUT
C/LFE
OUT
SURR
OUT
MONO
OUT
REF JS1
JS0
JSMT2
JSMT1
JSMT0
NOTES
20
2ꢀ
OUT (0)
OUT (0)
IN (ꢀ)
ꢀ
ꢀ
0
0
ꢀ
ꢀ
FMUTE
FMUTE
FMUTE
FMUTE
FMUTE
FMUTE
FMUTE
FMUTE
ACTIVE
ACTIVE
JS0 no mute action
OUT (0)
JSꢀ mutes mono and enables
all rear.
22
23
IN (ꢀ)
IN (ꢀ)
OUT (0)
IN (ꢀ)
ꢀ
ꢀ
0
0
ꢀ
ꢀ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FMUTE
FMUTE
Standard six channel
configuration swapped
HP_OUT and LINE_OUT
24
25
26
27
28
29
30
3ꢀ
OUT (0)
OUT (0)
IN (ꢀ)
OUT (0)
IN (ꢀ)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**RESERVED
OUT (0)
IN (ꢀ)
IN (ꢀ)
OUT (0)
OUT (0)
IN (ꢀ)
OUT (0)
IN (ꢀ)
**RESERVED
OUT (0)
IN (ꢀ)
IN (ꢀ)
FMUTE = Output is forced to mute independent of the respective volume register setting.
ACTIVE = Output is not muted and its status is dependent on the respective volume register setting.
OUT = Nothing is plugged into the jack and therefore the JS status is 0 (via the load resistor pull-down action).
IN = Jack has plug inserted and therefore the JS status is 1 (via the codec JS pin internal pull-up).
SERIAL CONFIGURATION (REGISTER 0x74)
When Register 0x00 is written (soft reset) the SLOT 16, REGM [2:0], SPOVR, SPAL, SPDZ, and SPLNK bits do not reset. All bits are reset
on a hardware reset or power-on reset.
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x74
Serial
Configuration
SLOT
ꢀ6
REGM2
REGMꢀ
REGM0
REGM3
OMS2
OMSꢀ
OM0
SPOVR
LBKSꢀ
LBKS0
INTS
CSWP
SPAL
SPDZ
SP
LNK
0xꢀ00ꢀ
Table 105.
Register
Function
Default
SPLNK
(S/PDIF
LINK)
This bit enables S/PDIF to link with the front DACs for data requesting. When linked, the S/PDIF and front DACs should be set
to the same data rate because they both generate data requests at the front DACs request rate.
SPLNK
Function
0
ꢀ
S/PDIF and front DACs are not linked
S/PDIF and front DACs are linked
Default
SPDZ
(S/PDIF
DACZ)
Sets data fill mode for S/PDIF transmitter FIFO under-runs. When this bit is set to on (ꢀ), the S/PDIF and ADC rates should be
set to the same rate.
SPDZ
On Under-Runs
0
ꢀ
Repeat last sample out the S/PDIF stream
Forces midscale sample out the S/PDIF stream
S/PDIF Transmitter Source
Default
Default
SPAL
SPAL
(S/PDIF
ADC Loop
Around)
0
ꢀ
Connected to the AC-LINK stream
Connected to the digital ADC stream
(CSWP
Center/LFE
Swap)
Swaps the center/LFE channels. Some systems have a swapped external connection for the center and LFE channels. Setting
this bit will swap these channels internal to the codec. The center and LFE controls do not change and remain at the same
addresses and bit assignments.
CSWP
CENTER Pin
Center channel
LFE channel
LFE Pin
0
ꢀ
LFE channel
Center channel
Default
Rev. 0 | Page 4ꢀ of 56
AD1986A
Register
Function
Default
INTS
(Interrupt
Mode
This bit selects the audio interrupt implementation path. Note that this bit does not generate an interrupt, rather it steers the
path of the generated interrupt.
INTS
Interrupt Mode
Select)
0
ꢀ
Bit 0 Slot ꢀ2 (modem interrupt)
Slot 6 valid bit (MIC ADC interrupt)
Default
Default
LBKS [ꢀ:0]
Loop-Back
Selection
These bits select the internal digital loop-back path when LPBK bit is active (see Register 0x20).
LBKS [1:0]
Interrupt Mode
00
0ꢀ
ꢀ0
Loop back through the front DACs
Loop back through the surround DACs
Loop back through the center and LFE DACs (center
DAC loops back from the ADC left channel, the LFE
DAC from the ADC right channel)
ꢀꢀ
Reserved
SPOVR
Use this bit to enable S/PDIF operation even if the external S/PDIF detection resistor is not installed.
(S/PDIF
Enable
Override)
SPOVR
S/PDIF Detection
0
External resistor determines the presence of
S/PDIF
Default
ꢀ
Enable S/PDIF operation
OMS [2:0]
Optional
Selects the source of the microphone gain boost amplifiers. These bits work in conjuction with the 2CMIC (0x76, D06),
MS (0x20 D08), and MMIX (0x7A D08) bits.
Microphone
Selector
OMS [2:0]
000
Left Channel
MIC pins
Default
00ꢀ
LINE_IN pins
0ꢀx
C/LFE pins
ꢀ00
ꢀ0ꢀ
ꢀꢀ0
ꢀꢀꢀ
Mix of MIC and C/LFE pins
Mix of MIC and LINE_IN pins
Mix of LINE_IN and C/LFE pins
Mix of MIC, LINE_IN and C/LFE pins
REGM [3:0]
Bit mask indicating which codec is being accessed in a chained codec configuration.
REGM0—Master codec register mask
Default
REGMꢀ—Slave ꢀ codec register mask
REGM2—Slave 2 codec register mask
REGM3—Slave 3 codec register mask
SLOT ꢀ6
Enable ꢀ6-bit slot mode: SLOTꢀ6 makes all AC link slots ꢀ6 bits in length, formatted into ꢀ6 slots. This is a preferred mode for
DSP serial port interfacing.
SLOT 16
Function
0
ꢀ
Standard AC ’97 operation
All ac link S slots are ꢀ6 bits
Default
x
Reserved
Default: 0
Rev. 0 | Page 42 of 56
AD1986A
MISC CONTROL BITS 1 (REGISTER 0x76)
Reg Name
D15
D14
D13
D12
D11
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x76 Misc
Control
DACZ AC97NC MSPLT SODIS CLDIS
x DMIXꢀ DMIX0 SPRD 2CMIC SOSEL SRU LISELꢀ LISEL0 MBGꢀ MBG0 60ꢀ0
Bits ꢀ
Table 106.
Register
Function
MBG [ꢀ:0]
(MIC Boost Gain Select
Register)
These two bits allow changing both MIC preamp gain blocks from the nominal 20 dB gain boost. Both MIC_ꢀ/2
and MIC_2 preamps will be set to the same selected gain. This gain setting takes affect only while Bit D6 (M20)
on the MIC volume register (0x0E) is set to ꢀ, otherwise the MIC boost blocks have a gain of 0 dB.
MGB [1:0]
Microphone Boost Gain
Default
00
0ꢀ
ꢀ0
ꢀꢀ
20 dB
ꢀ0 dB
30 dB
Reserved
Default
LISEL [ꢀ:0]
Selects the source of the internal LINE_IN signals.
(LINE_IN Selector)
LISEL [1:0]
LINE_IN Selection
00
0ꢀ
ꢀx
LINE_IN pins
Default
SURROUND pins—Places surround outputs in Hi-Z state
MIC_ꢀ/2 pins
SRU
Controls all DAC sample rate locking.
(Sample Rate Unlock)
SRU
0
Surround State
All DAC sample rates are locked to the front sample rate
ꢀ
Front, surround, and LFE sample rates can be set independently Default
SOSEL
Selects either the surround DAC or analog mixer as the source driving the SURROUND output pin amplifier.
(Surround Amplifier
Input Selection)
SOSEL
Surround Source
Surround DACs
Analog Mixer
0
ꢀ
Default
2CMIC
(2-Channel MIC Select)
Used in conjunction with the OMS [2:0] (0x74 Dꢀ0:08]), MS (0x20 D08), and MMIX (0x7A D02) bits to set the
microphone selection. This bit enables simultaneous recording from MIC_ꢀ and MIC_2 inputs, using a stereo
microphone array. If the MMIX (0x7A D02) bit is set, this bit is ignored.
2CMIC
2 Channel MIC State
0
ꢀ
Both outputs are driven by the left channel of the selector
Stereo operation, the left and right channels are driven
separately
Default
SPRD
(Spread Enable)
This bit enables spreading of 2-channel media to all 6-output channels. This function is implemented in the
analog section by using the output selector control lines for the center/LFE, surround, and LINE_OUT output
channels. The jack sense pins can also be set up to control (gate) this function, depending on the JSSPRD bit
(see Register 0x72). The SPRD bit operates independently and does not affect the LOSEL and HPSEL operation.
SPRD
Spread State
0
ꢀ
No spreading occurs unless activated by jack sense
The SPDR selector drives the center and LFE outputs from the
MONO_OUT
Default
CLDIS
(C/LFE Output Enable)
Controls the Hi-Z state of the SURROUND_L/R output pins. Pins are placed into a Hi-Z mode by software control
or when they are selected as inputs to the MIC_ꢀ/2 selector (see the OMS [2:0] Bits 740x D [ꢀ0:08]).
CLDIS
C/LFE Output State
Outputs enabled
Outputs tristated
0
ꢀ
Default
Rev. 0 | Page 43 of 56
AD1986A
Register
Function
DMIX [ꢀ:0]
(DOWN MIX Mode
Select)
Provides analog down-mixing of the center, LFE, and/or surround channels into the mixer channels. This allows
the full content of 5.ꢀ or quad media to be played through stereo headphones or speakers. The jack sense pins
can also be set up to control (gate) this function depending on the JS0DMx and JSꢀDMx Bits (0x72 D [ꢀ4:ꢀ3]).
DMIX [1:0]
Down-Mix State
Default
0x
ꢀ0
No down-mix unless activated by jack sense
Selects 6-to-4 down mix. The center and LFE channels are
summed equally into the Mixer L/R channels
Default
ꢀꢀ
Selects 6-to-2 down mix. In addition to the center and LFE
channels, the SURROUND channels are summed into the
mixer L/R channels
SODIS
(Surround Output
Enable)
Controls the Hi-Z state of the SURROUND output pins. Pins are placed into a Hi-Z mode by software control or
when they are selected as inputs to the LINE_IN selector (see the LISEL [ꢀ:0] bits 0x76 D [03:02]).
CLDIS
SURROUND_OUT State
Outputs enabled
Outputs three-stated (Hi-Z)
0
ꢀ
Default
MSPLT (RO)
(Mute Split)
Separates the left and right mutes on all volume registers. This bit is read-only ꢀ (one) on the ADꢀ986A,
indicating that mute split is always enabled.
AC ‘97NC (RO)
Changes addressing to ADI model (vs. true AC ’97 definition). This bit is read-only ꢀ (one) on the ADꢀ986A,
(AC ‘97 No Compatibility indicating that ADI addressing is always enabled.
Mode)
DACZ
Determines DAC data fill under starved condition.
(DAC Zero-Fill)
DACZ
DAC Fill State
0
ꢀ
DAC data is repeated when DACs are starved for data
DAC data is zero-filled when DACs are starved for data
Default
x
Reserved.
Default: 0
Rev. 0 | Page 44 of 56
AD1986A
ADVANCED JACK SENSE (REGISTER 0x78)
All register bits are read/write except for JSxST bits, which are read only. Important: Refer to Table 116 to understand how
JACK_SENSE_A and JACK_SENSE_B codec pins translate to JS7…JS2.
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8 D7
D6 D5
JS3 JS2 JS3 JS2 JS3 JS2 0xxxxx
MD MD ST ST INT INT
D4
D3 D2 D1
D0
Default
0x78 Advanced
Jack Sense
JS7
ST
JS7
INT
JS6
ST
JS6
INT
JS5
ST
JS5
INT
JS4 JS4 JS4-
ST INT 7H
x
Table 107.
Register
Function
JS [7:2] INT
Indicates that JSx has generated an interrupt. Remains set until the software services JSx interrupt; that is, JSx ISR should
clear this bit by writing a 0 to it.
Interrupts are generated by valid state changes of JSx.
Interrupt to the system is actually an OR combination of this bit and JS7 JS0 INT.
Interrupt implementation path is selected by the INTS bit (Register 0x74).
It is also possible to generate a software system interrupt by writing a ꢀ to this bit.
JS [7:4] INT
Read
Write
Default
0
ꢀ
JSx logic is not interrupted
Sx logic interrupted
Clears JSx interrupt
Generates a software interrupt
Default
JS [7:4] ST (RO) This bit always reports the logic state of JS7 through JS4 detection logic.
JS [7:4] ST
Jack State
0
ꢀ
No jack present
Jack detected
JS [3:2] MD
This bit selects the operation mode for JS2 and JS3.
JS [3:2] MD
Interrupt Mode
0
ꢀ
Jack Sense Mode—jack sense state requires software polling
Interrupt Mode—jack sense events will generate interrupts
Default
JS [4–7]
Interrupt
Mode Select
This bit selects the audio interrupt implementation path (for JS4 to 7). This bit does not generate an interrupt, rather it
steers the path of the generated interrupt.
JS4 to 7
Interrupt Mode—JS4 to 7
0
Bit 0 Slot ꢀ2 (modem interrupt)
Slot 6 valid bit (MIC ADC interrupt)
Default
ꢀ
x
Reserved
Default: 0
MISC CONTROL BITS 3 (REGISTER 0x7A)
Reg Name
D15
D14
D13
D12
D11
D10
D9
D8
D7 D6 D5 D4
D3
D2
D1 D0 Default
0x7A Misc Control
Bits 3
JSINVB HPSELꢀ HPSEL0 LOSEL JSINVA LVREF 2 LVREFꢀ LVREF 0
x
x
x
LOHPEN GPO MMIX
x
x
0x0000
Table 108.
Register
MMIX
Function
Used in conjunction with the OMS [2:0] (0x74 Dꢀ0:08), MS (0x20 D08), and 2CMIC (0x76 D06) bits to mix the microphone
selector left/right channels. If the MMIX bit is set, the 2CMIC and MS bits are ignored.
MMIX
Function
Default
0
Microphone
channels are not
mixed
Default
ꢀ
The left/right channels from the microphone selector are mixed
Sets the state of the GPO pin
GPO
GPO
Function
0
GPO pin is at logic Default
low (DVSS)
ꢀ
GPO pin is at logic
high (DVDD)
Rev. 0 | Page 45 of 56
AD1986A
Register
Function
LOHPEN
Enables the headphone drive on the LINE_OUT pins. Disabling the headphone drive is the same as powering it down (see
the PR6 bit (0x26 Dꢀ4)).
LOHPEN
Function
0
LINE_OUT
Default
headphone drive
is disabled
ꢀ
LINE_OUT
headphone drive
is enabled
LVREF [2:0]
(Line In
VREF_OUT)
Sets the voltage/state of the LINE_IN VREF_OUT signal. VREF_OUT is used to power microphone style devices plugged into
the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right channels through external
resistors to function properly. Selections other than those defined are invalid and should not be programmed.
LINE_IN VREF_OUT Setting
LVREF
[2:0]
000
00ꢀ
0ꢀ0
ꢀ00
5.0 AVDD
Hi-Z
2.25 V
0V
Default
3.70 V
LOSEL
This bit allows the LINE_OUT output amplifiers to be driven by the mixer or the surround DACs. The main purpose for this is
to allow swapping of the front and surround channels to make better use of the SURR/HP_OUT output amplifiers. This bit
should normally be used in tandem with the HPSEL bit (following in table).
(LINE_OUT
Amplifiers
Input Select)
LOSEL
LINE_OUT Select
0
LINE_OUT
Default
amplifiers are
driven by the
analog mixer
outputs
ꢀ
LINE_OUT
amplifiers are
driven by the
surround DAC
JSINVA
SENSE_A: Select the style of switch used on the audio jacks connected to Sense A.
Jack Sense
Invert
JSINVA
Jack Sense Invert—SENSE_A
0
SENSE_A
Default
configured for
normally-open
(NO) switches
ꢀ
SENSE_A
configured for
normally-closed
(NC) switches
HPSEL [ꢀ:0]
(Headphone
Amplifier
This bit allows the headphone power amps to be driven from the surround DACs, C/LFE DACs, or from the mixer outputs.
HPSEL
[1:0]
HP_OUT Selection
Input Select)
00
Outputs are
driven by the
mixer outputs
Default
0ꢀ
ꢀx
Outputs are
driven by the
surround DACs
Outputs are
driven by the
C/LFE DACs
Rev. 0 | Page 46 of 56
AD1986A
Register
Function
JSINVB
SENSE_B: Select the style of switch used on the audio jacks connected to Sense B.
(Jack Sense
Invert)
JSINVB
Jack Sense Invert—SENSE_B
0
JACK_SENSE_B
configured for
normally-open
(NO) switches
Default
ꢀ
JACK_SENSE_B
configured for
normally-closed
(NC) switches
x
Reserved.
Default: 0
VENDOR ID REGISTERS (REGISTER 0x7C to 0x7E)
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7
D6
D5
D4
D3
D2
D1
D0
Default
0x7C Vendor
ID ꢀ
F7
F6
F5
F4
F3
F2
Fꢀ
F0
S7
S6
S5
S4
S3
S2
Sꢀ
S0
0x4ꢀ44
0x7E Vendor
ID 2
T7
T6
T5
T4
T3
T2
Tꢀ
T0
REV7
REV6
REV5
REV4
REV3
REV2
REVꢀ
REV0
0x5378
Table 109.
Register
S [7:0]
F [7:0]
T [7:0]
Function
This register is ASCII encoded to A.
This register is ASCII encoded to D.
This register is ASCII encoded to S.
REV [7:0]
This register is set to 0x78, identifying the ADꢀ986A.
CODEC CLASS/REVISION REGISTER (REGISTER 0x60)
Reg
0x60ꢀ Codec
Class/Rev
Name
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
x
x
x
CL4 CL3 CL2 CLꢀ CL0 RV7 RV6 RV5 RV4 RV3 RV2 RVꢀ RV0 0x0002
Table 110.
Register
Function
Default
RV [7:0]
(Revision ID:
(RO))
These bits specify a device specific revision identifier. The vendor chooses this value. Zero is an acceptable
value. This field should be viewed as a vendor defined extension to the codec ID. This number changes
with new codec stepping of the same codec ID. This number will increment with each stepping/rev. of the
codec chip.
CL [4:0]
(Codec
The ADꢀ986A will return 0x00 from this register. This is a codec vendor specific field to define software
compatibility for the codec. Software reads this field together with codec vendor ID (Register 0x7C–0x7E)
Compatibility to determine vendor-specific programming interface compatibility. Software can rely on vendor specific
Class (RO))
register behavior to be compatible among vendor codecs of the same class.
0x00
Field not implemented
0x0ꢀ-0xꢀF
Reserved.
Vendor-specific compatibility class code
x
Default: 0
Rev. 0 | Page 47 of 56
AD1986A
PCI SUBSYSTEM VENDOR ID REGISTER (REGISTER 0x62, PAGE 01)
This register is only reset by power-on. It is used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specification)
and must not be reset by soft or hardware resets.
Reg
0x62ꢀ PCI
SVID
Name D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
PVIꢀ5 PVIꢀ4 PVIꢀ3 PVIꢀ2 PVIꢀꢀ PVIꢀ0 PVI9 PVI8 PVI7 PVI6 PVI5 PVI4 PVI3 PVI2 PVIꢀ PVI0 0xFFFF
Table 111.
Register
Function
PVI [ꢀ5:0]
PCI Sub
System
Optional per AC ‘97 specifications, should be implemented as read/write on ADꢀ986A.
This field provides the PCI subsystem vendor ID of the audio or modem subassembly vendor (that is, CNR manufacturer,
motherboard vendor). This is not the codec vendor PCI vendor ID or the AC ’97 controller PCI vendor ID. If data is not
available it returns 0xFFFF.
Vendor ID
PCI SUBSYSTEM DEVICE ID REGISTER (REGISTER 0x64, PAGE 01)
This register is only reset by power-on. It is used by the BIOS to store configuration information (per AC’97 v2.3 specification) and must
not be reset by soft or hardware resets.
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
0x64ꢀ PCI SID
PIꢀ5 PIꢀ4 PIꢀ3 PIꢀ2 PIꢀꢀ PIꢀ0 PI9 PI8 PI7 PI6 PI5 PI4 PI3 PI2 PIꢀ PI0 0xFFFF
Table 112.
Register
Function
PI [ꢀ5:0]
(PCI Vendor
ID)
Optional per AC ‘97 specifications, should be implemented as read/write on the ADꢀ986A. This field provides the PCI
subsystem ID of the audio or modem subassembly (that is, CNR model, motherboard SKU). This is not the codec vendor PCI
ID or the AC ’97 controller PCI ID. Information in this field must be available, because the AC ’97 controller reads when the
codec ready is asserted in the AC link. If data is not available, it should return 0xFFFF.
Rev. 0 | Page 48 of 56
AD1986A
FUNCTION SELECT REGISTER (REGISTER 0x66, PAGE 01)
This register is used to select which function (analog I/O pins), information and I/O (0x6801), and sense (0x6A01) registers apply to it.
The AD1986A associates FC = 0x0 with surround functions and FC = 0x01 with front functions. These are changed in the AD1986A to
align with the device pinout and to separate LINE_OUT functions.
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1
D0 Default
0x66ꢀ Function
Select
x
x
x
x
x
x
x
x
x
x
x
FC3 FC2 FCꢀ FC0 T/R 0x0000
Table 113.
Register
Function
T/R
(FIP or Ring
Selection Bit)
This bit sets which jack conductor the sense value is measured from. Software will program the corresponding rng/tp
selector bit together with the I/O number in bits FC [3:0]. Once software programs the value and properly reads it back to
confirm selection and implementation, it will access the rest of the bits fields in the descriptor. Mono inputs and outputs
should report the relevant function and sense information when T/R is set to 0 (tip). The FIP bit should report 0 (Page
0x0ꢀ, Register 0x68, Bit 0 reports no function information present) when T/R is set to a ꢀ on a mono input or output.
T/R
0
ꢀ
Function
Tip (left channel)
Ring (right channel)
Default
FC [3:0]
Function Code
Bits
These bits specify the type of audio function described by this page. These bits are read/write and represent current
AC ’97 Revision 2.2 defined I/O capabilities. Software will program the corresponding I/O number in this field together
with the tip/ring selector bit T/R. Once software programs the value and properly reads it back to confirm selection and
implementation, it will access the rest of the bits fields in the descriptor.
FC [3:0]
0x0
Function
Default
DAC ꢀ (master out). maps to front DACs (L/R)
Default
0xꢀ
DAC 2 (AUX out). maps to surround DACs (L/R)
0x2
DAC 3 (C/LFE). maps to C/LFE DACs
0x3
0x4
S/P-DIF out
Phone in
0x5
0x6
0x7
MIC_ꢀ (Mic select = 0)
MIC_2 (Mic select = ꢀ)
Line in
0x8
CD in
0x9
Video in
Not supported on the
ADꢀ986A
0xA
Aux in
0xB
0xC
0xD–0xF
Reserved.
Mono out
Headphone ut
Reserved
x
Default: 0
Rev. 0 | Page 49 of 56
AD1986A
INFORMATION AND I/O REGISTER (REGISTER 0x68, PAGE 01)
This address represents multiple registers (one for each supported function code (FC [3:0] bits (0x66 D [04:01])). These values are only
reset by power-on. It is used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specifications) and must not be reset
by soft or hardware resets.
Reg
Name
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4 D3 D2 D1 D0 Default
FIP 0xxxxx
0x68ꢀ Information G4
and I/O
G3
G2
Gꢀ
G0
INV
DL4 DL3 DL2 DLꢀ DL0 IV
x
x
x
Table 114.
Register
Function
codec default. When set to a ꢀ, this bit indicates that the G [4:0], INV, DL [4:0] (in Register 0x68ꢀ), and ST [2:0] (in
FIP (RO)
(Function
Information
Present)
Register 0x6Aꢀ) bits are supported and are read/write capable. This bit set to a 0 indicates that the G [4:0], INV, DL [4:0], and
ST [2:0] bits are not supported, and are read-only with a value of 0. Mono inputs and outputs report the relevant function
and sense information when T/R is set to 0 (tip). The FIP bit reports a 0 (Page 0x0ꢀ, Register 0x68, Bit 0 reports no function
information present) when T/R is set to a ꢀ on a mono input or output.
FIP
0
ꢀ
Function
Function information not supported
Function information supported
Power-on default
IV
Indicates whether a sensing method is provided by the codec and if information field is valid. This field is updated by the
(Information codec.
Valid Bit)
IV
Function
0
After codec reset de-assertion, it indicates the codec does not provide sensing logic and this bit will be read-
only. A completed sense cycle indicates that no information is provided on the sensing method.
ꢀ
After codec reset de-assertion, it indicates the codec provides sensing logic for this I/O and this bit is
read/write. After clearing this bit by writing ꢀ, when a sense cycle is completed indicates that there is valid
information in the remaining descriptor bits. Writing 0 to this bit has no effect.
DL [4:0]
(Buffer
Delays,
A number representing a delay measurement for the input and output channels. The default value is the delay internal to
the codec. The BIOS can add to this value the known delays external to the codec, such as for an external amplifier or logic.
Software will use this value to accurately calculate audio stream position with respect to what is been reproduced or
recorded. These values are in 20.83 microsecond (ꢀ/48000 second) units. For output channels, this timing is from the end of
AC link frame in which the sample is provided, until the time the analog signal appears at the output pin. For input streams,
this is from when the analog signal is presented at the pin until the representative sample is provided on the AC link. Analog
to analog paths are not considered in this measurement. The measurement is a typical measurement, at a 48 kHz sample
rate, with minimal in-codec processing (that is, 3D effects are turned off.) An example of an audio output delay is filter group
delay and FIFO or other sample buffers in the path. When an audio PCM sample is written to the codec in an AC ’97 frame it
will be delayed before the output pin is updated to that value.
Read/Write)
DL [4:0]
0x00
0x0ꢀ-0xꢀE
0xꢀF
Function
Information not provided
Buffer delay: 20.83 µs per unit
Reserved
INV
(Inversion
Bit,
Read/Write,
Codec
Default)
Indicates that the codec presents a ꢀ80° phase shift to the signal. This bit is only reset by a power-on reset, since it is typically
written by the system BIOS and is not reset by codec hard or soft resets as long as power remains applied to the codec.
INV
0
Function
No phase shift
ꢀ
Signal is shifted by ꢀ80° from the source signal
Rev. 0 | Page 50 of 56
AD1986A
Register
Function
G [4:0]
(Gain Bits
The codec updates these bits with the gain value (dB relative to level-out) in ꢀ.5 dBV increments, not including the volume
control gains. For example, if the volume gain is to 0 dB, then the output pin should be at the 0 dB level. Any difference in
(Read/Write)) the gain is reflected here. When relevant, the BIOS updates this bit to take into consideration external amplifiers or other
external logic that it knows about. G [3:0] indicates the magnitude of the gain. G [4] indicates whether the value is a gain or
attenuation—essentially it is a sign bit. These bits are only reset by a power-on reset because they are typically written by
the system BIOS and are not reset by codec hard or soft resets as long as power remains applied to the codec.
G4
G [3:0]
0000
000ꢀ
...
ꢀꢀꢀꢀ
000ꢀ
...
Gain/Attenuation (dB Relative to Level-Out)
0
0 dB
+ꢀ.5 dB
+ꢀ.5 dB × G [3:0]
+24.0 dB
0
−ꢀ.5 dB
−ꢀ.5 dB × G [3:0]
−24.0 dB
ꢀ
x
ꢀꢀꢀꢀ
Reserved
Default: 0
SENSE REGISTER (REGISTER 0x6A, PAGE 01)
This address represents multiple registers (one for each supported function code (FC [3:0] bits (0x66 D [04:01])). The ST [2:0] bits are
only reset by power-on. They are used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specifications) and must
not be reset by soft, hard, or hardware resets. The remaining bits are the result of the last sense operation performed by the impedance
sensing circuitry.
Reg
0x6Aꢀ Sense
Register
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7
D6
D5 D4 D3 D2 D1 D0 Default
ST2
STꢀ
ST0
S4
S3
S2
Sꢀ S0 ORꢀ OR0 SR5 SR4 SR3 SR2 SRꢀ SR0 0xxxxx
Table 115.
Register
Function
Default
SR [5:0] (RO)
(Sense Result
Bits, RO)
These bits are used to report a vendor specific fingerprint or value (resistance, impedance, or
reactance). Used with the OR bits which are the multiplying factor.
Default: 0
OR [ꢀ:0] (RO)
(Order Bits)
These bits indicate the order the sense result bits SR [5:0] are using. For example, if measuring resistance SR = ꢀ/OR =
ꢀꢀ: the result is ꢀ kΩ.
OR [1:0]
Order Value
00
0ꢀ
ꢀ0
ꢀꢀ
ꢀ00—SR bits indicate the actual impedance in ohms
ꢀ0ꢀ—SSR bits indicate the impedance in ohms × ꢀ0
ꢀ02—SR bits indicate the impedance in ohms × ꢀ00
ꢀ03—SSR bits indicate the impedance in ohms × ꢀ,000
Default
S [4:0] (RO)
Sensed bits meaning relates to the I/O being sensed as input or output. Read-only. Sensed bits (when output sense
cycle initiated). This field allows for the reporting of the type of output peripheral/device plugged in the jack. Values
specified below should be interrogated with the SR [5:0] and OR [ꢀ:0] for accurate reporting.
S [4:0]
0x00
0x0ꢀ
0x02
Sense Value
Data not valid. Indicates that the reported value(s) is invalid
No connection. Indicates that there are no connected devices
Indicates a specific fingerprint value for devices that are not specified or are
unknown
Default
0x03
0x04
0x05
0x06
0x07
0x08
Speakers (8 Ω)
Speakers (4 Ω)
Powered speakers
Stereo headphone
SPDIF out (electrical)
SPDIF out (TOS)
Rev. 0 | Page 5ꢀ of 56
AD1986A
Register
Function
Default
0x09
Mono headset (mono speaker left channel and mic. Read Functions 5 and 6 for
matching microphone)
0x0A
Allows a vendor to report sensing other type of devices/peripherals. SR [5:0]
together with OR [ꢀ:0] provide information regarding the type of device sensed
0x0B–0x0E
0x0F
0xꢀ0–0xꢀF
Reserved
Unknown (use fingerprint)
Reserved
S [4:0] (RO)
Sensed bits (when input sense cycle initiated). This field allows for the reporting of the type of input peripheral/device
plugged in the jack. Specified values should be interrogated with the SR [5:0] and OR [ꢀ:0] bits for accurate reporting.
ST [2:0]
0xꢀ0
0xꢀꢀ
Sense Value
Data not valid. Indicates that the reported value(s) is invalid
No connection. Indicates that there are no connected devices
Default
0xꢀ2
Indicates a specific fingerprint value for devices that are not specified or are
unknown
0xꢀ3
0xꢀ4
0xꢀ5
0xꢀ6
0xꢀ7
0xꢀ8
0xꢀ9
Microphone (mono)
Microphone (stereo)
Stereo line in (CE device attached)
Mono line in (CE device attached)
SPDIF In (electrical)
SPDIF In (TOS)
Headset (mono speaker left channel and mic.) Read Functions 0 to 3 for matching
DAC out
0xꢀA
Allows a vendor to report sensing other types of devices/peripherals. SR [5:0]
together with OR [ꢀ:0] provide information regarding the type of device sensed
0xꢀB–0xꢀE
0xꢀF
Reserved
Unknown (use fingerprint)
ST [2:0]
This field describes the location of the jack in the system. This field is updated by the BIOS. These bits are only reset by a
power-on reset because it is typically written by the system BIOS and is not reset by codec hard or soft resets as long as
power remains applied to the codec.
(Connector/Jack
location Bits,
Read/Write)
ST [2:0]
Jack Location
0x0
Rear I/O panel
Power-on
default
0xꢀ
Front panel
0x2
Motherboard
0x3
0x4–0x6
0x7
Dock/external
Reserved
No connection/unused I/O
Rev. 0 | Page 52 of 56
AD1986A
JACK PRESENCE DETECTION
sense style for SENSE_B is controlled by the JSINVB bit
The AD1986A uses two jack sense lines for presence detection
on up to eight external jacks. These lines, combined with the
device detection circuitry, enable software to determine whether
there is a device plugged into the circuit and what type of device
it is. With this feature, software can reconfigure jacks and
amplifiers as necessary to ensure proper audio operation.
(Register 0x7A Bit D15). Writing a 1 to these bits will configure
the corresponding sense circuit for normally closed instead of
normally open switch types.
Wrap-back jacks cannot be used in microphone-capable cir-
cuits. For this reason isolated switches are recommended. The
codec defaults to sensing No style switches and this method is
preferred.
Jack presence is detected using a resistor tree arrangement. Up
to four jacks can be sensed on a single sense line by using a
different value resistance for each jack between the sense line
and ground (AVSS). Each sense line must have a single 2.49 kΩ
1% resistor connected between the sense line and AVDD. The
specific resistor values for each jack are shown in Table 116.
One percent tolerance resistors should be used for all jack
presence circuitry to ensure accurate detection.
Normally-Open Switches
If a connection is not present, do not install the sense resistor
pertaining to that connection.
If a connection is present, but there is no related switch (such as
an internal connection), install the sense resistor pertaining to
that connection.
AUDIO JACK STYLES (NC/NO)
Normally Closed Switches
The jack sense lines on the AD1986A can be programmed for
use with normally-open (NO) or normally closed (NC) switch
types. Current standard stereo audio jacks have wrap-back pins
that are normally closed. New audio jacks use isolated, normally
open switches, which are required for resistive ladder jack
presence detection. Each sense group (A or B) must have the
same style of jack for presence detection to function correctly.
However, the group (A or B) sense type can be programmed
separately to accommodate systems with different styles of jacks
on the front versus rear panel.
Connections capable of MIC bias require isolated switches to
function correctly. When using normally closed, wrap-back
switches, the jack resistor must be split into two values. One
value connects the sense line to the jack switch and the other
connects the related audio connection to AVSS. The total
resistance (sense line to AVSS) must equal the value specified in
Table 116.
If a connection is not present, install the sense resistors
pertaining to that connection.
The AD1986A defaults to the isolated, normally open switch
types on power-up. The jack sense style for SENSE_A is
controlled by the JSINVA bit (Register 0x7A Bit D11). The jack
If a connection is present, but there is no related switch (such as
an internal connection), do not install the sense resistors
pertaining to that connection.
Table 116. Jack Sense Mapping
JACK_SENSE_A
JACK_SENSE_B
Resister (1% tolerance)
4.99 kΩ
ꢀ0.0 kΩ
20.0 kΩ
40.2 kΩ
Mnemonic
Jack
D
JS
Mnemonic
LINE OUT
C/LFE
Jack
JS
JS7
JS4
JS5
JSꢀ
H
G
F
JS0
JS3
JS2
JS6
LINE IN
C
MIC_ꢀ/2
HP_OUT
B
SURROUND
AUX IN
A
E
Rev. 0 | Page 53 of 56
AD1986A
MICROPHONE SELECTION/MIXING
MIC 1
CENTER
LINE IN L
NID: 0x0F
MIC Select: OMS[2:0]
0x74 D10-D08
DEF=000 (MIC 1/2)
G
MIC LEFT
000-MIC 1/2
001-Line In
01x-C/LFE
100-MIC+C/LFE
101-MIC+Line In
110-C/LFE+Line In
111-MIC+C/LFE+Line
NID: 0x11
MIC Boost: AC97
M20 0x0E D6 DEF=0
MGB[1:0] 0x76 D[1:0] DEF=00
MIC Swap: AC97
MS 0x20 D08 DEF=0
2CMIC 0x76 D06 DEF=0
MMIX 0x7A D02 DEF=0
MGB
M20
0
[1:0]
xx
Gain
0dB
1
1
1
1
00
01
10
11
+20dB
+10dB
+30dB
reserved
Azalia
MSWP[2:0] 0x7A D02:00
MMIX 2CMIC MS
MSWP2 MSWP1 MSWP0 Right
NID: 0x2B
Azalia
MGBL[1:0] 0x70 D[1:0]
MGBR[1:0} 0x70 D[14:13]
MIC 2
LFE
Left
MIC
MIC
MIC
MIC
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
MIC
MIC
MIC
MIC
1
2
2
1
1
2
1
2
MGBL/R
[1:0]
00
Gain
0dB
MIC 1+2 MIC 1+2
LINE IN R
01
10
11
+10dB
+20dB
+30dB
MIC RIGHT
NID: 0x27
NID: 0x28
NID: 0x29
G
NID: 0x2A
Figure 3. Microphone Selection/Mixing Block Diagram
Rev. 0 | Page 54 of 56
AD1986A
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00
BSC SQ
1.60
MAX
37
48
36
1
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 4. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.30
7.00
BSC SQ
0.23
0.18
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
PAD
(BOTTOM VIEW)
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 5. 48-Lead Lead Frame Chip Scale Package {LFCSP_VQ}
7 × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
0°C to 70°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Package Description
48-Lead LQFP, Tray
48-Lead LQFP, Reel
48-Lead LQFP, Tray
48-Lead LQFP, Reel
48-Lead LFCSP_VQ, Tray
48-Lead LFCSP_VQ, Reel
48-Lead LFCSP_VQ, Tray
48-Lead LFCSP_VQ, Reel
Package Option
ADꢀ986AJSTZꢀ
ADꢀ986AJSTZ-REELꢀ
ADꢀ986ABSTZꢀ
ADꢀ986ABSTZ-REELꢀ
ADꢀ986AJCP
ADꢀ986AJCP-RL
ADꢀ986AJCPZꢀ
ADꢀ986AJCPZ-RLꢀ
ST-48
ST-48
ST-48
ST-48
CP-48-ꢀ
CP-48-ꢀ
CP-48-ꢀ
CP-48-ꢀ
ꢀ Z = Pb-free part.
Rev. 0 | Page 55 of 56
AD1986A
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05496–0-–4/05(0)
Rev. 0 | Page 56 of 56
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